ADDR
P20
P21
P22
P23
P24
P25
P26
P27
RESET
P00
P01
P02
P03
P04
P05
P06
P07
VCCI
GND
INT
VCCP
SDA
P17
P16
P15
P14
P13
P10
P11
P12
SCL
1
2
3
4
5
6
7
8
25
26
27
29
28
30
31
32
16
15
14
13
9
10
11
12
18
17
24
23
22
21
20
19
Exposed
Center Pad
TCA6424A
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SCPS193B –JULY 2010–REVISED SEPTEMBER 2010
LOW-VOLTAGE 24-BIT I
2
C AND SMBus I/O EXPANDER
WITH INTERRUPT OUTPUT, RESET, AND CONFIGURATION REGISTERS
Check for Samples: TCA6424A
1FEATURES
• Operating Power-Supply Voltage Range of • Polarity Inversion Register
1.65 V to 5.5 V • Internal Power-On Reset
• Allows Bidirectional Voltage-Level Translation • Power Up With All Channels Configured as
and GPIO Expansion Between: Inputs
– 1.8-V SCL/SDA and • No Glitch On Power Up
1.8-V, 2.5-V, 3.3-V, or 5-V P Port • Noise Filter on SCL/SDA Inputs
– 2.5-V SCL/SDA and • Latched Outputs With High-Current Drive
1.8-V, 2.5-V, 3.3-V, or 5-V P Port Maximum Capability for Directly Driving LEDs
– 3.3-V SCL/SDA and • Latch-Up Performance Exceeds 100 mA Per
1.8-V, 2.5-V, 3.3-V, or 5-V P Port JESD 78, Class II
– 5-V SCL/SDA and • ESD Protection Exceeds JESD 22
1.8-V, 2.5-V, 3.3-V, or 5-V P Port – 2000-V Human-Body Model (A114-A)
• I2C to Parallel Port Expander – 200-V Machine Model (A115-A)
• Low Standby Current Consumption of 1 mA– 1000-V Charged-Device Model (C101)
• Schmitt-Trigger Action Allows Slow Input
Transition and Better Switching Noise RGJ/RSM PACKAGE
(BOTTOM VIEW)
Immunity at the SCL and SDA Inputs
– Vhys = 0.18 V Typ at 1.8 V
– Vhys = 0.25 V Typ at 2.5 V
– Vhys = 0.33 V Typ at 3.3 V
– Vhys = 0.5 V Typ at 5 V
• 5-V Tolerant I/O Ports
• Active-Low Reset Input (RESET)
• Open-Drain Active-Low Interrupt Output (INT)
• 400-kHz Fast I2C Bus
• Input/Output Configuration Register
If used, the exposed center pad must be
connected as a secondary ground or left
electrically open.
DESCRIPTION/ORDERING INFORMATION
This 24-bit I/O expander for the two-line bidirectional bus (I2C) is designed to provide general-purpose remote I/O
expansion for most microcontroller families via the I2C interface [serial clock (SCL) and serial data (SDA)].
The major benefit of this device is its wide VCC range. It can operate from 1.65 V to 5.5 V on the P-port side and
on the SDA/SCL side. This allows the TCA6424A to interface with next-generation microprocessors and
microcontrollers on the SDA/SCL side, where supply levels are dropping down to conserve power. In contrast to
the dropping power supplies of microprocessors and microcontrollers, some PCB components, such as LEDs,
remain at a 5-V power supply.
1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date. Copyright © 2010, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
TCA6424A
SCPS193B –JULY 2010–REVISED SEPTEMBER 2010
www.ti.com
DESCRIPTION/ORDERING INFORMATION (CONTINUED)
The bidirectional voltage level translation in the TCA6424A is provided through VCCI. VCCI should be connected to
the VCC of the external SCL/SDA lines. This indicates the VCC level of the I2C bus to the TCA6424A. The voltage
level on the P-port of the TCA6424A is determined by the VCCP.
The TCA6424A consists of three 8-bit Configuration (input or output selection), Input, Output, and Polarity
Inversion (active high) registers. At power on, the I/Os are configured as inputs. However, the system master can
enable the I/Os as either inputs or outputs by writing to the I/O configuration bits. The data for each input or
output is kept in the corresponding input or output register. The polarity of the Input Port register can be inverted
with the Polarity Inversion register. All registers can be read by the system master.
The system master can reset the TCA6424A in the event of a timeout or other improper operation by asserting a
low in the RESET input. The power-on reset puts the registers in their default state and initializes the I2C/SMBus
state machine. The RESET pin causes the same reset/initialization to occur without depowering the part.
The TCA6424A open-drain interrupt (INT) output is activated when any input state differs from its corresponding
Input Port register state and is used to indicate to the system master that an input state has changed.
INT can be connected to the interrupt input of a microcontroller. By sending an interrupt signal on this line, the
remote I/O can inform the microcontroller if there is incoming data on its ports without having to communicate via
the I2C bus. Thus, the TCA6424A can remain a simple slave device.
The device P-port outputs have high-current sink capabilities for directly driving LEDs while consuming low
device current.
One hardware pin (ADDR) can be used to program and vary the fixed I2C address and allow up to two devices to
share the same I2C bus or SMBus.
ORDERING INFORMATION
TAPACKAGE(1) (2) ORDERABLE PART NUMBER TOP-SIDE MARKING
QFN – RGJ Reel of 3000 TCA6424ARGJR PH424
–40°C to 85°C QFN – RSM TBD TCA6424ARSMR TBD
(1) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
(2) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
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Table 1. TERMINAL FUNCTIONS
TERMINAL DESCRIPTION
PIN NO. NAME
1 P00 P-port input/output (push-pull design structure). At power on, P00 is configured as an input.
2 P01 P-port input/output (push-pull design structure). At power on, P01 is configured as an input.
3 P02 P-port input/output (push-pull design structure). At power on, P02 is configured as an input.
4 P03 P-port input/output (push-pull design structure). At power on, P03 is configured as an input.
5 P04 P-port input/output (push-pull design structure). At power on, P04 is configured as an input.
6 P05 P-port input/output (push-pull design structure). At power on, P05 is configured as an input.
7 P06 P-port input/output (push-pull design structure). At power on, P06 is configured as an input.
8 P07 P-port input/output (push-pull design structure). At power on, P07 is configured as an input.
9 P10 P-port input/output (push-pull design structure). At power on, P10 is configured as an input.
10 P11 P-port input/output (push-pull design structure). At power on, P11 is configured as an input.
11 P12 P-port input/output (push-pull design structure). At power on, P12 is configured as an input.
12 P13 P-port input/output (push-pull design structure). At power on, P13 is configured as an input.
13 P14 P-port input/output (push-pull design structure). At power on, P14 is configured as an input.
14 P15 P-port input/output (push-pull design structure). At power on, P15 is configured as an input.
15 P16 P-port input/output (push-pull design structure). At power on, P16 is configured as an input.
16 P17 P-port input/output (push-pull design structure). At power on, P17 is configured as an input.
17 P20 P-port input/output (push-pull design structure). At power on, P20 is configured as an input.
18 P21 P-port input/output (push-pull design structure). At power on, P21 is configured as an input.
19 P22 P-port input/output (push-pull design structure). At power on, P22 is configured as an input.
20 P23 P-port input/output (push-pull design structure). At power on, P23 is configured as an input.
21 P24 P-port input/output (push-pull design structure). At power on, P24 is configured as an input.
22 P25 P-port input/output (push-pull design structure). At power on, P25 is configured as an input.
23 P26 P-port input/output (push-pull design structure). At power on, P26 is configured as an input.
24 P27 P-port input/output (push-pull design structure). At power on, P27 is configured as an input.
25 GND Ground
26 ADDR Address input. Connect directly to VCCP or ground.
27 VCCP Supply voltage of TCA6424A for P port
28 RESET Active-low reset input. Connect to VCCI through a pullup resistor, if no active connection is used.
29 SCL Serial clock bus. Connect to VCCI through a pullup resistor.
30 SDA Serial data bus. Connect to VCCI through a pullup resistor.
Supply voltage of I2C bus. Connect directly to the VCC of the external I2C master. Provides voltage-level
31 VCCI translation.
32 INT Interrupt output. Connect to VCCI through a pullup resistor.
Voltage Translation
Table 2 shows how to set up VCC levels for the necessary voltage translation between the I2C bus and the
TCA6424A.
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29
I/O Port
Shift
Register 24 Bits
Input
Filter
30
Power-On
Reset
Read Pulse
Write Pulse
26
27
25
GND
VCCP
SDA
SCL
ADDR
I C Bus
Control
2
RESET 28
INT Interrupt
Logic
LP Filter
32
VCCI
31
P27
P17–P10
P07–P00
–P20
TCA6424A
SCPS193B –JULY 2010–REVISED SEPTEMBER 2010
www.ti.com
Table 2. Voltage Translation
VCCI (SDA AND SCL OF I2C MASTER) VCCP (P PORT)
(V) (V)
1.8 1.8
1.8 2.5
1.8 3.3
1.8 5
2.5 1.8
2.5 2.5
2.5 3.3
2.5 5
3.3 1.8
3.3 2.5
3.3 3.3
3.3 5
5 1.8
5 2.5
5 3.3
5 5
LOGIC DIAGRAM (POSITIVE LOGIC)
A. All I/Os are set to inputs at reset.
B. Pin numbers shown are for the RGJ package.
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Data From
Shift Register
Write Configuration
Pulse
Write Pulse
Read Pulse
Write Polarity Pulse
Polarity
Inversion
Register
Input
Port
Register
Output
Port
Register
Configuration
Register VCCP
GND
Input Port
Register Data
Polarity
Register Data
ESD Protection Diode
P00 to P27
Output Port
Register Data
To INT
Q1
Q2
D
FF
CK
Q
Q
D
FF
CK
Q
Q
D
FF
CK
Q
Q
D
FF
CK
Q
Q
Data From
Shift Register
Data From
Shift Register
TCA6424A
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SCPS193B –JULY 2010–REVISED SEPTEMBER 2010
Simplified Schematic of P00 to P27
A. On power up or reset, all registers return to default values.
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SDA
SCL S P
StartCondition StopCondition
SDA
SCL
DataLine Change
TCA6424A
SCPS193B –JULY 2010–REVISED SEPTEMBER 2010
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I/O Port
When an I/O is configured as an input, FETs Q1 and Q2 are off, which creates a high-impedance input. The
input voltage may be raised above VCC to a maximum of 5.5 V.
If the I/O is configured as an output, Q1 or Q2 is enabled, depending on the state of the output port register. In
this case, there are low-impedance paths between the I/O pin and either VCC or GND. The external voltage
applied to this I/O pin should not exceed the recommended levels for proper operation.
I2C Interface
The bidirectional I2C bus consists of the serial clock (SCL) and serial data (SDA) lines. Both lines must be
connected to a positive supply through a pullup resistor when connected to the output stages of a device. Data
transfer may be initiated only when the bus is not busy.
I2C communication with this device is initiated by a master sending a Start condition, a high-to-low transition on
the SDA input/output, while the SCL input is high (see Figure 1). After the Start condition, the device address
byte is sent, most significant bit (MSB) first, including the data direction bit (R/W).
After receiving the valid address byte, this device responds with an acknowledge (ACK), a low on the SDA
input/output during the high of the ACK-related clock pulse. The address (ADDR) input of the slave device must
not be changed between the Start and the Stop conditions.
On the I2C bus, only one data bit is transferred during each clock pulse. The data on the SDA line must remain
stable during the high pulse of the clock period, as changes in the data line at this time are interpreted as control
commands (Start or Stop) (see Figure 2).
A Stop condition, a low-to-high transition on the SDA input/output while the SCL input is high, is sent by the
master (see Figure 1).
Any number of data bytes can be transferred from the transmitter to receiver between the Start and the Stop
conditions. Each byte of eight bits is followed by one ACK bit. The transmitter must release the SDA line before
the receiver can send an ACK bit. The device that acknowledges must pull down the SDA line during the ACK
clock pulse, so that the SDA line is stable low during the high pulse of the ACK-related clock period (see
Figure 3). When a slave receiver is addressed, it must generate an ACK after each byte is received. Similarly,
the master must generate an ACK after each byte that it receives from the slave transmitter. Setup and hold
times must be met to ensure proper operation.
A master receiver signals an end of data to the slave transmitter by not generating an acknowledge (NACK) after
the last byte has been clocked out of the slave. This is done by the master receiver by holding the SDA line high.
In this event, the transmitter must release the data line to enable the master to generate a Stop condition.
Figure 1. Definition of Start and Stop Conditions
Figure 2. Bit Transfer
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S
1 2 8 9
NACK
ACK
DataOutput
byTransmitter
DataOutput
byReceiver
SCL From
Master
Start
Condition
ClockPulsefor
Acknowledgment
0
Slave Address
10 0 0 1 AD
DR R/W
Fixed Programmable
TCA6424A
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SCPS193B –JULY 2010–REVISED SEPTEMBER 2010
Figure 3. Acknowledgment on the I2C Bus
Table 3. Interface Definition
BIT
BYTE 7 (MSB) 6 5 4 3 2 1 0 (LSB)
I2C slave address L H L L L H ADDR R/W
P07 P06 P05 P04 P03 P02 P01 P00
I/O data bus P17 P16 P15 P14 P13 P12 P11 P10
P27 P26 P25 P24 P23 P22 P21 P20
Device Address
The address of the TCA6424A is shown in Figure 4.
Figure 4. TCA6424A Address
Table 4. Address Reference
ADDR I2C BUS SLAVE ADDRESS
L 34 (decimal), 22 (hexadecimal)
H 35 (decimal), 23 (hexadecimal)
The last bit of the slave address defines the operation (read or write) to be performed. A high (1) selects a read
operation, while a low (0) selects a write operation.
Control Register and Command Byte
Following the successful acknowledgment of the address byte, the bus master sends a command byte, which is
stored in the control register in the TCA6424A. Four bits of this data byte state the operation (read or write) and
the internal registers (input, output, polarity inversion, or configuration) that will be affected. The control register
can be written or read through the I2C bus. The command byte is sent only during a write transmission.
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B2 B1 B0B5 B4 B3
AI B6
TCA6424A
SCPS193B –JULY 2010–REVISED SEPTEMBER 2010
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The control register includes an Auto-Increment (AI) bit which is the most significant bit (bit 7) of the command
byte. At power-up, the control register defaults to 00 (hex), with the AI bit set to logic 1, and the lowest 7 bits set
to logic 0.
If AI is 1, the 2 least significant bits are automatically incremented after a read or write. This allows the user to
program and/or read the 3 register banks sequentially. If more than 3 bytes of data are written when AI is 1,
previous data in the selected registers will be overwritten. Reserved registers are skipped and not accessed
(refer to Table 5).
If AI is 0, the 2 least significant bits are not incremented after data is read or written. During a read operation, the
same register bank is read each time. During a write operation, data is written to the same register bank each
time.
Reserved command codes and command byte outside the range stated in the Command Byte table must not be
accessed for proper device functionality.
Figure 5. Control Register Bits
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Table 5. Command Byte
CONTROL REGISTER BITS AUTO- COMMAND POWER-UP
INCREMENT BYTE REGISTER PROTOCOL DEFAULT
AI B6 B5 B4 B3 B2 B1 B0 STATE (HEX)
0 0 0 0 0 0 0 0 Disable 00 Input Port 0 Read byte xxxx xxxx(1)
1 0 0 0 0 0 0 0 Enable 80
0 0 0 0 0 0 0 1 Disable 01 Input Port 1 Read byte xxxx xxxx(1)
1 0 0 0 0 0 0 1 Enable 81
0 0 0 0 0 0 1 0 Disable 02 Input Port 2 Read byte xxxx xxxx(1)
1 0 0 0 0 0 1 0 Enable 82
0 0 0 0 0 0 1 1 Disable 03 Reserved Reserved Reserved
1 0 0 0 0 0 1 1 Enable 83
0 0 0 0 0 1 0 0 Disable 04 Read/write
Output Port 0 1111 1111
byte
1 0 0 0 0 1 0 0 Enable 84
0 0 0 0 0 1 0 1 Disable 05 Read/write
Output Port 1 1111 1111
byte
1 0 0 0 0 1 0 1 Enable 85
0 0 0 0 0 1 1 0 Disable 06 Read/write
Output Port 2 1111 1111
byte
1 0 0 0 0 1 1 0 Enable 86
0 0 0 0 0 1 1 1 Disable 07 Reserved Reserved Reserved
1 0 0 0 0 1 1 1 Enable 87
0 0 0 0 1 0 0 0 Disable 08 Polarity Inversion Read/write 0000 0000
Port 0 byte
1 0 0 0 1 0 0 0 Enable 88
0 0 0 0 1 0 0 1 Disable 09 Polarity Inversion Read/write 0000 0000
Port 1 byte
1 0 0 0 1 0 0 1 Enable 89
0 0 0 0 1 0 1 0 Disable 0A Polarity Inversion Read/write 0000 0000
Port 2 byte
1 0 0 0 1 0 1 0 Enable 8A
0 0 0 0 1 0 1 1 Disable 0B Reserved Reserved Reserved
1 0 0 0 1 0 1 1 Enable 8B
0 0 0 0 1 1 0 0 Disable 0C Read/write
Configuration Port 0 1111 1111
byte
1 0 0 0 1 1 0 0 Enable 8C
0 0 0 0 1 1 0 1 Disable 0D Read/write
Configuration Port 1 1111 1111
byte
1 0 0 0 1 1 0 1 Enable 8D
0 0 0 0 1 1 1 0 Disable 0E Read/write
Configuration Port 2 1111 1111
byte
1 0 0 0 1 1 1 0 Enable 8E
0 0 0 0 1 1 1 1 Disable 0F Reserved Reserved Reserved
1 0 0 0 1 1 1 1 Enable 8F
(1) Undefined
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Register Descriptions
The Input Port registers (registers 0, 1 and 2) reflect the incoming logic levels of the pins, regardless of whether
the pin is defined as an input or an output by the Configuration register. They act only on read operation. Writes
to these registers have no effect. The default value (X) is determined by the externally applied logic level. Before
a read operation, a write transmission is sent with the command byte to indicate to the I2C device that the Input
Port register will be accessed next.
Table 6. Registers 0 and 1 (Input Port Registers)
BIT I-07 I-06 I-05 I-04 I-03 I-02 I-01 I-00
DEFAULT XXXXXXXX
BIT I-17 I-16 I-15 I-14 I-13 I-12 I-11 I-10
DEFAULT XXXXXXXX
BIT I-27 I-26 I-25 I-24 I-23 I-22 I-21 I-20
DEFAULT XXXXXXXX
The Output Port registers (registers 4, 5 and 6) shows the outgoing logic levels of the pins defined as outputs by
the Configuration register. Bit values in these registers have no effect on pins defined as inputs. In turn, reads
from these registers reflect the value that is in the flip-flop controlling the output selection, NOT the actual pin
value.
Table 7. Registers 2 and 3 (Output Port Registers)
BIT O-07 O-06 O-05 O-04 O-03 O-02 O-01 O-00
DEFAULT 1 1 1 1 1 1 1 1
BIT O-17 O-16 O-15 O-14 O-13 O-12 O-11 O-10
DEFAULT 1 1 1 1 1 1 1 1
BIT O-27 O-26 O-25 O-24 O-23 O-22 O-21 O-20
DEFAULT 1 1 1 1 1 1 1 1
The Polarity Inversion registers (registers 8, 9 and 10) allow polarity inversion of pins defined as inputs by the
Configuration register. If a bit in these registers is set (written with 1), the corresponding port pin's polarity is
inverted. If a bit in these registers is cleared (written with a 0), the corresponding port pin's original polarity is
retained.
Table 8. Registers 4 and 5 (Polarity Inversion Registers)
BIT P-07 P-06 P-05 P-04 P-03 P-02 P-01 P-00
DEFAULT 00000000
BIT P-17 P-16 P-15 P-14 P-13 P-12 P-11 P-10
DEFAULT 00000000
BIT P-27 P-26 P-25 P-24 P-23 P-22 P-21 P-20
DEFAULT 00000000
The Configuration registers (registers 12, 13 and 14) configure the direction of the I/O pins. If a bit in these
registers is set to 1, the corresponding port pin is enabled as an input with a high-impedance output driver. If a
bit in these registers is cleared to 0, the corresponding port pin is enabled as an output.
Table 9. Registers 6 and 7 (Configuration Registers)
BIT C-07 C-06 C-05 C-04 C-03 C-02 C-01 C-00
DEFAULT 11111111
BIT C-17 C-16 C-15 C-14 C-13 C-12 C-11 C-10
DEFAULT 11111111
BIT C-27 C-26 C-25 C-24 C-23 C-22 C-21 C-20
DEFAULT 11111111
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Power-On Reset
When power (from 0 V) is applied to VCCP, an internal power-on reset holds the TCA6424A in a reset condition
until VCCP has reached VPOR. At that time, the reset condition is released, and the TCA6424A registers and
I2C/SMBus state machine initializes to their default states. After that, VCCP must be lowered to below 0.2 V and
back up to the operating voltage for a power-reset cycle.
ADD TABLE WITH SPECS AND DEFINITIONS TO SUPPORT POR OPERATION
Reset Input (RESET)
The RESET input can be asserted to initialize the system while keeping the VCCP at its operating level. A reset
can be accomplished by holding the RESET pin low for a minimum of tW. The TCA6424A registers and
I2C/SMBus state machine are changed to their default state once RESET is low (0). When RESET is high (1),
the I/O levels at the P port can be changed externally or through the master. This input requires a pullup resistor
to VCCI, if no active connection is used.
Interrupt Output (INT)
An interrupt is generated by any rising or falling edge of the port inputs in the input mode. After time tiv, the signal
INT is valid. Resetting the interrupt circuit is achieved when data on the port is changed to the original setting or
when data is read from the port that generated the interrupt. Resetting occurs in the read mode at the
acknowledge (ACK) or not acknowledge (NACK) bit after the rising edge of the SCL signal. Interrupts that occur
during the ACK or NACK clock pulse can be lost (or be very short) due to the resetting of the interrupt during this
pulse. Each change of the I/Os after resetting is detected and is transmitted as INT.
Reading from or writing to another device does not affect the interrupt circuit, and a pin configured as an output
cannot cause an interrupt. Changing an I/O from an output to an input may cause a false interrupt to occur, if the
state of the pin does not match the contents of the Input Port register.
The INT output has an open-drain structure and requires pullup resistor to VCCP or VCCI depending on the
application. If the INT signal is connected back to the processor that provides the SCL signal to the TCA6424A
then the INT pin has to be connected to VCCI. If not, the INT pin can be connected to VCCP.
Bus Transactions
Data is exchanged between the master and TCA6424A through write and read commands.
Writes
Data is transmitted to the TCA6424A by sending the device address and setting the least-significant bit (LSB) to
a logic 0 (see Figure 4 for device address). The command byte is sent after the address and determines which
register receives the data that follows the command byte. There is no limitation on the number of data bytes sent
in one write transmission.
The twelve registers within the TCA6424A are grouped into four different sets. The four sets of registers are input
ports, output ports, polarity inversion ports and configuration ports. After sending data to one register, the next
data byte is sent to the next register in the group of 3 registers (see Figure 6 and Figure 7). For example, if the
first byte is send to Output Port 2 (register 6), the next byte is stored in Output Port 0 (register 4).
There is no limitation on the number of data bytes sent in one write transmission. In this way, each 8-bit register
may be updated independently of the other registers.
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1 2
SCL 345678
SDA A A A
Data0
Datat Registero
R/W
9
0/10 0 0 0 1 0/1 MSB LSB Data1
MSB LSB A
S010 0 0 1 AD
DR 0
1 2 345678 9 1 2 345678 9 1 2 345
P
Acknowledge
FromSlave
Acknowledge
FromSlave
StartCondition
CommandByteSlave Address
Acknowledge
FromSlave
Datat Registero
0/1
TCA6424A
SCPS193B –JULY 2010–REVISED SEPTEMBER 2010
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Figure 6. Write to Output Port Register
<br/>
Figure 7. Write to Configuration or Polarity Inversion Registers
Reads
The bus master first must send the TCA6424A address with the LSB set to a logic 0 (see Figure 4 for device
address). The command byte is sent after the address and determines which register is accessed.
After a restart, the device address is sent again but, this time, the LSB is set to a logic 1. Data from the register
defined by the command byte then is sent by the TCA6424A (see Figure 8 and Figure 9).
After a restart, the value of the register defined by the command byte matches the register being accessed when
the restart occurred. For example, if the command byte references Input Port 1 before the restart, and the restart
occurs when Input Port 0 is being read, the stored command byte changes to reference Input Port 0. The original
command byte is forgotten. If a subsequent restart occurs, Input Port 0 is read first. Data is clocked into the
register on the rising edge of the ACK clock pulse. After the first byte is read, additional bytes may be read, but
the data now reflects the information in the other register in the pair. For example, if Input Port 1 is read, the next
byte read is Input Port 0.
Data is clocked into the register on the rising edge of the ACK clock pulse. There is no limitation on the number
of data bytes received in one read transmission, but when the final byte is received, the bus master must not
acknowledge the data.
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Product Folder Link(s): TCA6424A
0 0 0 1 AD
DR
01
S0A A A
R/W
A
PNA
S1MSB LSB
MSB LSB
Slave Address
Acknowledge
FromSlave
CommandByte
DataFromUpper
orLowerByte
ofRegister
LastByte
Data
Acknowledge
FromSlave
Acknowledge
FromSlave
Slave Address
DataFromLower
orUpperByte
ofRegister
FirstByte
Data
No Acknowledge
FromMaster
Acknowledge
FromMaster
Atthismoment,mastertransmitter
slavetransmitter.
becomesmasterreceiver,and
slavereceiverbecomes
0 0 0 1 AD
DR
01
R/W
123456789
S010 0 0 1 AD
DR 1AData 1 Data 2 Data 3 Data 4
A
I0.x
A
I1.x
A
I2.x
1
I0.x
P
SCL
SDA
INT
Read From
Port 0
Data Into
Port 0
Read From
Port 1
Data Into
Port 1
Read From
Port 2
Data Into
Port 2
Acknowledge
From Master
Acknowledge
From Slave
Acknowledge
From Master
Acknowledge
From Master
No Acknowledge
From Master
tiv tir
R/W
TCA6424A
www.ti.com
SCPS193B –JULY 2010–REVISED SEPTEMBER 2010
Figure 8. Read From Register
<br/>
A. Transfer of data can be stopped at any time by a Stop condition. When this occurs, data present at the latest
acknowledge phase is valid (output mode). It is assumed that the command byte previously has been set to 00 (read
Input Port register).
B. This figure eliminates the command byte transfer, a restart, and slave address call between the initial slave address
call and actual data transfer from P port (see Figure 8).
C. Auto-increment mode is enabled.
Figure 9. Read Input Port Register
Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback 13
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SCPS193B –JULY 2010–REVISED SEPTEMBER 2010
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ABSOLUTE MAXIMUM RATINGS(1)
over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT
VCCI Supply voltage range –0.5 6.5 V
VCCP Supply voltage range –0.5 6.5 V
VIInput voltage range(2) –0.5 6.5 V
VOOutput voltage range(2) –0.5 6.5 V
IIK Input clamp current ADDR, RESET, SCL VI< 0 ±20 mA
IOK Output clamp current INT VO< 0 ±20 mA
P port VO< 0 or VO> VCCP ±20
IIOK Input/output clamp current mA
SDA VO< 0 or VO> VCCI ±20
P port VO= 0 to VCCP 25
IOL Continuous output low current mA
SDA, INT VO= 0 to VCCI 15
IOH Continuous output high current P port VO= 0 to VCCP 25 mA
Continuous current through GND 200
ICC Continuous current through VCCP 160 mA
Continuous current through VCCI 10
RGJ package 50.05
qJA Package thermal impedance(3) °C/W
RSM package TBD
Tstg Storage temperature range –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
(3) The package thermal impedance is calculated in accordance with JESD 51-7.
RECOMMENDED OPERATING CONDITIONS MIN MAX UNIT
VCCI Supply voltage 1.65 5.5 V
VCCP Supply voltage 1.65 5.5 V
SCL, SDA, RESET 0.7 × VCCI 5.5
VIH High-level input voltage V
ADDR, P27–P00 0.7 × VCCP 5.5
SCL, SDA, RESET –0.5 0.3 × VCCI
VIL Low-level input voltage V
ADDR, P27–P00 –0.5 0.3 × VCCP
IOH High-level output current P27–P00 10 mA
IOL Low-level output current P27–P00 25 mA
TAOperating free-air temperature –40 85 °C
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SCPS193B –JULY 2010–REVISED SEPTEMBER 2010
ELECTRICAL CHARACTERISTICS
over recommended operating free-air temperature range, VCCI = 1.65 V to 5.5 V (unless otherwise noted)
PARAMETER TEST CONDITIONS VCCP MIN TYP(1) MAX UNIT
Input diode clamp
VIK II= –18 mA 1.65 V to 5.5 V –1.2 V
voltage
VPOR Power-on reset voltage VI= VCCP or GND, IO= 0 1.65 V to 5.5 V 1 1.4 V
1.65 V 1.2
2.3 V 1.8
IOH = –8 mA 3 V 2.6
4.5 V 4.1
P-port high-level output
VOH V
voltage 1.65 V 1
2.3 V 1.7
IOH = –10 mA 3 V 2.5
4.5 V 4.0
1.65 V 0.45
2.3 V 0.25
IOL = 8mA 3 V 0.25
4.5 V 0.23
P-port low-level output
VOL V
voltage 1.65 V 0.6
2.3 V 0.3
IOL = 10 mA 3 V 0.25
4.5 V 0.24
SDA VOL = 0.4 V 1.65 V to 5.5 V 3
IOL mA
INT VOL = 0.4 V 1.65 V to 5.5 V 3 15
SCL, SDA, RESET VI= VCCI or GND ±0.1
II1.65 V to 5.5 V mA
ADDR VI= VCCP or GND ±0.1
IIH P port VI= VCCP 1mA
1.65 V to 5.5 V
IIL P port VI= GND 1 mA
VIon SDA and RESET= VCCI
SDA, or GND,
P port, VIon P port and ADDR = 1.65 V to 5.5 V 8 30
ADDR, VCCP,
RESET IO= 0, I/O = inputs,
fSCL = 400 kHz
Operating
mode VIon SDA and RESET= VCCI
SDA, or GND,
ICC P port, VIon P port and ADDR = 1.65 V to 5.5 V 1.7 10 mA
(ICCP + ICCI) ADDR, VCCP,
RESET IO= 0, I/O = inputs,
fSCL = 100 kHz
VIon SCL, SDA and RESET =
SCL, VCCI or GND,
SDA,
Standby VIon P port and ADDR =
P port, 1.65 V to 5.5 V 0.1 3
mode VCCP,
ADDR, IO= 0, I/O = inputs,
RESET fSCL = 0
SCL,SDA One input at VCCI – 0.6 V,
Additional
ΔICCI 25
RESET Other inputs at VCCI or GND
current in 1.65 V to 5.5 V mA
Standby P port, One input at VCCP – 0.6 V,
ΔICCP 60
mode ADDR, Other inputs at VCCP or GND
CISCL VI= VCCI or GND 1.65 V to 5.5 V 6 7 pF
SDA VIO = VCCI or GND 7 8
Cio 1.65 V to 5.5 V pF
P port VIO = VCCP or GND 7.5 8.5
(1) Except for ICC, all typical values are at nominal supply voltage (VCCP = VCCI =1.8-V, 2.5-V, 3.3-V, or 5-V VCC) and TA= 25°C. For ICC, all
typical values are at VCCP = VCCI = 3.3 V and TA= 25°C.
Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback 15
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SCPS193B –JULY 2010–REVISED SEPTEMBER 2010
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I2C INTERFACE TIMING REQUIREMENTS
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 10)
STANDARD MODE FAST MODE
I2C BUS I2C BUS UNIT
MIN MAX MIN MAX
fscl I2C clock frequency 0 100 0 400 kHz
tsch I2C clock high time 4 0.6 ms
tscl I2C clock low time 4.7 1.3 ms
tsp I2C spike time 0 50 0 50 ns
tsds I2C serial data setup time 250 100 ns
tsdh I2C serial data hold time 0 0 ns
ticr I2C input rise time 1000 20 + 0.1Cb(1) 300 ns
ticf I2C input fall time 300 20 + 0.1Cb(1) 300 ns
tocf I2C output fall time; 10 pF to 400 pF bus 300 20 + 0.1Cb(1) 300 ms
tbuf I2C bus free time between Stop and Start 4.7 1.3 ms
tsts I2C Start or repeater Start condition setup time 4.7 0.6 ms
tsth I2C Start or repeater Start condition hold time 4 0.6 ms
tsps I2C Stop condition setup time 4 0.6 ms
tvd(data) Valid data time; SCL low to SDA output valid 1 1 ms
Valid data time of ACK condition; ACK signal from SCL low to SDA
tvd(ack) 1 1 ms
(out) low
(1) Cb= total capacitance of one bus line in pF
RESET TIMING REQUIREMENTS
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 13)
STANDARD MODE FAST MODE
I2C BUS I2C BUS UNIT
MIN MAX MIN MAX
tWReset pulse duration 4 4 ns
tREC Reset recovery time 0 0 ns
tRESET Time to reset(1) 600 600 ns
(1) Minimum time for SDA to become high or minimum time to wait before doing a START.
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SCPS193B –JULY 2010–REVISED SEPTEMBER 2010
SWITCHING CHARACTERISTICS
over recommended operating free-air temperature range, CL≤100 pF (unless otherwise noted) (see Figure 10)
STANDARD MODE FAST MODE
I2C BUS I2C BUS
PARAMETER FROM TO UNIT
MIN MAX MIN MAX
tIV Interrupt valid time P port INT 4 4 ms
tIR Interrupt reset delay time SCL INT 4 4 ms
tPV Output data valid SCL P27–P00 400 400 ns
tPS Input data setup time P port SCL 0 0 ns
tPH Input data hold time P port SCL 300 300 ns
Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback 17
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Temperature, °C)T (
A
Supply Current, µA)I (
CC
8535 6010–15
1
2
3
4
5
6
7
8
9
0
–40
SCL = VCC
All I/Os unloaded
V = 1.8 V
CC
V = 2.5 V
CC
V = 3.3 V
CC
V = 5 V
CC
8535 6010-15-40
10
20
30
40
50
60
70
80
90
100
0
f = 400 kHz
SCL
All I/Os unloaded
VCC = 3.3 V
VCC = 2.5 V
V = 1.8 V
CC
V = 5 V
CC
Temperature, °C)T (
A
Supply Current, µA)I (
CC
Supply Current, I (µA)
CC
5.0
4.5
3.5 4.0
3.02.5
10
20
30
40
50
60
70
80
90
100
0
Supply Voltage, V (V)
CC
2.0 5.5
1.65
f = 400 kHz
SCL
All I/Os unloaded
0.50.40.30.20.1
5
10
15
20
25
30
35
40
45
50
0
00.6
SinkCurrent, mA)I (
SINK
OutputLowVoltage, V)V (
OL
T = 40°C
A–
T =25°C
A
T =85°C
A
V =3.3V
CC
0.6
0.40.30.20.1
2
4
6
8
10
12
14
16
18
20
0
0
V =1.8V
CC T = 40°C
A–
0.5
SinkCurrent, (mA)ISINK
OutputLowVoltage, V)V (
OL
T =25°C
A
T =85°C
A
0.50.40.30.20.1
2
4
6
8
10
12
14
16
18
20
22
24
0
00.6
SinkCurrent, mA)I (
SINK
OutputLowVoltage, V)V (
OL
T = 40°C
A–
T =25°C
A
T =85°C
A
V =2.5V
CC
0.40.30.20.1
5
10
15
20
25
30
35
40
45
50
0
00.5
V =5V
CC
SinkCurrent, (mA)ISINK
OutputLowVoltage, V (V)
OL
T = 85°C
A
T =25°C
A
T = 40°C
A–
8535 6010−15−40
50
100
150
200
250
300
350
400
0
V =1.8V,I =10mA
CC SINK
OutputLowVoltage, mV)V (
OL
Temperature, °C)T (
A
V =5V,I =10mA
CC SINK
V =5V,I =1mA
CC SINK
V =1.8V,I =1mA
CC SINK
0.60.50.40.30.20.1
4
8
12
16
20
0
00.7
SourceCurrent, mA)I (
SOURCE
T = 40°C
A–
T =25°C
A
T =85°C
A
V =1.8V
CC
V V (V)
CC OH
–
TCA6424A
SCPS193B –JULY 2010–REVISED SEPTEMBER 2010
www.ti.com
TYPICAL CHARACTERISTICS
TA= 25°C (unless otherwise noted)
SUPPLY CURRENT STANDBY SUPPLY CURRENT SUPPLY CURRENT
vs vs vs
TEMPERATURE TEMPERATURE SUPPLY VOLTAGE
I/O SINK CURRENT I/O SINK CURRENT I/O SINK CURRENT
vs vs vs
OUTPUT LOW VOLTAGE OUTPUT LOW VOLTAGE OUTPUT LOW VOLTAGE
I/O SINK CURRENT I/O LOW VOLTAGE I/O SOURCE CURRENT
vs vs vs
OUTPUT LOW VOLTAGE TEMPERATURE OUTPUT HIGH VOLTAGE
18 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated
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0.6
0.50.3 0.40.20.1
5
10
15
20
25
30
35
40
45
50
0
0
SourceCurrent, mA)I (
SOURCE
T = 40°C
A–
T =25°C
A
T =85°C
A
V =5V
CC
V V (V)
CC OH
–
0.60.50.3 0.40.20.1
5
10
15
20
25
30
35
40
45
50
0
0
SourceCurrent, mA)I (
SOURCE
T = 40°C
A–
T =25°C
A
T =85°C
A
V =3.3V
CC
V V (V)
CC OH
–
0.7
0.60.50.40.30.20.1
5
10
15
20
25
0
00.7
SourceCurrent, mA)I (
SOURCE
T = 40°C
A–
T =25°C
A
T =85°C
A
V =2.5V
CC
V V (V)
CC OH
–
8535 6010−15−40
1
2
3
4
5
0
V =5V,I =10mA
CC SOURCE
V =1.8V,I =10mA
CC SOURCE
V V (V)
CC OH
–
Temperature, °C)T (
A
TCA6424A
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SCPS193B –JULY 2010–REVISED SEPTEMBER 2010
TYPICAL CHARACTERISTICS (continued)
TA= 25°C (unless otherwise noted)
I/O SOURCE CURRENT I/O SOURCE CURRENT I/O SOURCE CURRENT
vs vs vs
OUTPUT HIGH VOLTAGE OUTPUT HIGH VOLTAGE OUTPUT HIGH VOLTAGE
I/O HIGH VOLTAGE
vs
TEMPERATURE
Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback 19
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SDA LOADCONFIGURATION
VCCI
R =1k
LW
C =50pF
(seeNote A)
L
DUT
SDA
TwoBytesforREADInputPortRegister
(seeFigure9)
VOLTAGEWAVEFORMS
1
2
BYTE DESCRIPTION
I Caddress
2
Inputregisterportdata
SCL
SDA
Stop
Condition
(P)
Start
Condition
(S)
Address
Bit7
(MSB)
Address
Bit1
R/
Bit0
(LSB)
WACK
(A)
Data
Bit7
(MSB)
Data
Bit0
(LSB)
Stop
Condition
(P)
0.7 ´VCCI
0.3 ´VCCI
RepeatStart
Condition Stop
Condition
0.7 ´VCCI
0.3 ´VCCI
tscl tsch
tsp
ticf
ticf
ticr
tsth
ticr tsds tsdh
tocf
tvd(ack)
tvd
tvd
tsts
tsps
tbuf
TCA6424A
SCPS193B –JULY 2010–REVISED SEPTEMBER 2010
www.ti.com
PARAMETER MEASUREMENT INFORMATION
A. CLincludes probe and jig capacitance. tocf is measured with CLof 10 pF or 400 pF.
B. All inputs are supplied by generators having the following characteristics: PRR ≤10 MHz, ZO= 50 Ω, tr/tf≤30 ns.
C. All parameters and waveforms are not applicable to all devices.
Figure 10. I2C Interface Load Circuit and Voltage Waveforms
20 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated
Product Folder Link(s): TCA6424A
A
A
A
A
S 0 1 00 10 AD
DR 1Data1 1 PData2
Start
Condition 8Bits
(OneDataByte)
FromPort DataFromPortSlave Address
R/W
87654321
Address Data1 Data2
INT
B
B
A
A
Pn INT
R/W A
INT SCL
ViewB−BView A−A
ACK
FromSlave ACK
FromSlave
INTERRUPTLOADCONFIGURATION
VCCI
R =4.7k
LW
C =100pF
(seeNote A)
L
DUT
INT
0.7 V´CCI
0.5 V´CCI
0.5 V´CCI
0.5 V´CCP
tsps
tir
tir
tiv
tir
Data
Into
Port
tiv
TCA6424A
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SCPS193B –JULY 2010–REVISED SEPTEMBER 2010
PARAMETER MEASUREMENT INFORMATION (continued)
A. CLincludes probe and jig capacitance.
B. All inputs are supplied by generators having the following characteristics: PRR ≤10 MHz, ZO= 50 Ω, tr/tf≤30 ns.
C. All parameters and waveforms are not applicable to all devices.
Figure 11. Interrupt Load Circuit and Voltage Waveforms
Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback 21
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P0 A
SCL P3
Unstable
Data
LastStableBit
SDA
WRITEMODE(R/ =0)W
P0 A
SCL P3
READMODE(R/ =1)W
DUT
P PORTLOADCONFIGURATION
Pn
500 W
500 W
2 V´CCP
0.7 V´CCP
0.3 V´CCI
0.7 V´CCI
0.3 V´CCI
0.5 V´CCP
C =50pF
(seeNote A)
L
Slave
ACK
t
(seeNoteB)
pv
Pn
Pn
tps
tph
TCA6424A
SCPS193B –JULY 2010–REVISED SEPTEMBER 2010
www.ti.com
PARAMETER MEASUREMENT INFORMATION (continued)
A. CLincludes probe and jig capacitance.
B. tpv is measured from 0.7 × VCC on SCL to 50% I/O (Pn) output.
C. All inputs are supplied by generators having the following characteristics: PRR ≤10 MHz, ZO= 50 Ω, tr/tf≤30 ns.
D. The outputs are measured one at a time, with one transition per measurement.
E. All parameters and waveforms are not applicable to all devices.
Figure 12. P-Port Load Circuit and Timing Waveforms
22 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated
Product Folder Link(s): TCA6424A
SDA
SCL
Start
ACKorReadCycle
RESET
Pn
SDA LOADCONFIGURATION
VCCI
R =1k
LW
C =50pF
(seeNote A)
L
DUT
SDA DUT
P PORTLOADCONFIGURATION
Pn
500 W
500 W
2 V´CCP
C =50pF
(seeNote A)
L
0.3 V´CCI
V /2
CCP
V /2
CCP
tRESET
tREC
tREC
tRESET
tW
TCA6424A
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SCPS193B –JULY 2010–REVISED SEPTEMBER 2010
PARAMETER MEASUREMENT INFORMATION (continued)
A. CLincludes probe and jig capacitance.
B. All inputs are supplied by generators having the following characteristics: PRR ≤10 MHz, ZO= 50 Ω, tr/tf≤30 ns.
C. The outputs are measured one at a time, with one transition per measurement.
D. I/Os are configured as inputs.
E. All parameters and waveforms are not applicable to all devices.
Figure 13. Reset Load Circuits and Voltage Waveforms
Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback 23
Product Folder Link(s): TCA6424A
P00
ADDR
P12
P13
P14
P15
GND
INT
SDA
SCL
TCA6424A
SDA
SCL
INT
GND
Keypad
Status
Monitor
ALARM
Subsystem1
(e.g., Alarm)
A
B
Master
Controller
1
P01
ENABLE
2
P02
P03
P04
P05
P06
P07
P10
P11
P16
P17
P27
P26
P25
P24
P23
P22
P21
P20
6
5
4
3
7
8
9
10
11
12
13
14
15
16
18
17
19
20
21
22
23
24
29
31
30
32
26
25
27
RESET
29
RESET
V
(1.8V)
CCI
VCC VCCP
10kW10kW
10k ( 7)W´
10kW
VCCP
VCCI
VCCI
(seeNoteD)
10kW
TCA6424A
SCPS193B –JULY 2010–REVISED SEPTEMBER 2010
www.ti.com
APPLICATION INFORMATION
Figure 14 shows an application in which the TCA6424A can be used.
A. Device address configured as 0100000 for this example.
B. P00 and P02–P10 are configured as inputs.
C. P01, P11–P17, and P20–P27 are configured as outputs.
D. Resistors are required for inputs (on P port) that may float. If a driver to an input will not let the input float, a resistor is
not needed. Outputs (in the P port) do not need pullup resistors.
Figure 14. Typical Application
24 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated
Product Folder Link(s): TCA6424A
Px
LED
100 kW
VCC
VCC
3.3 V
Px
LED
5 V
VCC
VCC
Ramp-Up Re-Ramp-Up
Time to Re-Ramp
Time
Ramp-Down
VCC_RT VCC_RT
VCC_FT
VCC_TRR_GND
TCA6424A
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SCPS193B –JULY 2010–REVISED SEPTEMBER 2010
Minimizing ICC When I/Os Control LEDs
When the I/Os are used to control LEDs, normally they are connected to VCC through a resistor as shown in
Figure 14. The LED acts as a diode so, when the LED is off, the I/O VIN is about 1.2 V less than VCC. The ΔICC
parameter in Electrical Characteristics shows how ICC increases as VIN becomes lower than VCC. Designs that
must minimize current consumption, such as battery power applications, should consider maintaining the I/O pins
greater than or equal to VCC when the LED is off.
Figure 15 shows a high-value resistor in parallel with the LED. Figure 16 shows VCC less than the LED supply
voltage by at least 1.2 V. Both of these methods maintain the I/O VIN at or above VCC and prevent additional
supply current consumption when the LED is off.
Figure 15. High-Value Resistor in Parallel With the LED
Figure 16. Device Supplied by a Low Voltage
Power-On Reset Requirements
In the event of a glitch or data corruption, TCA6424A can be reset to its default conditions by using the power-on
reset feature. Power-on reset requires that the device go through a power cycle to be completely reset. This
reset also happens when the device is powered on for the first time in an application.
The two types of power-on reset are shown in Figure 17 and Figure 18.
Figure 17. VCC is Lowered Below 0.2 V or 0 V and Then Ramped Up to VCC
Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback 25
Product Folder Link(s): TCA6424A
VCC
Ramp-Up
Time to Re-Ramp
Time
Ramp-Down
VIN drops below POR levels
VCC_RT
VCC_FT
VCC_TRR_VPOR50
VCC
Time
VCC_GH
VCC_GW
TCA6424A
SCPS193B –JULY 2010–REVISED SEPTEMBER 2010
www.ti.com
Figure 18. VCC is Lowered Below the POR Threshold, Then Ramped Back Up to VCC
Table 10 specifies the performance of the power-on reset feature for TCA6424A for both types of power-on reset.
Table 10. Recommended Supply Sequencing and Rates (1)
PARAMETER MIN TYP MAX UNIT
tVCC_FT Fall rate See Figure 17 1 100 ms
tVCC_RT Rise rate See Figure 17 0.01 100 ms
tVCC_TRR_GND Time to re-ramp (when VCC drops to GND) See Figure 17 40 ms
tVCC_TRR_POR50 Time to re-ramp (when VCC drops to VPOR_MIN – 50 mV) See Figure 18 40 ms
Level that VCCP can glitch down to, but not cause a functional
VCC_GH See Figure 19 1.2 V
disruption when VCCX_GW = 1 ms
Glitch width that will not cause a functional disruption when
tVCC_GW See Figure 19 10 ms
VCCX_GH = 0.5 × VCCx
VPORF Voltage trip point of POR on falling VCC 0.767 1.144 V
VPORR Voltage trip point of POR on fising VCC 1.033 1.428 V
(1) TA= –40°C to 85°C (unless otherwise noted)
Glitches in the power supply can also affect the power-on reset performance of this device. The glitch width
(VCC_GW) and height (VCC_GH) are dependent on each other. The bypass capacitance, source impedance, and
device impedance are factors that affect power-on reset performance. Figure 19 and Table 10 provide more
information on how to measure these specifications.
Figure 19. Glitch Width and Glitch Height
VPOR is critical to the power-on reset. VPOR is the voltage level at which the reset condition is released and all the
registers and the I2C/SMBus state machine are initialized to their default states. The value of VPOR differs based
on the VCC being lowered to or from 0. Figure 20 and Table 10 provide more details on this specification.
26 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated
Product Folder Link(s): TCA6424A
VCC
VPOR
VPORF
Time
POR
Time
TCA6424A
www.ti.com
SCPS193B –JULY 2010–REVISED SEPTEMBER 2010
Figure 20. VPOR
Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback 27
Product Folder Link(s): TCA6424A
TCA6424A
SCPS193B –JULY 2010–REVISED SEPTEMBER 2010
www.ti.com
REVISION HISTORY
Changes from Original (July 2010) to Revision A Page
• Changed Recommended Supply Sequencing and Rates Table ........................................................................................ 26
28 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated
Product Folder Link(s): TCA6424A
PACKAGE OPTION ADDENDUM
www.ti.com 27-Sep-2010
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
TCA6424ARGJR ACTIVE UQFN RGJ 32 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Request Free Samples
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
TCA6424ARGJR UQFN RGJ 32 3000 330.0 12.4 5.3 5.3 0.75 8.0 12.0 Q2
PACKAGE MATERIALS INFORMATION
www.ti.com 22-Sep-2010
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TCA6424ARGJR UQFN RGJ 32 3000 346.0 346.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 22-Sep-2010
Pack Materials-Page 2
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