a LC2MOS Precision 5 V/3 V Quad SPST Switches ADG511/ADG512/ADG513 FEATURES +3 V, +5 V or 5 V Power Supplies Ultralow Power Dissipation (<0.5 W) Low Leakage (<100 pA) Low On Resistance (<50 ) Fast Switching Times Low Charge Injection TTL/CMOS Compatible 16-Lead DIP or SOIC Package APPLICATIONS Battery-Powered Instruments Single Supply Systems Remote Powered Equipment 5 V Supply Systems Computer Peripherals such as Disk Drives Precision Instrumentation Audio and Video Switching Automatic Test Equipment Precision Data Acquisition Sample Hold Systems Communication Systems Compatible with 5 V Supply DACs and ADCs such as AD7840/AD7848, AD7870/AD7871/AD7872/AD7874/ AD7875/AD7876/AD7878 FUNCTIONAL BLOCK DIAGRAMS S1 S1 IN1 IN1 D1 S2 D1 S2 ADG511 D2 S3 ADG512 D2 S3 IN3 IN3 D3 S4 ADG513 D4 D2 S3 IN3 D3 S4 IN4 IN4 D1 S2 IN2 IN2 IN2 S1 IN1 D3 S4 IN4 D4 D4 SWITCHES SHOWN FOR A LOGIC "1" INPUT The ADG511, ADG512 and ADG513 contain four independent SPST switches. The ADG511 and ADG512 differ only in that the digital control logic is inverted. The ADG511 switch is turned on with a logic low on the appropriate control input, while a logic high is required for the ADG512. The ADG513 contains two switches whose digital control logic is similar to that of the ADG511 while the logic is inverted in the remaining two switches. PRODUCT HIGHLIGHTS GENERAL DESCRIPTION The ADG511, ADG512 and ADG513 are monolithic CMOS ICs containing four independently selectable analog switches. These switches feature low, well-controlled on resistance and wide analog signal range, making them ideal for precision analog signal switching. These switch arrays are fabricated using Analog Devices' advanced linear compatible CMOS (LC2MOS) process which offers the additional benefits of low leakage currents, ultralow power dissipation and low capacitance for fast switching speeds with minimum charge injection. These features make the ADG511, ADG512 and ADG513 the optimum choice for a wide variety of signal switching tasks in precision analog signal processing and data acquisition systems. 1. 5 Volt Single Supply Operation The ADG511/ADG512/ADG513 offers high performance, including low on resistance and wide signal range, fully specified and guaranteed with +3 V, 5 V as well as +5 V supply rails. 2. Ultralow Power Dissipation CMOS construction ensures ultralow power dissipation. 3. Low RON 4. Break-Before-Make Switching Switches are guaranteed to have break-before-make operation. This allows multiple outputs to be tied together for multiplexer applications without the possibility of momentary shorting between channels. The ability to operate from single +3 V, +5 V or 5 V bipolar supplies make the ADG511, ADG512 and ADG513 perfect for use in battery-operated instruments, 4-20 mA loop systems and with the new generation of DACs and ADCs from Analog Devices. The use of 5 V supplies and reduced operating currents give much lower power dissipation than devices operating from 15 V supplies. REV. C Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 (c) Analog Devices, Inc., 2001 ADG511/ADG512/ADG513-SPECIFICATIONS1 Dual Supply (V DD = +5 V 10%, VSS = -5 V 10%, GND = 0 V, unless otherwise noted) Parameter B Versions -40C to 25C +85C ANALOG SWITCH Analog Signal Range RON 30 T Version -55C to 25C +125C VDD to VSS Drain OFF Leakage ID (OFF) Channel ON Leakage ID, IS (ON) 0.025 0.1 0.025 0.1 0.05 0.2 DIGITAL INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current IINL or IINH 0.005 DYNAMIC CHARACTERISTICS2 tON 200 Test Conditions/Comments V typ max VD = 3.5 V, IS = -10 mA; VDD = +4.5 V, VSS = -4.5 V 5 nA typ nA max nA typ nA max nA typ nA max VDD = +5.5 V, VSS = -5.5 V VD = 4.5 V, VS = 4.5 V; Test Circuit 2 VD = 4.5 V, VS = 4.5 V; Test Circuit 2 VD = VS = 4.5 V; Test Circuit 3 2.4 0.8 V min V max 0.1 A typ A max VIN = VINL or VINH RL = 300 . CL = 35 pF; VS = 3 V; Test Circuit 4 RL = 300 . CL = 35 pF; VS = 3 V; Test Circuit 4 RL = 300 , CL = 35 pF; VS1 = VS2 = 3 V; Test Circuit 5 VS = 0 V, RS = 0 , CL = 10 nF; Test Circuit 6 RL = 50 , CL = 5 pF, f = 1 MHz; Test Circuit 7 RL = 50 , CL = 5 pF, f = 1 MHz; Test Circuit 8 f = 1 MHz f = 1 MHz f = 1 MHz VDD to VSS 30 50 LEAKAGE CURRENTS Source OFF Leakage IS (OFF) Unit 2.5 2.5 5 50 0.025 0.1 0.025 0.1 0.05 0.2 2.4 0.8 2.5 2.5 0.005 0.1 200 Break-Before-Make Time Delay, tD (ADG513 Only) Charge Injection 100 100 ns typ ns max ns typ ns max ns typ 11 11 pC typ OFF Isolation 68 68 dB typ Channel-to-Channel Crosstalk 85 85 dB typ CS (OFF) CD (OFF) CD, CS (ON) 9 9 35 9 9 35 pF typ pF typ pF typ 375 tOFF 120 375 120 150 POWER REQUIREMENTS VDD VSS IDD 150 +4.5/5.5 -4.5/-5.5 0.0001 +4.5/5.5 -4.5/-5.5 0.0001 1 ISS 0.0001 1 0.0001 1 1 V min/max V min/max A typ A max A typ A max VDD = +5.5 V, VSS = -5.5 V Digital Inputs = 0 V or 5 V NOTES 1 Temperature ranges are as follows: B Versions -40C to +85C; T Version -55C to +125C. 2 Guaranteed by design, not subject to production test. Specifications subject to change without notice. -2- REV. C ADG511/ADG512/ADG513 Single Supply (V DD = 5 V 10%, VSS = 0 V, GND = 0 V, unless otherwise noted) Parameter B Versions -40C to 25C +85C ANALOG SWITCH Analog Signal Range RON 45 T Version -55C to 25C +125C Drain OFF Leakage ID (OFF) Channel ON Leakage ID, IS (ON) 0.025 0.1 0.025 0.1 0.05 0.2 DIGITAL INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current IINL or IINH 0.005 DYNAMIC CHARACTERISTICS2 tON 250 Test Conditions/Comments V typ max VD = 3.5 V, IS = -10 mA; VDD = 4.5 V 5 nA typ nA max nA typ nA max nA typ nA max VDD = 5.5 V VD = 4.5/1 V, VS = 14.5 V; Test Circuit 2 VD = 4.5/1 V, VS = 14.5 V; Test Circuit 2 VD = VS = 4.5 V/1 V; Test Circuit 3 2.4 0.8 V min V max 0.1 A typ A max VIN = VINL or VINH 0 V to VDD 0 V to VDD 45 75 LEAKAGE CURRENTS Source OFF Leakage IS (OFF) Unit 2.5 2.5 5 75 0.025 0.1 0.025 0.1 0.05 0.2 2.4 0.8 2.5 2.5 0.005 0.1 Break-Before-Make Time Delay, tD (ADG513 Only) Charge Injection 200 200 ns typ ns max ns typ ns max ns typ 16 16 pC typ OFF Isolation 68 68 dB typ Channel-to-Channel Crosstalk 85 85 dB typ CS (OFF) CD (OFF) CD, CS (ON) 9 9 35 9 9 35 pF typ pF typ pF typ RL = 300 , CL = 35 pF; VS = 2 V; Test Circuit 4 RL = 300 , CL = 35 pF; VS = 2 V; Test Circuit 4 RL = 300 , CL = 35 pF; VS1 = VS2 = 2 V; Test Circuit 5 VS = 0 V, RS = 0 , CL = 10 nF; Test Circuit 6 RL = 50 , CL = 5 pF, f = 1 MHz; Test Circuit 7 RL = 50 , CL = 5 pF, f = 1 MHz; Test Circuit 8 f = 1 MHz f = 1 MHz f = 1 MHz V min/max A typ A max VDD = 5.5 V Digital Inputs = 0 V or 5 V 250 500 tOFF 50 500 50 100 POWER REQUIREMENTS VDD IDD 100 4.5/5.5 0.0001 4.5/5.5 0.0001 1 1 NOTES 1 Temperature ranges are as follows: B Versions -40C to +85C; T Version -55C to +125C. 2 Guaranteed by design, not subject to production test. Specifications subject to change without notice. REV. C -3- ADG511/ADG512/ADG513-SPECIFICATIONS1 Single Supply (V DD = 3.3 V 10%, VSS = 0 V, GND = 0 V, unless otherwise noted) Parameter B Version 0C to 25C 70C ANALOG SWITCH Analog Signal Range RON 200 Unit Test Conditions/Comments V typ max VD = 1.5 V, IS = -1 mA; VDD = 3 V 5 nA typ nA max nA typ nA max nA typ nA max VDD = 3.6 V VD = 2.6/1 V, VS = 12.6 V; Test Circuit 2 VD = 2.6/1 V, VS = 12.6 V; Test Circuit 2 VD = VS = 2.6 V/1 V; Test Circuit 3 2.4 0.8 V min V max 0.1 A typ A max VIN = VINL or VINH 0 V to VDD 500 LEAKAGE CURRENTS Source OFF Leakage IS (OFF) Drain OFF Leakage ID (OFF) Channel ON Leakage ID, IS (ON) 0.025 0.1 0.025 0.1 0.05 0.2 DIGITAL INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current IINL or IINH 0.005 DYNAMIC CHARACTERISTICS2 tON 600 2.5 2.5 tOFF 100 Break-Before-Make Time Delay, tD (ADG513 Only) Charge Injection 500 ns typ ns max ns typ ns max ns typ 11 pC typ OFF Isolation 68 dB typ Channel-to-Channel Crosstalk 85 dB typ CS (OFF) CD (OFF) CD, CS (ON) 9 9 35 pF typ pF typ pF typ RL = 300 , CL = 35 pF; VS = 1 V; Test Circuit 4 RL = 300 , CL = 35 pF; VS = 1 V; Test Circuit 4 RL = 300 , CL = 35 pF; VS1 = VS2 = 1 V; Test Circuit 5 VS = 0 V, RS = 0 , CL = 10 nF; Test Circuit 6 RL = 50 , CL = 5 pF, f = 1 MHz; Test Circuit 7 RL = 50 , CL = 5 pF, f = 1 MHz; Test Circuit 8 f = 1 MHz f = 1 MHz f = 1 MHz V min/max A typ A max VDD = 3.6 V Digital Inputs = 0 V or 3 V 1200 160 POWER REQUIREMENTS VDD IDD 3/3.6 0.0001 1 NOTES 1 Temperature range is as follows: B Version -40C to +85C. 2 Guaranteed by design, not subject to production test. Specifications subject to change without notice. -4- REV. C ADG511/ADG512/ADG513 ABSOLUTE MAXIMUM RATINGS 1 Plastic Package, Power Dissipation . . . . . . . . . . . . . . . 470 mW JA Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 117C/W Lead Temperature, Soldering (10 sec) . . . . . . . . . . . . 260C SOIC Package, Power Dissipation . . . . . . . . . . . . . . . . 600 mW JA Thermal Impedance . . . . . . . . . . . . . . . . . . . . . . 77C/W Lead Temperature, Soldering Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . 215C Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . 220C (TA = +25C unless otherwise noted) VDD to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 V VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to +25 V VSS to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . +0.3 V to -25 V Analog, Digital Inputs2 . . . . . . . . . . VSS - 2 V to VDD + 2 V or 30 mA, Whichever Occurs First Continuous Current, S or D . . . . . . . . . . . . . . . . . . . . . 30 mA Peak Current, S or D . . . . . . . . . . . . . . . . . . . . . . . . . . 100 mA (Pulsed at 1 ms, 10% Duty Cycle max) Operating Temperature Range Industrial (B Version) . . . . . . . . . . . . . . . . . -40C to +85C Extended (T Version) . . . . . . . . . . . . . . . . -55C to +125C Storage Temperature Range . . . . . . . . . . . . . -65C to +150C Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 150C Cerdip Package, Power Dissipation . . . . . . . . . . . . . . . 900 mW JA Thermal Impedance . . . . . . . . . . . . . . . . . . . . . . 76C/W Lead Temperature, Soldering (10 sec) . . . . . . . . . . . . 300C NOTES 1 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Only one absolute maximum rating may be applied at any one time. 2 Overvoltages at IN, S or D will be clamped by internal diodes. Current should be limited to the maximum ratings given. CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the ADG511/ADG512/ADG513 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. WARNING! ORDERING GUIDE Model1 Temperature Range2 Package Option3 ADG511BN ADG511BR ADG511ABR4 ADG511TQ4 -40C to +85C -40C to +85C -40C to +85C -55C to +125C N-16 R-16A R-16A Q-16 ADG512BN ADG512BR ADG512ABR4 -40C to +85C -40C to +85C -40C to +85C N-16 R-16A R-16A ADG513BN ADG513BR ADG513ABR4 -40C to +85C -40C to +85C -40C to +85C N-16 R-16A R-16A NOTES 1 For availability of MIL-STD-883, Class B processed parts, contact factory. 2 3.3 V specifications apply over 0C to 70C temperature range. 3 N = Plastic DIP; R = 0.15" Small Outline IC (SOIC); Q = Cerdip. 4 Trench isolated latch-up proof parts. See Trench Isolation section. REV. C -5- ESD SENSITIVE DEVICE ADG511/ADG512/ADG513 PIN CONFIGURATION (DIP/SOIC) IN1 1 16 IN2 D1 2 15 D2 14 S2 ADG511 ADG512 ADG513 S1 3 TERMINOLOGY VDD VSS Most Positive Power Supply Potential. Most Negative Power Supply Potential in dual supplies. In single supply applications, it may be connected to GND. GND Ground (0 V) Reference. S Source Terminal. May be an input or output. D Drain Terminal. May be an input or output. IN Logic Control Input. RON Ohmic Resistance between D and S. IS (OFF) Source Leakage Current with the switch "OFF." ID (OFF) Drain Leakage Current with the switch "OFF." ID, IS (ON) Channel Leakage Current with the switch "ON." VD (VS) Analog Voltage on terminals D, S. CS (OFF) "OFF" Switch Source Capacitance. CD (OFF) "OFF" Switch Drain Capacitance. CD, CS (ON) "ON" Switch Capacitance. tON Delay between applying the digital control input and the output switching on. tOFF Delay between applying the digital control input and the output switching off. tD "OFF" or "ON" time measured between the 90% points of both switches when switching from one address state to another. Crosstalk A measure of unwanted signal which is coupled through from one channel to another as a result of parasitic capacitance. Off Isolation A measure of unwanted signal coupling through an "OFF" switch. Charge Injection A measure of the glitch impulse transferred from the digital input to the analog output during switching. VDD TOP VIEW GND 5 (Not to Scale) 12 NC VSS 4 13 S4 6 11 S3 D4 7 10 D3 IN4 8 9 IN3 NC = NO CONNECT Truth Table (ADG511/ADG512) ADG511 In ADG512 In Switch Condition 0 1 1 0 ON OFF Truth Table (ADG513) Logic Switch 1, 4 Switch 2, 3 0 1 OFF ON ON OFF -6- REV. C Typical Performance Characteristics-ADG511/ADG512/ADG513 50 10mA VDD = +5V VSS = -5V TA = 25C 1mA 100A VDD = +3V VSS = -3V 30 I-, I+ ISUPPLY RON - 40 20 10A 1A VDD = +5V VSS = -5V 10 1 SW 4 SW 100nA 0 -5 10nA -4 -3 -2 -1 1 2 3 4 0 VD OR VS - DRAIN OR SOURCE VOLTAGE - V 5 10 1k 10k 100k FREQUENCY - Hz 10M 1M TPC 4. Supply Current vs. Input Switching Frequency TPC 1. On Resistance as a Function of VD (VS) Dual Supplies 10 50 VDD = +5V VSS = -5V LEAKAGE CURRENT - nA 40 RON - 100 30 125C 85C 20 25C 1 VDD = +5V VSS = -5V VS = 5V VD = 5V ID (OFF) 0.1 ID (ON) 0.01 10 IS (OFF) 0 -5 -4 -3 -2 -1 1 2 3 4 0 VD OR VS - DRAIN OR SOURCE VOLTAGE - V 0.001 25 5 TPC 2. On Resistance as a Function of VD (VS) for Different Temperatures 35 45 55 65 75 85 95 TEMPERATURE - C 115 125 TPC 5. Leakage Currents as a Function of Temperature 120 90 TA = 25C VDD = +5V VSS = -5V 80 VDD = 3V VSS = 0V 100 OFF ISOLATION - dB 70 RON - 105 60 50 VDD = 5V VSS = 0V 40 80 60 30 20 0 1 2 3 4 VD OR VS - DRAIN OR SOURCE VOLTAGE - V 40 100 5 10k 100k FREQUENCY - Hz 1M TPC 6. Off Isolation vs. Frequency TPC 3. On Resistance as a Function of VD (VS) Single Supply REV. C 1k -7- 10M ADG511/ADG512/ADG513 network RC and CC. This compensation network also reduces the hold time glitch while optimizing the acquisition time. Using the illustrated op amps and component values, the pedestal error has a maximum value of 5 mV over the 3 V input range. The acquisition time is 2.5 s while the settling time is 1.85 s. 0.006 LEAKAGE CURRENT - nA 0.004 VDD = +5V VSS = -5V TA = +25C ID (ON) 0.002 ID (OFF) 0.000 IS (OFF) +5V 2200pF +5V SW2 -0.002 +5V -0.004 -0.006 -5 S VIN D SW1 AD845 S D -5V -4 -3 -2 -1 0 1 2 3 4 VD OR VS - DRAIN OR SOURCE VOLTAGE - V 5 RC 75 CC 1000pF CH 2200pF VOUT OP07 -5V ADG511/ ADG512/ ADG513 TPC 7. Leakage Currents as a Function of VD (VS) -5V Figure 1. Accurate Sample-and-Hold 110 VDD = +5V VSS = -5V TRENCH ISOLATION The MOS devices that make up the ADG511A/ADG512A/ ADG513A are isolated from each other by an oxide layer (trench) (see Figure 2). When the NMOS and PMOS devices are not electrically isolated from each other, there exists the possibility of "latch-up" caused by parasitic junctions between CMOS transistors. Latch-up is caused when P-N junctions that are normally reverse biased, become forward biased, causing large currents to flow. This can be destructive. CROSSTALK - dB 100 90 80 70 60 100 1k 10k 100k FREQUENCY - Hz 1M 10M TPC 8. Crosstalk vs. Frequency APPLICATION Figure 1 illustrates a precise sample-and-hold circuit. An AD845 is used as the input buffer while the output operational amplifier is an OP07. During the track mode, SW1 is closed and the output VOUT follows the input signal VIN. In the hold mode, SW1 is opened and the signal is held by the hold capacitor CH. CMOS devices are normally isolated from each other by Junction Isolation. In Junction Isolation the N and P wells of the CMOS transistors form a diode that is reverse biased under normal operation. However, during overvoltage conditions, this diode becomes forward biased. A Silicon-Controlled Rectifier (SCR)type circuit is formed by the two transistors, causing a significant amplification of the current that, in turn, leads to latch-up. With Trench Isolation, this diode is removed; the result is a latch-up-proof circuit. VS Due to switch and capacitor leakage, the voltage on the hold capacitor will decrease with time. The ADG511/ADG512/ ADG513 minimizes this droop due to its low leakage specifications. The droop rate is further minimized by the use of a polystyrene hold capacitor. The droop rate for the circuit shown is typically 15 V/s. T R E N C H P+ N- VG VD P-CHANNEL P+ VG VS T R E N C H N+ N-CHANNEL P- VD N+ T R E N C H BURIED OXIDE LAYER SUBSTRATE (BACKGATE) A second switch, SW2, which operates in parallel with SW1, is included in this circuit to reduce pedestal error. Since both switches will be at the same potential, they will have a differential effect on the op amp OP07, which will minimize charge injection effects. Pedestal error is also reduced by the compensation Figure 2. Trench Isolation -8- REV. C ADG511/ADG512/ADG513 Test Circuits IDS V1 S S A D D S A D RON = V1/IDS Test Circuit 1. On Resistance Test Circuit 2. Off Leakage Test Circuit 3. On Leakage VDD 0.1F 3V VDD S VS D VIN ADG511 VIN ADG512 VOUT RL 300 IN 50% 50% 50% 50% 3V CL 35pF 90% 90% VOUT VSS GND 0.1F VSS tON tOFF Test Circuit 4. Switching Times VDD 0.1F 3V VIN VDD VS1 VS2 S1 D1 S2 D2 VIN GND 50% 0V VOUT1 VOUT2 RL2 300 IN1, IN2 RL1 300 50% 90% 90% VOUT1 CL1 35pF 0V CL2 35pF VSS 90% VOUT2 90% 0V tD 0.1F VSS tD Test Circuit 5. Break-Before-Make Time Delay VDD 3V VDD RS VS S D VIN VOUT CL 10nF IN VOUT GND VSS VOUT QINJ = CL VOUT VSS Test Circuit 6. Charge Injection REV. C A VD VS VD VS VS ID (ON) ID (OFF) IS (OFF) -9- ADG511/ADG512/ADG513 VDD VDD 0.1F 0.1F VDD VDD S S D VOUT RL 50 VS VIN VIN1 VS VIN2 IN D VOUT GND VSS RL 50 0.1F VSS S GND NC VSS 0.1F VSS Test Circuit 7. Off Isolation 50 D CHANNEL-TO-CHANNEL CROSSTALK = 20 LOG VS/VOUT Test Circuit 8. Channel-to-Channel Crosstalk -10- REV. C ADG511/ADG512/ADG513 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 16-Lead Plastic DIP (N-16) 0.840 (21.34) 0.745 (18.92) 16 9 1 8 0.280 (7.11) 0.240 (6.10) PIN 1 0.060 (1.52) 0.015 (0.38) 0.210 (5.33) MAX 0.160 (4.06) 0.115 (2.93) 0.325 (8.26) 0.300 (7.62) 0.195 (4.95) 0.115 (2.93) 0.130 (3.30) MIN 0.022 (0.558) 0.014 (0.356) 0.015 (0.381) 0.008 (0.204) 0.070 (1.77) SEATING 0.045 (1.15) PLANE 0.100 (2.54) BSC 16-Lead Cerdip (Q-16) 0.005 (0.13) MIN 0.080 (2.03) MAX 16 9 1 8 0.310 (7.87) 0.220 (5.59) PIN 1 0.060 (1.52) 0.015 (0.38) 0.840 (21.34) MAX 0.200 (5.08) MAX 0.200 (5.08) 0.125 (3.18) 0.023 (0.58) 0.014 (0.36) 0.100 (2.54) BSC 0.150 (3.81) MIN SEATING 0.070 (1.78) PLANE 0.030 (0.76) 0.320 (8.13) 0.290 (7.37) 15 0 0.015 (0.38) 0.008 (0.20) 16-Lead SOIC (R-16A) 0.3937 (10.00) 0.3859 (9.80) 0.1574 (4.00) 0.1497 (3.80) 16 9 1 8 PIN 1 0.0098 (0.25) 0.0040 (0.10) 0.0500 SEATING (1.27) PLANE BSC REV. C 0.2440 (6.20) 0.2284 (5.80) 0.0688 (1.75) 0.0532 (1.35) 0.0192 (0.49) 0.0138 (0.35) 0.0196 (0.50) x 45 0.0099 (0.25) 8 0.0099 (0.25) 0 0.0500 (1.27) 0.0160 (0.41) 0.0075 (0.19) -11- ADG511/ADG512/ADG513-Revision History Location Page Data Sheet changed from REV. B to REV. C. Changes to Specifications table, Dual Supply, and Notes: "T Versions" made singular . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Changes to Specifications table, Single Supply, and Notes: "T Versions" made singular . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 PRINTED IN U.S.A. C00036b-0-5/01(C) Change to Ordering Guide: Removed one line . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 -12- REV. C