FUNCTIONAL BLOCK DIAGRAMS
IN1
IN2
IN3
IN4
S1
D1
S2
D2
S3
D3
S4
D4
ADG511
IN1
IN2
IN3
IN4
S1
D1
S2
D2
S3
D3
S4
D4
ADG512
IN1
IN2
IN3
IN4
S1
D1
S2
D2
S3
D3
S4
D4
ADG513
SWITCHES SHOWN FOR A LOGIC "1" INPUT
REV. C
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
a
LC
2
MOS
Precision 5 V/3 V Quad SPST Switches
ADG511/ADG512/ADG513
FEATURES
+3 V, +5 V or 5 V Power Supplies
Ultralow Power Dissipation (<0.5 W)
Low Leakage (<100 pA)
Low On Resistance (<50 )
Fast Switching Times
Low Charge Injection
TTL/CMOS Compatible
16-Lead DIP or SOIC Package
APPLICATIONS
Battery-Powered Instruments
Single Supply Systems
Remote Powered Equipment
5 V Supply Systems
Computer Peripherals such as Disk Drives
Precision Instrumentation
Audio and Video Switching
Automatic Test Equipment
Precision Data Acquisition
Sample Hold Systems
Communication Systems
Compatible with 5 V Supply DACs and ADCs such as
AD7840/AD7848, AD7870/AD7871/AD7872/AD7874/
AD7875/AD7876/AD7878
GENERAL DESCRIPTION
The ADG511, ADG512 and ADG513 are monolithic CMOS
ICs containing four independently selectable analog switches.
These switches feature low, well-controlled on resistance and
wide analog signal range, making them ideal for precision
analog signal switching.
These switch arrays are fabricated using Analog Devices’
advanced linear compatible CMOS (LC
2
MOS) process which
offers the additional benefits of low leakage currents, ultralow
power dissipation and low capacitance for fast switching speeds
with minimum charge injection. These features make the
ADG511, ADG512 and ADG513 the optimum choice for a
wide variety of signal switching tasks in precision analog signal
processing and data acquisition systems.
The ability to operate from single +3 V, +5 V or ±5 V bipolar
supplies make the ADG511, ADG512 and ADG513 perfect for
use in battery-operated instruments, 4–20 mA loop systems and
with the new generation of DACs and ADCs from Analog
Devices. The use of 5 V supplies and reduced operating currents
give much lower power dissipation than devices operating from
±15 V supplies.
The ADG511, ADG512 and ADG513 contain four indepen-
dent SPST switches. The ADG511 and ADG512 differ only in
that the digital control logic is inverted. The ADG511 switch is
turned on with a logic low on the appropriate control input,
while a logic high is required for the ADG512. The ADG513
contains two switches whose digital control logic is similar to
that of the ADG511 while the logic is inverted in the remaining
two switches.
PRODUCT HIGHLIGHTS
1. 5 Volt Single Supply Operation
The ADG511/ADG512/ADG513 offers high performance,
including low on resistance and wide signal range, fully
specified and guaranteed with +3 V, ±5 V as well as +5 V
supply rails.
2. Ultralow Power Dissipation
CMOS construction ensures ultralow power dissipation.
3. Low R
ON
4. Break-Before-Make Switching
Switches are guaranteed to have break-before-make opera-
tion. This allows multiple outputs to be tied together for
multiplexer applications without the possibility of momentary
shorting between channels.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 www.analog.com
Fax: 781/326-8703 © Analog Devices, Inc., 2001
Dual Supply
B Versions T Version
–40C to –55C to
Parameter 25C +85C25C +125C Unit Test Conditions/Comments
ANALOG SWITCH
Analog Signal Range V
DD
to V
SS
V
DD
to V
SS
V
R
ON
30 30 Ω typ V
D
= ±3.5 V, I
S
= –10 mA;
50 50 Ω max V
DD
= +4.5 V, V
SS
= –4.5 V
LEAKAGE CURRENTS V
DD
= +5.5 V, V
SS
= –5.5 V
Source OFF Leakage I
S
(OFF) ±0.025 ±0.025 nA typ V
D
= ±4.5 V, V
S
= ⫿4.5 V;
±0.1 ±2.5 ±0.1 ±2.5 nA max Test Circuit 2
Drain OFF Leakage I
D
(OFF) ±0.025 ±0.025 nA typ V
D
= ±4.5 V, V
S
= ⫿4.5 V;
±0.1 ±2.5 ±0.1 ±2.5 nA max Test Circuit 2
Channel ON Leakage I
D
, I
S
(ON) ±0.05 ±0.05 nA typ V
D
= V
S
= ±4.5 V;
±0.2 ±5±0.2 ±5 nA max Test Circuit 3
DIGITAL INPUTS
Input High Voltage, V
INH
2.4 2.4 V min
Input Low Voltage, V
INL
0.8 0.8 V max
Input Current
I
INL
or I
INH
0.005 0.005 µA typ V
IN
= V
INL
or V
INH
±0.1 ±0.1 µA max
DYNAMIC CHARACTERISTICS
2
t
ON
200 200 ns typ R
L
= 300 Ω. C
L
= 35 pF;
375 375 ns max V
S
= ±3 V; Test Circuit 4
t
OFF
120 120 ns typ R
L
= 300 Ω. C
L
= 35 pF;
150 150 ns max V
S
= ±3 V; Test Circuit 4
Break-Before-Make Time 100 100 ns typ R
L
= 300 Ω, C
L
= 35 pF;
Delay, t
D
(ADG513 Only) V
S1
= V
S2
= 3 V; Test Circuit 5
Charge Injection 11 11 pC typ V
S
= 0 V, R
S
= 0 Ω, C
L
= 10 nF;
Test Circuit 6
OFF Isolation 68 68 dB typ R
L
= 50 Ω, C
L
= 5 pF, f = 1 MHz;
Test Circuit 7
Channel-to-Channel Crosstalk 85 85 dB typ R
L
= 50 Ω, C
L
= 5 pF, f = 1 MHz;
Test Circuit 8
C
S
(OFF) 9 9 pF typ f = 1 MHz
C
D
(OFF) 9 9 pF typ f = 1 MHz
C
D
, C
S
(ON) 35 35 pF typ f = 1 MHz
POWER REQUIREMENTS
V
DD
+4.5/5.5 +4.5/5.5 V min/max
V
SS
–4.5/–5.5 –4.5/–5.5 V min/max
I
DD
0.0001 0.0001 µA typ V
DD
= +5.5 V, V
SS
= –5.5 V
11µA max Digital Inputs = 0 V or 5 V
I
SS
0.0001 0.0001 µA typ
11µA max
NOTES
1
Temperature ranges are as follows: B Versions –40°C to +85°C; T Version –55°C to +125°C.
2
Guaranteed by design, not subject to production test.
Specifications subject to change without notice.
REV. C–2–
(V
DD
= +5 V 10%, V
SS
= –5 V 10%, GND = 0 V, unless otherwise noted)
ADG511/ADG512/ADG513–SPECIFICATIONS
1
Single Supply
B Versions T Version
–40C to –55C to
Parameter 25C +85C25C +125C Unit Test Conditions/Comments
ANALOG SWITCH
Analog Signal Range 0 V to V
DD
0 V to V
DD
V
R
ON
45 45 Ω typ V
D
= 3.5 V, I
S
= –10 mA;
75 75 Ω max V
DD
= 4.5 V
LEAKAGE CURRENTS V
DD
= 5.5 V
Source OFF Leakage I
S
(OFF) ±0.025 ±0.025 nA typ V
D
= 4.5/1 V, V
S
= 1Ⲑ4.5 V;
±0.1 ±2.5 ±0.1 ±2.5 nA max Test Circuit 2
Drain OFF Leakage I
D
(OFF) ±0.025 ±0.025 nA typ V
D
= 4.5/1 V, V
S
= 1Ⲑ4.5 V;
±0.1 ±2.5 ±0.1 ±2.5 nA max Test Circuit 2
Channel ON Leakage I
D
, I
S
(ON) ±0.05 ±0.05 nA typ V
D
= V
S
= 4.5 V/1 V;
±0.2 ±5±0.2 ±5 nA max Test Circuit 3
DIGITAL INPUTS
Input High Voltage, V
INH
2.4 2.4 V min
Input Low Voltage, V
INL
0.8 0.8 V max
Input Current
I
INL
or I
INH
0.005 0.005 µA typ V
IN
= V
INL
or V
INH
±0.1 ±0.1 µA max
DYNAMIC CHARACTERISTICS
2
t
ON
250 250 ns typ R
L
= 300 Ω, C
L
= 35 pF;
500 500 ns max V
S
= 2 V; Test Circuit 4
t
OFF
50 50 ns typ R
L
= 300 Ω, C
L
= 35 pF;
100 100 ns max V
S
= 2 V; Test Circuit 4
Break-Before-Make Time 200 200 ns typ R
L
= 300 Ω, C
L
= 35 pF;
Delay, t
D
(ADG513 Only) V
S1
= V
S2
= 2 V; Test Circuit 5
Charge Injection 16 16 pC typ V
S
= 0 V, R
S
= 0 Ω, C
L
= 10 nF;
Test Circuit 6
OFF Isolation 68 68 dB typ R
L
= 50 Ω, C
L
= 5 pF, f = 1 MHz;
Test Circuit 7
Channel-to-Channel Crosstalk 85 85 dB typ R
L
= 50 Ω, C
L
= 5 pF, f = 1 MHz;
Test Circuit 8
C
S
(OFF) 9 9 pF typ f = 1 MHz
C
D
(OFF) 9 9 pF typ f = 1 MHz
C
D
, C
S
(ON) 35 35 pF typ f = 1 MHz
POWER REQUIREMENTS
V
DD
4.5/5.5 4.5/5.5 V min/max
I
DD
0.0001 0.0001 µA typ V
DD
= 5.5 V
11µA max Digital Inputs = 0 V or 5 V
NOTES
1
Temperature ranges are as follows: B Versions –40°C to +85°C; T Version –55°C to +125°C.
2
Guaranteed by design, not subject to production test.
Specifications subject to change without notice.
(V
DD
= 5 V 10%, V
SS
= 0 V, GND = 0 V, unless otherwise noted)
ADG511/ADG512/ADG513
REV. C –3–
Single Supply
B Version
0C to
Parameter 25C70C Unit Test Conditions/Comments
ANALOG SWITCH
Analog Signal Range 0 V to V
DD
V
R
ON
200 Ω typ V
D
= 1.5 V, I
S
= –1 mA;
500 Ω max V
DD
= 3 V
LEAKAGE CURRENTS V
DD
= 3.6 V
Source OFF Leakage I
S
(OFF) ±0.025 nA typ V
D
= 2.6/1 V, V
S
= 1Ⲑ2.6 V;
±0.1 ±2.5 nA max Test Circuit 2
Drain OFF Leakage I
D
(OFF) ±0.025 nA typ V
D
= 2.6/1 V, V
S
= 1Ⲑ2.6 V;
±0.1 ±2.5 nA max Test Circuit 2
Channel ON Leakage I
D
, I
S
(ON) ±0.05 nA typ V
D
= V
S
= 2.6 V/1 V;
±0.2 ±5 nA max Test Circuit 3
DIGITAL INPUTS
Input High Voltage, V
INH
2.4 V min
Input Low Voltage, V
INL
0.8 V max
Input Current
I
INL
or I
INH
0.005 µA typ V
IN
= V
INL
or V
INH
±0.1 µA max
DYNAMIC CHARACTERISTICS
2
t
ON
600 ns typ R
L
= 300 Ω, C
L
= 35 pF;
1200 ns max V
S
= 1 V; Test Circuit 4
t
OFF
100 ns typ R
L
= 300 Ω, C
L
= 35 pF;
160 ns max V
S
= 1 V; Test Circuit 4
Break-Before-Make Time 500 ns typ R
L
= 300 Ω, C
L
= 35 pF;
Delay, t
D
(ADG513 Only) V
S1
= V
S2
= 1 V; Test Circuit 5
Charge Injection 11 pC typ V
S
= 0 V, R
S
= 0 Ω, C
L
= 10 nF;
Test Circuit 6
OFF Isolation 68 dB typ R
L
= 50 Ω, C
L
= 5 pF, f = 1 MHz;
Test Circuit 7
Channel-to-Channel Crosstalk 85 dB typ R
L
= 50 Ω, C
L
= 5 pF, f = 1 MHz;
Test Circuit 8
C
S
(OFF) 9 pF typ f = 1 MHz
C
D
(OFF) 9 pF typ f = 1 MHz
C
D
, C
S
(ON) 35 pF typ f = 1 MHz
POWER REQUIREMENTS
V
DD
3/3.6 V min/max
I
DD
0.0001 µA typ V
DD
= 3.6 V
1µA max Digital Inputs = 0 V or 3 V
NOTES
1
Temperature range is as follows: B Version –40°C to +85°C.
2
Guaranteed by design, not subject to production test.
Specifications subject to change without notice.
REV. C
–4–
ADG511/ADG512/ADG513–SPECIFICATIONS
1
(V
DD
= 3.3 V 10%, V
SS
= 0 V, GND = 0 V, unless otherwise noted)
ADG511/ADG512/ADG513
REV. C –5–
ABSOLUTE MAXIMUM RATINGS
1
(T
A
= +25°C unless otherwise noted)
V
DD
to V
SS
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 V
V
DD
to GND . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +25 V
V
SS
to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . +0.3 V to –25 V
Analog, Digital Inputs
2
. . . . . . . . . . V
SS
– 2 V to V
DD
+ 2 V or
30 mA, Whichever Occurs First
Continuous Current, S or D . . . . . . . . . . . . . . . . . . . . . 30 mA
Peak Current, S or D . . . . . . . . . . . . . . . . . . . . . . . . . . 100 mA
(Pulsed at 1 ms, 10% Duty Cycle max)
Operating Temperature Range
Industrial (B Version) . . . . . . . . . . . . . . . . . –40°C to +85°C
Extended (T Version) . . . . . . . . . . . . . . . . –55°C to +125°C
Storage Temperature Range . . . . . . . . . . . . . –65°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C
Cerdip Package, Power Dissipation . . . . . . . . . . . . . . . 900 mW
θ
JA
Thermal Impedance . . . . . . . . . . . . . . . . . . . . . . 76°C/W
Lead Temperature, Soldering (10 sec) . . . . . . . . . . . . 300°C
Plastic Package, Power Dissipation . . . . . . . . . . . . . . . 470 mW
θ
JA
Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 117°C/W
Lead Temperature, Soldering (10 sec) . . . . . . . . . . . . 260°C
SOIC Package, Power Dissipation . . . . . . . . . . . . . . . . 600 mW
θ
JA
Thermal Impedance . . . . . . . . . . . . . . . . . . . . . . 77°C/W
Lead Temperature, Soldering
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . 215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . 220°C
NOTES
1
Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability. Only one absolute
maximum rating may be applied at any one time.
2
Overvoltages at IN, S or D will be clamped by internal diodes. Current should be
limited to the maximum ratings given.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the ADG511/ADG512/ADG513 features proprietary ESD protection circuitry,
permanent damage may occur on devices subjected to high-energy electrostatic discharges.
Therefore, proper ESD precautions are recommended to avoid performance degradation or loss
of functionality.
ORDERING GUIDE
Model
1
Temperature Range
2
Package Option
3
ADG511BN –40°C to +85°C N-16
ADG511BR –40°C to +85°C R-16A
ADG511ABR
4
–40°C to +85°C R-16A
ADG511TQ
4
–55°C to +125°C Q-16
ADG512BN –40°C to +85°C N-16
ADG512BR –40°C to +85°C R-16A
ADG512ABR
4
–40°C to +85°C R-16A
ADG513BN –40°C to +85°C N-16
ADG513BR –40°C to +85°C R-16A
ADG513ABR
4
–40°C to +85°C R-16A
NOTES
1
For availability of MIL-STD-883, Class B processed parts, contact factory.
2
3.3 V specifications apply over 0°C to 70°C temperature range.
3
N = Plastic DIP; R = 0.15" Small Outline IC (SOIC); Q = Cerdip.
4
Trench isolated latch-up proof parts. See Trench Isolation section.
WARNING!
ESD SENSITIVE DEVICE
ADG511/ADG512/ADG513
REV. C
–6–
PIN CONFIGURATION
(DIP/SOIC)
TOP VIEW
(Not to Scale)
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
IN1
D1
S1
V
SS
GND
S4
D4
IN4
IN2
D2
S2
V
DD
NC
S3
D3
IN3
ADG511
ADG512
ADG513
NC = NO CONNECT
Truth Table (ADG511/ADG512)
ADG511 ADG512 Switch
In In Condition
01 ON
1 0 OFF
Truth Table (ADG513)
Switch Switch
Logic 1, 4 2, 3
0 OFF ON
1 ON OFF
TERMINOLOGY
V
DD
Most Positive Power Supply Potential.
V
SS
Most Negative Power Supply Potential in
dual supplies. In single supply applications,
it may be connected to GND.
GND Ground (0 V) Reference.
S Source Terminal. May be an input or output.
D Drain Terminal. May be an input or output.
IN Logic Control Input.
R
ON
Ohmic Resistance between D and S.
I
S
(OFF) Source Leakage Current with the switch
“OFF.”
I
D
(OFF) Drain Leakage Current with the switch
“OFF.”
I
D
, I
S
(ON) Channel Leakage Current with the switch
“ON.”
V
D
(V
S
) Analog Voltage on terminals D, S.
C
S
(OFF) “OFF” Switch Source Capacitance.
C
D
(OFF) “OFF” Switch Drain Capacitance.
C
D
, C
S
(ON) “ON” Switch Capacitance.
t
ON
Delay between applying the digital control
input and the output switching on.
t
OFF
Delay between applying the digital control
input and the output switching off.
t
D
“OFF” or “ON” time measured between the
90% points of both switches when switching
from one address state to another.
Crosstalk A measure of unwanted signal which is
coupled through from one channel to
another as a result of parasitic capacitance.
Off Isolation A measure of unwanted signal coupling
through an “OFF” switch.
Charge Injection A measure of the glitch impulse transferred
from the digital input to the analog output
during switching.
V
D
OR V
S
– DRAIN OR SOURCE VOLTAGE – V
50
40
0
–5 5–4
R
ON
–
–3 –2 –1 01234
30
20
10
T
A
= 25C
V
DD
= +3V
V
SS
= –3V
V
DD
= +5V
V
SS
= –5V
TPC 1. On Resistance as a Function of V
D
(V
S
) Dual
Supplies
VD OR VS – DRAIN OR SOURCE VOLTAGE – V
50
40
0
–55–4
RON –
–3–2–101234
30
20
10
VDD = +5V
VSS = –5V
125C
85C
25C
TPC 2. On Resistance as a Function of V
D
(V
S
) for
Different Temperatures
V
D
OR V
S
– DRAIN OR SOURCE VOLTAGE – V
90
80
20051
R
ON
–
234
60
50
40
30
70
T
A
= 25C
V
DD
= 3V
V
SS
= 0V
V
DD
= 5V
V
SS
= 0V
TPC 3. On Resistance as a Function of V
D
(V
S
)
Single Supply
Typical Performance Characteristics–ADG511/ADG512/ADG513
REV. C –7–
FREQUENCY – Hz
10mA
10A
10nA
10M10
ISUPPLY
100 1k 10k 100k 1M
1mA
100A
1A
100nA
VDD = +5V
VSS = –5V
I–, I+
1 SW
4 SW
TPC 4. Supply Current vs. Input Switching Frequency
TEMPERATURE – C
10
1
0.001
25 12535
LEAKAGE CURRENT – nA
45 55 65 75 85 95 105 115
0.1
0.01
VDD = +5V
VSS = –5V
VS = 5V
VD = 5V ID (OFF)
ID (ON)
IS (OFF)
TPC 5. Leakage Currents as a Function of Temperature
FREQUENCY – Hz
120
100
40
100 10M1k
OFF ISOLATION – dB
10k 100k 1M
80
60
VDD = +5V
VSS = –5V
TPC 6. Off Isolation vs. Frequency
ADG511/ADG512/ADG513
REV. C
–8–
V
D
OR V
S
– DRAIN OR SOURCE VOLTAGE – V
0.006
0.000
–0.006
–5
LEAKAGE CURRENT – nA
0.004
0.002
–0.002
–0.004
V
DD
= +5V
V
SS
= –5V
T
A
= +25C
I
D
(OFF)
I
D
(ON)
I
S
(OFF)
–4–3–2–10 1234 5
TPC 7. Leakage Currents as a Function of V
D
(V
S
)
FREQUENCY – Hz
110
100
60
100 10M1k
CROSSTALK – dB
10k 100k 1M
90
80
70
VDD = +5V
VSS = –5V
TPC 8. Crosstalk vs. Frequency
APPLICATION
Figure 1 illustrates a precise sample-and-hold circuit. An AD845
is used as the input buffer while the output operational ampli-
fier is an OP07. During the track mode, SW1 is closed and the
output V
OUT
follows the input signal V
IN
. In the hold mode,
SW1 is opened and the signal is held by the hold capacitor C
H
.
Due to switch and capacitor leakage, the voltage on the hold
capacitor will decrease with time. The ADG511/ADG512/
ADG513 minimizes this droop due to its low leakage specifica-
tions. The droop rate is further minimized by the use of a poly-
styrene hold capacitor. The droop rate for the circuit shown is
typically 15 µV/µs.
A second switch, SW2, which operates in parallel with SW1, is
included in this circuit to reduce pedestal error. Since both
switches will be at the same potential, they will have a differen-
tial effect on the op amp OP07, which will minimize charge
injection effects. Pedestal error is also reduced by the compensation
network R
C
and C
C
. This compensation network also reduces
the hold time glitch while optimizing the acquisition time. Using
the illustrated op amps and component values, the pedestal
error has a maximum value of 5 mV over the ±3 V input range.
The acquisition time is 2.5 µs while the settling time is 1.85 µs.
+5V
–5V
2200pF
RC
75
CC
1000pF
CH
2200pF
VOUT
ADG511/
ADG512/
ADG513
SW1
SW2
S
S
D
D
+5V
–5V
AD845
+5V
–5V
VIN
OP07
Figure 1. Accurate Sample-and-Hold
TRENCH ISOLATION
The MOS devices that make up the ADG511A/ADG512A/
ADG513A are isolated from each other by an oxide layer
(trench) (see Figure 2). When the NMOS and PMOS devices
are not electrically isolated from each other, there exists the
possibility of “latch-up” caused by parasitic junctions between
CMOS transistors. Latch-up is caused when P-N junctions that
are normally reverse biased, become forward biased, causing
large currents to flow. This can be destructive.
CMOS devices are normally isolated from each other by Junction
Isolation. In Junction Isolation the N and P wells of the CMOS
transistors form a diode that is reverse biased under normal
operation. However, during overvoltage conditions, this diode
becomes forward biased. A Silicon-Controlled Rectifier (SCR)-
type circuit is formed by the two transistors, causing a signifi-
cant amplification of the current that, in turn, leads to latch-up.
With Trench Isolation, this diode is removed; the result is a
latch-up-proof circuit.
BURIED OXIDE LAYER
SUBSTRATE (BACKGATE)
T
R
E
N
C
H
T
R
E
N
C
H
T
R
E
N
C
H
P
+
P
+
P-CHANNEL
N
+
N
+
N-CHANNEL
P
–
N
–
V
G
V
D
V
S
V
G
V
D
V
S
Figure 2. Trench Isolation
ADG511/ADG512/ADG513
REV. C –9–
I
DS
V1
SD
V
S
R
ON
= V1/I
DS
Test Circuit 1. On Resistance
SD
V
S
A
V
D
A
I
S
(OFF) I
D
(OFF)
Test Circuit 2. Off Leakage
SD
VSVD
A
ID (ON)
Test Circuit 3. On Leakage
SD
V
DD
0.1F
V
DD
IN
V
S
GND V
SS
R
L
300
C
L
35pF
V
OUT
0.1F
V
SS
t
ON
t
OFF
3V
50% 50%
50% 50%
3V
90% 90%
V
IN
V
IN
V
OUT
ADG511
ADG512
Test Circuit 4. Switching Times
S1 D1
0.1F
VDD
IN1, IN2
VS1
GND VSS
RL1
300
CL1
35pF
VOUT1
0.1F
VS2
VOUT2
RL2
300
CL2
35pF
S2
VIN
D2
VDD
VSS
tDtD
3V
50% 50%
90%
VIN
VOUT1
VOUT2
90%
90%
90%
0V
0V
0V
Test Circuit 5. Break-Before-Make Time Delay
SD
VDD
IN
VS
GND VSS
CL
10nF
VOUT
RS
VSS
VDD
3V
VIN
VOUT VOUT
QINJ = CL VOUT
Test Circuit 6. Charge Injection
Test Circuits
ADG511/ADG512/ADG513
REV. C
–10–
SD
0.1F
VDD
IN
VS
GND VSS
RL
50
VOUT
0.1F
VIN
VSS
VDD
Test Circuit 7. Off Isolation
SD
0.1F
VDD
VS
GND VSS
50
NC
0.1F
VIN1
VIN2
SD
RL
50
VOUT
CHANNEL-TO-CHANNEL
CROSSTALK = 20 LOG VS/VOUT
VDD
VSS
Test Circuit 8. Channel-to-Channel Crosstalk
ADG511/ADG512/ADG513
REV. C –11–
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
16-Lead Plastic DIP
(N-16)
16
18
9
0.840 (21.34)
0.745 (18.92)
0.280 (7.11)
0.240 (6.10)
PIN 1
SEATING
PLANE
0.022 (0.558)
0.014 (0.356)
0.060 (1.52)
0.015 (0.38)
0.210 (5.33)
MAX 0.130
(3.30)
MIN
0.070 (1.77)
0.045 (1.15)
0.100
(2.54)
BSC
0.160 (4.06)
0.115 (2.93)
0.325 (8.26)
0.300 (7.62)
0.015 (0.381)
0.008 (0.204)
0.195 (4.95)
0.115 (2.93)
16-Lead Cerdip
(Q-16)
16
18
9
0.310 (7.87)
0.220 (5.59)
PIN 1
0.005 (0.13) MIN 0.080 (2.03) MAX
SEATING
PLANE
0.023 (0.58)
0.014 (0.36)
0.200 (5.08)
MAX
0.840 (21.34) MAX
0.150
(3.81)
MIN
0.070 (1.78)
0.030 (0.76)
0.200 (5.08)
0.125 (3.18)
0.100
(2.54)
BSC
0.060 (1.52)
0.015 (0.38)
15°
0°
0.320 (8.13)
0.290 (7.37)
0.015 (0.38)
0.008 (0.20)
16-Lead SOIC
(R-16A)
16 9
81
0.3937 (10.00)
0.3859 (9.80)
0.2440 (6.20)
0.2284 (5.80)
0.1574 (4.00)
0.1497 (3.80)
PIN 1
SEATING
PLANE
0.0098 (0.25)
0.0040 (0.10)
0.0192 (0.49)
0.0138 (0.35)
0.0688 (1.75)
0.0532 (1.35)
0.0500
(1.27)
BSC
0.0099 (0.25)
0.0075 (0.19)
0.0500 (1.27)
0.0160 (0.41)
8
0
0.0196 (0.50)
0.0099 (0.25) x 45
C00036b–0–5/01(C)
PRINTED IN U.S.A.
–12–
ADG511/ADG512/ADG513
–Revision History
REV. C
Location Page
Data Sheet changed from REV. B to REV. C.
Changes to Specifications table, Dual Supply, and Notes: “T Versions” made singular . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Changes to Specifications table, Single Supply, and Notes: “T Versions” made singular . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Change to Ordering Guide: Removed one line . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
