FDB3632_F085 - Fairchild Semiconductor

FDB3632_F085

N-Channel PowerTrench® MOSFET

100V, 80A, 9mΩ

Features

•r

DS(ON) = 7.5mΩ (Typ.), VGS = 10 V, I D = 80A

•Q

g(tot ) = 84nC (Typ .), VGS = 10V

• Low Miller Charge

•Low Q

RR Body Diode

• UIS Capability (Single Pulse and Repetitive Pulse)

• Qualified to AEC Q101

Applications

• DC/DC converters and Off-Line UPS

• Dist ributed Power Ar chitectures and VRMs

• Primary Switch for 24V and 48V Systems

• High Volt age Synch ronous Recti fier

• Direct Injection / Diesel Injection Systems

• 42V Automot ive Load Control

• Electronic Val v e Train Systems

MOSFET Maximum R at ings TC = 25°C unless ot herwise noted

Thermal Chara cteristics

Thi s produ ct has bee n desi gned to mee t the ex treme te st condi ti ons an d environme nt de mande d by the au tomot ive indust ry. For a

copy of the requirements, see AEC Q101 at: http://www.aecouncil.com/

Reliability data can be found at: http://www.fairchildsemi.co m/products/discrete/reliability/index.html.

All Fairchild Semiconductor produc ts are ma nufactured, a ssembled and teste d under ISO9000 and QS9000 quality systems

certification.

Symbol Parameter Ratings Units

VDSS Drain to Source Voltage 100 V

VGS Gate to Sourc e Volta ge ±20 V

ID

Drain Cur re nt 80 A

Continuous (TC < 111oC, VGS = 10V)

Continuous (Tamb = 25oC, VGS = 10V, RθJA = 43oC/W) 12 A

Pulsed Figure 4 A

EAS Single Pulse A v alanche Energy (Note 1) 338 mJ

PDPower dissipation 310 W

Derate above 25oC2.07W/

oC

TJ, TSTG Operating an d Storage Tempe rature -55 to +175 oC

RθJC Thermal Resistance J unction to Case TO-220, TO-263, TO-26 2 0.48 oC/W

RθJA Thermal Resistance Junction to Ambient TO -2 20, TO-262 (Note 2) 62 oC/W

RθJA Thermal Re sistan ce Junction t o Ambient TO-2 63, 1i n2 co pp er pad ar ea 43 oC/W

S

G

D

TO-263AB

FDB SERIES

GATE

SOURCE

DRAIN

(FLANGE)

March 2012

• RoHS Compliant

Package Marking and Order ing Information

Electrical Characteristics TC = 25°C unless ot herwise note d

Off Characteri stics

On Characteristics

Dynamic Characteristic s

Resistive Switching Characteristics (VGS = 10V)

Drain-Source Diode Character istics

Notes:

1: Starting TJ = 25°C, L = 0.12mH, IAS = 75A.

2: Pulse Width = 100s

Device Marking Device Package Reel Size Tape Width Quantity

FDB3632 FDB3632_F085 TO-263AB 330mm 24mm 800 units

Symbo l Parame ter Te st Cond itions Min Typ Max Unit s

BVDSS Drain to Source Breakdown Voltage ID = 250µA, VGS = 0V 100 - - V

IDSS Zero Gate Voltage Drain Current VDS = 8 0V - - 1 µA

VGS = 0V TC= 150oC- - 250

IGSS Gate to Source Leakage Current VGS = ±20V - - ±100 nA

VGS(TH) Gate to Source Threshold Voltage VGS = VDS, ID = 250µA2-4V

rDS(ON) Drain to Source On Resistance ID=80A, V GS=10V - 0.0075 0.009 Ω

ID=80A, VGS=10V, TC=175oC - 0.018 0.022

CISS Input Capacitance VDS = 25V, VGS = 0V,

f = 1MHz

-6000- pF

COSS Output Capacitance - 820 - pF

CRSS Rever se Tra nsfer Capacitance - 200 - pF

Qg(TOT) Total G ate Ch arg e at 10 V VGS = 0V to 10V

VDD = 50V

ID = 80A

Ig = 1.0mA

-84110nC

Qg(TH) Threshold Gate Charge VGS = 0V to 2V - 11 14 nC

Qgs Gate to Source Gate Charge - 30 - nC

Qgs2 Gate Charge Threshold to Plateau - 20 - nC

Qgd Gate to Drain “Miller” Charge - 20 - nC

tON Turn-On Time

VDD = 50V, ID = 80A

VGS = 10 V, RGS = 3.6Ω

--102ns

td(ON) Turn-On Delay Time - 30 - ns

trRise Time - 39 - ns

td(OFF) Turn-Off Delay Time - 96 - ns

tfFall Time - 46 - ns

tOFF Turn-Off Time - - 213 ns

VSD Source to Drain Diode Voltage ISD = 80A - - 1.25 V

ISD = 40A - - 1.0 V

trr Rev erse Recovery Time ISD = 75A, dISD/dt= 100A/µs- - 64ns

QRR Reve rse Recove red Char ge ISD = 75 A, dISD/dt= 100A/µs - - 120 nC

FDB3632_F085

Typical Characteristics TA = 25°C unless otherwise noted

Figure 1. Normalized Power Dissipation vs

Ambient Temperature Figure 2. Maximum Continuous Drai n Current vs

Case Temperature

Figure 3. Normalized Maximum Transient Thermal Impedance

Figure 4. Peak Current Capability

TC, CASE TEMPERATURE (oC)

POWER DISSIPATION MULTIPLIER

00255075100 175

0.2

0.4

0.6

0.8

1.0

1.2

125 150 0

25

50

75

100

125

25 50 75 100 125 150 175

ID, DRAIN CURRENT (A)

TC, CASE TEMPERATURE (oC)

VGS = 10V

CURRENT LIMITED

BY PACKAGE

0.01

0.1

1

10-5 10-4 10-3 10-2 10-1 100101

2

t, RECTANGULAR PULSE DURATION (s)

ZθJC, NORMALIZ ED

THERMAL IMPEDANCE

NOTES:

DUTY FACTOR: D = t1/t2

PEAK TJ = PDM x ZθJC x RθJC + TC

PDM

t1t2

0.5

0.2

0.1

0.05

0.01

0.02

DUTY CYCLE - DESCENDING ORDER

SINGLE PULSE

100

1000

10-5 10-4 10-3 10-2 10-1 100101

50

2000

IDM, PEAK CURRENT (A)

t, PULSE WIDTH (s)

TRANSCONDUCTANCE

MAY LIMIT CURRENT

IN THIS REGION

VGS = 10V

TC = 25oC

I = I25 175 - TC

150

FOR TEMPERATURES

ABOVE 25oC DERATE PEAK

CURRENT AS FOLLOWS:

FDB3632_F085

Figure 5. Forward Bias Safe Operating Area NOTE: Refer to Fairchild Application Notes AN7514 and AN7515

Figure 6. Unclamped Inductive Switching

Capability

Figure 7. Transfer Characteristics Figure 8. Saturation Characteristics

Figure 9. Drain to Source On Resistance vs Drain

Current Figure 10. Normalized Drain to Source On

Resistance vs Junction Temper ature

Typical Characteristics TA = 25°C unless otherwise noted

0.1

1

10

100

110100

200

400

ID, DRAIN CURRENT (A)

VDS, DRAIN TO SOURCE VOLTAGE (V)

TJ = MAX RATED

TC = 25oC

SINGLE PULSE

LIMITED BY rDS(ON)

AREA MAY BE

OPERATION IN THIS

10µs

10ms

1ms

DC

100µs

10

100

0.1 1 10

200

0.01

IAS, AVALANCHE CURRENT (A)

tAV, TIME IN AVALANCHE (ms)

STARTING TJ = 25oC

STARTING TJ = 150oC

tAV = (L)(IAS)/(1.3*RATED BVDSS - VDD)

If R = 0

If R ≠ 0

tAV = (L/R)ln[(IAS*R)/(1.3*RATED BVDSS - VDD) +1]

0

30

60

90

120

150

3.0 3.5 4.0 4.5 5.0 5.5 6.0

ID, DRAIN CURRENT (A)

VGS, GATE TO SOURCE VOLTAGE (V)

PULSE DURATION = 80µs

DUTY CYCLE = 0.5% MAX

VDD = 15V

TJ = 175oC

TJ = 25oC

TJ = -55oC

0

30

60

90

120

150

01234

ID, DRAIN CURRENT (A)

VDS, DRAIN TO SOURCE VOLTAGE (V)

VGS = 5.5V

PULSE DURATION = 80µs

DUTY CYCLE = 0.5% MAX

VGS = 5V

TC = 25oC

VGS = 10V VGS = 6V

6

7

8

9

10

0 20406280

ID, DRAIN CURRENT (A)

VGS = 10V

DRAIN TO SOURCE ON RESISTANCE (m Ω)

VGS = 6V

PULSE DURATION = 80µs

DUTY CYCLE = 0.5% MAX

0.5

1.0

1.5

2.0

2.5

-80 -40 0 40 80 120 160 200

NORMALIZED DRAIN TO SOURCE

TJ, JUNCTION TEMPERATURE (oC)

ON RESISTANCE

VGS = 10V, ID =80A

PULSE DURATION = 80µs

DUTY CYCLE = 0.5% MAX

FDB3632_F085

Figure 11. Normalized Gate Threshold Voltage vs

Junction Temperature Figure 12. Normalized Drain to Source

Breakdow n Voltage vs Junc tion Temperatu r e

Figure 13. Capacitance vs Drain to Source

Voltage Figure 14. Gate Charge Waveforms for Constant

Gate Currents

Typical Characteristics TA = 25°C unless otherwise noted

0.2

0.4

0.6

0.8

1.0

1.2

1.4

-80 -40 0 40 80 120 160 200

NORMALIZED GATE

TJ, JUNCTION TEMPERATURE (oC)

VGS = VDS, ID = 250µA

THRESHOLD VOLTAGE

0.9

1.0

1.1

1.2

-80 -40 0 40 80 120 160 200

TJ, JUNCTION TEMPERATURE (oC)

NORMALIZED DRAIN TO SOURCE

ID = 250µA

BREAKDO WN VOLTAGE

100

1000

10000

0.1 1 10 100

C, CAPACITANCE (pF)

VGS = 0V, f = 1MHz

CISS = CGS + CGD

COSS ≅ CDS + CGD

CRSS = CGD

VDS, DRAIN TO SOURCE VOLTAGE (V)

0

2

4

6

8

10

0 20406080100

VGS, GATE TO SOURCE VOLTAGE (V)

Qg, GATE CHARGE (nC)

VDD = 50V

ID = 80A

ID = 40A

WAVEFORMS IN

DESCENDING ORDER:

FDB3632_F085

Test Circuits and Waveforms

Figure 15. Unclamped Energy Test Circuit Figure 16. Unclamped Energy Waveforms

Figure 17. Gate Charge Test Circuit Figure 18. Gate Charge Waveforms

Figure 19. Switching Time Test Circuit Figure 20. Switching Time Waveforms

tP

VGS

0.01Ω

L

IAS

+

-

VDS

VDD

RG

DUT

VARY tP TO OBTAIN

REQUIRED PEAK IAS

0V

VDD

VDS

BVDSS

tP

IAS

tAV

0

VGS +

-

VDS

VDD

DUT

Ig(REF)

L

VDD

Qg(TH)

VGS = 2V

Qg(TOT)

VGS = 10V

VDS

VGS

Ig(REF)

0

Qgs Qgd

Qgs2

VGS

RL

RGS

DUT

+

-VDD

VDS

VGS

tON

td(ON)

tr

90%

10%

VDS 90%

10%

tf

td(OFF)

tOFF

90%

50%

10% PULSE WIDTH

VGS

0

FDB3632_F085

Thermal Resistance vs. Mounting Pad Area

The maximum rated junction temperature, TJM, and the

thermal resistance of the heat dissipating path determines

the maximum allowable device power dissipation, PDM, in an

application. Therefore the application’s ambient

temperature, TA (oC), and thermal resistance RθJA (oC/W)

must be reviewed to ensure that TJM is never exceeded.

Equation 1 mathematically represents the relationship and

serves as the basis for establishing the rating of the part.

In using surface mount devices such as the TO-263

package, the environment in which it is applied will have a

significant influence on the part’s current and maximum

power dissipation ratings. Precise determination of PDM is

complex and influenced by many factors:

1. Mounting pad area onto which the device is attached and

whether there is copper on one side or both sides of the

board.

2. The number of copper layers and the thickness of the

board.

3. The use of external heat sinks.

4. The use of thermal vias.

5. Air flow and board orientation.

6. For non steady state applications, the pulse width, the

duty cycle and the transient thermal response of the part,

the board and the environment they are in.

Fairchild provides thermal information to assist the

designer’s preliminary application evaluation. Figure 21

defines the RθJA for the device as a function of the top

copper (component side) area. This is for a horizontally

positioned FR-4 board with 1oz cop per after 1000 seconds

of steady state power with no air flow. This graph provides

the necessary information for calculation of the steady state

junction temperature or power dissipation. Pulse

applications can be evaluated using the Fairchild device

Spice thermal model or manually utilizing the normalized

maximum transient thermal impedance curve.

Thermal resistances corresponding to other copper areas

can be obtained from Figure 21 or by calculation using

Equation 2 or 3. Equation 2 is used for copper area defined

in inches square and equation 3 is for area in centimeters

square. The area, in square inches or square centimeters is

the top copper area including the gate and source pads.

(EQ. 1)

PDM

TJM TA

–()

RθJA

-----------------------------=

Area in Inches Squared

(EQ. 2)

RθJA 26.51 19.84

0.262 Area+()

-------------------------------------+=

(EQ. 3)

RθJA 26.51 128

1.69 Area+()

----------------------------------+=

Area in Centimeters Squared

Figure 21. Thermal Resistance vs Mounting

Pad Area

20

40

60

80

110

0.1

RθJA = 26.51+ 19.84/(0.262+Area) EQ.2

RθJA (oC/W)

AREA, TOP COPPER AREA in2 (cm2)

(0.645) (6.45) (64.5)

RθJA = 26.51+ 128/(1.69+Area) EQ.3

FDB3632_F085

PSPICE Electrical Model

.SUBCKT FDB3632 2 1 3 ; rev May 2002

CA 12 8 1.7e-9

Cb 15 14 2.5e-9

Cin 6 8 6.0e-9

Dbody 7 5 DbodyMOD

Dbreak 5 11 DbreakMOD

Dplcap 10 5 DplcapMOD

Ebreak 11 7 17 18 102.5

Eds 14 8 5 8 1

Egs 13 8 6 8 1

Esg 6 10 6 8 1

Evthres 6 21 19 8 1

Evtemp 20 6 18 22 1

It 8 17 1

Lgate 1 9 5.61e-9

Ldrain 2 5 1.0e-9

Lsource 3 7 2.7e-9

RLgate 1 9 56.1

RLdrain 2 5 10

RLsource 3 7 27

Mmed 16 6 8 8 MmedMOD

Mstro 16 6 8 8 MstroMOD

Mweak 16 21 8 8 MweakMOD

Rbreak 17 18 RbreakMOD 1

Rdrain 50 16 RdrainMOD 3.8 e-3

Rgate 9 20 1.1

RSLC1 5 51 RSLCMOD 1.0e-6

RSLC2 5 50 1.0e3

Rsource 8 7 RsourceMOD 2.5e-3

Rvthres 22 8 RvthresMOD 1

Rvtemp 18 19 RvtempMOD 1

S1a 6 12 13 8 S1AMOD

S1b 13 12 13 8 S1BMOD

S2a 6 15 14 13 S2AMOD

S2b 13 15 14 13 S2BMOD

Vbat 22 19 DC 1

ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*350),3))}

.MODEL DbodyMOD D (IS=5.9E-11 N=1.07 RS=2.3e-3 TRS1=3.0e-3 TRS2=1.0e-6

+ CJO=4e-9 M=0.58 TT=4.8e-8 XTI=4.2)

.MODEL DbreakMOD D (R S =0.17 TRS1=3.0e -3 TRS 2 =-8.9e-6)

.MODEL DplcapMOD D (CJO=15e-10 IS=1.0e-30 N=10 M=0.6)

.MODEL MstroMOD NMOS (VTO=4.1 KP=200 IS=1e-30 N=1 0 TOX=1 L=1u W=1u)

.MODEL MmedMOD NMOS (VTO=3.4 KP=10.0 IS=1e-30 N=10 TOX=1 L=1u W=1u RG=1.1)

.MODEL MweakMOD NMOS (VTO=2.75 KP=0. 05 IS =1e-30 N=10 TOX=1 L=1u W=1u RG=1.1e+1 RS =0 .1)

.MODEL RbreakMOD RES (TC1=1.0e-3 TC2=-1.7e-6)

.MODEL RdrainMOD RES (TC1=8.5e-3 TC2=2.8e-5)

.MODEL RSLCMOD RES (TC1=2.0e-3 TC 2=2.0e- 6)

.MODEL RsourceMOD RES (TC1=4e-3 TC2=1e-6)

.MODEL RvthresMOD RES (TC1=-4.0e-3 TC2=- 1.8e-5)

.MODEL RvtempMOD RE S (TC1=-4.4e-3 TC2=2.2e-6)

.MODEL S1AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-4 VOFF=-2)

.MODEL S1BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-2 VOFF=-4)

.MODEL S2AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-0.8 VOFF=0.4)

.MODEL S2BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=0.4 VOFF=-0.8)

.ENDS

Note: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global

Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank

Wheatley.

18

22

+-

6

8

+

-

5

51

+

-

19

8

+-

17

18

6

8

+

-

5

8+

-

RBREAK

RVTEMP

VBAT

RVTHRES

IT

17 18

19

22

12

13

15

S1A

S1B

S2A

S2B

CA CB

EGS EDS

14

8

13

814

13

MWEAK

EBREAK DBODY

RSOURCE

SOURCE

11

73

LSOURCE

RLSOURCE

CIN

RDRAIN

EVTHRES 16

21

8

MMED

MSTRO

DRAIN

2

LDRAIN

RLDRAIN

DBREAK

DPLCAP

ESLC

RSLC1

10

5

51

50

RSLC2

1

GATE RGATE EVTEMP

9

ESG

LGATE

RLGATE 20

+

-

+

-

+

-

6

FDB3632_F085

SABER Electrical Model

REV May 2002

template FDB3632 n2,n1,n3

electrical n2,n1,n3

{

var i iscl

dp..model dbodymod = (isl=5.9e-11,n l=1.07,rs=2.3e-3,trs1=3.0e-3,trs2=1.0e-6,cjo=4e-9,m=0.58,tt=4.8e-8,xti=4.2)

dp..model dbreakmod = (rs=0. 17,trs1=3.0e-3,trs2=-8.9e-6)

dp..model dplcapmod = (cjo=1 5e- 10,isl=10.0e-30,nl=10,m=0.6)

m..model mstrongmod = (type=_n,vto=4.1,kp=200,is=1e-30 , tox=1)

m..model mmedmod = (type=_n,vto=3.4,kp=10.0,is=1e-30, tox=1)

m..model mweak mod = (type=_n,vto=2.75,kp=0.05,is=1e-30, tox=1,rs=0.1)

sw_vcsp..model s1a m od = (ron=1e-5,roff=0.1,von=-4,voff=-2)

sw_vcsp..model s1b m od = (ron=1e-5,roff=0.1,von=-2,voff=-4)

sw_vcsp..model s2a m od = (ron=1e-5,roff=0.1,von=-0.8,voff=0.4)

sw_vcsp..model s2b m od = (ron=1e-5,roff=0.1,von=0.4,voff=-0.8)

c.ca n12 n8 = 1.7e-9

c.cb n15 n14 = 2.5e-9

c.cin n6 n8 = 6.0e-9

dp.dbody n7 n5 = model=db odymod

dp.dbreak n5 n11 = model=dbreakm od

dp.dplcap n10 n5 = m odel=dplcapmod

spe.ebreak n11 n7 n17 n18 = 102.5

spe.eds n14 n8 n5 n8 = 1

spe.egs n13 n8 n6 n8 = 1

spe.esg n6 n10 n6 n8 = 1

spe.evthres n6 n21 n19 n8 = 1

spe.evtemp n20 n6 n18 n22 = 1

i.it n8 n17 = 1

l.lgate n1 n9 = 5.61e-9

l.ldrain n2 n5 = 1.0e-9

l.lsource n3 n7 = 2.7e-9

res.rlgate n1 n9 = 56.1

res.rldrain n2 n5 = 10

res.rlsource n3 n7 = 27

m.mmed n16 n6 n8 n8 = model=mmedmod, l=1u, w=1u

m.mstrong n16 n6 n8 n8 = model=mstr ongmod, l=1u, w=1u

m.mweak n16 n21 n8 n8 = model=mweakmod, l=1u, w=1u

res.rbreak n17 n18 = 1, tc1=1.0e-3,tc2=-1.7e-6

res.rdrain n50 n16 = 3.8e-3, tc1=8.5e-3 ,tc2=2.8e-5

res.rg ate n9 n20 = 1.1

res.rslc1 n5 n51 = 1.0e-6, tc 1=2.0e-3,tc2=2.0e-6

res.rs lc2 n5 n50 = 1.0e3

res.rsource n8 n7 = 2.5e-3, tc1=4e- 3,tc 2=1e-6

res.rvthres n22 n8 = 1, tc1=-4.0e-3,tc2=-1.8e-5

res.rvtemp n18 n19 = 1, tc1=-4.4e -3,tc2=2.2e -6

sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod

sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod

sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod

sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod

v.vbat n22 n19 = dc=1

equations {

i (n51->n50) +=iscl

iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6/350))** 3))

}

18

22

+-

6

8

+

-

19

8

+-

17

18

6

8

+

-

5

8+

-

RBREAK

RVTEMP

VBAT

RVTHRES

IT

17 18

19

22

12

13

15

S1A

S1B

S2A

S2B

CA CB

EGS EDS

14

8

13

814

13

MWEAK

EBREAK

DBODY

RSOURCE

SOURCE

11

73

LSOURCE

RLSOURCE

CIN

RDRAIN

EVTHRES 16

21

8

MMED

MSTRO

DRAIN

2

LDRAIN

RLDRAIN

DBREAK

DPLCAP

ISCL

RSLC1

10

5

51

50

RSLC2

1

GATE RGATE EVTEMP

9

ESG

LGATE

RLGATE 20

+

-

+

-

+

-

6

FDB3632_F085

SPICE Thermal Model

REV May 2002

FDB3632

CTHERM1 TH 6 7.5e-3

CTHERM2 6 5 8.0e-3

CTHERM3 5 4 9.0e-3

CTHERM4 4 3 2.4e-2

CTHERM5 3 2 3.4e-2

CTHERM6 2 TL 6.5e-2

RTHERM1 TH 6 3.1e-4

RTHERM2 6 5 2.5e-3

RTHERM3 5 4 2.2e-2

RTHERM4 4 3 8.1e-2

RTHERM5 3 2 1.35e-1

RTHERM6 2 TL 1.5e-1

SABER Thermal Model

SABER thermal model FDB3632

templ a te thermal_ model th tl

thermal_c th, tl

{

ctherm.ctherm1 th 6 =7 .5e-3

ctherm.ctherm2 6 5 =8.0e-3

ctherm.ctherm3 5 4 =9.0e-3

ctherm.ctherm4 4 3 =2.4e-2

ctherm.ctherm5 3 2 =3.4e-2

ctherm.ctherm6 2 tl =6.5e-2

rtherm.rtherm1 th 6 =3.1e-4

rtherm. rtherm2 6 5 =2.5e-3

rtherm. rtherm3 5 4 =2.2e-2

rtherm. rtherm4 4 3 =8.1e-2

rtherm. rtherm5 3 2 =1.35e-1

rtherm.rtherm6 2 tl =1.5e-1

}

RTHERM4

RTHERM6

RTHERM5

RTHERM3

RTHERM2

RTHERM1

CTHERM4

CTHERM6

CTHERM5

CTHERM3

CTHERM2

CTHERM1

tl

2

3

4

5

6

th JUNCTION

CASE

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intended to be an exhaustive list of all such trademarks.

*Trademarks of System General Corporation, used under license by Fairchild Semiconductor.

DISCLAIMER

FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE

RELIABILITY, FUNCTION, OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY

PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.

THESE SPECIFICATIONS DO NOT EXPAND THE TERMS OF FAIRCHILD’S WORLDWIDE TERMS AN D CONDITIONS, SPECIFICALLY THE WARRANTY

THEREIN, WHICH COVERS THESE PRODUCTS.

LIFE SUPPORT POLICY

FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN L IFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE

EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION.

As used here in:

1. Life support devices or systems are devices or systems which, (a) are

intended for surgical impl ant into the body or (b) support or sustain life,

and (c) whose failure to perform when properly used in accordance with

instructions for use provided in the labeling, can be reasonably

expected to result in a significant injury of the user.

2. A critical component in any component of a life support, device, or

system whose failure to perform can be reasonably expected to cause

the failure of the life support device or system, or to affect its safety or

effectiveness.

PRODUCT STATUS DEFINITIONS

Definition of Terms

2Cool™

AccuPower™

Auto-SPM™

AX-CAP™*

BitSiC®

Build it Now™

CorePLUS™

CorePOWER™

CROSSVOLT™

CTL™

Current Transfer Logic™

DEUXPEED®

Dual Cool™

EcoSPARK®

EfficentMax™

ESBC™

Fairchild®

Fairchild Semiconductor®

FACT Quiet Series™

FACT®

FAST®

FastvCore™

FETBench™

FlashWriter® *

FPS™

F-PFS™

FRFET®

Global Power ResourceSM

GreenBridge™

Green FPS™

Green FPS™ e-Series™

Gmax™

GTO™

IntelliMAX™

ISOPLANAR™

Marking Small Speakers Sound Louder

and Better™

MegaBuck™

MICROCOUPLER™

MicroFET™

MicroPak™

MicroPak2™

MillerDrive™

MotionMax™

Motion-SPM™

mWSaver™

OptoHiT™

OPTOLOGIC®

OPTOPLANAR®

PowerTrench®

PowerXS™

Programmable Active Droop™

QFET®

QS™

Quiet Series™

RapidConfigure™

Saving our world, 1mW/W/kW at a time™

SignalWise™

SmartMax™

SMART START™

Solutions for Your Success™

SPM®

STEALTH™

SuperFET®

SuperSOT™-3

SuperSOT™-6

SuperSOT™-8

SupreMOS®

SyncFET™

Sync-Lock™®*

The Power Franchise®

®

TinyBoost™

TinyBuck™

TinyCalc™

TinyLogic®

TINYOPTO™

TinyPower™

TinyPWM™

TinyWire™

TranSiC®

TriFault Detect™

TRUECURRENT®*

μSerDes™

UHC®

Ultra FRFET™

UniFET™

VCX™

VisualMax™

VoltagePlus™

XS™

tm

®

™

tm

Datasheet Identification Product Status Definition

Advance Information Formative / In Design Datasheet contains the design specifications for product development. Specifications

may change in any manner without notice.

Preliminary First Production Datashee t contains preliminary data; supplementary data will be published at a later

date. Fairchild Semiconducto r reserves the right to make changes at any time without

notice to improve design.

No Identification Neede d Full Production Datasheet contains final specifications. Fairchild Semiconductor reser ves the right to

make changes at any time without notice to improve t he design.

Obsolete Not In Production Datasheet contains specifications on a pro duct that is discontinued by Fairchild

Semiconductor. The datasheet is for reference information only.

ANTI-COUNTERFEITING POLICY

Fairchild Semiconductor Corporation’s Anti-Counterfeiting Policy. Fairchild’s Anti-Counterfeiting Policy is also stated on our external website,

www.Fairchildsemi.com, under Sales Support.

Counterfeiti ng of semiconductor parts is a growing problem in the industry. All manufactures of semiconductor products a re experiencing counte rfeiting of their

parts. Customers who i nadvert ently p urchase count erfeit parts exper ience many problems su ch as l oss of bra nd reput ation , su bstan dard per fo rmance, f ailed

application, and increase d cost of production and manuf acturing delays. Fairchild is taking strong measures to protect ourselves and our customers from the

proliferation of coun terfeit parts. Fairchild strongly encoura ges customers to purchase Fairchild parts ei ther directl y from Fairchild or from Authorized Fairchild

Distributors who are listed by country on our web page cited above. Products customers buy either from Fairchild directly or from Authorized Fairchild

Distributors are genuine parts, have full traceability, meet Fairchild’s quality standards for handing and storage and provide access to Fairchild’s full range of

up-to-date technical and product information. Fairchild and our Authorized Distributors will stand behind all warranties and will appropriately address and

warranty issues that may arise. Fairchild wi ll not provide any warranty coverage or other assistance for parts bought from Unauthorized Sources. Fairchild is

committed to combat this global prob lem and encourage our customers to do their part in stopping th is practice by buying direct or from authorized dist ributors.

Rev. I60

tm

®

Mouser Electronics

Authorized Distributor

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