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IR3823

3A Highly Integrated SupIRBuck® Single-Input

Voltage, Synchronous Buck Regul at or

FEATURES

DESCRIPTION

• Single input voltage range from 5V to 21V

• Wide Input voltage range from 1.0V to 21V with

external VCC bias voltage

• Output voltag e from 0.6V to 0.86% of PVin

• Enhanced line/load regulation with feedforward

• Programmable switching frequency up to

1.5MHz

• Three user selectable soft-start time options

• Thermally compensated current lim i t with robust

hiccup mode over current protection

• Synchronization to an external clock

• Precise reference voltage (0.6V+/ -0.6%)

• Open-drain PGood indication

• Output over voltage protection

• Enable Input wit h Under-Voltage Loc kout

(UVLO)

• VCC Under-Voltage Lockout (UVLO)

• Enhanced Pre-bias start-up

• Integrated MOSF E T dri vers and Bootstrap

Diode

• Thermal shut-down

• -40°C to 125°C operating junction temperature

• 3.5mm x 3.5mm PQFN package

• Lead-free, Hal ogen-free and RoHS6 Compliant

The IR3823 SupIRBuck® is a 3A easy-to-use, fully

integrated and highly efficient synchronous Buck

regulator intended for Point-Of-

Load (POL)

applications.

The IR3823 features programmable switching

frequency from 300kHz to 1.5MHz, three selectable

soft-start time options

, and smooth synchronization to

an external clock. The IR3823 uses voltage mode

control employing a proprietary PWM modulator,

allowing high control bandwidth and fast loop response

with less output capacitors. The other important

functions include thermally compensated over current

protection, output over voltage protection and thermal

shut-

down, etc. The IR3823 is offered in a small

3.5mm x 3.5mm PQFN package with excellent thermal

performance.

APPLICATIONS

• Computing Applic ations

• Set Top Box Applicat i ons

• Storage Applications

• Data Center Applications

• Telecom Applicati ons

• Distributed Point of Load Power Arc hi tectures

ORDERING INFO RM ATION

Base Part Num ber Package Type

Standard Pack

Orderable Part Number

Form

Quantity

IR3823

PQFN 3.5 mm x 3.5 mm

Tape and Reel

4000

IR3823MTRPBF

IR3823      

PBF – Lead Free

TR – Tape and Reel

M – PQFN Package

IR3823

BASIC APPLICATION

Boot

Vcc

Comp

Gnd PGnd

PGood

Rt/Sync

PVinVin

Enable

IR3823

SS_Select

Vin

PGood

Figure 1: IR3823 Basic Application Circuit Figure 2: IR3823 Efficiency

PINOUT DIAGRAM

12 11 10

1 2 3 4 5 6

SS_Select

Comp

Gnd

Rt/Sync

PGood

Vin

Vcc/LDO_Out

Gnd

PGnd

PVin

Gnd

Boot GND

Enable

IR3823

Figure 3: 3.5mm x 3.5mm PQFN (Top View)

IR3823

BLOCK DIAGRA M

Rt/Sync

PGnd

Enable

VCC

TSD

HDin

UVcc

UVEN

HDrv

LDrv

Vin

SSOK

0.6V

VREF

SEQ

POR

UVcc

Gnd

Vin

SS_Select

Vcc/LDO_Out

5.1V

Internal LDO

UVcc

THERMAL

SHUT DOWN FAULT

CONTROL

+E/A

Comp

VREF +

CONTROL

LOGIC

0.15V

SOFT

START

UVEN

POR

OVER

VOLTAGE

FAULT

POR

VREF

INTL_SS

POR

GATE

DRIVE

PVin

LDin

Boot

VCCPOR

FAULT

Over Current

Protection

PGood

Figure 4: Simplified Block Diagram

IR3823

PIN DESCRIPTIONS

PIN # PIN NAME PIN DESCRIPTIO N

1 Fb Inverting input to the error amplifier. T his pin is connected directly to the output of the

regulator via resistor divider to set t he output voltage an d provide feedback to the err or

amplifier.

2 SS_Select

Soft start selection pin. Three user selec table soft start time is available: 1.5m s

(SS_Select=Vcc), 3ms (SS_Select=Float), 6ms (SS_Select=Gnd)

3 Comp

Output of the er r or amplifier. The loop compe nsation network should be connected

between Comp and Fb pin.

4,9,13, 16 Gnd Analog ground for the internal reference and the control circuitry.

5 Rt/Sync Multi-function pin to set the switching frequency. The interna l os cillator frequency is set

with a resistor between this pin and Gnd. Or synchronization to an external clock b y

connecting this pin to the external clock signal through a diode.

6 PGood Open-drain power good indication p in. Connect a pull-up resistor from this pin to Vcc.

7 Vin Input of t he Internal LDO. A 1.0µFceramic capacitor sho ul d be connected between this pin

and PGnd. If an external Vcc voltage is used , this pin shoul d be shorted to Vcc pin.

8 Vcc/LDO_Out

Output of the internal LDO and optional input of an external biased supply voltage. A

minimum 2.2µF ceramic cap ac i tor is recommended bet ween thi s pin and PGnd.

10 PGnd Power Ground. This pin serves as a separated ground for the MOSFET drivers an d

should be conn ec ted to the sys tem power ground plane.

11 SW Switch node. Connect this pi n to the output inductor.

12 PVin Power stage input.

14 Boot

Supply voltage for the high-side driver. A 100nF ceramic c apacitor should be connected

between this p in and SW pin.

15 Enable

Enable pin to t urn on/off the device. Connect this pin to PVin pin through a resistor divider

to implement the input volta ge UVLO.

IR3823

ABSOLUTE MAXI M UM RATINGS

Stresses beyond these listed under “Absolute Maximum Ratings” may cause permanent damage to the device.

These are stress ratings only and functional operation of the device at these or any other conditions beyond those

indicated in the ope rational sections of the specifications are not implied.

PVin, Vin to PGnd (Note 3) -0.3V to 25V

Vcc/LDO_Out to PGnd (Note 3) -0.3V to 8V (Note 1)

Boot to PGnd (Note 3) -0.3V to 33V

SW to PGnd (Note 3) -0.3V to 25V (DC), -4V to 25V (AC, 100ns)

Boot to SW -0.3V to VCC + 0.3V ( Note 2)

PGood, SS_Se l ec t to Gnd (Note 3) -0.3V to VCC + 0.3V ( Note 2)

Other Input/ Output Pins to Gnd (Note 3) -0.3V to +3.9V

PGnd to Gnd -0.3V to +0.3V

THERMAL INFORMATION

Junction to Ambient Ther m al Resistance ƟjA 37.4 °C/W (Note 4)

Junction to PCB Thermal Resistance Ɵj-PCB 10.1 °C/W

Junction to Case Top Thermal Resistance Ɵj-CTop 120 °C/W

Storage Temper ature Range

-55°C to 150°C

Junction Temperature Range

-40°C to 150°C

Note 1: Vcc must not exceed 7.5V for Junction Temperature between -10°C and -40°C

Note 2: Must not exceed 8V

Note 3: PGnd pin and Gnd pin are connected together.

Note 4: ƟjA is for the test in still air with IRDC3823 evaluation board. The IRDC3823 uses a 4-layer 2.6” x 2.2” FR4 PCB board. Each layer

uses 2 oz. copper.

IR3823

ELECTRICAL SPECIFICATIONS

RECOMMENDED OPE RAT IN G CONDITIONS

SYMBOL MIN MAX UNITS

Input Voltage Range with External Vcc (Note 5, Note 7) PVin 1.0 21

Input Voltage Range with Internal LDO (Note 6, Note 7) Vin, PVin 5.5 21

Supply Voltage Range (Note 6) VCC 4.5 7.5

Supply Voltage Range (Note 6) Boot to SW 4.5 7.5

Output Voltage Range V

0.6 0.86 x PV

Output Current Range I0 0 3 A

Switching Fr equency FS 300 1500 kHz

Operating Junction Temper ature TJ -40 125 °C

Note 5: Vin is connected to Vcc to bypass the internal LDO.

Note 6: Vin is connected to PVin. For single-rail applications with PVin=Vin= 4.5V-5.5V, please refer to the application information in the

section of Internal LDO and the section of Over Current Protection.

Note 7: Maximum SW node voltage should not exceed 25V.

ELECTRICAL CHARACTERISTICS

Unless otherwise specified, these specifications apply over, 5.5V < Vin = PVin < 21V, 0°C < TJ < 125°C, SS_Select=Float.

Typical values are specified at Ta = 25°C.

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

Power Stage

Power Losses PLOSS PVin= Vin = 12V, Vo = 1.2V,

Io = 3A, Fs = 1000kHz,

L = 1.0uH, Note 8 0.6 W

Top Switch RDS(ON) RDS(on)-T VBOOT -Vsw=5.1V,Io = 3A,

Tj = 25°C 40 52 mΩ

Bottom Switch RDS(ON) RDS(on)-B Vcc = 5.1V, Io = 3A, Tj = 25°C 26 34

Bootstrap Di ode Forward

Voltage

VD I(Boot) = 10mA 180 260 470 mV

SW Leakage Current ISW

= 0V, Enable = 0V,

VFB=1V

1 µA

= 0V, Enable = High,

VFB=1V

1 µA

Dead Band Time TD Note 8 12.5 ns

Supply Current

Vin Supply Cur rent (standby) Iin(Standby) EN = Low, No Switching

Vin=21V, PVin=0V 200 µA

Vin Supply Cur rent

(dynamic) Iin(Dyn) EN = High, FSW =1000kHz,

Vin = PVin = 16V 10 12.5 mA

IR3823

ELECTRICAL CHARACTERISTICS (CONTINUED)

Unless otherwise specified, these specifications apply over, 5.5V < Vin = PVin < 21V, 0°C < TJ < 125°C, SS_Select=Float.

Typical values are specified at Ta = 25°C.

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

VCC/LDO_Out

Output Voltage Vcc Vin(min) = 5.5V, Io = 0-25mA

CLOAD = 2.2uF 4.75 5.1 5.4 V

LDO Dropout Voltage Vcc_drop Vin=4.7V, Io=15mA,

CLOAD=2.2uF 0.4 V

Short Circuit Current Ishort Vin=7.3V, PV in=Float, Vcc=0V 70 mA

Oscillator

Rt Voltage VRt 1.0 V

Frequency Range Fs

Rt = 80.6kΩ 270 300 330

kHz

Rt = 23.2kΩ

900

1000

1100

Rt = 15kΩ 1350 1500 1650

Ramp Amplitude Vramp

Vin = 5.5V, Vin slew rate max

= 1V/µs, Not e 8 0.825

Vp-p

Vin = 12V, Vin slew rate max

= 1V/µs, Not e 8 1.80

Vin = 21V, Vin slew rate max

= 1V/µs, Note 8 3.15

Vin=Vcc=5V, For external Vcc

operation, N ote 8 0.75

Ramp Offset Note 8 0.16 V

Minimum Pulse Width Tmin(ctrl) Note 8 60 ns

Maximum Duty Cycle Dmax Fs = 300kHz, Vin =PVin= 12V 86 %

Fixed Off Time Toff Note 8 200 250 ns

Sync Fre quency Range Fsync 270 1650 kHz

Sync Pulse Duration Tsync 100 200 ns

Sync Level Threshold High 3.0 V

Low 0.6 V

Error Amplifier

Input Bias Current (VFB) IFB(E/A) -1 +1 µA

Output Sink Current Isink(E/A) 0.4 0.85 1.2 mA

Output Source Current Isource(E/A) 4 7.5 11 mA

Sl ew Rate SR Note 8 7 12 20 V/µs

Gain-Bandwidth Product GBWP Note 8 20 30 40 MHz

IR3823

ELECTRICAL CHARACTERISTI CS (CONTINUED)

Unless otherwise specified, these specifications apply over, 5.5V < Vin = PVin < 21V, 0°C < TJ < 125°C, SS_Select=Float.

Typical values are specified at Ta = 25°C.

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

Error Amplifier (Continued)

DC Gain Gain Note 8 100 110 120 dB

Maximum Output Voltage Vmax(E/A) 1.7 2.0 2.3 V

Minimum Outp ut Voltage Vmin(E/A) 100 mV

Reference Vol tage (VREF)

Feedback Voltage VFB 0.6 V

Accuracy 0°C < Tj < 70°C -0.6 +0.6 %

-40°C < Tj < 125°C ; Note 9 -1.2 +1.2

Soft Start

Soft Start R am p R ate

SS_Select=VCC 0.34 0.4 0.46

mV/µs

SS_Select=Float 0.16 0.2 0.24

SS_Select=Gnd 0.085 0.1 0.115

SS_Select Input Bias Current SS_Select=Gnd 40 80 uA

Power Good

Power Good Tur n on

Threshold VPG (on) VFB rising 85 90 95 % VREF

Power Good Lower Turn off

Threshold VPG(lower) VFB falling 80 85 90 % VREF

Power Good Tur n on Delay TPG(ON)_D VFB rising, see VPG (on) 2.56 ms

Power Good U pper Turn off

Threshold VPG(upper) VFB rising 115 120 125 % VREF

PGood Compar ator Delay VFB < VPG(lower) or

VFB > VPG(upper) 1 2 3.5 µs

PGood Voltage Low PG(voltage) IPGood = -5mA 0.5 V

Under-Voltage Lockout

Vcc-Start Threshold VCC UVLO

Start Vcc rising trip Level 3.9 4.1 4.3 V

Vcc-Stop Threshold VCC UVLO

Stop Vcc falling tr i p Lev el 3.6 3.8 4.0 V

Enable-Start-Threshold Enable

UVLO Start ramping up 1.14 1.2 1.26 V

Enable-Stop-Threshold Enable

UVLO Stop r amping down 0.95 1 1.05

Enable Leaka ge Current IEN_LK Enable = 3.3V 1 µA

IR3823

ELECTRICAL CHARACTERISTI CS (CONTINUED)

Unless otherwise specified, these specifications apply over, 5.5V < Vin = PVin < 21V, 0°C < TJ < 125°C, SS_Select=Float.

Typical values are specified at Ta = 25°C.

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

Over-Voltage Protection

OVP Trip Threshold OVP_Vth VFB rising 115 120 125 % VREF

OVP Comparator Delay TOVP_D 1 2 3.5 µs

Over-Current Protection

Current Limit ILIMIT Tj = 25°C, VCC=5.1V 3.6 4.5 5.4 A

Hiccup Blank ing Time TBLK_Hiccup

SS_Select = Vcc, Note 8 10

ms SS_Select = Float, Note 8 20

SS_Select = Gnd, Note 8 40

Over-Temperature Protection

Thermal Shutdown

Threshold

Note 8

145

°C

Hysteresis

Note 8

Note 8: Guaranteed by design, but not tested in production.

Note 9: Cold temperature performance is guaranteed via correlation using statistical quality control. Not tested in production.

IR3823

TYPICAL EFFICIENCY AND POWER LOSS CURVES

PVin = Vin=12V, VCC= Int er nal LDO, IO = 0A-3A, Room Temperature, N o A i r Flow. Note t hat the effici ency and power loss

curves include the losses of IR3823, the ind uctor losses and the losses of the input and output capacitors. The table bel ow

shows the ind uctors used for eac h of the output vol tages in the ef ficiency measurement.

VOUT (V) FS (kHz) LOUT (µH) P/N DCR (mΩ) SIZE (mm)

1.0 1000 1.0 XFL4020-102ME (Coilcraft) 10.8 4.0x4.0x2.1

1.2 1000 1.0 XFL4020-102ME (Coilcraft) 10.8 4.0x4.0x2.1

1.8 1000 1.2 PIMB053T-1R2MS-39 (Cyntec) 15 4.9x5.2x3.0

3.3 1000 2.2 XAL5030-222ME (Coilcraft) 13.2 5.28x5.48x3.1

5 1000 2.2 XAL5030-222ME (Coilcraft) 13.2 5.28x5.48x3.1

IR3823

TYPICAL EFFICIENCY AND POWER LOSS CURVES

PVin = 12V, Vin=VCC= Exter nal 5V, IO = 0A-3A, FS = 1000 kHz, Room Temperature, No Air Flow. Note that the efficiency and

power loss curves include the losses of IR3823, the induc tor losses an d the losses of the input and outp ut capacitors. The

table below shows the inductors used for each of the output voltages in the efficiency measurement.

VOUT (V) FS (kHz) LOUT (µH) P/N DCR (mΩ) SIZE (mm)

1.0 1000 1.0 XFL4020-1 02ME (Coilcraft) 10.8 4.0x4.0x2.1

1.2 1000 1.0 XFL4020-1 02ME (Coilcraft) 10.8 4.0x4.0x2.1

1.8 1000 1.2 PIMB053T-1R2MS-39 (Cyntec) 15 4.9x5.2x3.0

3.3 1000 2.2 XAL5030-222ME (Coilcraft) 13.2 5.28x5.48x3.1

5 1000 2.2 XAL5030-222ME (Coilcraft) 13.2 5.28x5.48x3.1

IR3823

TYPICAL EFFICIENCY AND POWER LOSS CURVES

PVin = Vin = VCC = 5V, IO = 0A-3A, FS = 1000 kHz, R oom Temperature, N o A i r Flow. Note t hat the efficien cy and power loss

curves include the losses of IR3823, the ind uctor losses and the losses of the input and output capacitors. The table bel ow

shows the ind uctors used for eac h of the output vol tages in the ef ficiency measurement.

VOUT (V) FS (kHz) LO UT (µH) P/N DCR (mΩ) SIZE (mm)

1.0 1000 1.0 XFL4020-1 02ME (Coilcraft) 10.8 4.0x4.0x2.1

1.2 1000 1.0 XFL4020-1 02ME (Coilcraft) 10.8 4.0x4.0x2.1

1.8 1000 1.0 XFL4020-1 02ME (Coilcraft) 10.8 4.0x4.0x2.1

3.3 1000 1.0 XFL4020-1 02ME (Coilcraft) 10.8 4.0x4.0x2.1

IR3823

RDS(ON) OF MOSFETS OVER TEMPERATURE AT VCC=5.1V

IR3823

TYPICAL OPERATING CHARAC TE RISTI CS ( -40°C TO +125°C)

IR3823

TYPICAL OPERATING CHARACTERISTI CS ( -40°C TO +125°C)

IR3823

THEORY OF OPERA TI ON

DESCRIPTION

The IR3823 SupIRBuck® is a 3A easy-to-use, fully

integrated and highly efficient synchronous Buck

regulator intended for Point-Of-Load (POL)

applications. It includes two IR HEXFETs with low

RDS(on). The bottom FET has an integrated

monolithic schottky diode in place of a conventional

body diode.

The IR3823 provides precisely regulated output

voltage programmed via two external resistors from

0.6V to 0.86×Vin. It uses voltage mode control

employing a proprietary PWM modulator with input

voltage feedforward. That provides excellent noise

immunity, easy loop compensation design, and good

line transient response.

The IR3823 has an internal Low Dropout (LDO)

Regulator, allowing single supply operation without

resorting to an external bias supply voltage. To

further improve the light load efficiency, the internal

LDO can be bypassed by using an external bias

supply. This mode allows the input bus voltage

range extended down to 1.0V.

The IR3823 features programmable switching

frequency from 300kHz to 1.5MHz, three selectable

soft-start time, and smooth synchronization to an

external clock. The other important functions include

thermally compensated over current protection,

output over voltage protection, pre-bias start-up,

enable with input voltage monitoring, PGood output

and thermal shut-down.

VOLTAGE LOOP C OM P ENSATION DESIGN

The IR3823 uses PWM voltage mode control. The

output voltage of the POL, sensed by a resistor

divider, is fed into an internal Error Amplifier (E/A).

The output of the E/R is then compared to an

internal ramp voltage to determine the pulse width of

the gate signal for the control FET. The amplitude of

the ramp voltage is proportional to Vin so that the

bandwidth of the voltage loop remains almost

constant for different input voltages. This feature is

called input voltage feedfoward. It allows the

feedback loop design independent of the input

voltage. Please refer to the next section for more

information.

A RC network has to be connected between the FB

pin and the COMP pin to form a feedback

compensator. The goal of the compensator design

is to achieve a high control bandwidth with a phase

margin of 45° or above. The high control bandwidth

is beneficial for the loop dynamic response, which

helps to reduce the number of output capacitors, the

PCB size and the cost. A phase margin of 45° or

higher is desired to ensure the system stability. For

most applications, a gain margin of -10dB or higher

is preferred to accommodate component variations

and to eliminate jittering/noise. The proprietary PWM

modulator in IR3823 significantly reduces the PWM

jittering, allowing the control bandwidth in the range

of 1/10th to 1/5th of the swit ching frequency.

Two types of compensators are commonly used:

Type II (PI) and Type III (PID), as shown in Figure 5.

The selection of the compensation type is

dependent on the ESR of the output capacitors.

Electrolytic capacitors have relatively higher ESR. If

the ESR pole is located at the frequency lower than

the cross-over frequency, FC, the ESR pole will help

to boost the phase margin. Thus a type II

compensator can be used. For the output capacitors

with lower ESR such as ceramic capacitors, type III

compensation is often desired.

Vout

REF

E/A

Fb Comp

(a)

Vout

Rf1

Rf2

RC1 CC1

CC2

E/A

Fb Comp

Rf3

Cf3

VREF

(b)

Figure 5: Loop Compensator (a) Type II, (b) Type III

IR3823

Table 1 lists the compensation selection for different

types of output capacitors.

For more detailed design guideline of voltage loop

compensation, please refer to the application note

AN-1162, “Compensation Design Procedure for

Buck Converter with Voltage-Mode Error-Amplifier”.

SupBuck design tool is also available at www.irf.com

providing the reference design based on user’s

design requirement s.

TABLE 1 RECOMMENDED COMPENSATION TYPE

COMPENSATOR LOCATION OF

CROSS-OVER

FREQUENCY

TYPE OF

OUTPUT

CAPACITORS

Type II (PI)

ESR

Electrolytic,

POS-CAP, SP-

CAP

Type III-A (PID)

ESR

POS-CAP, SP-

CAP

Type III-B (PID)

FLC<F0<FS/2<FESR

Ceramic

FLC is the resonant frequency of the output LC filter.

It is often referre d to as double pole.

F××

FESR is the ESR zero of the output ca pacitor.

ESR CESR

F××

F0 is the cross-over frequency of the closed voltage

loop and FS is the switching frequency.

INPUT VOLTAGE FEEDFORWARD

Input voltage feedforward is an important feature,

because it can keep the converter stable and

preserve its load transient performance when Vin

varies in a large range. In IR3823, feedforward

function is enabled when Vin pin is connected to PVin

pin and Vin>5.5V. In this case, the internal low

dropout (LDO) regulator is used. The PWM ramp

amplitude (Vramp) is proportionally changed with Vin

to maintain the ratio Vin/Vramp almost constant

throughout Vin variation range (as shown in Figure

6). Thus, the control loop bandwidth and phase

margin can be maintained constant. Feed-forward

function can also minimize impact on output voltage

from fast Vin change. The maximum Vin slew rate is

within 1V/µs.

If an external bias voltage is used as Vcc, Vin pin

should be connected to Vcc/LDO_out pin instead of

PVin pin. Then the feedforward function is disabled.

The control loop compensation might need to be

adjusted.

PWM Ramp

12V

Ramp Offset

7.3V

12V

PWM Ramp

Amplitude = 1.8V

PWM Ramp Amplitude

= 2.4V

PWM Ramp Amplitude

= 1.095V

16V

Figure 6: Timing Diagram for Input Feedforward

UNDER-VOLTAGE LOCKOUT AND POR

The Under-Voltage Lockout (UVLO) circuit monitors

the voltage of VCC/LDO_Output pin and the Enable

pin. It assures that the MOSFET driver outputs

remain off whenever either of these two signals is

below the set thresholds. Normal operation resumes

once both VCC/LDO_Output and En voltages rise

above their threshol ds.

The POR (Power On Ready) signal is generated

when all these signals reach the valid logic level

(see system block diagram). When the POR is

asserted, the soft start sequence starts (see soft

start section).

ENABLE/EXTERNAL PVIN MONITOR

The IR3823 has an Enable function providing

another level of flexibility for start-up. The Enable pin

has a precise threshold, which is internally

monitored by Under-Voltage Lockout (UVLO) circuit.

If the voltage at Enable pin is below its UVLO

threshold, both high-side and low-side FETs are off.

When Enable pin is below its UVLO, Over-Voltage

Protection (OVP) is disabled, and PGood stays low.

IR3823

The Enable pin should not be left floating. A pull-

down resistor in the range of several kilo ohms is

recommended to connect between the Enable Pin

and Gnd. It is recommended to apply the Enable

signal after the VCC voltage has been established. If

the Enable signal is present before VCC, a 50kΩ

resistor can be used in series with the Enable pin to

limit the current flowing into the Enable pin.

In addition to logical inputs, the Enable pin can be

used to implement precise input voltage UVLO. As

shown in Figure 7, the input of the Enable pin is

derived from the PVin voltage by a set of resistive

divider, R1 and R2. By selecting different divider

ratios, users can program the UVLO threshold

voltage. The bus voltage UVLO is a very desirable

feature. It prevents the IR3823 from regulating at

PVin lower than the desired voltage level. Figure 8

shows the start-up waveform with the input UVLO

voltage set at 10V .

IR3823

Enable

PVin

Figure 7: Implementation of Input Under-Voltage

Lockout (UVLO) using Enable Pin

Enable threshold

voltage1.2V

PVin (12V)

Vcc

Enable

Intl_SS

Vout

10V

Figure 8: Illustration of start-up with PVin UVLO

threshold voltage of 10V. The internal soft-start is

used in this case.

INTERNAL LOW DROPOUT REGU LATOR

The IR3823 has an internal Low Dropout Regulator

(LDO), offering a VCC voltage of 5.1V. The internal

LDO is beneficial for single rail (supply) applications,

where no external bias supplies will be needed. For

these applications, Vin pin should be connected to

PVin and VCC/LDO_Out pin is left floating as shown

in Figure 9. 1.0μF and 2.2μF ceramic bypass

capacitors should be placed close to Vin pin and

VCC/LDO_Out pin respectively.

IR3823

VCC/

LDO_OUT

PGnd

Vin PVin

1.0uF

2.2uF

Input =5V-21V

Figure 9: Internally Biased Single-Rail Configuration

When Vin drops below 5.5V, the internal LDO enters

the dropout mode. Figure 10 shows the

VCC/LDO_Out voltage for Vin=PVin=5V with switching

frequency of 600kHz and 1500kHz respectively.

Alternatively, if the input bus voltage, PVin, is in the

range of 4.5V to 7.5V, VCC/LDO_Out pin can be

directly connected to PVin pin to bypass the internal

LDO and therefore to avoid the voltage drop on the

internal LDO. This configuration is illustrated in

Figure 11.

Figure 12 shows the configuration using an external

VCC voltage. With thi s c onfiguration, t he input voltage

range can be extended down to 1.0V. Please note

that the input feedforward function is disabled for

this configuration. The feedback compensation

needs to be adjuste d accordingly.

It should be noted as the VCC voltage decreases, the

efficiency and the over current limit will decrease

due to the increase of RDS(ON). Please refer to the

section of the over current protection for more

information.

IR3823

Figure 10: LDO Dropout Voltage at Vin=PVin=5V

IR3823

VCC/

LDO_OUT

PGnd

Input =4.5V-7.5V

Vin PVin

1.0uF

2.2uF

Figure 11: Single-Rail Configuration for 4.5V-7V inputs

Ext VCC

4.5V-7.5V

IR3823

VCC/

LDO_OUT

PGnd

Vin PVin

2.2uF

Input =1.0V-21V

Figure 12: Use External Bia s Voltage

SOFT-START

The IR3823 has an internal digital soft-start circuit to

control the output voltage rise time, and to limit the

current surge at the start-up. To ensure correct start-

up, the soft-start sequence initiates when the Enable

and Vcc voltages rise above their UVLO thresholds

and generate the Power On Ready (POR) signal.

The slew rate of the internal soft-start can be

adjusted externally with SS_Select pin, as shown in

Table 2.

Table 2 User Selectable Soft-Start Time

SS_Select Slew Rate

(mV/ µs) Soft-Start Time

( ms )

Vcc

0.4

1.5

Float

0.2

Gnd

0.1

Figure 13 shows the waveforms during soft start.

The corresponding soft-start time can be calculated

as follows.

SlewRate VV

15.075.0 −

POR

Intl_SS

Vout

0.15V

0.75V

1.5V 3.0V

Figure 13: Theoretical start-up waveforms using

internal soft-start

It should be noted t hat during the soft-start, the over-

current protecti on (OCP) and over-v ol tage protection

(OVP) is enabled t o protect the device f or any short

circuit or over voltage condition.

PRE-BIAS START-UP

IR3823 is able to start up into a pre-charged output

smoothly, which prevents oscillations and

disturbances of the output voltage.

IR3823

The output starts in an asynchronous fashion and

keeps the synchronous MOSFET (Sync FET) off

until the first gate signal for control MOSFET (Ctrl

FET) is generated. Figure 14 shows a typical Pre-

Bias condition at start up. The gate signal of the

control FET is determined by the loop compensator.

The sync FET always starts with a narrow pulse

width (12.5% of a switching period) and gradually

increases its duty cycle with a step of 12.5% until it

reaches the steady state value. The number of these

startup pulses for each step is 16 and it’s internally

programmed. Figure 15 shows the series of 16x8

startup pulses.

It should be noted that during pre-bias start up,

PGood is not active until the first gate signal for

control FET is generated. Please refer to Power

Good Section f or m ore information.

Pre-Bias Voltage

Figure 14: Pre-Bias start-up

... ... ...

HDRv

... ... ...

16 End of

LDRv

12.5% 25% 87.5%

...

Figure 15: Pre-Bias startup pulses

SHUTDOWN

IR3823 can be shut down by pulling the Enable pin

below its 1.0V threshold. Both the high side and the

low side drivers will be pul led low.

OPERATING FRE QUENCY

The switching frequency can be programmed

between 300kHz – 1200kHz by connecting an

external resistor from Rt pin to Gnd. Rt can be

calculated as follows.

953.0

19954 −

×= ts RF

Where FS is in kHz, and Rt is in kΩ.

Table 3 shows the different oscill ator frequency and

its correspondi ng Rt for easy reference.

Table 3 Switching Frequ ency vs. Rt

Rt (kΩ)

FS (kHz)

80.6

300

60.4

400

48.7

500

39.2

600

700

29.4

800

26.1

900

23.2

1000

1100

19.1

1200

17.4

1300

16.2

1400

1500

OVER CURRENT PROTECTION

The over current (OC) protection is performed by

sensing current through the RDS(on) of the

Synchronous MOSFET. This method enhances the

converter’s efficiency, reduces cost by eliminating a

current sense resistor and any layout related noise

issues. The current limit is pre-set internally and is

compensated according to the IC temperature. So at

different ambient temperature, the over-current trip

threshold remai ns almost constant.

Detailed operation of OCP is explained as follows.

Over Current Protection circuit senses the inductor

current flowing through the Synchronous MOSFET

closer to the valley point. OCP circuit samples this

current for 40nsec typically after the rising edge of

the PWM set pulse, which has a width of 12.5% of

the switching period. The PWM pulse starts at the

falling edge of the PWM set pulse. This makes valley

current sense more robust as current is sensed

close to the bottom of the inductor downward slope

where transient and switching noise are lower and

helps to prevent false tripping due to noise and

transient. An OC condition is detected if the load

current exceeds the threshold, the converter enters

IR3823

into hiccup mode. PGood will go low and the internal

soft start signal will be pulled low. The converter

goes into hiccup mode with some hiccup blanking

time as shown in Figure 16. The convertor stays in

this mode until the over load or short circuit is

removed. With different SS_Select configurations,

the hiccup blanking time is different. Please refer to

the electrical table for details. The actual DC output

current limit point will be greater than the valley point

by an amount equal to approximately half of peak to

peak inductor ripple current.

LIMITOCP

∆

IOCP= DC current limit hiccu p point

ILIMIT= Over current limit (Valley of I nductor Current)

Δi= Peak-to-peak inductor ripple current

HDrv

LDrv

PGood

Over Current Limit

...

Hiccup Blanking Time

Figure 16: Timing Diagram for Hiccup OCP

Over current limit is affected by the VCC voltage. For

some single rail operations where Vin is 5V or less,

the OCP limit will de-rated due to the drop of VCC

voltage. Figure 17 and Figure 18 show the over

current limit for two single rail applications with

Vin=PVin=5V and Vin=PVin=VCC=4.5V respectively.

Figure 17:OCP Limit at Vin=PVin=5V using Internal LDO

Figure 18: OCP Limit at Vin=PVin=VCC=4.5V

OVER-VOLTAGE PROTECTION ( OVP)

Over-voltage protection in IR3823 is achieved by

comparing FB pin voltage to a pre-set threshold.

OVP threshold is set at 1.2×Vref. When FB pin

voltage exceeds the over voltage threshold, an over

voltage trip signal asserts after 2us (typ.) delay.

Then the high side drive signal HDrv is turned off

immediately, PGood flags low. The sync FET

remains on to discharge the output capacitor. When

the VFB voltage drops below the threshold, the sync

FET turns off to prevent the complete depletion of

the output capacitor. After that, HDrv remains off

until a reset is performed by cycling either Vcc or

Enable. Figure 19 shows the timing diagram for over

voltage protection. Please note that OVP

comparator becomes active only when the IR3823 is

enabled.

HDrv

LDrv

1.2*Vref

PGood

0.6V

Figure 19: Timing Diagram for Over Voltage Protect ion

IR3823

POWER GOOD OUTPUT

IR3823 continually monitors the output voltage via

FB voltage. The FB voltage is an input to the window

comparator with upper and lower threshold of 120%

and 85% of the reference voltage respectively.

PGood signal is high whenever FB voltage is within

the PGood comparator window thresholds. For pre-

biased start-up, PGood is not active until the first

gate signal of the control FET is generated.

The PGood pin is open drain and it needs to be

externally pulled high. High state indicates that

output is in regulation.

In addition, PGood is also gated by other faults

including over current and over temperature. When

either of the faults occurs, PGood pin will be pulled

low.

THERMAL SHUTDOW N

Temperature sensing is provided inside IR3823. The

trip threshold is typically set to 145ºC. When trip

threshold is exceeded, thermal shutdown turns off

both MOSFETs and resets the internal s oft start.

Automatic restart is initiated when the sensed

temperature drops within the operating range. There

is a 20°C hysteresis in the thermal shutdown

threshold.

EXTERNAL SYNCHRONIZATION

IR3823 incorporates an internal phase lock loop

(PLL) circuit which enables synchronization of the

internal oscillator to an external clock. This function

is important to avoid sub-harmonic oscillations due

to beat frequency for embedded systems when

multiple point-of-load (POL) regulators are used. A

multi-function pin, Rt/Sync, is used to connect the

external clock. If the external clock is present before

the converter turns on, Rt/Sync pin can be

connected to the external clock signal solely and no

other resistor is needed. If the external clock is

applied after the converter turns on, or the converter

switching frequency needs to toggle between the

external clock frequency and the internal free-

running frequency, an external resistor from Rt/Sync

pin to Gnd is required to set the free-running

frequency.

When an external clock is applied to Rt/Sync pin

after the converter runs in steady state with its free-

running frequency, a transition from the free-running

frequency to the external clock frequency will

happen. This transition is to gradually make the

actual switching frequency equal to the external

clock frequency, no matter which one is higher. On

the contrary, when the external clock signal is

removed from Rt/Sync pin, the switching frequency

is also changed to free-running gradually. In order to

minimize the impact from these transitions to output

voltage, a diode is recommended to add between

the external clock and Rt/Sync pin, as shown in

Figure 20. Figure 21 shows the timing diagram of

these transitions.

An internal compensation circuit is used to change

the PWM ramp slope according to the clock

frequency applied on Rt/Sync pin. Thus, the

effective amplitude of the PWM ramp (Vramp), which

is used in compensation loop calculation, has minor

impact from the variation of the external

synchronization signal.

IR3823

Rt/Sync

Gnd

Figure 20: Configuration of Ext e rnal Synchronization

SYNC

...

Gradually change

Fs1

Fs2

Fs1

Free Running

Frequency Synchronize to the

external clock Return to free-

running freq

Gradually change

Figure 21: Timing Diagram for Synchronization

to the External Clock (Fs1<Fs2 o r Fs1>Fs2)

IR3823

MINIMUM O N TIME CONSIDERATIONS

The minimum O N t i m e i s t he shortest amount of t i m e

for which Ctrl FET may be reliably turned on, and

this depends on the internal timing delays. For

IR3823, the worst case minimum on-time is specified

as 60ns.

Any design or application using IR3823 must ensure

operation with a pulse width that is higher than this

minimum on-time and preferably higher than 60ns.

This is necessary for the circuit to operate without

jitter and pulse-skipping, which can cause high

inductor current ripple and high output voltage ripple.

sin

out

on FVV

t×

In any application that uses IR3823, the following

condition must be sat isfied:

t≤

(min)

out

FVV

t×

≤

(min)

, therefore,

(min)on

out

sin tV

FV ≤×

The minimum output voltage is limited by the

reference voltage and hence Vout(min) = 0.6V.

Therefore,

Therefore, at the maximum recommended input

voltage 21V and minimum output voltage, the

converter should be designed at a switching

frequency that does not exceed 476 kHz.

Conversely, for operation at the maximum

recommended operating frequency (1.65 MHz) and

minimum output voltage (0.6V). The input voltage

(PVin) should not exceed 6V, otherwise pulse

skipping will happen.

MAXIMUM DUTY RATIO

A certain off-time is specified for IR3823. This

provides an upper limit on the operating duty ratio at

any given switching frequency. The off-time remains

at a relatively fixed ratio to switching period in low

and mid frequency range, while in high frequency

range this ratio increases, thus the lower the

maximum duty ratio at which IR3823 can operate.

Figure 22 shows a plot of the maximum duty ratio vs.

the switching frequency.

Figure 22: Maximum duty cycle vs. switching

frequency.

out

sin

/10

ns60 V6.0

(min)

==≤×

IR3823

DESIGN EXAMPLE

The following ex am pl e is a typical application for

IR3823. The applicat i on circuit is shown i n Figure

26.

PVin = Vin = 12V (±10%)

Vo = 1.2V

Io = 3A

Peak-to-Peak Ripple Voltage = ±1% of Vo

ΔVo = ± 4% of Vo (for 30% Load Transient)

Fs = 1MHz

EXTERNAL PVIN MONITOR (INPUT UVLO)

As explained in the section of Enable/External PVin

monitor, the input voltage, PVin, can be monitored by

connecting the Enable pin to PVin through a set of

resistor divider. When PVin exceeds the desired

voltage level such that the voltage at the Enable pin

exceeds the Enable threshold, 1.2V, the IR3823 is

turned on. The implementation of this function is

shown in Figure 7.

For a typical Enable threshold of VEN = 1.2 V

2.1

(min)

ENin

RR R

VPV V

RR −

×=

(min)

For the minimum input voltage PVin (min) = 9.2V,

select R1=49.9kΩ, and R2=7.5kΩ.

SWITCHING FREQUENCY

For FS = 1MHz, se lect Rt = 23.2 kΩ, from Table 3.

OUTPUT VOLTAGE SETTING

Output voltage is set by the reference voltage and

the external voltage divider connected to the FB pin.

The FB pin is the inverting input of the error

amplifier, which is internally referenced to 0.6V. The

divider ratio is set to provide 0.6V at the FB pin

when the output is at its desired value. The output

voltage is defined by using the foll owing equation:

)1(

REFoR

VV +×=

RF1 and RF2 are the feedback resistor divider, as

shown in Figure 23. For the selection of RF1 and RF2,

please see feedback compensati on section.

IR3823

Vout

Rf1

Rf2

Figure 23: The output voltage is programmed through

a set of feedback resistor divid er

BOOTSTRAP CAPACITOR SELECTION

To drive the Control FET, it is necessary to supply a

gate voltage at least 4V greater than the voltage at

the SW pin, which is connected to the source of the

Control FET. This is achieved by using a bootstrap

configuration, which comprises the internal bootstrap

diode and an external bootstrap capacitor, C1, as

shown in Figure 24. The operation of the circuit is as

follows: When the sync FET is turned on, the

capacitor node connected to SW is pulled low. VCC

starts to charge C1 through the internal bootstrap

didoe. The voltage, Vc, across the bootstrap

capacitor C1 can be calculated as

CCCV

VV −

where VD is the forward voltage drop of the

bootstrap diode.

When the control FET turns on in the next cycle, the

SW node voltage rises to the bus voltage, PVin. The

voltage at the Boot pin becomes:

DCCinBOOT

VVPVV−+=

IR3823

A good quality ceramic capacitor of 0.1μF with

voltage rating of at least 25V is recommended for

most applications.

VIN

Boot

PGnd

+ V

Cvin

Figure 24: Bootstrap circuit to generate the supply

voltage for the high-side driver voltage

INPUT CAPACITOR SELECTION

Good quality input capacitors are necessary to

minimize the input ripple voltage and to supply the

switch current during the on-time. The input

capacitors should be selected based on the RMS

value of the input ripple current and requirement of

the input ripple vol tage.

The RMS value of the input ripple current can be

calculated as follows:

)1( DDII

oRMS

−××=

Where D is the duty cycle and Io is the output

current. For Io=6A and D=0.1, IRMS= 0.9A

The input voltage ripple is the result of the charging

of the input capacitors and the voltage induced by

ESR and ESL of the i nput capacitors.

Ceramic capacitors are recommended due to their

high ripple current capabilities. They also feature low

ESR and ESL at higher frequency which enables

better efficiency.

For this application, it is suggested to use two

10μF/25V ceramic capacitors, C3216X5R1E106M,

from TDK. In addition, although not mandatory, a

1x100uF, 25V SMD capacitor EEE-1EA101XP from

Panasonic may also be used as a bulk capacitor and

is recommended if the input power supply is not

located close t o the converter.

INDUCTOR SELECTI ON

The inductor is selected based on output power,

operating frequency and efficiency requirements. A

low inductor value causes large ripple current,

resulting in the smaller size, faster response to a

load transient but poor efficiency and high output

noise. Generally, the selection of the inductor value

can be reduced to the desired maximum ripple

current in the inductor (Δi). The optimum point is

usually found between 20% and 50% ripple of the

output current.

The saturation current of the inductor is desired to

be higher than the over current limit plus the inductor

ripple current. An inductor with soft-saturation

characteristic is recommended.

For the buck converter, the inductor value for the

desired operating ripple current can be determined

using the followin g rel ation:

LVPV L

oin ∆

∆

×=− max

max

;

t=∆

sLin

oin

FiV V

PVL×∆×

×−=

max

)(

Where:

PVinmax = Maximum input voltage

V0 = Output Voltage

ΔiLmax = Maximum Inductor P eak-to-Peak Ripple

Current

Fs = Switching Frequency

Δt = On time

D = Duty Cycle

Select ΔiLmax ≈ 36%×Io, then the output inductor is

calculated to be 1.0μH. Select L=1.0μH, XFL4020-

102ME, from Coilcraft which provides a compact,

low profile inductor suitable for this application.

OUTPUT CAPACITOR SELECTION

Output capacitors are usually selected to meet two

specific requirements: (1) Output ripple voltage and

IR3823

(2) load transient response. The load transient

response is also greatly affected by the control

bandwidth. So it is common practice to select the

output capacitors to meet the requirements of the

output ripple voltage first, and then design the

control bandwidth to meet the transient load

response. For some cases, even with the highest

allowable control bandwidth, the resulting load

transient response still cannot meet the requirement.

The number of output capacitors then need to be

increased.

The voltage ripple is attributed by the ripple current

charging the output capacitors, and the voltage drop

due to the Equivalent Series Resistance (ESR) and

the Equivalent Series Inductance (ESL). Following

lists the respectiv e peak-to-peak ripple voltages:

ESL

LVPV

ESRiV

oin

ESLo

LESRo

−

=∆

×∆=∆

××

∆

=∆

)(

max)(

max

)(

Where ΔiLmax is maximum inductor peak-to-peak

ripple current.

Good quality ceramic capacitors are recommended

due to their low ESR, ESL and the small package

size. It should be noted that the capacitance of

ceramic capacitors are usually de-rated with the DC

and AC biased voltage. It is important to use the de-

rated capacitance value for the calculation of output

ripple voltage as well as the voltage loop

compensation design. The de-rated capacitance

value may be obtained from the manufacturer’s

datasheets.

In this case, one 22uF ceramic capacitors,

C2012X5R0J226M, from TDK are used to achieve

±12mV peak-to-peak ripple voltage requi rement. The

de-rated capacitance value with 1.2VDC bias and

10mVAC voltage is a round 18uF each.

FEEDBACK COMPENSATION

For this design, the resonant frequency of the output

LC filter, FLC, is

kHz5

37 10

181

100

××

−

The equivalent ESR zero of the output capacitors,

FESR, is.

kHz109.2 10

18103

12 1

×=

×××

−−

ESR CESR

Designing crossover frequency at 1/5th of switching

frequency gives F0=200 kHz.

According to Table 1, Type III B compensation is

selected for FLC<F0<FS/2<FESR. Type III compensator

is shown below for easy reference.

Vout

E/A

Fb Comp

REF

Frequency

Gain

(dB)

|H(s)|

Figure 25: Type III compensation and its asymptotic

gain plot

IR3823

As can be seen from Figure 25, Type III

compensator contains two zeros and three poles.

They can be calculated as follows.

The zeros are:

F××

)(2 1

133

2FFF

RRC

F+××

The poles are:

F××

Please note that the order of the zeros and poles do

not necessaril y follow the location sh own in Figure

25. It can vary with the design preference.

To archive the suf ficient phase boost near the cross-

over frequency, it is desired to place one zero and

one pole as follow s:

kHz

70sin170sin

10200

sin

1sin1

−

×=

−

kHz1134

70sin170sin1

10200

sin1sin1

−

×=

−

To compensate the phase lag of the pole at the

origin and to provide extra phase boost, the other

zero can be placed at one half of the first zero, i.e.

1/FZ = 17.5 kHz.

The third pole is usually placed at one half of the

switching frequency to damp the swit ching noise.

The selected compensation parameters are:

RF1=4.02kΩ, RF2=4.02kΩ, RF3=127Ω, CF3=2200pF,

RC1=1.0kΩ, CC1=4.7nF, CC2=56pF. The resulting

zeros and poles are listed in Table 4. Please note

that one of high-frequency poles has been moved to

2843 kHz to increase the phase margin.

Table 4 Zeros and Poles of the Voltag e Loop

Compensator

Zeros

Poles

34 kHz

17 kHz

570 kHz

2843 kHz

IR3823

APPLICATION DIAGRAM

Boot

Vcc/LDO_out

Comp

Gnd PGnd

PGood

Rt/Sync

PVinVin

Enable

IR3823

SS_Select

12V

PGood

1.2V

1.0uF 2x10uF

49.9k

7.5k

49.9k

2.2uF

23.2k

0.1uF

1.0uH

4.02k

127Ω

4.02k

1.0k

4.7nF

56pF

2200pF Cout

22uF

0.1uF

Figure 26: Single Rail 3A POL Application Circuit: PVin=Vin=12V, Vo=1.2V, Io=3A, fsw=1MHz

SUGGESTED BILL OF MATERIALS

QTY PART

REFERENCE VALUE DESCRIPTION MANUFACTURER PART NUMBER

Cin

10uF

1206, 25V, X5R, 20%

TDK

C3216X5R1E106M

C7, C12, C24

0.1uF

0603, 25V, X7R, 10%

Murata

GRM188R71E104KA01B

C11

56pF

0603, 50V, NP0, 5%

TDK

C1608C0G1H560J080AA

1 Cout 22uF 0805, 6.3V, X5R, 20% TDK C2012X5R0J226M

2200pF

0603,50V,X7R

Murata

GRM188R71H222KA01B

C23

2.2uF

0603, 16V, X5R, 20%

TDK

C1608X5R1C225M

C26

4700pF

0603, 50V 10% X7R

Murata

GRM188R71H472KA01D

C32

1.0uF

0603, 25V, X5R, 10%

Murata

GRM188R61E105KA12D

1.0k

Thick Film , 0603,1/10W,1%

Panasonic

ERJ-3EKF1001V

R2, R3

4.02k

Thick Film , 0603,1/10W,1%

Panasonic

ERJ-3EKF4021V

127

Thick Film, 0603,1/10W,1%

Panasonic

ERJ-3EKF1270V

23.2k

Thick Film , 0603,1/10W

Panasonic

ERJ-3EKF2322V

2 R17, R18 49.9k Thick Film, 0603,1/10W,1% Panasonic ERJ-3EKF4992V

R19

7.5k

Thick Film , 0603,1/10W,1%

Panasonic

ERJ-3EKF7501V

1 L 1.0uH

SMD, 4.0mmx4.0mmx2.1mm,

10.8mΩ

Coilcraft XFL4020-102ME

IR3823

3A POL, PQFN 3.5mm x3.5mm

IR3823

APPLICATION DIAGRAM

Boot

Vcc/LDO_out

Comp

Gnd PGnd

PGood

Rt/Sync

PVinVin

Enable

IR3823

SS_Select

12V

PGood

1.2V

1.0uF 2x10uF

Cin

C32

49.9k

R18

7.5k

R19

49.9k

R17

2.2uF

C23

23.2k

0.1uF

C24

0.1uF

1.0uH

4.02k

127Ω

4.02k

475Ω

R1C26

15nF

C11 220pF

C82200pF Cout

22uF

C12

0.1uF

Ext Vcc=5V

Figure 27: 3A POL Application Circuit with external 5V VCC: PVin=Vin=12V, Vo=1.2V, Io=3A, fsw=1MHz. Please note th at

loop compensation is adjusted to consider the absence of the input voltage feedforward.

Boot

Vcc/LDO_out

Comp

Gnd PGnd

PGood

Rt/Sync

PVinVin

Enable

IR3823

SS_Select

PGood

1.0uF 3x10uF

Enable

49.9k

2.2uF

23.2k

0.1uF

1.0uH

4.02k

127Ω

6.04k

4.7nF

100pF

2200pF Cout

22uF

0.1uF

Figure 28: Single Rail 3A POL Application Circuit: PVin=Vin=5V, Vo=1.0V, Io =3A, fsw=1MHz

IR3823

TYPICAL OPERATING WAVEFORMS

Vin = 12V, V0 = 1.2V, I0 = 0-3A, Unless otherwise Specified, SS_Select = Float. Room Temperature, No A i r Flow

Figure 29: Start up at 3A Load with SS_Select pin Figure 30: Start up at 3A Load with S S _Select pin

floating. Ch1:Vin, Ch2: PGood, Ch3:Vo ,Ch4: Enable floating. Ch1:Vin, Ch2: Vcc, Ch3:Vo ,Ch4: Enable

Figure 31: Start up with 1.06V Pre Bias, 0A Load Figure 32: Output Voltage Ripple, 3A load Ch3: Vout

Ch3:Vo, Ch2:PGood

Figure 33: Inductor node at 3A load, Ch3: SW node Figure 34: Short circuit (Hiccu p) Recovery,

Ch3:Vout , Ch4:Iout

IR3823

TYPICAL OPERATING WAVEFORMS

Vin = 12V, V0 = 1.2V, I0 = 0-3A, Unless otherwise Specified, SS_Select = Float. Room Temperature, No A i r Flow

Figure 35: Transient Response, 2A to 3A Figure 36: Feed Forward for Vin change

Step load Ch3:Vout Ch4-Iout from 7 to 14V and back to 7V. Ch3-Vout, Ch4-Vin

Figure 37: Bode Plot at 6A load, bandwidth = 188 kHz, and phase margin = 53 degrees and gain margin = -10dB

IR3823

TYPICAL OPERATING WAVEFORMS

Vin = 12V, V0 = 1.2V, I0 = 0-3A, Unless otherwise Specified, SS_Select = Float. Room Temperature, No A i r Flow

Figure 38: Efficiency vs. Load Current

Figure 39: Power Loss vs. Load Current

IR3823

TYPICAL OPERATING WAVEFORMS

Vin = 12V, V0 = 1.2V, I0 = 0-3A, Unless otherwise Specified, SS_Select = Float. Room Temperature, No A i r Flow

Figure 40: Thermal Image of the board at 3A load, IR3823=45°C, Inductor=41.3°C

IR3823

LAYOUT RECOMMENDATIONS

The layout is very important when designing high

frequency switching converters. Layout will affect

noise pickup and can cause a good design to

perform with worse than expected results.

Make the connections for the power components in

the top layer with wide, copper filled areas or

polygons. In general, it is desirable to make proper

use of power planes and polygons for power

distribution and heat dissipation.

The inductor, output capacitors and the IR3823

should be as close to each other as possible. This

helps to reduce the EMI radiated by the power

traces due to the high switching currents through

them. Place the input capacitor directly at the PVin

pin of IR3823.

The feedback part of the system should be kept

away from the inductor and other noise sources.

The critical bypass components such as capacitors

for Vin and VCC should be close to their respective

pins. It is important to place the feedback

components including feedback resistors and

compensation components close to Fb and Comp

pins.

In a multilayer PCB use one layer as a power

ground plane and have a control circuit ground

(analog ground), to which all signals are referenced.

The goal is to localize the high current path to a

separate loop that does not interfere with the more

sensitive analog control function. These two grounds

must be connected together on the PC board layout

at a single point. It is recommended to place all

the compensation parts over the analog ground

plane in top layer.

The Power QFN is a thermally enhanced package.

Based on thermal performance it is recommended to

use at least a 4-layers PCB. To effectively remove

heat from the device the exposed pad should be

connected to the ground plane using via holes.

Figure 41-Figure 44 illustrates the implementation of

the layout guidelines outlined above, on the

IRDC3823 4-layer demo board.

Figure 41: IRDC3823 Demo Board – Top Layer

PVin

PGnd

AGnd

Vout

Compensation par ts

should be plac ed

as close as possible

to the Comp pin

Resistor R

t should be

placed as clos e as

possible to their pins

Allow enough copper &

minimum grou nd length

path between Input and

Output

SW node copper i s

kept

only at the t op

layer to minimize

the switching noise

All bypass caps

should be plac ed

as close as possible

to their connecting pins

Single point c onnection

between AGN D &

PGND, should be c l ose

to the SupIRBu ck

and

kept away from noise

IR3823

Figure 42: IRDC3823 Demo Board – Bottom Layer

Figure 43: IRDC3823 Demo Board – Middle Layer 1

PVin

PGnd

Vout

AGnd

PGnd

IR3823

Figure 44: IRDC3827 Demo Board – Middle Layer 2

Feedback and V s ns trace

routing should be kept

away from noise sources

PGnd

IR3823

PCB METAL AND COMPONENT

PLACEMENT

Evaluations have shown that the best overall

performance is achieved using the substrate/PCB

layout as shown in following figures. PQFN devices

should be placed to an accuracy of 0.050mm on

both X and Y axes. Self-centering behavior is highly

dependent on solders and processes, and

experiments should be run to confirm the limits of

self-centering on spe cific processes.

For further information, please refer to “SupIRBuck®

Multi-Chip Module (MCM) Power Quad Flat No-Lead

(PQFN) Board Mounting Application Note.”

(AN1132)

Figure 45: PCB Metal Pad Spacing (all dimensions in mm)

* Contact International Rectifier to receive an electronic PCB Library file in your preferred format

IR3823

SOLDER RESIST

IR recommends t hat the larger Power or Land Area

pads are Solder Mask Defined (SMD.) This allows

the underlying Copper traces to be as large as

possible, which helps in terms of cur rent carrying

capability and device cooling capabilit y.

When using SMD pads, the underlying copper

traces should be at least 0.05mm large r (on each

edge) than the S older M ask window, in order to

accommodate any layer to layer misali gnment. (i.e.

0.1mm in X & Y.)

However, for t he smal l er Signal type leads around

the edge of the dev i ce, IR recommends t hat these

are Non Solder Mask Defined (NSMD) or Copper

Defined.

When using NSMD pads, the Solder Resist Window

should be larger than the Copper Pad by at least

0.025mm on each edge, (i.e. 0.05mm in X&Y,) in

order to accommodat e any layer to layer

misalignment.

Ensure that the solder resist in-between the smalle r

signal lead areas are at least 0.15mm wide, due to

the high x/y aspect rat i o of the solder mask strip.

Figure 46: Solder Resist

IR3823

STENCIL DESIGN

Stencils for PQFN can be used with thicknesses of

0.100-0.250mm (0.004-0.010"). Stencils thinner than

0.100mm are unsuitable because they deposit

insufficient solder paste to make good solder joints

with the ground pad; high reductions sometimes

create similar problems. Stencils in the range of

0.125mm-0.200mm (0.005-0.008"), with suitable

reductions, gi ve the best results.

Evaluations have shown that the best overall

performance is achieved using the stencil design

shown in following figure. This design is for a stencil

thickness of 0.127mm (0.005"). The reduction

should be adjusted for stencils

of other thicknes ses.

Figure 47: Stencil Pad Spacing (all dimensions in mm)

IR3823

MARKING INFORMATION

PACKAGE INFORMATION

IR3823

ENVIRONMENTAL QUALIFICATIONS

Qualification Level Industrial

Moisture Sensitivity Level 3.5mm x 3.5m m PQFN JEDEC Lev el 2 @ 260°C

ESD

Machine Model

(JESD22-A115A) Class B

≥200V to <400V

Human Body Model

(JESD22-A114F) Class 2

≥2000V to <4000V

Charged Device Model

(JESD22-C101D) Class III

≥500V to ≤1000V

RoHS6 Compliant Yes

† Qualification standards can be found at International Rectifier web site: http://www.irf.com

†† Exceptions to AEC-Q101 requirements are noted in the qualification report.

Data and specifications subject to change without notice.

Qualification Standards can be found on IR’s Web site.

IR WORLD HEADQUARTERS: 233 Kansas St., El Segund o, California 9 0245, USA Tel : (310) 252-7105

TAC Fax: (310) 252-7903

Visit us at ww w.irf.com for sales contact inf ormation.