LTC4251/LTC4251-1/
LTC4251-2
1
425112fa
■
Hot Board Insertion
■
Electronic Circuit Breaker
■
–48V Distributed Power Systems
■
Negative Power Supply Control
■
Central Office Switching
■
Programmable Current Limiting Circuit
■
High Availability Servers
■
Disk Arrays
■
Allows Safe Board Insertion and Removal from a
Live –48V Backplane
■
Floating Topology Permits Very High Voltage
Operation
■
Programmable Analog Current Limit with Circuit
Breaker Timer
■
Fast Response Time Limits Peak Fault Current
■
Programmable Timer
■
Programmable Undervoltage/Overvoltage Protection
■
Low Profile (1mm) ThinSOT
TM
Package
Negative Voltage
Hot Swap Controllers in SOT-23
–48V, 2.5A Hot Swap Controller
The LTC
®
4251/LTC4251-1/LTC4251-2 negative voltage
Hot Swap
TM
controllers allow a board to be safely inserted
and removed from a live backplane. Output current is
controlled by three stages of current limiting: a timed
circuit breaker, active current limiting and a fast feedforward
path that limits peak current under worst-case catastrophic
fault conditions.
Programmable undervoltage and overvoltage detectors
disconnect the load whenever the input supply exceeds
the desired operating range. The supply input is shunt
regulated, allowing safe operation with very high supply
voltages. A multifunction timer delays initial start-up and
controls the circuit breaker’s response time.
The LTC4251 UV/OV thresholds are designed to match the
standard telecom operating range of –43V to –75V. The
LTC4251-1 UV/OV thresholds extend the operating range
to encompass –36V to –72V. The LTC4251-2 implements
a UV threshold of –43V only.
All parts are available in the 6-Pin SOT-23 package.
Start-Up Behavior
GATE
5V/DIV
SENSE
2.5A/DIV
VOUT
20V/DIV
425112 TA02
1ms/DIV
+
LTC4251
UV/OV
TIMER
GATE
SENSE
VIN
VEE
1
2
3
4
56
LOAD
GND
GND
(SHORT PIN)
R1
402k
1%
RC
10ΩRS
0.02Ω
R2
32.4k
1%
–48V
CT
150nF
C1
10nF
CC
18nF
CIN
1µF
CL
100µF
RIN*
10k
500mW
VOUT
Q1
IRF530S
425112 TA01
4
3
2
1
*TWO 0.25W RESISTORS IN SERIES FOR
RIN ON THE PCB ARE RECOMMENDED.
APPLICATIO S
U
FEATURES
TYPICAL APPLICATIO
U
DESCRIPTIO
U
, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.
ThinSOT and Hot Swap are trademarks of Linear Technology Corporation.
LTC4251/LTC4251-1/
LTC4251-2
2
425112fa
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
V
Z
V
IN
to V
EE
Zener Voltage I
IN
= 2mA ●11.5 13 14.5 V
r
Z
V
IN
to V
EE
Zener Dynamic Impedance I
IN
= 2mA to 30mA 5 Ω
I
IN
V
IN
Supply Current UV/OV = 4V, V
IN
= (V
Z
– 0.3V) ●0.8 2 mA
V
LKO
V
IN
Undervoltage Lockout Coming out of UVLO (Rising V
IN
)●9.2 11.5 V
V
LKH
V
IN
Undervoltage Lockout Hysteresis 1V
V
CB
Circuit Breaker Current Limit Voltage V
CB
= (V
SENSE
– V
EE
)●40 50 60 mV
V
ACL
Analog Current Limit Voltage V
ACL
= (V
SENSE
– V
EE
)●80 100 120 mV
V
FCL
Fast Current Limit Voltage V
FCL
= (V
SENSE
– V
EE
)●150 200 300 mV
I
GATE
GATE Pin Output Current UV/OV = 4V, V
SENSE
= V
EE
, V
GATE
= 0V (Sourcing) ●40 58 80 µA
UV/OV = 4V, V
SENSE
– V
EE
= 0.15V, V
GATE
= 3V (Sinking) 17 mA
UV/OV = 4V, V
SENSE
– V
EE
= 0.3V, V
GATE
= 1V (Sinking) 190 mA
V
GATE
External MOSFET Gate Drive V
GATE
– V
EE
, I
IN
= 2mA ●10 12 V
Z
V
V
GATEL
Gate Low Threshold (Before Gate Ramp-Up) 0.5 V
V
UVHI
UV Threshold High LTC4251/LTC4251-2 ●3.075 3.225 3.375 V
LTC4251-1 ●2.300 2.420 2.540 V
V
UVLO
UV Threshold Low LTC4251/LTC4251-2 ●2.775 2.925 3.075 V
LTC4251-1 ●2.050 2.160 2.270 V
V
UVHST
UV Hysteresis LTC4251/LTC4251-2 0.30 V
LTC4251-1 0.26 V
V
OVHI
OV Threshold High LTC4251 ●5.85 6.15 6.45 V
LTC4251-1 ●5.86 6.17 6.48 V
ABSOLUTE AXI U RATI GS
W
WW
U
PACKAGE/ORDER I FOR ATIO
UUW
Current into V
IN
(100µs Pulse) ........................... 100mA
Minimum V
IN
Voltage ........................................... –0.3V
Gate, UV/OV, Timer Voltage .......................– 0.3V to 16V
Sense Voltage ............................................– 0.6V to 16V
Current Out of Sense Pin (20µs Pulse) ............. –200mA
Maximum Junction Temperature .......................... 125°C
Operating Temperature Range
LTC4251C/LTC4251-1C/LTC4251-2C ...... 0°C to 70°C
LTC4251I/LTC4251-1I/LTC4251-2I .... – 40°C to 85°C
Storage Temperature Range ................. – 65°C to 150°C
Lead Temperature (Soldering, 10 sec).................. 300°C
(Note 1), All Voltages are Referred to VEE
ELECTRICAL CHARACTERISTICS
The ● denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Notes 2, 3)
T
JMAX
= 125°C, θ
JA
= 256°C/W
SENSE 1
V
EE
2
V
IN
3
6 GATE
5 UV/OV*
4 TIMER
TOP VIEW
S6 PACKAGE
6-LEAD PLASTIC SOT-23
*UV FOR LTC4251-2
ORDER PART NUMBER S6 PART MARKING
Consult LTC Marketing for parts specified with wider operating temperature ranges.
LTC4251CS6
LTC4251IS6
LTC4251-
1CS6
LTC4251-1IS6
LTC4251-
2CS6
LTC4251-2IS6
LTUQ
LTUR
LTQU
LTQV
LTK6
LTAAZ
Order Options Tape and Reel: Add #TR
Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF
Lead Free Part Marking: http://www.linear.com/leadfree/
LTC4251/LTC4251-1/
LTC4251-2
3
425112fa
TEMPERATURE (°C)
–55
I
IN
(µA)
2000
1800
1600
1400
1200
1000
800
600
400
200
0–15 25 45 125
425112 G01
–35 5 65 85 105
V
IN
= (V
Z
– 0.3V)
V
IN
(V)
0 2 4 6 8 10 12 14 16 18 20 22
I
IN
(mA)
1000
100
10
1
0.1
425112 G02
T
A
= –40°C
T
A
= 125°C
T
A
= 25°C
T
A
= 85°C
TEMPERATURE (°C)
–55
rZ (Ω)
10
9
8
7
6
5
4
3
2–15 25 45 125
425112 G03
–35 5 65 85 105
IIN = 2mA
TYPICAL PERFOR A CE CHARACTERISTICS
UW
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
IIN vs Temperature IIN vs VIN rZ vs Temperature
ELECTRICAL CHARACTERISTICS
The ● denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Notes 2, 3)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
V
OVLO
OV Threshold Low LTC4251 ●5.25 5.55 5.85 V
LTC4251-1 ●5.61 5.91 6.21 V
V
OVHST
OV Hysteresis LTC4251 0.60 V
LTC4251-1 0.26 V
I
SENSE
SENSE Input Current UV/OV = 4V, V
SENSE
= 50mV ●–30 –15 µA
I
INP
UV/OV Input Current UV/OV = 4V ●±0.1 ±1µA
V
TMRH
Timer Voltage High Threshold 4V
V
TMRL
Timer Voltage Low Threshold 1V
I
TMR
Timer Current Timer On (Initial Cycle, Sourcing), V
TMR
= 2V 5.8 µA
Timer Off (Initial Cycle, Sinking), V
TMR
= 2V 28 mA
Timer On (Circuit Breaker, Sourcing), V
TMR
= 2V 230 µA
Timer Off (Cooling Cycle, Sinking), V
TMR
= 2V 5.8 µA
t
PLLUG
UV Low to GATE Low 0.7 µs
t
PHLOG
OV High to GATE Low LTC4251/LTC4251-1 1 µs
UV/OV = 4V refers to UV = 4V for the LTC4251-2.
Note 2: All currents into device pins are positive; all currents out of device
pins are negative. All voltages are referenced to V
EE
unless otherwise
specified.
Note 3: UV/OV = 4V refers to UV = 4V for the LTC4251-2.
LTC4251/LTC4251-1/
LTC4251-2
4
425112fa
Circuit Breaker Current Limit
Voltage VCB vs Temperature
Analog Current Limit Voltage VACL
vs Temperature
Fast Current Limit Voltage VFCL
vs Temperature
IGATE (Source) vs Temperature IGATE (ACL, Sink) vs Temperature IGATE (FCL, Sink) vs Temperature
TYPICAL PERFOR A CE CHARACTERISTICS
UW
TEMPERATURE (°C)
–55
V
CB
(mV)
60
58
56
54
52
50
48
46
44
42
40 –15 25 45 125
425112 G07
–35 5 65 85 105
TEMPERATURE (°C)
–55
VACL (V)
120
115
110
105
100
95
90
85
80 –15 25 45 125
425112 G08
–35 5 65 85 105
TEMPERATURE (°C)
–55
V
FCL
(mV)
300
275
250
225
200
175
150 –15 25 45 125
425112 G09
–35 5 65 85 105
TEMPERATURE (°C)
–55
I
GATE
(µA)
70
65
60
55
50
45
40 –15 25 45 125
425112 G10
–35 5 65 85 105
UV/0V = 4V
TIMER = 0V
V
SENSE
= V
EE
V
GATE
= 0V
TEMPERATURE (°C)
–55
IGATE (mA)
30
25
20
15
10
5
0–15 25 45 125
425112 G11
–35 5 65 85 105
UV/0V = 4V
TIMER = 0V
VSENSE – VEE = 0.15V
VGATE = 3V
TEMPERATURE (°C)
–55
IGATE (mA)
400
350
300
250
200
150
100
50
0–15 25 45 125
425112 G12
–35 5 65 85 105
UV/0V = 4V
TIMER = 0V
VSENSE – VEE = 0.3V
VGATE = 1V
UV/OV = 4V refers to UV = 4V for the LTC4251-2.
TEMPERATURE (°C)
–55
VZ (V)
14.5
14.0
13.5
13.0
12.5
12.0 –15 25 45 125
425112 G04
–35 5 65 85 105
IIN = 2mA
TEMPERATURE (°C)
–55
V
LKO
(V)
12.0
11.5
11.0
10.5
10.0
9.5
9.0
8.5
8.0 –15 25 45 125
425112 G05
–35 5 65 85 105
TEMPERATURE (°C)
–55
V
LKH
1.6
1.4
1.2
1
0.8
0.6
0.4
0.2
0–15 25 45 125
425112 G06
–35 5 65 85 105
VZ vs Temperature
Undervoltage Lockout VLKO vs
Temperature
Undervoltage Lockout Hysteresis
VLKH vs Temperature
LTC4251/LTC4251-1/
LTC4251-2
5
425112fa
OV Threshold vs Temperature
ISENSE vs Temperature ISENSE vs (VSENSE – VEE) TIMER Threshold vs Temperature
TYPICAL PERFOR A CE CHARACTERISTICS
UW
VGATE vs Temperature VGATEL vs Temperature UV Threshold vs Temperature
TEMPERATURE (°C)
–55
V
GATE
(V)
14.5
14.0
13.5
13.0
12.5
12.0
11.5
11.0
10.5
10.0 –15 25 45 125
425112 G13
–35 5 65 85 105
UV/0V = 4V
V
TMR
= 0V
V
SENSE
= V
EE
TEMPERATURE (°C)
–55
VGATEL (V)
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0–15 25 45 125
425112 G14
–35 5 65 85 105
UV/0V = 4V,
VTMR = 0V,
GATE THRESHOLD
BEFORE RAMP-UP
TEMPERATURE (°C)
–55
UV THRESHOLD (V)
3.375
3.275
3.175
3.075
2.975
2.875
2.775 –15 25 45 125
425112 G15
–35 5 65 85 105
VUVH
LTC4251/LTC4251-2
VUVL
TEMPERATURE (°C)
–55
OV THRESHOLD (V)
6.45
6.25
6.05
5.85
5.65
5.45
5.25 –15 25 45 125
425112 G17
–35 5 65 85 105
VOVH
LTC4251
VOVL
TEMPERATURE (°C)
–55
I
SENSE
(µA)
–10
–12
–14
–16
–18
–20
–22
–24
–26
–28
–30 –15 25 45 125
425112 G19
–35 5 65 85 105
UV/0V = 4V
TIMER = 0V
GATE = HIGH
V
SENSE
– V
EE
= 50mV
(VSENSE – VEE) (V)
–1.5 –1.0 –0.5 0 0.5 1.0 1.5 2.0
–ISENSE (mA)
0.01
0.1
1.0
10
100
1000
425112 G20
UV/0V = 4V
TIMER = 0V
GATE = HIGH
TA = 25°C
TEMPERATURE (°C)
–55
TIMER THRESHOLD (V)
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0–15 25 45 125
425112 G21
–35 5 65 85 105
VTMRH
VTMRL
TEMPERATURE (°C)
–55
UV THRESHOLD (V)
2.55
2.50
2.45
2.40
2.35
2.30
2.25
2.20
2.15
2.10
2.05 –15 25 45 125
425112 G16
–35 5 65 85 105
V
UVHI
LTC4251-1
V
UVLO
TEMPERATURE (°C)
–55
OV THRESHOLD (V)
6.51
6.41
6.31
6.21
6.11
6.01
5.91
5.81
5.71
5.61 –15 25 45 125
425112 G18
–35 5 65 85 105
V
OVHI
V
OVLO
LTC4251-1
UV Threshold vs Temperature OV Threshold vs Temperature
UV/OV = 4V refers to UV = 4V for the LTC4251-2.
LTC4251/LTC4251-1/
LTC4251-2
6
425112fa
ITMR (Cooling Cycle, Sinking)
vs Temperature
tPLLUG and tPHLOG
vs Temperature
TEMPERATURE (°C)
–55
I
TMR
(µA)
10
9
8
7
6
5
4
3
2
1
0–15 25 45 125
425112 G25
–35 5 65 85 105
TEMPERATURE (°C)
–55
DELAY (µs)
1.3
1.2
1.1
1.0
0.9
0.8
0.7
0.6
0.5 –15 25 45 125
425112 G26
–35 5 65 85 105
tPLLUG
tPHLOG (LTC4251/LTC4251-1)
TYPICAL PERFOR A CE CHARACTERISTICS
UW
ITMR (Initial Cycle, Sourcing) vs
Temperature
ITMR (Circuit Breaking, Sourcing)
vs Temperature
ITMR (Initial Cycle, Sinking) vs
Temperature
TEMPERATURE (°C)
–55
ITMR (µA)
10
9
8
7
6
5
4
3
2
1
0–15 25 45 125
425112 G22
–35 5 65 85 105
TEMPERATURE (°C)
–55
I
TMR
(mA)
50
45
40
35
30
25
20
15
10 –15 25 45 125
425112 G23
–35 5 65 85 105
TEMPERATURE (°C)
–55
I
TMR
(µA)
280
260
240
220
200
180 –15 25 45 125
425112 G24
–35 5 65 85 105
UV/OV = 4V refers to UV = 4V for the LTC4251-2.
LTC4251/LTC4251-1/
LTC4251-2
7
425112fa
If SENSE exceeds 50mV while GATE is high, a 230µA pull-
up current charges C
T
. If SENSE drops below 50mV before
TIMER reaches 4V, a 5.8µA pull-down current slowly
discharges C
T
. In the event that C
T
eventually integrates up
to the 4V V
TMRH
threshold, TIMER latches high with a
5.8µA pull-up source and GATE quickly pulls low. The
LTC4251/LTC4251-1/LTC4251-2 fault latches may be
cleared by either pulling TIMER low with an external
device, or by pulling UV/OV below V
UVLO
.
UV/OV (Pin 5): Undervoltage/Overvoltage Input. This dual
function pin detects undervoltage as well as overvoltage.
The high threshold at the UV comparator is set at V
UVHI
with V
UVHST
hysteresis. The high threshold at the OV
comparator is set at V
OVHI
with V
OVHST
hysteresis. If
UV/OV < V
UVLO
or UV/OV > V
OVHI
, GATE pulls low. If
UV/OV > V
UVHI
and UV/OV < V
OVLO
, the LTC4251/
LTC4251-1/LTC4251-2 attempt to start-up. The internal
UVLO at V
IN
always overrides UV/OV. A low at UV resets
an internal fault latch. A high at OV pulls GATE low but does
not reset the fault latch. A 1nF to 10nF capacitor at UV/OV
eliminates transients and switching noise from affecting
the UV/OV thresholds and prevents glitches at the GATE
pin.
GATE (Pin 6): N-Channel MOSFET Gate Drive Output. This
pin is pulled high by a 58µA current source. GATE is pulled
low by invalid conditions at V
IN
(UVLO), UV/OV, or the fault
latch. GATE is actively servoed to control fault current as
measured at SENSE. A compensation capacitor at GATE
stabilizes this loop. A comparator monitors GATE to
ensure that it is low before allowing an initial timing cycle,
GATE ramp up after an overvoltage event, or restart after
a current limit fault.
SENSE (Pin 1): Circuit Breaker/Current Limit SENSE Pin.
Load current is monitored by sense resistor R
S
connected
between SENSE and V
EE
, and controlled in three steps. If
SENSE exceeds V
CB
(50mV), the circuit breaker compara-
tor activates a 230µA TIMER pin pull-up current. The
LTC4251/LTC4251-1/LTC4251-2 latch off when C
T
charges
to 4V. If SENSE exceeds V
ACL
(100mV), the analog current
limit amplifier pulls GATE down and regulates the MOSFET
current at V
ACL
/R
S
. In the event of a catastrophic short-
circuit, SENSE may overshoot 100mV. If SENSE reaches
V
FCL
(200mV), the fast current limit comparator pulls
GATE low with a strong pull-down. To disable the circuit
breaker and current limit functions, connect SENSE to V
EE
.
Kelvin-sense connections between the sense resistor and
the V
EE
and SENSE pins are strongly recommended, see
Figure 6.
V
EE
(Pin 2): Negative Supply Voltage Input. Connect this
pin to the negative side of the power supply.
V
IN
(Pin 3): Positive Supply Input. Connect this pin to the
positive side of the supply through a dropping resistor. A
shunt regulator typically clamps V
IN
at 13V. An internal
undervoltage lockout (UVLO) circuit holds GATE low until
the V
IN
pin is greater than V
LKO
(9.2V), overriding UV/OV.
If UV is high, OV is low and V
IN
comes out of UVLO, TIMER
starts an initial timing cycle before initiating a GATE ramp
up. If V
IN
drops below approximately 8.2V, GATE pulls low
immediately.
TIMER (Pin 4): Timer Input. TIMER is used to generate a
delay at start up, and to delay shutdown in the event of an
output overload. TIMER starts an initial timing cycle when
the following conditions are met: UV is high, OV is low, V
IN
clears UVLO, TIMER pin is low, GATE is lower than V
GATEL
and V
SENSE
– V
EE
< V
CB
. A pull-up current of 5.8µA then
charges C
T
, generating a time delay. If C
T
charges to
V
TMRH
(4V) the timing cycle terminates, TIMER quickly
pulls low and GATE is activated.
UV/OV refers to the UV pin for the LTC4251-2. The OV comparator in the LTC4251-2 is disabled. All
references in the text to overvoltage, OV, VOVHI and VOVLO do not apply to the LTC4251-2.
PI FU CTIO S
UUU
LTC4251/LTC4251-1/
LTC4251-2
8
425112fa
Hot Circuit Insertion
When circuit boards are inserted into a live backplane, the
supply bypass capacitors can draw huge transient currents
from the power bus as they charge. The flow of current
damages the connector pins and glitches the power bus,
causing other boards in the system to reset. The LTC4251/
LTC4251-1/LTC4251-2 are designed to turn on a circuit
board supply in a controlled manner, allowing insertion or
removal without glitches or connector damage.
Initial Start-Up
The LTC4251/LTC4251-1/LTC4251-2 reside on a remov-
able circuit board and control the path between the con-
nector and load or power conversion circuitry with an
–
+
425112 BD
–
+
–
+
–
+
–
+
–
+
–
+
VIN VIN
VIN
VEE
VEE VEE
VEE
VEE
VEE
VEE
5.8µA
5.8µA
22µA
VIN
VIN
58µA
230µA
TIMER
VOVHI
VUVLO
4V
1V
LOGIC
+
–
+
–
VEE
VEE
VOS = 10mV
200mV
–
+
0.5V
UV/OV*
OV**
UV
GATE
SENSE
6
1
2
3
5
4
5k
CB
FCL
50mV
+
–
ACL
*UV FOR THE LTC4251-2
** THE OV COMPARATOR IS DISABLED FOR LTC4251-2
BLOCK DIAGRA
W
OPERATIO
U
Note that for simplicity, the following assumptions are made in the text. Firstly, UV/OV also means the UV
pin of the LTC4251-2. Secondly, all overvoltage conditions and references to OV, VOVHI and VOVLO do not apply to the LTC4251-2 as
the OV comparator in this part is disabled.
external MOSFET switch (see Figure 1). Both inrush con-
trol and short-circuit protection are provided by the
MOSFET.
A detailed schematic is shown in Figure 2. –48V and
–48RTN receive power through the longest connector
pins, and are the first to connect when the board is
inserted. The GATE pin holds the MOSFET off during this
time. UV/OV determines whether or not the MOSFET
should be turned on based upon internal, high-accuracy
thresholds and an external divider. UV/OV does double
duty by also monitoring whether or not the connector is
seated. The top of the divider detects –48RTN by way of a
short connector pin that is the last to mate during the
insertion sequence.
LTC4251/LTC4251-1/
LTC4251-2
9
425112fa
OPERATIO
U
Figure 1. Basic LTC4251 Hot Swap Topology
Figure 2. –48V, 2.5A Hot Swap Controller
425112 F01
LTC4251
C
LOAD
ISOLATED
DC/DC
CONVERTER
MODULE
LOW
VOLTAGE
CIRCUITRY
++
––
PLUG-IN BOARD
BACKPLANE
–48RTN
–48V
+
4
3
21 425112 F02
–48RTN
–48V
UV/OV
TIMER
V
EE
V
IN
SENSE GATE
LTC4251
R1
402k
1%
R2
32.4k
1% C
T
150nF
C
C
18nF
R
S
20mΩ
Q1
IRF530S
R
C
10Ω
R
IN
10k
500mW
C1
10nF
C
IN
1µF
C
L
100µF
TYP
LONG
LONG
SHORT
+
Interlock Conditions
A start-up sequence commences once five initial “inter-
lock” conditions are met:
1. The input voltage V
IN
exceeds 9.2V (V
LKO
)
2. The voltage at UV/OV falls within the range of V
UVHI
to
V
OVLO
(UV > V
UVHI
, LTC4251-2)
3. The (SENSE – V
EE
) voltage is <50mV (V
CB
)
4. The voltage on the timer capacitor (C
T
) is less than 1V
(V
TMRL
)
5. GATE is less than 0.5V (V
GATEL
)
The first two conditions are continuously monitored and
the latter three are checked prior to initial timing or GATE
ramp-up. Upon exiting an OV condition, the TIMER pin
voltage requirement is inhibited. Details are described in
the Applications Information, Timing Waveforms section.
TIMER begins the start-up sequence by sourcing 5.8µA
into C
T
. If V
IN
or UV/OV falls out of range, the start-up cycle
stops and TIMER discharges C
T
to less than 1V, then waits
until the aforementioned conditions are once again met. If
C
T
successfully charges to 4V, TIMER pulls low and GATE
is released. GATE sources 58µA (I
GATE
), charging the
MOSFET gate and associated capacitance.
Two modes of operation are possible during the time the
MOSFET is first turning on, depending on the values of
external components, MOSFET characteristics and nomi-
nal design current. One possibility is that the MOSFET will
turn on gradually so that the inrush into the load capaci-
tance remains a low value. The output will simply ramp to
–48V and the MOSFET will be fully enhanced. A second
possibility is that the load current exceeds the current limit
threshold of 100mV/R
S
. In this case, the LTC4251/
LTC4251-1/LTC4251-2 will ramp the output by sourcing
100mV/R
S
current into the load capacitance. It is impor-
tant to set the timer delay so that, regardless of which
start-up mode is used, the start-up time is less than the
TIMER delay time. If this condition is not met, the LTC4251/
LTC4251-1/LTC4251-2 may shut down after one TIMER
delay.
Board Removal
If the board is withdrawn from the card cage, the UV/OV
divider is the first to lose connection. This shuts off the
MOSFET and commutates the flow of current in the
connector. When the power pins subsequently separate,
there is no arcing.
Current Control
Three levels of protection handle short-circuit and over-
load conditions. Load current is monitored by SENSE and
resistor R
S
. There are three distinct thresholds at SENSE:
50mV for a timed circuit breaker function; 100mV for an
analog current limit loop; and 200mV for a fast, feedforward
comparator which limits peak current in the event of a
catastrophic short-circuit.
If, owing to an output overload, the voltage drop across R
S
exceeds 50mV, TIMER sources 230µA into C
T
. C
T
eventu-
ally charges to a 4V threshold and the LTC4251/LTC4251-1/
LTC4251-2 latch off. If the overload goes away and SENSE
measures less than 50mV, C
T
slowly discharges (5.8µA).
In this way the circuit breaker function will also respond to
low duty cycle overloads, and accounts for fast heating
and slow cooling characteristic of the MOSFET.
LTC4251/LTC4251-1/
LTC4251-2
10
425112fa
APPLICATIO S I FOR ATIO
WUUU
OPERATIO
U
Higher overloads are handled by an analog current limit
loop. If the drop across R
S
reaches 100mV, the current
limiting loop servos the MOSFET gate and maintains a
constant output current of 100mV/R
S
. Note that because
SENSE > 50mV, TIMER charges C
T
during this time and
the LTC4251/LTC4251-1/LTC4251-2 will eventually shut
down.
Low impedance failures on the load side of the LTC4251/
LTC4251-1/LTC4251-2 coupled with 48V or more driving
potential can produce current slew rates well in excess of
50A/µs. Under these conditions, overshoot is inevitable. A
fast SENSE comparator with a threshold of 200mV detects
overshoot and pulls GATE low much harder and hence
much faster than can the weaker current limit loop. The
100mV/R
S
current limit loop then takes over, and servos
the current as previously described. As before, TIMER
runs and latches the LTC4251/LTC4251-1/LTC4251-2 off
when C
T
reaches 4V.
The LTC4251/LTC4251-1/LTC4251-2 circuit breaker latch
is reset by either pulling UV/OV momentarily low, or drop-
ping the input voltage V
IN
below the internal UVLO threshold
of 8.2V.
Although short-circuits are the most obvious fault type,
several operating conditions may invoke overcurrent pro-
tection. Noise spikes from the backplane or load, input
steps caused by the connection of a second, higher
voltage supply, transient currents caused by faults on
adjacent circuit boards sharing the same power bus, or the
insertion of non-hot swappable products could cause
higher than anticipated input current and temporary de-
tection of an overcurrent condition. The action of TIMER
and C
T
rejects these events allowing the LTC4251/
LTC4251-1/LTC4251-2 to “ride out” temporary overloads
and disturbances that would trip a simple current com-
parator and in some cases, blow a fuse.
SHUNT REGULATOR
A fast responding regulator shunts the LTC4251/
LTC4251-1/LTC4251-2 V
IN
pin. Power is derived from
–48RTN by an external current limiting resistor. The shunt
regulator clamps V
IN
to 13V (V
Z
). A 1µF decoupling
capacitor at V
IN
filters supply transients and contributes a
short delay at start-up. A 10k 1/2W (R
IN
) resistor can be
two 5k 1/4W resistors in series.
INTERNAL UNDERVOLTAGE LOCKOUT (UVLO)
Internal circuitry monitors V
IN
for undervoltage. The exact
thresholds are defined by V
LKO
and its hysteresis, V
LKH
.
When V
IN
rises above 9.2V (V
LKO
) the chip is enabled;
below 8.2V (V
LKO
-V
LKH
) it is disabled and GATE is pulled
low. The UVLO function at V
IN
should not be confused with
the UV/OV pin. These are completely separate functions.
UV/OV COMPARATORS
Two hysteretic comparators for detecting under- and
overvoltage conditions, with the following thresholds,
monitor the dual function UV/OV pin:
UV turning on at V
UVHI
UV turning off at V
UVLO
OV turning off at V
OVHI
OV turning on at V
OVLO
The UV and OV trip point ratio for LTC4251 is designed to
match the standard telecom operating range of 43V to
75V. The LTC4251-2 implements a UV threshold of 43V
only.
A divider (R1, R2) is used to scale the supply voltage.
Using R1 = 402k and R2 = 32.4k gives a typical operating
range of 43.2V to 74.4V. The under- and overvoltage
shutdown thresholds are then 39.2V and 82.5V. 1%
divider resistors are recommended to preserve threshold
accuracy. The same resistor values can be used for the
LTC4251-2.
(Refer to Block Diagram)
LTC4251/LTC4251-1/
LTC4251-2
11
425112fa
1. 5.8µA slow charge; initial timing delay
2. 230µA fast charge; circuit breaker delay
3. 5.8µA slow discharge; circuit breaker “cool-off”
4. Low impedance switch; resets capacitor after initial
timing delay, in undervoltage lockout, and in overvolt-
age
For initial startup, the 5.8µA pull-up is used. The low
impedance switch is turned off and the 5.8µA current
source is enabled when the four interlock conditions are
met. C
T
charges to 4V in a time period given by:
tVC
A
T
=µ
4
58
•
.
(1)
When C
T
reaches 4V (V
TMRH
), the low impedance switch
turns on and discharges C
T
. The GATE output is enabled
and the load turns on.
CIRCUIT BREAKER TIMER OPERATION
If the SENSE pin detects more than 50mV across R
S
, the
TIMER pin charges C
T
with 230µA. If C
T
charges to 4V, the
GATE pin pulls low and the LTC4251/LTC4251-1/
LTC4251-2 latch off. The part remains latched off until
either the UV/OV pin is momentarily pulsed low, or V
IN
dips into UVLO and is then restored. The circuit breaker
timeout period is given by
tVC
A
T
=µ
4
230
•
(2)
Intermittent overloads may exceed the 50mV threshold at
SENSE, but if their duration is sufficiently short TIMER will
not reach 4V and the LTC4251/LTC4251-1/LTC4251-2
will not latch off. To handle this situation, the TIMER
discharges C
T
slowly with a 5.8µA pull-down whenever the
SENSE voltage is less than 50mV. Therefore any intermit-
tent overload with an aggregate duty cycle of 2.5% or more
will eventually trip the circuit breaker and latch off the
LTC4251/LTC4251-1/LTC4251-2. Figure 3 shows the cir-
cuit breaker response time in seconds normalized to 1µF.
The asymmetric charging and discharging of C
T
is a fair
gauge of MOSFET heating.
APPLICATIO S I FOR ATIO
WUUU
The R1-R2 divider values shown in the Typical Application
set a standing current of slightly more than 100µA, and
define an impedance at UV/OV of 30k. In most applica-
tions, 30k impedance coupled with 300mV UV hysteresis
makes the LTC4251/LTC4251-1/LTC4251-2 insensitive to
noise. If more noise immunity is desired, add a 1nF to 10nF
filter capacitor from UV/OV to V
EE
.
The UV and OV trip point thresholds for the LTC4251-1 are
designed to encompass the standard telecom operating
range of –36V to –72V.
A divider (R1, R2) is used to scale the supply voltage.
Using R1 = 442k and R2 = 34.8k gives a typical operating
range of 33.2V to 81V. The typical under- and overvoltage
shutdown thresholds are then 29.6V and 84.5V. 1%
divider resistors are recommended to preserve threshold
accuracy.
The R1-R2 divider values shown in the Typical Application
set a standing current of slightly more than 100µA, and
define an impedance at UV/OV of 32k. In most applica-
tions, 32k impedance coupled with 260mV UV hysteresis
makes the LTC4251-1 insensitive to noise. If more noise
immunity is desired, add a 1nF to 10nF filter capacitor from
UV/OV to V
EE
.
UV/OV OPERATION
A low input to the UV comparator will reset the chip and
pull the GATE and TIMER pins low. A low-to-high UV
transition will initiate an initial timing sequence if the three
remaining interlock conditions are met.
Overvoltage conditions detected by the OV comparator
will also pull GATE low, thereby shutting down the load,
but it will not reset the circuit breaker latch. Returning the
supply voltage to an acceptable range restarts the GATE
pin provided all interlock conditions except TIMER are
met.
TIMER
The operation of the TIMER pin is somewhat complex as
it handles several key functions. A capacitor, C
T
, is used at
TIMER to provide timing for the LTC4251/LTC4251-1/
LTC4251-2. Four different charging and discharging modes
are available at TIMER:
LTC4251/LTC4251-1/
LTC4251-2
12
425112fa
GATE
GATE is pulled low to V
EE
under any of the following
conditions: in UVLO, during the initial timing cycle, in an
overvoltage condition, or when the LTC4251/LTC4251-1/
LTC4251-2 are latched off after a short-circuit. When
GATE turns on, a 58µA current source charges the MOSFET
gate and any associated external capacitance. V
IN
limits
gate drive to no more than 14.5V.
Gate-drain capacitance (C
GD
) feed through at the first
abrupt application of power can cause a gate-source
voltage sufficient to turn on the MOSFET. A unique circuit
pulls GATE low with practically no usable voltage at V
IN
,
and eliminates current spikes at insertion. A large external
gate-source capacitor is thus unnecessary for the purpose
of compensating C
GD
. Instead, a smaller value (≥10nF)
capacitor C
C
is adequate. C
C
also provides compensation
for the analog current limit loop.
SENSE
The SENSE pin is monitored by the circuit breaker (CB)
comparator, the analog current limit (ACL) amplifier, and
the fast current limit (FCL) comparator. Each of these three
measures the potential of SENSE relative to V
EE
. If SENSE
exceeds 50mV, the CB comparator activates the 230µA
TIMER pull-up. At 100mV, the ACL amplifier servos the
MOSFET current, and at 200mV the FCL comparator
abruptly pulls GATE low in an attempt to bring the MOSFET
current under control. If any of these conditions persists
long enough for TIMER to charge C
T
to 4V (see Equa-
tion (2)), the LTC4251/LTC4251-1/LTC4251-2 latch off
and pull GATE low.
If the SENSE pin encounters a voltage greater than 100mV,
the ACL amplifier will servo GATE downwards in an
attempt to control the MOSFET current. Since GATE over-
drives the MOSFET in normal operation, the ACL amplifier
needs time to discharge GATE to the threshold of the
MOSFET. For a mild overload, the ACL amplifier can
control the MOSFET current, but in the event of a severe
overload the current may overshoot. At SENSE = 200mV,
the FCL comparator takes over, quickly discharging the
GATE pin to near V
EE
potential. FCL then releases, and the
ACL amplifier takes over. All the while TIMER is running.
The effect of FCL is to add a nonlinear response to the
control loop in favor of reducing MOSFET current.
Owing to inductive effects in the system, FCL typically
overcorrects the current limit loop, and GATE under-
shoots. A zero in the loop (resistor R
C
in series with the
gate capacitor) helps the ACL amplifier recover.
SHORT-CIRCUIT OPERATION
Circuit behavior arising from a load-side low impedance
short is shown in Figure 4. Initially, the current overshoots
the analog current limit level of V
SENSE
= 100mV (Trace 2)
as the GATE pin works to bring V
GS
under control (Trace 3).
The overshoot glitches the backplane in the negative
direction, and when the current is reduced to 100mV/R
S
the backplane responds by glitching in the positive
direction.
TIMER commences charging C
T
(Trace 4) while the analog
current limit loop maintains the fault current at 100mV/R
S
,
which in this case is 5A (Trace 2). Note that the backplane
voltage (Trace 1) sags under load. When C
T
reaches 4V,
GATE turns off, the load current drops to zero and the
backplane rings up to over 100V. The positive peak is
usually limited by avalanche breakdown in the MOSFET,
and can be further limited by adding a zener diode across
the input from – 48V to – 48RTN, such as Diodes Inc.
SMAT70A.
A low-impedance short on one card may influence the
behavior of others sharing the same backplane. The initial
glitch and backplane sag as seen in Figure 4, Trace 1, can
rob charge from output capacitors on adjacent cards. When
the faulty card shuts down, current flows in to refresh the
APPLICATIO S I FOR ATIO
WUUU
FAULT DUTY CYCLE, D (%)
20 40 60 800
NORMALIZED RESPONSE TIME (s/µF)
10
1
0.1
0.01 100
425112 F03
t
C
T
(µF)
4
(235.8 • D) – 5.8
=
Figure 3. Circuit Breaker Response Time
LTC4251/LTC4251-1/
LTC4251-2
13
425112fa
APPLICATIO S I FOR ATIO
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capacitors. If LTC4251, LTC4251-1 or
LTC4251-2s
are
used throughout, they respond by limiting the inrush cur-
rent to a value of 100mV/R
S
. If C
T
is sized correctly, the
capacitors will recharge long before C
T
times out.
where 40mV represents the guaranteed minimum circuit
breaker threshold.
During the initial charging process, the LTC4251/
LTC4251-1/LTC4251-2 may operate the MOSFET in cur-
rent limit, forcing 80mV to 120mV across R
S
. The mini-
mum inrush current is given by:
ImV
R
INRUSH MIN S
()
=80
(4)
Maximum short-circuit current limit is calculated using
maximum V
SENSE
, or:
ImV
R
SHORT CIRCUIT MAX S
−
=
()
120
(5)
The TIMER capacitor C
T
must be selected based on the
slowest expected charging rate; otherwise TIMER might
time out before the load capacitor is fully charged. A value
for C
T
is calculated based on the maximum time it takes the
load capacitor to charge. That time is given by:
tCV
I
CV
I
CL CHARGE L SUPPLY MAX
INRUSH MIN
==
••
()
()
(6)
Substituting Equation (4) for I
INRUSH(MIN)
and equating
(6) with (2) gives:
CCV R A
VmV
TL SUPPLY MAX S
=µ•••
(• )
() 230
480
(7)
Returning to Equation (2), the TIMER period is calculated
and used in conjunction with V
SUPPLY(MAX)
and
I
SHORT-CIRCUIT(MAX)
to check the SOA curves of a prospec-
tive MOSFET.
As a numerical design example, consider a 30W load,
which requires 1A input current at 36V. If V
SUPPLY(MAX)
=
72V and C
L
= 100µF, Equation (3) gives R
SENSE
= 40mΩ;
Equation (7) gives C
T
= 207nF. To account for errors in
R
SENSE
, C
T
, TIMER current (230µA) and TIMER threshold
(4V), the calculated value should be multiplied by 1.5,
giving a nearest standard value of C
T
= 330nF.
If a short-circuit occurs, a current of up to 120mV/40mΩ
= 3A will flow in the MOSFET for 5.7ms as dictated by
GATE
10V/DIV
SENSE
200mV/DIV
–48RTN
50V/DIV
TIMER
5V/DIV
425112 F04
SUPPLY RING
OWING
TO CURRENT
OVERSHOOT
SUPPLY RING
OWING TO
MOSFET
TURN-OFF
ONSET OF OUTPUT
SHORT-CIRCUIT
FAST CURRENT
LIMIT
ANALOG
CURRENT LIMIT
CTIMER RAMP
LATCH OFF
TRACE 1
TRACE 2
TRACE 3
TRACE 4
2ms/DIV
Figure 4. Output Short-Circuit Behavior
(All Waveforms are Referenced to VEE)
MOSFET SELECTION
The external MOSFET switch must have adequate safe
operating area (SOA) to charge the load capacitance on
start-up and handle short-circuit conditions until TIMER
latchoff. These considerations take precedence over DC
current ratings. A MOSFET with adequate SOA for a given
application can always handle the required current, but the
opposite cannot be said. Consult the manufacturer’s MOSFET
data sheet for safe operating area and effective transient
thermal impedance curves.
MOSFET selection is a three-step process. First, R
S
is
calculated, and then the time required to charge the load
capacitance is determined. This timing, along with the
maximum short-circuit current and maximum input voltage
defines an operating point that is checked against the
MOSFET’s SOA curve.
To begin a design, first specify the required load current and
load capacitance, I
L
and C
L
. The circuit breaker current trip
point (50mV/R
S
) should be set to accommodate the maxi-
mum load current. Note that maximum input current to a
DC/DC converter is expected at V
SUPPLY (MIN)
. R
S
is given
by:
RmV
I
SL MAX
=40
()
(3)
LTC4251/LTC4251-1/
LTC4251-2
14
425112fa
W
CURRENT FLOW
FROM LOAD
CURRENT FLOW
TO –48V BACKPLANE
SENSE RESISTOR
TRACK WIDTH W:
0.03" PER AMP
ON 1 OZ COPPER
TO
SENSE
TO
VEE
425112 F06
Figure 6. Making PCB Connections to the Sense Resistor
APPLICATIO S I FOR ATIO
WUUU
Figure 5. Recommended Compensation
Capacitor CC vs MOSFET CISS
MOSFET CISS (pF)
COMPENSATION CAPACITOR CC (nF)
425112 F05
60
50
40
30
20
10
002000 4000 6000 8000
IRF530
IRF540
IRF740
IRF3710
MTY100N10E
C
T
= 330nF in Equation (2). The MOSFET must be selected
based on this criterion. The IRF530S can handle 100V and
3A for 10ms, and is safe to use in this application.
SUMMARY OF DESIGN FLOW
To summarize the design flow, consider the application
shown in Figure 2, which was designed for 50W:
Calculate maximum load current: 50W/36V = 1.4A; allow-
ing 83% converter efficiency, I
IN (MAX)
= 1.7A.
Calculate R
S
: from Equation (3) R
S
= 20mΩ.
Calculate C
T
: from Equation (7) C
T
= 150nF (including 1.5X
correction factor).
Calculate TIMER period: from Equation (2) the short-
circuit time-out period is t = 2.6ms.
Calculate maximum short-circuit current: from Equation
(5) maximum short-circuit current could be as high as
120mV/20mΩ = 6A.
Consult MOSFET SOA curves: the IRF530S can handle 6A
at 72V for 5ms, so it is safe to use in this application.
FREQUENCY COMPENSATION
The LTC4251/LTC4251-1/LTC4251-2 typical frequency
compensation network for the analog current limit loop is
a series R
C
(10Ω) and C
C
connected to V
EE
. Figure 5
depicts the relationship between the compensation ca-
pacitor C
C
and the MOSFET’s C
ISS
. The line in Figure 5 is
used to select a starting value for C
C
based upon the
MOSFET’s C
ISS
specification. Optimized values for C
C
are
shown for several popular MOSFETs. Differences in the
optimized value of C
C
versus the starting value are small.
Nevertheless, compensation values should be verified by
board level short-circuit testing.
As seen in Figure 4 previously, at the onset of a short-
circuit event, the input supply voltage can ring dramati-
cally owing to series inductance. If this voltage avalanches
the MOSFET, current continues to flow through the MOSFET
to the output. The analog current limit loop cannot control
this current flow and therefore the loop undershoots. This
effect cannot be eliminated by frequency compensation. A
zener diode is required to clamp the input supply voltage
and prevent MOSFET avalanche.
SENSE RESISTOR CONSIDERATIONS
For proper circuit breaker operation, Kelvin-sense PCB
connections between the sense resistor and the V
EE
and
SENSE pins are strongly recommended. The drawing in
Figure 6 illustrates the correct way of making connections
between the LTC4251/LTC4251-1/LTC4251-2 and the
sense resistor. PCB layout should be balanced and sym-
metrical to minimize wiring errors. In addition, the PCB
layout for the sense resistor should include good thermal
management techniques for optimal sense resistor power
dissipation.
TIMING WAVEFORMS
System Power-Up
Figure 7 details the timing waveforms for a typical power-
up sequence in the case where a board is already installed
in the backplane and system power is applied abruptly. At
time point 1, the supply ramps up, together with UV/OV
LTC4251/LTC4251-1/
LTC4251-2
15
425112fa
APPLICATIO S I FOR ATIO
WUUU
and V
OUT
. V
IN
follows at a slower rate as set by the V
IN
bypass capacitor. At time point 2, V
IN
exceeds V
LKO
and
the internal logic checks for V
UVHI
< UV/OV < V
OVLO
,
TIMER < V
TMRL
, GATE < V
GATEL
and SENSE < V
CB
. When
all conditions are met, an initial timing cycle starts and the
TIMER capacitor is charged by a 5.8µA current source
pull-up. At time point 3, TIMER reaches the V
TMRH
thresh-
old and the initial timing cycle terminates. The TIMER
capacitor is then quickly discharged. At time point 4, the
V
TMRL
threshold is reached and the conditions of GATE <
V
GATEL
and SENSE < V
CB
must be satisfied before a start-
up cycle is allowed to begin. GATE sources 58µA into the
external MOSFET gate and compensation network. When
the GATE voltage reaches the MOSFET’s threshold,
current begins flowing into the load capacitor. At time
point 5, the SENSE voltage (V
SENSE
– V
EE
) reaches the V
CB
threshold and activates the TIMER. The TIMER capacitor
is charged by a 230µA current-source pull-up. At time
point 6, the analog current limit loop activates. Between
time point 6 and time point 7, the GATE voltage is held
essentially constant and the sense voltage is regulated at
V
ACL
. As the load capacitor nears full charge, its current
begins to decline. At point 7, the load current falls and the
sense voltage drops below V
ACL
. The analog current limit
loop shuts off and the GATE pin ramps further. At time
point 8, the sense voltage drops below V
CB
and TIMER
now discharges through a 5.8µA current source pull-
down. At time point 9, GATE reaches its maximum voltage
as determined by V
IN
.
Live Insertion with Short Pin Control of UV/OV
In this example as shown in Figure 8, power is delivered
through long connector pins whereas the UV/OV divider
makes contact through a short pin. This ensures the power
connections are firmly established before the LTC4251/
LTC4251-1/LTC4251-2 are activated. At time point 1, the
power pins make contact and V
IN
ramps through V
LKO
. At
time point 2, the UV/OV divider makes contact and its
voltage exceeds V
UVHI
. In addition, the internal logic
checks for V
UVHI
< UV/OV < V
OVHI
, TIMER < V
TMRL
, GATE
< V
GATEL
and SENSE < V
CB
. When all conditions are met,
an initial timing cycle starts and the TIMER capacitor is
charged by a 5.8µA current source pull-up. At time point
3, TIMER reaches the V
TMRH
threshold and the initial
timing cycle terminates. The TIMER capacitor is then
quickly discharged. At time point 4, the V
TMRL
threshold is
reached and the conditions of GATE < V
GATEL
and SENSE
< V
CB
must be satisfied before a start-up cycle is allowed
to begin. GATE sources 58µA into the external MOSFET
gate and compensation network. When the GATE voltage
reaches the MOSFET’s threshold, current begins flowing
into the load capacitor. At time point 5, the SENSE voltage
(V
SENSE
– V
EE
) reaches the V
CB
threshold and activates the
TIMER. The TIMER capacitor is charged by a 230µA
current source pull-up. At time point 6, the analog current
limit loop activates. Between time point 6 and time point 7,
the GATE voltage is held essentially constant and the
sense voltage is regulated at V
ACL
. As the load capacitor
nears full charge, its current begins to decline. At time
point 7, the load current falls and the sense voltage drops
below V
ACL
. The analog current limit loop shuts off and the
GATE pin ramps further. At time point 8, the sense voltage
drops below V
CB
and TIMER now discharges through a
5.8µA current source pull-down. At time point 9, GATE
reaches its maximum voltage as determined by V
IN
.
Undervoltage Lockout Timing
In Figure 9, when UV/OV drops below V
UVLO
(time point 1),
TIMER and GATE pull low. If current has been flowing, the
SENSE pin voltage decreases to zero as GATE collapses.
When UV/OV recovers and clears V
UVHI
(time point 2), an
initial time cycle begins followed by a start-up cycle.
Undervoltage Timing with Overvoltage Glitch
In Figure 10, when UV/OV clears V
UVHI
(time point 1), an
initial timing cycle starts. If the system bus voltage over-
shoots V
OVHI
as shown at time point 2, TIMER discharges.
At time point 3, the supply voltage recovers and drops
below the V
OVLO
threshold. The initial timing cycle restarts
followed by a start-up cycle.
Overvoltage Timing
During normal operation, if UV/OV exceeds V
OVHI
as
shown at time point 1 of Figure 11, the TIMER status is
unaffected. Nevertheless, GATE pulls down and discon-
nects the load. At time point 2, UV/OV recovers and drops
below the V
OVLO
threshold. A gate ramp up cycle ensues.
LTC4251/LTC4251-1/
LTC4251-2
16
425112fa
If the overvoltage glitch is long enough to deplete the load
capacitor, a full start-up cycle may occur as shown be-
tween time points 3 through 6.
Figure 7. System Power-Up Timing (All Waveforms are Referenced to VEE)
Figure 8. Power-Up Timing with a Short-Pin (All Waveforms are Referenced to VEE)
APPLICATIO S I FOR ATIO
WUUU
132456789
VIN CLEARS VLKO, CHECK VUVHI <UV/0V < VOVLO, TIMER< VTMRL, GATE < VGATEL AND SENSE < VCB.
TIMER CLEARS VTMRL, CHECK GATE < VGATEL AND SENSE < VCB.
GND-VEE
UV/0V
VIN
TIMER
GATE
SENSE
VOUT
VLKO
VTMRH
VTMRL
VACL
VCB
5.8µA5.8µA
5.8µA
INITIAL TIMING CYCLE START-UP CYCLE
425112 F07
230µA
58µA
58µA
132456789
UV/0V CLEARS VUVHI, CHECK VIN < VLKO – VLKH, TIMER < VTMRL, GATE < VGATEL AND SENSE < VCB.
TIMER CLEARS VTMRL, CHECK GATE < VGATEL AND SENSE < VCB.
GND-VEE
UV/0V
VIN
TIMER
GATE
SENSE
VOUT
VUVHI
VLKO
VTMRH
VTMRL
VACL
VCB
5.8µA5.8µA
5.8µA
INITIAL TIMING CYCLE START-UP CYCLE
425112 F08
230µA
58µA
58µA
Timer Behavior
In Figure 12a, the TIMER capacitor charges at 230µA if the
SENSE pin exceeds V
CB
. It is discharged with 5.8µA if the
LTC4251/LTC4251-1/
LTC4251-2
17
425112fa
APPLICATIO S I FOR ATIO
WUUU
Figure 9. Undervoltage Lockout Timing (All Waveforms are Referenced to VEE)
Figure 10. Undervoltage Timing with an Overvoltage Glitch (All Waveforms are Referenced to VEE)
132456789
V
UV/0V
CLEARS V
UVHI
, CHECK TIMER < V
TMRL
, GATE < V
GATEL
AND SENSE < V
CB
.
V
UV/0V
DROPS BELOW V
UVLO
. TIMER, GATE, AND SENSE ARE PULLED TO V
EE
.
TIMER CLEARS V
TMRL
, CHECK GATE < V
GATEL
AND SENSE < V
CB
.
V
UVHI
V
UVLO
V
TMRH
V
TMRL
V
ACL
V
CB
5.8µA230µA
58µA
58µA
5.8µA5.8µA
INITIAL TIMING CYCLE START-UP CYCLE
425112 F09
UV/0V
TIMER
GATE
SENSE
132456789
VUV/0V DROPS BELOW VOVLO AND TIMER RESTARTS INITIAL TIMING CYCLE.
VUV/0V CLEARS VUVHI. CHECK TIMER < VTMRL, GATE < VGATEL AND SENSE < VCB.
VUV/0V OVERSHOOTS VOVHI AND TIMER ABORTS INITIAL TIMING CYCLE.
TIMER CLEARS VTMRL, CHECK GATE < VGATEL AND SENSE < VCB.
VOVHI
VUVHI
VOVLO
VTMRH
VTMRL
VACL
VCB
5.8µA230µA
58µA
58µA
5.8µA5.8µA
INITIAL TIMING CYCLE START-UP CYCLE
425112 F10
UV/0V
TIMER
GATE
SENSE
10
SENSE pin is less than V
CB
. In Figure 12b, when TIMER
exceeds V
TMRH
, TIMER is latched high by the 5.8µA pull-
up and GATE pulls down immediately. In Figure 12c,
multiple momentary faults cause the TIMER capacitor to
integrate until it latches.
Analog Current Limit and Fast Current Limit
In Figure 13a, when SENSE exceeds V
ACL
, GATE is regu-
lated by the analog current limit amplifier loop. When
SENSE drops below V
ACL
, GATE is allowed to pull up. In
Figure 13b, when a severe fault occurs, SENSE exceeds
V
FCL
and GATE immediately pulls down until the analog
current amplifier can establish control. If TIMER reaches
V
TMRH
, GATE pulls low and latches off.
Resetting a Fault Latch
As shown in Figure 14, a latched fault is reset by either
pulling UV/OV below V
UVLO
or pulling TIMER below V
TMRL
.
An initial timing cycle is initiated if UV/OV is used for reset.
If TIMER is used for reset, the initial timing cycle is skipped.
Internal Soft-Start
An internal soft-start feature ramps the positive input of
the analog current limit amplifier during initial start-up.
LTC4251/LTC4251-1/
LTC4251-2
18
425112fa
Figure 13. Current Limit Behavior (All Waveforms are Referenced to VEE)
TIMER
GATE
SENSE
VOUT
VACL
VTMRH
VCB
58µA
5.8µA
5.8µA
1432
230µA
425112 F13a
TIMER
GATE
SENSE
V
OUT
V
FCL
V
ACL
V
TMRH
V
CB
5.8µA
230µA
12
TIMER LATCHES OFF
425112 F13b
(13a) Analog Current Limit Fault (13b) Fast Current Limit Fault
TIMER
GATE
SENSE
V
OUT
V
ACL
V
TMRL
V
CB
5.8µA
5.8µA
CB FAULT
230µA
12
425112 F12a
TIMER
GATE
SENSE
V
OUT
V
ACL
V
TMRH
V
CB
5.8µA
CB FAULT
230µA
12
TIMER LATCHES OFF
425112 F12b
TIMER
GATE
SENSE
V
OUT
V
ACL
V
TMRH
V
CB
5.8µA
5.8µA230µA
230µA
1432
TIMER LATCHES OFF
425112 F12c
(12a) Momentary Circuit-Breaker Fault (12b) Circuit-Breaker Time-Out
Figure 12. Timer Behavior (All Waveforms are Referenced to VEE)
(12c) Multiple Circuit-Breaker Faults
APPLICATIO S I FOR ATIO
WUUU
1324567
UV/0V
TIMER
GATE
SENSE
VOVHI
VTMRH
VOVLO
VACL
VCB
5.8µA5.8µA5.8µA
5.8µA
425112 F11
230µA
58µA
58µA
VUV/0V DROPS BELOW VOVLO AND GATE RESTARTS.
VUV/0V OVERSHOOTS VOVHI AND GATE PULLS TO VEE. TIMER UNAFFECTED.
Figure 11. Overvoltage Timing (All Waveforms are Referenced to VEE)
The ramp duration is approximately 200µs. This feature
reduces load current dl/dt at start-up. As illustrated in
Figure 15, soft-start is initiated by a TIMER transition from
V
TMRH
to V
TMRL
or when UV/OV falls below the V
OVLO
threshold after an OV fault. After soft-start duration, load
current is limited by V
ACL
/R
S
.
LTC4251/LTC4251-1/
LTC4251-2
19
425112fa
APPLICATIO S I FOR ATIO
WUUU
Figure 14. Latched Fault Reset Timing
(All Waveforms are Referenced to VEE)
Figure 15. Internal Soft-Start Timing
(All Waveforms are Referenced to VEE)
TIMER
GATE
SENSE
V
ACL
V
TMRH
V
TMRL
V
CB
5.8µA
5.8µA
5.8µA
156432
230µA
58µA
58µA
RESET LATCHED TIMER FAULT BY EXTERNAL LOW PULSE.
425112 F14
TIMER
GATE
SENSE
V
ACL
V
ACL
+ 10mV
V
TMRH
V
TMRL
~V
GS(th)
V
CB
5.8µA
145 632
230µA
INTERNAL
SOFT-START
REFERENCE
58µA
10mV
END OF INITIAL TIMING CYCLE
425112 F15
PACKAGE DESCRIPTIO
U
S6 Package
6-Lead Plastic TSOT-23
(Reference LTC DWG # 05-08-1636)
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
1.50 – 1.75
(NOTE 4)
2.80 BSC
0.30 – 0.45
6 PLCS (NOTE 3)
DATUM ‘A’
0.09 – 0.20
(NOTE 3)
S6 TSOT-23 0302
2.90 BSC
(NOTE 4)
0.95 BSC
1.90 BSC
0.80 – 0.90
1.00 MAX 0.01 – 0.10
0.20 BSC
0.30 – 0.50 REF
PIN ONE ID
NOTE:
1. DIMENSIONS ARE IN MILLIMETERS
2. DRAWING NOT TO SCALE
3. DIMENSIONS ARE INCLUSIVE OF PLATING
4. DIMENSIONS ARE EXCLUSIVE OF MOLD FLASH AND METAL BURR
5. MOLD FLASH SHALL NOT EXCEED 0.254mm
6. JEDEC PACKAGE REFERENCE IS MO-193
3.85 MAX
0.62
MAX
0.95
REF
RECOMMENDED SOLDER PAD LAYOUT
PER IPC CALCULATOR
1.4 MIN
2.62 REF
1.22 REF
LTC4251/LTC4251-1/
LTC4251-2
20
425112fa
+
LTC4251-1
UV/OV
TIMER
GATE
SENSE
V
IN
V
EE
1
2
3
4
56
LOAD
GND
GND
(SHORT PIN)
R1
442k
1%
R
C
10ΩR
S
0.02Ω
R2
34.8k
1%
V
SUPPLY
= –48V
C
T
220nF
C1
10nF
C
C
22nF
C
IN
1µF
D1
BZX84C36
C
L
100µF
R
IN
10k
500mW
R3
31.6k
R4
22Ω
V
OUT
Q1
IRF540S
425112 TA04
4
3
2
1
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900
●
FAX: (408) 434-0507
●
www.linear.com
© LINEAR TECHNOLOGY CORPORATION 2001
LT 0406 REV A • PRINTED IN USA
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Figure 16. –48V/5A Application with Reverse
SENSE Pin Limiting and Push-Reset at TIMER Pin
+
LTC4251
UV/OV
TIMER
GATE
SENSE
VIN
VEE
1
2
3
4
56
LOAD
GND
GND
(SHORT PIN)
R1
402k
1%
RC
10ΩRS
0.01Ω
R3
22Ω
R2
32.4k
1%
–48V
CT
82nF
C1
10nF
CC
22nF
CIN
1µF
CL
100µF
RIN
10k
500mW
Q1
IRF540
425112 TA03
PUSH-
RESET S1
4
3
2
1
Figure 17. Power-Limited Circuit Breaker Application
TYPICAL APPLICATIO S
U
