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© 2005 Fairchild Semiconductor Corporation DS005760 www.fairchildsemi.com
Februa ry 198 4
Revised May 2005
MM74HCT273 Octal D-Type Flip-Flop with Clear
MM74HCT273
Octal D-Type Flip-Flop with Clear
General Descript ion
The MM74HCT273 utilizes advanced silicon-gate CMOS
technology. It has an input threshold and output drive simi-
lar to LS-TTL with the low standby power of CMOS.
These positive edge-triggered flip-flops have a common
clock and clear- indepe ndent Q outp uts. Data on a D input,
having the specified set-up an d hold time, is tra nsferred to
the corresp onding Q out put o n th e po siti ve- goin g tr ans it ion
of the clock pulse. The asynchronous clear forces a ll out-
puts LOW when it is LOW.
All inputs to this device are protec ted from dama ge due to
electrostatic discharge by diodes to VCC and ground.
MM74HCT devices are intended to interface TTL and
NMOS components to CMOS components. These parts
can be used as plug-in replacements to reduce system
power consumption in existing designs.
Features
■Typical propagation delay: 20 ns
■Low quiescent current: 80
P
A maximum (74HC T series)
■Fanout of 10 LS-TTL loads
Ordering Code:
Devices also available in Tape and R eel. Sp ec if y by appending the suffix lett er “X” to the orde ring code.
Connection Diagram
Pin Assignments for DIP, SOI C, SOP and TSSOP
Top View
Orde r Number Package
Number Packag e Desc ri ption
MM74HCT273WM M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
MM74HCT273SJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
MM74HCT273MTC MTC20 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
MM7 4HCT273N N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001 , 0.300" W ide
www.fairchildsemi.com 2
MM74HCT273
Truth Table (Each Flip-Flop)
H
HIGH Level (steady-state)
L
LOW Level (steady-state)
X
Don’t Care
n
Tra nsition from LOW-to-HIGH level
Q0
The level of Q before the indicated steady-state input
conditions were established.
Logic Diagram
Inputs Outputs
Clear Clock D Q
LXXL
H
n
HH
H
n
LL
HLXQ0
3 www.fairchildsemi.com
MM74HCT273
Absolute Maxim um Ratings(Note 1)
(Note 2) Recommended Operating
Conditions
Note 1: Absolute Maximum Ratings are those values beyond which dam-
age to the device may occur.
Note 2: Unl es s ot herwise spe c if ied all voltages are referenced to ground.
Note 3: Power diss ipation tem per ature der ating—plastic “N” package:
12
mW/
q
C from 65
q
C to 85
q
C.
DC Electrical Characteristics
VCC
5V
r
10% unless otherwise specified
Note 4: Measured per pin, all other inputs held at VCC or GND.
Supply Voltage (VCC)
0.5V to
7.0V
DC Input Voltage (VIN)
1.5V to VCC
1.5V
DC Output Voltage (VOUT)
0.5V to VCC
0.5V
Clamp Diode Current (IIK, IOK)
r
20 mA
DC Output Current, per Pin (IOUT)
r
25 mA
DC VCC or GND Current, per Pin (ICC)
r
50 mA
Storage Temperature Range (TSTG)
65
q
C to
150
q
C
Power Dissipation (PD)
(Note 3) 600 mW
S.O. Package only 500 mW
Lead Temperature (TL)
(Soldering, 10 seconds) 260
q
C
Min Max Units
Supply Voltage (VCC)4.55.5V
DC Input or Output Voltage
(VIN, VOUT)0V
CC V
Operati ng Tem per atu re R ang e (TA)
40
85
q
C
Input Rise or Fall Times
(tr, tf) 500 ns
Symbol Parameter Conditions TA
25
q
CT
A
40
q
C to 85
q
CT
A
55
q
C to 125
q
CUnits
Typ Guaranteed Limits
VIH Minimum HIGH Level 2.0 2.0 2.0 V
Input V olt age
VIL Maximum LOW Level 0.8 0.8 0.8 V
Input V olt age
VOH Minimum HIGH Level VIN
VIH or VIL
Output Voltage |IOUT|
20
P
AV
CC VCC
0.1 VCC
0.1 VCC
0.1 V
|IOUT|
4.0 mA, VCC
4.5V 4.2 3.98 3.84 3.7 V
|IOUT|
4.8 mA, VCC
5.5V 5.2 4.98 4.84 4.7 V
VOL Minimum LOW Level VIN
VIH or VIL
Voltage |IOUT|
20
P
A 0 0.1 0.1 0.1 V
|IOUT|
4.0 mA, VCC
4.5V 0.2 0.26 0.33 0.4 V
|IOUT|
4.8 mA, VCC
5.5V 0.2 0.26 0.33 0.4 V
IIN Maximum Input VIN
VCC or GND,
r
0.1
r
1.0
r
1.0
P
A
Current VIH or VIL
ICC Maximum Quiescent VIN
VCC or GND 8 80 160
P
A
Supply Current IOUT
0
P
A
VIN
2.4V or 0.5V (Note 4) 0.6 0.8 0.9 mA
www.fairchildsemi.com 4
MM74HCT273
AC Electrical Characteristics
VCC
5V, TA
25
q
C, CL
15 pF, tr
tf
6 ns
AC Electrical Characteristics
VCC
5.0V
r
10%, CL
50 pF, tr
tf
6 ns unless otherwise specified
Note 5: CPD determines the no load dy namic powe r c onsumptio n, PD
CPD VCC2 f
ICC VCC, and t he no load dy namic curre nt c onsumptio n,
IS
CPD VCC2 f
ICC.
Symbol Parameter Conditions Typ Guaranteed Units
Limits
fMAX Maximum Operating Frequency 68 30 MHz
tPHL, tPLH Maximum Propagation Delay from Clock to Q 18 30 ns
tPHL, tPLH Maximum Propagation Delay from Clear to Q 21 30 ns
tREM Minimum Removal Time, Clear to Clock
15ns
tSMinimum Set-Up Time D to Clock 6 20 ns
tHMinimum Hold Time Clock to D
35ns
tWMinimum Pulse Width Clock or Clear 10 16 ns
Symbol Parameter Conditions TA
25
q
CT
A
40
q
C to 85
q
CT
A
55
q
C to 125
q
CUnits
Typ Guaranteed Limits
fMAX Maximum Operating 68 27 21 18 MHz
Frequency
tPHL, tPLH Maximum Propagation 22 37 46 56 ns
Delay from Clock to Q
tPHL, tPLH Maximum Propagation 25 35 44 52 ns
Delay from Clear to Q
tREM Minimum Removal
15 6 7 ns
Time Clear to Clock
tSMinimum Set-Up Time 6 20 25 30 ns
D to Clock
tHMinimum Hold Time
35 5 5 ns
Clock to D
tWMinimum Pulse Width 10 16 25 30 ns
Clock or Clear
tr, tfMaximum Input Rise 500 500 500 ns
and Fall Time, Clock
tTHL, tTLH Maximum Output Rise 11 15 19 22 ns
and Fall Time
CPD Power Dissipation (Per Flip-Flop) 50 pF
Capacitance (Note 5)
CIN Maximum Input 6 10 10 10 pF
Capacitance
5 www.fairchildsemi.com
MM74HCT273
Physical Dim ensions inches (millimeters) unless otherwise noted
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
Package Number M20B
www.fairchildsemi.com 6
MM74HCT273
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Small Outline Package (SOP ), EIAJ TYPE II, 5.3mm W ide
Package Number M20D
7 www.fairchildsemi.com
MM74HCT273
Physical Dim ensions inches (millimeters) unless otherwise noted (Continued)
20-Lea d Th in S hri nk Sm all Ou tlin e Pack age (TSSOP), JED EC MO-1 53, 4.4mm Wide
Package Number MTC20
www.fairchildsemi.com 8
MM74HCT273 Octal D-Type Flip-Flop with Clear
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Package Number N20A
Fairchild does no t assume any responsibility for use of any circui try described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life suppor t de vices o r systems a re devices or syste ms
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical compon ent in any componen t of a life support
device or system whose failure to perform can be rea-
sonabl y ex pect ed to cause the fa ilu re of the lif e su pp ort
device or system, or to affect it s safety or effectiveness.
www.fairchildsemi.com
www.onsemi.com
1
ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent
coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein.
ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards,
regardless of any support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON Semiconductor data sheets and/or
specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer
application by customer’s technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not
designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification
in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use ON Semiconductor products for any such unintended or unauthorized
application, Buyer shall indemnify and hold ON Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and
expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such
claim alleges that ON Semiconductor was negligent regarding the design or manufacture of the part. ON Semiconductor is an Equal Opportunity/Affirmative Action Employer. This
literature is subject to all applicable copyright laws and is not for resale in any manner.
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