Februa ry 198 4
Revised February 1999
MM74HC4020 • MM74HC4040 14-Stage Binary Counter • 12-Stage Binary Counter
© 1999 Fairchild Semicond uctor Corpor ation DS005216.prf www.fairchildsemi.com
MM74HC4020 • MM74HC4040
14-Stage Binary Counter • 12-Stage Binary Counter
General Descript ion
The MM7 4HC4020, M M74HC4040 , are high spe ed binary
ripple c arr y co unt ers. Thes e co un ter s ar e impleme nte d u ti -
lizing advanced silicon-gate CMOS technology to achieve
speed performance s imilar to LS-TTL logic while retain ing
the low power and high noise immunity of CMOS.
The MM74HC4020 is a 14 stage counter and the
MM74HC4040 is a 12-stage counter. Both devices are
incremented on the fallin g edge (negat ive transition) of t he
input clo ck, and all th eir outp uts ar e reset to a l ow leve l by
applying a logical high on their reset input.
These devices are pin equivalent to the CD4020 and
CD4040 respectively. All inputs are protected from damage
due to static discharge by protection diodes to VCC and
ground.
Features
■Typical propagation delay: 16 ns
■Wide operat i ng voltage range: 2–6V
■Low input curre nt: 1 µA maximum
■Low quiescen t curre nt: 80 µA maximum (74HC Series )
■Output drive capability: 10 LS-TTL loads
Ordering Code:
Devices also ava ilable in Ta pe and Reel. Speci fy by append ing the suffix let t er “X” to the o rdering code.
Connection Diagrams
Pin Assignme nts for DIP, SOIC, SOP and TSSOP
MM74HC4020 MM74HC4040
Order Number Package Number Package Description
MM74HC4020M M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow
MM74HC4020SJ M16D 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
MM74HC4020MTC MTC16 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
MM74HC4020N N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
MM74HC4040M M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow
MM74HC4040SJ M16D 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
MM74HC4040MTC MTC16 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
MM74HC4040N N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
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MM74HC4020 • MM74HC4040
Logic Diagrams
MM74HC4020
MM74HC4040
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MM74HC4020 • MM74HC4040
Absolute Maximum Ratings(Note 1)
(Note 2) Recommended Operating
Conditions
Note 1: Maximum Ratings are those values beyond which damage to the
device may occur.
Note 2: Unl es s ot herwise specified all v olt ages are referenc ed to ground.
Note 3: Power Dis sipation te mperature d erating — pl astic “N” pa ckage: −
12 mW/°C from 65°C to 85°C.
DC Electrical Characteristics (Note 4)
Note 4: F or a pow er sup ply of 5V ±1 0% the worst case output voltages (VOH, and VOL) occ ur for HC at 4.5V. Thus the 4. 5V valu es shou ld be u sed when
designing with this supply. Worst case VIH and VIL occur at VCC = 5.5V and 4.5V respectiv ely. (T he VIH value at 5. 5V is 3.8 5V.) The worst c as e leakage cur-
rent (IIN, ICC, and IOZ) occur fo r C M OS at the h igher vol ta ge and so th e 6. 0V values s hould be used.
Supply Voltage (VCC)−0.5 to +7.0V
DC Input Voltage (VIN)−1.5 to VCC +1.5V
DC Output Voltage (VOUT)−0.5 to VCC +0.5V
Clamp Diode Current (ICD)±20 mA
DC Output Current, per pin (IOUT)±25 mA
DC VCC or GND Current, per pin (ICC)±50 mA
Storage Temperature Range (TSTG)−65°C to +150°C
Power Dissipation (PD)
(Note 3) 600 mW
S.O. Package only 500 mW
Lead Temperature (TL)
(Soldering 10 seconds) 260°C
Min Max Units
Supply Voltage (VCC)26V
DC Input or Output Voltage 0 VCC V
(VIN, VOUT)
Operating Temperature Range (TA)−40 +85 °C
Input Rise or Fall Times
(tr, tf) VCC
= 2.0V 1000 ns
VCC = 4.5V 500 ns
VCC = 6.0V 400 ns
Symbol Parameter Conditions VCC TA = 25°CT
A = −40 to 85°CT
A = −55 to 125°CUnits
Typ Guaranteed Limits
VIH Minimum HIGH Level Input 2.0V 1.5 1.5 1.5 V
Voltage 4.5V 3.15 3.15 3.15 V
6.0V 4.2 4.2 4.2 V
VIL Maximum LOW Level Input 2.0V 0.5 0.5 0.5 V
Voltage 4.5V 1.35 1.35 1.35 V
6.0V 1.8 1.8 1.8 V
VOH Minimum HIGH Level Output VIN = VIH or VIL
Voltage |IOUT| ≤ 20 µA 2.0V 2.0 1.9 1.9 1.9 V
4.5V 4.5 4.4 4.4 4.4 V
6.0V 6.0 5.9 5.9 5.9 V
VIN = VIH or VIL
|IOUT| ≤ 4.0 mA 4.5V 4.2 3.98 3.84 3.7 V
|IOUT| ≤ 5.2 mA 6.0V 5.7 5.48 5.34 5.2 V
VOL Maximum LOW Level Output VIN = VIH or VIL
Voltage |IOUT| ≤ 20 µA 2.0V 0 0.1 0.1 0.1 V
4.5V 0 0.1 0.1 0.1 V
6.0V 0 0.1 0.1 0.1 V
VIN = VIH or VIL
|IOUT| ≤ 4.0 mA 4.5V 0.2 .26 0.33 0.4 V
|IOUT| ≤ 5.2 mA 6.0V 0.2 .26 0.33 0.4 V
IIN Maximum Input Current VIN = VCC or GND 6.0V ±0.1 ±1.0 ±1.0 µA
ICC Maximum Quiescent Supply VIN = VCC or GND 6.0V 8.0 80 160 µA
Current IOUT = 0 µA
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MM74HC4020 • MM74HC4040
AC Electrical Characteristics
VCC = 5V, TA = 25°C, CL = 15 pF, tr = tf = 6 ns
Note 5: Typical Propagation delay time to any output can be calcu lat ed using: tP= 17 + 12(N –1) ns; whe re N is th e number of t he output, QW, at VCC = 5V.
AC Electrical Characteristics
VCC = 2.0V to 6.0V, CL = 50 pF, tr = tf = 6 ns (unless otherwise specified)
Note 6: CPD determines t he no load dy namic power con s um ption, PD = CPD VCC2 f + ICC VCC, and the no load dynamic current con su m pt ion,
IS = CPD VCC f + ICC.
Symbol Parameter Conditions Typ Guaranteed Units
Limit
fMAX Maximum Operating Frequency 50 30 MHz
tPHL, tPLH Maximum Propagation (Note 5) 17 35 ns
Delay Clock to Q
tPHL Maximum Propagation 16 40 ns
Delay Reset to any Q
tREM Minimum Reset 10 20 ns
Removal Time
tWMinimum Pulse Width 10 16 ns
Symbol Parameter Conditions VCC TA = 25°CT
A = −40 to 85°CT
A = −55 to 125°CUnits
Typ Guaranteed Limits
fMAX Maximum Operating 2.0V 10 6 5 4 MHz
Frequency 4.5V 40 30 24 20 MHz
6.0V 50 35 28 24 MHz
tPHL, tPLH Maximum Propagation 2.0V 80 210 265 313 ns
Delay Clock to Q14.5V 21 42 53 63 ns
6.0V 18 36 45 53 ns
TPHL, tPLH Maximum Propagation 2.0V 80 125 156 188 ns
Delay Between Stages 4.5V 18 25 31 38 ns
from Qn to Qn+16.0V 15 21 26 31 ns
tPHL Maximum Propagation 2.0V 72 240 302 358 ns
Delay Reset to any Q 4.5V 24 48 60 72 ns
(4020 and 4040) 6.0V 20 41 51 61 ns
tREM Minimum Reset 2.0V 100 126 149 ns
Removal Time 4.5V 20 25 50 ns
6.0V 16 21 25 ns
tWMinimum Pulse Width 2.0V 90 100 120 ns
4.5V 16 20 24 ns
6.0V 14 18 20 ns
tTLH, tTHL Maximum 2.0V 30 75 95 110 ns
Output Rise 4.5V 10 15 19 22 ns
and Fall Time 6.0V 9 13 16 19 ns
tr, tfMaximum Input Rise and 1000 1000 1000 ns
Fall Time 500 500 500 ns
400 400 400 ns
CPD Power Dissipation (per package) 55 pF
Capacitance (Note 6)
CIN Maximum Input 5 10 10 10 pF
Capacitance
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MM74HC4020 • MM74HC4040
Timing Diagram
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MM74HC4020 • MM74HC4040
Physical Dimensions inches (millimeters) unless otherwise noted
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow
Package Number M16A
16-Lead Sma ll Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package Number M16D
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MM74HC4020 • MM74HC4040
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Packag e Num be r MTC 16
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.
MM74HC4020 • MM74HC4040 14-Stage Binary Counter • 12-Stage Binary Counter
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life suppor t de vices o r systems a re devices or syste ms
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical compon ent i n any compon ent of a life su pport
device or system whose failure to perform can be rea-
sonabl y ex pect ed to ca use the fa i lure of the life su pp ort
device or system, or to affect its safety or effectiveness.
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Package Number N16E
