Quad Low Noise, Low Cost
Variable Gain Amplifier
Data Sheet AD8335
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
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Tel: 781.329.4700 www.analog.com
Fax: 781.461.3113 ©2004–2012 Analog Devices, Inc. All rights reserved.
FEATURES
Low noise preamplifier (PrA)
Voltage noise = 1.3 nV/√Hz typical
Current noise = 2.4 pA/√Hz typical
NF = 7 dB (RS = RIN = 50 Ω)
Single-ended input; VIN maximum = 625 mV p-p
Active input match
Input SNR (noise bandwidth = 20 MHz) = 92 dB
VGA
Differential output
VOUT maximum = 5 V p-p, RL = 500 Ω differential
Gain range (8 dB output gain step)
−10 dB to +38 dB—low gain mode
−2 dB to +46 dB—high gain mode
Accurate linear-in-dB gain control
PrA + VGA performance
−3 dB bandwidth of 85 MHz
Excellent overload performance
Supply: 5 V
Power consumption
95 mW/channel (380 mW total)
65 mW/channel (PrA off; 260 mW total)
Power-down
APPLICATIONS
Medical imaging (ultrasound, gamma cameras)
Sonar
Test and measurement
Precise, stable wideband gain control
FUNCTIONAL BLOCK DIAGRAM
PIP1
PMD1
PMD2
PIP2
PON2
POP2
VIP2
VIN2
VIN3
VIP3
V
CM3
POP3
PON3
PIP3
PMD3
PMD4
PIP4
PON1
POP1
VIP1
VIN1
V
CM2
VCM1
EN12
SP12
HL12
VOH1
VOL1
VGN1
SL12
VGN2
VOL2
VOH2
VOH3
VOL3
VGN3
SL34
VGN4
VOL4
VOH4
PON4
POP4
VIP4
VIN4
VCM4
EN34
SP34
HL34
18dB
18dB
18dB
18dB
VMD1
VMD2
VMD3
VMD4
INTERPOLATOR
INTERPOLATOR
INTERPOLATOR
INTERPOLATOR
20dB
TO
28dB
20dB
TO
28dB
20dB
TO
28dB
20dB
TO
28dB
ATTEN
–48dB TO
0dB
ATT EN
–48dB TO
0dB
ATTEN
–48dB TO
0dB
ATTEN
–48dB TO
0dB
GAIN INT
GAIN INT
GAIN INT
GAIN INT
AD8335
04976-001
Figure 1.
GENERAL DESCRIPTION
The AD8335 is a quad variable gain amplifier (VGA) with
low noise preamplifier intended for cost and power sensitive
applications. Each channel features a gain range of 48 dB, fully
differential signal paths, active input preamplifier matching,
and user-selectable maximum gains of 46 dB and 38 dB.
Individual gain controls are provided for each channel.
The preamplifier (PrA) has a single-ended to differential gain of
×8 (18.06 dB) and accepts input signals ≤625 mV p-p. PrA noise is
1.2 nV/√Hz and the combined input referred voltage noise of
the PrA and VGA is 1.3 nV/√Hz at maximum gain.
Assuming a 20 MHz noise bandwidth (NBW), the Nyquist
frequency for a 40 MHz ADC, the input SNR is 92 dB. The
HLxx pin optimizes the output SNR for 10-bit and 12-bit
ADCs with 1 V p-p or 2 V p-p full-scale (FS) inputs.
Channel 1 and Channel 2 are enabled through the EN12 pin, and
Channel 3 and Channel 4 are enabled through the EN34 pin.
For VGA only applications, the PrAs can be powered down,
significantly reducing power consumption.
The AD8335 is available in a 64-lead lead frame chip scale
package (9 mm × 9 mm) for the industrial temperature range
of −40°C to +85°C.
AD8335 Data Sheet
Rev. B | Page 2 of 28
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description......................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Absolute Maximum Ratings............................................................ 5
ESD Caution.................................................................................. 5
Pin Configuration and Function Descriptions............................. 6
Typical Performance Characteristics ............................................. 7
Test Circuits..................................................................................... 15
Theory of Operation ...................................................................... 16
Enable Summary ........................................................................ 16
Preamp......................................................................................... 17
VGA ............................................................................................. 18
Applications Information.............................................................. 20
Ultrasound .................................................................................. 20
Basic Connections...................................................................... 21
Preamp Connections ................................................................. 21
Input Overdrive.......................................................................... 22
Logic Inputs................................................................................. 22
Common-Mode Pins................................................................. 22
Driving ADCs............................................................................. 22
Evaluation Board............................................................................ 23
Board Layout............................................................................... 23
Outline Dimensions....................................................................... 28
Ordering Guide .......................................................................... 28
REVISION HISTORY
2/12—Rev. A to Rev. B
Changes to Figure 1.......................................................................... 1
Added Exposed Pad Notation to Figure 2 and Table 3................ 6
Changes to Figure 12 Caption....................................................... 11
Deleted Measurement Setup Section ........................................... 23
Changes to Figure 60 through Figure 68..................................... 23
Deleted Table 7................................................................................ 27
8/08—Rev. 0 to Rev. A
Changes to Features Section............................................................ 1
Changes to Table 1, Scale Factor Parameter.................................. 4
Changes to Theory of Operation Section.................................... 16
Changes to Figure 54...................................................................... 16
Changes to Equation 4................................................................... 18
Changes to Figure 58...................................................................... 21
Added Evaluation Board Section ................................................. 23
Added Figure 60 to Figure 68........................................................ 23
Updated Outline Dimensions....................................................... 28
Changes to Ordering Guide.......................................................... 28
9/04—Revision 0: Initial Version
Data Sheet AD8335
Rev. B | Page 3 of 28
SPECIFICATIONS
VS = 5 V, TA = 25°C, RL = 500 Ω, f = 5 MHz, CL = 10 pF, low gain range (−10 dB to +38 dB), RFB = 249 Ω (PrA RIN = 50 Ω) and signal
voltage specified differential, per channel performance, dBm (50 Ω), unless otherwise noted.
Table 1.
Parameter Test Conditions/Comments Min Typ Max Unit
PrA CHARACTERISTICS
Gain Single-ended input to differential output 18 dB
Single-ended input to single-ended output 12 dB
Input Voltage Range PrA output limited to 5 V p-p differential 625 mV p-p
Input Resistance RFB = 249 Ω 50 Ω
R
FB = 374 Ω 75 Ω
R
FB = 499 Ω 100 Ω
R
FB = ∞, low frequency value into PIPx 14.7 kΩ
Input Capacitance PIPx (Pin 2, Pin 15, Pin 18, Pin 63) 1.5 pF
−3 dB Small Signal Bandwidth With RFB = 249 Ω 110 MHz
Input Voltage Noise RS = 0 Ω, RFB = ∞ 1.15 nV/√Hz
Input Current Noise 2.4 pA/√Hz
Noise Figure
Active Termination Match RS = RIN = 50 Ω, RFB = 249 Ω 7 dB
Unterminated RS = 50 Ω, RFB = ∞ 4.4 dB
PrA + VGA CHARACTERISTICS
−3 dB Small Signal Bandwidth Unterminated: RS = 50 Ω, RFB = ∞ 70 MHz
Matched: RS = RIN = 50 Ω 85 MHz
Slew Rate Low gain, VGN = 3 V, VOUT = 2 V p-p 250 V/μs
High gain, VGN = 3 V, VOUT = 2 V p-p 350 V/μs
Input Voltage Noise VGNx pins = 3 V, RS = 0 Ω, RFB = ∞ 1.3 nV/√Hz
Noise Figure VGNx pins = 3 V, f = 1 MHz to 10 MHz
Active Termination Match RS = RIN = 50 Ω 7 dB
R
S = RIN = 100 Ω 4.5 dB
Unterminated RS = 50 Ω, RFB = ∞ 5.0 dB
R
S = 500 Ω, RFB = ∞ 1.3 dB
Output Referred Noise Low gain; VGN < 2 V 33 nV/√Hz
High gain; VGN < 2 V 80 nV/√Hz
Peak Output Voltage Differential, RL ≥ 500 Ω 5 V p-p
Output Resistance f < 1 MHz, VOHx, VOLx pins 1.2 Ω
Common-Mode Level Set to midsupply for PrA and VGA VS/2 V
Output Offset Voltage
Differential Between VOHx pins and VOLx pins, full gain range −25 +5 +35 mV
Common-Mode Between VOHx pins and VCMx pins, and between
VOLx pins and VCMx pins
−20 +0 +20 mV
Harmonic Distortion VOUT = 1 V p-p, low gain, VGN = 2 V
HD2 f = 1 MHz −69 dBc
HD3 f = 1 MHz −57 dBc
HD2 f = 10 MHz −57 dBc
HD3 f = 10 MHz −55 dBc
Harmonic Distortion VOUT = 1 V p-p, high gain, VGN = 2 V
HD2 f = 1 MHz −58 dBc
HD3 f = 1 MHz −70 dBc
HD2 f = 10 MHz −55 dBc
HD3 f = 10 MHz −55 dBc
Output 1 dB Compression (OP1dB) VGN = 3 V 18 dBm
VGN = 3 V 8 dBV peak
AD8335 Data Sheet
Rev. B | Page 4 of 28
Parameter Test Conditions/Comments Min Typ Max Unit
Two-Tone IMD3 Distortion VOUT = 1 V p-p, VGN = 3 V
f
1 = 1 MHz, f2 = 1.05 MHz −69 dBc
f
1 = 10 MHz, f2 = 10.05 MHz −65 dBc
Output IP3 (OIP3) VOUT = 1 V p-p, VGN = 3 V
f = 1 MHz 33 dBm
f = 10 MHz 31 dBm
Channel-to-Channel Crosstalk VOUT = 1 V p-p, f = 1 to 10 MHz −80 dBc
Overload Recovery PrA or VGA 10 ns
Group Delay Variation Full gain range, f = 1 MHz to 10 MHz 3.0 ns
GAIN CONTROL INTERFACE VGNx pins
Normal Operating Range 0 3 V
Maximum Range No gain foldover 0 VS V
Gain Range Low gain mode; (HLxx pins = 0 V) −10 to +38 dB
High gain mode; (HLxx pins = VS) −2 to +46 dB
Scale Factor Nominal (Pin SL12 and Pin SL34 = 2.5 V) 19.1 20.1 21.1 dB/V
Bias Current −0.3 μA
Response Bandwidth 5 MHz
Response Time 48 dB gain change 350 ns
GAIN ACCURACY VGNx pins
Absolute Gain Error 0 ≤ VGN ≤ 0.4 V 1.25 7.5 dB
0.4 ≤ VGN ≤ 2.6 V, 1σ −1.25 ±0.2 +1.25 dB
2.6 ≤ VGN ≤ 3 V −7.5 −1.25 dB
Gain Law Conformance Over Temperature 0.4 ≤ VGN ≤ 2.6 V; −40°C < TA< +85°C ±0.75 dB
Intercept Low gain mode; PrA matched to 50 Ω −16.1 dB
High gain mode; PrA matched to 50 Ω −8.1 dB
Channel-to-Channel Matching 0.4 ≤ VGN ≤ 2.6 V 0.15 dB
LOGIC LEVEL—HIGH/LOW, SHUTDOWN PREAMP,
and ENABLE INTERFACES
HLxx, SPxx, and ENxx pins
Logic High 2.75 5 V
Logic Low 0 1 V
BIAS CURRENT—HIGH/LOW, ENABLE
Logic High 80 μA
Logic Low −12 μA
INPUT RESISTANCE—HIGH/LOW, ENABLE 50 kΩ
BIAS CURRENT— SHUTDOWN PREAMP
Logic High 20 μA
Logic Low 0 μA
INPUT RESISTANCE—SHUTDOWN PREAMP 500 kΩ
High/Low Response Time 0.6 μs
Enable Response Time 100 μs
POWER SUPPLY VPPx and VPVx pins
Supply Voltage 4.5 5 5.5 V
Quiescent Current Each channel—PrA and VGA enabled 19 mA
Each channel—PrA disabled, VGA enabled 13 mA
All channels enabled 76 mA
Over Temperature −40°C < TA< +85°C 16 22.8 mA
Quiescent Power Each channel—PrA and VGA enabled 95 mW
Each channel—PrA disabled, VGA enabled 65 mW
Disable Current All channels disabled 0.8 mA
PSRR VGN = 0 V, all bypass capacitors removed, 1 MHz −60 dB
Data Sheet AD8335
Rev. B | Page 5 of 28
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter Rating
Voltage
Supply VS 6 V
Preamp Input VS
VGA Inputs VS
Enable, Shutdown Preamp, and
High/Low Interfaces
VS
Gain VS
Power Dissipation (4-Layer JEDEC Board (2s2p)) 2.46 W
θJA 26.4°C/W
θJC 6.8°C/W
Operating Temperature Range −40°C to +85°C
Storage Temperature Range −65°C to +150°C
Lead Temperature (Soldering 60 sec) 300°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
AD8335 Data Sheet
Rev. B | Page 6 of 28
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
PIN 1
IDENTIFIER
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
PMD4
PIP4
VPP4
PON4
POP4
VIP4
VIN4
COM4
VGN4
VCM4
VGN3
VCM3
EN34
SP34
SL34
HL34
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
PMD1
PIP1
VPP1
PON1
POP1
VIP1
VIN1
COM1
VGN1
VCM1
VGN2
VCM2
EN12
SP12
SL12
HL12
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
PMD2
PIP2
VPP2
PON2
POP2
VIP2
VIN2
COM2
COM3
VIN3
VIP3
POP3
PON3
VPP3
PIP3
PMD3
GND1
VOH1
VOL1
VPV1
VPV2
VOL2
VOH2
GND2
GND3
VOH3
VOL3
VPV3
VPV4
VOL4
VOH4
GND4
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
AD8335
TOP VIEW
(Not to Scale)
04976-058
NOTES
1. THE EXPOSED PADDLE MUST BE SOLDERED TO THE PCB GROUND
TO ENSURE PROPER HEAT DISSIPATION, NOISE, AND MECHANICAL
STRENGTH BENEFITS.
Figure 2. Pin Configuration
Table 3. Pin Function Descriptions
Pin No. Mnemonic Description
1 PMD2 Preamp Input Common—CH2
2 PIP2 Preamp Input—CH2
3 VPP2 Positive Supply Preamp—CH2
4 PON2 Preamp Output Negative—CH2
5 POP2 Preamp Output Positive—CH2
6 VIP2 VGA Input Positive—CH2
7 VIN2 VGA Input Negative—CH2
8 COM2 Ground Preamp—CH2
9 COM3 Ground Preamp—CH3
10 VIN3 VGA Input Negative—CH3
11 VIP3 VGA Input Positive—CH3
12 POP3 Preamp Output Positive—CH3
13 PON3 Preamp Output Negative—CH3
14 VPP3 Positive Supply Preamp—CH3
15 PIP3 Preamp Input—CH3
16 PMD3 Preamp Input Common—CH3
17 PMD4 Preamp Input Common—CH4
18 PIP4 Preamp Input—CH4
19 VPP4 Positive Supply Preamp—CH4
20 PON4 Preamp Output Negative—CH4
21 POP4 Preamp Output Positive—CH4
22 VIP4 VGA Input Positive—CH4
23 VIN4 VGA Input Negative—CH4
24 COM4 Ground Preamp—CH4
25 VGN4 Gain Control—CH4
26 VCM4 Common-Mode Decoupling Pin—CH4
27 VGN3 Gain Control—CH3
28 VCM3 Common-Mode Decoupling Pin—CH3
29 EN34 Enable—CH3 and CH4
30 SP34 Shutdown—Preamp 3 and Preamp 4
31 SL34 Slope Decoupling Pin—CH3 and CH4
32 HL34 High/Low Pin—CH3 and CH4
33 GND4 Ground VGA—CH4
34 VOH4 VGA Output Positive—CH4
Pin No. Mnemonic Description
35 VOL4 VGA Output Negative—CH4
36 VPV4 Positive Supply VGA—CH4
37 VPV3 Positive Supply VGA—CH3
38 VOL3 VGA Output Negative—CH3
39 VOH3 VGA Output Positive—CH3
40 GND3 Ground VGA—CH3
41 GND2 Ground VGA—CH2
42 VOH2 VGA Output Positive—CH2
43 VOL2 VGA Output Negative—CH2
44 VPV2 Positive Supply VGA—CH2
45 VPV1 Positive Supply VGA—CH1
46 VOL1 VGA Output Negative—CH1
47 VOH1 VGA Output Positive—CH1
48 GND1 Ground VGA—CH1
49 HL12 High/Low Pin—CH1 and CH2
50 SL12 Slope Decoupling Pin—CH1 and CH2
51 SP12 Shutdown—Preamp 1 and Preamp 2
52 EN12 Enable—CH1 and CH2
53 VCM2 Common-Mode Decoupling Pin—CH2
54 VGN2 Gain Control—CH2
55 VCM1 Common-Mode Decoupling Pin—CH1
56 VGN1 Gain Control—CH1
57 COM1 Ground Preamp—CH1
58 VIN1 VGA Input Negative—CH1
59 VIP1 VGA Input Positive—CH1
60 POP1 Preamp Output Positive—CH1
61 PON1 Preamp Output Negative—CH1
62 VPP1 Positive Supply Preamp—CH1
63 PIP1 Preamp Input—CH1
64 PMD1 Preamp Input Common—CH1
EPAD
The exposed paddle must be soldered to
the PCB ground to ensure proper heat
dissipation, noise, and mechanical
strength benefits.
Data Sheet AD8335
Rev. B | Page 7 of 28
TYPICAL PERFORMANCE CHARACTERISTICS
VS = 5 V, TA = 25°C, RL = 500 Ω, f = 5 MHz, CL = 10 pF, low gain range (−10 dB to +38 dB), RFB = 249 Ω (PrA RIN = 50 Ω) and signal
voltage specified differential, per channel performance, unless otherwise noted.
–20
–10
0
10
20
30
40
50
GAIN (dB)
1.0 1.50 0.5 2.0 2.5 3.0
V
GAIN
(V)
04976-002
LOW GAIN
HIGH GAIN
+85°C
+25°C
–40°C
Figure 3. Gain vs. VGAIN at Three Temperatures (See Figure 49)
–2.0
–1.5
–1.0
–0.5
0
0.5
GAIN ERROR (dB)
1.0
1.5
2.0
1.0 1.50 0.5 2.0 2.5 3.0
V
GAIN
(V)
04976-003
+85°C, LOW GAIN
+85°C, HIGH GAIN
+25°C, LOW GAIN
+25°C, HIGH GAIN
–40°C, LOW GAIN
–40°C, HIGH GAIN
Figure 4. Gain Error vs. VGAIN at Three Temperatures (See Figure 49)
–6.0
–4.0
–2.0
0
2.0
GAIN ERROR (dB)
4.0
6.0
1.0 1.50 0.5 2.0 2.5 3.0
V
GAIN
(V)
04976-004
1MHz
5MHz
10MHz
20MHz
Figure 5. Gain Error vs. VGAIN at Various Frequencies (See Figure 49)
0
2
4
6
8
10
12
14
16
18
20
–0.6 –0.5 –0.4 –0.3 –0.2 0 0.4–0.1 0.1 0.2 0.3 0.5 0.6
% OF UNITS
GAIN ERROR (dB)
04976-005
420 CHANNELS
(105 UNITS)
V
GAIN
= 1.5V
Figure 6. Gain Error Histogram
% OF UNITS
CHANNEL-TO-CHANNEL GAIN MATCH (dB)
04976-006
–1.0
–0.9
–0.8
–0.7
–0.6
–0.5
–0.4
–0.3
–0.2
–0.1
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
–1.0
–0.9
–0.8
–0.7
–0.6
–0.5
–0.4
–0.3
–0.2
–0.1
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
0
5
10
15
20
25
0
5
10
15
20
25
420 CHANNELS
(105 UNITS)
V
GAIN
= 1.0V
V
GAIN
= 2.0V
CH1 TO CH2
CH1 TO CH4
CH1 TO CH3
Figure 7. Gain Match Histogram for VGAIN = 1 V and 2 V
0
5
10
15
20
25
30
35
40
45
%TOTAL
GAIN SCALING FACTOR
04976-007
20.419.9 20.0 20.1 20.2 20.3
420 CHANNELS
(105 UNITS)
0.5V < V
GAIN
< 2.5V
Figure 8. Gain Scaling Factor Histogram for 0.5 V < VGAIN< 2.5 V
AD8335 Data Sheet
Rev. B | Page 8 of 28
0
5
10
15
20
25
–16.7
–16.6
–16.5
–16.4
–16.3
–16.1
–15.7
–16.2
–16.0
–15.9
–15.8
–15.6
–15.5
%TOTAL
INTERCEPT (dB)
04976-008
420 CHANNELS
(105 UNITS)
0.5V < V
GAIN
< 2.5V
Figure 9. Intercept Histogram
1M100k 10M 100M 1G
–20
–10
0
10
20
30
40
50
GAIN (dB)
FREQUENCY (Hz)
04976-009
V
GAIN
= 3.0V
V
GAIN
= 2.5V
V
GAIN
= 2.0V
V
GAIN
= 1.5V
V
GAIN
= 1.0V
V
GAIN
= 0.5V
V
GAIN
= 0V
Figure 10. Frequency Response for Various Values of VGAIN (See Figure 49)
1M100k 10M 100M 1G
–20
–10
0
10
20
30
40
50
GAIN (dB)
FREQUENCY (Hz)
04976-010
V
GAIN
= 3.0V
V
GAIN
= 2.5V
V
GAIN
= 2.0V
V
GAIN
= 1.5V
V
GAIN
= 1.0V
V
GAIN
= 0.5V
V
GAIN
= 0V
Figure 11. Frequency Response vs. Frequency for Various Values of VGAIN,
HLxx = High (See Figure 49)
1M100k 10M 100M 1G
–5
0
5
10
15
20
25
30
GAIN (dB)
FREQUENCY (Hz)
04976-011
–10
R
S
= 50Ω
V
IN
= 10mV p-p
R
FB
=
∞
R
FB
= 249Ω
Figure 12. Preamp Frequency Response for a Terminated and Unterminated
50 Ω Source (See Figure 49)
–100
–90
–80
–70
–60
–50
–40
–30
–20
–
10
CROSSTALK (dB)
FREQUENCY (Hz)
100k 10M1M 100M
04976-012
V
OUT
= 1V p-p
V
GAIN
= 3V
V
GAIN
= 2V
V
GAIN
= 1V
V
GAIN
= 1V
V
GAIN
= 2V
V
GAIN
= 3V
Figure 13. Channel-to-Channel Crosstalk vs. Frequency for
Various Values of VGAIN
GROUP DELAY (ns)
FREQUENCY (Hz)
100k 10M1M 100M
04976-013
10
20
30
40
50
60
70
80
0
Figure 14. Group Delay vs. Frequency
Data Sheet AD8335
Rev. B | Page 9 of 28
–25
–20
–15
–10
–5
0
5
10
15
20
25
OFFSET VOLTAGE (mV)
1.0 1.50 0.5 2.0 2.5 3.0
V
GAIN
(V)
04976-014
+85°C, HIGH
+85°C, LOW
–40°C, LOW –40°C, HIGH
+25°C, LOW
+25°C, HIGH
Figure 15. Differential Output Offset Voltage vs. VGAIN at Three Temperatures
–25
–20
–15
–10
–5
0
5
10
15
20
25
OFFSET VOLTAGE (mV)
1.0 1.50 0.5 2.0 2.5 3.0
V
GAIN
(V)
04976-015
Figure 16. Absolute Offset vs. VGAIN at VOHx and VOLx Pins
Relative to VCMx Pins
1M100k 10M 1G
0.1
1
10
100
OUTPUT IMPEDANCE (Ω)
FREQUENCY (Hz)
04976-016
V
IN
= 10mV p-p
VOHx
VOLx
Figure 17. Output Resistance at VOHx and VOLx Pins vs. Frequency
1M 10M 1G
INPUT IMPEDANCE (Ω)
FREQUENCY (Hz)
04976-017
10
100
1k
R
FB
= 2.5kΩ
R
FB
= 1kΩ
R
FB
= 499Ω
R
FB
= 249Ω
R
SH
= 49Ω, C
SH
= 22pF
R
SH
=
∞
, C
SH
= 0pF
Figure 18. Preamp Input Resistance vs. Frequency for
Various Values of RFB
–100
–90
–80
–70
–60
–50
–40
–30
–20
–10
CROSSTALK (dB)
04976-018
25j
50j
100j
–75j
–50j
–25j
0Ω17Ω50Ω150Ω
STOP
1GHz
START
100kHz
V
IN
= 10mV p-p
100MHz
Figure 19. Smith Chart S11 vs. Frequency, 100 kHz to 1 GHz
0
50
100
150
200
250
OUTPUT REFERRED NOISE (nV/ Hz)
1.0 1.50 0.5 2.0 2.5 3.0
V
GAIN
(V)
04976-019
HLxx = HIGH
HLxx = LOW
R
S
= 0Ω
R
FB
=
∞
Figure 20. Output Referred Noise vs. VGAIN (See Figure 50)
AD8335 Data Sheet
Rev. B | Page 10 of 28
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
FREQUENCY (MHz)
0.1 101 100
04976-020
INPUT REFERRED NOISE (nV/ Hz)
V
GAIN
= 3.0V
R
S
= 0Ω
R
FB
=
∞
Figure 21. Short-Circuit Input Referred Noise vs. Frequency at Maximum Gain
(See Figure 50)
V
GAIN
(V)
04976-021
0.1
1.0
10
100
1k
1.0 1.50 0.5 2.0 2.5 3.0
NOISE (nV/ Hz)
T = –40°C
T = +25°C
T = +85°C
Figure 22. Input Referred Noise vs. VGAIN at Three Temperatures
(See Figure 50)
101100
0.1
1.0
10
SOURCE RESISTANCE (Ω)
04976-022
1k
INPUT NOISE (nV/ Hz)
R
S
THERMAL NOISE
ALONE
f = 1MHz, V
GAIN
= 3V
Figure 23. Input Referred Noise vs. RS
0
10
20
15
5
30
25
NOISE FIGURE (dB)
40
35
50
45
60
55
1.0 1.50 0.5 2.0 2.5 3.0
V
GAIN
(V)
04976-062
f = 10MHz
Figure 24. Noise Figure vs. VGAIN for RS = RIN = 50 Ω
–70
–65
–60
–55
–50
–45
–40
–35
DISTORTION (dBc)
200 400 600 800 1.0k 1.2k 1.4k 1.6k 1.8k 2.0k
R
LOAD
(Ω)
04976-025
f = 10MHz
V
OUT
= 1V p-p
V
GAIN
= 1.5V
HLxx = LOW
HD2 HD3
HLxx = HIGH
HD2 HD3
Figure 25. Harmonic Distortion vs. RLOAD (See Figure 53)
–80
–70
–60
–50
–40
–30
–20
DISTORTION (dBc)
01020304050
C
LOAD
(pF)
04976-200
f = 10MHz
V
OUT
= 1V p-p
HLxx = LOW
HD3
HLxx = HIGH,
HD3
HLxx = HIGH,
HD2 HLxx = LOW,
HD2
Figure 26. Harmonic Distortion vs. CLOAD (See Figure 53)
Data Sheet AD8335
Rev. B | Page 11 of 28
–80
–70
–60
–50
–40
–30
–20
DISTORTION (dBc)
0.5 1.0 1.5 2.0 2.5 3.0
V
GAIN
(V)
04976-026
LOW GAIN
V
OUT
= 1V p-p
f = 10MHz
f = 5MHz
f = 1MHz
Figure 27. HD2 vs. VGAIN at Three Frequencies, Low Gain (See Figure 53)
–80
–70
–60
–50
–40
–30
–20
DISTORTION (dBc)
0.5 1.0 1.5 2.0 2.5 3.0
V
GAIN
(V)
04976-027
LOW GAIN
V
OUT
= 1V p-p
f = 10MHz
f = 5MHz
f = 1MHz
Figure 28. HD3 vs. VGAIN at Three Frequencies, Low Gain (See Figure 53)
–80
–70
–60
–50
–40
–30
–20
DISTORTION (dBc)
0.5 1.0 1.5 2.0 2.5 3.0
V
GAIN
(V)
04976-029
HIGH GAIN
V
OUT
= 1V p-p
f = 10MHz
f = 5MHz
f = 1MHz
Figure 29. HD2 vs. VGAIN at Three Frequencies, High Gain (See Figure 53)
–80
–70
–60
–50
–40
–30
–20
DISTORTION (dBc)
0.5 1.0 1.5 2.0 2.5 3.0
V
GAIN
(V)
04976-030
HIGH GAIN
V
OUT
= 1V p-p
f = 10MHz
f = 5MHz
f = 1MHz
Figure 30. HD3 vs. VGAIN at Three Frequencies, High Gain (See Figure 53)
–80
–75
–70
–65
–60
–55
–50
–45
–40
–
35
DISTORTION (dBc)
0.51.01.52.02.53.0
V
GAIN
(V)
04976-031
f = 1MHz
2V p-p
1V p-p
0.5V p-p
Figure 31. HD2 vs. VGAIN at Three Output Voltages, Low Gain (See Figure 53)
–90
–80
–70
–60
–50
–40
–30
–20
DISTORTION (dBc)
04976-032
0.5 1.0 1.5 2.0 2.5 3.0
V
GAIN
(V)
f = 1MHz
2V p-p
1V p-p
0.5V p-p
Figure 32. HD3 vs. VGAIN, at Three Output Voltages, Low Gain (See Figure 53)
AD8335 Data Sheet
Rev. B | Page 12 of 28
–70
–65
–60
–55
–50
–45
–40
–35
DISTORTION (dBc)
1.0 1.50 0.5 2.0 2.5 3.0
V
GAIN
(V)
04976-034
f = 1MHz
2V p-p
1V p-p
0.5V p-p
Figure 33. HD2 vs. VGAIN at Three Output Voltages, High Gain, f = 1 MHz
(See Figure 53)
–90
–80
–70
–60
–50
–40
–30
–20
DISTORTION (dBc)
04976-035
0.5 1.0 1.5 2.0 2.5 3.0
V
GAIN
(V)
f = 1MHz
2V p-p
1V p-p
0.5V p-p
0
Figure 34. HD3 vs. VGAIN at Three Output Voltages, High Gain (See Figure 53)
IMD3 (dBc)
FREQUENCY (MHz)
04976-036
–90
–80
–70
–60
–50
–40
–30
–20
–10
0
1 10 100
IMD3 (HIGH)
IMD3 (LOW)
V
OUT
= 1V p-p
V
GAIN
= 3V
Figure 35. IMD3 vs. Frequency
0
5
10
15
20
25
IP3 (dBm)
30
35
40
1.0 1.50 0.5 2.0 2.5 3.0
V
GAIN
(V)
04976-037
5MHz (LOW)
5MHz (HIGH)
V
OUT
= 1Vp-p
Figure 36. Output Referred IP3 (OIP3) vs. VGAIN
–30
–25
–20
–15
–10
–5
0
5
INPUT POWER (dBm)
1.0 1.50 0.5 2.0 2.5 3.0
V
GAIN
(V)
04976-038
HLxx = HIGH
HLxx = LOW
f = 10MHz
Figure 37. Input P1dB (IP1dB) vs. VGAIN
HARMONIC DISTORTION (dBc)
04976-039
100
90
10
0
10mV
50mV 10ns
Figure 38. Small Signal Pulse Response, Low Gain (See Figure 51)
Data Sheet AD8335
Rev. B | Page 13 of 28
HARMONIC DISTORTION (dBc)
04976-040
100
90
10
0
100mV
500mV 10ns
Figure 39. Large Signal Pulse Response, Low Gain (See Figure 51)
V
OUT
(V)
TIME (ns)
04976-041
–2
–1
0
1
2
0 102030405060708090100
V
GAIN
= 2V C
L
= 47pF
C
L
= 22pF
C
L
= 10pF
INPUT
INPUT IS NOT TO SCALE
C
L
= 0pF
Figure 40. Large Signal Pulse Response for Various Capacitive Loads,
CL = 0 pF, 10 pF, 20 pF, 47 pF Each Output (See Figure 51)
HARMONIC DISTORTION (dBc)
04976-042
100
90
10
0
400ns
2V
500mV
Figure 41. Gain Response, VGAIN Stepped from 0 V to3 V, VOUT = 2 V p-p
(See Figure 51)
HARMONIC DISTORTION (dBc)
04976-043
100
90
10
0
100µs
100mV
2V
Figure 42. Small Signal Enable Response (See Figure 51)
HARMONIC DISTORTION (dBc)
04976-044
100
90
10
0
1V
2V
100µs
Figure 43. Large Signal Enable Response (See Figure 51)
HARMONIC DISTORTION (dBc)
04976-045
100
90
10
0
1µs
1V
Figure 44. Preamp Overdrive Recovery,
50 mV p-p to 1.5 V p-p at Preamp Input (Measured at Preamp Output)
AD8335 Data Sheet
Rev. B | Page 14 of 28
HARMONIC DISTORTION (dBc)
04976-046
100
90
10
0
1µs
1V
Figure 45. VGA Overdrive Recovery, 40 mV to 500 mV Input, VGAIN = 2.5 V
PSRR (dB)
FREQUENCY (Hz)
100k 10M1M 100M
04976-100
–70
–60
–50
–40
–30
–20
–10
0
–80
V
GAIN
= 2.5V
V
GAIN
= 0V
V
GAIN
= 0.5V
V
GAIN
= 1.5V
Figure 46. PSRR vs. Frequency (All Bypass Capacitors Removed)
60
65
70
75
80
85
90
95
QUIESCENT SUPPLY CURRENT (mA)
–40 –20 0 20 40 60 80 100
TEMPERATURE (°C)
04976-047
V
GAIN
= 2.5V
Figure 47. Quiescent Supply Current vs. Temperature
04976-101
100
90
0
500mV
2V
1µs
10
Figure 48 High/Low Response Time
Data Sheet AD8335
Rev. B | Page 15 of 28
TEST CIRCUITS
28Ω
237Ω
249Ω
1:1
NETWORK AN
A
LYZ E
R
AD8335
18nF
22pF
50Ω
IN
OUT
0.1µF
237Ω
28Ω
0.1µF
0.1µF
50Ω
49.9Ω
0.1µF
04976-048
Figure 49. Test Circuit for Gain and Bandwidth Measurements
1:1
AD8335
22pF
0.1µF
0.1µF
0.1µF
49Ω
0.1µF IN
50Ω
SPECTRUM
ANALYZER
04976-050
Figure 50. Test Circuit for Noise Measurements
28Ω
237Ω
249Ω
1:1
AD8335
18nF
22pF
0.1µF
237Ω
28Ω
0.1µF
0.1µF
49.9Ω
0.1µF
50Ω
IN
50Ω
OSCILLOSCOPE
04976-049
Figure 51. Test Circuit for Transient Measurements
28Ω
237Ω
249Ω
1:1
NETWORK AN
A
LYZ ER
AD8335
18nF
22pF
50Ω
INOUT
0.1µF
237Ω
28Ω
0.1µF
0.1µF
50Ω
49.9Ω
0.1µF
50Ω
50Ω
04976-052
Figure 52. Test Circuit for S11 Measurements
28Ω
237Ω
249Ω
1:1
AD8335
18nF
22pF
0.1µF
237Ω
28Ω
0.1µF
0.1µF
50Ω
0.1µF
50Ω
IN
50Ω
SPECTRUM
ANALYZER
04976-051
LPF
SIGNAL
GENERATOR
Figure 53. Test Circuit Used for Distortion Measurements
AD8335 Data Sheet
Rev. B | Page 16 of 28
THEORY OF OPERATION
Figure 54 is a simplified block diagram of a single channel. Each
channel consists of a low noise preamplifier (PrA) followed by a
VGA with a user-selectable gain of 20 dB or 28 dB. Channels are
enabled in pairs, Channel 1 and Channel 2, and Channel 3 and
Channel 4. The preamps are enabled by grounding the SPxx
pins and powered down by connecting them to the positive supply.
The ENxx pins are connected to the positive supply to enable
the VGAs and the overall channel. HLxx configures VGA for a
fixed gain of 20 dB or 28 dB, with 0 V or 5 V applied to the
HLxx pins, respectively. Channel 1 and Channel 2 share Pin HL12,
and Channel 3 and Channel 4 share Pin HL34. The HLxx pins
are typically hardwired to adjust the VGA gain according to an
ADC resolution of 12 bits for low gain and 10 bits for high gain.
The signal path is fully differential throughout to maximize signal
swing and reduce even-order distortion; however, the preamplifiers
are designed to be driven from a single-ended signal source. Gain
values are referenced from the single-ended PrA input to the
differential output of either the PrA or the VGA. Again referring to
Figure 54, the system gain is distributed as listed in Table 4.
In the remainder of this document, the gain values are rounded
to −10 dB to +38 dB for low gain mode and to −2 dB to +46 dB
for high gain mode. If desired, Equation 1 can be used to calculate
the gain at a value of VGAIN.
ICPTVGNGain += V
dB
1.20[dB] (1)
where ICPT = −16.1 dB for low gain mode −8.1 dB for high
gain mode.
Power consumption is 95 mW/channel from a 5 V supply, or
380 mW for all four channels. Power is distributed 35% for the
PrA, and 65% for the remainder of the circuit. The preamps can
be shut down via the SP12 and SP34 pins if a user wants to use
the VGAs only. However, to avoid feedthrough around the
preamp, feedback resistors should not be installed.
Table 4. Channel Gain Distribution
Section
Low Nominal Gain
(dB)
High Nominal Gain
(dB)
PrA 18.06 18.06
Attenuator 0 to −48.16 0 to −48.16
Output Amp 20 27.96
Aggregate −10.1 to +38.6 −2.14 to +46.02
ENABLE SUMMARY
Table 5summarizes the enable/shutdown logic and resulting
supply current.
Table 5. Control Pin Logic and Power Consumption
EN12 SP12 EN34 SP34 PrA1/PrA2 VGA1/VGA2 PrA3/PrA4 VGA3/VGA4 IS
High Low High Low On On On On 76 mA
High High High High Off On Off On 52 mA
Low Low Low Low Off Off Off Off 0.8 mA
Low High Low High Off Off Off Off 0.8 mA
+1
+1
+1
+1
PrA
18dB
HIGH/LOW
+1
INTERPOLATOR
ATT ENx
–48dB TO 0dB
GAIN INTERFACE
+1
BIAS
OUTPUT AMP
20dB OR 28dB VOHx
VOLx
HLxx
SLxx
VGNx
VCMx
VIPx
POPx
ENxx
PMDx
PIPx
PONx
VINx
04976-054
RFB
R
S
Figure 54. Simplified Block Diagram of Single Channel
Data Sheet AD8335
Rev. B | Page 17 of 28
PREAMP
Although the preamp signal path is fully differential, the design is
optimized for single-ended input drive and signal source resistance
matching. Thus, the negative input to the differential preamplifier
PMDx pins must be ac-grounded to provide a balanced differential
signal at the PrA outputs. Detailed information regarding the
preamplifier architecture is found in the LNA section of the
AD8331/AD8332 data sheet.
The preamplifier consists of a fixed gain amplifier with differential
outputs. With the negative output available and a fixed gain of
8 (18.06 dB), an active input termination is synthesized by
connecting a feedback resistor between the negative output
and the positive input, Pin PIPx. This technique is well known
and results in the input resistance shown in Equation 2.
)2/1( A
R
RFB
IN +
= (2)
where A/2 is the single-ended gain, or the gain from the PIPx
inputs to the PONx outputs. Since the amplifier has a gain of ×8
from its input to its differential output, it is important to note
that the gain A/2 is the gain from Pin PIPx to Pin PONx, which
is 6 dB lower, or 12.04 dB (×4). The input resistance is reduced
by an internal bias resistor of 14.7 kΩ in parallel with the source
resistance connected to Pin PIPx, with Pin PMDx ac-grounded.
Equation 3 can be used to calculate the needed RFB for a desired
RIN, and is used for higher values of RIN.
k7.14||
)41( +
=FB
IN
R
R (3)
For example, to set RIN = 200 Ω, the value of RFB is 1.013 kΩ. If the
simplified Equation 2 is used to calculate RIN, the value is 197 Ω,
resulting in a less than 0.1 dB gain error. Factors such as a widely
varying source resistance might influence the absolute gain
accuracy more significantly. At higher frequencies, the input
capacitance of the PrA needs to be considered. The user must
determine the level of matching accuracy and adjust RFB
accordingly.
The bandwidths (BW) of the preamplifier and VGA are
approximately 110 MHz each, resulting in a cascaded BW of
approximately 80 MHz. Ultimately the BW of the PrA limits the
accuracy of the synthesized RIN. For RIN = RS up to approximately
200 Ω, the best match is between 100 kHz and 10 MHz, where
the lower frequency limit is determined by the size of the ac
coupling capacitors, and the upper limit is determined by the
preamplifier BW. Furthermore, the input capacitance and RS
limits the BW at higher frequencies.
INPUT IMPEDANCE (Ω)
FREQUENCY (Hz)
04976-102
10
100
1k
100k 1M 10M 50M
R
IN
= 500Ω, R
FB
= 2.5kΩR
SH
=
∞
, C
SH
= 0pF
R
IN
= 200Ω, R
FB
= 1kΩ
R
SH
= 50Ω, C
SH
= 22pF
R
IN
= 100Ω, R
FB
= 499Ω
R
IN
= 50Ω, R
FB
= 249Ω
R
SH
=
∞
, C
SH
= 0pF
R
SH
= 50Ω, C
SH
= 22pF
Figure 55. RIN vs. Frequency for Various Values of RFB;
Effects of RSH and CSH are also shown.
Figure 55 shows RIN vs. frequency for various values of RFB. Note
that at the lowest value, 50 Ω, RIN peaks at frequencies greater than
10 MHz. This is due to the BW roll-off of the PrA as mentioned
earlier. The RSH and CSH network shown in Figure 58 reduces
this peaking.
However, as can be seen for larger RIN values, parasitic capacitance
starts rolling off the signal BW before the PrA can produce
peaking and the RSH/CSH network further degrades the match.
Therefore, RSH and CSH should not be used for values of RIN
greater than 50 Ω.
Noise
The total input referred noise (IRN) is approximately 1.3 nV/√Hz.
Allowing for a gain of ×8 in the preamp, the VGA noise is
0.46 nV/√Hz referred to the PrA input. The preamp noise is
1.2 nV/√Hz. It is important to note that these noise values include
all amplifier noise sources, including the VGA and the preamplifier
gain resistors. Frequently, manufacturer noise specifications
exclude gain setting resistors, and the voltage noise spectral density
of an op amp might be presented as 1 nV/√Hz. Including the
gain resistors results in a much higher noise specification.
AD8335 Data Sheet
Rev. B | Page 18 of 28
Figure 56 shows the simulated noise figure (NF) vs. source
resistance, and various values of preamplifier RIN from 50 Ω to
14.7 kΩ, the value seen looking into the PIPx pins when RFB = ∞.
As shown in the figure, the minimum NF for RIN = 50 Ω is slightly
less than 7 dB. Note that, for this preamplifier, the NF is optimized
for the RIN from 50 Ω to 200 Ω; for RFB = ∞, the minimum NF is at
approximately 480 Ω. This optimum noise resistance can also be
calculated by dividing the input referred voltage noise by the
current noise.
0
2
4
6
8
10
NOISE FIGURE (dB)
12
14
16
R
S
(Ω)
10 100 1k
04976-066
R
IN
= 50Ω
R
FB
= 250Ω
R
IN
= 75Ω
R
FB
= 375Ω
R
IN
= 100Ω
R
FB
= 500Ω
R
IN
= 200Ω
R
FB
= 1kΩ
R
IN
= 14.7kΩ
R
FB
=
∞
SIMULATION
INCLUDES NOISE OF VGA
f = 1MHz
Figure 56. Simulated Noise Figure vs. RS for
Various Fixed Values of RIN, Actively Matched
VGA
As seen in Figure 54, the basic architecture, an X-AMP®, consists of
a ladder attenuator, followed by a fixed gain amplifier with selectable
input stages. Earlier examples of this architecture are to be found in
the AD60x series, AD8331/AD8332, andAD8367 VGAs. Through
a proprietary, temperature-compensated interpolator design, the
bias currents to the input gm stages are continuously steered from
right to left (decreasing attenuation) resulting in increasing gain.
The HLxx gain pins (HL12 and HL34) select one of two output
amplifier networks consisting of the feedback resistors, amplifier
stages, and buffers.
Optimizing the System Dynamic Range
The VGA output gain switch of 8 dB (×2.5) optimizes the VGA
noise floor for a 10-bit or 12-bit ADC, assuming a full-scale ADC
input voltage of 1 V p-p.
At low gain, the ADC SNR should limit the system noise
performance, whereas at high gains, the noise is defined by
the source and preamplifier. The maximum voltage swing is
bounded by the full-scale, peak-to-peak ADC input voltage
(typically 1 V p-p to 2 V p-p). The noise performance is optimized
by adjusting the noise floor of the VGA according to the ADC
resolution. The SNR of a 12-bit converter is theoretically 12 dB
better than a 10-bit; however, approximately 8 dB is typical in
practice, accounting for the 8 dB gain option of the AD8335. The
IRN and the power consumption of the VGA are unaffected by
either gain setting; therefore, only the output referred noise
(ORN) changes (by 8 dB) without affecting any other parameters.
Attenuator
The attenuator is an 8-stage differential R-2R ladder with a total
attenuation of 48.16 dB or 6.02 dB per tap. The effective input
resistance per side is 320 Ω nominal for a total differential resis-
tance of 640 Ω. The common-mode voltage of the attenuator
and the VGA is controlled by an amplifier that uses the same
midsupply voltage derived in the preamplifier, permitting dc
coupling of the PrA to the VGA without introducing large offsets
due to common-mode differences. However, when dc coupling
between the PrA and VGA, any offset from the PrA is amplified
as the gain is increased, producing an exponentially increasing
VGA output offset. When the PrA and the VGA are ac-coupled,
the output offset is unchanged with changes in gain (see Figure 15).
As a result, ac coupling is recommended for most applications.
As can be seen from Figure 54, The VCMx pins connect to the
respective midpoints on each channel and are used to ac decouple
the common-mode node at high frequencies. It is very important
that at least a 0.1 µF capacitor be used, with better decoupling at
higher frequencies when another smaller capacitor (10 nF) is
connected in parallel. The internal +1 buffer provides correct
common-mode bias levels and any dynamic currents have to be
absorbed by the external decoupling capacitors.
Gain Control
The gain control interface has two inputs, VGAIN (VGNx pins)
and VSLP (SLxx pins). The slope input is intended only as a
decoupling pin, and the only guaranteed gain slope is the
20 dB/V default. However, if a voltage is applied to the VSLP
inputs, the gain slope can be increased by reducing the slope
voltage. For example, if a voltage of 1.67 V is applied to the SLxx
pins, the gain slope changes to 30 dB/V. Use Equation 4 to
calculate the gain slope.
Slope
VSLP dB/V1.20V5.2 ×
= (4)
VGAIN varies the gain of the VGA through the interpolator by
selecting the appropriate input stages connected to the input
attenuator. The nominal VGAIN range for 20 dB/V is 0 V to 3 V,
with the best gain linearity from approximately 0.5 V to 2.5 V,
where the error is typically less than ±0.2 dB. For VGAIN voltages
above 2.5 V and less than 0.5 V, the error increases (see Figure 4).
The value of the VGAIN voltage can be increased to that of the
supply voltage, without gain foldover.
Each channel has separate gain control pins that can be connected
to a common voltage source such as found in most ultrasound
applications. For control of individual channels, connect the
appropriate gain control signal to each channel.
Data Sheet AD8335
Rev. B | Page 19 of 28
Output Stage VGA Noise
Duplicate output stages of the VGA provide an 8 dB (×2.5) gain
switch. The gain switch is intended to optimize the output noise
floor for either a 10-bit or a 12-bit ADC. The VGA gain is 20 dB
(×10) in low gain mode and 28 dB (×25) in high gain mode. The
logic setting of the HLxx pins selects between output amplifiers
including the gain resistors and feedback buffers.
As with all X-AMPs, the output noise of the VGA is constant with
gain. This causes the input referred noise to increase as the gain
is decreased. This characteristic is desirable in receiver applications
where wide dynamic range input signals are compressed with a
fixed ceiling and noise floor into an ADC. The VGA output noise is
approximately 33 nV/√Hz in low gain mode and 2.5 times higher
than this, 83 nV/√Hz, in high gain mode. As the gain increases,
the noise of the preamplifier prevails and, at the maximum VGA
gain, the output noise is approximately 90 nV/√Hz and 225
nV/√Hz for low and high gain modes, respectively.
100 MHz bandwidth is maintained between the amplifiers by
changing the compensation capacitance as the gain switches gain
settings. Power consumption is the same for either level of gain.
In certain applications, power consumption can be reduced by
lowering the supply voltage as much as possible; however, the
output dynamic range is affected by the more limited swing.
The fully differential signal path of the AD8335 restores 6 dB
of dynamic range, and the common-mode level is maintained
automatically at half the supply voltage for maximum signal swing.
The differential signal has the added benefit of suppressing the
even order harmonics.
The output SNR is determined by the noise floor and the largest
signal level, typically limited by the FS of the ADC. Modulation
noise, essentially the noise introduced by the gain control input,
can be troublesome. Normally one tends to look at the main
amplifier signal path for noise, but a VGA is really a multiplier
with the following function:
REF
IN
GAIN
OUT V
V
V
V
×
= (5)
The output amplifier is designed to drive a nominal differential
load of 500 Ω or greater; the signal swing can be as large as
5 V p-p differential before clipping occurs. However, that distortion
increases before reaching the clipping level. Distortion is shown
in Figure 25 through Figure 34 for typical values of 1 V p-p or
2 V p-p (full-scale inputs for many ADCs). The output is ac-
coupled to a differential antialias filter driving a differential
ADC. Most modern ADCs have differential inputs and achieve
optimum performance when driven differentially. For more
information, see the Applications Information section.
where VREF (bias) and VGAIN (gain control interface) are both
noise contributors under certain conditions. It is therefore
important that the gain control signals be kept clean, especially
at higher gain control slopes.
AD8335 Data Sheet
Rev. B | Page 20 of 28
APPLICATIONS INFORMATION
ULTRASOUND
The primary application for the AD8335 is medical ultrasound.
Figure 57 shows a simplified block diagram of an ultrasound
system. The most critical function of an ultrasound system is
the time gain control (TGC) compensation for physiological
signal attenuation. Because the attenuation of ultrasound signals is
exponential with respect to distance (time), a linear-in-dB VGA
is the optimal solution.
Key requirements in an ultrasound signal chain are very low
noise, active input termination, fast overload recovery, low
power, and differential drive to an ADC. Because ultrasound
machines use beamforming techniques requiring large binary
weighted numbers (for example, 32 to 512) of channels, the
lowest power at the lowest possible noise is of key importance.
Most modern machines use digital beamforming. In this technique,
the signal is converted to digital format immediately following
the TGC amplifier; beamforming is done digitally.
Typical ADC resolution in general purpose machines is 10 bits
with sampling rates greater than 40 MSPS, and high-end systems
use 12 bits.
Power consumption and low cost are of primary importance in
low-end and portable ultrasound machines, and the AD8335 is
designed for these criteria.
For additional information regarding ultrasound systems, refer
to “How Ultrasound System Considerations Influence Front-End
Component Choice”, Analog Dialogue, Vol. 36, No. 3, May–July
2003. (www.analog.com/library/analogDialogue/archives/36-
03/ultrasound/index.html)
BEAMFORMER
CENTRAL CONTROL
Rx BEAMFORMER
(B AND F MODES)
COLOR
DOPPLER (PW)
PROCESSING
(F MODE)
IMAGE AND
MOTION
PROCESSING
(B MODE)
SPECTRAL
DOPPLER
PROCESSING
MODE
DISPLAY
AUDIO
OUTPUT
TX BEAMFORMER
CW (ANALOG)
BEAMFORMER
LNAs
TRANSDUCER
ARRAY
128, 256 ETC.
ELEMENTS
BIDIRECTIONAL
CABLE
HV
MUX/
DEMUX
T/R
SWITCHES
TX HV AMPs
MULTICHANNEL
TGC USES MANY VGAs
TGC
TIME GAIN COMPENSATION
04976-053
VGAs
AD8335
Figure 57. Simplified Ultrasound System Block Diagram
Data Sheet AD8335
Rev. B | Page 21 of 28
BASIC CONNECTIONS
Figure 58 shows the basic connections for the AD8335. Input
signals enter from the left and output signals exit from the right,
providing straight line signal paths. Of course, a device with
four differential VGAs such as this requires a multilayer printed
circuit board. Power supply isolation is shown for the preamps,
and for the VGA sections. If components are mounted to both
sides of the board, those in the signal path should be located on
the top, with power-supply decoupling components on the
wiring side.
PREAMP CONNECTIONS
To configure the AD8335 for input matching, a feedback resistor
(RFB) is ac-coupled between Pin PONx and Pin PIPx. AC coupling
accommodates dissimilar common-mode voltages at the input
and output ports. For values of RSOURCE between 50 Ω and 200 Ω,
RFB is simply 5 × RSOURCE. Table 6 lists a few larger values of source
resistor (or RIN), along with the exact value and nearest standard
1% feedback resistor. For values other those than listed in Table 6,
RFB can be calculated using Equation 6. For values larger than
1 kΩ, it may be advantageous to simply remove RFB.
Table 6. Feedback Resistor Values for Various Input
Resistances
RIN (Ω) Exact RFB Value (Ω) Nearest Standard 1% Value (Ω)
200 1014 1.02 k
500 2588 2.61 k
1000 5365 5.36 k
k7.14
1
5
)(
IN
IN
FB R
R
R
−
×
= (6)
PIP2
C
SH
2
22pF R
FB
2
249Ω
PIP3
C
SH
3
22pF
R
FB
3
249Ω
R
SH
3
49.9Ω
R
SH
4
49.9Ω
C
SH
4
22pF
R
FB
4
249Ω
120nH FB
+5V
VOH3
VOH4
R
SH
1
49.9Ω
C
SH
1
22pF
R
FB
1
249Ω
VGN2
1nF*
SL12
120nH FB
+5V
1nF* 1nF*
SL34
VGN1 H
+5V
L
PIP4
+5V
PIP1
VPP
VPP +5V
VOH1
VOL1
VOL2
VOH2
VOL3
VPV
VPV
VOL4
VGN3VGN4
VPP
VPP
1nF*
0.1µF
0.1µF
0.1µF 0.1µF
0.1µF
0.1µF 0.1µF
0.1µF
0.1µF
0.1µF
0.1µF
0.1µF
0.1µF
0.1µF
0.1µF
0.1µF
0.1µF
0.1µF
0.1µF
0.1µF
0.1µF
0.1µF
0.1µF
0.1µF
0.1µF
0.1µF
0.1µF
0.1µF
0.1µF
0.1µF
0.1µF
0.1µF
0.1µF 0.1µF
0.1
µ
F
0.1µF
50 49
56 55 5154 53 5258 57
5962 61 60
VIP1
PON1
VCM2
PIP1
63
POP1
VPP1
VIN1
EN12
VCM1
PMD1
VGN1
SL12
VGN2
SP12
COM1
64
HL12
GND4
VPV2
VOL2
VOH1
VOL1
VOH2
VPV4
VOH3
VOL3
VOH4
VPV3
VOL4
VPV1
GND1
35
36
37
38
42
39
40
41
34
33
48
47
43
46
45
44
GND3
GND2
H
+5V
L
2825 26 2717 18 19 21 22 23 24 29 30 31 32
PMD4
PIP4
POP4
VPP4
SP34
SL34
EN34
VCM3
VIP4
VCM4
COM4
VGN4
VIN4
VGN3
PON4
HL34
20
PMD2
PON2
PIP2
COM2
VIP2
VIN2
POP2
COM3
VIP3
VIN3
PIP3
PON3
PMD3
POP3
VPP3
VPP2
15
16
8
7
6
5
1
4
3
2
14
13
9
12
11
10
AD8335
04976-056
VPP
*SEE TEXT
R
SH
2
49.9Ω
Figure 58. Basic Connections for RIN = 50 Ω
AD8335 Data Sheet
Rev. B | Page 22 of 28
The preamp PMD pins must be capacitively coupled to ground.
Although the preamplifier is a differential design, the PMD pins
are the internal input bias nodes and are made available for
bypassing only. Do not use these pins as signal inputs.
The PIPx inputs must be capacitively coupled from the signal
source because they have a nominal dc level of more than half
the supply voltage. AC coupling capacitors throughout the circuit
should be as large as possible for the application. Although 0.1 µF
capacitors are shown in Figure 58 (and used in most positions
in the evaluation board), values of these capacitors should be
determined by the application. Capacitors used for coupling
PMDx and PIPx pins should be the same value.
When synthesizing low values of RIN, the bandwidth of the
preamplifier produces some peaking at the high end of the
frequency response. The optional series RSHx/CSHx network shown
in Figure 58 flattens the response (see Figure 55). With a 50 Ω
source, the resistor and capacitor values should be 49.9 Ω and
22 pF. For RS values greater than 100 Ω, the network is not needed.
The circuit is stable in either scenario.
The starred capacitors in Figure 58 (*) on the VGNx pins can be
removed when faster gain control signals are required.
INPUT OVERDRIVE
Excellent overload behavior is of primary importance in ultra-
sound. Both the preamplifier and VGA have built-in overdrive
protection and quickly recover after an overload event.
Input Overload Protection
As with any amplifier, voltage clamping prior to the inputs is
highly recommended if the application is subject to high
transient voltages.
A block diagram of a simplified ultrasound transducer interface
is shown in Figure 59. A common transducer element serves the
dual functions of transmit and receive of ultrasound energy. During
the transmit phase, high voltage pulses are applied to the ceramic
elements. A typical T/R (transmit/receive) switch may consist of
four high voltage diodes in a bridge configuration. Although they
ideally block transmit pulses from the sensitive receiver input,
diode characteristics are not ideal, and resulting leakage
transients impinging on the PIPx inputs can be problematic.
Because ultrasound is a pulse system, and time-of-flight is used to
determine depth, quick recovery from input overloads is essential.
Overload can occur in the preamp and the VGA. Immediately
following a transmit pulse, the typical VGA gains are low, and
the PrA is subject to overload from T/R switch leakage. With
increasing gain, the VGA can become overloaded from strong
echoes that occur with near field echoes and acoustically dense
materials, such as bone.
Figure 59 illustrates an external overload protection scheme. A
pair of back-to-back Schottky diodes is installed prior to installing
the ac-coupling capacitors. Although the BAS40 is shown, many
types are available and merit investigation by the user. With such
diodes, clamping levels of ±0.5 V or less greatly enhance the
system overload performance.
PrA
18dB
Rs
T
RANSDUCE
R
–HV
BAS40-04
PMDx
PIPx
PONx
POPx
OPTIONAL
SCHOTTKY
OVERLOAD
CLAMP
RFB
3
21
+H
V
04976-057
Figure 59. Input Overload Protection
LOGIC INPUTS
The EN12 and EN34 enable pins, the SP12 and SP34 preamp
shutdown pins, and the HL12 and HL34 high/low pins are all
logic inputs of the AD8335. The enable inputs turn on and off
each of the corresponding pairs of channels; the preamp shutdown
pins do the same for the preamplifiers only; inputs HL12 and
HL34 set the high/low gain for Channel 1 and Channel 2, and
Channel 3 and Channel 4, respectively.
Shutting down the preamplifiers allows use of the VGAs alone,
while reducing power consumption. The VGAs cannot be shut
down independently. The SPxx (shutdown preamp) pins are
logic high; thus, the pins are grounded to enable the preamplifiers.
The pins can be enabled by connecting to the supply or to ground
for fixed enable or disable, or to the output of a logic device. Be
sure to check the data sheet of the device for voltage and current
requirements.
COMMON-MODE PINS
The common-mode VCMx pins are provided for bypassing the
internal common-mode reference for each channel to ground.
They require a capacitor at each of the four pins and can neither
be connected together nor driven by an external source.
DRIVING ADCs
The AD8335 VGA is designed to drive 10-bit and 12-bit ADCs
with minimal extra components. Because the AD8335 is a single
supply 5 V part and many of the newest ADCs operate from a 3 V
supply, dissimilar common-mode voltages exist between the VGA
output and the ADC input. This level shift is most easily accom-
modated by ac coupling, especially if the signal is filtered, as is
the case in most ultrasound and communications applications.
When an antialiasing filter (AAF) is called for, it is advantageous
to implement a differential configuration. A fully differential
AAF requires approximately 1.5 times the number of components
than a single-ended filter, because the components that in the
single-ended case are tied to ground, now connect across the
differential signal path. Although the series components double,
the component count for the differential filter is more economical
when compared to simply building a pair of single-ended filters
requiring twice as many components.
Data Sheet AD8335
Rev. B | Page 23 of 28
EVALUATION BOARD
The AD8335 evaluation board is a convenient way to experiment
with the operation and features of the AD8335 quad VGA.
Switches connect or disconnect the low noise preamp and VGA
channels and the two gain ranges. Just connect a 5 V/200 mA
power supply to the red and black test loop and a differential
probe (or two single-ended scope probes) to the output 2-pin
headers to observe the output voltage. Test loops are also provided
for the gain voltage inputs, which are typically dc bias voltages
between 0 V and 3 V. The LNA and VGA channels are enabled
independently. All channels are tested functionally before shipment.
The low noise preamp active input matching is configured for
50 Ω to terminate a corresponding signal generator or network
analyzer. Input impedances up to 14.7 kΩ are possible by
adjusting RFB1 through RFB4 using the resistor values listed in
Table 6. All passive components are 0603 size surface-mount
components. A low noise voltage source (be careful of noise at
the switching supply terminals) is recommended for gain control
voltage (VGN1, VGN2, VGN3, and VGN4) inputs.
BOARD LAYOUT
The evaluation board has a four-layer construction that provides a
solid near-zero impedance ground, with power and ground on
the inner layers, and interconnecting circuitry on the outer layers.
Figure 63 through Figure 68 illustrate various board layers.
04976-060
Figure 60. Photograph of the AD8335-EVALZ Evaluation Board
AD8335 Data Sheet
Rev. B | Page 24 of 28
2825 26 2717 18 19 21 22 23 24
50 49
56 55 5154 53 52
35
36
37
38
42
39
40
41
34
33
29 30 31 32
48
47
43
46
45
44
58 57
5962 61 60
PMD4
PIN4
POP4
VPP4
SP34
SL34
EN34
VCM3
VIP4
VCM4
COM4
VGN4
VIN4
VGN3
PON4
HL34
VIP1
PON1
VCM2
PIN1
63
POP1
VPP1
VIN1
EN12
VCM1
PMD1
VGN1
SL12
VGN2
SP12
COM1
64
20
PIN2
IN2
RS2
49.9Ω
RFB2
249Ω
PIN3
RFB3
249Ω
IN3
RS3
49.9Ω
RS4
49.9Ω
RFB4
249Ω
VGN3
VO2
VO1
VO3
VO4
RS1
49.9Ω
RFB1
249Ω
IN4
IN1
HL12
+5V
+5V
VGN4
HI
LO
+5V
SL34
EN
DIS
EN34 DIS-PRE
HI
+5V
LO
PIN4 +5V
VPV
HL34
HL12
+5V
GND4
VPV2
VOL2
VOH1
VOL1
VOH2
VPV4
VOH3
VOL3
VOH4
VPV3
VOL4
VPV1
GND1
GND3
GND2
VPV
+5V
PMD2
PON2
PIN2
COM2
VIP2
VIN2
POP2
COM3
VIP3
VIN3
PIN3
PON3
PMD3
POP3
VPP3
VPP2
GND3GND2GND1 GND4
+
GND
SP34
SL12
15
16
8
7
6
5
1
4
3
2
14
13
9
12
11
10
+5V
EN
DIS
EN12
EN-PRE
04976-061
PIN1
C10
0.1µF
+5
+5V
C3
10µF
10V
C83
0.1µF
C8
0.1µF
C14
0.1µF
C1
0.1µF
C9
.1µF
C71
0.1µF
C85
0.1µF
C84
0.1µF
C65
0.1µF C60
0.1µF
C26
0.1µF
C21
0.1µF
C24
0.1µF
CS3
22pF
CS4
22pF
CFB4
.018µF
C19
0.1µF
C18
0.1µF
C23
0.1µF
C20
0.1µF
C11
0.1µF
+5V
VGN1 C68
0.1µF
VGN2
C16
1nF
C81
1nF
C53
0.1µF
C57
0.1µF
L21
20nH FB
C62
0.1µF
C74
0.1µF
C55
0.1µF
CFB2
.018µF
CS1
22pF
CFB1
.018µF
C64
1nF
C80
1nF
C7
0.1 µF
EN-PRE
DIS-PRE
SP12
AD8335
CS2
22pF
C27
0.1µF CFB3
.018 µF
Figure 61. AD8335-EVALZ Schematic Diagram
Data Sheet AD8335
Rev. B | Page 25 of 28
DIFFERENTIAL PROBE
GND
GND
NETWORK ANALYZER
POWER
SUPPLY
SIGNAL
INPUT
PRECISION VOLTAGE REFERENCE
(FOR VGAIN)
PROBE POWER SUPPLY
04976-063
0 TO +3 V
Figure 62. AD8335-EVALZ Typical Test Connections
AD8335 Data Sheet
Rev. B | Page 26 of 28
04976-064
Figure 63. AD8335-EVALZ Assembly
04976-065
Figure 64. AD8335-EVALZ Component Side Copper
0
4976-069
Figure 65. AD8335-EVALZ Secondary Side Copper
04976-070
Figure 66. AD8335-EVALZ Internal Power Plane
Data Sheet AD8335
Rev. B | Page 27 of 28
04976-071
Figure 67. AD8335-EVALZ Internal Ground Plane
04976-072
Figure 68. AD8335-EVALZ Primary Side Silk screen
AD8335 Data Sheet
Rev. B | Page 28 of 28
OUTLINE DIMENSIONS
PIN 1
INDICATOR
TOP
VIEW
8.75
BSC SQ
9.00
BSC SQ
1
64
16
17
49
48
32
33
0.50
0.40
0.30
0.50 BSC 0.20 REF
12° MAX 0.80 MAX
0.65 TYP
1.00
0.85
0.80
7.50
REF
0.05 MAX
0.02 NOM
0.60 MAX
0.60 MAX
*4.85
4.70 SQ
4.55
EXPOSED PAD
(BOTTOM VIEW)
*COMPLIANT TO JEDEC STANDARDS MO-220-VMMD-4
EXCEPT FOR EXPOSED PAD DIMENSION
082908-B
SEATING
PLANE
PIN 1
INDICATOR
0.30
0.25
0.18
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
Figure 69. 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
9 mm × 9 mm Body, Very Thin Quad
(CP-64-1)
Dimensions shown in millimeters
ORDERING GUIDE
Model1 Temperature Range Package Description Package Option
AD8335ACPZ −40°C to +85°C 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-64-1
AD8335ACPZ-REEL −40°C to +85°C 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-64-1
AD8335ACPZ-REEL7 −40°C to +85°C 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-64-1
AD8335-EVALZ Evaluation Board
1 Z = RoHS Compliant Part.
©2004–2012 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D04976-0-2/12(B)