UC3845D - Fairchild Semiconductor

www.fairchildsemi.com

Rev. 1.0.1

Features

• Low Start up Current

• Maximum Duty Clamp

• UVLO With Hysteresis

• Op erating Frequency up to 500 KHz

Description

The UC3842/UC 3843/ UC3844/UC3845 are fixed

frequencycurrent-mode PWM controller . They are specially

desi gn ed fo r O ff-Line and DC to D C con ve r t e r applic ations

with minimum external com ponents. These integrated

circuits feature a trimmed oscillator fo r pr ecise du ty cycle

control, a temperature compensated ref erence, high gain

error amplifier, current sensing comparator and a hi gh

curr ent t ote mp ol e ou t pu t for dr i vi n g a Pow e r M OSFE T. The

UC38 42 and UC3844 have UVLO th resholds of 16V (on)

and 10V (off). The UC3843 and UC3845 are 8.5V(on) and

7.9V (off). The UC3842 and UC3843 can operate within

100% duty cycle. The UC3844 and UC3845 can operate

with 50% duty cycle.

8-DIP

14-SOP

8-SOP

Internal Block Diagram

UC3842/UC3843/UC3844/UC3845

SMPS Controller

* NORMALLY 8DIP/8SOP PIN NO.

* ( ) IS 14SOP PINNO.

* TOGGLE FLIP FLOP USED ON LY IN UC3844, UC3845

UC3842/UC3843/UC3844/UC3845

Absolute Maximum Ratings

Note:

1. Board Thickness 1.6mm, Board Dimension 76.2mm ×114.3mm, (Reference EIA / JSED51-3, 51-7)

2. Do not exceeed PD and SOA (Safe Operation Area)

Power Dissipation Curve

Thermal Data

Pin Array

Parameter Symbol Value Unit

Supply Voltage VCC 30 V

Output Current IO±1A

Analog Inputs (Pin 2.3) V(ANA) -0.3 to 6.3 V

Error Amp Output Sink Current ISINK (E.A) 10 mA

Power Dissipation at TA≤25°C (8DIP) PD(Note1,2) 1200 mW

Power Dissipation at TA≤25°C (8SOP) PD(Note1,2) 460 mW

Power Dissipation at TA≤25°C (14SOP) PD(Note1,2) 680 mW

Storage Temperature Range TSTG -65 ~ +150 °C

Lead Temperature (Soldering, 10sec) TLEAD +300 °C

Characteristic Symbol 8-DIP 8-SOP 14-SOP Unit

Thermal Resistance Junction-ambient Rthj-amb(MAX) 100 265 180 °C/W

800

700

600

500

400

300

900

1000

1100

0 102030405060708090100110120130140150

AMBIENT TEMPERATURE (℃)

POW ER DISSIPATI ON (mW)

1200 8DIP

14SOP

8SOP

800

700

600

500

400

300

900

1000

1100

0 102030405030 40 50 60 70 8060 70 80 90 100 11090 100 110 120 130 140120 130 140 150

AMBIENT TEMPERATURE (℃)

POW ER DISSIPATI ON (mW)

1200 8DIP

14SOP

8SOP

VCC

GND

PW R GND

COMP 1

N/C 2

VFB

N/C

VREF

N/C

PW R VC

CURR ENT SENSE 5

N/C

RT/CT

OUTPUT

COMP 1

VFB 2

CURR ENT SENSE

RT/CT

VREF

VCC

OUTPUT

GND

8DIP,8SOP 14SOP

VCC

GND

PW R GND

COMP 1

N/C 2

VFB

N/C

VREF

N/C

PW R VC

CURR ENT SENSE 5

N/C

RT/CT

OUTPUT

VCC

GND

PW R GND

COMP 1

N/C 2

VFB

N/C

VREF

N/C

PW R VC

CURR ENT SENSE 5

N/C

RT/CT

OUTPUT

COMP 1

VFB 2

CURR ENT SENSE

RT/CT

VREF

VCC

OUTPUT

GND

COMP 1

VFB 2

CURR ENT SENSE

RT/CT

VREF

VCC

OUTPUT

GND

8DIP,8SOP 14SOP

UC3842/UC3843/UC3844/UC3845

Electrical Characteristics

(VCC=15V, RT=10kΩ, CT=3.3nF, TA= 0°C to +70°C, unless otherwise specified)

Parameter Symbol Conditions Min. Typ. Max. Unit

REFERENCE SECTION

Reference Output Voltage VREF TJ = 25°C, IREF = 1mA 4.90 5.00 5.10 V

Line Regulation ∆VREF 12V ≤ VCC ≤ 25V - 6 20 mV

Load Regulation ∆VREF 1mA ≤ IREF ≤ 20mA - 6 25 mV

Short Circuit Output Current ISC TA = 25°C - -100 -180 mA

OSCILLATOR SECTION

Oscillation Frequency f TJ = 25°C475257kHz

Frequency Change with

Voltage ∆f/∆VCC 12V ≤ VCC ≤ 25V - 0.05 1 %

Oscillator Amplitude VOSC --1.6-V

P-P

ERROR AMPLIFIER SECTION

Input Bias Current IBIAS ---0.1-2µA

Input Voltage VI(E>A) Vpin1 = 2.5V 2.42 2.50 2.58 V

Open Loop Voltage Gain GVO 2V ≤ VO ≤ 4V (Note3) 65 90 - dB

Power Supply Rejection Ratio PSRR 12V ≤ VCC ≤ 25V (Note3) 60 70 - dB

Output Sink Current ISINK Vpin2 = 2.7V, Vpin1 = 1.1V 2 7 - mA

Output Source Current ISOURCE Vpin2 = 2.3V, Vpin1 = 5V -0.6 -1.0 - mA

High Output Voltage VOH Vpin2 = 2.3V, RL = 15k Ω to GND 5 6 - V

Low Output Voltage VOL Vpin2 = 2.7V, RL = 15kΩ to Pin 8 - 0.8 1.1 V

CURRENT SENSE SECTION

Gain GV (Note 1 & 2) 2.85 3 3.15 V/V

Maximum Input Signal VI(MAX) Vpin1 = 5V(Note 1) 0.9 1 1.1 V

Power Supply Rejection Ratio PSRR 12V ≤ VCC ≤ 25V (Note 1,3) - 70 - dB

Input Bias Current IBIAS ---3-10µA

OUTPUT SECTION

Low Output Voltage VOL

ISINK = 20mA - 0.08 0.4 V

ISINK = 200mA - 1.4 2.2 V

High Output Voltage

VOH ISOURCE = 20mA 13 13.5 - V

ISOURCE = 200mA 12 13.0 - V

Rise Time tR TJ = 25°C, CL= 1nF (Note 3) - 45 150 ns

Fall Time tF TJ = 25°C, CL= 1nF (Note 3) - 35 150 ns

UNDER-VOLTAGE LOCKOUT SECTION

Start Threshold

VTH(ST) UC3842/UC3844 14.5 16.0 17.5 V

UC3843/UC3845 7.8 8.4 9.0 V

Min. Operating Voltage

(After Turn On) VOPR(MIN) UC3842/UC3844 8.5 10.0 11.5 V

UC3843/UC3844 7.0 7.6 8.2 V

UC3842/UC3843/UC3844/UC3845

Electrical Characteristics (Continued)

(VCC=15V, RT=10kΩ, CT=3.3nF, TA= 0°C to +70°C, unless otherwise specified)

Adjust VCC above the start threshould before setting at 15V

Note:

1. Paramet er me asured at trip po int of latch

2. Gain defined as:

3. These parameters, although guaranteed, are not 100 tested in production.

Figure 1. Open Loop Test Ci rcuit

High peak currents associated with capacitive loads necessitate careful grounding techniques Timing and bypass capacitors

should be connected clos e to pin 5 in a single point ground. T he tr ansistor and 5kΩ potentiometer are used to sample the

oscillator waveform and apply an adjustable ramp to pin 3.

Parameter Symbol Conditions Min. Typ. Max. Unit

PWM SECTION

Max. Duty Cycle D(Max) UC3842/UC3843 95 97 100 %

D(Max) UC3844/UC3845 47 48 50 %

Min. Duty Cycle D(MIN) ---0%

TOTAL STANDBY CURRENT

Start-Up Current IST --0.451mA

Operating Supply Current ICC(OPR) Vpin3=Vpin2=ON - 14 17 mA

Zener Voltage VZ ICC = 25mA 30 38 - V

A∆Vpin1

∆Vpin3

------------------=

UC3842

,0 ≤ Vpin3 ≤ 0.8V

UC3842/UC3843/UC3844/UC3845

Figure 2. Under Voltage Lockout

During Und er-Voltag e L ock -Out , th e out put dri ver i s bi as ed to a high imp edanc e state . Pin 6 s hou ld be shu nted to gr ound wit h

a bleeder resistor to prevent activating the power switch with output leakage current.

Figure 3. Error Amp Configuration

Figure 4. Current Sense Circuit

Peak current (IS) is determ ined by the formula:

A small RC filter may be required to suppress switch transients.

UC3842/44 UC3843/45

ISMAX()

1.0V

------------=

UC3842/UC3843/UC3844/UC3845

Figure 5. Oscillator Waveforms and Maximum Duty Cycle

Oscillator timing capacitor, CT, is charged by VREF through RT and discharged by an internal current source. During the

discharge time, the internal clock signal blanks the output to the lo w state. Selection of RT and CT therefore deter mines both

oscillator frequency and maximum duty cycle. Charge and discharge times are determined by the formulas:

tc = 0.55 RT CT

Frequency, then, is: f=(tc + td)-1

Figure 8. Shutdown Techniques

Figure 6. Oscillator Dead Time & Frequency Figure 7. Timing Resistance vs Frequency

tDRTCTIn0.0063RT2.7–

0.0063RT4–

----------------------------------------





ForRT 5KΩf1.8

RTCT

---------------=,>

(Deadtime vs CT RT > 5kΩ)

UC3842/UC3843/UC3844/UC3845

Shutdown of the UC3842 can be accomplished by two methods; either raise pin 3 above 1V or pull pin 1 below a voltage two

diode dr ops ab ove gro und. E ither m ethod cause s the ou tput o f the PWM compa rato r to be hig h (refe r to bl ock di agra m). The

PWM latch is reset dominant so that the output will remain low until the next clock cycle after the shutdown condition at pins

1 and/or 3 i s r e mo ve d. I n one exa mp l e , a n e xte r na ll y l a tc he d sh ut d ow n ma y be a ccompli she d by a d di ng a n S CR whic h w il l be

reset by cycling VCC below the lower UVLO threshold. At this point the reference turns off, allowing the SCR to reset.

Figure 9. Slope Compensation

A fraction of the oscillator ramp can be resistively summed with the current sense signal to provide slope compensation for

converters requiring duty cycles over 50%. Note that capacitor, C T, forms a filter with R2 to suppress the leading edge switch

spikes.

Tempera ture (°C)

Figure 10. Temperature Dri ft (Vref) Temperature (°C)

Figure 11. Temperature Drift (Ist)

Tempera ture (°C)

Figure 12. Temperature Drift (Icc)

UC3842/UC3843

UC3842/UC3843/UC3844/UC3845

Mechanical Dimensions

Package

6.40

±0.20

3.30

±0.30

0.130

±0.012

3.40

±0.20

0.134

±0.008

#4 #5

0.252

±0.008

9.20

±0.20

0.79

2.54

0.100

0.031

()

0.46

±0.10

0.018

±0.004

0.060

±0.004

1.524

±0.10

0.362

±0.008

9.60

0.378 MAX

5.08

0.200

0.33

0.013

7.62

0~15°

0.300

MAX

MIN

0.25 +0.10

–0.05

0.010+0.004

–0.002

8-DIP

UC3842/UC3843/UC3844/UC3845

Mechanical Dimensions (Continued)

Package

8-SOP

4.92 ±0.20

0.194 ±0.008

0.41 ±0.10

0.016 ±0.004

1.27

0.050

5.72

0.225

1.55 ±0.20

0.061 ±0.008

0.1~0.25

0.004~0.001

6.00 ±0.30

0.236 ±0.012

3.95 ±0.20

0.156 ±0.008

0.50 ±0.20

0.020 ±0.008

5.13

0.202 MAX

#4 #5

0~8°

0.56

0.022

()

1.80

0.071

MAX0.10

MAX0.004

MAX

MIN

0.10

-0.05

0.15+

0.004

-0.002

0.006

UC3842/UC3843/UC3844/UC3845

Mechanical Dimensions (Continued)

Package

8.56

±0.20

0.337

±0.008

1.27

0.050

5.72

0.225

1.55

±0.10

0.061

±0.004

0.05

0.002

6.00

±0.30

0.236

±0.012

3.95

±0.20

0.156

±0.008

0.60

±0.20

0.024

±0.008

8.70

0.343 MAX

#7 #8

0~8°

#14

0.47

0.019

()

1.80

0.071

MAX0.10

MAX0.004

MAX

MIN

0.10

-0.05

0.20+

0.004

-0.002

0.008

0.10

-0.05

0.406+

0.004

-0.002

0.016

14-SOP

UC3842/UC3843/UC3844/UC3845

Ordering Information

Product Number Package Operating Temperature

UC3842N

8-DIP

0 ~ + 70°C

UC3843N

UC3844N

UC3845N

UC3842D1

8-SOP

UC3843D1

UC3844D1

UC3845D1

UC3842D

14-SOP

UC3843D

UC3844D

UC3845D

UC3842/UC3843/UC3844/UC3845

2/19/02 0.0m 001

Stock#DSxxxxxxxx

 2002 Fairchild Semicond uctor Corporation

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FAIRCHILD’S PRODUCTS AR E NOT AUTHORIZED FOR USE AS C RITICAL COMPONENTS I N LIFE S UPPORT DEVICE S

OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR

CORPORA TION. As used he rein :

1. Life support devices or systems are devices or systems

which, (a) are intended for surgical implant into the body,

or (b) support or sustain life, and (c) whose failure to

perform when properly used in accordance with

instructions for use provided in the labeling, can be

reasonably expected to result in a significant injury of the

user.

2. A critical component in any component of a life support

device or syst em who se failure to perform can be

reasonably expected to cause the failure of the life support

device or system, or to affect its safety or effec tiv ene ss.

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PRO DUCTS HEREIN TO IMPROVE RELIABILITY, FUN C TION OR DESIGN . FAIRCHILD DO ES NOT ASSUME ANY

LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER

DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIG HTS, NOR THE RIGHTS OF OTHERS.