PIC17C756AT-16I/PT - Microchip Technology

 2000 Microchip Technology Inc. DS30289B-page 1

PIC17C7XX

Microcontroller Core Features:

• Only 58 single word instructions to learn

• All single cycle instructions (121 ns), except for

program branches and table reads/writes which

are two-cycle

• Operati ng spe ed:

- DC - 33 MHz clock input

- DC - 121 ns instruction cycle

• 8 x 8 Single-Cycle Hardware Multiplier

• Interrupt capability

• 16 level deep hardware stack

• Direct, indirect, and relative addressing modes

• Internal/external program memory execution,

cap able of addres sing 64 K x 16 prog ram memory

space

Peripheral Feat ures:

• Up to 66 I/O pins with individual direction control

• 10-bit, multi-channel Analog-to-Digital converter

• High current sink/source for direct LED drive

• Four capture inpu t pins

- Captures are 16-bit, max resolution 121 ns

• Three PWM outputs (resolution is 1 to 10-bits)

• TMR0: 16-bit timer/counter with

8-bit programmable prescaler

• TMR1: 8-bit timer/counter

• TMR2: 8-bit timer/counter

• TMR3: 16-bit timer/counter

• Two Universal Synchronous Asynchronous

Receiver Transmitters (USART/SCI) with

independent baud rate generators

• Synchronous Serial Port (SSP) with SPI™ and

I2C™ modes (including I2C Master mode)

Pin Diagrams

S pecial Microcontroller Featu res:

• Power-on Reset (POR), Power-up Timer (PWRT)

and Oscillator Start-up Timer (OST)

• Watchdog Timer (WDT) with its own on-chip RC

oscillator for reliable operation

• Brown-out Reset

• Code protection

• Power saving SLEEP mode

• Selectable oscillator opti ons

CMOS Technology:

• Low power, high speed CMOS EPROM

technology

• Fully static design

• Wide operating voltage range (3.0V to 5.5V)

• Commercial and Industrial temperature ranges

• Low power consumption

- < 5 mA @ 5V, 4 MHz

- 100 µA typical @ 4.5V, 32 kHz

- < 1 µA typical standby current @ 5V

Device Memory

Program (x16) Data (x8)

PIC17C752 8 K 678

PIC17C756A 16 K 902

PIC17C762 8 K 678

PIC17C766 16 K 902

RF1/AN5

RF0/AN4

AVDD

AVSS

RG3/AN0/VREF+

RG2/AN1/VREF-

RG1/AN2

RG0/AN3

VSS

VDD

RG4/CAP3

RG5/PWM3

RG7/TX2/CK2

RG6/RX2/DT2

RA4/RX1/DT1

RA5/TX1/CK1

RJ0

RJ1

RH6/AN14

RH7/AN15

RD1/AD9

RD0/AD8

RE0/ALE

RE1/OE

RE2/WR

RE3/CAP4

MCLR/VPP

TEST

VSS

VDD

RF7/AN11

RF6/AN10

RF5/AN9

RF4/AN8

RF3/AN7

RF2/AN6

RH2

RH3

RH4/AN12

RH5/AN13

1011

26 60

53525150494847464544

987654321

323334353637383940414243

PIC17C76X

RA0/INT

RB0/CAP1

RB1/CAP2

RB3/PWM2

RB4/TCLK12

RB5/TCLK3

RB2/PWM1

VSS

OSC2/CLKOUT

OSC1/CLKIN

VDD

RB7/SDO

RA3/SDI/SDA

RA2/SS/SCL

RA1/T0CKI

RD2/AD10

RD3/AD11

RD4/AD12

RD5/AD13

RD6/AD14

RD7/AD15

RC0/AD0

VDD

VSS

RC1/AD1

RC2/AD2

RC3/AD3

RC4/AD4

RC5/AD5

RC6/AD6

RC7/AD7

RB6/SCK

RJ5

RJ4

RJ7

RJ6

RJ3

RJ2

RH1

RH0

767978778083828184 75

84 PLCC

High-Performance 8-bit CMOS EPROM Microcontr ollers with 10-bit A/D

PIC17C7XX

DS30289B-page 2  2000 Microchip Technology Inc.

Pin Diagrams cont.’d

RA0/INT

RB0/CAP1

RB1/CAP2

RB3/PWM2

RB4/TCLK12

RB5/TCLK3

RB2/PWM1

VSS

OSC2/CLKOUT

OSC1/CLKIN

VDD

RB7/SDO

RA3/SDI/SDA

RA2/SS/SCL

RA1/T0CKI

RD1/AD9

RD0/AD8

RE0/ALE

RE1/OE

RE2/WR

RE3/CAP4

MCLR/VPP

TEST

VSS

VDD

RF7/AN11

RF6/AN10

RF5/AN9

RF4/AN8

RF3/AN7

RF2/AN6

RD2/AD10

RD3/AD11

RD4/AD12

RD5/AD13

RD6/AD14

RD7/AD15

RC0/AD0

VDD

VSS

RC1/AD1

RC2/AD2

RC3/AD3

RC4/AD4

RC5/AD5

RC6/AD6

RC7/AD7

RF1/AN5

RF0/AN4

AVDD

AVSS

RG3/AN0/VREF+

RG2/AN1/VREF-

RG1/AN2

RG0/AN3

VSS

VDD

RG4/CAP3

RG5/PWM3

RG7/TX2/CK2

RG6/RX2/DT2

RA4/RX1/DT1

RA5/TX1/CK1

RB6/SCK

PIC17C75X

RD2/AD10

RD3/AD11

RD4/AD12

RD5/AD13

RD6/AD14

RD7/AD15

RC0/AD0

VDD

VSS

RC1/AD1

RC2/AD2

RC3/AD3

RC4/AD4

RC5/AD5

RC6/AD6

RC7/AD7

RD1/AD9

RD0/AD8

RE0/ALE

RE1/OE

RE2/WR

RE3/CAP4

MCLR/VPP

TEST

VSS

VDD

RF7/AN11

RF6/AN10

RF5/AN9

RF4/AN8

RF3/AN7

RF2/AN6

RA0/INT

RB0/CAP1

RB1/CAP2

RB3/PWM2

RB4/TCLK12

RB5/TCLK3

RB2/PWM1

VSS

OSC2/CLKOUT

OSC1/CLKIN

VDD

RB7/SDO

RA3/SDI/SDA

RA2/SS/SCL

RA1/T0CKI

RF1/AN5

RF0/AN4

AVDD

AVSS

RG3/AN0/VREF+

RG2/AN1/VREF-

RG1/AN2

RG0/AN3

VSS

VDD

RG4/CAP3

RG5/PWM3

RG7/TX2/CK2

RG6/RX2/DT2

RA4/RX1/DT1

RA5/TX1/CK1

RB6/SCK

PIC17C75X

68-Pin PLCC

64-Pin TQFP

 2000 Microchip Technology Inc. DS30289B-page 3

PIC17C7XX

Pin Diagrams cont.’d

RF1/AN5

RF0/AN4

AVDD

AVSS

RG3/AN0/VREF+

RG2/AN1/VREF-

RG1/AN2

RG0/AN3

VSS

VDD

RG4/CAP3

RG5/PWM3

RG7/TX2/CK2

RG6/RX2/DT2

RA4/RX1/DT1

RA5/TX1/CK1

RJ0

RJ1

RH6/AN14

RH7/AN15

RD1/AD9

RD0/AD8

RE0/ALE

RE1/OE

RE2/WR

RE3/CAP4

MCLR/VPP

TEST

VSS

VDD

RF7/AN11

RF6/AN10

RF5/AN9

RF4/AN8

RF3/AN7

RF2/AN6

RH2

RH3

RH4/AN12

RH5/AN13

1011

26 60

5352

4948

4645

987654321

323334353637383940414243

PIC17C76X

RA0/INT

RB0/CAP1

RB1/CAP2

RB3/PWM2

RB4/TCLK12

RB5/TCLK3

RB2/PWM1

VSS

OSC2/CLKOUT

OSC1/CLKIN

VDD

RB7/SDO

RA3/SDI/SDA

RA2/SS/SCL

RA1/T0CKI

RD2/AD10

RD3/AD11

RD4/AD12

RD5/AD13

RD6/AD14

RD7/AD15

RC0/AD0

VDD

VSS

RC1/AD1

RC2/AD2

RC3/AD3

RC4/AD4

RC5/AD5

RC6/AD6

RC7/AD7

RB6/SCK

RJ5

RJ4

RJ7

RJ6

RJ3

RJ2

RH1

RH0

767978778083828184 75

84-pin PLCC

64636261

212223242526272829303132

RD2/AD10

RD3/AD11

RD4/AD12

RD5/AD13

RD6/AD14

RD7/AD15

RC0/AD0

VDD

VSS

RC1/AD1

RC2/AD2

RC3/AD3

RC4/AD4

RC5/AD5

RC6/AD6

RC7/AD7

RD1/AD9

RD0/AD8

RE0/ALE

RE1/OE

RE2/WR

RE3/CAP4

MCLR/VPP

TEST

VSS

VDD

RF7/AN11

RF6/AN10

RF5/AN9

RF4/AN8

RF3/AN7

RF2/AN6

RA0/INT

RB0/CAP1

RB1/CAP2

RB3/PWM2

RB4/TCLK12

RB5/TCLK3

RB2/PWM1

VSS

OSC2/CLKOUT

OSC1/CLKIN

VDD

RB7/SDO

RA3/SDI/SDA

RA2/SS/SCL

RA1/T0CKI

RF1/AN5

RF0/AN4

AVDD

AVSS

RG3/AN0/VREF+

RG2/AN1/VREF-

RG1/AN2

RG0/AN3

VSS

VDD

RG4/CAP3

RG5/PWM3

RG7/TX2/CK2

RG6/RX2/DT2

RA4/RX1/DT1

RA5/TX1/CK1

RB6/SCK

RJ7

RJ6

RH1

RH0

RH2

RH3

RH4/AN12

RH5/AN13

RH6/AN14

RH7/AN15

RJ1

RJ0

RJ3

RJ2

RJ5

RJ4

33343536 38

68676665727170697473

78777675

7980

PIC17C76X

80-Pin TQFP

PIC17C7XX
DS30289B-page 4  2000 Microchip Technology Inc.
Table of Contents
1.0 Overview........................................................................................................................................................7
2.0 Device Varie tie s....................... ..... ...... ..... ................. ................. ................. ................. . .................................9
3.0 Architectural Overview.................................................................................................................................11
4.0 On-chip Oscillator Circuit.............................................................................................................................17
5.0 Reset............................................................................................................................................................23
6.0 Interrupts......................................................................................................................................................33
7.0 Memory Organization...................................................................................................................................43
8.0 Table Reads and Table Writes ....................................................................................................................59
9.0 Hardware Multiplier......................................................................................................................................67
10.0 I/O Ports.......................................................................................................................................................71
11.0 Overview of Timer Resources......................................................................................................................95
12.0 Timer0..........................................................................................................................................................97
13.0 Timer1, Timer2, Timer3, PWMs and Captures..........................................................................................101
14.0 Universal Synchronous Asynchronous Receiver Transmitter (USART) Modules......................................117
15.0 Master Synchronous Serial Port (MSSP) Module......................................................................................133
16.0 Analog-to-Digital Converter (A/D) Module .................................................................................................179
17.0 Special Features of the CPU .....................................................................................................................191
18.0 Instruction Set Summary............................................................................................................................197
19.0 Development Support................................................................................................................................233
20.0 PIC17C7XX Electri cal Charac teri sti cs............................ ................. ..... .................................. ... ................239
21.0 PIC17C7XX DC and AC Characteristics.............. ..... ...... ...... ..... ................. ...... ................ ...... ...................267
22.0 Packaging Information...............................................................................................................................281
Appendix A: Modifications.......................................................................................................................................287
Appendix B: Compatibility........................................................................................................................................287
Appendix C: What’s New.........................................................................................................................................288
Appendix D: What’s Changed..................................................................................................................................288
Index .......................................................................................................................................................................... 289
On-Line Support..........................................................................................................................................................299
Reader Response.......................................................................................................................................................300
Product Identification System......................................................................................................................................301
     

 2000 Microchip Technology Inc. DS30289B-page 5

PIC17C7XX

TO OUR VALUED CUSTOMERS

It is our intention to provide our valued custome rs with the best docume ntation possible to ensure succ essful use of your Micro-

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If you have any questions or comments regarding this publication, please contact the Marketing Communications Department

via E-mail at docerrors@mail.microchip.com or fa x the Reader Response Form in the back of this data sheet to (480) 792-

4150. We welcome your feedback.

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http://www.microchip.com

You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page.

The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000).

Errata

An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current

devices. As device/documentation issues become known to us, we will publish an errata sheet. The errat a will specify the revision

of silicon and revision of document to which it applies.

To determine if an errata sheet exists for a particular device, please check with one of the following:

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When contacting a sales office or the literature center, please specify which dev ice, revision of silicon and data sheet (include lit-

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Customer Noti fic atio n Syst em

PIC17C7XX

DS30289B-page 6  2000 Microchip Technology Inc.

NOTES:

 2000 Microchip Technology Inc. DS30289B-page 7

PIC17C7XX

1.0 OVERVIEW

This data sheet covers the PIC17C7XX group of the

PIC17CXXX family of microcontrollers. The following

dev i ces are discussed in this data sheet:

•PIC17C752

•PIC17C756A

•PIC17C762

•PIC17C766

The PIC17C7XX devices are 68/84-pin, EPROM

based members of the versatile PIC17CXXX family of

low cost, high performance, CMOS, fully static, 8-bit

microcontrollers.

All PICmicro® microcontrollers employ an advanced

RISC architecture. The PIC17CXXX has enhanced

core features, 16-level d eep stack, a nd multiple int ernal

and external interrupt sources. The separate instruc-

tion and da t a buse s of the Harv ard arch itectu re allow a

16-b it wide instr uction word w ith a s eparate 8-bit w ide

data path. The two stage instruction pipeline allows all

instruc tions to execu te in a single cyc le, except for pro-

gram b ranc hes (which requi re two cy cles ). A to t al o f 58

instructions (reduced instruction set) are available.

Additionally, a large register set gives some of the

architectural innovations used to achieve a very high

perf orm an c e. F o r ma t h em ati ca l in t ensive ap pl i ca tio n s,

all devices have a single cycle 8 x 8 Hardware

Multiplier.

PIC17CXXX microcontrollers typically achieve a 2:1

code compression and a 4:1 speed improvement over

other 8-bit microcontrollers in their class.

PIC17C7XX de vic es h av e u p t o 9 02 by tes o f R AM an d

66 I/O pins. In addition, the PIC17C7XX adds several

peripheral features, useful in many high performance

applications, including:

•Four timer/counters

•Four capture inputs

•Three PWM outputs

•Two independent Universal Synchronous Asyn-

chronous Receiver Transmitters (USARTs)

•An A/D converter (multi-channel, 10-bit resolution)

•A Synchronous Serial Port

(SPI and I2C w/ Master mode)

These special features reduce external components,

thus reducing cost, enhancing system reliability and

reducing power cons umption.

There ar e four oscillator opti ons, of which the s ingle pin

RC osc il lat or p r ov ide s a l ow c os t s olution, the LF oscil-

lator is fo r lo w frequenc y cry stals and mi nim iz es po wer

consum ption, XT is a st andard crystal an d the EC is for

external clock input.

The SLEEP (power-down) mode offers additional

power saving. W ake-up from SLEEP can occur through

several external and internal interrupts and device

RESETS.

A highly reliable Watchdog Timer with its own on-chip

RC osci llator pro vides protec tion aga inst so f twar e mal-

function.

There are four configuration options for the device

operational mode:

•Microprocessor

•Microcontroller

•Extende d microcontroller

•Protected microcontroller

The microprocessor and extended microcontroller

modes allow up to 64K-words of external program

memory.

The device also has Brown-out Reset circuitry. This

allows a device RESET to occur if the device VDD falls

below the Brown-out voltage trip point (BV DD). The chip

will remain in Brown-out Reset until VDD rises above

BVDD.

A UV erasable, CERQUAD p ackaged version (compat-

ible with PLCC), is ideal for code development, while

the cost-e ff ect ive On e-T i me-P rogrammab le (OTP) ver-

sion is suitable for production in any volume.

The PIC17C7XX fits perfectly in applications that

require extremely fast execution of complex software

programs. These include applications ranging from

precise motor control and industrial process control to

automot ive, ins trumen tat ion , and telec om appl ications .

The EPROM technology makes custom ization of appli-

cation p rograms (with uniqu e secu rity co des, com bina-

tions, model numbers, parameter storage, etc.) fast

and convenient. Small footprint package options

(including die sales) make the PIC17C7XX ideal for

applications with space limitations that require high

performance.

High speed execution, powerful peripheral features,

flexible I/O, and low power consumption all at low cost

make th e PIC17C7X X ideal for a wide r ange of embe d-

ded control applications.

1.1 Family and Upward Compatibility

The PIC17CXXX family of microcontrollers have archi-

tectural enhancements over the PIC16C5X and

PIC16CXX families. These enhancements allow the

device to be more efficient in software and hardware

requirements. Refer to Appendix A for a detailed list of

enhancements and modifications. Code written for

PIC16C5X or PIC16CXX can be easily ported to

PIC17CXXX devices (Appendix B).

1.2 Development Support

The PIC17CXXX family is supported by a full featured

macro assembler, a software simulator, an in-circuit

emulator, a universal programmer, a “C” compiler and

fuzzy logic support tools. For additional information,

see Section 19.0.

PIC17C7XX

DS30289B-page 8  2000 Microchip Technology Inc.

TABLE 1-1: PIC17CXXX FAMILY OF DEVICES

Features PIC17C42A PIC17C43 PIC17C44 PIC17C752 PIC17C756A PIC17C762 PIC17C766

Maximum Frequency

of Operation 33 MHz 33 MHz 33 MHz 33 MHz 33 MHz 33 MHz 33 MHz

Operating Voltage Range 2.5 - 6.0V 2.5 - 6.0V 2.5 - 6.0V 3.0 - 5.5V 3.0 - 5.5V 3.0 - 5.5V 3.0 - 5.5V

Program

Memory ( x16) (EPROM) 2 K 4 K 8 K 8 K 16 K 8 K 16 K

(ROM) — — — — — — —

Data Memory (bytes) 232 454 454 678 902 678 902

Hardware Multiplier (8 x 8) Yes Yes Yes Yes Yes Yes Yes

Timer0

(16-bit + 8-bit postscaler) Yes Yes Yes Yes Yes Yes Yes

Timer1 (8-bit) Yes Yes Yes Yes Yes Yes Yes

Timer2 (8-bit) Yes Yes Yes Yes Yes Yes Yes

Timer3 (16-bit) Yes Yes Yes Yes Yes Yes Yes

Capture inputs (16-bit) 2 2 24444

PWM outputs (up to 10-bit) 2 2 23333

USART/SCI 1 1 12222

A/D channels (10-bit) — — — 12 12 16 16

SSP (SPI/ I2C w/Master

mode) — — — Yes Yes Yes Yes

Power-on Reset Yes Yes Yes Yes Yes Yes Yes

Watchdog Timer Yes Yes Yes Yes Yes Yes Yes

External Interrupts Yes Yes Yes Yes Yes Yes Yes

Interrupt Sources 11 11 11 18 18 18 18

Code Protect Yes Yes Yes Yes Yes Yes Yes

Brown-out Reset — — — Yes Yes Yes Yes

In-Circuit Serial

Programming — — — Yes Yes Yes Yes

I/O Pins 33 33 33 50 50 66 66

I/O High

Current Capability Source 25 mA 25 mA 25 mA 25 mA 25 mA 25 mA 25 mA

Sink 25 mA(1) 25 mA(1) 25 mA(1) 25 mA(1) 25 mA(1) 25 mA(1) 25 mA(1)

Package Types 40-pin DIP

44-pin PLCC

44-pin MQFP

44-pin TQFP

40-pin DIP

44-pin PLCC

44-pin

MQFP

44-pin TQFP

40-pin DIP

44-pin PLCC

44-pin

MQFP

44-pin TQFP

64-pin TQFP

68-pin PLCC 64-pin TQFP

68-pin PLCC 80 - p i n T QFP

84-pin PLCC 80-pin TQFP

84-pin PLCC

Note 1: Pins RA2 and RA3 can sink up to 60 mA.

 2000 Microchip Technology Inc. DS30289B-page 9

PIC17C7XX

2.0 DEVICE VARIETIES

Each device has a variety of frequency ranges and

packaging options. Depending on application and pro-

duction requirements, the proper device option can be

select ed using the i nformation in the PIC17C7XX Prod-

uct Selection System section at the end of this data

sheet. When placing orders, please use the

“PIC17C7XX Product Identification System” at the

back of this data sheet to specify the correct part num-

ber. When discussing the functionality of the device,

memory technolog y and vol tage rang e does not matter .

Ther e a re t wo mem ory type op tio ns. Th ese are spe ci-

fied in the middl e cha racters of the part numbe r.

1. C, as in PIC17C756A. These devices have

EPROM type memory.

2. CR, as in PIC17CR756A. These devices have

ROM type memory.

All these devices operate over the standard voltage

range. Devices are also offered wh ich operate ov er an

extended voltage range (and reduced frequency

range). Table 2-1 show s all possib le memory types and

voltage range designators for a particular device.

These designators are in bold typeface.

TABLE 2-1: DEVICE MEMORY VARIETIES

2.1 UV Erasable Devices

The UV erasable version, offered in CERQUAD pack-

age, is optimal for prototype development and pilot

programs.

The UV erasable version can be erased and repro-

grammed to any of the configuration modes. Third

party programmers also are available; refer t o the Third

Party Guide for a list of sources.

2.2 One-Time-Programmable (OTP)

Devices

The availability of OTP devices is especially useful for

customers expecting frequent code changes and

updates.

The OTP devi ces, packaged in pl astic packages, permit

the user to program them once. In addition to the program

memory, the configuration bits must be programmed.

2.3 Quick-Turnaround-Production

(QTP) Devices

Microchip offers a QTP Programming Service for fac-

tory production orders. This service is made available

for users who choose not to program a medium to high

quantity of units and whose code patterns have stabi-

lized. The devi ces ar e id enti ca l to the O TP d e vi ce s b ut

with all EPROM locations and configuration options

already programmed by the factory. Certain code and

prototype verification procedures apply before produc-

tion shipm en ts are available. Please conta ct you r loca l

Microchip Technology sales office for more details.

2.4 Serialized Quick-Turnaround

Production (SQTP

sm) Devices

Microchip offers a unique programming service, where

a few user defined locations in each device are pro-

grammed with diffe rent serial numbers. The serial num-

bers may be random, pseudo-random or sequential.

Serial programming allows each device to have a

unique number which can serve as an entry code,

password or ID number.

2.5 Read Only Memory (ROM) Devices

Microchip offers masked ROM versions of several of

the highest volume parts, thus giving customers a low

cost option for high volume, mature products.

ROM devices do not allow serialization information in

the program memory space.

For information on submitting ROM code, please con-

tact your regional sales office.

Memory Type Voltage Range

Standard Extended

EPROM PIC17CXXX PIC17LCXXX

ROM PIC17CRXXX PIC17LCRXXX

Note: Not all memory technologies are available

for a particular device. Note: Presently, NO ROM versions of the

PIC17C7XX devices are available.

PIC17C7XX

DS30289B-page 10  2000 Microchip Technology Inc.

NOTES:

 2000 Microchip Technology Inc. DS30289B-page 11

PIC17C7XX

3.0 ARCHITECTURAL OVERVIEW

The high performance of th e PIC17CXXX can be attrib-

uted to a number of architectural features, commonly

found in RISC microprocessors. To begin with, the

PIC17CXXX uses a modified Harvard architecture.

This architecture has the program and data accessed

from sep arate memorie s. So, the device h as a program

memory bus and a data memory bus. This improves

bandwidth over traditional von Neumann architecture,

where program and data are fetched from the same

memory (accesses over the same bus). Separating

program and data memory further allows instructions to

be sized differently than the 8-bit wide data word.

PIC17CXXX opc ode s ar e 16 -bi t s wide , en abl ing si ngl e

word ins tructions. Th e full 1 6-bit wide pro gram memo ry

bus fetc hes a 16-bit i nstruc tion i n a sin gle cy cle. A tw o-

stage pipeline overlaps fetch and execution of instruc-

tions. C onsequen tly, all instructi ons execu te in a singl e

cycle (121 ns @ 33 MHz), except for program branches

and two sp ec ial ins truc ti ons tha t transfer da ta between

program and data memory.

The PIC17CXXX can address up to 64K x 16 of pro-

gram memory space.

The PIC17C752 and PIC17C762 integrate 8K x 16 of

EPROM program memory on-chip.

The PIC17C756A and PIC17C766 integrate 16K x 16

EPROM program memory on-chip.

A simplified block diagram is shown in Figure 3-1. The

descriptions of the device pins are listed in Table 3-1.

Prog ram exec ution can b e inter nal only (Mic rocont rol-

ler or Protected Microcontroller mode), external only

(Microprocessor mode), or both (Extended Microcon-

troller m od e). Exte nde d M ic roc ont roll er m od e d oes n ot

allow code protection.

The PIC17CXXX can directly or indirectly address its

ters, including the Program Counter (PC) and Working

PIC17CXXX has an orthogonal (symmetrical) instruction

set that makes it possible to carry out any operation on

any register using any addressing mode. This symmetri-

cal nature and lack of ‘special optimal situations’ make

programming with the PIC17CXXX simple, yet efficient.

In addition, the learning curve is reduc ed signi ficantly.

One of the PIC17CXXX family architectural enhance-

ment s fro m the PIC16CXX famil y, allows two file regis-

ters to be used in some two operand instructions. This

allow s dat a to be mov ed dire ctly b etween two re giste rs

without going throug h the WREG register , thus increas-

ing performance and decreasing program memory

usage.

The PIC17CXXX devices contain an 8-bit ALU and

working register. The ALU is a general purpose arith-

metic u nit. It performs arithmetic a nd Boolean funct ions

between data in the working register and any register

file.

The WR EG register is an 8-bit working regi ster used for

ALU operations .

All PIC17CXXX devices have an 8 x 8 hardware multi-

plier. Th is multipl ier generat es a 16-bi t result in a si ngle

cycle.

The ALU is 8-bits wide and capable of addition, sub-

traction, shift and logical operations. Unless otherwise

mentioned, arithmetic operations are two's comple-

ment in nature.

Depending on the instruction executed, the ALU may

affect the values of the Carry (C), Digit Carry (DC), Zero

(Z) and Overfl ow ( OV) bit s in the AL USTA register. The

C and DC bi ts opera te as a borro w and digit borrow out

bit, respectively, in subtraction. See the SUBLW and

SUBWF instructions for examples.

Signed arithmetic is comprised of a magnitude and a

sign bit. The overflow bit indicates if the magnitude

overflow s and caus es the s ign bit to change s tate. Th at

is, if the resu lt of 8-bit signed opera tions is grea ter than

127 (7Fh), or less than -128 (80h).

Signed math can have greater than 7-bit values (mag-

nitude), if mo re than one by te is used . The ove rflow bit

only operates on bit6 (MSb of magnitude) and bit7 (sign

bit) of each by te valu e in the ALU. That is , the overfl ow

bit is not useful if trying to implement signed math

where the magnitude, for example, is 11-bits.

If the signed math values are greater than 7-bits (such

as 15-, 24-, or 31-bit), the algorithm must ensure that

the low order bytes of th e signed v alue igno re the over-

flow status bit.

Example 3-1 shows two cases of doing signed arith-

metic. The Carry (C) bit and the Overflow (OV) bit are the

most import ant s t atus bit s for si gned math op era tions.

EXAMPLE 3-1: 8-BIT MATH ADDITION

Hex Value Signed Values Unsigned Values

FFh

+ 01h

= 00h

C bit = 1

OV bit = 0

DC bit = 1

Z bit = 1

-1

+ 1

= 0 (FEh)

C bit = 1

OV bit = 0

DC bit = 1

Z bit = 1

255

+ 1

= 256 → 00h

C bit = 1

OV bit = 0

DC bit = 1

Z bit = 1

Hex Value Signed Values Unsigned Values

7Fh

+ 01h

= 80h

C bit = 0

OV bit = 1

DC bit = 1

Z bit = 0

127

+ 1

= 128 → 00h

C bit = 0

OV bit = 1

DC bit = 1

Z bit = 0

127

+ 1

= 128

C bit = 0

OV bit = 1

DC bit = 1

Z bit = 0

PIC17C7XX

DS30289B-page 12  2000 Microchip Technology Inc.

FIGURE 3-1: PIC17C752/756A BLOCK DIAGRAM

RB0/CAP1

RB1/CAP2

RB2/PWM1

RB3/PWM2

RB4/TCLK12

RB5/TCLK3

RB6/SCK

RB7/SDO

RA0/INT

RA1/T0CKI

RA2/SS/SCL

RA3/SDI/SDA

RA4/RX1/DT1

RA5/TX1/CK1

PORTA

RC0/AD0

RC1/AD1

RC2/AD2

RC3/AD3

RC4/AD4

RC5/AD5

RC6/AD6

RC7/AD7

RD0/AD8

RD1/AD9

RD2/AD10

RD3/AD11

RD4/AD12

RD5/AD13

RD6/AD14

RD7/AD15

RE0/ALE

RE1/OE

RE2/WR

RE3/CAP4

RF0/AN4

RF1/AN5

RF2/AN6

RF3/AN7

RF4/AN8

RF5/AN9

RF6/AN10

RF7/AN11

RG0/AN3

RG1/AN2

RG2/AN1/VREF-

RG3/AN0/VREF+

RG4/CAP3

RG5/PWM3

RG6/RX2/DT2

RG7/TX2/CK2

Timer0

Clock

Generator

Power-on

Reset

Watchdog

Timer

Test Mode

Select

VDD, VSS

OSC1,

MCLR, VPP

Test

Q1, Q2,

Chip_reset

& Other

Control

System Bus Interface

Decode

Data Latch

Address

Program

Memory

(EPROM)

Table Pointer<16>

Stack

16 x 16

Table

ROM Latch <16>

Instruction

Decode

Control Outputs

IR Latch <16>

16K x 16

PCH

PCLATH<8>

Literal

RAM

Data Latch

BSR

Data RAM

902 x 8

Latch

PCL

Read/Write

Decode

for

Mapped

in Data

Space

WREG<8> BITOP

ALU

Shifter

8 x 8 mult

PRODH PRODL

Registers

Latch <16>

Address

Buffer

USART1

Timer1 Timer3

Timer2 PWM1

PWM2

PWM3

Capture1 Capture3

Capture2

Interrupt

Module

10-bit

A/D

PORTB

PORTC

PORTD

PORTE

PORTF

PORTG

AD<15:0>

Signals

Q3, Q4 OSC2

Data Bus<8>

IR<16>

SSP

PORTC,

PORTD

ALE,

WR,

OE,

PORTE

IR <7:0>

BSR <7:4>

USART2 Capture4

Brown-out

Reset

17C756A

17C752

8K x 16

17C756A

17C752

678 x 8

 2000 Microchip Technology Inc. DS30289B-page 13

PIC17C7XX

FIGURE 3-2: PIC17C762/766 BLOCK DIAGRAM

RB0/CAP1

RB1/CAP2

RB2/PWM1

RB3/PWM2

RB4/TCLK12

RB5/TCLK3

RB6/SCK

RB7/SDO

RA0/INT

RA1/T0CKI

RA2/SS/SCL

RA3/SDI/SDA

RA4/RX1/DT1

RA5/TX1/CK1

PORTA

RC0/AD0

RC1/AD1

RC2/AD2

RC3/AD3

RC4/AD4

RC5/AD5

RC6/AD6

RC7/AD7

RD0/AD8

RD1/AD9

RD2/AD10

RD3/AD11

RD4/AD12

RD5/AD13

RD6/AD14

RD7/AD15

RE0/ALE

RE1/OE

RE2/WR

RE3/CAP4

RF0/AN4

RF1/AN5

RF2/AN6

RF3/AN7

RF4/AN8

RF5/AN9

RF6/AN10

RF7/AN11

RG0/AN3

RG1/AN2

RG2/AN1/VREF-

RG3/AN0/VREF+

RG4/CAP3

RG5/PWM3

RG6/RX2/DT2

RG7/TX2/CK2

Timer0

Clock

Generator

Power-on

Reset

Watchdog

Timer

Test Mode

Select

VDD, VSS

OSC1,

MCLR, VPP

Test

Q1, Q2,

Chip_reset

& Other

Control

System Bus Interface

Decode

Data Latch

Address

Program

Memory

(EPROM)

Table Pointer<16>

Stack

16 x 16

Table

ROM Latch <16>

Instruction

Decode

Control Outputs

IR Latch <16>

FSR0

FSR1

16K x 16,

PCH

PCLATH<8>

Literal

RAM

Data Latch

BSR

Data RAM

902 x 8

Latch

PCL

Read/Write

Decode

for

Mapped

in Data

Space

WREG<8> BITOP

ALU

Shifter

8 x 8 mult

PRODH PRODL

Registers

Latch <16>

Address

Buffer

USART1

Timer1 Timer3

Timer2 PWM1

PWM2

PWM3

Capture1

Capture3Capture2

Interrupt

Module 10-bit

A/D

PORTB

PORTC

PORTD

PORTE

PORTF

PORTG

AD<15:0>

Signals

Q3, Q4 OSC2

Data Bus<8>

IR<16>

SSP

PORTC,

PORTD

ALE,

WR,

OE,

PORTE

IR <7:0>

BSR <7:4>

USART2

Capture4

RH0

RH1

RH2

RH3

RH4/AN12

RH5/AN13

RH6/AN14

RH7/AN15

PORTH

RJ0

RJ1

RJ2

RJ3

RJ4

RJ5

RJ6

RJ7

PORTJ

Brown-out

Reset

AVDD, AVSS

17C766

17C762

678 x 8

and

17C766

and

17C762

8K x 16

PIC17C7XX

DS30289B-page 14  2000 Microchip Technology Inc.

TABLE 3-1: PINOUT DESCRIPTIONS

Name

PIC17C75X PIC17C76X

Description

DIP

No. PLCC

No. TQFP

No. PLCC

No. QFP

No. I/O/P

Type Buffer

Type

OSC1/CLKIN 47 50 39 62 49 I ST Oscillator input in Crystal/Resonator or RC Oscillator

mode. External clock input in External Clock mode.

OSC2/CLKOUT4851406350O—Oscillator output. Connects to crystal or resonator in

Crystal Oscillator mode. In RC Oscillator or External

Clock modes, OSC2 pin outputs CLKOUT which has

one fourth the frequency (FOSC/4) of OSC1 and

denotes the instruction cycle rate.

MCLR/VPP 15 16 7 20 9 I/P ST Master clear (RESET) input or Programming V olt age

(VPP) input. This is the active low RESET input to the

device.

PORTA pins have individual differentiations that are

listed in the following descriptions:

RA0/INT 56 60 48 72 58 I ST RA0 can also be selected as an external inter-

rupt input. Interrupt can be configured to be on

positive or negative edge. Input only pin.

RA1/T0CKI 41 44 33 56 43 I ST RA1 can also be selected as an external inter-

rupt input and the interrupt can be configured to

be on positive or negative edge. RA1 can also

be selected to be the clock input to the Timer0

timer/counter. Input only pin.

RA2/SS/SCL 42 45 34 57 44 I/O(2) ST RA2 can also be used as the slave select input

for the SPI or the clock input for the I2C bus.

High voltage, high current, open drain port pin.

RA3/SDI/SDA4346355845I/O

(2) ST RA3 can also be used as the data input for the

SPI or the data for the I2C bus.

High voltage, high current, open drain port pin.

RA4/RX1/DT1 40 43 32 51 38 I/O(1) ST RA4 can also be selected as the USART1 (SCI)

Asynchronous Receive or USA RT1 (SCI)

Synchronous Data.

Output available from USART only.

RA5/TX1/CK13942315037I/O

(1) ST RA5 can also be selected as the USART1 (SCI)

Asynchronous Transmit or USART1 (SCI)

Synchronous Clock.

Output available from USART only.

PORTB is a bi-directional I/O Port with software

configurable weak pull-ups.

RB0/CAP1 55 59 47 71 57 I/O ST RB0 can also be the Capture1 input pin.

RB1/CAP2 54 58 46 70 56 I/O ST RB1 can also be the Capture2 input pin.

RB2/PWM1 50 54 42 66 52 I/O ST RB2 can also be the PWM1 output pin.

RB3/PWM2 53 57 45 69 55 I/O ST RB3 can also be the PWM2 output pin.

RB4/TCLK12 52 56 44 68 54 I /O ST RB4 can also be the external clock input to

Timer1 and Timer2.

RB5/TCLK3 51 55 43 67 53 I/O S T RB5 can also be the external clock input to

Timer3.

RB6/SCK 44 47 36 59 46 I/O ST RB6 can also be used as the master/slave clock

for the SPI.

RB7/SDO 45 48 37 60 47 I/O ST RB7 can also be used as the data output for the

SPI.

Legend: I = Input only; O = Output only; I/O = Input/Output;

P = Power; — = Not Used; TTL = TTL input; ST = Schmitt Trigger input

Note 1: The output is only available by the peripheral operation.

2: Open drain input/output pin. Pin forced to input upon any device RESET.

 2000 Microchip Technology Inc. DS30289B-page 15

PIC17C7XX

PORTC is a bi-directional I/O Port.

RC0/AD0 2 3 58 3 72 I/O T TL This is also the least significant byte (LSB) of

the 16-bit wide system bus in Microprocessor

mode or Extended Microcontroller mode. In

multiplexed system bus configuration, these

pins are address output as well as data input or

output.

RC1/AD1 63 67 55 83 69 I/O TTL

RC2/AD2 62 66 54 82 68 I/O TTL

RC3/AD3 61 65 53 81 67 I/O TTL

RC4/AD4 60 64 52 80 66 I/O TTL

RC5/AD5 58 63 51 79 65 I/O TTL

RC6/AD6 58 62 50 78 64 I/O TTL

RC7/AD7 57 61 49 77 63 I/O TTL PORTD is a bi-directional I/O Port.

RD0/AD8 10 11 2 15 4 I/O TTL This is also the most significant byte (MSB) of

the 16-bit system bus in Microprocessor mod e

or Extended Microcontroller mode. In multi-

plexed system bus configuration, these pins are

address output as well as data input or output.

RD1/AD9 9 10 1 14 3 I/O TTL

RD2/AD10 8 9 64 9 78 I/O TTL

RD3/AD11 7 8 63 8 77 I/O TTL

RD4/AD12 6 7 62 7 76 I/O TTL

RD5/AD13 5 6 61 6 75 I/O TTL

RD6/AD14 4 5 60 5 74 I/O TTL

RD7/AD15 3 4 59 4 73 I/O TTL PORTE is a bi-directional I/O Port.

RE0/ALE 11 12 3 16 5 I/O TTL In Microprocessor mode or Extended Microcon-

troller mode, RE0 is the Address Latch Enable

(ALE) output. Address should be latched on the

falling edge of ALE output.

RE1/OE 12 13 4 17 6 I/O TTL In Microprocessor or Extended Micro controller

mode, RE1 is the Output Enable (OE) cont rol

output (active low).

RE2/WR 13 14 5 18 7 I/O TTL In Microprocessor or Extended Microcontroller

mode, RE2 is the Write Enable (WR) cont rol

output (active low).

RE3/CAP4 14 15 6 19 8 I/O ST RE3 can also be the Capture4 input pin.

PORTF is a bi-directional I/O Port.

RF0/AN4 26 28 18 36 24 I/O ST RF0 can also be analog input 4.

RF1/AN5 25 27 17 35 23 I/O ST RF1 can also be analog input 5.

RF2/AN6 24 26 16 30 18 I/O ST RF2 can also be analog input 6.

RF3/AN7 23 25 15 29 17 I/O ST RF3 can also be analog input 7.

RF4/AN8 22 24 14 28 16 I/O ST RF4 can also be analog input 8.

RF5/AN9 21 23 13 27 15 I/O ST RF5 can also be analog input 9.

RF6/AN10 20 22 12 26 14 I/O ST RF6 can also be analog input 10.

RF7/AN11 19 21 11 25 13 I/O ST RF7 can also be analog input 11.

TABLE 3-1: PINOUT DESCRIPTIONS (CONTINUED)

Name

PIC17C75X PIC17C76X

Description

DIP

No. PLCC

No. TQFP

No. PLCC

No. QFP

No. I/O/P

Type Buffer

Type

Legend: I = Input only; O = Output only; I/O = Input/Output;

P = Power; — = Not Used; TTL = TTL input; ST = Schmitt Trigger input

Note 1: The output is only available by the peripheral operation.

2: Open drain input/output pin. Pin forced to input upon any device RESET.

PIC17C7XX

DS30289B-page 16  2000 Microchip Technology Inc.

PORTG is a bi-directional I/O Port.

RG0/AN3 32 34 24 42 30 I/O ST RG0 can also be analog input 3.

RG1/AN2 31 33 23 41 29 I/O ST RG1 can also be analog input 2.

RG2/AN1/VREF- 30 32 22 40 28 I/O ST RG2 can also be analog input 1, or

the ground reference voltage.

RG3/AN0/VREF+ 29 31 21 39 27 I/O ST RG3 can also be analog input 0, or

the positive reference voltage.

RG4/CAP3 35 38 27 46 33 I/O ST RG4 can also be the Capture3 input pin.

RG5/PWM3 36 39 28 47 34 I/O ST RG5 can also be the PWM3 output pin.

RG6/RX2/DT2 38 41 30 49 36 I/O ST RG6 can also be selected as t he USART2 (SCI)

Asynchronous Receive or USA RT2 (SCI)

Synchronous Data.

RG7/TX2/CK2 37 40 29 48 35 I/O ST RG7 can also be selected as the USART 2 (SCI)

Asynchronous Transmit or USART2 (SCI)

Synchronous Clock.

PORTH is a bi-directional I/O Port. PORTH is only

available on the PIC17C76X devices.

RH0 ———10 79 I/O ST

RH1 ———11 80 I/O ST

RH2 ———12 1 I/O ST

RH3 ———13 2 I/O ST

RH4/AN12 ———31 19 I /O ST RH4 can also be analog input 12.

RH5/AN13 ———32 20 I /O ST RH5 can also be analog input 13.

RH6/AN14 ———33 21 I /O ST RH6 can also be analog input 14.

RH7/AN15 ———34 22 I /O ST RH7 can also be analog input 15.

PORTJ is a bi-directional I/O Port. PORTJ is only

available on the PIC17C76X devices.

RJ0 ———52 39 I/O ST

RJ1 ———53 40 I/O ST

RJ2 ———54 41 I/O ST

RJ3 ———55 42 I/O ST

RJ4 ———73 59 I/O ST

RJ5 ———74 60 I/O ST

RJ6 ———75 61 I/O ST

RJ7 ———76 62 I/O ST

TEST 16 17 8 21 10 I ST Test mode selection control input. Always tie to VSS

for normal operation.

VSS 17, 33,

49, 64 19, 36,

53, 68 9, 25,

41, 56 23, 44,

65, 84 11, 31,

51, 70 P Ground reference for logic and I/O pins.

VDD 1, 18,

34, 46 2, 20,

37, 49, 10, 26,

38, 57 24, 45,

61, 2 12, 32,

48, 71 P Positive supply for logic and I/O pins.

AVSS 28 30 20 38 26 P Ground reference for A/D converter.

This pin MUST be at the same potential as VSS.

AVDD 27 29 19 37 25 P Positive supply for A/D converter.

This pin MUST be at the same potential as VDD.

NC —1, 18,

35, 52 —1, 22,

43, 64 —No Connect. Leave these pins unconnected.

TABLE 3-1: PINOUT DESCRIPTIONS (CONTINUED)

Name

PIC17C75X PIC17C76X

Description

DIP

No. PLCC

No. TQFP

No. PLCC

No. QFP

No. I/O/P

Type Buffer

Type

Legend: I = Input only; O = Output only; I/O = Input/Output;

P = Power; — = Not Used; TTL = TTL input; ST = Schmitt Trigger input

Note 1: The output is only available by the peripheral operation.

2: Open drain input/output pin. Pin forced to input upon any device RESET.

 2000 Microchip Technology Inc. DS30289B-page 17

PIC17C7XX

4.0 ON-CHIP OSCILLATOR

CIRCUIT

The internal oscillator circuit is used to generate the

device clock. Four device clock periods generate an

internal instruction clock (TCY).

There ar e four modes that the osc illator can operate in.

They are selected by the device configuration bits dur-

ing device programming. These modes are:

•LF Low Frequency (FOSC ≤ 2 MHz)

•XT Standard Crystal/Resonator Frequency

(2 MHz ≤ FOSC ≤ 33 MHz)

•EC External Clock Input

(Default oscillator configuration)

•RC External Resi st or/C apacitor

(FOSC ≤ 4 MHz)

There are two timers that offer necessary delays on

power-up. One is the Os ci lla tor Star t-up Timer (OST),

intended to keep the chip in RESET until the crystal

oscillator is stable. The other is the Power-up Timer

(PWRT), which provides a fixed delay of 96 ms (nomi-

nal) on PO R and BOR . The PW R T is de signe d to kee p

the part in RESET while the power supply stabilizes.

With these two timers on-chip, most applications need

no external RESET circuitry.

SLEEP mode is designed to offer a very low current

power-down mode. The user can wake from SLEEP

through external RESET, Watchdog Timer Reset, or

through an interrupt.

Several oscillator options are made available to allow

the part to better fit the application. The RC oscillator

option saves system cost while the LF crystal option

saves power. Configuration bits are use d to selec t var-

ious options.

4.1 Oscillator Configurations

4.1.1 OSCILLATOR TYPES

The PIC17CXXX can be operated in four d ifferent oscil-

lator modes. The user can program two configuration

bits (FOSC1:FOSC0) to select one of these four

modes:

•LF Low Power Crystal

•XT Crystal/Resonator

•EC External Clock Input

•RC Resistor/Capacitor

The main difference between the LF and XT modes is

the gain of the internal inverter of the oscillator circ uit,

which allows the different frequency ranges.

For more details on the device configuration bits, see

Section 17.0.

4.1.2 CRYSTAL OSCILLATOR/CERAMIC

RESONATORS

In XT or LF modes, a cryst al or ceramic resonator is con-

nected to the OSC1/CLKIN and OSC2/CLKOUT pins to

establish osc illation (Figure 4-2). The PIC17CXXX oscil-

lator design requires the use of a parallel cut crystal. Use

of a series cut crystal may give a frequency out of the

crystal man ufacturers spec ifications.

For frequencies above 24 MHz, it is common for the

crystal to be an overtone mode crystal. Use of overtone

mode crystals require a tank circuit to attenuate the

gain at the fundamental frequency. Figure 4-3 shows

an example circuit.

4.1.3 OSCILLATOR/RESONATOR

START-UP

As the dev ice volt age increase s from Vss, the oscillator

will start its osci ll ati ons . Th e ti me require d fo r the osci l-

lator to start oscillating depends on many factors.

These include:

•Crystal/resonator frequency

•Capacitor values used (C1 and C2)

•Device VDD rise time

•System temperature

•Series resistor value (and type) if used

•Oscil lator mode s election of device (w hich sel ects

the gain of the internal oscillator inverter)

Figure 4-1 shows an example of a typical oscillator/

resonator start-up. The peak-to-peak voltage of the

oscill ato r wav efo rm ca n be qu ite lo w (less than 50% of

device VDD) when the waveform is centered at VDD/2

(refer to p ara meter #D 033 and p ara meter # D043 i n the

electrical specification section).

FIGURE 4-1: OSCILLATOR/

RESONATOR START-UP

CHARACTERISTICS

VDD

Crystal Start-up T ime

Time

PIC17C7XX

DS30289B-page 18  2000 Microchip Technology Inc.

FIGURE 4-2: CRYSTAL OR CERAMIC

RESONATOR OPERATION

(XT OR LF OSC

CONFIGURATION)

TABLE 4-1: CAPACITOR SELECTION FOR

CERAMIC RESONATORS

FIGURE 4-3: CRYSTAL OPERATION,

OVERTONE CRYSTALS

(XT OSC

CONFIGURATION)

T ABLE 4-2: CAPACITOR SELECTION FOR

CRYSTAL OSCILLATOR

Oscillator

Type Resonator

Frequency Capacitor Range

C1 = C2(1)

LF 455 kHz

2.0 MHz 15 - 68 pF

10 - 33 pF

XT 4.0 MHz

8.0 MHz

16.0 MHz

22 - 68 pF

33 - 100 pF

Higher capacitance increases the stability of the oscillator,

but also increases the start-up time. These values are for

design guidance only. Since each resonator has its own

characteristics, the user should consult the resonator manu-

facturer for appropriate values of external components.

Note 1: These values include all board capacitances on

this pin. Actual capacitor value depends on

board capacitance.

Resonators Used:

455 kHz Panasonic EFO-A455K04B ± 0.3%

2.0 MHz Murata Erie CSA2.00MG ± 0.5%

4.0 MHz Murata Erie CSA4.00MG ± 0.5%

8.0 MHz Murata Erie CSA8.00MT ± 0.5%

16.0 MHz Murata Erie CSA16.00MX ± 0.5%

Resonators used did not have built-in capacitors.

See Table 4-1 and Table 4-2 for recommended values of C1

and C2.

Note 1: A series resistor (Rs) may be required for AT strip

cut crystals.

XTAL

OSC2

(Note 1)

OSC1

RF SLEEP

PIC17CXXX

To internal

logic

Osc

Type Freq C1(2) C2(2)

LF 32 kHz

1 MHz

2 MHz

100-150 pF

10-68 pF

100-150 pF

10-68 pF

XT 2 MHz

4 MHz

8 MHz

16 MHz

24 MHz(1)

32 MHz(1)

47-100 pF

15-68 pF

15-47 pF

10-47 pF

47-100 pF

15-68 pF

15-47 pF

10-47 pF

Higher capacitance increases the stability of the oscillator,

but also increases the start-up time and the oscillator cur-

rent. These values are for design guidance only. RS may be

required in XT mode to avoid overdriving the crystals with

low drive level specification. Since each crystal has its own

characteristics, the user should consult the crystal manufac-

turer for appropriate values for external components.

Note 1: Overtone crystals are used at 24 MHz and

higher. The circuit in Figure 4-3 should be used

to select the desired harmonic frequency.

2: These values include all board capacitances on

this pin. Actual capacitor value depends on

board capacitance.

Cryst als Used:

32.768 kHz Epson C-001R32.768K-A ± 20 PPM

1.0 MHz ECS-10-13- 1 ± 50 PPM

2.0 MHz ECS-20-20- 1 ± 50 PPM

4.0 MHz ECS-40-20- 1 ± 50 PPM

8.0 MHz ECS ECS- 80-S-4

ECS-80-18-1 ± 50 PPM

16.0 MHz ECS-160-20-1 ± 50 PPM

25 MHz CTS CTS25M ± 50 PPM

32 MHz CRYSTEK HF- 2 ± 50 PPM

0.1 µF

SLEEP

OSC2

OSC1

PIC17CXXX

To filter the fundamental frequency:

L1*C2=(2πf)2

Where f = tank circuit resonant frequency. This should be

midway between the fundamental and the 3rd overtone

frequencies of the crystal.

C3 blocks DC current to ground.

 2000 Microchip Technology Inc. DS30289B-page 19

PIC17C7XX

4.1.4 EXTERNAL CLOCK OSCILLATOR

In the EC oscillator mode, the OSC1 input can be

driven by CMOS drivers. In this mode, the OSC1/

CLKIN pin is hi-imped ance and the OSC2/CLKOUT pin

is the CLKOUT output (4 TOSC).

FIGURE 4-4: EXTERNAL CLOCK INPUT

OPERATION (EC OSC

CONFIGURATION)

4.1.5 EXTERNAL CRYSTAL OSCILLATOR

CIRCUIT

Eith er a p repa ck ag ed o sc il l ato r can b e us e d, or a s i m-

ple oscillator circuit with TTL gates can be built. Pre-

packaged oscillators provide a wide operating range

and better stability. A well designed crystal oscillator

will provide good performance with TTL gates. Two

types o f crys tal oscil lator c ircuit s can be use d: one w ith

series resonance, or one with parallel resonance.

Figure 4- 5 shows implem entation of a p arallel resonant

oscillator circuit. The circuit is designed to use the fun-

dament al frequen cy of the c rystal. The 74AS04 in verter

performs the 180-degree phase shift that a parallel

oscillator requires. The 4.7 kΩ resistor provides the

negative feedback for stability. The 10 kΩ potentiome-

ter biases the 74AS04 in the linear region. This could

be used for external oscillator designs.

FIGURE 4-5: EXTERNAL PARALLEL

RESONANT CRYSTAL

OSCILLATOR CIRCUIT

Figure 4-6 shows a series resonant oscillator circuit.

This circ uit is also designe d to use the fundame ntal fre-

quency of the crystal. The inverter performs a 180-

degree phase shift in a series resonant oscillator cir-

cuit. T he 330 Ω resistors provide the negative feedback

to bias the inverters in their linear region.

FIGURE 4-6: EXTERNAL SERIES

RESONANT CRYSTAL

OSCILLATOR CIRCUIT

Clock from

ext. system OSC1

OSC2

PIC17CXXX

CLKOUT

(FOSC/4)

20 pF

+5V

20 pF

10 kΩ

4.7 kΩ

10 kΩ

74AS04

XTAL

10kΩ

74AS04 PIC17CXXX

OSC1

To Other

Devices

330 Ω

74AS04 74AS04 PIC17CXXX

OSC1

To Other

Devices

XTAL

330 Ω

74AS04

0.1 µF

PIC17C7XX

DS30289B-page 20  2000 Microchip Technology Inc.

4.1.6 RC OSCILLATOR

For timing insensitive applications, the RC device

option offers additional cost savings. RC oscillator fre-

quency is a function of the supply voltage, the resistor

(REXT) and capacitor (CEXT) values, and the operating

tempera ture. In addition to this , oscillat or frequen cy will

vary from unit to unit due to normal process parameter

variation. Furthermore, the difference in lead frame

capacitance between package types will also affect

oscillation frequency, especially for low CEXT values.

The user also needs to take into account variation due

to tolerance of external R and C components used.

Figure 4-7 shows how the R/C combination is con-

nected to the PIC17CXXX. For REXT values below

2.2 kΩ, the oscillator operation may become unstable,

or stop completely. For very high REXT values (e.g.

1MΩ), the oscillator becomes sensitive to noise,

humidity and leakage. Thus, we recommend to keep

REXT between 3 kΩ and 100 kΩ.

Although the oscillator will operate with no external

capacitor (CEXT = 0 pF), we recomme nd using valu es

above 20 pF for noise and stability reasons. With little

or no external capacitance, oscillation frequency can

vary dramatically due to changes in external capaci-

tances, such as PCB trace capacitance or package

lead frame capacitance.

See Section 21.0 for RC frequency variation from part

to pa rt due to normal pro cess varia tion. Th e variation i s

larger for larger R (since leakage current variation will

affect RC frequency more for large R) and for smaller

C (since variation of input capacitance will affect RC

frequency more).

See Section 21.0 for variation of oscillator frequency

due to VDD for given REXT/CEXT values, as well as fre-

quency variation due to operating temperature for

given R, C, and VDD values.

The oscillator frequency, divided by 4, is available on

the OSC2/CLKOUT pin and can be used for test pur-

poses or to synchronize other logic (see Figure 4-8 for

waveform).

FIGURE 4-7: RC OSCILLATOR MODE

4.1.6.1 RC Start-up

As the device voltage increases, the RC will immedi-

ately start its oscillations once the pin voltage levels

meet the input threshold specifications (parameter

#D032 a nd parame ter #D042 in the el ectrical speci fica-

tion sec tion). The tim e required for th e RC to sta rt oscil-

lating de pend s on many factors. These include:

•Resist or va lue used

•Capacitor value used

•Device VDD rise time

•System temperature

VDD

REXT

CEXT

VSS

OSC1 Internal

Clock

OSC2/CLKOUT

FOSC/4

PIC17CXXX

 2000 Microchip Technology Inc. DS30289B-page 21

PIC17C7XX

4.2 Clocking Scheme/Instruction

Cycle

The clock input (from OSC1) is internally divided by

four to generate four non-overlapping quadrature

clocks, namely Q1, Q2, Q3 and Q4. Internally, the pro-

gram counter (PC) is incremented every Q1 and the

instruction is fetched from the program memory and

latched into the instruction register in Q4. The instruc-

tion is decoded and executed during the following Q1

through Q4. The clocks and instruction execution flow

are shown in Figure 4-8.

4.3 Instruction Flow/Pipelining

An “Instruction Cycle” consists of four Q cycles (Q1,

Q2, Q3 and Q 4). The instruc tio n fe tch and ex ecu te are

pipelined such that fetch takes one instruction cycle,

while decode and execute takes another instruction

cycle. However, due to the pipelining, each instruction

effectively executes in one cycle. If an instruction

causes the program counter to change (e.g. GOTO),

then tw o cycles are req uired to com plete the ins truction

(Example 4-1).

A fetch cycle begins with the program counter incre-

menting in Q1.

In the execution cycle, the fetched instruction is latched

into the “Instruction Register (IR)” in cycle Q1. This

instruction is then de coded and executed during the Q2,

Q3 and Q4 cycles. Data memory is read during Q2

(operand read) and written during Q4 (destin ation write).

FIGURE 4-8: CLOCK/INSTRUCTION CYCLE

EXAMPLE 4-1: INSTRUCTION PIPELINE FLOW

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

OSC1

OSC2/CLKOUT

(RC mode)

PC PC+1 PC+2

Fetch INST (PC)

Execute INST (PC-1) Fetch INST (PC+1)

Execute INST (PC) Fetch INST (PC+2)

Execute INST (PC+1)

Internal

Phase

Clock

All instruc tions are s ingle cycle , except fo r any program bra nches. The se take tw o cycles s ince the fetch ed instruc -

tion is “flushed” from the pipeline, while the new instruction is being fetched and then executed.

TCY0TCY1TCY2TCY3TCY4TCY5

1. MOVLW 55h Fetch 1 Execute 1

2. MOVWF PORTB Fetch 2 Execute 2

3. CALL SUB_1 Fetch 3 Execute 3

4. BSF PORTA, BIT3 (Forced NOP) Fetch 4 Flush

5. Instruction @ address SUB_1 Fetch SUB_1 Execute SUB_1

PIC17C7XX

DS30289B-page 22  2000 Microchip Technology Inc.

NOTES:

 2000 Microchip Technology Inc. DS30289B-page 23

PIC17C7XX

5.0 RESET

The PIC17CXXX differentiates between various kinds

of RESET:

•Power-on Reset (POR)

•Brown-out Reset

•MCLR Reset

•WDT R eset

Some registers are not affected in any RESET condi-

tion, the ir stat us is unk nown on POR and un changed i n

any other RESET. Most other registers are forced to a

“RESET state”. The TO and PD bits are set or cleared

diff erently in diffe rent RESET s ituations, as indicat ed in

Table 5-3. These bits, in conjunction with the POR and

BOR bits , are us ed in s oftware to determi ne the natu re

of the RESET. See Table 5-4 for a full descrip tion of th e

RESET states of all registers.

When the device enters the “RESET state”, the Data

Direction registers (DDR) are forced set, which will

make the I/O hi-impe dance input s. The RESET sta te of

some peripheral modules may force the I/O to other

operations, such as analog inputs or the system bus.

A simplif ied block diagra m of the On-Chip Rese t Circuit

is sh own in Figu re 5-1.

FIGURE 5-1: SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT

Note: While the device is in a RESET state, the

internal phase clock is he ld in the Q1 stat e.

Any processor mode that allows external

execution will force the RE0/ALE pin as a

low output and the RE1/OE and RE2/WR

pins as high outputs.

External

Reset

MCLR

VDD

OSC1

WDT

Module

VDD Rise

Detect

OST/PWRT

On-chip

RC OSC†

WDT

Time_Out

Power_On_Reset

OST

10-bit Ripple Counter

PWRT

Chip_Reset

10-bit Ripple Counter

(Enable the PWRT timer

only during POR or BOR)

(If PWRT is invoked, or a Wake-up from

SLEEP and OSC type is XT or LF)

Reset

Enable OST

Enable PWRT

† This RC oscillator is shared with the WDT when not in a power-up sequence.

BOR

Module Brown-out

Reset

PIC17C7XX

DS30289B-page 24  2000 Microchip Technology Inc.

5.1 Power-on Reset (POR), Power-up

T imer (PWRT), Oscillat or Start-up

Timer (OST) and Brown-out Reset

(BOR)

5.1.1 POWER-ON RESET (POR)

The Power-on Reset circ uit hol ds the device in RESET

unti l VDD is above the trip point (in the range of 1.4V -

2.3V). The devices pro duce an internal RESET for both

rising and falling VDD. To take advantage of the POR,

just tie the MCLR/VPP pin directly (or thr ough a resistor)

to VDD. This will eliminate external RC components

usually needed to create Power-on Reset. A minimum

rise time for VDD is requ ired. S ee Elect rical Spec ifica-

tions for details.

Figure 5-2 and Figure 5-3 show two possible POR

circuits.

FIGURE 5-2: USING ON-CHIP POR

FIGURE 5-3: EXTERNAL POWER-ON

RESET CIRCUIT (FOR

SLOW VDD POWER-UP)

5.1.2 POWER-UP TIMER (PWRT)

The Power-up Timer provides a fixed 96 ms time-out

(nominal) on power-up. This occurs from the rising

edge of the internal POR signal if VDD and MCLR are

tied, or after the first rising edge of MCLR (detected

high). The Power-up Timer operates on an internal RC

oscillator. The chip is kept in RESET as long as the

PWRT is active. In most cases, the PWRT delay allows

VDD to rise to an acceptable level.

The pow er-up time de lay will v ary from chip to chip and

with VDD and temperature. See DC parameters for

details.

5.1.3 OSCILLATOR START-UP TIMER

(OST)

The Oscillator Start-up Timer (OST) provides a 1024

oscillator cycle (1024TOSC) delay whenever the PWRT

is invoked, or a wake-up from SLEEP event occurs in XT

or LF mode. The PWR T and OST operate in p aral lel.

The OST counts the oscillator pulses on the OSC1/

CLKIN pin. The counter only starts incrementing after

the amplitude of the signal reaches the oscillator input

thresholds. This delay allows the crystal oscillator or

resonator to stabilize before the device exits RESET.

The length of the time-out is a function of the crystal/

resonator frequency.

Figure 5-4 shows the operation of the OST circuit. In

this figu re, the oscil lator is o f such a lo w frequency th at

although enabled simultaneously, the OST does not

time-out until after the Power-up Timer time-out.

FIGURE 5-4: OSCILLATOR START-UP

TIME (LOW F RE QU EN CY)

VDD

MCLR

PIC17CXXX

VDD

Note 1: An external Power-on Reset circuit is

required only if VDD power-up time is too

slow. The diode D helps discharge the capac-

itor quickly when VDD powers down.

2: R < 40 kΩ is recommended to ensure that the

voltage drop across R does not exceed 0.2V

(max. leakage current spec. on the MCLR/

VPP pin is 5 µA). A larger voltage drop will

degrade VIH level on the M CLR/VPP pin.

3: R1 = 100Ω to 1 kΩ will limit any current flow-

ing into MCLR fro m exter nal ca pacitor C in

the event of MCLR/VPP pin breakdown due to

Electrostatic Discharge (ESD) or Electrical

Overstress (EOS).

VDD

MCLR

PIC17CXXX

VDD

MCLR

OSC2

OST TIME_OUT

PWRT TIME_OUT

INTERNAL RESET

TOSC1TOST

TPWRT

POR or BOR Trip Point

This figure shows in greater detail the timings involved

with the oscillator start-up timer. In this example, the low

frequency crystal start-up time is larger than power-up

time (TPWRT).

TOSC1 = time for the crystal oscillator to react to an oscil-

lation level detectable by the Oscillator Start-up Timer

(OST).

TOST = 1024TOSC.

 2000 Microchip Technology Inc. DS30289B-page 25

PIC17C7XX

5.1.4 TIME-OUT SEQUENCE

On power-up, the time-out sequence is as follows: First,

the internal POR signal goes high when the POR trip

point is reach ed. If MCLR is high, then both the OST and

PWRT timers start. In general, the PWRT time-out is

longer, except with low frequency crystals/resonators.

The total time-out also varies based on osci llator config-

uration. Table 5-1 shows the times that are associated

with the oscillator configuration. Figure 5-5 and Figure 5-

6 display these time-out s equences .

If the d evice v oltag e is not within electrical specif ication

at the end of a time-out, the MCLR/VPP pin must be

held low un til th e voltage is within the de vice spe ci fic a-

tion. The use of an external RC delay is sufficient for

many of these applications.

The time -out seque nce begins from the first risi ng edge

of MCLR.

Table 5-3 shows the RESET conditions for some spe-

cial registers, while Table 5-4 shows the initialization

conditions for all the registers.

TABLE 5-1: TIME-OUT IN VARIOUS SITUATIONS

TABLE 5-2: STATUS BITS AND THEIR SIGNIFICANCE

TABLE 5-3: RESET CONDITION FOR THE PROGRAM COUNTER AND THE CPUSTA REGISTER

Oscillator

Configuration POR, BOR Wake-up from

SLEEP MCLR Re s et

XT, LF Greater of: 96 ms or 1024TOSC 1024TOSC —

EC, RC Greater of: 96 ms or 1024TOSC ——

POR BOR(1) TO PD Event

0011

Power-on Reset

1110

MCLR Reset during SLEEP or interrupt wake-up from SLEEP

1101

WDT Res et dur ing normal oper at i on

1100

WDT Wake-up during SLEEP

1111

MCLR Reset during norm al operation

1011

Bro w n-out Reset

000x

Illegal, TO is set on POR

00x0

Illegal, PD is set on POR

xx11

CLRWDT instruct i on executed

Note 1: When BO DE N i s enabled, else t he BO R status bit is unknown.

Event PCH:PCL CPUSTA(4) OST Active

Power-on Reset 0000h --11 1100 Yes

Brown-out Reset 0000h --11 1110 Yes

MCLR Reset during normal operation 0000h --11 1111 No

MCLR Reset during SLEEP 0000h --11 1011 Yes(2)

WDT Reset during normal operation 0000h --11 0111 No

WDT Reset during SLEEP(3) 0000h --11 0011 Yes(2)

Interrupt Wake-up from SLEEP GLINTD is set PC + 1 --11 1011 Yes(2)

GLINTD is clear PC + 1(1) --10 1011 Yes(2)

Legend: u = unchanged, x = unknown, - = unimplemented, read as '0'

Note 1: On wake-up, this instruction is executed. The instruction at the appropriate interrupt vector is fetched and

then execu ted.

2: The OST is only active (on wake-up) when the oscillator is configured for XT or LF modes.

3: The Program Counter = 0; that is, the device branches to the RESET vector and places SFRs in WDT

Reset states. This is different from the mid-range devices.

4: When BODEN is enabled, else the BOR status bit is unknown.

PIC17C7XX

DS30289B-page 26  2000 Microchip Technology Inc.

In Figure 5-5, Figure 5-6 and Figure 5-7, the TPWRT

timer time-out is greater then the TOST timer time-out,

as would be the case in higher frequency crystals. For

lower frequency crystals (i.e., 32 kHz), TOST may be

greater.

FIGURE 5-5: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD)

FIGURE 5-6: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD)

FIGURE 5-7: SLOW RISE TIME (MCLR TIED TO VDD)

TPWRT

TOST

VDD

MCLR

INTERNAL POR

PWRT TIME-OUT

OST TIME-OUT

INTERNAL RE SET

TPWRT

TOST

VDD

MCLR

INTERNAL POR

PWRT TIME-OUT

OST TIME-OUT

INTERNAL RESET

VDD

MCLR

INTERNAL POR

PWRT TIME-OUT

OST TIME-O UT

INTERNAL RESET

0V 1V 5V

TPWRT

TOST

Minimum VDD Operating Voltage

 2000 Microchip Technology Inc. DS30289B-page 27

PIC17C7XX

TABLE 5-4: INITIALIZATION CONDITIONS FOR SPECIAL FUNCTION REGISTERS

Brown-out Reset MCLR Reset

WDT R eset Wake-up from SLEEP

through Interrupt

Unbanked

INDF0 00h N/A N/A N/A

FSR0 01h xxxx xxxx uuuu uuuu uuuu uuuu

PCL 02h 0000h 0000h PC + 1(2)

PCLATH 03h 0000 0000 uuuu uuuu uuuu uuuu

ALUSTA 04h 1111 xxxx 1111 uuuu 1111 uuuu

T0STA 05h 0000 000- 0000 000- 0000 000-

CPUSTA(3) 06h --11 11qq --11 qquu --uu qquu

INTSTA 07h 0000 0000 0000 0000 uuuu uuuu(1)

INDF1 08h N/A N/A N/A

FSR1 09h xxxx xxxx uuuu uuuu uuuu uuuu

WREG 0Ah xxxx xxxx uuuu uuuu uuuu uuuu

TMR0L 0Bh xxxx xxxx uuuu uuuu uuuu uuuu

TMR0H 0Ch xxxx xxxx uuuu uuuu uuuu uuuu

TBLPTRL 0Dh 0000 0000 0000 0000 uuuu uuuu

TBLPTRH 0Eh 0000 0000 0000 0000 uuuu uuuu

BSR 0Fh 0000 0000 0000 0000 uuuu uuuu

Bank 0

PORTA(4,6) 10h 0-xx 11xx 0-uu 11uu u-uu uuuu

DDRB 11h 1111 1111 1111 1111 uuuu uuuu

PORTB(4) 12h xxxx xxxx uuuu uuuu uuuu uuuu

RCSTA1 13h 0000 -00x 0000 -00u uuuu -uuu

RCREG1 14h xxxx xxxx uuuu uuuu uuuu uuuu

TXSTA1 15h 0000 --1x 0000 --1u uuuu --uu

TXREG1 16h xxxx xxxx uuuu uuuu uuuu uuuu

SPBRG1 17h 0000 0000 0000 0000 uuuu uuuu

Legend: u = unchanged, x = unkn own, - = unimplemented, read as ’0’, q = value depends on condition

Note 1: One or more bits in INTSTA, PIR1, PIR2 will be affected (to cause wake-up).

2: When the wake-up is due to an interrupt and the GLINTD bit is cleared, the PC is loaded with the interrupt

vector.

3: See Table 5-3 for RESET value of specific condition.

4: This is the value that will be in the port output latch.

5: When the device is configured for Microprocessor or Extended Microcontroller mode, the operation of this

port does not rely on these registers.

6: On any device RESET, these pins are configured as inputs .

PIC17C7XX

DS30289B-page 28  2000 Microchip Technology Inc.

Bank 1

DDRC(5) 10h 1111 1111 1111 1111 uuuu uuuu

PORTC(4,5) 11h xxxx xxxx uuuu uuuu uuuu uuuu

DDRD(5) 12h 1111 1111 1111 1111 uuuu uuuu

PORTD(4,5) 13h xxxx xxxx uuuu uuuu uuuu uuuu

DDRE(5) 14h ---- 1111 ---- 1111 ---- uuuu

PORTE(4,5) 15h ---- xxxx ---- uuuu ---- uuuu

PIR1 16h x000 0010 u000 0010 uuuu uuuu(1)

PIE1 17h 0000 0000 0000 0000 uuuu uuuu

Bank 2

TMR1 10h xxxx xxxx uuuu uuuu uuuu uuuu

TMR2 11h xxxx xxxx uuuu uuuu uuuu uuuu

TMR3L 12h xxxx xxxx uuuu uuuu uuuu uuuu

TMR3H 13h xxxx xxxx uuuu uuuu uuuu uuuu

PR1 14h xxxx xxxx uuuu uuuu uuuu uuuu

PR2 15h xxxx xxxx uuuu uuuu uuuu uuuu

PR3/CA1L 16h xxxx xxxx uuuu uuuu uuuu uuuu

PR3/CA1H 17h xxxx xxxx uuuu uuuu uuuu uuuu

Bank 3

PW1DCL 10h xx-- ---- uu-- ---- uu-- ----

PW2DCL 11h xx0- ---- uu0- ---- uuu- ----

PW1DCH 12h xxxx xxxx uuuu uuuu uuuu uuuu

PW2DCH 13h xxxx xxxx uuuu uuuu uuuu uuuu

CA2L 14h xxxx xxxx uuuu uuuu uuuu uuuu

CA2H 15h xxxx xxxx uuuu uuuu uuuu uuuu

TCON1 16h 0000 0000 0000 0000 uuuu uuuu

TCON2 17h 0000 0000 0000 0000 uuuu uuuu

TABLE 5-4: INITIALIZATION CONDITIONS FOR SPECIAL FUNCTION REGISTERS (CONTINUED)

Brown-out Reset MCLR Reset

WDT R eset Wake-up from SLEEP

through Interrupt

Legend: u = unchanged, x = unkn own, - = unimplemented, read as ’0’, q = value depends on condition

Note 1: One or more bits in INTSTA, PIR1, PIR2 will be affected (to cause wake-up).

2: When the wake-up is due to an interrupt and the GLINTD bit is cleared, the PC is loaded with the interrupt

vector.

3: See Table 5-3 for RESET value of specific condition.

4: This is the value that will be in the port output latch.

5: When the device is configured for Microprocessor or Extended Microcontroller mode, the operation of this

port does not rely on these registers.

6: On any device RESET, these pins are configured as inputs .

 2000 Microchip Technology Inc. DS30289B-page 29

PIC17C7XX

Bank 4

PIR2 10h 000- 0010 000- 0010 uuu- uuuu(1)

PIE2 11h 000- 0000 000- 0000 uuu- uuuu

Unimplemented 12h ---- ---- ---- ---- ---- ----

RCSTA2 13h 0000 -00x 0000 -00u uuuu -uuu

RCREG2 14h xxxx xxxx uuuu uuuu uuuu uuuu

TXSTA2 15h 0000 --1x 0000 --1u uuuu --uu

TXREG2 16h xxxx xxxx uuuu uuuu uuuu uuuu

SPBRG2 17h 0000 0000 0000 0000 uuuu uuuu

Bank 5

DDRF 10h 1111 1111 1111 1111 uuuu uuuu

PORTF(4) 11h 0000 0000 0000 0000 uuuu uuuu

DDRG 12h 1111 1111 1111 1111 uuuu uuuu

PORTG(4) 13h xxxx 0000 uuuu 0000 uuuu uuuu

ADCON0 14h 0000 -0-0 0000 -0-0 uuuu uuuu

ADCON1 15h 000- 0000 000- 0000 uuuu uuuu

ADRESL 16h xxxx xxxx uuuu uuuu uuuu uuuu

ADRESH 17h xxxx xxxx uuuu uuuu uuuu uuuu

Bank 6

SSPADD 10h 0000 0000 0000 0000 uuuu uuuu

SSPCON1 11h 0000 0000 0000 0000 uuuu uuuu

SSPCON2 12h 0000 0000 0000 0000 uuuu uuuu

SSPSTAT 13h 0000 0000 0000 0000 uuuu uuuu

SSPBUF 14h xxxx xxxx uuuu uuuu uuuu uuuu

Unimplemented 15h ---- ---- ---- ---- ---- ----

Unimplemented 16h ---- ---- ---- ---- ---- ----

Unimplemented 17h ---- ---- ---- ---- ---- ----

TABLE 5-4: INITIALIZATION CONDITIONS FOR SPECIAL FUNCTION REGISTERS (CONTINUED)

Brown-out Reset MCLR Reset

WDT R eset Wake-up from SLEEP

through Interrupt

Legend: u = unchanged, x = unkn own, - = unimplemented, read as ’0’, q = value depends on condition

Note 1: One or more bits in INTSTA, PIR1, PIR2 will be affected (to cause wake-up).

2: When the wake-up is due to an interrupt and the GLINTD bit is cleared, the PC is loaded with the interrupt

vector.

3: See Table 5-3 for RESET value of specific condition.

4: This is the value that will be in the port output latch.

5: When the device is configured for Microprocessor or Extended Microcontroller mode, the operation of this

port does not rely on these registers.

6: On any device RESET, these pins are configured as inputs .

PIC17C7XX

DS30289B-page 30  2000 Microchip Technology Inc.

Bank 7

PW3DCL 10h xx0- ---- uu0- ---- uuu- ----

PW3DCH 11h xxxx xxxx uuuu uuuu uuuu uuuu

CA3L 12h xxxx xxxx uuuu uuuu uuuu uuuu

CA3H 13h xxxx xxxx uuuu uuuu uuuu uuuu

CA4L 14h xxxx xxxx uuuu uuuu uuuu uuuu

CA4H 15h xxxx xxxx uuuu uuuu uuuu uuuu

TCON3 16h -000 0000 -000 0000 -uuu uuuu

Unimplemented 17h ---- ---- ---- ---- ---- ----

Bank 8

DDRH 10h 1111 1111 1111 1111 uuuu uuuu

PORTH(4) 11h xxxx xxxx uuuu uuuu uuuu uuuu

DDRJ 12h 1111 1111 1111 1111 uuuu uuuu

PORTJ(4) 13h xxxx xxxx uuuu uuuu uuuu uuuu

Unbanked

PRODL 18h xxxx xxxx uuuu uuuu uuuu uuuu

PRODH 19h xxxx xxxx uuuu uuuu uuuu uuuu

TABLE 5-4: INITIALIZATION CONDITIONS FOR SPECIAL FUNCTION REGISTERS (CONTINUED)

Brown-out Reset MCLR Reset

WDT R eset Wake-up from SLEEP

through Interrupt

Legend: u = unchanged, x = unkn own, - = unimplemented, read as ’0’, q = value depends on condition

Note 1: One or more bits in INTSTA, PIR1, PIR2 will be affected (to cause wake-up).

2: When the wake-up is due to an interrupt and the GLINTD bit is cleared, the PC is loaded with the interrupt

vector.

3: See Table 5-3 for RESET value of specific condition.

4: This is the value that will be in the port output latch.

5: When the device is configured for Microprocessor or Extended Microcontroller mode, the operation of this

port does not rely on these registers.

6: On any device RESET, these pins are configured as inputs .

 2000 Microchip Technology Inc. DS30289B-page 31

PIC17C7XX

5.1.5 BROWN-OUT RESET (BOR)

PIC17C7XX devices have on-chip Brown-out Reset

circuitry. This circuitry places the device into a RESET

when the d evice vol tag e f alls below a trip po int (BV DD).

This ensures that the device does not continue pro-

gram ex ecution outs ide the v alid operat ion ra nge of th e

dev ic e. B row n -o ut Re se ts are ty pi ca l ly us ed in A C li ne

applications, or large battery applications, where large

loads may be switched in (such as automotive).

The BODEN configuration bit can disable (if clear/

programmed), or enable (if set) the Brown-out Reset

circuitry. If VDD falls below BVDD (typically 4.0 V,

paramt er #D0 05 in elect rical s peci ficati on sec tion ), fo r

greater than parameter #35, the Brown-out situation

will res et the chip. A RESET is n ot guarant eed to occ ur

if VDD falls bel ow BVDD for less tha n paramter #3 5. The

chip will remain in Brown-out Reset until VDD rises

above BVDD. The Pow er-up Timer and Osc illator Sta rt-

up Timer will t hen be i nvoked. Thi s will k eep the chip i n

RESET the greater of 96 ms and 1024 TOSC. If VDD

drops below BVDD while the Power-up Timer/Oscillator

Start-up Timer is running, the chip will go back into a

Brown-ou t Reset. The Power-up Timer/Oscil lator S ta rt-

up Timer will be initialized. Once VDD rises above

BVDD, the Power-up Timer/Oscillator Start-up Timer

will start their time delays. Figure 5-10 shows typical

Brown-out situations.

In some applications, the Brown-out Reset trip point of

the de vice may n ot be at the desir ed level . Figure 5-8

and Figure 5-9 are two examples of external circuitry

that may be implemented. Each needs to be evaluated

to determine if they match the requirements of the

application.

FIGURE 5-8: EXTERNAL BROWN-OUT

PROTECTION CIRCUIT 1

FIGURE 5-9: EXTERNAL BROWN-OUT

PROTECTION CIRCUIT 2

FIGURE 5-10: BROWN-OUT SITUATIONS

Note: Before using the on-chip Brown-out for a

voltage supervisory function, please

review the electrical specifications to

ensure that they meet your requirements .

VDD

33k

10kΩ

40 k Ω

VDD

MCLR

PIC17CXXX

This circuit will activate RESET when VDD goes below

(Vz + 0.7V) where Vz = Zener voltage.

This brown-out circuit is less expensive, albeit less

accurate. Transistor Q1 turns off when VDD is below a

certain level such that:

VDD •R1

R1 + R2 = 0.7V

R2 40 kΩ

VDD

MCLR

PIC17CXXX

VDD

Greater of 96 ms

BVDD Max.

BVDD Min.

VDD

Internal

RESET

BVDD Max.

BVDD Min.

VDD

Internal

RESET < 96 ms

BVDD Max.

BVDD Min.

VDD

Internal

RESET

and 1024 TOSC

Greater of 96 ms

and 1024 TOSC

Greater of 96 ms

and 1024 TOSC

PIC17C7XX

DS30289B-page 32  2000 Microchip Technology Inc.

NOTES:

 2000 Microchip Technology Inc. DS30289B-page 33

PIC17C7XX

6.0 INTERRUPTS

PIC17C7XX dev ic es have 18 source s of inte rrupt:

•External int errup t from the RA0/INT pin

•Change on RB7:RB0 pins

•TMR0 Overfl ow

•TMR1 Overfl ow

•TMR2 Overfl ow

•TMR3 Overfl ow

•USART1 Transmit buffer empty

•USART1 Receive buffer f ull

•USART2 Transmit buffer empty

•USART2 Receive buffer f ull

•SSP Interrupt

•SSP I2C bus collision interrupt

•A/D con ve rsi on com pl ete

•Capture1

•Capture2

•Capture3

•Capture4

•T0CKI edge occurred

There ar e six registe rs used in the contro l and sta tus of

interrupts. These are:

•CPUSTA

•INTSTA

•PIE1

•PIR1

•PIE2

•PIR2

The CPUSTA register contains the GLINTD bit. This is

the Global Interrupt Disable bit. When this bit is set, all

interrupts are disabled. This bit is part of the controller

core functionality and is described in the Section 6.4.

When an interrupt is responded to, the GLINTD bit is

automatically set to disable any further interrupts, the

return address is pushed onto the stack and the PC is

loaded w ith the interrupt ve ctor address. The re are four

interrupt vectors. Each vector address is for a specific

interrupt source (except the pe ripheral interrupts, which

all vector to the same address). These sources are:

•External interrupt from the RA0/INT pin

•TMR0 Overflow

•T0CKI edge occurred

•Any peripheral interrupt

When prog ram ex ecu tio n v ec tors to o ne o f the se inter-

rupt vector addresses (except for the peripheral inter-

rupts), the interrupt flag bit is automatically cleared.

Vectoring to the peripheral interrupt vector address

does no t automati cally cl ear the so urce of the interrupt.

In the peripheral Interrupt Service Routine, the

source(s) of the interrupt can be determined by testing

the i nterr upt flag bits. T he inte rrupt flag bi t(s) mu st be

cleared in software before re-enabling interrupts to

avoid infinite interrupt requests.

When an interrup t conditi on is met, that indivi dual int er-

rupt flag bit will be set, regardless of the status of its

corresponding mask bit or the GLINTD bit.

For external interrupt events, there will be an interrupt

latency. For two-cy cle instructi ons, the latency cou ld be

one instruction cycle longer.

The “return from interrupt” instruction, RETFIE, can be

used to mark the end of the Interrupt Service Routine.

When this instruction is executed, the stack is “POPed”

and the GLINTD bit is c leared (to re-enable interrupt s).

FIGURE 6-1: INTERRUP T LOGIC

RBIF

RBIETMR3IF

TMR3IE TMR2IF

TMR2IE

TMR1IF

TMR1IE CA2IF

CA2IE

CA1IF

CA1IE TX1IF

TX1IE RC1IF

RC1IE

T0IF

T0IE

INTF

INTE

T0CKIF

T0CKIE

GLINTD (CPUSTA<4>)

PEIE

Wa ke-up (If in SLEEP mode)

or terminate long write

Interrupt to CPU

PEIF

SSPIF

SSPIE BCLIF

BCLIE ADIF

ADIE

CA4IF

CA4IE CA3IF

CA3IE

TX2IF

TX2IE RC2IF

RC2IE

PIR1/PIE1

PIR2/PIE2

INTSTA

PIC17C7XX

DS30289B-page 34  2000 Microchip Technology Inc.

6.1 Interrupt Status Register (INTSTA)

The Inter rupt S tatus /Control regis ter (INTSTA) cont ains

the flag and enable bits for non-peripheral interrupts.

The PEIF bit is a read only , bit wise OR of all the periph-

eral flag bits in the PIR registers (Figure 6-4 and

Figure 6-5).

Care should be taken w hen clea ring any of the INTS TA

(GLINTD is clear). If any of the INTSTA flag bits (T0IF,

INTF, T0CKIF, or PEIF) are set in the same instruction

cycle as the correspo nding interrupt enable bit is cleared,

the de vi ce wi ll v ecto r t o t he RESET a dd res s (0 x00).

Prior to disabling any of the INTSTA enable bits, the

GLINTD bit should be set (disabled).

Note: All interrupt flag bits get set by their speci-

fied condition, even if the corresponding

interrupt enable bit is clear (interrupt dis-

abled), or the GLINTD bit is set (all inter-

rupts disabled).

R-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

PEIF T0CKIF T0IF INTF PEIE T0CKIE T0IE INTE

bit 7 bit 0

bit 7 PEIF: Peripheral Interrupt Flag bi t

This bit is the OR o f all pe ripheral interru pt flag b its AND’ed with t heir cor res pondin g enabl e bit s.

The interrupt logic forces program execution to address (20h) when a peripheral interrupt is

pending.

1 = A peripheral interrupt is pending

0 = No peripheral interrupt is pending

bit 6 T0CKIF: External Interrupt on T0CKI Pin Flag bit

This bit is cleared by hardware, when the interrupt logic forces program execution to address (18h).

1 = The software specified edge occurred on the RA1/T0CKI pin

0 = The software specified edge did not occur on the RA1/T0CKI pin

bit 5 T0IF: TMR0 Overflow Interrupt Flag bit

This bit is cleared by hardware, when the interrupt logic forces program execution to address (10h).

1 = TMR0 overflowed

0 = TMR0 did not overflow

bit 4 INTF: External Interrupt on INT Pin Flag bit

This bit is cleared by hardware, when the interrupt logic forces program execution to address (08h).

1 = The software specified edge occurred on the RA0/INT pin

0 = The software specified edge did not occur on the RA0/INT pin

bit 3 PEIE: Peripheral Interrupt Enable bit

This bit acts as a global enable bit for the peripheral interrupts that have their corresponding

enable bits set.

1 = Enable peripheral interrupts

0 = Disable peripheral interrupts

bit 2 T0CKIE: External Interrupt on T0CKI Pin Enable bit

1 = Enable software specified edge interrupt on the RA1/T0CKI pin

0 = Disable interrupt on the RA1/T0CKI pin

bit 1 T0IE: TMR0 Overflow Interrupt Enable bit

1 = Enable TMR0 overflow interrupt

0 = Disable TMR0 overflow interrupt

bit 0 INTE: External Interrupt on RA0/INT Pin Enable bit

1 = Enable software specified edge interrupt on the RA0/INT pin

0 = Disable software specified edge interrupt on the RA0/INT pin

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

- n = Value at POR Reset ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown

 2000 Microchip Technology Inc. DS30289B-page 35

PIC17C7XX

6.2 Peripheral Interrupt Enable

Register1 (PI E1 ) and Register2

(PIE2)

These registers contains the individual enable bits for

the peri phera l interru pts.

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

RBIE TMR3IE TMR2IE TMR1IE CA2IE CA1IE TX1IE RC1IE

bit 7 bit 0

bit 7 RBIE: PORTB Interrupt-on-Change Enable bit

1 = Enable PORTB interrupt-on-change

0 = Disable PORTB interrupt-on-change

bit 6 TMR3IE: TMR3 Interrupt Enable bit

1 = Enable TMR3 interrupt

0 = Disable TMR3 interrupt

bit 5 TMR2IE: TMR2 Interrupt Enable bit

1 = Enable TMR2 interrupt

0 = Disable TMR2 interrupt

bit 4 TMR1IE: TMR1 Interrupt Enable bit

1 = Enable TMR1 interrupt

0 = Disable TMR1 interrupt

bit 3 CA2IE: Capture2 Interrup t Enable bit

1 = Enable Capture2 interrupt

0 = Disable Capture2 interrupt

bit 2 CA1IE: Capture1 Interrup t Enable bit

1 = Enable Capture1 interrupt

0 = Disable Capture1 interrupt

bit 1 TX1IE: USART1 Transmit Interrupt Enable bit

1 = Enable USART1 Transmit buffer empty int e rrupt

0 = Disable USART1 Transmit buffer empty interrupt

bit 0 RC1IE: USART1 Rece iv e Interru pt Enab le bit

1 = Enable USART1 Receive buffer full interrupt

0 = Disable USART1 Receive buffer full interrupt

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

- n = Value at POR Reset ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown

PIC17C7XX

DS30289B-page 36  2000 Microchip Technology Inc.

R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0

SSPIE BCLIE ADIE —CA4IE CA3IE TX2IE RC2IE

bit 7 bit 0

bit 7 SSPIE: Synchronous Serial Port Interrupt Enable bit

1 = Enable SSP interrupt

0 = Disable SSP interrupt

bit 6 BCLIE: Bus Collision Interrupt Enable bit

1 = Enable bus collision interrupt

0 = Disable bus collision interrupt

bit 5 ADIE: A/D Module Interrupt Enable bit

1 = Enable A/D module interrupt

0 = Disable A/D module interrupt

bit 4 Unimplemented: Read as ‘0’

bit 3 CA4IE: Capture4 Interrup t Enable bit

1 = Enable Capture4 interrupt

0 = Disabl e Capture4 interrup t

bit 2 CA3IE: Capture3 Interrup t Enable bit

1 = Enable Capture3 interrupt

0 = Disabl e Capture3 interrup t

bit 1 TX2IE: USART2 Transmit Interrupt Enable bit

1 = Enable USART2 Transmit buffer empty int e rrupt

0 = Disable USART2 Transmit buffer empty interrupt

bit 0 RC2IE: USART2 Rece iv e Interru pt Enab le bit

1 = Enable USART2 Receive buffer full interrupt

0 = Disable USART2 Receive buffer full interrupt

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

- n = Value at POR Reset ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown

 2000 Microchip Technology Inc. DS30289B-page 37

PIC17C7XX

6.3 Peripheral Interrupt Request

Register1 (PI R1 ) and Register2

(PIR2)

These registers contains the individual flag bits for the

peripheral interrupts.

Note: These bits will be set by the specified condi-

tion, even if the corresponding interrupt

enable bit is cleared (interrupt disabled), or

the GLINTD bit is set (all interrupts disabled).

Before enabling an interrupt, the user may

wish to clear the interrupt flag to ensure that

the program does not immediately branch to

the peripheral Interrupt Service Routine.

R/W-x R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-1 R-0

RBIF TMR3IF TMR2IF TMR1IF CA2IF CA1IF TX1IF RC1IF

bit 7 bit 0

bit 7 RBIF: PORTB Interrupt-on-C hange Flag bit

1 = One of the PORTB inputs changed (software must end the mismatch condition)

0 = None of the PORTB inputs have changed

bit 6 TMR3IF: TMR3 Interrupt Flag bit

If Capture1 is enabled (CA1/PR3 = 1):

1 = TMR3 overflowed

0 = TMR3 did not overflow

If Capture1 is disabled (CA1/PR3 = 0):

1 = TMR3 value has rolled over to 0000h from equalling the period register (PR3H:PR3L) value

0 = TMR3 value has not rolled over to 0000h from equalling the period register (PR3H:PR3L)

value

bit 5 TMR2IF: TMR2 Interrupt Flag bit

1 = TMR2 value has rolled over to 0000h from equalling the period register (PR2) value

0 = TMR2 value has not rolled over to 0000h from equalling the period register (PR2) value

bit 4 TMR1IF: TMR1 Interrupt Flag bit

If TMR1 is in 8-bit mode (T16 = 0):

1 = TMR1 value has rolled over to 0000h from equalling the period register (PR1) value

0 = TMR1 value has not rolled over to 0000h from equalling the period register (PR1) value

If Timer1 is in 16-bit mode (T16 = 1):

1 = TMR2:TMR1 value has rolled over to 0000h from equalling the period register (PR2:PR1)

value

0 = TMR2:T MR1 value has not ro lled over to 00 00h from equal ling the period register (PR2:PR1 )

value

bit 3 CA2IF: Capture2 Interrupt Flag bit

1 = Capture event occurred on RB1/CAP2 pin

0 = Capture event did not occur on RB1/CAP2 pin

bit 2 CA1IF: Capture1 Interrupt Flag bit

1 = Capture event occurred on RB0/CAP1 pin

0 = Capture event did not occur on RB0/CAP1 pin

bit 1 TX1IF: USART1 Transmit Interrupt Flag bit (state controlled by hardware)

1 = US ART1 Transmit buffer is empty

0 = USART1 Transmit buffer is full

bit 0 RC1IF: USART1 Receive In terrupt Flag bit (state controlled by hardware)

1 = USART1 Receive buffer is full

0 = US ART1 Receive buffer is empty

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

- n = Value at POR Reset ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown

PIC17C7XX

DS30289B-page 38  2000 Microchip Technology Inc.

R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R-1 R-0

SSPIF BCLIF ADIF —CA4IF CA3IF TX2IF RC2IF

bit 7 bit 0

bit 7 SSPIF: Synchronous Serial Port (SSP) Interrupt Flag bit

1 = The SSP interrupt condition has occurred and must be cleared in software before returning

from the Interrupt Service Routine. The conditions that will set this bit are:

SPI:

A transmission/reception has taken place.

I2 C Slave/Master:

A transmission/reception has taken place.

I2 C Master:

The initiated START condition was completed by the SSP module.

The initiated STOP c ondition was completed by the SSP module.

The initiated Restart condition was completed by the SSP module.

The initiated Acknowledge condition was completed by the SSP module.

A START condition occurred while the SSP module was idle (Multi-master system).

A STOP condition occurred while the SSP module was idle (Multi-master system).

0 = An SSP interrupt condition has NOT occurred

bit 6 BCLIF: Bus Collision Interrupt Flag bit

1 = A bus collision has occurred in the SSP, when configured for I2C Master mode

0 = No bus collision has occurred

bit 5 ADIF: A/D Module Interrupt Flag bit

1 = An A/D conversion is complete

0 = An A/D conversion is not complete

bit 4 Unimplemented: Read as ’0’

bit 3 CA4IF: Capture4 Interrupt Flag bit

1 = Capture event occurred on RE3/CAP4 pin

0 = Capture event did not occur on RE3/CAP4 pin

bit 2 CA3IF: Capture3 Interrupt Flag bit

1 = Capture event occurred on RG4/CAP3 pin

0 = Capture event did not occur on RG4/CAP3 pin

bit 1 TX2IF:USART2 Transmit Interrupt Flag bit (state controlled by hardware)

1 = USART2 Transmit buffer is empty

0 = USART2 Transmit buffer is full

bit 0 RC2IF: USART2 Receive In terrupt Flag bit (state controlled by hardware)

1 = USART2 Receive buffer is full

0 = USART2 Receive buffe r is empty

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

- n = Value at POR Reset ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown

 2000 Microchip Technology Inc. DS30289B-page 39

PIC17C7XX

6.4 Interrupt Operation

Global Interrupt Disable bit, GLINTD (CPUSTA<4>),

enables all unmasked interrupts (if clear), or disables

all interrupts (if set). Individual interrupts can be dis-

abled through their corresponding enable bits in the

INTSTA register. Peripheral interrupts need either the

global peripheral enable PEIE bit disabled, or the spe-

cific peripheral enable bit disabled. Disabling the

peripherals via the global peripheral enable bit, dis-

ables all peripheral interrupts. GLINTD is set on

RESET (interrupts disabled).

The RETFIE instruction clears the GLINTD bit while

forcing the Program Counter (PC) to the value loaded

at the Top-of-Stack.

When an interrupt is responded to, the GLINTD bit is

automatically set to disable any further interrupt, the

return address is pushed onto the stack and the PC is

loaded with the inte rrupt vector . T here are four interrupt

vectors which help reduce interrupt latency.

The peripheral interrupt vector has multiple interrupt

sources. Once in the peripheral Interrupt Service Rou-

tine, the source(s) of the interrupt ca n be determined by

polling the interrupt flag bits. The peripheral interrupt

flag bit(s) must be cleared in software before re-

enabling interrupts to avoid continuous interrupts.

The PIC17C7XX devices have four interrupt vectors.

These v ec tors and the ir ha rdware pri ority are sh ow n i n

Table 6-1. If two enabled interrupts occur “at the same

time”, the interrupt of the highest priority will be ser-

viced first. This means that the vector address of that

interrupt will be loaded into the program counter (PC).

TABLE 6-1: INTERRUPT VECTORS/

PRIORITIES

6.5 RA0/INT Interrupt

The external interrupt on the RA0/INT pin is edge trig-

gered. Either the rising edge if the INTEDG bit

(T0STA<7>) is set, or the fa lling edge if the INTEDG b it

is clear. When a valid edge appears on the RA0/INT

pin, the IN TF b it (INTSTA<4>) is set. Thi s i nte rrupt ca n

be disabled by clearing the INTE control bit

(INTSTA<0>). The INT interrupt can wake the proces-

sor from SLEEP. See Section 17.4 for details on

SLEEP operation.

6.6 T0CKI Interrupt

The external interrupt on the RA1/T0CKI pin is edge

triggered. Either the rising edge if the T0SE bit

(T0STA<6>) is set, or the fall ing edge if the T0SE bit i s

clear. When a valid edge appears on the RA1/T0CKI

pin, the T0CKIF bit (INTSTA<6>) is set. This interrupt

can be disabled by clearing the T0CKIE control bit

(INTSTA<2>). The T0CKI interrupt can wake up the

process or from SLEEP. See Section 17.4 fo r det ails on

SLEEP operation.

6.7 Peripheral Interrupt

The peri pheral int errupt flag indicates that at least one

of the periphe ral interrupts occurred (P EIF is set). The

PEIF bit is a read only bit and is a bit wise OR of all the

flag bits in the PIR registers AND’d with the correspond-

ing enable bits in the PIE registers. Some of the periph-

eral interrupts can wake the processor from SLEEP.

See Section 17.4 for details on SLEEP operat ion.

6.8 Context Saving During Interrupts

During an interrupt, only th e returned PC value is sa ved

on the stack. Typically, users may wish to save key reg-

isters during an interrupt; e.g. WREG, ALUSTA and the

BSR registers. This requires implement ation in software.

Example 6-2 shows the saving and restoring of infor-

mation for an Interrupt Service Routine. This is for a

simple interrupt scheme, where only one interrupt may

occur at a time (no interrupt nesting). The SFRs are

stored in the non-banked GPR area.

Example 6-2 shows the saving and restoring of infor-

mation for a more complex Interrupt Service Routine.

This is useful where nesting of interrupts is required. A

maxim um of 6 levels can be don e by this ex ample. Th e

BSR is stored in the non-banked GPR area, while the

other registers would be stored in a particular bank.

Therefore, 6 saves may be don e with this routine (si nce

there are 6 non-banke d GPR registers). These routines

require a d edica ted ind irect ad dress ing reg ister, FSR 0,

to be selected for this.

The PUSH and POP code segments could either be in

each I nterrupt Servi ce Routin e, or could be subrouti nes

that were called. Depending on the application, other

registers may also need to be saved.

Address Vector Priority

0008h External Interrupt on RA0/

INT pin (INTF) 1 (Highest)

0010h TMR0 Overfl ow Interru pt

(T0IF) 2

0018h External Interrupt on T0CKI

(T0CKIF) 3

0020h Periphera ls (PEIF) 4 (Lowest)

Note 1: Indiv idual inter rupt flag bit s are set, reg ard-

less of the status of their corresponding

mask bit or the GLINTD bit.

2: Before dis abling an y of the INT STA enable

bits, the GLINTD bit should be set

(disabled).

PIC17C7XX

DS30289B-page 40  2000 Microchip Technology Inc.

FIGURE 6-2: INT PIN/T0CKI PIN INTERRUPT TIMING

Q2Q1 Q3 Q4 Q2Q1 Q3 Q4 Q2Q1 Q3 Q4 Q2Q1 Q3 Q4 Q2Q1 Q3 Q4 Q2Q1 Q3 Q4 Q2Q1 Q3 Q4

OSC1

OSC2

RA0/INT or

RA1/T0CKI

INTF or

T0CKIF

GLINTD

Instruction

Executed

System Bus

Instruction

Fetched

PC PC + 1 Addr (Vect or)

PC Inst (PC) Inst (PC+1)

Inst (PC) Dummy Dummy

YY YY + 1

RETFIE

Inst (PC+1) Inst (Vector)

Addr

Addr Addr Addr Inst (YY + 1)

Dummy

PC + 1

 2000 Microchip Technology Inc. DS30289B-page 41

PIC17C7XX

EXAMPLE 6-1: SAVING STATUS AND WREG IN RAM (SIMPLE)

; The addresses that are used to store the CPUSTA and WREG values must be in the data memory

; address range of 1Ah - 1Fh. Up to 6 locations can be saved and restored using the MOVFP

; instruction. This instruction neither affects the status bits, nor corrupts the WREG register.

;

UNBANK1 EQU 0x01A ; Address for 1st location to save

UNBANK2 EQU 0x01B ; Address for 2nd location to save

UNBANK3 EQU 0x01C ; Address for 3rd location to save

UNBANK4 EQU 0x01D ; Address for 4th location to save

UNBANK5 EQU 0x01E ; Address for 5th location to save

; (Label Not used in program)

UNBANK6 EQU 0x01F ; Address for 6th location to save

; (Label Not used in program)

;

: ; At Interrupt Vector Address

PUSH MOVFP ALUSTA, UNBANK1 ; Push ALUSTA value

MOVFP BSR, UNBANK2 ; Push BSR value

MOVFP WREG, UNBANK3 ; Push WREG value

MOVFP PCLATH, UNBANK4 ; Push PCLATH value

;

: ; Interrupt Service Routine (ISR) code

;

POP MOVFP UNBANK4, PCLATH ; Restore PCLATH value

MOVFP UNBANK3, WREG ; Restore WREG value

MOVFP UNBANK2, BSR ; Restore BSR value

MOVFP UNBANK1, ALUSTA ; Restore ALUSTA value

;

RETFIE ; Return from interrupt (enable interrupts)

PIC17C7XX

DS30289B-page 42  2000 Microchip Technology Inc.

EXAMPLE 6-2: SAVING STATUS AND WREG IN RAM (NESTED)

; The addresses that are used to store the CPUSTA and WREG values must be in the data memory

; address range of 1Ah - 1Fh. Up to 6 locations can be saved and restored using the MOVFP

; instruction. This instruction neither affects the status bits, nor corrupts the WREG register.

; This routine uses the FRS0, so it controls the FS1 and FS0 bits in the ALUSTA register.

;

Nobank_FSR EQU 0x40

Bank_FSR EQU 0x41

ALU_Temp EQU 0x42

WREG_TEMP EQU 0x43

BSR_S1 EQU 0x01A ; 1st location to save BSR

BSR_S2 EQU 0x01B ; 2nd location to save BSR (Label Not used in program)

BSR_S3 EQU 0x01C ; 3rd location to save BSR (Label Not used in program)

BSR_S4 EQU 0x01D ; 4th location to save BSR (Label Not used in program)

BSR_S5 EQU 0x01E ; 5th location to save BSR (Label Not used in program)

BSR_S6 EQU 0x01F ; 6th location to save BSR (Label Not used in program)

;

INITIALIZATION ;

CALL CLEAR_RAM ; Must Clear all Data RAM

;

INIT_POINTERS ; Must Initialize the pointers for POP and PUSH

CLRF BSR, F ; Set All banks to 0

CLRF ALUSTA, F ; FSR0 post increment

BSF ALUSTA, FS1

CLRF WREG, F ; Clear WREG

MOVLW BSR_S1 ; Load FSR0 with 1st address to save BSR

MOVWF FSR0

MOVWF Nobank_FSR

MOVLW 0x20

MOVWF Bank_FSR

: ; Your code

: ; At Interrupt Vector Address

PUSH BSF ALUSTA, FS0 ; FSR0 has auto-increment, does not affect status bits

BCF ALUSTA, FS1 ; does not affect status bits

MOVFP BSR, INDF0 ; No Status bits are affected

CLRF BSR, F ; Peripheral and Data RAM Bank 0 No Status bits are affected

MOVPF ALUSTA, ALU_Temp ;

MOVPF FSR0, Nobank_FSR ; Save the FSR for BSR values

MOVPF WREG, WREG_TEMP ;

MOVFP Bank_FSR, FSR0 ; Restore FSR value for other values

MOVFP ALU_Temp, INDF0 ; Push ALUSTA value

MOVFP WREG_TEMP, INDF0 ; Push WREG value

MOVFP PCLATH, INDF0 ; Push PCLATH value

MOVPF FSR0, Bank_FSR ; Restore FSR value for other values

MOVFP Nobank_FSR, FSR0 ;

;

: ; Interrupt Service Routine (ISR) code

;

POP CLRF ALUSTA, F ; FSR0 has auto-decrement, does not affect status bits

MOVFP Bank_FSR, FSR0 ; Restore FSR value for other values

DECF FSR0, F ;

MOVFP INDF0, PCLATH ; Pop PCLATH value

MOVFP INDF0, WREG ; Pop WREG value

BSF ALUSTA, FS1 ; FSR0 does not change

MOVPF INDF0, ALU_Temp ; Pop ALUSTA value

MOVPF FSR0, Bank_FSR ; Restore FSR value for other values

DECF Nobank_FSR, F ;

MOVFP Nobank_FSR, FSR0 ; Save the FSR for BSR values

MOVFP ALU_Temp, ALUSTA ;

MOVFP INDF0, BSR ; No Status bits are affected

;

RETFIE ; Return from interrupt (enable interrupts)

 2000 Microchip Technology Inc. DS30289B-page 43

PIC17C7XX

7.0 MEMORY ORGANIZATION

There are two memory blocks in the PIC17C7XX; pro-

gram memory and data memory. Each block has its

own bus , so that acces s to each block ca n occur during

the same oscillator cycle.

The data memory can further be broken down into

General Purpose RAM and the Special Function Reg-

isters (SFRs). The operation of the SFRs that control

the “core” are descr ibed he re. Th e SFRs us ed to con -

trol the peripheral modules are described in the section

discus s ing each ind iv idu al peri phe ral modul e.

7.1 Program Memory Organization

PIC17C7XX devices have a 16-bit program counter

capable of addressing a 64K x 16 program memory

spa ce. The RESET vector is at 0000h and the interru pt

vectors are at 0008h, 0010h, 0018h, and 0020h

(Figure 7-1).

7.1.1 PROGRAM MEMORY OPERATION

The PIC17C7XX can operate in one of four possible

program memory configurations. The configuration is

select ed by configu ration bit s. The poss ible modes a re:

•Microprocessor

•Microcontroller

•Extended Microcontroller

•Protected Microcontroller

The Microcontroller and Protected Microcontroller

modes only allow internal execution. Any access

beyond the program m emory reads unk nown dat a. The

Protected Microcontroller mode also enables the code

prote ction feature.

The Extended Microcontroller mode accesses both

the internal program memory, as well as external pro-

gram memory. Execution automatically switches

between internal and external memory. The 16-bits of

address al low a pro gram m emory rang e o f 64 K-w ords.

The Microprocessor mod e only acce sses the ext ernal

program memory. The on-chip program memory is

ignored. The 16-bits of address allow a program mem-

ory range of 64K-words. Microprocessor mode is the

default mode of an unp rogrammed device.

The di ffere nt modes all ow diffe rent ac cess to the c on-

figuration bits, test memory and boot ROM. Table 7-1

lists which modes can access which areas in memory.

Test Memory and Boot Memory are not required for

normal operation of the device. Care should be taken

to ensure that no unintended branches occur to these

areas.

FIGURE 7-1: PROGRAM MEMORY MAP

AND STACK

PC<15:0>

Stack Level 1

•

Stack Level 16

RESET Vector

INT Pin Interrupt Vec tor

Timer0 Interrupt Vec tor

T0CKI Pin Interrupt Vector

Peripheral Interrupt Vector

FOSC0

FOSC1

WDTPS0

WDTPS1

PM0

Reserved

PM1

Reserved

•

Configuration Memory

Space User Mem o ry

Space(1)

CALL, RETURN

RETFIE, RETLW

0000h

0008h

0010h

0020h

0021h

0018h

FDFFh

FE00h

FE01h

FE02h

FE03h

FE04h

FE05h

FE06h

FE07h

FE0Fh

Test EPROM

Boot RO M

FE10h

FF5Fh

FF60h

FFFFh

1FFFh

3FFFh

(PIC17C752

(PIC17C756A

Reserved

PM2

FE08h

Note 1: User memory space may be internal, external,

or both. The memory configuration depends

on the processor mode.

FE0Eh

BODEN FE0Dh

PIC17C762)

PIC17C766)

PIC17C7XX

DS30289B-page 44  2000 Microchip Technology Inc.

TABLE 7-1: MODE MEMORY ACCESS The PIC17C7XX can operate in modes where the pro-

gram memory is off-chip. They are the Microprocessor

and Extended Microcontroller modes. The Micropro-

cessor mode is the default for an unprogrammed

device.

Regardless of the processor mode, data memory is

always on-chip.

FIGURE 7-2: MEMORY MAP IN DIFFERENT MODES

Operating

Mode

Internal

Program

Memory

Configuration Bits,

Test Memory,

Boot ROM

Microprocessor No Access No Access

Microcontroller Access Access

Extended

Microcontroller Access No Access

Protected

Microcontroller Access Access

Microprocessor

Mode

0000h

FFFFh

External

Program

Memory External

Program

Memory

2000h

FFFFh

0000h

01FFFh

On-chip

Program

Memory

Extended

Microcontroller

Mode

Microcontroller

Modes

0000h

01FFFh

2000h

FE00h

FFFFh

ON-CHIP ON-CHIP ON-CHIP

OFF-CHIP ON-CHIP OFF-CHIP ON-CHIP OFF-CHIP ON-CHIP

PROGRAM SPACEDATA SPACE

Config. Bits

Test Memory

Boot ROM

PIC17C752/762

0000h

FFFFh

External

Program

Memory External

Program

Memory

FFFFh

0000h 0000h

3FFFh

4000h

FE00h

FFFFh

OFF-CHIP ON-CHIP OFF-CHIP ON-CHIP OFF-CHIP ON-CHIP

Config. Bits

Test Memory

Boot ROM

PROGRAM SPACEDATA SPACE

ON-CHIPON-CHIP

00h

FFh 1FFh

120h

ON-CHIP

3FFFh

4000h

PIC17C756A/766

On-chip

Program

Memory

On-chip

Program

Memory

On-chip

Program

Memory

2FFh

220h

3FFh

320h

00h

FFh 1FFh

120h

2FFh

220h

3FFh

320h

00h

FFh 1FFh

120h

2FFh

220h

3FFh

320h

00h

FFh 1FFh

120h

00h

FFh 1FFh

120h

00h

FFh 1FFh

120h

 2000 Microchip Technology Inc. DS30289B-page 45

PIC17C7XX

7.1.2 EX TERN AL ME MORY INT ERFA CE

When eit her Microp rocessor or Extended M icrocontro l-

ler mo de is s elected, PO RTC, PORTD a nd POR TE are

configu red as the system bus . PORTC and PORTD a re

the multiplexed address/data bus and PORTE<2:0> is

for the control signals. External components are

needed to demultiplex the address and data. This can

be done as shown in Figure 7-4. The waveforms of

address and data are shown in Figure 7-3. For com-

plete timings, please refer to the electrical specification

section.

FIGURE 7-3: EXTERNAL PROGRAM

MEMORY ACCESS

WAVEFORMS

The system bus requires that there is no bus conflict

(minim al leakage), so t he output val ue (address) wi ll be

capacitively held at the desired value.

As the speed of the processor increases, external

EPROM memory with faster access time must be used.

Table 7-2 lists external m emory speed requirement s for

a given PIC 17C7XX device frequen c y.

In Extended Microcontroller mode, when the device is

executing out of internal memory, the control signals

will continue to be active. That is, they indicate the

action that is occurring in the internal memory. The

external memory access is ignored.

The following selection is for use with Microchip

EPROMs. For inte rfacing to other manufac turers mem-

ory, please refer to the electrical specifications of the

desired PIC17C7XX device, as well as the desired

memory device to ensure compatibility.

TABLE 7-2: EPROM MEMORY ACCESS

TIME OR DERING SUFFIX

The elec trical speci ficati ons no w includ e timi ng spe cifi-

cations for the memory interface with PIC17LCXXX

devices. These specifications reflect the capability of

the device by characterization. Please validate your

design w ith the se tim in gs.

FIGURE 7-4: TYPICAL EXTERNAL PROGRAM MEMORY CONNECTION DIAGRAM

Q1 Q2 Q4 Q3

Q1 Q2 Q4

<15:0>

ALE

WR ’1’

Read Cycle Write Cycle

Address out Data in Address out Data out

PIC17C7XX

Oscillator

Frequency

Instruction

Cycle Time

(TCY) EPROM Suffix

8 MHz 500 ns -25

16 MHz 250 ns -15

20 MHz 200 ns -10

25 MHz 160 ns -70

Note: The access times for this requires the use

of fast SRAMs.

AD7-AD0

PIC17CXXX

AD15-AD8

ALE

I/O(1)

AD15-AD0

Memory(3)

(MSB)

Ax-A0

D7-D0

A15-A0 Memory(3)

(LSB)

Ax-A0

D7-D0

138(1)

OE OE

WR(2) WR(2)

CE CE

Note 1: Use of I/O pins is only required for paged memory.

2: This signal is unused for ROM and EPROM devices.

3: 16-bit wide devices are now common and could be used instead of 8-bit wide devices.

373(3)

PIC17C7XX

DS30289B-page 46  2000 Microchip Technology Inc.

7.2 Data Memory Organizati on

Data memory is partitioned into two areas. The first is

the General Purpose Registers (GPR) area, and the

second is the Special Function Registers (SFR) area.

The SFRs control and provide status of device opera-

tion.

Portions of data memory are banked, this occurs in

both areas. The GPR area is banked to allow greater

than 232 bytes of general purpose RAM.

Banking requires the use of control bits for bank selec-

tion. These control bits are located in the Bank Select

region, th e BSR bi t s a re ig nore d. Fi gure 7-5 shows the

data m emory map organization.

Instructions MOVPF and MOVFP provide the means to

move v alues fro m the periph eral ar ea ( “P”) to an y loca-

tion in the register file (“F”), an d vic e-vers a. The defin i-

tion of the “P” range is from 0h to 1Fh, while the “F”

range is 0h to FFh. The “P” range has six more loca-

tions than peripheral registers, which can be used as

General Purpose Registers. This can be useful in some

applic ations wher e variables need to be co pied to other

locations in the general purpose RAM (such as saving

status information during an interrupt).

The entire data memory can be accessed either

directly, or indirectly (through file select registers FSR0

and FSR1) (see Section 7.4). Indirect addressing uses

the appropriate control bits of the BSR for access into

the banked areas of data memory. The BSR is

explained in greater detail in Section 7.8.

7.2. 1 GENERAL PURPOSE REGISTER

(GPR)

All devi ces have some amoun t of GPR area. The GPRs

are 8-bits wide. When the GPR area is greater than

232, it must be banked to allow acce ss to the additi onal

memory space.

All the PIC17C7XX devices have banked memory in

the GPR area. To facilitate switching between these

banks, the MOVLR bank instructio n has been a dded to

the instru ction set. GPRs are not initi alized by a Power-

on Reset and are unchanged on all other RESETS.

7.2.2 SPECIAL FUNCTION REGISTERS

(SFR)

The SFRs are used by the CPU and peripheral func-

tions to control th e operation of the dev ice (Figure 7-5).

These registers are static RAM.

The SFRs can be classified into two sets, those asso-

ciated with the “core” function and those related to the

peripheral functions. Those registers related to the

“core” are described here, while those related to a

periphera l featu re ar e desc ribed i n the s ection for eac h

peripheral feature.

The peripheral registers are in the banked portion of

memory, while the core registers are in the unbanked

region. To facilitate switching between the peripheral

banks, the MOVLB bank inst ruction has been pr ovided.

 2000 Microchip Technology Inc. DS30289B-page 47

PIC17C7XX

FIGURE 7-5: PIC17C7XX REGISTER FILE MAP

Addr Unbanked

00h INDF0

01h FSR0

02h PCL

03h PCLATH

04h ALUSTA

05h T0STA

06h CPUSTA

07h INTSTA

08h INDF1

09h FSR1

0Ah WREG

0Bh TMR0L

0Ch TMR0H

0Dh TBLPTRL

0Eh TBLPTRH

0Fh BSR

Bank 0 Bank 1(1) Bank 2(1) Bank 3(1) Bank 4(1) Bank 5(1) Bank 6(1) Bank 7(1) Bank 8(1,4)

10h PORTA DDRC TMR1 PW1DCL PIR2 DDRF SSPADD PW3DCL DDRH

11h DDRB PORTC TMR2 PW2DCL PIE2 PORTF SSPCON1 PW3DCH PORTH

12h PORTB DDRD TMR3L PW1DCH —DDRG SSPCON2 CA3L DDRJ

13h RCSTA1 PORTD TMR3H PW2DCH RCSTA2 PORTG SSPSTAT CA3H PORTJ

14h RCREG1 DDRE PR1 CA2L RCREG2 ADCON0 SSPBUF CA4L —

15h TXSTA1 PORTE PR2 CA2H TXSTA2 ADCON1 —CA4H —

16h TXREG1 PIR1 PR3L/CA1L TCON1 TXREG2 ADRESL —TCON3 —

17h SPBRG1 PIE1 PR3H/CA1H TCON2 SPBRG2 ADRESH — — —

Unbanked

18h PRODL

19h PRODH

1Ah

1Fh

General

Purpose

RAM

Bank 0(2) Bank 1(2) Bank 2(2) Bank 3(2,3)

20h

FFh

General

Purpose

RAM

General

Purpose

RAM

General

Purpose

RAM

General

Purpose

RAM

Note 1: SFR file locations 10h - 17h are banked. The lower nibble of the BSR specifies the bank. All unbanked

SFRs ignore the Bank Select Register (BSR) bits.

2: General Purpose Registers (GPR) locations 20h - FFh, 120h - 1FFh, 220h - 2FFh, and 320h - 3FFh are

banked. The upper nibble of the BSR specifies this bank. All other GPRs ignore the Bank Select Register

(BSR) bits.

3: RAM bank 3 is not implemented on the PIC17C752 and the PIC17C762. Reading any unimplemented reg-

ister reads ‘0’s.

4: Bank 8 is only implemented on the PIC17C76X devices.

PIC17C7XX

DS30289B-page 48  2000 Microchip Technology Inc.

TABLE 7-3: SPECIAL FUNCTION REGISTERS

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on

POR,

BOR

MCLR,

WDT

Unbanked

00h INDF0 Uses contents of FSR0 to address Data Memory (not a physical register) ---- ---- ---- ----

01h FSR0 Indirect Data Memory Address Pointer 0 xxxx xxxx uuuu uuuu

02h PCL Low order 8-bit s of PC 0000 0000 0000 0000

03h(1) PCLATH Holding Register for upper 8-bits of PC 0000 0000 uuuu uuuu

04h ALUSTA FS3 FS2 FS1 FS0 OV Z DC C 1111 xxxx 1111 uuuu

05h T0STA INTEDG T0SE T0CS T0PS3 T0PS2 T0PS1 T0PS0 —0000 000- 0000 000-

06h(2) CPUSTA — — STKAV GLINTD TO PD POR BOR --11 11qq --11 qquu

07h INTSTA PEIF T0CKIF T0IF INTF PEIE T0CKIE T0IE INTE 0000 0000 0000 0000

08h INDF1 Uses contents of FSR1 to address Data Memory (not a physical register) ---- ---- ---- ----

09h FSR1 Indirect Data Memory Address Pointer 1 xxxx xxxx uuuu uuuu

0Ah WREG Working Register xxxx xxxx uuuu uuuu

0Bh TMR0L TMR0 Register; Low Byte xxxx xxxx uuuu uuuu

0Ch TMR0H TMR0 Register; High Byte xxxx xxxx uuuu uuuu

0Dh TBLPTRL Low Byte of Progra m Memory Table Pointer 0000 0000 0000 0000

0Eh TBLP TRH High Byte of Progra m Memory Table Pointer 0000 0000 0000 0000

0Fh BSR Bank Select Regist er 0000 0000 0000 0000

Bank 0

10h PORTA(4,6) RBPU —RA5/TX1/

CK1 RA4/RX1/

DT1 RA3/SDI/

SDA RA2/SS/

SCL RA1/T0CKI RA0/INT 0-xx 11xx 0-uu 11uu

11h DDRB Data Direct ion Register for PORTB 1111 1111 1111 1111

12h PORTB(4) RB7/

SDO RB6/

SCK RB5/

TCLK3 RB4/

TCLK12 RB3/

PWM2 RB2/

PWM1 RB1/

CAP2 RB0/

CAP1 xxxx xxxx uuuu uuuu

13h RCSTA1 SPEN RX9 SREN CREN —FERR OERR RX9D 0000 -00x 0000 -00u

14h RCREG1 Serial Port Receive Register xxxx xxxx uuuu uuuu

15h TXSTA1 CSRC TX9 TXEN SYNC — — TRMT TX9D 0000 --1x 0000 --1u

16h TXREG1 Serial Port Transmit Register (for USART1) xxxx xxxx uuuu uuuu

17h SPBRG1 Baud Rate Generator Register (for USART 1) 0000 0000 0000 0000

Bank 1

10h DDRC(5) Data Direct ion Regis ter for POR TC 1111 1111 1111 1111

11h PORTC(4,5) RC7/AD7 RC6/AD6 RC5/AD5 RC4/AD4 RC3/AD3 RC2/AD2 RC1/AD1 RC0/AD0 xxxx xxxx uuuu uuuu

12h DDRD(5) Data Direct ion Regis ter for POR TD 1111 1111 1111 1111

13h PORTD(4,5) RD7/

AD15 RD6/

AD14 RD5/

AD13 RD4/

AD12 RD3/

AD11 RD2/

AD10 RD1/AD9 RD0/AD8 xxxx xxxx uuuu uuuu

14h DDRE(5) Data Direct ion Registe r for POR TE ---- 1111 ---- 1111

15h PORTE(4,5) — — — — RE3/

CAP4 RE2/WR RE1/OE RE0/ALE ---- xxxx ---- uuuu

16h PIR1 RBIF TMR3IF TMR2IF TMR1IF CA2IF CA1IF TX1IF RC1IF x000 0010 u000 0010

17h PIE1 RBIE TMR3IE TMR2IE TMR1IE CA2IE CA1IE TX1IE RC1IE 0000 0000 0000 0000

Legend: x = unknown, u = unchanged, - = unimp lemented, read as '0', q = value depends on condition.

Shaded ce lls are unimplemented, r ead as '0'.

Note 1: The upper byte of the program counter is not di rectly access i ble. PCLATH is a holding register for PC<15:8> whose

conten ts are updated from, or transferred to, the upper byte of the program c ounter.

2: The TO and PD status bits in CPUSTA are not affected by a MCLR Reset.

3: Bank 8 and associated registers are only implemented on the PIC17C76X devices.

4: This is the value that will be in the port output latch.

5: When the device is configured for Microprocessor or Extended Micro controlle r mode, the operation of this port does not rely on these

registers.

6: On any devic e RESET, these pins are con figured as inputs.

 2000 Microchip Technology Inc. DS30289B-page 49

PIC17C7XX

Bank 2

10h TMR1 Timer1’s Register xxxx xxxx uuuu uuuu

11h TMR2 Timer2’s Register xxxx xxxx uuuu uuuu

12h TMR3L Timer3’s Register; Low Byte xxxx xxxx uuuu uuuu

13h TMR3H Timer3’s Register; High Byt e xxxx xxxx uuuu uuuu

14h PR1 Timer1’s Per iod Regis ter xxxx xxxx uuuu uuuu

15h PR2 Timer2’s Per iod Regis ter xxxx xxxx uuuu uuuu

16h PR3L/CA1L Timer3’s Period Re giste r - Low Byte/Cap tur e1 Regis ter ; Low Byte xxxx xxxx uuuu uuuu

17h PR3H/CA1H Timer3’s Period Register - High Byt e/Cap ture1 Re giste r; High Byte xxxx xxxx uuuu uuuu

Bank 3

10h PW1DCL DC1 DC0 — — — — — — xx-- ---- uu-- ----

11h PW2DCL DC1 DC0 TM2PW2 — — — — — xx0- ---- uu0- ----

12h PW1DCH DC9 DC8 DC7 DC6 DC5 DC4 DC3 DC2 xxxx xxxx uuuu uuuu

13h PW2DCH DC9 DC8 DC7 DC6 DC5 DC4 DC3 DC2 xxxx xxxx uuuu uuuu

14h CA2L Capture2 Low Byte xxxx xxxx uuuu uuuu

15h CA2H Capture2 High Byte xxxx xxxx uuuu uuuu

16h TCON1 CA2ED1 CA2ED0 CA1ED1 CA1ED0 T16 TMR3CS TMR2CS TMR1CS 0000 0000 0000 0000

17h TCON2 CA2OVF CA1OVF PWM2ON PWM1ON CA1/PR3 TMR3ON TMR2ON TMR1ON 0000 0000 0000 0000

Bank 4

10h PIR2 SSPIF BCLIF ADIF —CA4IF CA3IF TX2IF RC2IF 000- 0010 000- 0010

11h PIE2 SSPIE BCLIE ADIE —CA4IE CA3IE TX2IE RC2IE 000- 0000 000- 0000

12h Unimplemented — — — — — — — — ---- ---- ---- ----

13h RCSTA2 SPEN RX9 SREN CREN —FERR OERR RX9D 0000 -00x 0000 -00u

14h RCREG2 Serial Port Receive Register for USART2 xxxx xxxx uuuu uuuu

15h TXSTA2 CSRC TX9 TXEN SYNC — — TRMT TX9D 0000 --1x 0000 --1u

16h TXREG2 Serial Port Transmit Register for USART2 xxxx xxxx uuuu uuuu

17h SPBRG2 Baud Rate Generator for USAR T2 0000 0000 0000 0000

Bank 5:

10h DDRF Data Direction Register for POR TF 1111 1111 1111 1111

11h PORTF(4) RF7/

AN11 RF6/

AN10 RF5/

AN9 RF4/

AN8 RF3/

AN7 RF2/

AN6 RF1/

AN5 RF0/

AN4 0000 0000 0000 0000

12h DDRG Data Direction Register for POR TG 1111 1111 1111 1111

13h PORTG(4) RG7/

TX2/CK2 RG6/

RX2/DT2 RG5/

PWM3 RG4/

CAP3 RG3/

AN0 RG2/

AN1 RG1/

AN2 RG0/

AN3 xxxx 0000 uuuu 0000

14h ADCON0 CHS3 CHS2 CHS1 CHS0 —GO/DONE —ADON 0000 -0-0 0000 -0-0

15h ADCON1 ADCS1 ADCS0 ADFM —PCFG3 PCFG2 PCFG1 PCFG0 000- 0000 000- 0000

16h ADRESL A/D Result Register Low By te xxxx xxxx uuuu uuuu

17h ADRESH A/D Result Register High Byte xxxx xxxx uuuu uuuu

TABLE 7-3: SPECIAL FUNCTION REGISTERS (CONTINUED)

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on

POR,

BOR

MCLR,

WDT

Legend: x = unknown, u = unchanged, - = unimp lemented, read as '0', q = value depends on condition.

Shaded ce lls are unimplemented, r ead as '0'.

Note 1: The upper byte of the program counter is not direc tly accessible. PCLATH is a holding register for PC<15:8> whose

conten ts are up dated from, or transferred to, the upper byte of the program c ounter.

2: The TO and PD status bits in CPUSTA are not affected by a MCLR Reset.

3: Bank 8 and associated registers are only implemented on the PIC17C76X devices.

4: This is the value that will be in the port output latch.

5: When the device is configured for Microprocessor or Extended Microcontroller mode, the operation of this port does not rely on these

registers.

6: On any devic e RESET, these pins are con figured as inputs.

PIC17C7XX

DS30289B-page 50  2000 Microchip Technology Inc.

Bank 6

10h SSPADD SSP Address Regi ster in I2C Sl ave mode. SSP Baud Ra te Reloa d Re gister in I2C Maste r mode 0000 0000 0000 0000

11h SSPCON1 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 0000 0000

12h SSPCON2 GCEN AKSTAT AKDT AKEN RCEN PEN RSEN SEN 0000 0000 0000 0000

13h SSPSTAT SMP CKE D/A PSR/WUA BF 0000 0000 0000 0000

14h SSPBUF Synchrono us Serial Port Receive Buff er/ Transmit Register xxxx xxxx uuuu uuuu

15h Unimplemented — — — — — — — — ---- ---- ---- ----

16h Unimplemented — — — — — — — — ---- ---- ---- ----

17h Unimplemented — — — — — — — — ---- ---- ---- ----

Bank 7

10h PW3DCL DC1 DC0 TM2PW3 — — — — — xx0- ---- uu0- ----

11h PW3DCH DC9 DC8 DC7 DC6 DC5 DC4 DC3 DC2 xxxx xxxx uuuu uuuu

12h CA3L Capture3 Low Byte xxxx xxxx uuuu uuuu

13h CA3H Capture3 High Byte xxxx xxxx uuuu uuuu

14h CA4L Capture4 Low Byte xxxx xxxx uuuu uuuu

15h CA4H Capture4 High Byte xxxx xxxx uuuu uuuu

16h TCON3 —CA4OVF CA3OVF CA4ED1 CA4ED0 CA3ED1 CA3ED0 PWM3ON -000 0000 -000 0000

17h Unimplemented — — — — — — — — ---- ---- ---- ----

Bank 8(3)

10h(3) DDRH Data Direc tion Regis ter for PO R TH 1111 1111 1111 1111

11h(3) PORTH(4) RH7/

AN15 RH6/

AN14 RH5/

AN13 RH4/

AN12 RH3 RH2 RH1 RH0 xxxx xxxx uuuu uuuu

12h(3) DDRJ Data Direction Registe r for POR TJ 1111 1111 1111 1111

13h(3) PORTJ(4) RJ7 RJ6 RJ5 RJ4 RJ3 RJ2 RJ1 RJ0 xxxx xxxx uuuu uuuu

14h(3) Unimplemented — — — — — — — — ---- ---- ---- ----

15h(3) Unimplemented — — — — — — — — ---- ---- ---- ----

16h(3) Unimplemented — — — — — — — — ---- ---- ---- ----

17h(3) Unimplemented — — — — — — — — ---- ---- ---- ----

Unbanked

18h PRODL Low Byte of 16-bit Product (8 x 8 Hardware Mult iply) xxxx xxxx uuuu uuuu

19h PRODH High Byte of 16-bit Product (8 x 8 Hardware Multiply) xxxx xxxx uuuu uuuu

TABLE 7-3: SPECIAL FUNCTION REGISTERS (CONTINUED)

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on

POR,

BOR

MCLR,

WDT

Legend: x = unknown, u = unchanged, - = unimp lemented, read as '0', q = value depends on condition.

Shaded ce lls are unimplemented, r ead as '0'.

Note 1: The upper byte of the program counter is not di rectly access i ble. PCLATH is a holding register for PC<15:8> whose

conten ts are updated from, or transferred to, the upper byte of the program c ounter.

2: The TO and PD status bits in CPUSTA are not affected by a MCLR Reset.

3: Bank 8 and associated registers are only implemented on the PIC17C76X devices.

4: This is the value that will be in the port output latch.

5: When the device is configured for Microprocessor or Extended Micro controlle r mode, the operation of this port does not rely on these

registers.

6: On any devic e RESET, these pins are con figured as inputs.

 2000 Microchip Technology Inc. DS30289B-page 51

PIC17C7XX

7.2.2.1 ALU Status Register (ALUSTA)

The ALUSTA register contains the status bits of the

Arithmetic and Logic Unit and the mode control bits for

the indirect addressing register.

As with all the other re gisters, t he ALUSTA register ca n

be the destination for any instruction. If the ALUSTA

the Z, DC, C, or OV bits, then the write to these three

bits is disabled. These bits are set or cleared according

to th e dev ice lo gic. Theref ore, the r esult of an i nstr uc-

tion with the ALUSTA register as destination may be

different than intended.

For example, the CLRF ALUSTA, F instruction will clear

the upper four bits and set the Z bit. This leaves the

ALUST A register as 0000u1uu (where u = unchanged).

It is recommended, therefore, that only BCF, BSF, SWAPF

and MOVWF instructions be used to alter the ALUSTA

status bits. To see how other instructions affect the sta-

tus bit s, see the “Instruction Set Summary.”

The A ri th me tic a nd Log i c Un it (A L U) i s c apabl e o f ca r-

rying out arithm etic or logical operations on two oper-

ands, or a single operand. All single operand

instructions operate either on the WREG register, or

the given file register . For two operand instructio ns, one

of the operands is the WREG register and the other is

either a file register, or an 8-bit immediate constant.

Note 1: The C and DC bits opera te as a borr ow and

digit borrow bit, respectively, in subtracti on.

See the SUBLW and SUBWF instructions for

examples.

2: The overflow bit will be set if the 2’s c omple-

ment result exceeds +127, or is less than -128.

R/W-1 R/W-1 R/W-1 R/W-1 R/W-x R/W-x R/W-x R/W-x

FS3 FS2 FS1 FS0 OV Z DC C

bit 7 bit 0

bit 7-6 FS3:FS2: FSR1 Mode Select bits

00 = Post auto-decrement FSR1 value

01 = Post auto-increment FSR1 value

1x = FSR1 value does not change

bit 5-4 FS1:FS0: FSR0 Mode Select bits

00 = Post auto-decrement FSR0 value

01 = Post auto-increment FSR0 value

1x = FSR0 value does not change

bit 3 OV: Overflow bit

This bit is used for signed arithmetic (2’s complement). It indicates an overflow of the 7-bit

magnitude, which causes the sign bit (bit7) to change state.

1 = Overflow occurred f or signed arithmetic (in this ar ithmetic operation)

0 = No overflow occurred

bit 2 Z: Zero bit

1 = The result of an arithmetic or logic operation is zero

0 = The result of an arithmetic or logic operation is not zero

bit 1 DC: Digit carry/borrow bit

For ADDWF and ADDLW instructions.

1 = A carry-out from the 4th low order bit of the result occurred

0 = No carry-out from the 4th low order bit of the result

Note: For borrow, the polarity is reversed.

bit 0 C: Carry/borrow bit

For ADDWF and ADDLW instructions. Note that a subtraction is executed by adding the two’s

complement of the second operand.

For rotate (RRCF, RLCF) instructions, this bit is loaded with either the high or low order bit of the

source register.

1 = A carry-out from the Most Significant bit of the result occurred

0 = No carry-out from the Most Significant bit of the result

Note: For borrow, the polarity is reversed.

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

- n = Value at POR Reset ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown

PIC17C7XX

DS30289B-page 52  2000 Microchip Technology Inc.

7.2.2.2 CPU Status Register (CPUSTA)

The CPUSTA register contains the status and control

bits for the CPU. This register has a bit that is used to

globally enable/disable interrupts. If only a specific

inter rupt is desire d to be enabled/d isabled, ple ase refer

to the Interrupt Status (INTSTA) register and the

Peripheral Interrupt Enable (PIE) registers. The

CPUSTA register als o indi cates if the st ack is avail able

and contains the Power-down (PD) and Time-out (TO)

bits. The TO, PD, and STKAV bits are not writable.

These bits are set and cleared according to device

logic. Therefore, the result of an instruction with the

CPUSTA register as destination may be different than

intended.

The POR bit allows the differentiation between a

Power-on Reset, external MCLR Reset, or a WDT

Reset. The BOR bit indicates if a Brown-out Reset

occurred.

Note 1: The BOR status bit is a don’t care and is

not necessarily predictable if the Brown-out

circuit is disabled (when the BODEN bit in

the Configuration word is programmed).

U-0 U-0 R-1 R/W-1 R-1 R-1 R/W-0 R/W-1

— — STKAV GLINTD TO PD POR BOR

bit 7 bit 0

bit 7-6 Unimplemented: Read as '0'

bit 5 STKAV: Stack Available bit

This bit indicates that the 4-bit stack pointer value is Fh, or has rolled over from Fh → 0h

(stack overflow).

1 =Stack is available

0 =Stack is full, or a stack overflow may have occurred (once this bit has been cleared by a

stack overflow, only a device RESET will set this bit)

bit 4 GLINTD: Global Interrupt Disable bit

This bit disables all interrupts. When enabling interrupts, only the sources with their enable bits

set can cause an interru pt.

1 = Disable all interrupts

0 = Enables all unmasked interrupts

bit 3 TO: WDT Time-out Status bit

1 = After power-up, by a CLRWDT instruction, or by a SLEEP instruction

0 = A Watchdog Timer time-out occurred

bit 2 PD: Power-down Status bit

1 = After power-up or by the CLRWDT instruction

0 = By execution of the SLEEP instruction

bit 1 POR: Power-on Reset Status bit

1 = No Power-on Reset occurred

0 = A Power-on Reset occurred (must be set by software)

bit 0 BOR: Brown-out Reset Status bit

When BODEN Configuration bit is set (enabled):

1 = No Brown-out Reset occurred

0 = A Brown-out Reset occurred (must be set by software)

When BODEN Configuration bit is clear (disabled):

Don’t care

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

- n = Value at POR Reset ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown

 2000 Microchip Technology Inc. DS30289B-page 53

PIC17C7XX

7.2.2.3 TMR0 Status/Control Register

(T0STA)

This register contains various control bits. Bit7

(INTEDG) is used to control the ed ge upon which a si g-

nal on the RA0/INT pin will set the RA0/INT interrupt

flag. The other bit s co nfigure Timer0, it’s prescaler an d

clock source.

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0

INTEDG T0SE T0CS T0PS3 T0PS2 T0PS1 T0PS0 —

bit 7 bit 0

bit 7 INTEDG: RA0/INT Pin Interrupt Edge Select bit

This bit selects the edge upon which the interrupt is detected.

1 = Rising edge of RA0/INT pin generates interrupt

0 = Falling edge of RA0/INT pin generates interrupt

bit 6 T0SE: Timer0 External Clock Input Edge Select bit

This bit selects the edge upon which TMR0 will increment.

When T0CS = 0 (External Clock):

1 = Rising edge of RA1/T0CKI pin increments TMR0 and/or sets the T0CKIF bit

0 = Falling edge of RA1/T0CKI pin increments TMR0 and/or sets a T0CKIF bit

When T0CS = 1 (Internal Clock):

Don’t care

bit 5 T0CS: Timer0 Clock Source Select bit

This bit selects the clock source for Timer0.

1 = Internal instruction clock cycle (TCY)

0 = External clock input on the T0CKI pin

bit 4-1 T0PS3:T0PS0: Timer0 Prescale Selection bits

These bits select the prescale value for Timer0.

bit 0 Unimplemented: Read as ’0’

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

- n = Value at POR Reset ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown

T0PS3:T0PS0 Prescale Value

0000

0001

0010

0011

0100

0101

0110

0111

1xxx

1:1

1:2

1:4

1:8

1:16

1:32

1:64

1:128

1:256

PIC17C7XX

DS30289B-page 54  2000 Microchip Technology Inc.

7.3 S tack Operation

PIC17C7XX d evices have a 1 6 x 16-bit ha rdware st ack

(Figure 7-1). The stack is not part of either the program

or data memory space, and the stack pointer is neither

readable nor writable. The PC (Program Counter) is

“PUSH’d” onto the stack when a CALL or LCALL

instruction is executed, or an interrupt is acknowl-

edged. The stack is “POP’d” in the event of a RETURN,

RETLW, or a RETFIE inst ruc ti o n e x ec ut i on. P CLATH is

not affected by a “PUSH” or a “POP” operation.

The stack operates as a circular buffer, with the stack

pointer initialized to '0' after all RESETS. There is a

stac k av ai lab le bi t (STKAV) to all ow s oftware to ensu re

that the stack will not overflow. The STKAV bit is set

after a device RESET. When the stack pointer equals

Fh, STKAV is cleared. When the stack pointer rolls over

from Fh to 0h, the STKAV bit will be held clear until a

device RESET.

After the device is “PUSH’d” sixteen times (without a

“POP”), the seventeenth push overwrites the value

from the firs t push. The eigh teenth pu sh overwri tes the

second push (and so on).

7.4 Indirect Addressing

Indirect addressing is a mode of add ressing dat a mem-

ory where the data memory address in the instruction

is not fixed. That is, the register that is to be read or

written can be modified by the program. This can be

useful for data tables in the data memory. Figure 7-6

shows the operation of indirect addressing. This

depicts the moving of the value to the data memory

address spec ifi ed by the value of the FSR regis ter.

Example 7-1 shows the use of indirect addressing to

clear RA M in a min imum numbe r of instru ctions. A s im-

ilar concept could be used to move a defined number

of bytes (block) of data to the USART transmit register

(TXREG). The starting address of the block of data to

be transmitted could ea sily be modified by the program.

FIGURE 7-6: INDIRECT ADDRESSING

7.4.1 INDIRECT ADDRESSING

REGISTERS

The PIC17C7XX ha s four registers for ind irect address-

ing. These regi ste r s are:

•INDF0 and FSR0

•INDF1 and FSR1

Registers INDF0 and INDF1 are not physically imple-

mented. Read ing or wr i tin g to the se regi st ers ac tiv ate s

indirec t addressing , with the va lue in the co rresponding

FSR regist er being the add ress of the da ta. The FSR is

an 8-bit re gister and al lows addre ssing anywhere i n the

256-byte data memory address range. For banked

memory, the bank of memory accessed is specified by

the value in the BSR.

If file INDF0 (or INDF1) itself is read indirectly via an

FSR, all '0's are read (Zero bit is set ). Similarly , if INDF0

(or INDF1) is written to indirectly, the operation will be

equival ent to a NOP, an d the stat us bits are not affec ted.

Note 1: There is not a status bit for stack under-

flow. The STKAV bit can be used to detect

the underflow which results in the stack

pointer being at the Top-of-Stack.

2: There are no instruction mnemonics

called PUSH or POP. These are actions

that occur from the execution of the CALL,

RETURN, RETLW and RETFIE instruc-

tions, or the vectoring to an interrupt

vector.

3: After a RESET, if a “POP” operation

occurs before a “PUSH” operation, the

STKAV bit will be cleared. This will

appear as if the stack is full (underflow

has occurred). If a “PUSH” operation

occurs next (before another “POP”), the

STKAV bit will be locked clear. Only a

device RESET will cause this bit to set.

Opcode Address

File = INDFx

FSR

Instruction

Executed

Instruction

Fetched

RAM

Opcode File

 2000 Microchip Technology Inc. DS30289B-page 55

PIC17C7XX

7.4.2 INDIRECT ADDRESSING

OPERATION

The indirect addressing capability has been enhanced

over that of the PIC16CXX family . There are two control

bits associated with each FSR register. These two bits

configure the FSR register to:

•Auto-decrement the value (address) in the FSR

after an indirect access

•Auto-increment the va lue (addres s) in the FSR

after an indirect access

•No chan ge to the value (addr ess) in the FSR afte r

an indirect access

These control bits are located in the ALUSTA register.

The FSR1 register is controlled by the FS3:FS2 bits

and FSR0 is controlled by the FS1:FS0 bits.

When us ing the auto-in crement or aut o-decrement fe a-

tures, the effect on the FSR is not reflected in the

ALUSTA register. For example, if the indirect address

causes the FSR to equal '0', the Z bit will not be set.

If the FSR register contains a value of 0h, an indirect

read will rea d 0h (Zero bit is set) while an in dire ct write

will b e equivalent to a NOP (status bit s are not af fected).

Indirect addressing allows single cycle data transfers

within the entire data space. This is possible with the

use of the MOVPF a nd MOVFP instructions, where either

'p' or 'f' is specified as INDF0 (or INDF1).

If the source or destination of the indirect address is in

banked memory, the location accessed will be deter-

mined by the value in t he BSR .

A simple program to clear RAM from 20h - FFh is

shown in Example 7-1.

EXAMPLE 7-1: INDIRECT ADDRESSING

7.5 Table Pointer (TBLPTRL and

TBLPTRH)

File registers TBLPTRL and TBLPTRH form a 16-bit

pointer to address the 64K program memory space.

The table pointer is used by instructions TABLWT and

TABLRD.

The TABLRD and the TABLWT instructions allow trans-

fer of dat a between program and dat a spa ce. The t able

pointer serves as the 16-bit address of the data word

within the program memory. For a more complete

description of these registers and the operation of

Table Reads and Table Writes, see Section 8.0.

7.6 Table Latch (TBLATH, TBLATL)

The table latch (TBLAT) is a 16-bit register, with

TBLATH and TBLATL referring to the high and low

bytes of the register. It is not mapped into data or pro-

gram memory. The table latch is used as a temporary

holding latch during data transfer between program

and data memory (see TABLRD, TABLWT, TLRD and

TLWT instruction descriptions). For a more complete

description of these registers and the operation of

Table Reads and Table Writes, see Section 8.0.

MOVLW 0x20 ;

MOVWF FSR0 ; FSR0 = 20h

BCF ALUSTA, FS1 ; Increment FSR

BSF ALUSTA, FS0 ; after access

BCF ALUSTA, C ; C = 0

MOVLW END_RAM + 1 ;

LP CLRF INDF0, F ; Addr(FSR) = 0

CPFSEQ FSR0 ; FSR0 = END_RAM+1?

GOTO LP ; NO, clear next

: ; YES, All RAM is

: ; cleared

PIC17C7XX

DS30289B-page 56  2000 Microchip Technology Inc.

7.7 Program Counter Module

The Program Counter (PC) is a 16-bit register . PCL, the

low byte of the PC, is mapped in the data memory . PCL

is readable and writable just as is any other register.

PCH is the high byte of the PC and is not directly

addressable. Since PCH is not mapped in data or pro-

gram memory, an 8-bit register PCLATH (PC high

latch) i s u sed as a h old in g la tch for the high by te of th e

PC. PCLATH is mapped into data memory. The user

can read or write PCH through PCLATH.

The 16-bit wide PC is incremented after each instruc-

tion fetch duri ng Q1 unles s:

•Modified by a GOTO, CALL, LCALL, RETURN,

RETLW, or RETFIE instruction

•Modified by an interrupt response

•Due to destination write to PCL by an instruction

“Skips” are equivalent to a forced NOP cycle at the

skipped address.

Figure 7-7 and Figure 7-8 show the operation of the

program counter for various situations.

FIGURE 7-7: PROGRAM COUNTER

OPERATION

FIGURE 7-8: PROGRAM COUNTER

USING THE CALL AND

GOTO INSTRUCTIONS

Using Figure 7-7, the operations of the PC and

PCLATH for diffe rent instructions are as foll ows:

a) LCALL instructions:

An 8-bit destination address is provided in the

instruction (opcode). PCLATH is unchanged.

PCLATH → PCH

Opcode<7:0> → PCL

b) Read instructions on PCL:

Any instruction that reads PCL.

PCL → data bus → ALU or destination

PCH → PCLATH

c) Write instructions on PCL:

Any instruction that writes to PCL.

8-bit data → data bus → PCL

PCLATH → PCH

d) Read-Modify-Write instructions on PCL:

Any instruction that does a read-write-modify

operation on PCL, such as ADDWF PCL.

Read: PCL → data bus → ALU

Write: 8-bi t result → data bus → PCL

PCLATH → PCH

e) RETURN instruction:

Stack<MRU> → PC<15:0>

Using Fig ure 7-8, the opera tion of t he PC and PCLATH

for GOTO and CALL instructions is as follows:

CALL, GOTO instructions:

A 13-bit destination address is provided in the

ins truction (opcod e).

Opcode<12:0> → PC<12:0>

PC<15:13> → PCLATH<7:5>

Opcode<12:8> → PCLATH<4:0>

The read-modify-write only affects the PCL with the

result. P CH is loaded with the value in the PCLA TH. For

example, ADDWF PCL will result in a jump within the

current page. If PC = 03F0h, WREG = 30h and

PCLATH = 03h be fore instru ction, PC = 0320h after th e

instruction. To accomplish a true 16-bit computed jump,

the user needs to compute the 16-bit destination

address, write the high byte to PCLATH and then write

the low value to PCL.

The following PC related operations do not change

PCLATH:

a) LCALL, RETLW, and RETFIE instructions .

b) Interrupt vector is forced onto the PC.

c) Read-modify-write instructions on PCL

(e.g. BSF PCL).

Inte r nal Da ta B u s <8>

PCLATH 8

PCH PCL

15 0

7540

12 8 7 0

PC<15:13>

PCLATH

From Instruction

PCH PCL

1315

 2000 Microchip Technology Inc. DS30289B-page 57

PIC17C7XX

7.8 Bank Select Register (BSR)

The BSR is used to switch between banks in the data

memory area (Fi gure 7-9). In the PIC17C7XX devi ces ,

the entire byte is implemented. The lower nibble is

used to select the peripheral register bank. The upper

nibble is used to select the general purpose memory

bank.

All the Special Function Registers (SFRs) are mapped

into the data memory space. In order to accommodate

the large number of registers, a banking scheme has

been used. A segment of the SFRs, from address 10h

to addres s 17h, is bank ed. The low er nibble of t he bank

select register (BSR) selects the currently active

“peripheral bank.” Effort has been made to group the

periphera l registers of related fu nctional ity in one bank .

Howeve r , it wil l still be ne cessary to sw itch from ba nk to

bank in order to address a ll periph erals rel ated to a sin-

gle task. To assist this, a MOVLB bank instruct ion has

been included in the instruction set.

The need for a large general purpose memory space

dictated a general purpose RAM b ank in g sc hem e. Th e

upper nibble of the BSR selects the currently active

general purpose RAM bank. To assist this, a MOVLR

bank instruction has been provided in the instruction

set.

If the currentl y select ed bank is no t implemen ted (suc h

as Bank 13), any read will read all '0's. Any write is

comple ted to th e b it bucket and th e ALU status bi ts wil l

be set/cleared as appropriate.

FIGURE 7-9: BSR OPERATION

Note: Registers in Bank 15 in the Special Func-

tion Register area, are reserved for

Microchip use. Reading of registers in this

bank may caus e random valu es to be read.

7430

10h

17h

BSR

0 123 8 15

• • •

20h

FFh • • •

(1)

(2)

Bank 15Bank 8

Bank 3Bank 2Bank 1Bank 0

012

Bank 2Bank 1Bank 0

Bank 15

SFR

Banks

GPR

Banks

Address

Range

Note 1: For the SFRs only Banks 0 through 8 are implemented. Selection of an unimplemented bank is not recommended.

Bank 15 is reserved for Microchip use, reading of registers in this bank may cause random values to be read.

2: For the GPRs, Bank 3 is unimplemented on the PIC17C752 and the PIC17C762. Selection of an unimplemented bank

is not recommended.

3: SFR Bank 8 is only implemented on the PIC17C76X.

Bank 3

Bank 4

4 56 7

Bank 7Bank 6B ank 5Bank 4

(Peripheral)

(RAM)

PIC17C7XX

DS30289B-page 58  2000 Microchip Technology Inc.

NOTES:

 2000 Microchip Technology Inc. DS30289B-page 59

PIC17C7XX

8.0 TABLE READS AND TABLE

WRITES

The PIC17C7XX has four instructions that allow the

process or to move dat a from the data mem ory space to

the program memory space, and vice versa. Since the

program memory space is 16-bits wide and the data

memory space is 8-bits wide, two operations are

required to move 16-bit values to/from the data

memory.

The TLWT t,f and TABLWT t,i,f instructions are

used to write data from the data memory space to the

program memory space. The TLRD t,f and TABLRD

t,i,f instructio ns are us ed to wri te dat a from the pro-

gram memory space to the data memory space.

The program memory can be internal or external. For

the pr ogra m mem ory ac ce ss to b e ex tern al , the dev ic e

needs to be operating in Microprocessor or Extended

Microcontroller mode.

Figure 8-1 through Figure 8-4 show the operation of

these four instructions. The steps show the sequence

of operation.

FIGURE 8-1: TLWT INSTRUCTION

OPERATION

FIGURE 8-2: TABLWT INSTRUCTION

OPERATION

TABLE POINTER

TABLE LATCH (16-bit)

Program Memory

Data

Memory

TBLPTRH TBLPTRL

TABLATH TABLATL

TLWT 1,f TLWT 0,f

Step 1: 8-bit value from register ’f’, loaded into the high or low

byte in TABLAT (16-bit).

TABLE POINTER

TABLE LATCH (16-bit)

Program Memory

Data

Memory

TBLPTRH TBLPTRL

TABLATH TABLATL

TABLWT 1,i,f TABLWT 0,i,f

Prog-Mem

(TBLPTR)

Step 1: 8-bit value from register ’f’, loaded into the high or low

byte in TABLAT (16-bit).

2: 16-bit T ABLAT value written to address Program Memory

(TBLPTR).

3: If “i” = 1, then TBLPTR = TBLPTR + 1,

If “i” = 0, then TBLPTR is unchanged.

PIC17C7XX

DS30289B-page 60  2000 Microchip Technology Inc.

FIGURE 8-3: TLRD INSTRUCTION

OPERATION FIGURE 8-4: TABLRD INSTRUCTION

OPERATION

TABLE POINTER

TABLE LATCH (16-bit)

Program Memory

Data

Memory

TBLPTRH TBLPTRL

TABLATH TABLATL

TLRD 1,f TLRD 0,f

Step 1: 8-bit value from TABLAT (16-bit) high or low byte,

loaded into register ’f’.

TABLE POINTER

TABLE LATCH (16-bit)

Program Memory

Data

Memory

TBLPTRH TBLPTRL

TABLATH TABLATL

TABLRD 1,i,f TABLRD 0,i,f

Prog-Mem

(TBLPTR)

Step 1: 8-bit value from TABLAT (16-bit) high or low byte,

loaded into register ’f’.

2: 16-bit value at Program Memory (TBLPTR), loaded into

TABLAT register.

3: If “i” = 1, then TBLPTR = TBLPTR + 1,

If “i” = 0, then TBLPTR is unchanged.

 2000 Microchip Technology Inc. DS30289B-page 61

PIC17C7XX

8.1 Table Writes to In ternal Memory

A table write operation to internal memory causes a

long write operation. The long write is necessary for

programming the internal EPROM. Instruction execu-

tion is halted while in a long write cycle. The long write

will be terminated by any enabled interrupt. To ensure

that the EPROM location has been well programmed,

a minimum programming time is required (see specifi-

cation #D1 14). Having o nly one i nterrupt enabled to t er-

minate the long write ensures that no unintentional

interrupts will prematurely terminate the long write.

The sequence of events for programming an internal

program memory location should be:

1. Disa ble all i nter rupt so urces, except the s ource

to terminate EPROM program write.

2. Raise MCLR/VPP pin to the programming

voltage.

3. Clear the WDT.

4. Do the table write. The interrupt will terminate

the long write.

5. Verify the memory location (table read).

8.1.1 TERMINATIN G LONG WR ITES

An interrupt source or RESET are the only events that

terminate a long write operation. Terminating the long

write fro m an interrupt source requires that the interru pt

enable and flag bits are set. The GLINTD bit only

enables the vectoring to the interrupt address.

If the T0CKI, RA0/INT, or TMR0 interrupt source is

used to term inate the long write, th e interrupt flag of th e

highest priority enabled interrupt, will terminate the long

write and automatically be cleared.

If a peripheral interrupt source is used to terminate the

long write, the interrupt enable and flag bits must be

set. The interrupt flag will not be automatically cleared

upon the vectoring to the interrupt vector address.

The GLINTD bit determines whether the program will

branch to the interrupt v ector when the long write is t er-

minated. If GLINTD is clear, the program will vector, if

GLINTD is set, the program will not vector to the

interrupt add res s.

TABLE 8-1: INTERRUPT - TABLE WRITE INTERACTION

Note 1: Programming requirements must be

met. See timing specifica tion in electrical

specifications for the desired device.

Violating these specifications (including

temperature) may result in EPROM

locations that are not fully programmed

and may lose their state over time.

2: If the VPP requirement is not met, the

ta ble write is a 2- cycle writ e and the pro-

gram memory is unchanged.

Note 1: If an interru pt is pen di ng, th e TABLWT is

aborted (a NOP is exec uted). The highest

priority pending interrupt, from the

T0CKI, RA0/INT, or TMR0 sources that

is enabled, has its flag cleared.

2: If the interrupt is not being used for the

program write timing, the interrupt

should be dis abled. This will ensure that

the interrupt is not lost, nor will it termi-

nate the long wri te prem aturely.

Interrupt

Source GLINTD Enable

Bit Flag

Bit Action

RA0/INT,

TMR0,

T0CKI

Terminate long t ab le wr i te (to inte rna l pro gram mem ory),

branch to interrupt vector (branch clears flag bit).

None.

Terminate long table write, do not branch to interrupt

vector (flag is automatically cleared).

Peripheral 0

Terminate long table write, branch to interrupt vector.

None.

Terminate long table write, do not branch to interrupt

vector (flag rema ins set).

PIC17C7XX

DS30289B-page 62  2000 Microchip Technology Inc.

8.2 Table Writes to External Memory

Tab le writ es to ex ternal m emory a re alwa ys two-c ycle

instructions. The second cycle writes the data to the

external memory location. The sequence of events for

an external memory write are the same for an internal

write.

8.2.1 TABLE WRITE CODE

The “i” operand of the TABLWT instruction can specify

that the value in the 1 6-bit TBLP TR re gister i s automat-

ically incremented (for the next write). In Example 8-1,

the TBLPTR register is not automatically incremented.

EXAMPLE 8-1: TABLE WRITE

FIGURE 8-5: TABLWT WRITE TIMING (EXTERNAL MEMORY)

CLRWDT ; Clear WDT

MOVLW HIGH (TBL_ADDR) ; Load the Table

MOVWF TBLPTRH ; address

MOVLW LOW (TBL_ADDR) ;

MOVWF TBLPTRL ;

MOVLW HIGH (DATA) ; Load HI byte

TLWT 1, WREG ; in TABLATH

MOVLW LOW (DATA) ; Load LO byte

TABLWT 0,0,WREG ; in TABLATL

; and write to

; program memory

; (Ext. SRAM)

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

AD15:AD0

Instruction

Fetched

Instruction

Executed

ALE

TABLWT INST (PC+1)

INST (PC-1) TABLWT cy cle1 TABLWT cycle2

INST (PC+2)

Data write cycle

’1’

PC PC+1 TBL PC+2Data out

INST (PC+1)

Note: If external write and GLINTD = ’1’ and Enable bit = ’1’, then when ’1’ → Flag bit, do table write.

The highest pending interrupt is cleared.

 2000 Microchip Technology Inc. DS30289B-page 63

PIC17C7XX

FIGURE 8-6: CONSECUTIVE TABLWT WRITE TIMING (EXTERNAL MEMORY)

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

AD15:AD0

Instruction

Fetched

Instruction

Executed

ALE

TABLWT1 TABLWT2 INST (PC+2)

INST (PC-1) TABLWT1 cycle1 TABLWT1 cycle2 TABLWT2 cycle1 TABLWT 2 cyc le2

Data write cycle Data write cycle

INST (PC+3)

PC+1 TBL1 PC+2 TBL2 PC+3

Data out 1 Data out 2

INST (PC+2)

PIC17C7XX

DS30289B-page 64  2000 Microchip Technology Inc.

8.3 Table Reads

The table read allo w s th e pro gram memory to be rea d.

This allows constant s to be stored in the program mem-

ory space and retrieved into data memory when

needed. Example 8-2 reads the 16-bit value at program

memory address TBLPTR. After the dummy byte has

been read from the TABLATH, the TABLATH is loaded

with the 16-bit data from program memory address

TBLPTR and then increments the TBLPTR value. The

first read loads the data into the latch and can be con-

sidered a dummy read (unknown data loaded into ’f’).

INDF0 should be configured for either auto-increment

or auto-decrement.

EXAMPLE 8-2: TABLE READ

FIGURE 8-7: TABLRD TIMING

FIGURE 8-8: TABLRD TIMING (CONSECUTIVE TABLRD INSTRUCTIONS)

MOVLW HIGH (TBL_ADDR) ; Load the Table

MOVWF TBLPTRH ; address

MOVLW LOW (TBL_ADDR) ;

MOVWF TBLPTRL ;

TABLRD 0, 1, DUMMY ; Dummy read,

; Updates TABLATH

; Increments TBLPTR

TLRD 1, INDF0 ; Read HI byte

; of TABLATH

TABLRD 0, 1, INDF0 ; Read LO byte

; of TABLATL and

; Update TABLATH

; Increment TBLPTR

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

AD15:AD0

Instruction

Fetched

Instruction

Executed

ALE

TABLRD INST (PC+ 1) INST (PC+2)

INST (PC-1) TABLRD cycle1 TABLRD cycle2 INST (PC+1)

Data read cycle

PC PC+1 TBL Data in PC+2

’1’

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

AD15:AD0

Instruction

Fetched

Instruction

Executed

TABLRD1 TABLRD2 INST (PC+2) INST (PC+3)

INST (PC+2)

ALE

INST (PC-1) TABLRD1 cycle1 TABLRD1 cycle2 TABLRD2 cycle1 TABLRD2 cyc le2

Data read cycle Data read cycle

’1’

PC PC+1 PC+2 PC+3

TBL1 D ata in 1 TB L2 Data in 2

 2000 Microchip Technology Inc. DS30289B-page 65

PIC17C7XX

8.4 Operation with Exter nal Memory

Interface

When the table reads/writes are accessing external

memory (via the external system interface bus), the

tabl e latch for the t abl e rea ds is d if f eren t from the t abl e

latch for the table writes (see Figure 8-9).

This means that you cannot do a TABLRD instruction,

and use the values that were loaded into the table

latches for a TABLWT instruction. Any table write

sequence should use both the TLWT and then the

TABLWT instructions.

FIGURE 8-9: ACCESSING EXTERNAL MEMORY WITH TABLRD AND TABLWT INSTRUCTIONS

TABLPTR

TABLATH (for Table Reads)

TABLATH (for Table Wr ites )

Progra m Me mor y

TABLRD

TABLWT

(In External Memory Space)

PIC17C7XX

DS30289B-page 66  2000 Microchip Technology Inc.

NOTES:

 2000 Microchip Technology Inc. DS30289B-page 67

PIC17C7XX

9.0 HARDWARE MULTIPLIER

All PI C17 C7 XX de vice s ha ve an 8 x 8 ha rd ware mu lti -

plier included in the ALU of the device. By making the

multiply a hardware operation, it completes in a single

instruc tion cycle. This is an unsigned multip ly that gives

a 16-bit result. The result is stored into the 16-bit

Product register (PRODH:PRODL). The multiplier does

not affect any flags in the ALUSTA register.

Making the 8 x 8 multiplier execute in a single cycle

gives the fol low i ng adv antages:

•Higher computational throughput

•Reduc es c od e si ze requirements for mu ltiply alg o-

rithms

The performance increase allows the device to be used

in applications previously reserved for Digital Signal

Processors.

Table 9-1 shows a performance comparison between

PIC17CXXX devices using the single cycle hardware

multiply and performing the same function without the

hardware multiply.

Example 9-1 shows the sequence to do an 8 x 8

unsigned multiply. Only one instruction is required

when one arg um ent of the multiply is al rea dy lo ade d in

the WREG register.

Example 9-2 shows the sequence t o do an 8 x 8 signed

multiply. To account for the sign bits of the arguments,

each argument’s most significant bit (MSb) is tested

and the appropriate subtractions are done.

EXAMPLE 9- 1: 8 x 8 UNSIGNED

MULTIPLY ROUTINE

EXAMPLE 9-2: 8 x 8 SIGNED MULTIPLY

ROUTINE

TABLE 9-1: PERFORMANCE COMPARISON

MOVFP ARG1, WREG ;

MULWF ARG2 ; ARG1 * ARG2 ->

; PRODH:PRODL

MOVFP ARG1, WREG

MULWF ARG2 ; ARG1 * ARG2 ->

; PRODH:PRODL

BTFSC ARG2, SB ; Test Sign Bit

SUBWF PRODH, F ; PRODH = PRODH

; - ARG1

MOVFP ARG2, WREG

BTFSC ARG1, SB ; Test Sign Bit

SUBWF PRODH, F ; PRODH = PRODH

; - ARG2

Routine Mult iply Me thod Program

Memory

(Words)

Cycles

(Max)

Time

@ 33 MHz @ 16 MHz @ 8 MHz

8 x 8 unsigned Without hardware multiply 13 69 8.364 µs17.25 µs 34.50 µs

Hardware multiply 1 1 0.121 µs0.25 µs0.50 µs

8 x 8 si gned Without hardwar e multiply —————

Hardware multiply 6 6 0.727 µs1.50 µs3.0 µs

16 x 16 unsigned Without hardware multiply 21 242 29.333 µs60.50 µs 121.0 µs

Hardware multiply 24 24 2.91 µs6.0 µs 12.0 µs

16 x 16 signed Without hardware multiply 52 254 30.788 µs63.50 µs 127.0 µs

Hardware multiply 36 36 4.36 µs9.0 µs 18.0 µs

PIC17C7XX

DS30289B-page 68  2000 Microchip Technology Inc.

Example 9-3 shows the sequence to do a 16 x 16

unsigned multiply. Equation 9-1 shows the algorithm

that is used. The 32-bit result is stored in 4 registers,

RES3:RES0.

EQUATION 9-1: 16 x 16 UNSIGNED

MULTIPLICATION

ALGORITHM

EXAMPLE 9-3: 16 x 16 UNSIGNED

MU LTIPLY ROUTINE

RES3:RES0 = ARG1H:ARG1L • ARG2H:ARG2L

= (ARG1H • ARG2H • 216)+

(ARG1H • ARG2L • 28)+

(ARG1L • ARG2H • 28)+

(ARG1L • ARG2L)

MOVFP ARG1L, WREG

MULWF ARG2L ; ARG1L * ARG2L ->

; PRODH:PRODL

MOVPF PRODH, RES1 ;

MOVPF PRODL, RES0 ;

;

MOVFP ARG1H, WREG

MULWF ARG2H ; ARG1H * ARG2H ->

; PRODH:PRODL

MOVPF PRODH, RES3 ;

MOVPF PRODL, RES2 ;

;

MOVFP ARG1L, WREG

MULWF ARG2H ; ARG1L * ARG2H ->

; PRODH:PRODL

MOVFP PRODL, WREG ;

ADDWF RES1, F ; Add cross

MOVFP PRODH, WREG ; products

ADDWFC RES2, F ;

CLRF WREG, F ;

ADDWFC RES3, F ;

;

MOVFP ARG1H, WREG ;

MULWF ARG2L ; ARG1H * ARG2L ->

; PRODH:PRODL

MOVFP PRODL, WREG ;

ADDWF RES1, F ; Add cross

MOVFP PRODH, WREG ; products

ADDWFC RES2, F ;

CLRF WREG, F ;

ADDWFC RES3, F ;

 2000 Microchip Technology Inc. DS30289B-page 69

PIC17C7XX

Example 9-4 shows the sequence to do a 16 x 16

signed multiply. Equation 9-2 shows the algorithm

used. The 32-bit result is stored in four registers,

RES3:RES0. To account for the sign bits of the argu-

ments, e ach a rgume nt pai rs most sign if icant bit ( MSb)

is tested and the appropriate subtractions are done.

EQUATION 9-2: 16 x 16 SIGNED

MULTIPLICATION

ALGORITHM

EXAMPLE 9-4: 16 x 16 SIGNED

MULTIPLY ROUTINE

RES3:RES0

= ARG1H:ARG1L • ARG2H:ARG2L

= (ARG1H • ARG2H • 216)+

(ARG1H • ARG2L • 28)+

(ARG1L • ARG2H • 28)+

(ARG1L • ARG2L ) +

(-1 • ARG2H<7> • ARG1H:ARG1L • 216)+

(-1 • ARG1H<7> • ARG2H:ARG2L • 216)

MOVFP ARG1L, WREG

MULWF ARG2L ; ARG1L * ARG2L ->

; PRODH:PRODL

MOVPF PRODH, RES1 ;

MOVPF PRODL, RES0 ;

;

MOVFP ARG1H, WREG

MULWF ARG2H ; ARG1H * ARG2H ->

; PRODH:PRODL

MOVPF PRODH, RES3 ;

MOVPF PRODL, RES2 ;

;

MOVFP ARG1L, WREG

MULWF ARG2H ; ARG1L * ARG2H ->

; PRODH:PRODL

MOVFP PRODL, WREG ;

ADDWF RES1, F ; Add cross

MOVFP PRODH, WREG ; products

ADDWFC RES2, F ;

CLRF WREG, F ;

ADDWFC RES3, F ;

;

MOVFP ARG1H, WREG ;

MULWF ARG2L ; ARG1H * ARG2L ->

; PRODH:PRODL

MOVFP PRODL, WREG ;

ADDWF RES1, F ; Add cross

MOVFP PRODH, WREG ; products

ADDWFC RES2, F ;

CLRF WREG, F ;

ADDWFC RES3, F ;

;

BTFSS ARG2H, 7 ; ARG2H:ARG2L neg?

GOTO SIGN_ARG1 ; no, check ARG1

MOVFP ARG1L, WREG ;

SUBWF RES2 ;

MOVFP ARG1H, WREG ;

SUBWFB RES3

;

SIGN_ARG1

BTFSS ARG1H, 7 ; ARG1H:ARG1L neg?

GOTO CONT_CODE ; no, done

MOVFP ARG2L, WREG ;

SUBWF RES2 ;

MOVFP ARG2H, WREG ;

SUBWFB RES3

;

CONT_CODE

PIC17C7XX

DS30289B-page 70  2000 Microchip Technology Inc.

NOTES:

 2000 Microchip Technology Inc. DS30289B-page 71

PIC17C7XX

10.0 I/O PORTS

PIC17C75X devices have seven I/O ports, PORTA

through PORTG. PIC17C76X devices have nine I/O

ports, PORTA through PORTJ. PORTB through

PORTJ have a corresponding Data Direction Register

(DDR), which is used to configure the port pins as

inputs or outputs. Some of these ports pins are multi-

plexed with alternate functions.

PORT C, PORTD, and POR TE are multip lexed wit h the

system bus. These pins are configured as the system

bus w hen the dev ice’s configuration bits are selected to

Microprocessor or Extended Microcontroller mode s. In

the two other microcontroller modes, these pins are

general purpose I/O.

PORTA, PORTB, PORTE<3>, PORTF, PORTG and

the upper four bits of PORTH are multiplexed with the

periphera l features of the devi ce. These periph eral fea-

tures are:

•Timer Modules

•Capture Modules

•PWM Modules

•USART/SCI Modules

•SSP Module

•A/D Modul e

•External Inte rrup t pin

When so me of these p eripheral m odules are t urned on,

the port pi n w il l au tom at ica ll y c onfigure to the alte rna t e

function. The modules that do this are:

•PWM Mo dule

•SSP Module

•USART/SCI Module

When a pin is auto mat ically c onf igured a s an outp ut by

a peripheral module, the pins data direction (DDR) bit

is unknown. After disabling the peripheral module, the

user should re-initialize the DDR bit to the desired con-

figuration.

The other peripheral modules (which require an input)

must h av e th ei r da ta direction bi t s c onfi gu r ed app rop ri-

ately.

When the device enters the “RESET state”, the Data

Direction registers (DDR) are forced set, which will

make the I/O hi-impe dance input s. The RESET sta te of

some peripheral modules may force the I/O to other

operations, such as analog inputs or the system bus.

Note: A pin tha t is a periph eral input, can b e con-

figured as an output (DDRx<y> is cle ared).

The peripheral events will be determined

by the action out put on the port pin .

PIC17C7XX

DS30289B-page 72  2000 Microchip Technology Inc.

10.1 PORTA Register

PORTA is a 6-bit wide latch. PORTA does not have a

corresponding Data Direction Register (DDR). Upon a

device RESET, the PORTA pins are forced to be hi-

impedance inputs. For the RA4 and RA5 pins, the

peripheral module controls the output. When a device

RESET occurs, the peripheral module is disabled, so

these pins are forced to be hi-impedance inputs.

Reading PORTA reads the status of the pins.

The RA0 pin is multiplexed with the external interrupt,

INT. The RA1 p in is mu ltiple xed wi th T MR0 cl ock i nput,

RA2 and RA3 are multiplexed with the SSP functions,

and RA4 and RA5 are multiplexed with the USART1

functions. The control of RA2, RA3, RA4 and RA5 as

outputs, is automatically configured by their multi-

plexed peripheral module when the module is enabled.

10.1.1 USING RA2, RA3 AS OUTPUTS

The RA2 and RA3 pins are open drain outputs. To use

the RA2 and/or the RA3 pin(s) as output(s), simply

write to the PO R TA register the de si red v al ue. A ’0’ will

cause the pin to drive low, while a ’1’ will cause the pin

to float (hi-impedance). An external pull-up resistor

should be used to pull the pin high. Writes to the RA2

and RA3 pins will not affect the other PORTA pins.

Example 10-1 shows a n instruc tio n s equence to initia l-

ize PORTA. The Bank Select Register (BSR) must be

select ed to Bank 0 fo r the po rt to be initia liz ed . Th e fol-

lowing example uses the MOVLB instruction to load the

BSR r egister for bank selection.

EXAMPLE 10-1: INITIALIZING PORTA

FIGURE 10-1: RA0 AND RA1 BLOCK

DIAGRAM

FIGURE 10-2: RA2 BLOCK DIAGRAM

Note: When using the RA2 or RA3 pin(s) as out-

put(s), read-modify-write instructions (such

as BCF, BSF, BTG) on PORTA are not

recommended.

Such operations read the port pins, do the

desired operatio n, and then write this value

to the data latch. This may inadvertently

cause the RA2 or RA3 pins to switch from

input to output (or vice-versa).

To avoid this po ssib ility, use a sha dow reg-

ister for PORTA. Do the bit operations on

this shadow register and then move it to

PORTA.

MOVLB 0 ; Select Bank 0

MOVLW 0xF3 ;

MOVWF PORTA ; Initialize PORTA

; RA<3:2> are output low

; RA<5:4> and RA<1:0>

; are inputs

; (outputs floating)

Note: Input pins have protection diodes to VDD and VSS.

Data Bus

RD_PORTA

(Q2)

Note: I/O pin has protection diodes to VSS.

Data Bus

WR_PORTA

(Q4)

QCK

RD_PORTA

(Q2)

Peripheral Data In

I2C Mode Enable

SCL Out

 2000 Microchip Technology Inc. DS30289B-page 73

PIC17C7XX

FIGURE 10-3: RA3 BLOCK DIAGRAM FIGURE 10-4: RA4 AND RA5 BLOCK

DIAGRAM

TABLE 10-1: PORTA FUNCTIONS

TABLE 10-2: REGISTERS/BITS ASSOCIATED WITH PORTA

Note: I/O pin has protection diodes to VSS.

Data Bus

WR_PORTA

(Q4)

QCK

RD_PORTA

(Q2)

Peripheral Data In

SDA Out

SSP Mode

’1’

Note: I/O pins have protection diodes to VDD and VSS.

Data Bus

RD_PORTA

(Q2)

Serial Port Output Signals

Serial Port Input Signal

OE = SPEN,SY N C, TXEN, C REN, SREN for RA 4

OE = SPEN (SYNC +S YNC, CSRC) for RA5

Name Bit0 Buffer Type Function

RA0/ INT bit0 S T Input or exte rnal interrupt input.

RA1/T0CKI bit1 ST Input or clock input to the TMR0 timer/counter and/or an external interrupt

input.

RA2/SS/SCL bit2 ST Input/output or slave select input for the SPI, or clock input for the I2C bus.

Output is open drain type.

RA3/SDI/SDA bit3 ST Input/output or data input for the SPI, or data for the I2C bus.

Output is open drain type.

RA4/RX1/DT1 bit4 ST Input or USART1 Asynchronous Receive input, or

USART1 Synchronous Data input/output.

RA5/TX1/CK1 bit5 ST Input or USART1 Asynchronous Transmit output, or

USART1 Synchronous Clock input/output.

RBPU bit7 —Control bit for PORTB weak pull-ups.

Legend: ST = Schmitt Trigger input

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on

POR,

BOR MCLR, WDT

10h, Bank 0 PO RTA (1) RBPU —RA5/

TX1/CK1 RA4/

RX1/DT1 RA3/

SDI/SDA RA2/

SS/SCL RA1/T0CKI RA0/INT 0-xx 11xx 0-uu 11uu

05h, Unba nke d T0STA INTEDG T 0S E T0CS T0PS3 T0PS2 T0PS1 T0PS0 —0000 000- 0000 000-

13h, Bank 0 RCSTA1 SPEN RX9 SREN CREN —FERR OERR RX9D 0000 -00x 0000 -00u

15h, Bank 0 TXS TA1 CSR C TX9 TXEN SYNC — — TRMT TX9D 0000 --1x 0000 --1u

Legend: x = unknown, u = unchanged, - = unimplemented, reads as '0'. Shaded cells are not used by PORTA.

Note 1: On any device RESET, these pins are configured as inputs.

PIC17C7XX

DS30289B-page 74  2000 Microchip Technology Inc.

10.2 PORTB and DDRB Registers

PORTB is an 8-bit wide, bi-directional port. The corre-

sponding data direction register is DDRB. A ’1’ in DDRB

configu r es the c orre sp ond ing port pin as an in put. A ’0’

in the DDRB register configures the corre sponding port

pin as an output. Reading PORTB reads the status of

the pins, whereas writing to POR TB will write to the port

latch.

Each of th e POR TB pins has a we ak inte rnal pul l-up. A

single control bit can turn on all the pull-ups. This is

done by c learing the RBPU (PORTA<7>) bit. The weak

pull-up is automatically turned off when the port pin is

configured as an output. The pull-ups are enabled on

any RESET.

PORTB also has an interrupt-on-change feature. Only

pins configured as inputs can cause this interrupt to

occur (i.e ., any RB7: RB0 pin config ured as an out put is

excluded from the interrupt-on-change comparison).

The input pins (of RB7:RB0) are compared with the

value i n the POR TB data latc h. The “mismatch” output s

of RB7:RB0 are OR’d together to se t the PORTB In ter-

rupt Flag bit, RBIF (PIR1<7>).

This interrupt can wake the device from SLEEP. The

user, in the Interrupt Service Routine, can clear the

interrupt by :

a) Read-Write PORTB (such as: MOVPF PORTB,

PORTB). This will end the mismatch condition.

b) Then, clear the RBIF bit.

A mismatch condition will continue to set the RBIF bit.

Reading, then writing PORTB, will end the mismatch

condition and allow the RBIF bit to be cleared.

This interrupt-on-mismatch feature, together with soft-

ware configurable pull-ups on this port, allows easy

interface to a keypad and makes it possible for wake-

up on key depression. For an example, refer to Appli-

cation Note AN552, “Implementing Wake-up on

Keystroke.”

The interrupt-on-change feature is recommended for

wake-up on operati ons , w here PORTB is only used f or

the interrupt-on-change feature and key depression

operations.

FIGURE 10-5: BLOCK DIAGRAM OF RB5:RB4 AND RB1:RB0 PORT PINS

Note: On a device RESET, the RBIF bit is inde-

terminate, since the value in the latch may

be different than the pin.

Note: I/O pins have protection diodes to VDD and VSS.

Data Bus

Weak

Pull-up

Port

Input Latch

Port

Data

WR_PORTB (Q4)

WR_DDRB (Q4)

RD_PORTB ( Q2)

RD_DDRB (Q2)

RBIF

RBPU

Match Signal

from other

port pins

(PORTA<7>)

Peripheral Data In

 2000 Microchip Technology Inc. DS30289B-page 75

PIC17C7XX

Exampl e 10-2 s hows a n i ns truc tio n s eq uence to ini t ia l-

ize PORTB. The Bank Select Register (BSR) must be

select ed t o Bank 0 fo r the po rt to be ini tia liz ed . Th e fol-

lowing example uses the MOVLB instruction to load the

BSR register for bank selection.

EXAMPLE 10-2: INITIALIZING PORTB

FIGURE 10-6: BLOCK DIAGRAM OF RB3:RB2 PORT PINS

MOVLB 0 ; Select Bank 0

CLRF PORTB, F ; Init PORTB by clearing

; output data latches

MOVLW 0xCF ; Value used to initialize

; data direction

MOVWF DDRB ; Set RB<3:0> as inputs

; RB<5:4> as outputs

; RB<7:6> as inputs

Note: I/O pins have protection diodes to VDD and VSS.

Data Bus

Weak

Pull-up

Port

Input Latch

Port

Data

Peripheral_enable

Peripheral_output

WR_PORTB (Q4)

WR_DDRB (Q4)

RD_PORTB (Q2)

RD_DDRB (Q2)

RBIF

RBPU

Match Signal

from other

port pins

(PORTA<7>)

Peripheral Data In

PIC17C7XX

DS30289B-page 76  2000 Microchip Technology Inc.

FIGURE 10-7: BLOCK DIAGRAM OF RB6 PORT PIN

FIGURE 10-8: BLOCK DIAGRAM OF RB7 PORT PIN

Note: I/O pin has protection diodes to Vdd and Vss .

Data Bus

Weak

Pull-up

Port

Data

SPI Output Enab l e

SPI Output

WR_PORTB (Q4)

WR_DDRB (Q4)

RD_PORTB ( Q2)

RD_DDRB (Q2)

RBIF

RBPU

Match Signal

from other

port pins

(PORTA<7>)

Periphe ra l Data In

Note: I/O pin has protection diod es to VDD and VSS.

Data Bus

Weak

Pull-up

Port

Data

SPI Output Enab l e

SPI Output

WR_PORTB (Q4)

WR_DDRB (Q4)

RD_PORTB (Q2)

RD_DDRB (Q2)

RBIF

RBPU

Match Signal

from other

port pins

(PORTA<7>)

Peripheral Data In

SS Output Disabl e

 2000 Microchip Technology Inc. DS30289B-page 77

PIC17C7XX

TABLE 10-3: PORTB FUNCTIONS

TABLE 10-4: REGISTERS/BITS ASSOCIATED WITH PORTB

Name Bit Buffer Type Function

RB0/CAP1 bit0 ST Input/output or the Capture1 input pin. Software programmable weak

pull-up and interrupt-on-change features.

RB1/CAP2 bit1 ST Input/output or the Capture2 input pin. Software programmable weak

pull-up and interrupt-on-change features.

RB2/PWM 1 bit2 ST Input/output or th e PWM1 output pin. Sof twa re programm able wea k pull-u p

and interrupt-on-change features.

RB3/PWM 2 bit3 ST Input/output or th e PWM2 output pin. Sof twa re programm able wea k pull-u p

and interrupt-on-change features.

RB4/TCLK12 bit4 ST Input/output or the external clock input to Timer1 and Timer2. Software

programmable weak pull-up and interrupt-on-change features.

RB5/TCLK3 bit5 ST Input/output or the external clock input to Timer3. Software programmable

weak pull-up and interrupt-on-change features.

RB6/SCK bit6 ST Input/output or the M as ter/Sl ave clo ck for the SPI. Software progra mm able

weak pull-up and interrupt-on-change features.

RB7/SDO bit7 ST Input/output or data output for the SPI. Software programmable weak

pull-up and interrupt-on-change features.

Legend: ST = Schmitt Trigger input

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on

POR,

BOR

MCLR,

WDT

12h, Bank 0 PORTB RB7/

SDO RB6/

SCK RB5/

TCLK3 RB4/

TCLK12 RB3/

PWM2 RB2/

PWM1 RB1/

CAP2 RB0/

CAP1 xxxx xxxx uuuu uuuu

11h, Bank 0 DDRB Data Direction Register for PORTB 1111 1111 1111 1111

10h, Bank 0 PORTA RBPU —RA5/

TX1/CK1 RA4/

RX1/DT1 RA3/

SDI/SDA RA2/

SS/SCL RA1/T0CKI RA0/INT 0-xx 11xx 0-uu 11uu

06h, Unba nke d CPU STA — — STKAV GLINTD TO PD POR BOR --11 11qq --11 qquu

07h, Unba nke d IN TS TA PEIF T0CKIF T0IF INTF PEIE T0CKIE T0IE INTE 0000 0000 0000 0000

16h, Bank 1 PIR1 RBIF TMR3IF TMR2IF TMR1IF CA2IF CA1IF TX1IF RC1IF x000 0010 u000 0010

17h, Bank 1 PIE1 RB IE TMR3IE TMR2IE TMR1IE CA2IE CA1IE TX1IE RC1IE 0000 0000 0000 0000

16h, Bank 3 TCON1 CA2ED1 CA2ED0 CA1ED1 CA1ED0 T16 TMR3CS TMR2CS TMR1CS 0000 0000 0000 0000

17h, Bank 3 TCON2 CA2OVF CA1OVF PWM2ON PWM1ON CA1/PR3 TMR3ON TMR2ON TMR1ON 0000 0000 0000 0000

Legend: x = unknown, u = unchanged, - = unimplemented, read as ’0’, q = value depends on condition. Shaded cells are not used by PORTB.

PIC17C7XX

DS30289B-page 78  2000 Microchip Technology Inc.

10.3 PORTC and DDRC Registers

PORTC is an 8-bit bi-directional port. The correspond-

ing data direction register is DDRC. A ’1’ in DDRC con-

figures the corresponding port pin as an input. A ’0’ in

the DDRC register configures the corresponding port

pin as an output. Reading PORTC reads the status of

the pins, whereas writi ng to PORTC will writ e to the port

latch. PORTC is multiplexed with the system bus.

When op er a tin g as t h e s ys tem bus, P ORTC i s th e l o w

order byt e of the address/data bus (AD7:AD0). The tim-

ing for the sys tem bus is show n in the Elect ric al Speci-

fications section.

Example 10-3 shows a n instruc tio n s equence to initia l-

ize PORTC. The Bank Select Register (BSR) must be

select ed to Bank 1 fo r the po rt to be initia liz ed . Th e fol-

lowing example uses the MOVLB instruction to load the

BSR r egister for bank selection.

EXAMPLE 10-3: INITIALIZING PORTC

FIGURE 10-9: BLOCK DIAGRAM OF RC7:RC0 PORT PINS

Note: This port is configured as the system bus

when the device’s configuration bits are

selected to Microprocessor or Extended

Microcontroller modes. In the two other

microcontroller modes, this port is a

general purpose I/O.

MOVLB 1 ; Select Bank 1

CLRF PORTC, F ; Initialize PORTC data

; latches before setting

; the data direction reg

MOVLW 0xCF ; Value used to initialize

; data direction

MOVWF DDRC ; Set RC<3:0> as inputs

; RC<5:4> as outputs

; RC<7:6> as inputs

Note: I/O pins have protection diodes to VDD and VSS.

TTL

Input

Buffer

Port

Data

To D_Bus → IR

INSTRUCTION READ

Data Bus

RD_PORTC

WR_PORTC

RD_DDRC

WR_DDRC

EX_EN

DATA/ADDR_OUT

DRV_SYS System Bus

Control

 2000 Microchip Technology Inc. DS30289B-page 79

PIC17C7XX

TABLE 10-5: PORTC FUNCTIONS

TABLE 10-6: REGISTERS/BITS ASSOCIATED WITH PORTC

Name Bit Buffer Type Function

RC0/AD0 bit0 TTL Input/output or system bus address/data pin.

RC1/AD1 bit1 TTL Input/output or system bus address/data pin.

RC2/AD2 bit2 TTL Input/output or system bus address/data pin.

RC3/AD3 bit3 TTL Input/output or system bus address/data pin.

RC4/AD4 bit4 TTL Input/output or system bus address/data pin.

RC5/AD5 bit5 TTL Input/output or system bus address/data pin.

RC6/AD6 bit6 TTL Input/output or system bus address/data pin.

RC7/AD7 bit7 TTL Input/output or system bus address/data pin.

Legend: TTL = TTL input

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value o n

POR,

BOR

MCLR,

WDT

11h, Bank 1 PORTC RC7/

AD7 RC6/

AD6 RC5/

AD5 RC4/

AD4 RC3/

AD3 RC2/

AD2 RC1/

AD1 RC0/

AD0 xxxx xxxx uuuu uuuu

10h, Bank 1 DDRC Data Direction Register for PORTC 1111 1111 1111 1111

Legend: x = unknown, u = unchanged

PIC17C7XX

DS30289B-page 80  2000 Microchip Technology Inc.

10.4 PORTD and DDRD Registers

PORTD is an 8-bit bi-directional port. The correspond-

ing data direction register is DDRD. A ’1’ in DDRD con-

figures the corresponding port pin as an input. A ’0’ in

the DDRD register configures the corresponding port

pin as an output. Reading PORTD reads the status of

the pins, whereas writi ng to PORTD will writ e to the port

latch. PORTD is multiplexed with the system bus.

When ope rati ng as the syst em bus , POR T D is the high

order byte of the address/data bus (AD15:AD8). The

timing for the system bus is shown in the Electrical

Specifications section.

Example 10-4 shows a n instruc tio n s equence to initia l-

ize PORTD. The Bank Select Register (BSR) must be

select ed to Bank 1 fo r the po rt to be initia liz ed . Th e fol-

lowing example uses the MOVLB instruction to load the

BSR r egister for bank selection.

EXAMPLE 10-4: INITIALIZING PORTD

FIGURE 10-10: BLOCK DIAGRAM OF RD7:RD0 PORT PINS (IN I/O PORT MODE)

Note: This port is configured as the system bus

when the device’s configuration bits are

selected to Microprocessor or Extended

Microcontroller modes. In the two other

microcontroller modes, this port is a gen-

eral purpos e I/O.

MOVLB 1 ; Select Bank 1

CLRF PORTD, F ; Initialize PORTD data

; latches before setting

; the data direction reg

MOVLW 0xCF ; Value used to initialize

; data direction

MOVWF DDRD ; Set RD<3:0> as inputs

; RD<5:4> as outputs

; RD<7:6> as inputs

Note: I/O pins have protection diodes to VDD and VSS.

TTL

Input

Buffer

Port

Data

To D_Bus → IR

INSTRUCTION READ

Data Bus

RD_PORTD

WR_PORTD

RD_DDRD

WR_DDRD

EX_EN

DATA/ADDR_OUT

DRV_SYS System Bus

Control

 2000 Microchip Technology Inc. DS30289B-page 81

PIC17C7XX

TABLE 10-7: PORTD FUNCTIONS

TABLE 10-8: REGISTERS/BITS ASSOCIATED WITH PORTD

Name Bit Buffer Type Function

RD0/AD8 bit0 TTL Input/output or system bus address/data pin.

RD1/AD9 bit1 TTL Input/output or system bus address/data pin.

RD2/AD10 bit2 TTL Input/output or system bus address/data pin.

RD3/AD11 bit3 TTL Input/output or system bus address/data pin.

RD4/AD12 bit4 TTL Input/output or system bus address/data pin.

RD5/AD13 bit5 TTL Input/output or system bus address/data pin.

RD6/AD14 bit6 TTL Input/output or system bus address/data pin.

RD7/AD15 bit7 TTL Input/output or system bus address/data pin.

Legend: TTL = TTL input

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on

POR,

BOR

MCLR,

WDT

13h, Bank 1 PORTD RD7/

AD15 RD6/

AD14 RD5/

AD13 RD4/

AD12 RD3/

AD11 RD2/

AD10 RD1/

AD9 RD0/

AD8 xxxx xxxx uuuu uuuu

12h, Bank 1 DDRD Data Direction Register for PORTD 1111 1111 1111 1111

Legend: x = unknown, u = unchanged

PIC17C7XX

DS30289B-page 82  2000 Microchip Technology Inc.

10.5 PORTE and DDRE Register

PORT E is a 4-bi t bi-direc tional po rt. The co rrespondin g

data direction register is DDRE. A ’1’ in DD RE con fig-

ures the correspon din g p ort p in as an i nput. A ’0’ in the

DDRE register configures the corresponding port pin

as an output. Reading PORTE reads the status of the

pins, whereas writing to PORTE will write to the port

latch. PORTE is multiplexed with the system bus.

When operating as the system bus, PORTE contains

the control signals for the address/data bus

(AD15:AD0). These control signals are Address Latch

Enable (ALE), Output Enable (OE) and Write (WR).

The control signals OE and WR are active low signals.

The tim ing f or t he sys tem b us is sho wn i n the Electr ical

Specifications section.

Example 10-5 shows a n instruc tio n s equence to initia l-

ize PORT E. The Bank Select Register (BSR) must be

select ed to Bank 1 fo r the po rt to be initia liz ed . Th e fol-

lowing example uses the MOVLB instruction to load the

BSR r egister for bank selection.

EXAMPLE 10-5: INITIALIZING PORTE

FIGURE 10-11: BLOCK DIAGRAM OF RE2:RE0 (IN I/O PORT MODE)

Note: Three pins of this port are configured as

the sys tem bu s wh en the dev ic e’s configu-

ration bits are selected to Microprocessor

or Extended Microcontroller modes. The

other pin is a general purpose I/O or

Capture4 pin. In the two other micro-

controller modes, RE2:RE0 are general

purpose I /O pins.

MOVLB 1 ; Select Bank 1

CLRF PORTE, F ; Initialize PORTE data

; latches before setting

; the data direction

; register

MOVLW 0x03 ; Value used to initialize

; data direction

MOVWF DDRE ; Set RE<1:0> as inputs

; RE<3:2> as outputs

; RE<7:4> are always

; read as ’0’

Note: I/O pins have protection diodes to VDD and VSS.

TTL

Input

Buffer

Port

Data

Data Bus

RD_PORTE

WR_PORTE

RD_DDRE

WR_DDRE

EX_EN

CNTL

DRV_SYS System Bus

Control

 2000 Microchip Technology Inc. DS30289B-page 83

PIC17C7XX

FIGURE 10-12: BLOCK DIAGRAM OF RE3/CAP4 PORT PIN

TABLE 10-9: PORTE FUNCTIONS

TABLE 10-10: REGISTERS/BITS ASSOCIATED WITH PORTE

Note: I/O pin has protection diodes to VDD and VSS.

Port

Data

Data Bus

RD_PORTE

WR_PORTE

RD_DDRE

WR_DDRE

Peripheral In

VDD

Name Bit Buffer Type Function

RE0/ALE bit0 TTL Input/output or system bus Address Latch Enable (ALE) control pin.

RE1/OE bit1 TTL Input/output or system bus Output Enable (OE) control pin.

RE2/WR bit2 TTL Input/output or system bus Write (WR) control pin.

RE3/CAP4 bit3 ST Input/output or Capture4 input pin.

Legend: TTL = TTL input, ST = Schmitt Trigger input

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on

POR,

BOR MCLR, W DT

15h, Bank 1 PORTE — — — — RE3/CAP4 RE2/WR RE1/OE RE0/ALE ---- xxxx ---- uuuu

14h, Bank 1 DDRE Data Direction Register for PORTE ---- 1111 ---- 1111

14h, Bank 7 CA 4L Ca ptu re4 Low Byte xxxx xxxx uuuu uuuu

15h, Bank 7 CA 4H C a ptu re4 High Byte xxxx xxxx uuuu uuuu

16h, Bank 7 T CON3 —CA4OVFCA3OVF CA4ED1 CA4ED0 CA3ED1 CA3ED0 PWM3ON -000 0000 -000 0000

Legend: x = unknown, u = unchanged, - = unimplemented, read as '0'. Shaded cells are not used by PORTE.

PIC17C7XX

DS30289B-page 84  2000 Microchip Technology Inc.

10.6 PORTF and DDRF Registers

PORTF is an 8-bit wide bi-directional port. The corre-

sponding data direction register is DDRF. A ’1’ in DDRF

configu r es the c orre sp ond ing port pin as an in put. A ’0’

in the D DRF registe r configure s the correspo nding port

pin as an output. Reading PORTF reads the status of

the pins, whereas writing to PORTF will write to the

respective port latch.

All eight bits of POR TF are multi plexed w ith 8 chan nels

of the 10-bit A/D converter.

Upon RESET, the entire Port is automatically config-

ured as analog inputs and must be configured in soft-

ware to be a digital I/O.

Example 10-6 shows a n instruc tio n s equence to initia l-

ize PORTF. The Bank Select Register (BSR) must be

select ed to Bank 5 fo r the po rt to be initia liz ed . Th e fol-

lowing example uses the MOVLB instruction to load the

BSR r egister for bank selection.

EXAMPLE 10-6: INITIALIZING PORTF

FIGURE 10-13: BLOCK DIAGRAM OF RF7:RF0

MOVLB 5 ; Select Bank 5

MOVWF 0x0E ; Configure PORTF as

MOVWF ADCON1 ; Digital

CLRF PORTF, F ; Initialize PORTF data

; latches before

; the data direction

; register

MOVLW 0x03 ; Value used to init

; data direction

MOVWF DDRF ; Set RF<1:0> as inputs

; RF<7:2> as outputs

Data Bus

WR PORTF

WR DDRF

RD PORTF

Data Latch

DDRF Latch

VSS

I/O pin

PCFG3:PCFG0

QCK

Input

Buffer

VDD

RD DDRF

To other pads

VAIN

CHS3:CHS0 To other pads

Note: I/O pins have protection diodes to VDD and VSS.

 2000 Microchip Technology Inc. DS30289B-page 85

PIC17C7XX

TABLE 10-11: PORTF FUNCTIONS

TABLE 10-12: REGISTERS/BITS ASSOCIATED WITH PORTF

Name Bit Buffer Type Function

RF0/AN4 bit0 ST Input/output or analog input 4.

RF1/AN5 bit1 ST Input/output or analog input 5.

RF2/AN6 bit2 ST Input/output or analog input 6.

RF3/AN7 bit3 ST Input/output or analog input 7.

RF4/AN8 bit4 ST Input/output or analog input 8.

RF5/AN9 bit5 ST Input/output or analog input 9.

RF6/AN10 bit6 ST Input/output or analog input 10.

RF7/AN11 bit7 ST Input/output or analog input 11.

Legend: ST = Schmitt Trigger input

Addr e s s Name B it 7 Bit 6 Bi t 5 B it 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on

POR,

BOR

MCLR,

WDT

10h, Bank 5 DDRF D ata Direction Register for PORTF 1111 1111 1111 1111

11h, Bank 5 PORTF RF7/

AN11 RF6/

AN10 RF5/

AN9 RF4/

AN8 RF3/

AN7 RF2/

AN6 RF1/

AN5 RF0/

AN4 0000 0000 0000 0000

15h, Bank 5 ADCON1 ADCS1 ADCS0 ADFM —PCFG3 PCFG2 PCFG1 PCFG0 000- 0000 000- 0000

Legend: x = unknown, u = unchanged, - = unimplem ented, read as '0'. Shaded cells are not used by PORTF.

PIC17C7XX

DS30289B-page 86  2000 Microchip Technology Inc.

10.7 PORTG and DDRG Registers

PORTG is an 8-bit wide, bi-directional port. The corre-

sponding data direction register is DDRG. A ’1’ in

DDRG configures the corresponding port pin as an

input. A ’0’ in the DDRG register configures the corre-

spondi ng port pin as an output. Reading PORT G reads

the status of the pins, whereas writing to PORTG will

write to the port latch.

The low er four b its of PO R TG a re mult iplex ed with fo ur

channels of the 10-bit A/D converter.

The remaining bits of PORTG are multiplexed with

peripheral output and inputs. RG4 is multiplexed with

the CAP3 input, RG5 is multiplexed with the PWM3

output, RG6 and RG7 are multiplexed with the

USART2 functions.

Upon RESET, RG3:RG0 is autom atically configu red as

analog i np uts and m ust be config ured in sof tware to b e

a di gital I/O.

Example 10-7 shows the instru ction s equence t o initial-

ize PORTG. The Bank Select Register (BSR) must be

select ed to Bank 5 fo r the po rt to be initia liz ed . Th e fol-

lowing example uses the MOVLB instruction to load the

BSR r egister for bank selection.

EXAMPLE 10-7: INITIALIZING PORTG

FIGURE 10-14: BLOCK DIAGRAM OF RG3:RG0

MOVLB 5 ; Select Bank 5

MOVLW 0x0E ; Configure PORTG as

MOVPF WREG, ADCON1 ; digital

CLRF PORTG, F ; Initialize PORTG data

; latches before

; the data direction

; register

MOVLW 0x03 ; Value used to init

; data direction

MOVWF DDRG ; Set RG<1:0> as inputs

; RG<7:2> as outputs

Data Bus

WR PORTG

WR DDRG

RD PORTG

Data Latch

DDRG Latch

VSS

I/O pin

PCFG3:PCFG0

QCK

Input

Buffer

VDD

RD DDRG

To other pads

VAIN

CHS3:CHS0 To other pads

Note: I/O pins have protection diodes to VDD and VSS.

 2000 Microchip Technology Inc. DS30289B-page 87

PIC17C7XX

FIGURE 10-15: RG4 BLOCK DIAGRAM

FIGURE 10-16: RG7:RG5 BLOCK DIAGRAM

Note: I/O pins have protection diodes to VDD and VSS.

Data Bus

RD_PORTG

WR_PORTG

RD_DDRG

WR_DDRG

Peripheral Data In

VDD

Note: I/O pins have protection diodes to VDD and VSS.

Port

Data

Data Bus

RD_PORTG

WR_PORTG

RD_DDRG

WR_DDRG

OUTPUT

OUTPUT ENABLE

Peripheral Data In

VDD

PIC17C7XX

DS30289B-page 88  2000 Microchip Technology Inc.

TABLE 10-13: PORTG FUNCTIONS

TABLE 10-14: REGISTERS/BITS ASSOCIATED WITH PORTG

Name Bit Buffer Type Function

RG0/AN3 bit0 ST Input/output or analog input 3.

RG1/AN2 bit1 ST Input/output or analog input 2.

RG2/AN1/VREF- bit2 ST Input/output or analog input 1 or the ground reference voltage.

RG3/AN0/VREF+ bit3 ST Input/output or analog input 0 or the positive reference voltage.

RG4/CAP3 bit4 ST Input/output or the Capture3 input pin.

RG5/PWM3 bit5 ST Input/output or the PWM3 output pin.

RG6/RX2/DT2 bit6 ST Input/output or the USART2 (SCI) Asynchronous Receive or USART2

(SCI) Synchr ono us Dat a .

RG7/TX 2/CK2 b it7 ST Input/output or the USAR T2 (SCI ) Asyn chrono us Transmi t or USAR T2

(SCI) Synchr ono us C lock.

Legend: ST = Schmitt Trigger input

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on

POR,

BOR MCLR, WDT

12h, Bank 5 DDRG Data Direction Register for PORTG 1111 1111 1111 1111

13h, Bank 5 PORTG RG7 /

TX2/CK2 RG6/

RX2/DT2 RG5/

PWM3 RG4/

CAP3 RG3/

AN0 RG2/

AN1 RG1/

AN2 RG0/

AN3 xxxx 0000 uuuu 0000

15h, Bank 5 ADCON1 ADCS1 ADCS0 ADFM —PCFG3 PCFG2 PCFG1 PCFG0 000- 0000 000- 0000

Legend: x = unknown, u = unchanged, - = unimplemented, read as '0'. Shaded cells are not used by PORTG.

 2000 Microchip Technology Inc. DS30289B-page 89

PIC17C7XX

10.8 PORTH and DDRH Registers

(PIC17C76X only)

PORTH is an 8-bit wide, bi-directional port. The corre-

sponding data direction register is DDRH. A ’1’ in

DDRH configures the corresponding port pin as an

input. A ’0’ in the DDRH register configures the corre-

spondi ng port pin as an outpu t. Reading POR TH reads

the status of the pins, whereas writing to PORTH will

write to the respective port latch.

The upper four bits of PORTH are multiplexed with

4 channels of the 10-bit A/D converter.

The remai ning bi ts of PORT H are ge neral pur pose I/O .

Upon RESET, RH7:RH4 are automatically configured

as analo g input s and m ust be co nfigure d in sof twa re to

be a digital I/O.

EXAMPLE 10-8: INITIALIZING PORTH

FIGURE 10-17: BLOCK DIAGRAM OF RH7:RH4

MOVLB 8 ; Select Bank 8

MOVLW 0x0E ; Configure PORTH as

MOVPF ADCON1 ; digital

CLRF PORTH, F ; Initialize PORTH data

; latches before

; the data direction

; register

MOVLW 0x03 ; Value used to init

; data direction

MOVWF DDRH ; Set RH<1:0> as inputs

; RH<7:2> as outputs

Data Bus

WR PORTH

WR DDRH

RD PORT

Data Latch

DDRH Latch

VSS

I/O pin

PCFG3:PCFG0

To other pads

Input

Buffer

VDD

RD DDRH

To other pads

VAIN

CHS3:CHS0

QCK

Note: I/O pins have protection diodes to VDD and VSS.

PIC17C7XX

DS30289B-page 90  2000 Microchip Technology Inc.

FIGURE 10-18: RH3:RH0 BLOCK DIAGRAM

TABLE 10-15: PORTH FUNCTIONS

TABLE 10-16: REGISTERS/BITS ASSOCIATED WITH PORTH

Note: I/O pins have protection diodes to VDD and VSS.

Data Bus

RD_PORTH

WR_PORTH

RD_DDRH

WR_DDRH

VDD

Name Bit Buffer Type Function

RH0 bit0 ST Input/output.

RH1 bit1 ST Input/output.

RH2 bit2 ST Input/output.

RH3 bit3 ST Input/output.

RH4/AN12 bit4 ST Input/output or analog input 12.

RH5/AN13 bit5 ST Input/output or analog input 13.

RH6/AN14 bit6 ST Input/output or analog input 14.

RH7/AN15 bit7 ST Input/output or analog input 15.

Legend: ST = Schmitt Trigger input

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on

POR,

BOR MCLR, WDT

10h, Bank 8 DDRH Data Direction Register for PORTH 1111 1111 1111 1111

11h, Bank 8 PORTH RH7/

AN15 RH6/

AN14 RH5/

AN13 RH4/

AN12 RH3 RH2 RH1 RH0 0000 xxxx 0000 uuuu

15h, Bank 5 AD CON 1 ADCS1 ADCS0 ADFM —PCFG3 PCFG2 PCFG1 PCFG0 000- 0000 000- 0000

Legend: x = unknown, u = unchanged

 2000 Microchip Technology Inc. DS30289B-page 91

PIC17C7XX

10.9 PORTJ and DDRJ Registers

(PIC17C76X only)

PORTJ is an 8-bit wide, bi-directional port. The corre-

spondi ng data dire ction regis ter is DDRJ. A ’1’ in DDRJ

configu r es the c orre sp ond ing port pin as a n in put. A ’0’

in the DDRJ register configures the corresponding port

pin as an output. Reading PORTJ reads the status of

the pins, whereas writing to PORTJ will write to the

respective port latch.

PORTJ is a gen eral purpose I/O por t.

EXAMPLE 10-9: INITIALIZING PORTJ

FIGURE 10-19: PORTJ BLOCK DIAGRAM

MOVLB 8 ; Select Bank 8

CLRF PORTJ, F ; Initialize PORTJ data

; latches before setting

; the data direction

; register

MOVLW 0xCF ; Value used to initialize

; data direction

MOVWF DDRJ ; Set RJ<3:0> as inputs

; RJ<5:4> as outputs

; RJ<7:6> as inputs

Note: I/O pins have protection diodes to VDD and VSS.

Data Bus

RD_PORTJ

WR_PORTJ

RD_DDRJ

WR_DDRJ

VDD

PIC17C7XX

DS30289B-page 92  2000 Microchip Technology Inc.

TABLE 10-17: PORTJ FUNCTIONS

TABLE 10-18: REGISTERS/BITS ASSOCIATED WITH PORTJ

Name Bit Buffer Type Function

RJ0 bit0 ST Input/output

RJ1 bit1 ST Input/output

RJ2 bit2 ST Input/output

RJ3 bit3 ST Input/output

RJ4 bit4 ST Input/output

RJ5 bit5 ST Input/output

RJ6 bit6 ST Input/output

RJ7 bit7 ST Input/output

Legend: ST = Schmitt Trigger input

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on,

POR,

BOR

MCLR,

WDT

12h, Bank 8 DDRJ Data Direction Register for PORTJ 1111 1111 1111 1111

13h, Bank 8 PORTJ RJ7 RJ6 RJ5 RJ4 RJ3 RJ2 RJ1 RJ0 xxxx xxxx uuuu uuuu

Legend: x = unknown, u = unchanged

 2000 Microchip Technology Inc. DS30289B-page 93

PIC17C7XX

10.10 I/O Programming Considerations

10.10.1 BI-DIRECTIONAL I/O PORTS

Any instruction which writes, operates internally as a

read, followed by a write operation. For example, the

BCF and BSF instructions read the register into the

CPU, execute the bit operation and write the result

back to the register. Caution must be used when thes e

instructions are applied to a port with both inputs and

outputs defined. For example, a BSF operation on bit5

of POR TB, will caus e all eight bits of PORTB to be rea d

into the CPU. Then the BSF operation takes place on

bit5 and PORTB is written to the output latches. If

another bit of PORTB is used as a bi- directional I/O pin

(e.g. bit0) and it is defined as an input at this time, the

input si gnal presen t on th e pi n itself wo uld be rea d in to

the CPU and rewri tten to the dat a latch of this p articular

pin, ov erwriting the previous co ntent. As long as the pin

stays in the input mode, no problem occurs. However,

if bit 0 is switch ed into outp ut mode la ter on, the co ntent

of the data latch may now be unknown.

Reading a por t reads the values of the port pins. Writing

to the port register writes the value to the port latch.

When us ing rea d-modi fy-wri te instruc tions (BCF, BSF,

BTG, etc.) on a port, the value of the port pins is read,

the desired operation is performed with this value and

the value is then written to the port latch.

Example 10-10 shows the possible effect of two

sequential read-modify-write instructions on an I/O port.

EXAMPLE 10-10: READ-MODIFY -WRITE

INSTRUCTIONS ON AN

I/O PORT

; Initial PORT settings: PORTB<7:4> Inputs

; PORTB<3:0> Outputs

; PORTB<7:6> have pull-ups and are

; not connected to other circuitry

;

; PORT latch PORT pins

; ---------- ---------

;

BCF PORTB, 7 ; 01pp pppp 11pp pppp

BCF PORTB, 6 ; 10pp pppp 11pp pppp

BCF DDRB, 7 ; 10pp pppp 11pp pppp

BCF DDRB, 6 ; 10pp pppp 10pp pppp

;

; Note that the user may have expected the

; pin values to be 00pp pppp. The 2nd BCF

; caused RB7 to be latched as the pin value

; (High).

Note: A pin actively outputting a Low or High

should not be driven from external devices,

in order to ch ange the level on this pi n (i.e.,

“wired-or”, “wired-and”). The res ul ting hig h

output currents may damage the dev ice.

PIC17C7XX

DS30289B-page 94  2000 Microchip Technology Inc.

10.10.2 SUCCESSIVE OPERATIONS ON I/O

PORTS

The actu al write to an I/O port ha ppens at t he end of a n

instruc tion cycle, whereas for re ading, the d ata mus t be

valid at the beginning of the instruction cycle

(Figure 10-20). Therefore, care must be exercised if a

write followed by a read operation is carried out on the

same I/O port. The sequence of instructions should be

such to allow the pin voltage to stabilize (load depen-

dent) before executing the instruction that reads the

values on tha t I/O po rt. Otherwise, the pre vious sta te of

that pin may be read into the CPU, rather than the

“new” state. When in doubt, it is better to separate

these instructions with a NOP, or another instruction

not accessing this I/O port.

Figure 10-21 shows the I/O model which causes this

situation. As the effective capacitance (C) becomes

larger, the rise/fall time of the I/O pin increases. As the

device frequency increases, or the effective capaci-

tance increases, the possibility of this subsequent

PORTx read-modify-write instruction issue increases.

This effective capacitance includes the effects of the

board traces.

The best w ay to ad dres s this is to add a ser ies res ist or

at the I/O pin. This resistor allows the I/O pin to get to

the desired level before the next instruction.

The use of NOP instructions between the subsequent

PORTx read-modify-write instructions, is a lower cost

solution, but has the issue that the number of NOP

instructions is dependent on the effective capacitance

C and the frequency of the device.

FIGURE 10-20: SUCCESSIVE I/O OPERATION

FIGURE 10-21: I/O CONNECTION ISSUES

PC PC + 1 PC + 2 PC + 3

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

Instruction

Fetched

RB7:RB0

MOVWF PORTB

write to

PORTB NOP

Port pin

sample d here

NOP

MOVF PORTB,W

Instruction

Executed MOVWF PORTB

write to

PORTB

NOPMOVF PORTB,W

Note:

This example shows a write to PORTB,

followed by a read from PORTB.

Note tha t:

data setup time = (0.25TCY - TPD)

where TCY = instruction cycle

TPD = propagation delay

Therefore, at higher clock frequencies, a

write followed by a read may be problematic.

PIC17CXXX

I/O

C(1)

Q4 Q1 Q2 Q3 Q4 Q1

VIL

BSF PORTx, PINy

Q2 Q3

BSF PORTx, PINz

PORTx, PINy

Read PORTx, PINy as low

BSF PORTx, PINz clears the value

to be driven on the PORTx, PINy pin.

Note 1: This is not a capacitor to ground, but the effective

capacitive loading on the trace.

 2000 Microchip Technology Inc. DS30289B-page 95

PIC17C7XX

11.0 OVERVIEW OF TIMER

RESOURCES

The P IC17C7 XX has four tim er mo dules . Each modul e

can generate an interrupt to indicate that an event has

occurred. These timers are called:

•Timer0 - 16-bit timer with programmable 8-bit

prescaler

•Timer1 - 8-bit timer

•Timer2 - 8-bit timer

•Timer3 - 16-bit timer

For enhanced time base functionality, four input Cap-

tures an d three Puls e Width Mod ulation (PWM) outputs

are possible. The PWMs use the Timer1 and Timer2

resources and the input Captures use the Timer3

resource.

11.1 Timer0 Overview

The Timer0 module is a simple 16-bit overflow counter.

The clock source can be either the internal system

clock (Fosc/4) or an external clock.

When Timer0 uses an external clock source, it has the

flexibility to allow user selection of the incrementing

edge, rising or falling.

The Timer0 module also has a programmable pres-

caler. The T0PS 3:T0PS0 bi ts (T0STA<4:1>) determin e

the prescale value. TMR0 can increment at the follow-

ing rates: 1:1, 1:2, 1:4, 1:8, 1:16, 1:32, 1:64, 1:128,

1:256.

Synchronization of the external clock occurs after the

prescaler. When the prescaler is used, the external

clock frequency may be higher than the device’s fre-

quency. The maximum external frequency on the

T0CKI pin is 50 MHz, given the high and low time

requirements of the clock.

11.2 Timer1 Overview

The Timer1 module is an 8-bit timer/counter with an 8-

bit period register (PR1). When the TMR1 value rolls

over from the period match value to 0h, the TMR1IF

flag is se t and an int errupt w ill be ge nerated if enable d.

In Counter mode, the clock comes from the RB4/

TCLK12 p in, which ca n also be selec ted to be the cloc k

for the Timer2 module.

TMR1 can be concatenated with TMR2 to form a 16-bit

timer. The TMR1 register is the LSB and TMR2 is the

MSB. When in the 16-bit timer mode, there is a corre-

sponding 16-bit period register (PR2:PR1). When the

TMR2:TMR1 value rolls over from the period match

value t o 0h , th e TM R 1IF fla g i s set and an int errup t w il l

be generated, if enabled.

11.3 Timer2 Overview

The Timer2 module is an 8-bit timer/counter with an 8-

bit period register (PR2). When the TMR2 value rolls

over from the period match value to 0h, the TMR2IF

flag is se t and an interrupt wil l be generated, if enabled.

In Counter mode, the clock comes from the RB4/

TCLK12 pin, which can also provide the clock for the

Timer1 module.

TMR2 can be concaten ated with TMR1 to form a 16-bit

timer. The TMR2 register is the MSB and TMR1 is the

LSB. When in the 16-bit timer mode, there is a corre-

sponding 16-bit period register (PR2:PR1). When the

TMR2:TMR1 value rolls over from the period match

value to 0h , th e TM R1IF fla g i s s et and an int errup t wil l

be generated, if enabled.

11.4 Timer3 Overview

The Timer3 module is a 16-bit timer/counter with a 16-

bit period register. When the TMR3H:TMR3L value

rolls over to 0h, the TM R3IF bit is set and an interrupt

will be generated, if enabled. In Counter mode, the

clock comes from the RB5/TCLK3 pin.

When operating in the four Capture modes, the period

registers become the second (of four) 16-bit capture

registers.

11.5 Ro le of the Tim er /Coun ters

The timer mo dules are general purpose , but have de d-

icated resources associated with them. TImer1 and

Timer2 are the time bases for the three Pulse Width

Modulation (PWM) outputs, while Timer3 is the time

base for the four input captures.

PIC17C7XX

DS30289B-page 96  2000 Microchip Technology Inc.

NOTES:

 2000 Microchip Technology Inc. DS30289B-page 97

PIC17C7XX

12.0 TIMER0

The Timer0 module consists of a 16-bit timer/counter,

TMR0. The high byte is register TMR0H and the low

byte is regis ter TMR0L. A softw are programm able 8-bit

prescaler makes Timer0 an effective 24-bit overflow

timer. The clock source is software programmable as

either th e internal i nstructio n clock, or an external clock

on the RA1/T0CKI pin. The control bits for this module

are in register T0STA (Figure 12-1).

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0

INTEDG T0SE T0CS T0PS3 T0PS2 T0PS1 T0PS0 —

bit 7 bit 0

bit 7 INTEDG: RA0/INT Pin Interrupt Edge Select bit

This bit selects the edge upon which the interrupt is detected.

1 = Rising edge of RA0/INT pin generates interrupt

0 = Falling edge of RA0/INT pin generates interrupt

bit 6 T0SE: Timer0 Clock Input Edge Select bit

This bit selects the edge upon which TMR0 will increment.

When T0CS = 0 (External Clock):

1 = Rising edge of RA1/T0CKI pin increments TMR0 and/or sets the T0CKIF bit

0 = Falling edge of RA1/T0CKI pin increments TMR0 and/or sets the T0CKIF bit

When T0CS = 1 (Internal Clock):

Don’t care

bit 5 T0CS: Timer0 Clock Source Select bit

This bit selects the clock source for TMR0.

1 = Internal instruction clock cycle (TCY)

0 = External clock input on the T0CKI pin

bit 4-1 T0PS3:T0PS0: Timer0 Prescale Selection bits

These bits select the prescale value for TMR0.

bit 0 Unimplemented: Read as ’0’

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

- n = Value at POR Reset ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown

T0PS3:T0PS0 Prescale Value

0000

0001

0010

0011

0100

0101

0110

0111

1xxx

1:1

1:2

1:4

1:8

1:16

1:32

1:64

1:128

1:256

PIC17C7XX

DS30289B-page 98  2000 Microchip Technology Inc.

12.1 Timer0 Operation

When the T0CS (T0STA<5>) bit is set, TMR0 incre-

ment s on the i nternal clo ck. When T0 CS is clear, TM R0

increm ents on th e exter nal cl ock (RA1 /T0CKI pin). Th e

external c loc k ed ge can b e selected in sof tware. Whe n

the T0SE (T0STA<6>) bit is set , the timer will increment

on the r ising edg e of the RA 1/T0CK I pin. When T0 SE

is clear, the timer will increment on the falling edge of

the RA1/T0 CKI pin. The prescale r can be programmed

to introduc e a prescale of 1:1 to 1:256. The time r incre-

ments from 0000h to FFFFh and rolls over to 0000h.

On overflow, the TMR0 Interrupt Flag bit (T0IF) is set.

The TMR0 interrupt can be masked by clearing the cor-

responding TMR0 Interrupt Enable bit (T0IE). The

TMR0 Interrupt Flag bit (T0IF) is automatically cleared

when vectoring to the TMR0 interrupt vector.

12.2 Using Timer0 with External Clock

When an external clock input is used for Timer0, it is

synchronized with the internal phase clocks. Figure 12-

2 shows the sy nchron izati on of the exte rnal clock . This

synchronization is done after the prescaler. The output

of the prescaler (PSOUT) is sampled twice in every

instruc tion cycl e to detect a rising or a fa lling edg e. The

timing requirements for the external clock are detailed

in the electrical specification section.

12.2.1 DELAY FROM EXTERNAL CLOCK

EDGE

Since the prescaler output is synchronized with the

internal clocks, there is a small delay from the time the

external clock edge occurs to the time TMR0 is actually

incremented. Figure 12-2 shows that this delay is

between 3TOSC and 7TOSC. Thus, for example, mea-

suring th e in terv al bet we en two ed ges (e. g. pe rio d) w il l

be accurate within ±4TOSC (±121 ns @ 33 MHz).

FIGURE 12-1: TIMER0 MODULE BLOCK DIAGRAM

FIGURE 12-2: TMR0 TIMING WITH EXTERNAL CLOCK (INCREMENT ON FALLING EDGE)

RA1/T0CKI Synchronization

Prescaler

(8 Stage

Async Ripple

Counter)

T0SE

(T0STA<6>)

FOSC/4

T0CS

(T0STA<5>) T0PS3:T0PS0

(T0STA<4:1>) Q2 Q4

1TMR0H<8> TMR0L<8>

Interrupt-on-Overflow

sets T0IF

(INTSTA<5>)

PSOUT

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

Prescaler

Output

(PSOUT)

Sampled

Prescaler

Output

Increment

TMR0

TMR0 T0 T0 + 1 T0 + 2

(Note 3)

(Note 2)

Note 1: The delay from the T0CKI edge to the TMR0 increment is 3Tosc to 7Tosc.

2: ↑ = PSOUT is sampled here.

3: The PSOUT high time is too short and is missed by the sampling circuit.

(Note 1)

 2000 Microchip Technology Inc. DS30289B-page 99

PIC17C7XX

12.3 Read/Write Consideration for

TMR0

Although TMR0 is a 16-bit timer/counter, only 8-bits at

a time c an be re ad or wr itten during a sing le instruc tion

cycle. Care must be taken during any read or write.

12.3.1 READING 16-BIT VALUE

The problem in reading the entire 16-bit value is that

after reading the low (or high) byte, its value may

change from FFh to 00h.

Exampl e 12-1 s hows a 1 6-bi t rea d. To ensure a prop er

read, interrupts must be disabled during this routine.

EXAMPLE 12-1: 16-BIT READ

12.3.2 WRITING A 16-BIT VALUE TO TMR0

Since writing to either TMR0L or TMR0H will effectively

inhibit increment of that half of the TMR0 in the next

cycle (following write), but not inhibit increment of the

other half, the user must write to TMR0L first and

TMR0H second, in two consecutive instructions, as

shown in Example 12-2. The interrupt must be dis-

abl ed. An y write to either TMR0L or TMR0H clear s the

prescaler.

EXAMPLE 12-2: 16-BIT WRITE

12.4 Prescaler Assignments

Timer0 has an 8-bit prescaler. The prescaler selection

is fully under software control; i.e., it can be changed

“on the fly” during program execution. Clearing the

prescaler is recommended before changing its setting.

The va lu e o f t h e pre sc al e r is “unknown” and assigning

a value that i s les s tha n the presen t valu e, mak es i t dif-

ficult to take this unknown time into account.

FIGURE 12-3: TMR0 TIMING: WRITE HIGH OR LOW BYTE

MOVPF TMR0L, TMPLO ;read low tmr0

MOVPF TMR0H, TMPHI ;read high tmr0

MOVFP TMPLO, WREG ;tmplo −> wreg

CPFSLT TMR0L ;tmr0l < wreg?

RETURN ;no then return

MOVPF TMR0L, TMPLO ;read low tmr0

MOVPF TMR0H, TMPHI ;read high tmr0

RETURN ;return

BSF CPUSTA, GLINTD ; Disable interrupts

MOVFP RAM_L, TMR0L ;

MOVFP RAM_H, TMR0H ;

BCF CPUSTA, GLINTD ; Done, enable

; interrupts

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

AD15:AD0

ALE

TMR0L

TMR0H

MOVFP W,TMR0L

Write to TMR0L MOVFP TMR0L,W

Read TMR0L

(Value = NT0)

MOVF P TMR0L,W

Read TMR0L

(Value = NT0)

MOVFP TMR0L, W

Read TMR0L

(Value = NT0 +1)

T0 T0+1 New T0 (NT0) New T0+1

PC PC+1 PC+2 PC+3 PC+4

Fetch

Instruction

Executed

PIC17C7XX

DS30289B-page 100  2000 Microchip Technology Inc.

FIGURE 12-4: TMR0 READ/WRITE IN TIMER MODE

TABLE 12-1: REGISTERS/BITS ASSOCIATED WITH TIMER0

Instruction

Executed

MOVFP

DATAL,TMR0L

Wr ite TMR0L

MOVFP

DATAH,TMR0H

Write TMR0H

MOVPF

TMR0L,W

Read TMR0L

MOVPF

TMR0L,W

Read TMR0L

MOVPF

TMR0L,W

Read TMR0L

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

AD15:AD0

ALE

WR_TRM0L

WR_TMR0H

RD_TMR0L

TMR0H

TMR0L

12 12 13 AB

FE FF 56 57 58

Note: In this example, old TMR0 value is 12FEh, new value of AB56h is written.

Instruction

Fetched

MOVFP

DATAL,TMR0L

Wr ite TMR0L

MOVFP

DATAH,TMR0H

Write TMR0H

MOVPF

TMR0L,W

Read TMR0L

MOVPF

TMR0L,W

Read TMR0L

MOVPF

TMR0L,W

Read TMR0L

MOVPF

TMR0L,W

Read TMR0L

Previously

Fetched

Instruction

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on

POR,

BOR MCLR, WDT

05h, Unba nke d T0STA INTEDG T0SE T0CS T0PS3 T0PS2 T0PS1 T0PS0 —0000 000- 0000 000-

06h, Unba nke d CPUSTA — — STKAV GLINTD TO PD POR BOR --11 11qq --11 qquu

07h, Unba nke d INTSTA PEIF T0CKIF T0IF INTF PEIE T0CKIE T0IE INTE 0000 0000 0000 0000

0Bh, Unbanked TMR0L TMR0 Register; Low Byte xxxx xxxx uuuu uuuu

0Ch, Unbanked TMR0H TMR0 Register; High Byte xxxx xxxx uuuu uuuu

Legend: x = unknown, u = unchanged, - = unimplemented, read as a '0', q = value depends on condition. Shaded cells are not used by Timer0.

 2000 Microchip Technology Inc. DS30289B-page 101

PIC17C7XX

13.0 TIMER1, TIMER2, TIMER3,

PWMS AND CAPTURES

The PIC1 7C7XX has a w ealth of time rs and time b ased

functio ns to ease the implementation of control applica-

tions. These time base functions include three PWM

outputs and four Capture inputs.

Timer1 and Timer2 are two 8-bit incrementing timers,

each with an 8-bit period register (PR1 and PR2, respec-

tively) and sep arate ov erflow interru pt flags. Timer1 and

T ime r2 can operate either as timers (increment on inte r-

nal FOSC/4 clock), or as counters (increment on falling

edge of external clock on pin RB4/TCLK12). They are

also software configurable to operate as a single 16-bit

timer/counter. These timers are also used as the time

base for the PWM (Pulse Wid th M odulation) mo dules.

T imer3 is a 16-b it timer/counte r which uses the TM R3H

and TMR3L registers. Timer3 also has two additional

registers (PR3H/CA1H:PR3L/CA1L) that are config-

urable as a 16-bit period register or a 16-bit capture

ment from the internal system clock (FOSC/4), or from

an external signal on the RB5/TCLK3 pin. T imer3 is the

time base for all of the 16-bit captures.

Six other registers comprise the Capture2, Capture3,

and Capture4 registers (CA2H:CA2L, CA3H:CA3L,

and CA4H:CA4L).

Figure 13-1, Figure 13-2 and Figure 13-3 are the con-

trol registers for the operation of Timer1, Timer2 and

Timer3, as well as PWM1, PWM2, PWM3, Capture1,

Capture2, Capture3 and Capture4.

Table 13-1 shows the Timer resource requirements for

these time base functions. Each timer is an open

resource so that multiple functions may operate with it.

TABLE 13-1: TIME-BASE FUNCTION/

RESOURCE REQUIREMENTS

Time Ba se Func tion Timer Resou r ce

PWM1 Timer1

PWM2 Timer1 or Timer2

PWM3 Timer1 or Timer2

Capture1 Timer3

Capture2 Timer3

Capture3 Timer3

Capture4 Timer3

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

CA2ED1 CA2ED0 CA1ED1 CA1ED0 T16 TMR3CS TMR2CS TMR1CS

bit 7 bit 0

bit 7-6 CA2ED1:CA2ED0: Capture2 Mode Select bits

00 = Capture on every falling edge

01 = Capture on every rising edge

10 = Capture on every 4th rising edge

11 = Capture on every 16th rising edge

bit 5-4 CA1ED1:CA1ED0: Capture1 Mode Select bits

00 = Capture on every falling edge

01 = Capture on every rising edge

10 = Capture on every 4th rising edge

11 = Capture on every 16th rising edge

bit 3 T16: Timer2:Timer1 Mode Select bit

1 = Timer2 and Timer1 form a 16-bit timer

0 = Timer2 and Timer1 are two 8-bit timers

bit 2 TMR3CS: Timer3 Clock Source Select bit

1 = TMR3 increments off the falling edge of the RB5/TCLK3 pin

0 = TMR3 increments off the inte rnal clock

bit 1 TMR2CS: Timer2 Clock Source Select bit

1 = TMR2 increments of f the fal lin g edge of the RB4/TCLK12 pin

0 = TMR2 increments off the inte rnal clock

bit 0 TMR1CS: Timer1 Clock Source Select bit

1 = TMR1 increments of f the fal lin g edge of the RB4/TCLK12 pin

0 = TMR1 increments off the inte rnal clock

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

- n = Value at POR Reset ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown

PIC17C7XX

DS30289B-page 102  2000 Microchip Technology Inc.

R-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

CA2OVF CA1OVF PWM2ON PWM1ON CA1/PR3 TMR3ON TMR2ON TMR1ON

bit 7 bit 0

bit 7 CA2OVF: Capture2 Overflow Status bit

This bit indicates that the capture value had not been read from the capture register pair

(CA2H:CA2L) before the next capture event occurred. The capture register retains the oldest

unread capture value (last capture before overflow). Subsequent capture events will not update

the capture register with the TMR3 value until the capture register has been read (both bytes).

1 = Overflow occurred on Capture2 register

0 = No overflow occurred on Capture2 register

bit 6 CA1OVF: Capture1 Overflow Status bit

This bit ind icate s that the capture val ue had no t been rea d from the capture register pair (PR3H/

CA1H:PR3 L/CA1L), before the next capture e vent occurred. The capture regist er retains the old-

est unread capture value (last capture before overflow). Subsequent capture events will not

update the capture register with the TMR3 value until the capture register has been read (both

bytes).

1 = Overflow occurred on Capture1 register

0 = No overflow occurred on Capture1 register

bit 5 PWM2ON: PWM2 On bit

1 =PWM2 is enabled

(The RB3/PWM2 pin ignores the state of the DDRB<3> bit.)

0 =PWM2 is disabled

(The RB3/PWM2 pin uses the state of the DDRB<3> bit for data direction.)

bit 4 PWM1ON: PWM1 On bit

1 =PWM1 is enabled

(The RB2/PWM1 pin ignores the state of the DDRB<2> bit.)

0 =PWM1 is disabled

(The RB2/PWM1 pin uses the state of the DDRB<2> bit for data direction.)

bit 3 CA1/PR3: C A1/PR3 Register Mode Select bit

1 =Enables Capture1

(PR3H/CA1H:PR3L/CA1L is the Capture1 register. Timer3 runs without a period register.)

0 =Enables the Period register

(PR3H/CA1H:PR3L/CA1L is the Period register for Timer3.)

bit 2 TMR3ON: Timer3 On bit

1 = Starts Ti mer3

0 = Stops Timer3

bit 1 TMR2ON: Timer2 On bit

This bit controls the incrementing of the TMR2 register . When TMR2:TMR1 form the 16-bit timer

(T16 is set), TMR2ON must be set. This allows the MSB of the timer to increment.

1 = Starts Timer2 (must be enabled if the T16 bit (TCON1<3>) is set)

0 = Stops Timer2

bit 0 TMR1ON: Timer1 On bit

When T16 is set (in 16-bit Timer mode):

1 = Starts 16-bit TMR2:TMR1

0 = Stops 16-bit TMR2:TMR1

When T16 is clear (in 8-bit Timer mode:

1 = Starts 8-bit Timer1

0 = Stops 8- bit Timer1

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

- n = Value at POR Reset ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown

 2000 Microchip Technology Inc. DS30289B-page 103

PIC17C7XX

U-0 R-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

—CA4OVF CA3OVF CA4ED1 CA4ED0 CA3ED1 CA3ED0 PWM3ON

bit 7 bit 0

bit 7 Unimplemented: Read as ‘0’

bit 6 CA4OVF: Capture4 Overflow Status bit

This bit indicates that the capture value had not been read from the capture register pair

(CA4H:CA4L) before the next capture event occurred. The capture register retains the oldest

unread capture value (last capture before overflow). Subsequent capture events will not update

the capture register with the TMR3 value until the capture register has been read (both bytes).

1 = Overflow occurred on Capture4 registers

0 = No overflow occurred on Capture4 registers

bit 5 CA3OVF: Capture3 Overflow Status bit

This bit indicates that the capture value had not been read from the capture register pair

(CA3H:CA3L) before the next capture event occurred. The capture register retains the oldest

unread capture value (last capture before overflow). Subsequent capture events will not update

the capture register with the TMR3 value until the capture register has been read (both bytes).

1 = Overflow occurred on Capture3 registers

0 = No overflow occurred on Capture3 registers

bit 4-3 CA4ED1:CA4ED0: Capture4 Mode Select bits

00 = Capture on every falling edge

01 = Capture on every rising edge

10 = Capture on every 4th rising edge

11 = Capture on every 16th rising edge

bit 2-1 CA3ED1:CA3ED0: Capture3 Mode Select bits

00 = Capture on every falling edge

01 = Capture on every rising edge

10 = Capture on every 4th rising edge

11 = Capture on every 16th rising edge

bit 0 PWM3ON: PWM3 On bit

1 = PWM3 is enabled (the RG5/PWM3 pin ignores the state of the DDRG<5> bit)

0 = PWM3 is disabled (the RG5/PWM3 pin uses the state of the DDRG<5> bit for data direction)

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

- n = Value at POR Reset ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown

PIC17C7XX

DS30289B-page 104  2000 Microchip Technology Inc.

13.1 Timer1 and Timer2

13.1.1 TIMER1, TIMER2 IN 8-BIT MODE

Both Timer1 and Timer2 will operate in 8-bit mode

when the T16 bit is clear . These two timers can be inde-

pendently configured to increment from the internal

instr uction cycle c lock (TCY), or from an external clock

source on the RB4/TC LK12 pin. The timer clock so urce

is configured by the TMRxCS bit (x = 1 for Timer1,

or = 2 for Timer2). When TMRxCS is clear, the clock

source is internal and increments once every instruc-

tion cycle (FOSC/4). When TMRxCS is set, the clock

source is the RB4/TCLK12 pin and the counters will

increment on every falling edge of the RB4/TCLK12

pin.

The tim er incremen ts from 00h until it e quals the Period

ment cycle. The timer interrupt flag is set when the

timer is reset. TMR1 and TMR2 have individual inter-

rupt flag b its . The TM R1 interru pt flag bit is l atched in to

TMR1IF and the TMR2 interrupt flag bit is latched into

TMR2IF.

Each timer also has a corresponding interrupt enable

bit (TMRxIE). The timer interrupt can be enabled/

disabled by setting/clearing this bit. For peripheral

interrupts to be enabled, the Peripheral Interrupt

Enable bit must be set (PEIE = ’1’) and global interrupt

must be enabled (GLINTD = ’0’).

The timers can be turned on and off under software

control. When the ti mer on contro l bit (TMRxON) is set,

the timer increments from the clock source. When

TMRxON is cleared, the timer is turned off and cannot

cause the timer interrupt flag to be set.

13.1.1.1 External Clock Input for Timer1 and

Timer2

When TMRxCS is set, the clock source is the RB4/

TCLK12 pin, and the counter will increment on every

falling edge on the RB4/TCLK12 pin. The TCLK12

input is synchronized with internal phase clocks. This

causes a del ay from the tim e a fal ling e dge ap pears o n

TCLK12 to the time TMR1 or TMR2 is actually incre-

mented. For the external clock input timing require-

ments, see the Elect r ic al Specific ati on se cti on.

FIGURE 13-1: TIMER1 AND TIMER2 IN TWO 8-BIT TIMER/COUNTER MODE

FOSC/4

RB4/TCLK12

TMR1ON

(TCON2<0>)

TMR1CS

(TCON1<0>)

TMR1

PR1

RESET

Equal

Set TMR1IF

(PIR1<4>)

Comparator<8>Comparator x8

FOSC/4

TMR2ON

(TCON2<1>)

TMR2CS

(TCON1<1>)

TMR2

PR2

RESET

Equal

Set TMR2IF

(PIR1<5>)

Comparator<8>Comparator x8

 2000 Microchip Technology Inc. DS30289B-page 105

PIC17C7XX

13.1.2 T IMER1 AND TIMER2 IN 16-BIT

MODE

To select 16-bit mode, set the T16 bit. In this mode,

TMR2 and TMR1 are concatenated to form a 16-bit

timer (TMR2:TMR1). The 16-bit timer increments until

it matc hes the 16 -bit period register (PR2:P R1). On th e

followin g timer clock , the ti mer va lue is reset to 0h, an d

the TMR1IF bit is set.

When selectin g the clock source for the 16-bit ti mer , the

TMR1CS bit controls the entire 16-bit timer and

TMR2CS is a “don’t care”, however, ensure that

TMR2ON is set (allows TMR2 to increment). When

TMR1CS is clear, the timer increments once every

instruction cycle (FOSC/4). When TMR1CS is set, the

timer increments on every falling edge of the RB4/

TCLK12 pin. For the 16-bit timer to increment, both

TMR1ON and TMR2ON bits must be set (Table 13-2).

TABLE 13-2: TURNING ON 16-BIT TIMER

13.1.2.1 External Clock Input for

TMR2:TMR1

When TMR1CS is set, the 16-bit TMR2:TMR1 incre-

ments on the falling edge of clock input TCLK12. The

input on the RB4 /TC LK1 2 p in i s sam ple d and syn ch ro-

nized by the internal phase clocks twice every instruc-

tion cycle. This causes a delay from the time a falling

edge appears on RB4/TCLK12 to the time

TMR2 :TMR1 is actually increme nted. F or the exte rnal

clock input timing requirements, see the Electrical

Specification section.

FIGURE 13-2: TMR2 AND TMR1 IN 16-BIT TIMER/COUNTER MODE

T16 TMR2ON TMR1ON Result

11 116-bit timer

(TMR2:TMR1) ON

10 1Only TMR1 increments

1x 016-bit timer OFF

01 1Timers in 8-bit mode

RB4/TCLK12 FOSC/4 TMR1ON

(TCON2<0>)

TMR1CS

(TCON1<0>) TMR1 x 8

PR1 x 8

RESET

Equal

Set Int errupt TMR1IF

(PIR1<4>)

Comparator<8>

Comparator x16

TMR2 x 8

PR2 x 8

MSB LSB

PIC17C7XX

DS30289B-page 106  2000 Microchip Technology Inc.

TABLE 13-3: SUMMARY OF TIMER1, TIMER2 AND TIMER3 REGISTERS

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on

POR,

BOR MCLR, WDT

16h, Bank 3 TCON1 CA2ED1 CA2ED0 CA1ED1 CA1ED0 T16 TMR3CS TMR2CS TMR1CS 0000 0000 0000 0000

17h, Bank 3 TCON2 CA2OVF CA1OVF PWM2ON PWM1ON CA1/PR3 TMR3ON TMR2ON TMR1ON 0000 0000 0000 0000

16h, Bank 7 TCON3 —CA4OVF CA3OVF CA4ED1 CA4ED0 CA3ED1 CA3ED0 PWM3ON -000 0000 -000 0000

10h, Bank 2 TMR1 Timer1’s Register xxxx xxxx uuuu uuuu

11h, B ank 2 TM R2 Timer2’s Register xxxx xxxx uuuu uuuu

16h, Bank 1 PIR1 RBIF TMR3IF TMR2IF TMR1IF CA2IF CA1IF TX1IF RC1IF x000 0010 u000 0010

17h, Bank 1 PIE1 RBIE TMR3IE TMR2IE TMR1IE CA2IE CA1IE TX1IE RC1IE 0000 0000 0000 0000

07h, Unba nked INTSTA PEIF T0CKIF T0IF INTF PEIE T0CKIE T0IE INTE 0000 0000 0000 0000

06h, Unbanked CPUSTA — — STKAV GLINTD TO PD POR BOR --11 11qq --11 qquu

14h, Bank 2 PR1 Timer1 Period Register xxxx xxxx uuuu uuuu

15h, Bank 2 PR2 Timer2 Period Register xxxx xxxx uuuu uuuu

10h, Bank 3 PW1DCL DC1 DC0 — — — — — — xx-- ---- uu-- ----

11h, Bank 3 P W2DCL DC1 DC0 TM2PW2 — — — — — xx0- ---- uu0- ----

10h, Bank 7 PW3DCL DC1 DC0 TM2PW3 — — — — — xx0- ---- uu0- ----

12h, Bank 3 PW1DCH DC9 DC8 DC7 DC6 DC5 DC4 DC3 DC2 xxxx xxxx uuuu uuuu

13h, Bank 3 PW2DCH DC9 DC8 DC7 DC6 DC5 DC4 DC3 DC2 xxxx xxxx uuuu uuuu

11h, Bank 7 PW3DCH DC9 DC8 DC7 DC6 DC5 DC4 DC3 DC2 xxxx xxxx uuuu uuuu

Legend: x = unknown, u = unchanged, - = unimplemented, read as a '0', q = value depends on condition.

Shaded cells are not used by Timer1 or Timer2.

 2000 Microchip Technology Inc. DS30289B-page 107

PIC17C7XX

13.1.3 USING PULSE WIDTH

MODULATION (PWM) OUTPUTS

WITH TIMER1 AND TIMER2

Three high speed pulse width modulation (PWM) out-

puts are provided. The PWM1 output uses Timer1 as

its time base, while PWM2 and PWM3 may indepen-

dently be software configured to use either Timer1 or

Timer2 as the time base. The PWM outputs are on the

RB2/PWM1, RB3/P WM2 and RG5/PWM3 pins.

Each PWM output has a maximum resolution of 10-

bits. At 10-bit resolution, the PWM output frequency is

32.2 kHz (@ 32 MHz clock) and at 8-bit resolution the

PWM out put freq ue ncy is 12 8.9 kHz . The du ty cy cl e of

the output can vary from 0% to 100%.

Figure 13-3 shows a simplified block diagram of a

PWM module.

The duty cycle registers are double buffered for glitch

free operation. Figure 13-4 shows how a glitch could

occur if the duty cycle registers were not double

buffered.

The user needs to set the PWM1ON bit (TCON2<4>)

to enable the PWM1 output. When the PWM1ON bit is

set, the RB2/PWM1 pin is configured as PWM1 output

and forced as an output, irrespective of the data direc-

tion bit (DDRB<2>). When the PWM1ON bit is clear,

the pin behaves as a port pin and its direction is con-

trolled by its data direction bit (DDRB<2>). Similarly,

the PWM2ON (TCON2<5>) bit controls the configura-

tion of the RB3/PWM2 pin and the PWM3ON

(TCON3<0>) bit controls the configuration of the RG5/

PWM3 pin.

FIGURE 13-3: SIMPLIFIED PWM BLOCK

DIAGRAM

FIGURE 13-4: PWM OUTPUT (NOT BUFFERED)

PWxDCH

Duty Cycle Registers PWxDCL<7:6>

Clear Timer,

PWMx pin and

Latch D.C.

(Slave)

Comparator

TMRx

Comparator

PRy

(Note 1)

PWMxON

PWMx

Note 1: 8-bit timer is concatenated with 2-bit internal

Q clock or 2 bits of the prescaler to create

Read

Write

10-bit time base.

010203040 0

PWM

Output

Timer

Interrupt Write New

PWM Duty Cycle Value Timer Interrupt

New PWM Duty Cycle Value

Transferred to Slave

The dotted line shows PWM output if duty cycle registers were not double buffered.

If the new duty cycle is written after the timer has passed that value, then the PWM does

not reset at all during the current cycle, causing a “glitch”.

In this example, PWM period = 50. Old duty cycle is 30. New duty cycle value is 10.

10 20 30 40 0

Note:

PIC17C7XX

DS30289B-page 108  2000 Microchip Technology Inc.

13.1.3.1 PWM Periods

The period of the PWM1 output is determined by

Timer1 and its period register (PR1). The period of the

PWM2 and PWM3 output s can be in dividual ly softwa re

configured to use either Timer1 or Timer2 as the time-

base. For PWM 2, when TM2PW 2 bit (PW2 DCL<5> ) is

clear, the time base is determined by TMR1 and PR1

and whe n TM2PW2 is set, the ti me bas e is de termine d

by Timer2 and PR2. For PWM3, when TM2PW3 bit

(PW3DCL<5 >) is c lea r, the tim e b as e is de term in ed b y

TMR1 and PR1, and when TM2PW3 is set, the time

base is determined by Timer2 and PR2.

Running two different PWM outputs on two different

timers allows different PWM periods. Running all

PWMs from Tim er1 allows the bes t use of resources b y

freeing Timer2 t o operate a s an 8 - bi t ti me r. Timer1 and

Timer2 cannot be used as a 16-bit timer if any PWM is

being used.

The PWM periods can be calculated as follows:

period of PWM1 = [(PR1) + 1] x 4TOSC

period of PWM2 = [(PR1) + 1] x 4TOSC or

[(PR2) + 1] x 4TOSC

period of PWM3 = [(PR1) + 1] x 4TOSC or

[(PR2) + 1] x 4TOSC

The duty cycle of PWMx is determined by the 10-bit

value DCx<9:0>. The upper 8-bits are from register

PWxDCH and the lower 2-bits are f rom PWxDCL<7:6>

(PWxDCH:PWxDCL<7:6>). Table 13-4 shows the

maximum PWM frequency (FPWM), given the value in

the period register.

The number of bits of resolution that the PWM can

achieve depends on the operation frequency of the

device as well as the PWM frequency (FPWM).

Maximum PWM resolution (bits) for a given PWM

frequency:

where: FPWM = 1 / period of PWM

The PWMx duty cycle is as follows:

PWMx Duty Cycle = (DCx) x TOSC

where DCx represents the 10-bit value from

PWxDCH:PWxDCL.

If DCx = 0, then the duty cycle is zero. If

PRx = PWxDCH, then the PWM output will be low for

one to four Q-clocks (depending on the state of the

PWxDCL<7:6> bits). For a duty cycle to be 100%, the

PWxDCH value must be greater then the PRx val ue.

The duty cycle regis ters for both PWM out puts a re dou-

ble buffered. When the user writes to these registers,

they are stored in master latches. When TMR1 (or

TMR2) overflows and a new PWM period begins, the

master la tch values are transferred to the slave latc hes

and the PWMx pin is forced high.

The user should also avoid any "read-modify-write"

operations on the duty cycle registers, such as:

ADDWF PW1DCH. This may cause duty cycle outputs

that are unpredictable.

TABLE 13-4: PW M FREQUENCY vs.

RESOLUTION AT 33 MHz

13.1.3.2 PWM INTERRUPTS

The PWM modules make use of the TMR1 and/or

TMR2 interrupts. A timer interrupt is generated when

TMR1 or TMR2 equals its period register and on the

following increment is cleared to zero. This interrupt

also marks the beginning of a PWM cycle. The user

can write new duty cycle values before the timer

rollove r . The TMR1 interrup t is latched into th e TMR1IF

bit and the TMR2 interrupt is latched into the TMR2IF

bit. These flags must be cleared in software.

log (FPWM

log (2)

FOSC )bits=

Note: For PW1DCH, PW1DCL, PW2DCH,

PW2DCL, PW3DCH and PW3DCL regis-

ters, a w rite opera tion wri tes to the "master

latches", while a read operation reads the

"slave latches". As a result, the user may

not read back what was just written to the

duty cycle registers (until transferred to

slave latch).

PWM

Frequency Frequency (kHz)

32.2 64.5 90.66 128.9 515.6

PRx Value 0xFF 0x7F 0x5A 0x3F 0x0F

High

Resolution 10-bit 9-bit 8.5-bit 8-bit 6-bit

Standard

Resolution 8-bit 7-bit 6.5-bit 6-bit 4-bit

 2000 Microchip Technology Inc. DS30289B-page 109

PIC17C7XX

13.1.3.3 External Clock Source

The PWMs will operate, regardless of the clock source

of the timer. The use of an external clock has ramifica-

tions that must be understood. Because the external

TCLK12 input is synchroni zed internally (sampled once

per instruction cycle), the time TCLK12 changes to the

time the timer inc rement s, will vary by as m uch as 1TCY

(one instruction cycle). This will cause jitter in the duty

cycle as well as the period of the PWM output.

This j itter will b e ±1TCY, unless the external clock is syn-

chronized with the processor clock. Use of one of the

PWM outp ut s as th e cloc k so urce to the TCLK1 2 inpu t,

will supply a synchronized clock.

In general, when using an external clock source for

PWM, its frequency should be much less than the

device frequency (FOSC).

13.1.3.4 Maximum Resolution/Frequency for

Extern al Cloc k Input

The use of an external clock for the PWM time base

(Timer1 or Timer2) limits the PWM output to a maxi-

mum re sol uti on of 8-b it s . Th e PWxD CL <7:6 > b it s m us t

be kept cleared. Use of any other value will distort the

PWM output. All resolutions are supported when inter-

nal clock mode is selected. The maximum attainable

frequency is also lower. This is a result of the timing

requirem ents of an exte rnal c lock input f or a tim er (se e

the Electrical Specification section). The maximum

PWM frequency, when the timers clock source is the

RB4/TCLK12 pin, is shown in Table 13-4 (Standard

Resolution mode).

TABLE 13-5: REGISTERS/BITS ASSOCIATED WITH PWM

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on

POR,

BOR

MCLR,

WDT

16h, Bank 3 TCO N1 CA2ED1 CA2ED0 CA1ED1 CA1ED0 T16 TMR3CS TMR2CS TMR1CS 0000 0000 0000 0000

17h, Bank 3 TCO N2 CA2OVF CA1OVF PWM2ON PWM1ON CA1/PR3 TMR3ON TMR2ON TMR1ON 0000 0000 0000 0000

16h, Bank 7 TCO N3 —CA4OVF CA3OVF CA4ED1 CA4ED0 CA3ED1 CA3ED0 PWM3ON -000 0000 -000 0000

10h, Bank 2 TMR 1 Timer 1’s Register xxxx xxxx uuuu uuuu

11h, Bank 2 TMR2 Timer2’s Register xxxx xxxx uuuu uuuu

16h, Bank 1 PIR 1 RBIF TMR3IF TMR2IF TMR1IF CA2IF CA1IF TX1IF RC1IF x000 0010 u000 0010

17h, Bank 1 PIE1 RBIE TMR3IE TMR2IE TMR1IE CA2IE CA1IE TX1IE RC1IE 0000 0000 0000 0000

07h, Unba nke d INTSTA PE IF T0CKIF T0IF INTF PEIE T0CKIE T0IE INTE 0000 0000 0000 0000

06h, Unba nke d CPUSTA — — STKAV GLINTD TO PD POR BOR --11 11qq --11 qquu

14h, Bank 2 PR1 Timer1 Period Regi s ter xxxx xxxx uuuu uuuu

15h, Bank 2 PR2 Timer2 Period Regi s ter xxxx xxxx uuuu uuuu

10h, Bank 3 PW1DCL DC1 DC0 — — — — — — xx-- ---- uu-- ----

11h, Bank 3 PW2DCL DC1 DC0 TM2PW2 — — — — — xx0- ---- uu0- ----

10h, Bank 7 PW3DCL DC1 DC0 TM2PW3 — — — — — xx0- ---- uu0- ----

12h, Bank 3 PW1DCH DC9 DC8 DC7 DC6 DC5 DC4 DC3 DC2 xxxx xxxx uuuu uuuu

13h, Bank 3 PW2DCH DC9 DC8 DC7 DC6 DC5 DC4 DC3 DC2 xxxx xxxx uuuu uuuu

11h, Bank 7 PW3DCH DC9 DC8 DC7 DC6 DC5 DC4 DC3 DC2 xxxx xxxx uuuu uuuu

Legend: x = unknown, u = unchanged, - = unimplemented, read as '0', q = value depe nds on conditions .

Shaded cells are not used by PWM Module.

PIC17C7XX

DS30289B-page 110  2000 Microchip Technology Inc.

13.2 Timer3

Timer3 is a 16-bit timer consisting of the TMR3H and

TMR3L registers. TMR3H is the high byte of the timer

and TMR3L is the low byte. This timer has an associ-

ated 16-bit period register (PR3H/CA1H:PR3L/CA1L).

This pe rio d re gis ter can be soft wa re c on fig ured to be a

another 16-bit capture register.

When the TMR3CS bit (TCON1<2>) is clear, the timer

increments every instruction cycle (FOSC/4). When

TMR3CS i s set, the counter increment s on every fallin g

edge of the RB5/TCLK3 pin. In either mode, the

TMR3ON bi t mu st b e se t for t he ti mer/count er to incre-

ment. When TMR3ON is clear, the timer will not incre-

ment or set flag bit TMR3IF.

Timer3 has two modes of operation, depending on the

CA1/PR3 bit (TCON2<3>). These modes are:

•Three capture and one period register mode

•Four captu re register mode

The PIC17C7XX has up to four 16-bit capture registers

that capt ure th e 16-bit val ue of TMR3 when e vents are

detected on capture pins. There are four capture pins

(RB0/CAP1, RB1/CAP2, RG4/CAP3, and RE3/CAP4),

one for ea ch captu re regis ter pai r . The c apture pin s are

multiplexed with the I/O pins. An event can be:

•A rising edge

•A falling edge

•Every 4th rising edge

•Every 16th rising edge

Each 16-b it c apt ure re gi ster has an int errup t flag asso-

ciated with it. The flag is set when a capture is made.

The cap ture m odules are t ruly part of the Timer3 blo ck.

Figure 13-5 and Figure 13-6 show the block diagrams

for the two modes of operation.

13.2.1 THREE CAPTURE AND ONE

PERIOD REGISTER MODE

In this mode, registers PR3H/CA1H and PR3L/CA1L

constitute a 16-bit period register. A block diagram is

shown in Figure 13-5. The timer increments until it

equals the period register and then resets to 0000h on

the next timer clock. TMR3 Interrupt Flag bit (TMR3IF)

is set at this point. This interrupt can be disabled by

clearing the TMR3 Interrupt Enable bit (TMR3IE).

TMR3IF must be cleared in software.

FIGURE 13-5: TIMER3 WITH THREE CAPTURE AND ONE PERIOD REGISTER BLOCK DIAGRAM

PR3H/CA1H

TMR3H

Comparator<8>

FOSC/4

TMR3ON

Reset

Equal

Comparator x16

RB5/TCLK3

Set TMR3IF

TMR3CS PR3L/CA1L

TMR3L

CA2H CA2L

RB1/CAP2

Edge select,

Prescaler select

Set CA2IF

Capture2

CA2ED1: CA2ED0

(TCON1<7:6>)

(TCON2<2>)

(TCON1<2>)

(PIR1<3>)

(PIR1<6>)

Enable

CA3H CA3L

RG4/CAP3

Edge select,

Prescaler selec t

Set CA3IF

Capture3

CA3ED1: CA3ED0

(TCON3<2:1>) (PIR2<2>)

Enable

CA4H CA4L

RE3/CAP4

Edge select,

Prescaler selec t

Set CA4IF

Capture4

CA4ED1: CA4ED0

(TCON3<4:3>) (PIR2<3>)

Enable

 2000 Microchip Technology Inc. DS30289B-page 111

PIC17C7XX

This mode (3 Capt ure, 1 Period) is selected if control b it

CA1/PR3 is clear. In this mode, the Capture1 register,

consisting of high byte (PR3H/CA1H) and low byte

(PR3L/CA1L ), is confi gured as the period con trol regis-

ter for TM R3. Capture1 is d isabled in this mode and th e

corresponding interrupt bit, CA1IF, is never set. TMR3

increments until it equals the value in the period regis-

ter and then reset s to 0000h on the nex t time r clock.

All other Captures are active in this mode.

13.2.1.1 Capture Operation

The CAx ED1 an d CAxED0 bit s determ ine the event on

which capture will occur. The possible events are:

•Capture on every falling edge

•Capture on every rising edge

•Capture every 4th rising edge

•Capture every 16th rising edge

When a c apture t akes pla ce, an in terrupt flag is latche d

into the CAxIF b it. This int errupt can be enabl ed by s et-

ting the correspon din g m as k bit C Ax IE. T he Peripheral

Interrupt Enable bit (PEIE) must be set and the Global

Interrupt Disable bit (GLINTD) must be cleared for the

interrupt to be acknowledged. The CAxIF interrupt flag

bit is cleared in software.

When the capture pr escale sele ct is ch anged, the pre s-

caler is not reset and an event may be generated.

Therefore, the first capture after such a change will be

ambiguous. However, it sets the time-base for the next

capture. The prescaler is reset upon chip RESET.

The capture pin, CAPx, is a multiplexed pin. When

used as a port pin, the capture is not disabled. How-

ever, the user can simply disable the Capture interrupt

by clear ing CAxIE. If the CAPx pin is used as an output

pin, the user can activate a capture by writing to the

port pin. This may be useful du ring devel opment p hase

to emulate a capture interrupt.

The input on the capture pin CAPx is synchronized

internal ly to intern al phase c locks. Th is imposes certain

restrictions on the input waveform (see the Electrical

Specification section for timing).

The capture overflow status flag bit is double buffered.

The master bit is set if one captured word is already

residing in the Capture register (CAxH:CAxL) and

another “event” has occurred on the CAPx pin. The

new event will not transfer the TMR3 value to the cap-

ture register, protecting the previous unread capture

value . W hen the use r re ads bot h the hi gh and the low

bytes (in an y orde r) of the Ca ptu re regi ste r, the master

overflow bit is transferred to the slave overflow bit

(CAxOVF) and then the master bit is reset. The user

can then read TCONx to determine the value of CAx-

OVF.

The recommended sequence to read capture registers

and capture overflo w flag bit s is shown in Example 13-1.

PIC17C7XX

DS30289B-page 112  2000 Microchip Technology Inc.

13.2.2 FOUR CAPTURE MODE

This mode is selected by setting bit CA1/PR3. A block

diagram is shown in Figure 13-6. In this mode, TMR3

runs without a period register and increments from

0000h to FFFFh and rolls over to 0000h. The TMR3

interrupt Flag (TMR3IF) is set on this rollover. The

TMR3IF bit must be cleared in software.

Registers PR3H/CA1H and PR3L/CA1L make a 16-bit

capture register (Capture1). It captures events on pin

RB0/CAP1. Capture mode is configured by the

CA1ED1 and CA1ED0 bits. Capture1 Interrupt Flag bit

(CA1IF) is set upon detection of the capture event. The

corresponding interrupt mask bit is CA1IE. The

Capture1 Overflow Status bit is CA1OVF.

All the captures operate in the same manner. Refer to

Section 13.2.1 for the operation of capture.

FIGURE 13-6: TIMER3 WITH FOUR CAPTURES BLOCK DIAGRAM

RB0/CAP1

Edge Select,

Prescaler Select

PR3H/CA1H PR3L/CA1L

RB1/CAP2

RG4/CAP3

Edge Select,

Prescaler Select

Set CA1IF

(PIR1<2>)

Capture1 Enable

TMR3ON

TMR3CS

(TCON1<2>)

Set TMR3IF

(PIR1<6>)

Edge Select,

Prescaler Sele ct

CA2H CA2L

Set CA2IF

(PIR1<3>)

CA3H CA3L

Set CA3IF

(PIR2<2>)

CA1ED1, CA1ED0

(TCON1<5:4>)

(TCON2<2>)

FOSC/4

RB5/TCLK3

Capture2 Enable

Capture3 Enable

CA2ED1, CA2ED0

(TCON1<7:6>)

CA3ED1: CA3ED0

(TCON3<2:1>)

TMR3H TMR3L

RE3/CAP4

Edge Select,

Prescaler Select

2CA4H CA4L

Set CA4IF

(PIR2<3>)

Capture4 Enable

CA4ED1: CA4ED0

(TCON3<4:3>)

 2000 Microchip Technology Inc. DS30289B-page 113

PIC17C7XX

13.2.3 READING THE CAPTURE

REGISTERS

The Capture overflow status flag bits are double buff-

ered. The master bit is set if one captured word is

already residing in the Capture register and another

“event” has occurred on the CAPx pin. The new event

will not tran sfer th e TMR 3 va lue to the c apture registe r,

protecting the previous unread capture value. When

the user reads both the high and the low bytes (in any

order) of the Capt ure register , the m aster overflow bit i s

transferred to the slave overflow bit (CAxOVF) and

then the master bit is reset. The user can then read

TCONx to determine the value of CAxOVF.

An examp le of a n instr uct ion se quenc e to read captu re

registers and capture overflow flag bits is shown in

Example 13-1. Depending on the capture source, dif-

ferent registers will need to be read.

EXAMPLE 13-1: SEQUENCE TO READ CAPTURE REGISTERS

TABLE 13-6: REGISTERS ASSOCIATED WITH CAPTURE

MOVLB 3 ; Select Bank 3

MOVPF CA2L, LO_BYTE ; Read Capture2 low byte, store in LO_BYTE

MOVPF CA2H, HI_BYTE ; Read Capture2 high byte, store in HI_BYTE

MOVPF TCON2, STAT_VAL ; Read TCON2 into file STAT_VAL

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on

POR,

BOR MCLR, WDT

16h, Bank 3 TCON1 CA2ED1 CA2ED0 CA1ED1 CA1ED0 T16 TMR3CS TMR2CS TMR1CS 0000 0000 0000 0000

17h, Bank 3 TCON2 CA2OVF CA1O VF PWM2ON PWM1ON CA1/PR3 TMR3ON TMR2ON TMR1ON 0000 0000 0000 0000

16h, Bank 7 TCON3 —CA4OVF CA3OVF CA4ED1 CA4ED0 CA3ED1 CA3ED0 PWM3ON -000 0000 -000 0000

12h, Bank 2 TMR3L Holding Register for the Low Byte of the 16-bit TMR3 Register xxxx xxxx uuuu uuuu

13h, Bank 2 TMR3H Holding Register for the High Byte of the 16-bit TM R3 Regist er xxxx xxxx uuuu uuuu

16h, Bank 1 PIR1 RBIF TMR3IF TMR2IF TMR1IF CA2IF CA1IF TX1IF RC1IF x000 0010 u000 0010

17h, Bank 1 PIE1 RBIE TMR3IE TMR2IE TMR1IE CA2IE CA1IE TX1IE RC1IE 0000 0000 0000 0000

10h, Bank 4 PIR2 SSPIF BCLIF ADIF —CA4IF CA3IF TX2IF RC2IF 000- 0010 000- 0010

11h, B ank 4 PIE 2 SSPIE BCLIE ADIE —CA4IE CA3IE TX2IE RC2IE 000- 0000 000- 0000

07h, Unba nked INTSTA PEIF T0CKIF T0IF INTF PEIE T0CKIE T0IE INTE 0000 0000 0000 0000

06h, Unbanked CPUSTA — — STKAV GLINTD TO PD POR BOR --11 11qq --11 qquu

16h, Bank 2 PR3L/CA1L Timer3 Period Register, Low Byte/Capture1 Register, Low Byte xxxx xxxx uuuu uuuu

17h, Bank 2 PR3H/CA1H Timer3 Period Register, High Byte/Cap ture1 Re gist er, High Byte xxxx xxxx uuuu uuuu

14h, Bank 3 CA2L Capture2 Low Byte xxxx xxxx uuuu uuuu

15h, Bank 3 CA2H Capture2 High Byte xxxx xxxx uuuu uuuu

12h, Bank 7 CA3L Capture3 Low Byte xxxx xxxx uuuu uuuu

13h, Bank 7 CA3H Capture3 High Byte xxxx xxxx uuuu uuuu

14h, Bank 7 CA4L Capture4 Low Byte xxxx xxxx uuuu uuuu

15h, Bank 7 CA4H Capture4 High Byte xxxx xxxx uuuu uuuu

Legend: x = unknown, u = unchange d, - = unimplemented, read as '0', q = value depends on condition.

Shaded cells are not used by Capture.

PIC17C7XX

DS30289B-page 114  2000 Microchip Technology Inc.

13.2.4 EXTERNAL CLOCK INPUT FOR

TIMER3

When TM R 3 CS is s et , th e 1 6 - bit T MR 3 i nc rem en ts on

the falling edge of clock input TCLK3. The input on the

RB5/TCLK3 pin is sampled and synchronized by the

internal phase clocks, twice every instruction cycle.

This causes a delay from the time a falling edge

appears on TCLK3 to the time TMR3 is actually incre-

mented. For the external clock input timing require-

ments, see the Electrical Specification section.

Figure 13-7 shows the timing diagram when operating

from an external clock.

13.2.5 READING/WRITING TIMER3

Since Timer3 is a 16-bit timer and only 8-bits at a time

can be read or written, care should be taken when

reading or writing while the timer is running. The best

method is to stop the timer, perform any read or write

operation and then restart Timer3 (using the TMR3ON

bit). However, if it is necessary to keep Timer3 free-

running, care must be taken. For writing to the 16-bit

TMR3, Example 13-2 may be used. For rea ding the 16-

bit TMR3, Example 13-3 may be used . Interrupts must

be d isabled during thi s rout ine.

EXAMPLE 13-2: WRITING TO TMR3

EXAMPLE 13-3: READING FROM TMR3

FIGURE 13-7: TIMER1, TIMER2 AND TIMER3 OPERATION (IN COUNTER MODE)

BSF CPUSTA, GLINTD ; Disable interrupts

MOVFP RAM_L, TMR3L ;

MOVFP RAM_H, TMR3H ;

BCF CPUSTA, GLINTD ; Done, enable interrupts

MOVPF TMR3L, TMPLO ; read low TMR3

MOVPF TMR3H, TMPHI ; read high TMR3

MOVFP TMPLO, WREG ; tmplo −> wreg

CPFSLT TMR3L ; TMR3L < wreg?

RETURN ; no then return

MOVPF TMR3L, TMPLO ; read low TMR3

MOVPF TMR3H, TMPHI ; read high TMR3

RETURN ; return

Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4 Q1Q2Q3Q4 Q1Q2Q3Q4Q1Q2Q3Q4

Instruction

Executed

MOVWF MOVFP

TMRx,WTMRx MOVFP

TMRx,W

Write to TMRx Read TMRx Read TMRx

34h 35h A8h A9h 00h

’A9h’’A9h’

TCLK12

TMR1, TMR2, or TMR3

PR1, PR2, or PR3H:PR3L

WR_TMR

RD_TMR

TMRxIF

Note 1: TCLK12 is sampled in Q2 and Q4.

2: ↓ indicates a sampling point.

3: The latency from TCLK12 ↓ to timer increment is between 2Tosc and 6Tosc.

or TCLK3

 2000 Microchip Technology Inc. DS30289B-page 115

PIC17C7XX

FIGURE 13-8: TIMER1, TIMER2 AND TIMER3 OPERATION (IN TIMER MODE)

Q1Q2Q3Q4 Q1Q2Q3Q4 Q1Q2Q3Q4 Q1Q2Q3Q4 Q1Q2Q3Q4 Q1Q2Q3 Q4 Q1Q2Q3Q4 Q1Q2Q3Q4 Q1Q2Q3Q4 Q1Q2 Q3Q4 Q1Q2 Q3Q4

AD15:AD0

ALE

Instruction

Fetched

TMR1

PR1

TMR1ON

WR_TMR1

WR_TCON2

TMR1IF

RD_TMR1 TMR1

Reads 03h TMR1

Reads 04h

MOVWF

TMR1

Write TMR1

MOVF

TMR1, W

Read TMR1

MOVF

TMR1, W

Read TMR1

BSF

TCON2, 0

Stop TMR1

BCF

TCON2, 0

Start TMR1

MOVLB 3 NOP NOP NOP NOP NOP

04h 05h 03h 04h 05h 06h 07h 08h 00h

PIC17C7XX

DS30289B-page 116  2000 Microchip Technology Inc.

NOTES:

 2000 Microchip Technology Inc. DS30289B-page 117

PIC17C7XX

14.0 UNIVERSAL SYNCHRONOUS

ASYNCHRONOUS RECEIVER

TRANSMITTER (USART)

MODULES

Each USART module is a serial I/O module. There are

two USART modules that are available on the

PIC17C7XX. They are specified as USART1 and

USAR T2. The de scription of the operation of these mod-

ules is generic in regard to the register names and pin

names used. Table 14-1 shows the generic names that

are used in the description of operation and the actual

names for both USART1 and USART2. Since the control

bits in each register have the same function, their names

are the same (there is no need to dif ferentiate).

The Transmit Status and Control Register (TXSTA) is

shown in Figure 14-1, while the Receive Status and

Control Register (RCSTA) is shown in Figure 14-2.

TABLE 14-1: USART MODULE GENERIC

NAMES

TXSTA2 REGISTER (ADDRESS: 15h, BANK 4)

Generic Name USART1 Name USART2 Name

Registers

RCSTA RCSTA1 RCSTA2

TXSTA TXSTA1 TXSTA2

SPBRG SPBRG1 SPBRG2

RCREG RCREG1 RCREG2

TXREG TXREG1 TXREG2

Interrupt Contro l Bit s

RCIE RC1IE RC2IE

RCIF RC1IF RC2IF

TXIE TX1IE TX2IE

TXIF TX1IF TX2IF

Pins

RX/DT RA4/RX1/DT1 RG6/RX2/DT2

TX/CK RA5/TX1/CK1 RG7/TX2/CK2

R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0 R-1 R/W-x

CSRC TX9 TXEN SYNC — — TRMT TX9D

bit 7 bit 0

bit 7 CSRC: Clock Source Select bit

Synchronous mode:

1 = Master mode (clock generated internally from BRG)

0 = Slave mode (clock from external source)

Asynchronous mode:

Don’t care

bit 6 TX9: 9-bit Transmit Select bit

1 = Selects 9-b it transmission

0 = Selects 8-b it transmission

bit 5 TXEN: Transmit Enable bit

1 = Transmit enabled

0 = Transmit disabled

SREN/CREN overrides TXEN in SYNC mode

bit 4 SYNC: USART Mode Select bit

(Synchronous/Asynchronous)

1 = Synchronous mode

0 = Asynchr ono us mo de

bit 3-2 Unimplemented: Read as '0'

bit 1 TRMT: Transmit Shift Register (TSR) Empty bit

1 = TSR empty

0 = TSR full

bit 0 TX9D: 9th bit of Transmit Data (can be used to calculate the parity in software)

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

- n = Value at POR Reset ’1’ = Bit is se t ’0’ = Bit is cleared x = Bit is unknown

PIC17C7XX

DS30289B-page 118  2000 Microchip Technology Inc.

The USART can be configured as a full duplex asyn-

chronous system that can communicate with peripheral

devices such as CRT terminals and personal comput-

ers, or it can be configured as a half duplex synchro-

nous system that can communicate with peripheral

devices such as A/D or D/A integrated circuits, Serial

EEPROMs etc. The USART can be configured in the

following modes:

•Asynchronous (full duplex)

•Synchronous - Master (half duplex)

•Synchronous - Slave (half duplex)

The SPEN (RCSTA<7>) bit has to be set in order to

configure the I/O pins as the Serial Communication

Interface (USART).

The USAR T module w ill control the direction of the RX/

DT and TX/CK pins, depending on the states of the

USART configuration bits in the RCSTA and TXSTA

registers. The bits that control I/O direction are:

•SPEN

•TXEN

•SREN

•CREN

•CSRC

RCSTA2 REGISTER (ADDRESS: 13h, BANK 4)

R/W-0 R/W-0 R/W-0 R/W-0 U-0 R-0 R-0 R-x

SPEN RX9 SREN CREN —FERR OERR RX9D

bit 7 bit 0

bit 7 SPEN: Serial Port Enable bit

1 = Configures TX/CK and RX/DT pins as serial port pins

0 = Serial port disabled

bit 6 RX9: 9-bit Receive Select bit

1 = Selects 9-bit reception

0 = Selects 8-bit reception

bit 5 SREN: Single Receive Enable bit

This bit enables the reception of a single byte. After receiving the byte, this bit is automatically

cleared.

Synchronous mode:

1 = Enable reception

0 = Disable recepti on

Note: This bit is ignored in synchronous slave reception.

Asynchronous mode:

Don’t care

bit 4 CREN: Continuous Rec eive Enable bit

This bit enables the continuous reception of serial data.

Asynchronous mode:

1 = Enable continuous reception

0 = Disables continuous reception

Synchronous mode:

1 = Enables contin uo us rec epti on until CREN is cleared (CREN overrides SREN)

0 = Disables continuous reception

bit 3 Unimplemented: Read as '0'

bit 2 FERR: Framing Error bit

1 = Framing error (updated by reading RCREG)

0 = No framing error

bit 1 bit OERR: Overrun Error bit

1 = Overrun (cleared by clearing CR EN)

0 = No overrun error

bit 0 RX9D: 9th bit of Receive Data (can be the software calculated parity bit)

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

- n = Value at POR Reset ’1’ = Bit i s set ’0’ = Bit is cleared x = Bit is unknown

 2000 Microchip Technology Inc. DS30289B-page 119

PIC17C7XX

FIGURE 14-1: USART TRANSMIT

FIGURE 14-2: USART RECEIVE

CK/TX

Sync/Async TSR

Start 0 1 7 8 Stop

• • •

÷ 16

÷ 4BRG

01 7

• • • 8Bit Count

TXIE

Interrupt

TXEN/

Write to TXREG

Clock

Sync/Async

TXSTA<0>

Sync

Master/Slave

Data Bus

Load

TXREG

RX 0178Stop • • •

÷ 16

÷ 4

BRG

Bit Count

Clock

Buffer

Logic

Buffer

Logic

SPEN

OSC

START

017RX9D • • • 017RX9D • • •

FERR

Majority

Detect Data MSb LSb

RSR

RCREG

Async/Sync

Sync/Async

Master/Slave

Sync

Enable

FIFO

Logic

Clk

FIFO

RCIE

Interrupt

RX9

Data Bus

SREN/

CREN/

Start_Bit

Async/Sync

Detect

PIC17C7XX

DS30289B-page 120  2000 Microchip Technology Inc.

14.1 USART Baud Rate Generator

(BRG)

The BRG supports both the Asynchronous and Syn-

chronous modes of the USART. It is a dedicated 8-bit

baud rate generator. The SPBRG register controls the

period of a free running 8-bit timer. Table 14-2 shows

the formula for computation of the baud rate for differ-

ent USAR T modes. Thes e only apply whe n the USART

is in Synchronous Master mode (internal clock) and

Asynchronous mode.

Given the desired b aud rate an d Fosc, the n earest inte-

ger value between 0 and 255 can be calculated using

the formula below. The error in baud rate can then be

determined.

TABLE 14-2: BAUD RATE FORMULA

Example 14-1 shows the calculation of the baud rate

error for the following conditions:

FOSC = 16 MHz

Desired Baud Rate = 9600

SYNC = 0

EXAMPLE 14-1: CALCULATING BAUD

RATE ERROR

Writing a new value to the SPBRG, causes the BRG

timer to be reset (or cleared). This ensures that the

BRG does not wait for a timer overflow before output-

ting the new baud rate.

Effects of Reset

After any device RESET, the SPBRG register is

cleared. The SPBRG register will need to be loaded

with the desired value after each RESET.

TABLE 14-3: REGISTERS ASSOCIATED WITH BAUD RATE GENERATOR

SYNC Mode Baud Rate

1Asynchronous

Synchronous FOSC/(64(X+1))

FOSC/(4(X+1))

X = value in SPBRG (0 to 255)

Desired Baud Rate = F OSC / (64 (X + 1) )

9600 = 16000000 /(64 (X + 1))

X = 25.042 → 25

Calculat ed Baud Ra te = 160 0000 0 / (64 (25 + 1))

= 9615

Error = (Calculate d Baud Rate - Desi red Baud Rate )

Desired Baud Rate

= (9615 - 9600) / 9600

=0.16%

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on

POR,

BOR MCLR, WDT

USART1

13h, Bank 0 RCSTA1 SPEN RX9 SREN CREN —FERR OERR RX9D 0000 -00x 0000 -00u

15h, Bank 0 TXSTA1 CSRC TX9 TXEN SYNC — — TRMT TX9D 0000 --1x 0000 --1u

17h, Bank 0 SPBRG1 Baud Rate Generator Register 0000 0000 0000 0000

USART2

13h, Bank 4 RCSTA2 SPEN RX9 SREN CREN —FERR OERR RX9D 0000 -00x 0000 -00u

15h, Bank 4 TXSTA2 CSRC TX9 TXEN SYNC — — TRMT TX9D 0000 --1x 0000 --1u

17h, Bank 4 SPBRG2 Baud Rate Generator Register 0000 0000 0000 0000

Legend: x = unknown, u = unchanged, - = unimplemented, read as '0'. Shaded cells are not used by the Baud Rate Generator.

 2000 Microchip Technology Inc. DS30289B-page 121

PIC17C7XX

TABLE 14-4: BAUD RATES FOR SYNCHRONOUS MODE

BAUD

RATE

(K)

FOSC = 33 MHz SPBRG

VALUE

(DECIMAL)

FOSC = 25 MHz SPBRG

VALUE

(DECIMAL)

FOSC = 20 MHz SPBRG

VALUE

(DECIMAL)

FOSC = 16 MHz SPBRG

VALUE

(DECIMAL)KBAUD %ERROR KBAUD %ERROR KBAUD %ERROR KBAUD %ERROR

0.3 NA ——NA ——NA ——NA ——

1.2 NA ——NA ——NA ——NA ——

2.4 NA ——NA ——NA ——NA ——

9.6 NA ——NA ——NA ——NA ——

19.2 NA ——NA ——19.53 +1.73 255 19.23 +0.16 207

76.8 77.10 +0.39 106 77.16 +0.47 80 76.92 +0.16 64 76.92 +0.16 51

96 95.93 -0.07 85 96.15 +0.16 64 96.15 +0.16 51 95.24 -0.79 41

300 294.64 -1.79 27 297.62 -0.79 20 294.1 -1.96 16 307.69 +2.56 12

500 485.29 -2.94 16 480.77 -3.85 12 500 0 9 500 0 7

HIGH 8250 —06250—05000—0 4000 —0

LOW 32.22 —255 24.41 —255 19.53 —255 15.625 —255

BAUD

RATE

(K)

FOSC = 10 MHz SPBRG

VALUE

(DECIMAL)

FOSC = 7.159 MHz SPBRG

VALUE

(DECIMAL)

FOSC = 5.068 MHz SPBRG

VALUE

(DECIMAL)KBAUD %ERROR KBAUD %ERROR KBAUD %ERROR

0.3 NA ——NA ——NA ——

1.2 NA ——NA ——NA ——

2.4 NA ——NA ——NA ——

9.6 9.766 +1.73 255 9.622 +0.23 185 9.6 0 131

19.2 19.23 +0.16 129 19.24 +0.23 92 19.2 0 65

76.8 75.76 -1.36 32 77.82 +1.32 22 79.2 +3.13 15

96 96.15 +0.16 25 94.20 -1.88 18 97.48 +1.54 12

300 312.5 +4.17 7 298.3 -0.57 5 316.8 +5.60 3

500 500 0 4 NA — —NA ——

HIGH 2500 —0 1789.8 —0 1267 —0

LOW 9.766 —255 6.991 —255 4.950 —255

BAUD

RATE

(K)

FOSC = 3.579 MHz SPBRG

VALUE

(DECIMAL)

FOSC = 1 MHz SPBRG

VALUE

(DECIMAL)

FOSC = 32.768 kHz SPBRG

VALUE

(DECIMAL)KBAUD %ERROR KBAUD %ERROR KBAUD %ERROR

0.3 NA ——NA ——0.303 +1.14 26

1.2 NA ——1.202 +0.16 207 1.170 -2.48 6

2.4 NA ——2.404 +0.16 103 NA ——

9.6 9.622 +0.23 92 9.615 +0.16 25 NA ——

19.2 19.04 -0.83 46 19.24 +0.16 12 NA ——

76.8 74.57 -2.90 1 1 83.34 +8.51 2 NA ——

96 99.43 _3.57 8 NA ——NA ——

300 298.3 -0.57 2 NA ——NA ——

500 NA ——NA ——NA ——

HIGH 894.9 —0250—0 8.192 —0

LOW 3.496 —255 0.976 —255 0.032 —255

PIC17C7XX

DS30289B-page 122  2000 Microchip Technology Inc.

TABLE 14-5: BAUD RATES FOR ASYNCHRONOUS MODE

BAUD

RATE

(K)

FOSC = 33 MHz SPBRG

VALUE

(DECIMAL)

FOSC = 25 MHz SPBRG

VALUE

(DECIMAL)

FOSC = 20 MHz SPBRG

VALUE

(DECIMAL)

FOSC = 16 MHz SPBRG

VALUE

(DECIMAL)KBAUD %ERROR KBAUD %ERROR KBAUD %ERROR KBAUD %ERROR

0.3 NA ——NA ——NA ——NA ——

1.2 NA ——NA ——1.221 +1.73 255 1.202 +0.16 207

2.4 2.398 -0.07 214 2.396 0.14 162 2.404 +0.16 129 2.404 +0.16 103

9.6 9.548 -0.54 53 9.53 -0.76 40 9.469 -1.36 32 9.615 +0.16 25

19.2 19.09 -0.54 26 19.53 +1.73 19 19.53 +1.73 15 19.23 +0.16 12

76.8 73.66 -4.09 6 78.13 +1.73 4 78.13 +1.73 3 83.33 +8.51 2

96 103.12 +7.42 4 97.65 +1.73 3 104.2 +8.51 2 NA ——

300 257.81 -14.06 1 390.63 +30.21 0 312.5 +4.17 0 NA ——

500 515.62 +3.13 0 NA ——NA ——NA ——

HIGH 515.62 —0—— 0312.5—0250—0

LOW 2.014 —255 1.53 —255 1.221 —255 0.977 —255

BAUD

RATE

(K)

FOSC = 10 MHz SPBRG

VALUE

(DECIMAL)

FOSC = 7.159 M Hz SPBRG

VALUE

(DECIMAL)

FOSC = 5.068 MHz SPBRG

VALUE

(DECIMAL)KBAUD %ERROR KBAUD %ERROR KBAUD %ERROR

0.3 NA ——NA ——0.31 +3.13 255

1.2 1.202 +0.16 129 1.203 _0.23 92 1.2 0 65

2.4 2.404 +0.16 64 2.380 -0.83 46 2.4 0 32

9.6 9.766 +1.73 15 9.322 -2.90 11 9.9 -3.13 7

19.2 19.53 +1.73 7 18.64 -2.90 5 19.8 +3.13 3

76.8 78.13 +1.73 1 NA ——79.2 +3.13 0

96 NA ——NA ——NA ——

300 NA ——NA ——NA ——

500 NA ——NA ——NA ——

HIGH 156.3 —0 111.9 —079.2—0

LOW 0.610 —255 0.437 —255 0.309 —255

BAUD

RATE

(K)

FOSC = 3.579 MHz SPBRG

VALUE

(DECIMAL)

FOSC = 1 MHz SPBRG

VALUE

(DECIMAL)

FOSC = 32.768 kHz SPBRG

VALUE

(DECIMAL)KBAUD %ERROR KBAUD %ERROR KBAUD %ERROR

0.3 0.301 +0.23 185 0.300 +0.16 51 0.256 -14.67 1

1.2 1.190 -0.83 46 1.202 +0.16 12 NA ——

2.4 2.432 +1.32 22 2.232 -6.99 6 NA ——

9.6 9.322 -2.90 5 NA ——NA ——

19.2 18.64 -2.90 2 NA ——NA ——

76.8 NA ——NA ——NA ——

96 NA ——NA ——NA ——

300 NA ——NA ——NA ——

500 NA ——NA ——NA ——

HIGH 55.93 —015.63—0 0.512 —0

LOW 0.218 —255 0.061 —255 0.002 —255

 2000 Microchip Technology Inc. DS30289B-page 123

PIC17C7XX

14.2 USART Asynchronous Mode

In this mode, the USART uses standard nonreturn-to-

zero (NRZ) format (one START bit, eight or nine data

bits, and one STOP bit). The most common data format

is 8-bits. An on-chip dedicated 8-bit baud rate genera-

tor c an be us ed to deriv e standa rd baud rate frequ en-

cies from the osc illator. The USART’s transmitter and

receive r are func tionally in depend ent but use the same

data format and baud rate. The baud rate generator

produces a clock x64 of the bit shift rate. Parity is not

supporte d by the hard ware, but can be imple mente d in

software (and stored as the ninth data bit). Asynchro-

nous mode is stopped during SLEEP.

The Asynchronous mode is selected by clearing the

SYNC bit (TXSTA<4>).

The USART As ynchronous module consists of the fol-

lowing components:

•Baud Rate Ge nera tor

•Sampling Circuit

•Asynchronous Transmitter

•Asynchronous Receiver

14.2.1 USART ASYNCHRONOUS

TRANSMITTER

The USART transmitter block diagram is shown in

Figure 14-1. The heart of the transmitter is the transmit

shift register (TSR). The shift register obtains its data

from the read/write transmit buffer (TXREG). TXREG is

loaded with data in software. The TSR is not loaded until

the STOP bit has been transmitted from the previous

load. A s s oo n as the STOP bit is trans m it ted , th e T SR is

loaded with new data from the TXREG (if available).

Once TXREG transfers the data to the TSR (occurs in

one TCY at the end of the current BRG cycle), the TXREG

is empty and an interrupt bit, TXIF, is set. This interrupt

can be enab led/ di sabl ed by s ettin g/cl earin g t he TXIE bit.

TXIF wi ll be s et, regardle ss of TXIE and c ann ot be re se t

in software. It will reset only when new data is loaded into

TXREG. Whil e TXIF indica tes the s tatus of the T XREG,

the TRMT (TXSTA<1>) bit shows the status of the TSR.

TRMT is a read only bit which is set when the TSR is

empty . No interrupt logic is tied to this bit, so the user has

to poll this bit in order to determine if the TSR is empty.

Transmission is enabled by setting the

TXEN (TXSTA<5> ) bit. The actua l transmi ssion wil l not

occur until TXREG has been loaded with data and the

baud rate generator (BRG) has produced a shift clock

(Figure 14-3). The transmission can also be started by

first loading TXREG and then setting TXEN. Normally,

when trans mission is first s tarte d, the TS R is e mpty, so

a transfer to TXR EG will resu lt in an immediat e transfer

to TS R, resul ting i n an empty TXREG. A back-t o-back

transfer is thus possible (Figure 14-4). Clearing TXEN

during a tr ans mi ss io n wi ll c aus e the tra ns mi ss ion to b e

aborted. This will reset the transmitter and the TX/CK

pin will revert to hi-impedance.

In order to select 9-bit transmission, the

TX9 (TXSTA<6>) bit should be set and the ninth bit

value should be written to TX9D (TXSTA<0>). The

ninth bit value must be written before writing the 8-bit

data to the TXREG. This is because a data write to

TXREG can result in an immediate transfer of the data

to the TSR (if the TSR is empty).

Steps to follow when setting up an Asynchronous

Transmission:

1. Initialize the SPBRG re gis ter for the ap prop ria te

baud rate.

2. Enable the asy nch ron ous seri al port by cle arin g

the SYNC bit and setting the SPEN bit.

3. If interrupts are desired, then set the TXIE bit.

4. If 9-bit tran smis si on is des ire d, th en s et the TX9

bit.

5. If 9-bit transmission is selected, the ninth bit

should be loa ded in TX9D.

6. Load data to the TXREG register.

7. Enable the transm ission by settin g TXEN (start s

transmission).

FIGURE 14-3: ASYNCHRONOUS MASTER TRANSMISSION

Note: The TSR is not mapped in data memory,

so it is not available to the user.

Word 1 STOP Bit

Word 1

Transmit Shift Reg

START Bit Bit 0 Bit 1 Bit 7/8

Write to TXREG Wo r d 1

BRG Output

(Shift Clock)

TXIF bit

TRMT bi t

(TX/CK pin)

PIC17C7XX

DS30289B-page 124  2000 Microchip Technology Inc.

FIGURE 14-4: ASYNCHRONOUS MASTER TRANSMISSION (BACK TO BACK)

TABLE 14-6: REGISTERS ASSOCIATED WITH ASYNCHRONOUS TRANSMISSION

Transmit Shift Reg.

Write to TXREG

BRG output

(shift clock)

TXIF bit

TRMT bi t

Word 1 Word 2

START Bit STOP Bit START Bit

Transmit Shift Reg.

Word 1 Word 2

Bit 0 Bit 1 Bit 7/8 Bit 0

Note: This timing diagram shows two conse cuti ve trans missions .

(TX/CK pin)

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on

POR,

BOR MCLR, WDT

16h, Bank 1 PIR1 RBIF TMR3IF TMR2IF TMR1IF CA2IF CA1IF TX1IF RC1IF x000 0010 u000 0010

17h, Bank 1 PIE1 RBIE TMR3IE TMR2IE TMR1IE CA2IE CA1IE TX1IE RC1IE 0000 0000 0000 0000

13h, Bank 0 RCSTA1 SPEN RX9 SREN CREN —FERR OERR RX9D 0000 -00x 0000 -00u

16h, Bank 0 TXRE G1 Serial Port Transmit Reg is ter (USART1 ) xxxx xxxx uuuu uuuu

15h, Bank 0 TXSTA1 CSRC TX9 TXEN SYNC — — TRMT TX9D 0000 --1x 0000 --1u

17h, Bank 0 SPBRG1 Baud Rate Generator Register (USART1) 0000 0000 0000 0000

10h, Bank 4 PIR2 SSPIF BCLIF ADIF —CA4IF CA3IF TX2IF RC2IF 000- 0010 000- 0010

11h, Bank 4 PIE2 SSPIE BCLIE ADIE —CA4IE CA3IE TX2IE RC2IE 000- 0000 000- 0000

13h, Bank 4 RCSTA2 SPEN RX9 SREN CREN —FERR OERR RX9D 0000 -00x 0000 -00u

16h, Bank 4 TXRE G2 Serial Port Transmit Reg is ter (USART2 ) xxxx xxxx uuuu uuuu

15h, Bank 4 TXSTA2 CSRC TX9 TXEN SYNC — — TRMT TX9D 0000 --1x 0000 --1u

17h, Bank 4 SPBRG2 Baud Rate Generator Register (USART2) 0000 0000 0000 0000

Legend: x = unknown, u = unchanged, - = unimplemented, read as a '0'. Shaded cells are not used for asynchronous transmission.

 2000 Microchip Technology Inc. DS30289B-page 125

PIC17C7XX

14.2.2 USART ASYNCHRONOUS

RECEIVER

The receiver block diagram is shown in Figure 14-2.

The data comes in the RX/DT pin and drives the data

recovery block. The data recovery block is actually a

high speed shifter operating at 16 times the baud rate,

whereas the main receive serial shifter operates at the

bit rate or at FOSC.

Once Asynchronous mode is selected, reception is

enabled by setting bit CREN (RCSTA<4>).

The heart of the receive r is the receive (s erial) shif t reg-

ister (RSR). After sampling the STOP bit, the received

data in the RSR is transferred to the RCREG (if it is

empty). If the transfer is complete, the interrupt bit,

RCIF, is set. The actual interrupt can be enabled/

disabled by setting/clearing the RCIE bit. RCIF is a

read only bit which is cleared by the hardware. It is

cleared when RCREG has been read and is empty.

RCREG is a double buffered register (i.e., it is a two-

deep FIFO). It is possible for two bytes of data to be

received and transferred to the RCREG FIFO and a

third by te begin shifti ng to the R SR. On d etection o f the

STOP bit of the third byte, if the RCREG is still full, then

the overrun error bit, OERR (RCSTA<1>) will be set.

The word in the RSR will be lost. RCREG can be read

twice to retrieve the two bytes in the FIFO. The OERR

bit has to be cleared i n software w hich is done by reset-

ting the receive logic (CREN is set). If the OERR bit is

set, trans fers from the RSR to RCREG are inhibited, so

it is essen tial to cle ar the OERR bit if it is set. The fram -

ing error bit FERR (RCSTA<2>) is set if a STOP bit is

not detected.

14.2.3 SAMPLING

The dat a on the RX/DT p in is samp led three t imes by a

majority detect circuit to determine if a high or a low

level is present at the RX/DT pin. The sam pling is done

on the seventh, eighth and ninth falling edges of a x16

clock (Figure 14-5).

The x16 clock is a free running clock and the three

sample points occur at a frequency of every 16 falling

edges.

FIGURE 14-5: RX PIN SAMPLING SCHEME

FIGURE 14-6: START BIT DETECT

Note: The F E RR an d t he 9th re cei ve bi t are buff-

ered the same way as the receive data.

Reading the RCREG register will allow the

RX9D and FERR b its to b e loaded wi th val-

ues for the next received data. Therefore,

it is essential for the user to read the

RCSTA register before reading RCREG, in

order not to lose the old FERR and RX9D

information.

Baud CLK

x16 CLK

START bit Bit0

Samples

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3

Baud CLK for all but START bit

(RX/DT pin)

x16 CLK

Q2, Q4 CLK

START bit

(RX/DT pin)

First rising edge of x16 clock after RX pin goes low

RX sampled low

PIC17C7XX

DS30289B-page 126  2000 Microchip Technology Inc.

Steps to follow when setting up an Asynchronous

Reception:

1. Initialize th e SPBRG re gis te r for the ap prop ria te

baud rate.

2. Enable the asynchronous serial port by clearing

the SYNC bit and setting the SPEN bit.

3. If interrupts are desired, then set the RCIE bit.

4. If 9-bit rece ption is de sired, then set the RX9 bi t.

5. Enable the reception by setting the CREN bit.

6. The RCIF bit will be set when reception com-

pletes and an interrupt will be generated if the

RCIE b it wa s set.

7. Read RCSTA to get the ni nth bit (if enabled) and

FERR bit to determine if an y error occurred dur-

ing reception.

8. Read RCREG for the 8-bit received data.

9. If an overrun error occurred, clear the error by

clearing the OERR bit.

FIGURE 14-7: ASYNCHRONOUS RECEPTION

TABLE 14-7: REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION

Note: To terminate a reception, either clear the

SREN and CREN bits, or the SPEN bit.

This will reset the receive logic, so that it

will be in the proper state when receive is

re-enabled.

START

bit bit7/8

bit1bit0 bit7/8 bit0STOP

bit

START

bit START

bit

bit7/8 STOP

bit

Reg

Rcv Buffer Reg

Rcv Shift

Read Rcv

Buffer Reg

RCREG

RCIF

(Interrupt Flag)

OERR bit

CREN

Word 1

RCREG Word 2

RCREG

STOP

bit

Note: This timing diagram shows three words appearing on the RX input. The RCREG (receive buffer) is read after the third word,

causing the OERR (overrun) bit to be set.

(RX/DT pin)

Word 3

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on

POR,

BOR MCLR, WDT

16h, Bank 1 PIR1 RBIF TMR3IF TMR2IF TMR1IF CA2IF CA1IF TX1IF RC1IF x000 0010 u000 0010

17h, Bank 1 PIE1 RBIE TMR3IE TMR2IE TMR1IE CA2IE CA1IE TX1IE RC1IE 0000 0000 0000 0000

13h, Bank 0 RCSTA 1 SPEN RX9 SREN CREN —FERR OERR RX9D 0000 -00x 0000 -00u

14h, Bank 0 RCREG1 RX7 RX6 RX5 RX4 RX3 RX2 RX1 RX0 xxxx xxxx uuuu uuuu

15h, Bank 0 TXSTA1 CSRC TX9 TXEN SYNC — — TRMT TX9D 0000 --1x 0000 --1u

17h, Bank 0 SPBRG1 Baud Rate Generator Register 0000 0000 0000 0000

10h, Bank 4 PIR2 SSPIF BCLIF ADIF —CA4IF CA3IF TX2IF RC2IF 000- 0010 000- 0010

11h, Bank 4 PIE2 SSPIE BCLIE ADIE —CA4IE CA3IE TX2IE RC2IE 000- 0000 000- 0000

13h, Bank 4 RCSTA 2 SPEN RX9 SREN CREN —FERR OERR RX9D 0000 -00x 0000 -00u

14h, Bank 4 RCREG2 RX7 RX6 RX5 RX4 RX3 RX2 RX1 RX0 xxxx xxxx uuuu uuuu

15h, Bank 4 TXSTA2 CSRC TX9 TXEN SYNC — — TRMT TX9D 0000 --1x 0000 --1u

17h, Bank 4 SPBRG2 Baud Rate Generator Register 0000 0000 0000 0000

Legend: x = unknown, u = unchanged, - = unimplemented, read as a '0'. Shaded cells are not used for asynchronous reception.

 2000 Microchip Technology Inc. DS30289B-page 127

PIC17C7XX

14.3 USART Synchronous Master

Mode

In Mas ter Synchron ous mode, the data is transmi tted in

a half -dupl ex mann er; i .e., t ransmis sion a nd recep tion

do not occur at the sa me time : whe n trans m itti ng data,

the reception is inhibited and vice versa. The synchro-

nous mode is entered by setting the SYNC

(TXST A< 4>) bit. In addition, the SPEN (RCSTA<7> ) bit

is set in order to configure the I/ O pins to CK (clock) and

DT (data) lines, respectively. The Master mode indi-

cates that the processor transmits the master clock on

the CK lin e. The Master m ode is e nter ed by se ttin g th e

CSRC (TXSTA<7>) bit.

14.3.1 USART SYNCHRONOUS MASTER

TRANSMISSION

The USART transmitter block diagram is shown in

Figure 14-1. T he hea rt of t he trans mitte r is the t ransm it

(serial) shi ft register (TSR). The shif t register obta ins its

data from the read/write transmit buffer TXREG.

TXREG is loaded with data in software. The TSR is not

loaded until the last bit has been transmitted from the

previous load. As soon as the last bit is transmitted, the

TSR is loaded with new dat a from TXREG (if available).

Once TXREG transfers the data to the TSR (occurs in

one TCY at the en d of the cur rent BRG cy cle), TXR EG

is empty and the TXIF bit is set. This interrupt can be

enabled / di sa ble d b y s et ting /c lea ring the TX IE bi t. T XIF

will be set regardl ess of the state of bit TXIE and cannot

be cleared in software. It will reset only when new data

is loaded into TXREG. While TXIF indicates the status

of TXREG, TRMT (TXSTA<1>) sh ows the s t atu s of th e

TSR. TRMT is a read only bit which is set when the

TSR is emp ty. No inte rrupt logic is tied to thi s bit, so the

user has to pol l this bit in o rder to dete rmi ne i f the TSR

is em pty. The TSR i s not map ped i n d at a m em ory, so it

is no t available to t he user.

Transmission is enabled by setting the TXEN

(TXSTA<5>) bit. The actual transmission will not occur

until TXREG has been loaded with data. The first data

bit will be shifted out on the next available rising edge

of the cl ock on the TX/CK pi n. Data o ut is stable a round

the falli ng edge of the synchronou s clock (Fig ure 14-9).

The transmission can also be started by first loading

TXREG and then setting TXEN. This is advantageous

when slow baud rates are selected, since BRG is kept

in RESET when the TXEN, CREN, and SREN bits are

clear. Setti ng the TXE N bi t wi ll s tart the BRG, cr eati ng

a shift clock immediately. Normally when transmission

is first started, the TSR is empty, so a transfer to

TXREG will res ul t i n a n i mmed iate trans fer to the TSR ,

resulting in an empty TXREG. Back-to-back transfers

are possible.

Clearing TXEN during a transmission will cause the

transmission to be aborted and will reset the transmit-

ter. The RX/DT and TX/CK pins will revert to hi-imped-

ance. If either CREN or SREN are set during a

transmission, the transmission is aborted and the RX/

DT pin reverts to a hi-impedance state (for a reception).

The TX/CK pin will remain an output if the CSRC bit is

set (internal clock). The transmitter logic is not reset,

although it is disconnected from the pins. In order to

reset the transmitter , the user has to clear the TXEN bit.

If the SREN bit is s et (to i nte rrup t a n on goi ng tra nsm is -

sion and receive a single word), then after the single

word is received, SREN will be cleared and the serial

port will revert back to transmitting, since the TXEN bit

is still set. The DT line will immediately switch from hi-

impeda nce Re ceive mode to tran smit an d st art driv ing.

To avoid this, TXEN should be cleared.

In order to select 9-bit transmission, the

TX9 (TXSTA<6>) bit should be set and the ninth bit

should be written to TX9D (TXSTA<0>). The ninth bit

must be writ ten before writi ng the 8-bit dat a to TXREG.

This is b ecaus e a dat a wri te to TXREG can re sult in an

immedi ate transfer of the dat a to the TSR (if the TSR is

empty). If the TS R wa s e mpt y an d TXRE G w as wr itte n

before writing the “new” TX9D, the “present” value of

TX9D is loaded.

Steps to follow when setting up a Synchronous Master

Transmission:

1. Initialize the SPBRG re gis ter for the ap prop ria te

baud rate (s ee Baud Rate Generator Se ction for

details).

2. Enable the synchronous master serial port by

setting the SYNC, SPEN, and CSRC bits.

3. Ensure that the CREN and SREN bits are clear

(these bits override transmission when set).

4. If interrupts are desired, then set the TXIE bit

(the GLIN TD b it m ust b e cl ear and th e PEI E bi t

must be set).

5. If 9-bit transmission is desired, then set the TX9 bit.

6. If 9-bit transmission is selected, the ninth bit

should be loa ded in TX9D.

7. S tart transmission by loading data to the TXREG

8. Enable the transmission by setting TXEN.

Writing the transmit data to the TXREG, then enabling

the transmit (setting TXEN), allows transmission to st art

sooner than doing these two events in the reverse order .

Note: To terminate a transmission, either clear

the SPEN bit, or the TXEN bit. This will

reset the transmit logic, so that it will be in

the proper state when transmit is re-

enabled.

PIC17C7XX

DS30289B-page 128  2000 Microchip Technology Inc.

TABLE 14-8: REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER TRANSMISSION

FIGURE 14-8: SYNCHRONOUS TRANSMISSION

FIGURE 14-9: SYNCHRONOUS TRANSMISSION (THROUGH TXEN)

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on

POR,

BOR MCLR, WDT

16h, Bank 1 PIR1 RBIF TMR3IF TMR2IF TMR1IF CA2IF CA1IF TX1IF RC1IF x000 0010 u000 0010

17h, Bank 1 PIE1 RBIE TMR3IE TMR2IE TMR1IE CA2IE CA1IE TX1IE RC1IE 0000 0000 0000 0000

13h, Bank 0 RCSTA 1 SPEN RX9 SREN CREN —FERR OERR RX9D 0000 -00x 0000 -00u

16h, Bank 0 TXREG1 TX7 TX6 TX5 TX4 TX3 TX2 TX1 TX0 xxxx xxxx uuuu uuuu

15h, Bank 0 TXSTA1 CSRC TX9 TXEN SYNC — — TRMT TX9D 0000 --1x 0000 --1u

17h, Bank 0 SPBRG1 Baud Rate Generator Register 0000 0000 0000 0000

10h, Bank 4 PIR2 SSPIF BCLIF ADIF —CA4IF CA3IF TX2IF RC2IF 000- 0010 000- 0010

11h, Bank 4 PIE2 SSPIE BCLIE ADIE —CA4IE CA3IE TX2IE RC2IE 000- 0000 000- 0000

13h, Bank 4 RCSTA 2 SPEN RX9 SREN CREN —FERR OERR RX9D 0000 -00x 0000 -00u

16h, Bank 4 TXREG2 TX7 TX6 TX5 TX4 TX3 TX2 TX1 TX0 xxxx xxxx uuuu uuuu

15h, Bank 4 TXSTA2 CSRC TX9 TXEN SYNC — — TRMT TX9D 0000 --1x 0000 --1u

17h, Bank 4 SPBRG2 Baud Rate Generator Register 0000 0000 0000 0000

Legend: x = unknown, u = unchanged, - = unimplemented, read as a '0'. Shaded cells are not used for synchronous master transmission.

Q1 Q2Q3Q4Q1 Q2Q3Q4Q1 Q2Q3Q4Q1 Q2Q3Q4Q1 Q2Q3 Q4 Q1 Q2Q3Q4Q1 Q2Q3 Q4Q1 Q2Q3Q4Q1 Q2Q3 Q4Q1 Q2Q3Q4Q1 Q2Q3 Q4Q3Q4

Write to

TXREG

TXIF

Interrupt Flag

TRMT

TXEN ’1’

Write Word 1 Wri te Word 2

bit0 bit1 bit2 bit7 bit0

Word 1 Word 2

(RX/DT pin)

(TX/CK pin)

Write to

TXREG

TXIF bit

TRMT bit

bit0 bit1 bit2 bit6 bit7

(RX/DT pin)

(TX/CK pin)

 2000 Microchip Technology Inc. DS30289B-page 129

PIC17C7XX

14.3.2 USART SYNCHRONOUS MASTER

RECEPTION

Once Synchronous mode is selected, reception is

enabled by set ting eit her the SREN (RCSTA<5>) bit or

the CREN (RCSTA<4>) bit. Dat a is sampled on th e RX/

DT pin on the falling edge of the clock. If SREN is set,

then only a single word is received. If CREN is set, the

reception is co ntin uo us u ntil CREN i s reset. If both bits

are set, then CREN takes precedence. After clocking

the last bit, the received data in the Receive Shift

If the transfer is complete, the interrupt bit RCIF is set.

The actual interrupt can be enabled/disabled by set-

ting/cl earing the R CIE bit. RCI F i s a r ead on ly b it whic h

is reset by the hardware. In this case, it is reset when

RCREG has been read and is empty . RCREG is a dou-

ble buffered register; i.e., it is a two deep FIFO. It is

possib le for tw o byt es of da ta t o be received and tran s-

ferred to the RCREG FIFO and a third byte to begin

shifting into the RSR. On the clocking of the last bit of

the third byte, if RCREG is still full, then the overrun

error bit OERR (RCSTA<1>) is set. The word in the

RSR will be lost. RCREG can be read twice to retrieve

the two bytes in the FIFO. The OERR bit has to be

cleared in software. This is done by clearing the CREN

bit. If OERR is set, transfers from RSR to RCREG are

inhibited, so it is essential to clear the OERR bit if it is

set. The 9th rece ive bit i s buf fered the same w ay as the

receive data. Reading the RCREG register will allow

the RX9D and FERR bits to be loaded with values for

the next received data; therefore, it is essential for the

user to read the RCSTA register before reading

RCREG in order not to lose the old FERR and RX9D

information.

Steps to follow when setting up a Synchronous Master

Reception:

1. Initialize the SPBRG re gis ter for the ap prop ria te

baud rate. See Section 14.1 for details.

2. Enable the synchronous master serial port by

setting bits SYNC, SPEN, and CSRC.

3. If interrupts are desired, then set the RCIE bit.

4. If 9-bit rece ption is de sired, then set th e RX9 bit.

5. If a single reception is required, set bit SREN.

For continuous reception set bit CREN.

6. The RCIF bit will be set when reception is com-

plete and an interrupt will be generated if the

RCIE bit was set.

7. Read RCSTA to get the ni nth bit (if enabled) and

determine if any error occurred during reception.

8. Read the 8-bit received data by reading

RCREG.

9. If any error occurred, clear the error by clearing

CREN.

FIGURE 14-10: SYNCHRONOUS RECEPTION (MASTER MODE, SREN)

Note: To terminate a reception, either clear the

SREN and CREN bits, or the SPEN bit.

This will reset t he receive logic so that it will

be in the proper state when receive is re-

enabled.

CREN bit

Write to the

SREN bit

RCIF bit

Read

RCREG

Note: Timing diagram demonstrates SYNC Master mode with SREN = 1.

Q3 Q4Q1 Q2Q3 Q4Q1Q2Q3Q4Q2 Q1Q2 Q3Q4Q1 Q2Q3 Q4 Q1 Q2Q3 Q4Q1 Q2Q3Q4 Q1 Q2Q3 Q4Q1Q2Q3 Q4 Q1Q2 Q3Q4

’0’

bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7

’0’

Q1Q2Q3Q4

(RX/DT pin)

(TX/CK pin)

PIC17C7XX

DS30289B-page 130  2000 Microchip Technology Inc.

TABLE 14-9: REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER RECEPTION