DS07-13607-5E
FUJITSU SEMICONDUCTOR
DATA SHEET
16-bit Proprietary Microcontrollers
CMOS
F2MC-16L MB90650A Series
MB90652A/653A/654A/F654A/V650A
DESCRIPTION
The MB90650A series are 16-bit microcontrollers designed for high speed real-time processing in consumer
product applications such as controlling cellular phones, CD-ROMs, or VTRs. Based on the F2MC*1-16L CPU
core, an F2MC-16L is used as the CPU. This CPU includes high-level language-support instructions and robust
task switching instructions, and additional addressing modes. In order to reduce the consumption current, dual-
clock (main/sub) is used. Furthermore, low consumption power supply is achieved by using stop mode, sleep
mode, watch mode, pseudo-watch mode, CPU intermittent operation mode.
Microcontrollers in this series have built-in peripheral resources including 10-bit A/D converter, 8-bit D/A converter,
UART, 8/16-bit PPG, 8/16-bit up/down counter/timer, I2C interface*2, 8/16-bit I/O timer (input capture, output
compare, and 16-bit free-run timer).
*1:F2MC stands for FUJITSU Flexible Microcontroller.
*2:Purchase of Fujitsu I2C components conveys a license under the Philips I2C Patent Rights to use these
components in an I2C system, provided that the system conf orms to the I2C Standard Specification as defined
by Philips.
FEATURES
F2MC-16L CPU
Minimum execution time: 83.3 ns/3 MHz oscillation (Uses PLL clock multiplication) maximum multiplier = 4
Instruction set optimized for controller applications
Object code compatibility with F2MC-16(H)
(Continued)
PACKAGES 100-pin plastic LQFP
(FPT-100P-M05)
100-pin plastic QFP
(FPT-100P-M06)
MB90650A Series
2
(Continued)
Wide range of data Types (bit, byte, word, and long word)
Improved instruction cycles provide increased speed
Additional addressing modes: 23 modes
High code efficiency
Access methods (bank access, linear pointer)
High precision operations are enhanced by use of a 32-bit accumulator
Extended intelligent I/O service (access area extended to 64 Kbytes)
Maximum memory space: 16 Mbytes
Enhanced high level language (C) and multitasking support instructions
Use of a system stack pointer
Enhanced pointer indirect instructions
Barrel shift instructions
Improved execution speed: Four byte instruction queue
Powerful interrupt function
Automatic data transfer function that does not use instruction (extended I2OS)
MB90650A Series
3
PRODUCT LINEUP
(Continued)
Part number
Item MB90652A MB90653A MB90654A MB90F654A MB90V650A*
Classification Mask ROM product Mask ROM
product FLASH
product For evaluation
ROM size 64 Kbytes 128 Kbytes 256 Kbytes
RAM size 3 Kbytes 5 Kbytes 8 Kbytes 6 Kbytes
Power supply voltage 2.2 V to 3.6 V 2.2 V to 3.6 V 2.4 V to 3.6 V 2.7 V to 5.5 V
CPU functions
The number of instructions : 340
Instruction bit length : 8/16 bits
Instruction length : 1 to 7 bytes
Data bit length : 1/4/8/16/32 bits
Minimum execution time : 83.3 ns/3 MHz (PLL multiplier = 4)
Interrupt processing time : 2 µs/12 MHz (minimum)
Ports
I/O ports (N-channel open-drain) : 4
I/O ports (CMOS) : 75 (Input pull-up resistors available: 24/
Can be set as N-channel open-drain: 8)
Total : 79
A/D converter
Analog inputs: 8 channels
10-bit resolution
Conversion time: minimum
8.17 µs/12 MHz
Analog inputs: 8 channels
10-bit resolution
Conversion time:
minimum 8.17 µs/12 MHz
D/A converter 2 channels (independent),
8-bit resolution, R-2R type
8/16-bit up/down
counter/timer 16 bits × 1 channel/8 bits × 2 channels selectable
Includes reload and compare functions.
I2C interface 1 channel
Master mode/slave mode available
UART 1 channel
Clock synchronous communication
Clock asynchronous communication
I/O extended serial
interface 8 bits × 2 channels
LSB-first or MSB-first operation selectable
8/16-bit PPG 8 bits × 2 channels/16 bits × 1 channel selectable
16-bit I/O timer 1 channel
(Input capture × 2 channels, output compare × 4 channels, and free-run timer × 1 channel)
DTP/external interrupt 8 inputs
Timer functions Timebase timer (18-bit)/watchdog timer (18-bit)/watch timer (15-bit)
DTMF generator Supports every ITU-T (CCITT) tone for output (Internal 12 MHz shall be used for
DTMF generator).
Low-power
consumption modes CPU intermittent operation mode, sub clock mode, stop mode, sleep mode,
watch mode, pseudo-watch mode
MB90650A Series
4
(Continued)
* : MB90V650A has products of single clock power supply and dual clock power supply.
Model : Single clock system MB90V650ACR-ES
Dual clock system MB90V650ACR-ES-H
Note : MB90V650A device is assured only when operate with the tools, under the condition of power supply
voltage : 2.7 V to 3.3 V, operating temperature: 0°C to 70°C and operating frequency: 1.5 MHz to 12 MHz
For more information about each package, see section “PACKAGE DIMENSIONS”.
Part number
Item MB90652A MB90653A MB90654A MB90F654A MB90V650A*
PLL function Selectable multiplier: 1/2/3/4
(Set a multiplier that does not exceed the assured operation frequency range.)
Other
Package FPT-100P-M05,
FPT-100P-M06 PGA-256C-A02
MB90650A Series
5
PIN ASSIGNMENTS
(Continued)
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
RST
PA1/OUT1
PA0/OUT0
P97/IN1
P96/IN0
P95/ZIN1
P94/BIN1
P93/AIN1/IRQ7
P92/ZIN0
P91/BIN0
P90/AIN0/IRQ6
P67/PPG11
P66/PPG10
P65/CKOT
P64/PPG01
P63/PPG00
P62/SCK2
P61/SOT2
P60/SIN2
DTMF
P86/OUT3
P85/IRQ5
P84/IRQ4
P83/IRQ3
P82/IRQ2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
P22/A18
P23/A19
P24/A20
P25/A21
P26/A22
P27/A23
P30/ALE
P31/RD
VSS
P32/WRL
P33/WRH
P34/HRQ
P35/HAK
P36/RDY
P37/CLK
P40/SIN0
P41/SOT0
P42/SCK0
P43/SIN1
P44/SOT1
VCC2
P45/SCK1
P46/ADTG
P47
P70/SDA
P71/SCL
P72
DVRH
DVSS
P73/DA00
P74/DA01
AVCC
AVRH
AVRL
AVSS
P50/AN0
P51/AN1
P52/AN2
P53/AN3
VSS
P54/AN4
P55/AN5
P56/AN6
P57/AN7
P80/IRQ0
P81/IRQ1
MD0
MD1
MD2
TEST
P21/A17
P20/A16
P17/AD15
P16/AD14
P15/AD13
P14/AD12
P13/AD11
P12/AD10
P11/AD09
P10/AD08
P07/AD07
P06/AD06
P05/AD05
P04/AD04
P03/AD03
P02/AD02
P01/AD01
P00/AD00
VCC1
X1
X0
VSS
X0A
X1A
PA2/OUT2
(Top view)
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
(FPT-100P-M05)
MB90650A Series
6
(Continued)
1P20
/
A16 2P21
/
A17 3P22
/
A18 4P23
/
A19 5P24
/
A20 6P25
/
A21 7P26
/
A22 8P27
/
A23 9P30
/
ALE 10P31
/
RD 11V
SS
12P32
/
WRL 13P33
/
WRH 14P34
/
HRQ 15P35
/
HAK 16P36
/
RDY 17P37
/
CLK 18P40
/
SIN0 19P41
/
SOT0 20P42
/
SCK0 21P43
/
SIN1 22P44
/
SOT1 23V
CC
2
24P45
/
SCK1 25P46
/
ADTG 26P47 27P70
/
SDA 28P71
/
SCL 29P72 30DVRH
X0A
X1A
PA2
/
OUT2
RST
PA1
/
OUT1
PA0
/
OUT0
P97
/
IN1
P96
/
IN0
P95
/
ZIN1
P94
/
BIN1
P93
/
AIN1
/
IRQ7
P92
/
ZIN0
P91
/
BIN0
P90
/
AIN0
/
IRQ6
P67
/
PPG11
P66
/
PPG10
P65
/
CKOT
P64
/
PPG01
P63
/
PPG00
P62
/
SCK2
P61
/
SOT2
P60
/
SIN2
DTMF
P86
/
OUT3
P85
/
IRQ5
P84
/
IRQ4
P83
/
IRQ3
P82
/
IRQ2
TEST
MD2
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
31
DV
SS
32
P73
/
DA00 33
P74
/
DA01 34
AV
CC
35
AVRH 36
AVRL 37
AV
SS
38
P50
/
AN0 39
P51
/
AN1 40
P52
/
AN2 41
P53
/
AN3 42
V
SS
43
P54
/
AN4 44
P55
/
AN5 45
P56
/
AN6 46
P57
/
AN7 47
P80
/
IRQ0 48
P81
/
IRQ1 49
MD0 50
MD1
P17
/
AD15
P16
/
AD14
P15
/
AD13
P14
/
AD12
P13
/
AD11
P12
/
AD10
P11
/
AD09
P10
/
AD08
P07
/
AD07
P06
/
AD06
P05
/
AD05
P04
/
AD04
P03
/
AD03
P02
/
AD02
P01
/
AD01
P00
/
AD00
V
CC
1
X1
X0
V
SS
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
(Top view)
(FPT-100P-M06)
MB90650A Series
7
PIN DESCRIPTION
(Continued)
Pin no. Pin name Circuit
type Function
LQFP*1QFP*2
80 82 X0 A Crystal oscillator pin
81 83 X1 A Crystal oscillator pin
77 79 X1A B Crystal oscillator pins (32 kHz)
78 80 X0A B Crystal oscillator pins (32 kHz)
47 to 49 49 to 51 MD0 to MD2 D Operating mode selection pins
Connect directly to VCC or VSS.
50 52 TEST D Test input pin
This pin must always be fixed to “H”.
75 77 RST C Reset input pin
83 to 90 85 to 92 P00 to P07 E
(STBC)
General-purpose I/O ports
Pull-up resistors can be set (RD07 to RD00 = “1”) using the
pull-up resistor setting register (RDR0).
The setting does not apply for ports set as outputs (D07 to D00
= “1”: invalid at the output setting).
AD00 to AD07 In external bus mode, the pins function as the lower data I/O or
lower address outputs (AD00 to AD07).
91 to 98 93 to 100 P10 to P17 E
(STBC)
General-purpose I/O ports
Pull-up resistors can be set (RD17 to RD10 = “1”) using the
pull-up resistor setting register (RDR1).
The setting does not apply for ports set as outputs (D17 to D10
= “1”: invalid at the output setting).
AD08 to AD15 In 16-bit external bus mode, the pins function as the upper data
I/O or middle address outputs (AD08 to AD15).
99, 100,
1 to 6 1, 2,
3 to 8
P20, P21,
P22 to P27 I
(STBC)
General-purpose I/O ports
In external bus mode, pins for which the corresponding bit in
the external address output control register (HACR) is “1”
function as the general-purpose I/O pots.
A16, A17,
A18 to A23
External address bus output pins (A16 to A23)
In external bus mode, pins for which the corresponding bit in
the external address output control register (HACR) is “0”
function as the upper address output pins (A16 to A23).
79
P30 I
(STBC)
General-purpose I/O port
Functions as the ALE pin in external bus mode.
ALE Functions as the address latch enable signal.
810
P31 I
(STBC)
General-purpose I/O port
Functions as the RD pin in external bus mode.
RD Functions as the read strobe output (RD).
10 12 P32 I
(STBC)
General-purpose I/O port
Functions as the WRL pin in external bus mode if the WRE bit
in the ECSR register is “1”.
WRL Functions as the lower data write strobe output (WRL).
MB90650A Series
8
(Continued)
Pin no. Pin name Circuit
type Function
LQFP*1QFP*2
11 13 P33 I
(STBC)
General-purpose I/O port
Functions as the WRH pin in 16-bit external bus mode if the
WRE bit in the ECSR register is “1”.
WRH Functions as the upper data write strobe output (WRH).
12 14 P34 I
(STBC)
General-purpose I/O port
Functions as the HRQ pin in external bus mode if the HDE bit
in the ECSR register is “1”.
HRQ Functions as the hold request input pin (HRQ).
13 15 P35 I
(STBC)
General-purpose I/O port
Functions as the HAK pin in external bus mode if the HDE bit in
the ECSR register is “1”.
HAK Functions as the hold acknowledge output (HAK) pin.
14 16 P36 I
(STBC)
General-purpose I/O port
Functions as the RDY pin in external bus mode if the RYE bit in
the ECSR register is “1”.
RDY Functions as the external ready input (RDY) pin.
15 17 P37 I
(STBC)
General-purpose I/O port
Functions as the CLK pin in external bus mode if the CKE bit in
the ECSR register is “1”.
CLK Functions as the machine cycle clock output (CLK) pin.
16 18 P40 H
(STBC)
General-purpose I/O port
When UART0 is operating, the data at the pin is used as the
serial input (SIN0).
Can be set as an open-drain output port (OD40 = “1”) by the
open-drain control register (ODR4).
The setting does not apply for ports set as inputs (D40 = “0”:
invalid at the input setting).
SIN0 Functions as the UART0 serial input (SIN0).
17 19 P41 G
(STBC)
General-purpose I/O port
Functions as the SOT0 pin if the SOE bit in the UMC register is
“1”.
Can be set as an open-drain output port (OD41 = “1”) by the
open-drain control register (ODR4).
The setting does not apply for ports set as inputs (D41 = “0”:
invalid at the input setting).
SOT0 Functions as the UART0 serial data output pin (SOT0).
MB90650A Series
9
(Continued)
Pin no. Pin name Circuit
type Function
LQFP*1QFP*2
18 20 P42 H
(STBC)
General-purpose I/O port
When UART0 is operating in external shift clock mode, the
data at the pin is used as the clock input (SCK0).
Also, functions as the SCK0 pin if the SOE bit in the UMC
register is “1”.
Can be set as an open-drain output port (OD42 = “1”) by the
open-drain control register (ODR4).
The setting does not apply for ports set as inputs (D42 = “0”:
invalid at the input setting).
SCK0 Functions as the UART0 serial clock I/O pin (SCK0).
19 21 P43 H
(STBC)
General-purpose I/O port
When I/O extended serial is operating, the data at the pin is
used as the serial input (SIN1).
Can be set as an open-drain output port (OD43 = “1”) by the
open-drain control register (ODR4).
The setting does not apply for ports set as inputs (D43 = “0”:
invalid at the input setting).
SIN1 Functions as the serial input for I/O extended serial data.
20 22 P44 G
(STBC)
General-purpose I/O port
Functions as the SOT1 pin if the SOE bit in the UMC register is
“1”.
Can be set as an open-drain output port (OD44 = “1”) by the
open-drain control register (ODR4).
The setting does not apply for ports set as inputs (D44 = “0”:
invalid at the input setting).
SOT1 Functions as the output pin (SOT1) for I/O extended serial
data.
22 24 P45 H
(STBC)
General-purpose I/O port
When I/O extended serial is operating in external shift clock
mode, the data at the pin is used as the clock input (SCK1).
Also, functions as the SCK1 pin if the SOE bit in the UMC
register is “1”.
Can be set as an open-drain output port (OD45 = “1”) by the
open-drain control register (ODR4).
The setting does not apply for ports set as inputs (D45 = “0”:
invalid at the input setting).
SCK1 Functions as the I/O extended serial clock I/O pin (SCK1).
23 25 P46 G
(STBC)
General-purpose I/O port
Can be set as an open-drain output port (OD46 = “1”) by the
open-drain control register (ODR4).
The setting does not apply for ports set as inputs (D46 = “0”:
invalid at the input setting).
ADTG Functions as the external trigger input pin for the A/D
converter.
24 26 P47 K
(NMOS/H)
(STBC)
Open-drain type general-purpose I/O port
MB90650A Series
10
(Continued)
Pin no. Pin name Circuit
type Function
LQFP*1QFP*2
36 to 39,
41 to 44 38 to 41,
43 to 46
P50 to P53,
P54 to P57 L
(STBC)
General-purpose I/O ports
AN0 to AN3,
AN4 to AN7 The pins are used as analog inputs (AN0 to AN7) when the A/D
converter is operating.
57 59 P60 F
(STBC)
General-purpose I/O port
A pull-up resistor can be set (RD60 = “1”) using the pull-up
resistor setting register (RDR6).
The setting does not apply for ports set as outputs (D60 = “1”:
invalid at the output setting).
SIN2 Functions as a data input pin (SIN2) for I/O extended serial.
58 60 P61 E
(STBC)
General-purpose I/O port
Function as the SOT2 pin if the SOE bit in the UMC register is
“1”.
A pull-up resistor can be set (RD61 = “1”) using the pull-up
resistor setting register (RDR6).
The setting does not apply for ports set as outputs (D61 = “1”:
invalid at the output setting).
SOT2 Functions as an output pin (SOT2) for I/O extended serial data.
59 61 P62 F
(STBC)
General-purpose I/O port
When I/O extended serial is operating in external shift clock
mode, the data at the pin is used as the clock input (SCK2).
Also, functions as the SCK2 pin if the SOE bit in the UMC
register is “1”.
A pull-up resistor can be set (RD62 = “1”) using the pull-up
resistor setting register (RDR6).
The setting does not apply for ports set as outputs (D62 = “1”:
invalid at the output setting).
SCK2 Functions as the I/O extended serial clock I/O pin (SCK2).
60 62 P63 E
(STBC)
General-purpose I/O port
A pull-up resistor can be set (RD63 = “1”) using the pull-up
resistor setting register (RDR6).
The setting does not apply for ports set as outputs (D63 = “1”:
invalid at the output setting).
PPG00 Functions as the PPG00 output when PPG output is enabled.
61 63 P64 E
(STBC)
General-purpose I/O port
A pull-up resistor can be set (RD64 = “1”) using the pull-up
resistor setting register (RDR6).
The setting does not apply for ports set as outputs (D64 = “1”:
invalid at the output setting).
PPG01 Functions as the PPG01 output when PPG output is enabled.
MB90650A Series
11
(Continued)
Pin no. Pin name Circuit
type Function
LQFP*1QFP*2
62 64 P65 E
(STBC)
General-purpose I/O port
A pull-up resistor can be set (RD65 = “1”) using the pull-up
resistor setting register (RDR6).
The setting does not apply for ports set as outputs (D65 = “1”:
invalid at the output setting).
CKOT Functions as the CKOT output when CKOT is operating.
63 65 P66 E
(STBC)
General-purpose I/O port
A pull-up resistor can be set (RD66 = “1”) using the pull-up
resistor setting register (RDR6).
The setting does not apply for ports set as outputs (D66 = “1”:
invalid at the output setting).
PPG10 Functions as the PPG10 output when PPG output is enabled.
64 66 P67 E
(STBC)
General-purpose I/O port
A pull-up resistor can be set (RD67 = “1”) using the pull-up
resistor setting register (RDR6).
The setting does not apply for ports set as outputs (D67 = “1”:
invalid at the output setting).
PPG11 Functions as the PPG11 output when PPG output is enabled.
25 27
P70
K
(NMOS/H)
(STBC)
Open-drain type I/O port
SDA
I2C interface data I/O pin
This function is valid when I2C interface operations are
enab led.
Set port output to Hi-Z (PDR = 1) during I2C interface
operations.
26 28
P71
K
(NMOS/H)
(STBC)
Open-drain type I/O port
SCL
I2C interface clock I/O pin
This function is valid when I2C interface operations are
enab led.
Set port output to Hi-Z (PDR = 1) during I2C interface
operations.
27 29 P72 K
(STBC) Open-drain type I/O port
30 32 P73 M
(STBC)
Open-drain type I/O port
Functions as a D/A output pin when DAE0 = “1” in the D/A
control register (DACR).
DA00 Functions as D/A output 0 when the D/A converter is operating.
31 33 P74 M
(STBC)
General-purpose I/O port
Functions as a D/A output pin when DAE1 = “1” in the D/A
control register (DACR).
DA01 Functions as D/A output 1 when the D/A converter is operating.
45 47 P80 JGeneral-purpose I/O port
IRQ0 Functions as external interrupt request I/O 0.
MB90650A Series
12
(Continued)
Pin no. Pin name Circuit
type Function
LQFP*1QFP*2
46 48 P81 JGeneral-purpose I/O port
IRQ1 Functions as external interrupt request I/O 1.
51 53 P82 JGeneral-purpose I/O port
IRQ2 Functions as external interrupt request I/O 2.
52 54 P83 JGeneral-purpose I/O port
IRQ3 Functions as external interrupt request I/O 3.
53 55 P84 JGeneral-purpose I/O port
IRQ4 Functions as external interrupt request I/O 4.
54 56 P85 JGeneral-purpose I/O port
IRQ5 Functions as external interrupt request I/O 5.
55 57 P86 I
(STBC)
General-purpose I/O port
This applies in all cases.
OUT3 Event output for channel 3 of the output compare
65 67
P90
J
General-purpose I/O port
AIN0 Input to channel 0 of the 8/16-bit up/down counter/timer
IRQ6 Functions as an interrupt request input.
66 68 P91 J
(STBC) General-purpose I/O port
BIN0 Input to channel 0 of the 8/16-bit up/down counter/timer
67 69 P92 J
(STBC) General-purpose I/O port
ZIN0 Input to channel 0 of the 8/16-bit up/down counter/timer
68 70
P93
J
General-purpose I/O port
AIN1 Input to channel 1 of the 8/16-bit up/down counter/timer
IRQ7 Functions as an interrupt request input.
69 71 P94 J
(STBC) General-purpose I/O port
BIN1 Input to channel 1 of the 8/16-bit up/down counter/timer
70 72 P95 J
(STBC) General-purpose I/O port
ZIN1 Input to channel 1 of the 8/16-bit up/down counter/timer
71 73 P96 J
(STBC) General-purpose I/O port
IN0 Trigger input for channel 0 of the input capture
72 74 P97 J
(STBC) General-purpose I/O port
IN1 Trigger input for channel 1 of the input capture
73 75 PA0 I
(STBC) General-purpose I/O port
OUT0 Event output for channel 0 of the output compare
MB90650A Series
13
(Continued)
*1: FPT-100P-M05
*2: FPT-100P-M06
Note : STBC = Incorporates standby control
NMOS = N-ch open-drain output
Pin no. Pin name Circuit
type Function
LQFP*1QFP*2
74 76 PA1 I
(STBC) General-purpose I/O port
OUT1 Event output for channel 1 of the output compare
76 78 PA2 I
(STBC) General-purpose I/O port
OUT2 Event output for channel 2 of the output compare
82 84 VCC1 Power supply (3.0 V) input pin
21 23 VCC2 Power supply (3.0 V/5.0 V) input pin
9, 40, 79 11, 42,
81 VSS Power supply (0.0 V) input pin
32 34 AVCC A/D converter power supply pin
33 35 AVRH A/D converter external reference power supply pin
34 36 AVRL A/D converter external reference power supply pin
35 37 AVSS A/D converter power supply pin
28 30 DVRH D/A converter external reference power supply pin
29 31 DVSS D/A converter power supply pin
56 58 DTMF N DTMF output pin
MB90650A Series
14
I/O CIRCUIT TYPE
(Continued)
Type Circuit Remarks
A
Oscillation feedback resistance: Approx.
1 M
B
Oscillation feedback resistance: Approx.
10 M
C
Hysteresis input with pull-up
Resistance approx. 50 k
D
Hysteresis input port
E
Incorporates pull-up resistor control
(for input)
CMOS level I/O
Resistance approx. 50 k
F
Incorporates pull-up resistor control
(for input)
CMOS level output
Hysteresis input
Resistance approx. 50 k
X1
X0
Standby control signal
X1A
X0A
Standby control signal
Hysteresis input
R
R
Hysteresis input
R
CTL
CMOS
R
CTL
Hysteresis input
R
MB90650A Series
15
(Continued)
Type Circuit Remarks
G
CMOS level I/O
Incorporates open-drain control
H
CMOS level output
Hysteresis input
Incorporates open-drain control
I
CMOS level I/O
J
CMOS level output
Hysteresis input
K
Hysteresis input
N-ch open-drain output
L
CMOS level I/O
Analog input
Open-drain control
signal
CMOS
R
Hysteresis input
Open-drain control
signal
R
CMOS
R
Hysteresis input
R
Hysteresis input
Digital output
R
CMOS
RAnalog input
MB90650A Series
16
(Continued)
Type Circuit Remarks
M
CMOS level I/O
Analog output
Shared with D/A outputs
N
DTMF analog output
CMOS
D/A output
R
R
R
R
MB90650A Series
17
HANDLING DEVICES
1. Preventing Latch-up
Latch-up occurs in a CMOS IC if a voltage greater than VCC or less than VSS is applied to an input or output pin
or if the voltage applied between VCC and VSS exceeds the rating.
If latch-up occurs, the power supply current increases rapidly resulting in thermal damage to circuit elements.
Therefore, ensure that maximum ratings are not exceeded in circuit operation.
For the same reason, also ensure that the analog supply voltage does not exceed the digital supply voltage.
2. Treatment of Unused Pins
Leaving unused input pins unconnected can cause misoperation. Always pull-up or pull-down unused pins.
3. External Reset Input
To reliably reset the controller by inputting an “L” level to the RST pin, ensure that the “L” level is applied for at
least five machine cycles. Take particular note when using an external clock input.
4. VCC and VSS Pins
Ensure that all VCC pins are at the same voltage. The same applies for the VSS pins.
5. Precautions when Using an External Clock
Drive the X0 pin only when using an external clock.
6. A/D Converter Power Supply and the Turn-on Sequence for Analog Inputs
Always tur n off the A/D converter power supply (AVCC, AVRH, AVRL) and analog inputs (AN0 to AN7) before
turning off the digital power supply (VCC).
When turning the power on or off, ensure that AVRH does not exceed AVCC.
Also, when using the analog input pins as input ports, ensure that the input voltage does not exceed AVCC.
7. Turn-on Sequence for D/A Converter Power Supply
Always turn on the D/A converter power supply (DVR), after turning off the digital power supply (VCC).
And in the turning off the pow er supply sequence always turn off the digital power supply (VCC) after turning off
the D/A converter power supply (DVR).
X0
X1
MB90650A Series
Using an external clock
MB90650A Series
18
8. Initializing
In this device there are some kinds of inner resisters which are initialized only by power on reset. It is possible
to initialize these resisters by turning on the power supply again.
9. Power Supply Pins
When there are several VCC and VSS pins, those pins that should have the same electric potential are connected
within the device when the device is designed in order to prevent misoperation, such as latchup. However, all
of those pins must be connected to the power supply and ground externally in order to reduce unnecessary
emissions, prevent misoperation of strobe signals due to an increase in the ground level, and to observe the
total output current standards.
In addition, give a due consideration to the connection in that current supply be connected to VCC and VSS with
the lowest possible impedance.
Finally, it is recommended to connect a capacitor of about 0.1 µF between VCC and VSS near this device as a
bypass capacitor.
10. Crystal Oscillation Circuit
Noise in the vicinity of the X0 and X1 pins will cause this device to operate incorrectly. Design the printed circuit
board so that the bypass capacitor connecting X0, X1 and the crystal oscillator (or ceramic oscillator) to ground
is located as close to the device as possible, and that the wiring does not cross the other wirings.
In addition, because printed circuit board artwork in which the area around the X0 and X1 pins is surrounded
by ground provides stable operation, such an arrangement is strongly recommended.
11. About 2 Power Supplies
The MB90650A series usually uses the 3-V power supply as the main po wer source. With Vcc1 = 3 V and Vcc2
= 5 V, how ev er , it can interf ace with P20/A16 to P27/A23, P30/ALE to P37/CLK, P40/SIN0 to P47, and P70/SD A
to P72 f or the 5-V power supply separ ately from the 3-V power supply at all operation mode . Note, how ev er , that
the analog power supplies such as A/D and D/A can be used only as 3-V power supplies.
12. When not Using a Sub Clock Signal
Also when the sub-clock is not used, X0A and X1A pins should be connected to an oscillator.
13. Caution on Operations during PLL Clock Mode
If the PLL clock mode is selected, the microcontroller attempt to be w orking with the self-oscillating circuit e ven
when there is no external oscillator or external clock input is stopped. Performance of this operation, however,
cannot be guaranteed.
MB90650A Series
19
BLOCK DIAGRAM
Clock control
circuit
RAM Interrupt controller
8/16-bit up/down
counter/timer
8 bits × 2 channels
(16 bits × 1 channel)
8 8 8 8 8 8 8 57
P00
to
P07
P10
to
P17
P20
to
P27
P30
to
P37
P40
to
P47
P50
to
P57
P60
to
P67
P70
to
P74
P80
to
P86
I/O ports
CPU
F
2
MC-16L family core
ROM
Prescaler
16-bit I/O timers
IN0, IN1
OUT1 to OUT3
DTP/external interrupt
8
P90
to
P97
2
6IRQ0 to IRQ5
IRQ6, IRQ7
3
PA0
to
PA2
5
X0, X1
RST
X0A, X1A
CKOT
(Output switching) × 1 channel
UART
SIN0
SOT0
SCK0
SIN1, SIN2
SOT1, SOT2
SCK1, SCK2
A/D converter
(10 bits)
AV
CC
AVRH, AVRL
AV
SS
ADTG
AN0 to AN7
Communications prescaler
D/A converter
(8 bits)
16-bit input capture × 2 channels
16-bit output compare × 4 channels
16-bit free-run timer × 1 channel
AIN0, AIN1
BIN0, BIN1
ZIN0, ZIN1
2
2
2
2
2
8
DA00, DA01
DVRH
DV
SS
P00 to P07 (8 pins) : Incorporates a pull-up resistor setting register (for input)
P10 to P17 (8 pins) : Incorporates a pull-up resistor setting register (for input)
P60 to P67 (8 pins) : Incorporates a pull-up resistor setting register (for input)
P40 to P46 (7 pins) : Incorporates an open-drain setting register
P47, P70 to P72 (4 pins) : Open-drain
PPG00, PPG01
PPG10, PPG11
8/16-bit PPG
Internal data bus
4
2
2
I
2
C interface SCL
SDA
2
2
2
2
I/O extended serial
interface × 2 channels
TEST, AD00 to AD15,
A16 to A23, ALE, RD,
WRL, WRH, HRQ,
HAK, RDY, CLK, N.C.,
MD0 to MD2, V
CC
, V
SS
Other pins
DTMF DTMF
MB90650A Series
20
MEMORY MAP
MB90652A, MB90653A, MB90V650A
Note : While the ROM data image of bank FF can be seen in the upper portion of bank 00, this is done only to permit
effective use of the C compiler’s small model. Because the lower 16 bits are the same, it is possible to
reference tables in ROM without declaring the “far” specification in the pointer.
For example, to access to 00C000H is to access to the ROM content of FFC000H in practice.
Because the ROM area of FF bank exceeds 48 Kbytes, all the area can be seen in bank 00.
So, the image for FF4000H to FFFFFFH can be seen in bank 00, while FE0000H to FF3FFFH can only be
seen in bank FF and FE.
ROM area
FFFFFFH
Address #1
FE0000H
010000H
Address #2
004000H
002000H
Address #3
000100H
0000C0H
000000H
Single chip mode Internal ROM/external bus mode External ROM/external bus mode
ROM area
ROM area
(FF bank image) ROM area
(FF bank image)
RAM Registers RAM Registers RAM Registers
Peripherals Peripherals Peripherals
: Internal access memory
: External access memory
: No access
* : Address #1, #2, and #3 are different owing to their devices respectively.
Type Address #1 Address #2
MB90652A
MB90653A
MB90V650A
FF0000H
FE0000H
(FE0000H)
004000H
004000H
004000H
000CFFH
0014FFH
0018FFH
Address #3 *
**
MB90650A Series
21
MB90654A, MB90F654A
Note : While the ROM data image of bank FF can be seen in the upper portion of bank 00, this is done only to permit
effective use of the C compiler’s small model. Because the lower 16 bits are the same, it is possible to
reference tables in ROM without declaring the “far” specification in the pointer.
For example, to access to 00C000H is to access to the ROM content of FFC000H in pr actice.
Because the ROM area of FF bank exceeds 48 Kbytes, all the area can be seen in bank 00.
So, the image for FF4000H to FFFFFFH can be seen in bank 00, while FE0000H to FF3FFFH can only be
seen in bank FF and FE.
FFFFFFH
010000H
002100H
000100H
0000C0H
000000H
RAMRAM RAM
Registers Registers Registers
Peripherals
Peripherals
Peripherals
ROM area
(FF bank image)
ROM area
(FF bank image)
ROM area
MB90654A*
MB90F654A* FC0000H
FC0000H
004000H
004000H0020FFH
0020FFH
: Internal access memory
: External access memory
: No access
Type Address #1 Address #2 Address #3
* : In the MB90654A and MB90F654A, RAM area 2000H is 2100H.
MB90650A Series
22
F2MC-16L CPU PROGRAMMING MODEL
Maximum 32 banks
R7 R6
R5 R4
R3 R2
R1 R0
RW3
RW2
RW1
RW0
16 bits
000180H + RP × 10H
RW7
RW6
RW5
RW4
RL3
RL2
RL1
RL0
ILM RP ISTNZVC
CCR
AH AL
DPR
PCB
DTB
USB
SSB
ADB
8 bits
16 bits
32 bits
Accumulator
USP
SSP
PS
PC
User stack pointer
System stack pointer
Processor status
Program counter
Direct page register
Program bank register
Data bank register
User stack bank register
System stack bank register
Additional data bank register
Dedicated registers
General-purpose registers
Processor status (PS)
MB90650A Series
23
I/O MAP
(Continued)
Address Register Register
name Read/
write Resource name Initial value
00HPort 0 data register PDR0 R/W Port 0 XXXXXXXXB
01HPort 1 data register PDR1 R/W Port 1 XXXXXXXXB
02HPort 2 data register PDR2 R/W Port 2 XXXXXXXXB
03HPort 3 data register PDR3 R/W Port 3 XXXXXXXXB
04HPort 4 data register PDR4 R/W Port 4 1XXXXXXXB
05HPort 5 data register PDR5 R/W Port 5 XXXXXXXXB
06HPort 6 data register PDR6 R/W Port 6 XXXXXXXXB
07HPort 7 data register PDR7 R/W Port 7 –––XX111B
08HPort 8 data register PDR8 R/W Port 8 –XXXXXXXB
09HPort 9 data register PDR9 R/W Port 9 XXXXXXXXB
0AHPort A data register PDRA R/W Port A –––––XXXB
0BH to 0FH(Reserved area)
10HPort 0 direction register DDR0 R/W Port 0 00000000B
11HPort 1 direction register DDR1 R/W Port 1 00000000B
12HPort 2 direction register DDR2 R/W Port 2 00000000B
13HPort 3 direction register DDR3 R/W Port 3 00000000B
14HPort 4 direction register DDR4 R/W Port 4 0000000B
15HPort 5 direction register DDR5 R/W Port 5 00000000B
16HPort 6 direction register DDR6 R/W Port 6 00000000B
17HPort 7 direction register DDR7 R/W Port 7 00B
18HPort 8 direction register DDR8 R/W Port 8 0000000B
19HPort 9 direction register DDR9 R/W Port 9 00000000B
1AHPort A direction register DDRA R/W Port A 000B
1BHPort 4 pin register ODR4 R/W Port 4 0000000B
1CHPort 0 resistance register RDR0 R/W Port 0 00000000B
1DHPort 1 resistance register RDR1 R/W Port 1 00000000B
1EHPort 6 resistance register RDR6 R/W Port 6 00000000B
1FHAnalog input enable register ADER R/W Port 5, A/D 11111111B
20HSerial mode register 0 SMR0 R/W
UART0
00000000B
21HSerial control register 0 SCR0 R/W 00000100B
22HSerial input register/
serial output register 0 SIDR/
SODR0 R/W XXXXXXXXB
MB90650A Series
24
(Continued)
Address Register Register
name Read/
write Resource name Initial value
23HSerial status register 0 SSR0 R/W UART0 0000100B
24HSerial mode control status register 0 SMCS0 R/W I/O extended serial
interface 0
––––0000B
25HSerial mode control status register 0 SMCS0 R/W 00000010B
26HSerial data register 0 SDR0 R/W XXXXXXXXB
27HClock division control register CDCR R/W Communications prescaler 0–––1111B
28HSerial mode control status register 1 SMCS1 R/W I/O extended serial
interface 1
––––0000B
29HSerial mode control status register 1 SMCS1 R/W 00000010B
2AHSerial data register 1 SDR1 R/W XXXXXXXXB
2BH to 2FH(Reserved area)
30HInterrupt/DTP enable register ENIR R/W
DTP/external interrupts
00000000B
31HInterrupt/DTP source register EIRR R/W 00000000B
32HRequest level setting register ELVR R/W 00000000B
33H00000000B
34H to 35H(Reserved area)
36HControl status register 1 ADCS1 R/W A/D converter
00000000B
37HControl status register 2 ADCS2 00000000B
38HData register 1 ADCR1 RXXXXXXXXB
39HData register 2 ADCR2 XXXXXXXXB
3AHD/A converter data register 0 DAT0 R/W
D/A converter
XXXXXXXXB
3BHD/A converter data register 1 DAT1 R/W XXXXXXXXB
3CHD/A control register channel 0 DACR0 R/W –––––––0B
3DHD/A control register channel 1 DACR1 R/W –––––––0B
3EHClock control register CLKR R/W Clock output control
register ––––0000B
3FH(Reserved area)
40HReload register lower channel 0 PRLL0 R/W
8/16-bit PPG
XXXXXXXXB
41HReload register upper channel 0 PRLH0 R/W XXXXXXXXB
42HReload register lower channel 1 PRLL1 R/W XXXXXXXXB
43HReload register upper channel 1 PRLH1 R/W XXXXXXXXB
44HPPG0 operation mode control register
channel 0 PPGC0 R/W 0X000XX1B
45HPPG1 operation mode control register
channel 1 PPGC1 R/W 0X000001B
46HPPG0, PPG1 output control register
channel 0, channel 1 PPGOE R/W 00000000B
47H to 4FH(Reserved area)
50HLower compare register channel 0 OCCP0 R/W 16-bit I/O timer output
compare (channel 0 to
channel 3) XXXXXXXXB
MB90650A Series
25
(Continued)
Address Register Register
name Read/
write Resource name Initial value
51HUpper compare register channel 0 OCCP0 R/W
16-bit I/O timer
Output compare
(channel 0 to channel 3)
XXXXXXXXB
52HLower compare register channel 1 OCCP1 R/W XXXXXXXXB
53HUpper compare register channel 1 XXXXXXXXB
54HLower compare register channel 2 OCCP2 R/W XXXXXXXXB
55HUpper compare register channel 2 XXXXXXXXB
56HLower compare register channel 3 OCCP3 R/W XXXXXXXXB
57HUpper compare register channel 3 XXXXXXXXB
58HCompare control status register channel 0 OCS0 R/W 0000––00B
59HCompare control status register channel 1 OCS1 R/W –––00000B
5AHCompare control status register channel 2 OCS2 R/W 0000––00B
5BHCompare control status register channel 3 OCS3 R/W –––00000B
5CH to 5FH(Reserved area)
60HLower input capture register channel 0 IPCP0 R
16-bit I/O timer
Input capture
(channel 0, channel 1)
XXXXXXXXB
61HUpper input capture register channel 0 R XXXXXXXXB
62HLower input capture register channel 1 IPCP1 R XXXXXXXXB
63HUpper input capture register channel 1 R XXXXXXXXB
64HInput capture control status register ICS0, 1 R/W 00000000B
65H(Reserved area)
66HLower timer data register TCDTL R/W 16-bit I/O timer
Free-run timer
00000000B
67HUpper timer data register TCDTH R/W 00000000B
68HTimer control status register TCCS R/W 00000000B
69H to 6FH(Reserved area)
70HUp/down count register channel 0 UDCR0 R
8/16-bit up/down
counter/timer
00000000B
71HUp/down count register channel 1 UDCR1 00000000B
72HReload compare register channel 0 RCR0 W00000000B
73HReload compare register channel 1 RCR1 00000000B
74HCounter status register channel 0 CSR0 R/W 00000000B
75H(Reserved area)
76HCounter control register channel 0 CCRL0 R/W 8/16-bit up/down
counter/timer
00001000B
77HCCRH0 00000000B
78HCounter status register channel 1 CSR1 R/W 00000000B
79H(Reserved area)
7AHCounter control register channel 1 CCRL1 R/W 8/16-bit up/down
counter/timer 00000000B
MB90650A Series
26
(Continued)
Address Register Register
name Read/
write Resource name Initial value
7BHCounter control register channel 1 CCRH1 R/W 8/16-bit up/down
counter/timer X0001000B
7CH to 7FH(Reserved area)
80HI2C bus status register IBSR R
I2C interface
00000000B
81HI2C bus control register IBCR R/W 00000000B
82HI2C bus clock control register ICCR R/W 0XXXXXB
83HI2C bus address register IADR R/W XXXXXXXB
84HI2C bus data register IDAR R/W XXXXXXXXB
85H to 87H(Reserved area)
88HDTMF control register DTMC 00000000B
89HDTMF data register DTMD 000X0000B
8A to 9EH(Reserved area) (Accessing 90H to 9EH is prohibited)
9FHDelayed interrupt generation/
release register DIRR R/W Delayed interrupt
generation module –––––––0B
A0HLow-power consumption mode
control register LPMCR R/W Low-power consumption
mode 00011000B
A1HClock selection register CKSCR R/W Low-power consumption
mode 11111100B
A2H to A4H(Reserved area)
A5HAuto-ready function selection register ARSR W External bus pin control circuit 0011––00B
A6HExternal address output control
register HACR W External bus pin control circuit 00000000B
A7HBus control signal selection register ECSR W External bus pin control circuit 0000*00–B
A8HWatchdog timer control register WDTC R/W Watchdog timer XXXXX111B
A9HTimebase timer control register TBTC R/W Timebase timer 100000B
AAHWatch timer control register WTC R/W Watch timer 1X–00000B
ABH to AFH(Reserved area)
MB90650A Series
27
(Continued)
About Programming
R/W : Readable and writable
R : Read only
W : Write only
Explanation of initial values
0: The initial value of this bit is “0”.
1: The initial value of this bit is “1”.
* :The initial value of this bit is “0” or “1”.
X:The initial value of this bit is undefined.
–: This bit is not used. The initial value is undefined.
Note : Areas below address 0000FFH not listed in the tab le are reserv ed areas. These addresses are accessed b y
internal access. No access signals are output on the external bus.
Address Register Register
name Read/
write Resource name Initial value
B0HInterrupt control register 00 ICR00 R/W
Interrupt controller
00000111B
B1HInterrupt control register 01 ICR01 R/W 00000111B
B2HInterrupt control register 02 ICR02 R/W 00000111B
B3HInterrupt control register 03 ICR03 R/W 00000111B
B4HInterrupt control register 04 ICR04 R/W 00000111B
B5HInterrupt control register 05 ICR05 R/W 00000111B
B6HInterrupt control register 06 ICR06 R/W 00000111B
B7HInterrupt control register 07 ICR07 R/W 00000111B
B8HInterrupt control register 08 ICR08 R/W 00000111B
B9HInterrupt control register 09 ICR09 R/W 00000111B
BAHInterrupt control register 10 ICR10 R/W 00000111B
BBHInterrupt control register 11 ICR11 R/W 00000111B
BCHInterrupt control register 12 ICR12 R/W 00000111B
BDHInterrupt control register 13 ICR13 R/W 00000111B
BEHInterrupt control register 14 ICR14 R/W 00000111B
BFHInterrupt control register 15 ICR15 R/W 00000111B
C0H to FFH(External area)
MB90650A Series
28
INTERRUPT VECTOR AND INTERRUPT CONTROL REGISTER ASSIGNMENTS TO
INTERRUPT SOURCES
: Indicates that the interrupt request flag is cleared by the I2OS interrupt clear signal.
: Indicates that the interrupt request flag is cleared by the I2OS interrupt clear signal (stop request present).
: Indicates that the interrupt request flag is not cleared by the I2OS interrupt clear signal.
Note: F or resources in which two interrupt sources share the same interrupt number , the I2OS interrupt clear signal
clears both interrupt request flags.
Interrupt source I2OS
support Interrupt vector Interrupt control register
Number Address Number Address
Reset ×#08 FFFFDCH——
INT 9 instruction ×#09 FFFFD8H——
Exception ×#10 FFFFD4H——
A/D converter #11 FFFFD0HICR00 0000B0H
Timebase timer interval interrupt ×#12 FFFFCCH
DTP/e xternal interrupt 0 (External interrupt 0) #13 FFFFC8HICR01 0000B1H
16-bit free-run timer (I/O timer) overflow #14 FFFFC4H
I/O extended serial interface 1 #15 FFFFC0HICR02 0000B2H
DTP/e xternal interrupt 1 (External interrupt 1) #16 FFFFBCH
I/O extended serial interface 2 #17 FFFFB8HICR03 0000B3H
DTP/e xternal interrupt 2 (External interrupt 2) #18 FFFFB4H
DTP/e xternal interrupt 3 (External interrupt 3) #19 FFFFB0HICR04 0000B4H
8/16-bit PPG 0 counter borrow #20 FFFFACH
8/16-bit up/down counter/timer 0 compare #21 FFFFA8HICR05 0000B5H
8/16-bit up/down counter/timer 0
underflow/overflow, up/down invert #22 FFFFA4H
8/16-bit PPG 1 counter borrow #23 FFFFA0HICR06 0000B6H
DTP/e xternal interrupt 4/5 (External interrupt 4/5) #24 FFFF9CH
Output compare (channel 2) match (I/O timer) #25 FFFF98HICR07 0000B7H
Output compare (channel 3) match (I/O timer) #26 FFFF94H
Watch prescaler ×#27 FFFF90HICR08 0000B8H
DTP/e xternal interrupt 6 (External interrupt 6) #28 FFFF8CH
8/16-bit up/down counter/timer 1 compare #29 FFFF88HICR09 0000B9H
8/16-bit up/down counter/timer 1
underflow/overflow, up/down invert #30 FFFF84H
Input capture (channel 0) read (I/O timer) #31 FFFF80HICR10 0000BAH
Input capture (channel 1) read (I/O timer) #32 FFFF7CH
Output compare (channel 0) match (I/O timer) #33 FFFF78HICR11 0000BBH
Output compare (channel 1) match (I/O timer) #34 FFFF74H
Completion of flash memory write/erase ×#35 FFFF70HICR12 0000BCH
DTP/e xternal interrupt 7 (External interrupt 7) #36 FFFF6CH
UART0 receive complete #37 FFFF68HICR13 0000BDH
UART0 transmit complete #39 FFFF60HICR14 0000BEH
I2C interface ×#41 FFFF58HICR15 0000BFH
Delayed interrupt generation module ×#42 FFFF54H
MB90650A Series
29
PERIPHERAL RESOURCES
1. Parallel Ports
(1) I/O Ports
Each port pin can be specified as either an input or output by its corresponding direction register when the pin
is not set f or use by a peripheral. When a port is set as an input, reading the data register alwa ys reads the value
corresponding to the pin le v el. When a port is set as an output, reading the data register reads the data register
latch value. The same applies when reading using a read-modify-write instruction.
When used as control outputs, reading the data register reads the control output value, irrespective of the direction
register value.
Note that if a read-modify-write instr uction (set bit or similar instruction) is used to set output data in the data
register before switching a pin from input to output, the instruction reads the input level at the pin and not the
data register latch value.
Data register
Direction register
Data register read
Data register write
Direction register write
Direction register read
Pin
Internal data bus
•Block diagram
MB90650A Series
30
(2) Port Direction Registers
Address : 000000HP07 P06 P05 P04 P03 P02 P01 P00
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 Initial value
Initial value
Access
Initial value
Access
Access
Initial value Access
Initial value Access
Initial value Access
Initial value Access
Initial value Access
Initial value Access
Initial value Access
Initial value Access
XXXXXXXXBR/W*
Port 0 data register (PDR0)
P17 P16 P15 P14 P13 P12 P11 P10
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
XXXXXXXXB
Address : 000001HR/W*
Port 1 data register (PDR1)
P27 P26 P25 P24 P23 P22 P21 P20
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
XXXXXXXXB
Address : 000002HR/W*
Port 2 data register (PDR2)
Address : 000003HP37 P36 P35 P34 P33 P32 P31 P30
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
XXXXXXXXBR/W*
Port 3 data register (PDR3)
Address : 000004HP47 P46 P45 P44 P43 P42 P41 P40
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
1XXXXXXXBR/W*
Port 4 data register (PDR4)
Address : 000005HP57 P56 P55 P54 P53 P52 P51 P50
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
XXXXXXXXBR/W*
Port 5 data register (PDR5)
Address : 000006HP67 P66 P65 P64 P63 P62 P61 P60
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
XXXXXXXXBR/W*
Port 6 data register (PDR6)
Address : 000007H P74 P73 P72 P71 P70
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
- - - XX111BR/W*
Port 7 data register (PDR7)
Address : 000008H P86 P85 P84 P83 P82 P81 P80
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
- XXXXXXXBR/W*
Port 8 data register (PDR8)
Address : 00000AH—————PA2PA1PA0
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
- - - - - XXXBR/W*
Port A data register (PDRA)
Address : 000009HP97 P96 P95 P94 P93 P92 P91 P90
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
XXXXXXXXBR/W*
Port 9 data register (PDR9)
R/W
X
: Readable and writable
: Unused
: Indeterminate
* : The operation of reading or writing to I/O ports is slightly different from reading or writing to memory , as follows.
Input mode
Read: Reads the corresponding pin level.
Write: Writes to the output latch.
Output mode
Read: Reads the value of the data register latch.
Write: The value is output from the corresponding pin.
MB90650A Series
31
(3) Port Direction Registers
(Continued)
D07 D06 D05 D04 D03 D02 D01 D00
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 Initial value Access
Initial value Access
Initial value Access
Initial value Access
Initial value Access
Initial value Access
Initial value Access
Initial value Access
Initial value Access
Initial value Access
Initial value Access
00000000BR/W*
D17 D16 D15 D14 D13 D12 D11 D10
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
00000000BR/W*
D27 D26 D25 D24 D23 D22 D21 D20
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
00000000BR/W*
D37 D36 D35 D34 D33 D32 D31 D30
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
00000000BR/W*
D46 D45 D44 D43 D42 D41 D40
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
-0000000BR/W*
D57 D56 D55 D54 D53 D52 D51 D50
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
00000000BR/W*
D67 D66 D65 D64 D63 D62 D61 D60
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
00000000BR/W*
D74 D73
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
---00---BR/W*
D86 D85 D84 D83 D82 D81 D80
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
-0000000BR/W*
—————DA2DA1DA0
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
-----000BR/W*
D97 D96 D95 D94 D93 D92 D91 D90
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
00000000BR/W*
R/W
: Readable and writable
: Unused
Address : 000010H
Address : 000011H
Address : 000012H
Address : 000013H
Address : 000014H
Address : 000015H
Address : 000016H
Address : 000017H
Address : 000018H
Address : 000019H
Address : 00001AH
Port 0 direction register (DDR0)
Port 1 direction register (DDR1)
Port 2 direction register (DDR2)
Port 3 direction register (DDR3)
Port 4 direction register (DDR4)
Port 5 direction register (DDR5)
Port 6 direction register (DDR6)
Port 7 direction register (DDR7)
Port 8 direction register (DDR8)
Port A direction register (DDRA)
Port 9 direction register (DDR9)
MB90650A Series
32
(Continued)
* : The operation of reading or writing to I/O ports is slightly diff erent from reading or writing to memory, as f ollo ws .
Input mode
Read: Reads the corresponding pin level.
Write: Writes to the output latch.
Output mode
Read: Reads the value of the data register latch.
Write: The value is output from the corresponding pin.
When pins are used as ports, the register bits control the corresponding pins as follows.
0: Input mode
1: Output mode
Bits are set to “0” by a reset.
P47, P70 to P72
No DDR for this port. Data is always available in this port, so when using P70 and P71 as I2C pin, set PDR
value to “1”. (Otherwise when using P70 and P71 by themselves, turn off the I2C.)
As this port is open-drain output style, so when using this port as an input port, in order to turn off the output
transistor, set the output data resister value to “1” and add the pull up resister to the external pin.
MB90650A Series
33
(4) Port Resistance Registers
Register configuration
•Block diagram
RD07 RD06 RD05 RD04 RD03 RD02 RD01 RD00
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 Initial value Access
00000000
B
R/W
Initial value Access
00000000
B
R/W
Initial value Access
00000000
B
R/W
RD17 RD16 RD15 RD14 RD13 RD12 RD11 RD10
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
RD67 RD66 RD65 RD64 RD63 RD62 RD61 RD60
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
Address : 00001C
H
Port 0 resistance register (RDR0)
Address : 00001D
H
Port 1 resistance register (RDR1)
Address : 00001E
H
Port 6 resistance register (RDR6)
R/W : Readable and writable
Data register
Direction register
Port I/O
Resistance register
Pull-up resistor (approx. 50 k)
Internal data bus
Notes : Input resistance register R/W
Controls the pull-up resistor in input mode.
0: Pull-up resistor disconnected in input mode.
1: Pull-up resistor connected in input mode.
The setting has no meaning in output mode (pull-up resistor disconnected).
The direction register (DDR) sets input or output mode.
The pull-up resistor is disconnected in hardware standb y or stop mode (SPL = 1) (high impedance).
This function is disabled when using an external bus mode. In this case , do not write to this register .
MB90650A Series
34
(5) Port Pin Register
Register configuration
•Block diagram
(6) Analog Input Enable Register
Register configuration
Controls each port 5 pin as follows.
0: Port input mode
1: Analog input mode
Set to “1” by a reset.
: Readable and writable
OD46 OD45 OD44 OD43 OD42 OD41 OD40
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
: Unused
Address : 00001B
H
Port 4 pin register (ODR4)
Initial value Access
-0000000
B
R/W
R/W
Data register
Direction register
Port I/O
Pin register
Internal data bus
Notes: Pin register R/W
Performs open-drain control in output mode.
0: Operate as a standard output port in output mode.
1: Operate as an open-drain output port in output mode.
The setting has no meaning in input mode (output Hi-z).
The direction register (DDR) sets input or output mode.
This function is disabled when using an e xternal bus mode. In this case, do not write to this register.
ADE7 ADE6 ADE5 ADE4 ADE3 ADE2 ADE1 ADE0
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
R/W : Readable and writable
Address : 00001F
H
Analog input enable register (ADER)
Initial value
11111111
B
Access
R/W
R/W R/W R/W R/W R/W R/W R/W
R/W
MB90650A Series
35
2. UART
The UART is a serial I/O port that can be used for CLK asynchronous (start-stop synchronization) or CLK
synchronous communications. The UART has the following features.
Full duplex, double buffered
Supports asynchronous (start-stop synchronization) and CLK synchronous data transfer
Supports multi-processor mode
Built-in dedicated baud rate generator
Supports flexible baud rate setting using an external clock
Error detect function (parity, framing, and overrun)
NRZ type transmission signal
Intelligent I/O service support
Asynchronous: 9615 bps, 31250 bps, 4808 bps, 2404 bps and 1202 bps
CLK synchronous: 1 Mbps, 500 Kbps, 250 Kbps, 125 Kbps and 62.5 Kbps For a 6, 8, 10 or 12 MHz
clock.
MB90650A Series
36
(1) Register Configuration
MD1 MD0 CS2 CS1 CS0
Reserved
SCKE SOE
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 Initial value
Initial value
Initial value
Initial value
Initial value
00000000B
PEN P SBL CL A/D REC RXE TXE
bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8
00000100B
D7 D6 D5 D4 D3 D2 D1 D0
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
XXXXXXXXB
PE ORE FRE RDRF TDRE
RIE TIE
bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8
00001-00B
Serial status register 0 (SSR0)
MD
——
DIV3 DIV2 DIV1 DIV0
bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8
0---1111B
Clock division control register (CDCR)
CDCR
SCR
SSR SIDR (R) /SODR (W)
SMR
8 bits
bit 15 bit 8 bit 7 bit 0
8 bits
R/W
R
W
X
: Readable and writable
: Read only
: Write only
: Unused
: Indeterminate
Address : 000020H
Serial mode register 0 (SMR0)
Address : 000021H
Serial control register 0 (SCR0)
Address : 000022H
Address : 000023H
Address : 000027H
Serial input register/serial output register 0 (SIDR/SODR0)
R/W
R/W R/W
R/W R/W R/W R/W R/W R/W R/W
R/W
R/W R/W R/W R/W R/W
R/W
R/W
R/W R/W R/W W R/W
R/W R/W R/W R/W R/W R/W R/W
RRRRRR
R/W
MB90650A Series
37
(2) Block Diagram
SMR
register SCR
register
Control signals
Dedicated baud rate generator
16-bit timer 0
(Connected internally)
External clock
SIN0
Clock select
circuit
Reception interrupt
(to CPU)
Transmission interrupt
(to CPU)
Reception control
circuit
Start bit detection
circuit
Reception bit
counter
Reception parity
counter
Transmission control
circuit
Transmission start
circuit
Transmission bit
counter
Transmission parity
counter
Reception status
determination circuit Reception shifter
End of
reception
Transmission shifter
Start of
transmission
Reception error
occurrence signal
for I2OS
(to CPU) SIDR SODR
Internal data bus
MD1
MD0
CS2
CS1
CS0
SCKE
SOE
SSR
register
Control signals
Transmission clock
pulses
Reception clock
pulses
SOT0, SOT1
PEN
P
SBL
CL
A/D
REC
RXE
TXE
PE
ORE
FRE
RDRF
TDRE
RIE
TIE
SCK0, SCK1
MB90650A Series
38
3. I/O Extended Serial Interface
I/O extended ser ial interface consists of an 8-bit serial I/O interface that can perfor m clock synchronous data
transfer. Either LSB-first or MSB-first data transfer can be selected.
The following two serial I/O operation modes are available.
• Internal shift clock mode: Data transfer is synchronized with the internal clock.
• External shift clock mode: Data transfer is synchronized with the clock input from the external pin (SCK). By
manipulating the general-purpose port that shares the external pin (SCK), this
mode also enables the data transfer operation to be driven by CPU instructions.
(1) Register Details
SMD2 SMD1 SMD0 SIE SIR BUSY STOP STRT
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
R/W R/W R/W R/W
R/W
R/W R/W R/W R/W R/W R/W R/W R/W
R/W R/W R/W
R/W*1 R R/W R/W*2
Initial value
Initial value
Initial value
00000010B
————
MODE BDS SOE SCOE ----0000B
bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8
R/W
R
X
: Readable and writable
: Read only
: Unused
: Indeterminate
D7 D6 D5 D4 D3 D2 D1 D0
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
XXXXXXXXB
Serial data register 0, 1 (SDR0, SDR1)
Address : 000025H
000029H
Address : 000024H
000028H
Address : 000026H
00002AH
Serial mode control status register 0, 1 (SMCS0, SMCS1)
*1: Only “0” can be written.
*2: Only “1” can be written. Reading always returns “0”.
This register controls the transfer operation mode of the serial I/O. The following describes the function of each bit.
bit 3: Serial mode selection bit (MODE)
This bit selects the conditions for starting operation from the halted state. Changing the mode during
operation is prohibited
The bit is initialized to “0” by a reset. The bit is readable and writable. Set to “1” when using the intelligent I/O
MODE Operation
0 Start when STRT is set to “1”. [Initial value]
1 Start on reading from or writing to the serial data register.
bit 2: Transfer direction selection bit (BDS: Bit Direction Select)
Selects as follows at the time of serial data input and output whether the data are to be transferred in
the order from LSB to MSB or vice versa.
MODE Operation
0 LSB-first [Initial value]
1 MSB-first
MB90650A Series
39
(2) Bloc k Diagram
Internal data bus
Internal data bus
(MSB-first) D0 to D7 Transfer direction selection
Read
Write
SDR (Serial data register)
Internal clock
Control circuit Shift clock counter
Interrupt
request
SIN1, SIN2
SOT1, SOT2
SCK1, SCK2
SMD2 SMD1 SMD0 SIE SIR BUSY STOP STRT MODE BDS
D7 to D0 (LSB-first)
21 0
SOE SCOE
MB90650A Series
40
4. A/D Converter
The A/D conv erter conv erts analog input voltages to digital values. The A/D con verter has the following f eatures.
Conversion time: Minimum of 8.167 µs per channel (for a 12 MHz machine clock)
Uses RC-type successive approximation conversion with a sample and hold circuit.
10-bit resolution
Eight program-selectable analog input channels
Single conversion mode: Selectively convert a one channel.
Scan conversion mode: Continuously convert multiple channels. Maximum of 8 program-
selectable channels.
Continuous conversion mode: Repeatedly convert specified channels.
Stop conversion mode: Convert one channel then halt until the next activation. (Enables
synchronization of the conversion start timing.)
An A/D conversion completion interrupt request to the CPU can be generated on the completion of A/D
conversion. This interrupt can activate I2OS to transfer the result of A/D conversion to memory and is suitable
for continuous operation.
Activation by software, external trigger (falling edge), or timer (rising edge) can be selected.
(1) Register Configuration
MD1 MD0 ANS2 ANS1 ANS0 ANE2 ANE1 ANE0
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 Initial value
Initial value
Initial value
Initial value
00000000
B
Control status register 1 (ADCS1)
BUSY INT INTE PAUS STS1 STS0 STRT DA
bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8
00000000
B
Control status register 2 (ADCS2)
76543210
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
XXXXXXXX
B
Data register 1 (ADCR1)
——————9 8
bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8
XXXXXXXX
B
Data register 2 (ADCR2)
: Readable and writable
: Read only
: Indeterminate
ADCS2
ADCR2 ADCR1
ADCS1
8 bits
bit 15 bit 8 bit 7 bit 0
8 bits
Address : 000036
H
Address : 000037
H
Address : 000038
H
Address : 000039
H
R/W R/W R/W R/W R/W R/W R/W R/W
R/W R/W R/W R/W R/W R/W R/W R/W
R
RRRRRRRR
RRRRRRR
R/W
R
X
MB90650A Series
41
(2) Bloc k Diagram
AVCC AVRH
AVRL
AN0
AN1
AN2
AN3
AN4
AN5
AN6
AN7
MPX
Sample and
hold circuit
Comparator
D/A converter
Successive
approximation register
Data register
A/D control register 1
A/D control register 2
ADCR1, ADCR2
ADCS1, ADCS2
ADTG PPG01
φ
Timer activation
Trigger activation
Operating clock
Prescaler
AVSS
Input circuit
Decoder
Internal data bus
MB90650A Series
42
5. D/A Converter
D/A conv erter is an R-2R type D/A conv erter with 8-bit resolution. The device contains tw o D/A conv erters. The
D/A control register controls the output of the two D/A converters independently.
(1) Register Configuration
Address : 00003AHDA07 DA06 DA05 DA04 DA03 DA02 DA01 DA00
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
Initial value
Initial value
Initial value
Initial value
XXXXXXXXB
D/A converter data register 0 (DAT0)
Address : 00003BHDA17 DA16 DA15 DA14 DA13 DA12 DA11 DA10
bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8
XXXXXXXXB
D/A converter data register 1 (DAT1)
Address : 00003CH
———
——————
——
DAE0
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
-------0B
D/A control register channel 0 (DACR0)
Address : 00003DH———————
———————
DAE1
bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8
-------0B
D/A control register channel 1 (DACR1)
X: Unused
: Indeterminate
R/W
R/W R/W R/W R/W R/W R/W R/W R/W
R/W
R/W
R/W R/W R/W R/W R/W R/W R/W
R/W : Readable and writable
MB90650A Series
43
(2) Bloc k Diagram
Internal data bus
DA
17 DA
16 DA
15 DA
14 DA
13 DA
12 DA
11 DA
10 DA
07 DA
06 DA
05 DA
04 DA
03 DA
02 DA
01 DA
00
DAE1
Standby control Standby control
2R 2R
2R
2R
R
R
R
DVR
DA17
DA16
DA15
DA11
DA10
DA output
channel 1
DAE0
2R 2R
2R
2R
R
R
R
DVR
DA07
DA06
DA05
DA01
DA00
DA output
channel 0
2R 2R
MB90650A Series
44
6. 8/16-bit PPG
8/16-bit PPG is an 8-bit reload timer module. The block performs PPG output in which the pulse output is
controlled by the operation of the timer.
The hardware consists of two 8-bit down-counters, four 8-bit reload registers, one 16-bit control register, two
external pulse output pins, and two interrupt outputs. The PPG has the following functions.
8-bit PPG output in two channels independent operation mode:
Two independent PPG output channels are available.
16-bit PPG output operation mode: One 16-bit PPG output channel is available.
8 + 8-bit PPG output operation mode: Variable-period 8-bit PPG output operation is available by using the
output of channel 0 as the clock input to channel 1.
PPG output operation: Outputs pulse waveforms with variable period and duty ratio. Can be
used as a D/A converter in conjunction with an external circuit.
(1) Register Configuration
Address : 000044
H
PEN0 PE00 PIE0 PUF0
Reserved
R/W — R/W R/W R/W
Initial value
0X000XX1
B
PPG0 operation mode control register channel 0 (PPGC0)
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
Address : 000045
H
PEN1 PE10 PIE1 PUF1 MD1 MD0
Reserved
R/W R/W R/W R/W R/W R/W
Initial value
0X000001
B
PPG1 operation mode control register channel 1 (PPGC1)
bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8
: Readable and writable
: Indeterminate
Address : 000046
H
PCS2 PCS1 PCS0 PCM2 PCM1 PCM0 PE11 PE01
R/W R/W R/W R/W R/W R/W R/W R/W
Initial value
00000000
B
PPG0, PPG1 output control register channel 0, channel 1 (PPGOE)
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
Address : 000041
H
000043
H
R/W R/W R/W R/W R/W R/W R/W R/W
Initial value
XXXXXXXX
B
Reload register upper channel 0, channel 1 (PRLH0, PRLH1)
bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8
Address : 000040
H
000042
H
R/W R/W R/W R/W R/W R/W R/W R/W
Initial value
XXXXXXXX
B
Reload register lower channel 0, channel 1 (PRLL0, PRLL1)
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
R/W
X
MB90650A Series
45
(2) Bloc k Diagram
PPG0
output latch
PCNT (Down-counter) S
R
Q
PPG00 output enable
PPG01 output enable
L/H selector
PRLBH0
PPGC0
Peripheral clock divided by 16
Peripheral clock divided by 8
Peripheral clock divided by 4
Peripheral clock divided by 2
Peripheral clock
PRLL0
PRLH0
L-side data bus
H-side data bus
PPG00
PPG01
ClearInvert
PEN0
Reload Channel 1-borrow
IRQ
Count clock
selection
Timebase counter output
Main clock divided by 512
L/H select
PIE0
PUF0
(Operation mode control)
A/D converter
8/16-bit PPG (channel 0)
MB90650A Series
46
ClearInvert
PPG1
output latch
PCNT (Down-counter) S
R
Q
PPG10 output enable
PPG11 output enable
L/H selector
PRLBH1
PPGC1
PRLL1
PRLH1
L-side data bus
H-side data bus
PPG10
PPG11
PEN1
Reload
Channel 0-borrow IRQ
L/H select
PIE
PUF
UART
Peripheral clock divided by 16
Peripheral clock divided by 8
Peripheral clock divided by 4
Peripheral clock divided by 2
Peripheral clock
Count clock
selection
Timebase counter output
Main clock divided by 512
(Operation mode control)
8/16-bit PPG (channel 1)
MB90650A Series
47
7. 8/16-bit Up/Down Counter/Timer
8/16-bit up/down counter/timer is an up/down counter/timer and consists of six event input pins, two 8-bit up/
down counters, two 8-bit reload/compare registers, and their control circuits.
(1) Main Functions
The 8-bit count register can count in the range 0 to 256 (or 0 to 65535 in 1 × 16-bit operation mode).
The count clock selection can select between four different count modes.
Count modes
Two different internal count clocks are available in timer mode.
Count clock (at 12 MHz operation)
In up/down count mode, you can select which edge to detect on the external pin input signal.
Detected edge
Phase difference count mode is suitable for motor encoder counting. By inputting the A, B, and Z phase outputs
from the encoder, a high-precision rotational angle, speed, or similar count can be implemented simply.
Two different functions can be selected for the ZIN pin.
ZIN pin
Compare and reload functions are available and can be used either independently or together. A variable-
width up/down count can be performed by activating both functions.
Compare/reload function
Whether or not to generate an interrupt when a compare, reload (underflow), or overflow occurs can be set
independently.
The previous count direction can be determined from the count direction flag.
An interrupt can be generated when the count direction changes.
Timer mode
Up/down counter mode
Phase difference count mode (× 2)
Phase difference count mode (× 8)
166 ns (6 MHz: Divide by 2)
0.67 µs (1.5 MHz: Divide by 8)
Detect falling edges
Detect rising edges
Detect both rising and falling edges
Edge detection disabl ed
Counter clear function
Gate function
Compare function (Output an interrupt when a compare
occurs.)
Compare function (Output an interrupt and clear the
counter when a compare occurs.)
Reload function (Output an interrupt and reload when
an underflow occurs.)
Compare/reload function
(Output an interrupt and clear the counter when a com-
pare occurs. Output an interrupt and reload when an
underflow occurs.)
Compare/reload disabled
MB90650A Series
48
(2) Register Configuration
Address : 000070
H
D07 D06 D05 D04 D03 D02 D01 D00
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 Initial value
Initial value
Initial value
Initial value
Initial value
Initial value
Initial value
Initial value
00000000
B
Up/down count register channel 0 (UDCR0)
Address : 000071
H
D17 D16 D15 D14 D13 D12 D11 D10
bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8
00000000
B
Up/down count register channel 1 (UDCR1)
Address : 000072
H
D07 D06 D05 D04 D03 D02 D01 D00
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
00000000
B
Reload compare register channel 0 (RCR0)
Address : 000073
H
D17 D16 D15 D14 D13 D12 D11 D10
bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8
00000000
B
Reload compare register channel 1 (RCR1)
Address : 000074
H
000078
H
CSTR CITE UDIE CMPF OVFF UDFF UDF1 UDF0
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
Counter status register channel 0, channel 1 (CSR0, CSR1)
CCRH0
(Reversed area)
CCRH1 CCRL1
CSR1
CCRL0
UDCR1
RCR1
(Reversed area) CSR0
RCR0
UDCR0
8 bits
bit 15 bit 8 bit 7 bit 0
8 bits
00000000
B
Address : 000076
H
00007A
H
CTUT UCRE RLDE UDCC CGSC CGE1 CGE0
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
Counter control register channel 0, channel 1 (CCRL0, CCRL1)
00001000
B
00000000
B
Address : 000077
H
M16E CDCF CFIE CLKS CMS1 CMS0 CES1 CES0
bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8
Counter control register channel 0 (CCRH0)
00000000
B
Address : 00007B
H
CDCF CFIE CLKS CMS1 CMS0 CES1 CES0
bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8
Counter control register channel 1 (CCRH1)
X0001000
B
RRR
R
RRRR
RRR
R
RRRR
WWWWWWWW
WWWWWWWW
R/W R/W R/W R/W R/W R/W
R/W R/W R/W R/W R/W R/W R/W
R/W R/W R/W R/W R/W R/W R/W R/W
R/W R/W R/W R/W R/W R/W R/W
RR
: Readable and writable
: Read only
: Write only
R/W
R
W
: Unused
X
: Indeterminate
MB90650A Series
49
(3) Bloc k Diagram
Internal data bus
CGE1 CGE0 C/GS
Carry
CMS1 CMS0
CES1 CES0
CITE UDIE
UDF1 UDF0 CDCF CFIE
Edge or level detection
RCR0 (Reload/compare register 0)
CTUT
UCRE RLDE
Reload control
UDCC Counter clear
UDCR0 (Up/down count register 0)
CMPF
UDFF OVFF
Prescaler
CLKS
CSTR
Up/down count
clock selection
Count clock
Interrupt output
8 bits
8 bits
AIN0
BIN0
ZIN0
8/16-bit up/down counter/timer (channel 0)
MB90650A Series
50
Internal data bus
CGE1 CGE0 C/GS
Carry CITE UDIE
UDF1 UDF0 CDCF CFIE
Edge or level detection
RCR1 (Reload/compare register 1)
CTUT
UCRE RLDE
Reload control
UDCC Counter clear
UDCR1 (Up/down count register 1)
CMPF
UDFF OVFF
Prescaler
CLKS
CSTR
Up/down count
clock selection
Count clock
Interrupt output
8 bits
8 bits
AIN1
BIN1
ZIN1
CMS1 CMS0 CES1 CES0 EN16
8/16-bit up/down counter/timer (channel 1)
MB90650A Series
51
8. Clock Output Control Register
Clock output control register outputs the divided machine clock.
(1) Register Configuration
Address : 00003EH————CKEN FRQ2 FRQ1 FRQ0
R/W R/W R/W R/W
Initial value
----0000B
Clock control register (CLKR)
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
R/W
: Readable and writable
: Unused
bit 3: Clock output enable bit (CKEN)
bit 2 to bit 0: Clock output frequency select bit (FRQ2 to FRQ0)
MODE Operation
0 Operate as a standard port.
1 Operate as the clock output.
FRQ2 FRQ1 FRQ0 Output clock φ = 12 MHz φ = 8 MHz φ = 4 MHz
000 φ/21167 ns 250 ns 500 ns
001 φ/22333 ns 500 ns 1 µs
010 φ/23667 ns 1 µs2 µs
011 φ/241.33 µs2 µs4 µs
100 φ/252.67 µs4 µs8 µs
101 φ/265.33 µs8 µs16 µs
110 φ/2710.67 µs16 µs32 µs
111 φ/2821.33 µs32 µs64 µs
MB90650A Series
52
9. DTP/External Interrupts
The DTP (Data Transfer Peripheral) is a peripheral block that interfaces external peripherals to the F2MC-16L
CPU. The DTP receives DMA and interrupt processing requests from external peripherals and passes the
requests to the F2MC-16L CPU to activate the intelligent I/O service or interrupt processing. Two request levels
(“H” and “L”) are provided for the intelligent I/O service. For external interrupt requests, generation of interrupts
on a rising or falling edge as well as on “H” and “L” levels can be selected, giving a total of four types.
(1) Register Configuration
(2) Bloc k Diagram
Address : 000030HEN7 EN6 EN5 EN4 EN3 EN2 EN1 EN0
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 Initial value
Initial value
Initial value
Initial value
00000000B
Interrupt/DTP enable register (ENIR)
Address : 000031HER7 ER6 ER5 ER4 ER3 ER2 ER1 ER0
bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8
00000000B
00000000B
00000000B
Interrupt/DTP source register (EIRR)
Address : 000032HLB3 LA3 LB2 LA2 LB1 LA1 LB0 LA0
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
Request level setting register (ELVR)
Address : 000033HLB7 LA7 LB6 LA6 LB5 LA5 LB4 LA4
bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8
R/W R/W R/W R/W R/W R/W R/W R/W
R/W R/W R/W R/W R/W R/W R/W R/W
R/W R/W R/W R/W R/W R/W R/W R/W
R/W R/W R/W R/W R/W R/W R/W R/W
R/W : Readable and writable
4
4
4
8
4
Interrupt/DTP enable register
Interrupt/DTP source register
Request level setting register
Gate Request F/F Edge detect circuit Request input
Internal data bus
MB90650A Series
53
10. 16-bit I/O Timer
The 16-bit I/O timer consists of one 16-bit free-run timer, two output compare, and two input capture modules.
Based on the 16-bit free-run timer , these functions can be used to gener ate two independent w av ef orm outputs
and to measure input pulse widths and external clock periods.
Register configuration
•Block diagram
TCDTL : 000066H
TCDTH : 000067H
bit 15 bit 0
16-bit free-run timer
Timer data register lower, upper (TCDTL, TCDTH)
TCCS : 000068HTimer control status register (TCCS)
IPCP0 : 000060H, 61H
IPCP1 : 000062H, 63H
bit 15 bit 0
16-bit input capture
Input capture register channel 0, channel 1
lower, upper (IPCP0, IPCP1)
ICS0, 1 : 000064HInput capture control status register (ICS0, 1)
OCCP0 : 000050H, 51H
OCCP1 : 000052H, 53H
OCCP2 : 000054H, 55H
OCCP3 : 000056H, 57H
bit 15 bit 0
OCS0 : 000058H
OCS1 : 000059H
OCS2 : 00005AH
OCS3 : 00005BH
16-bit output compare
Compare register channel 0 to channel 3
lower, upper (OCCP0 to OCCP3)
Compare control status register
channel 0 to channel 3 (OCS0 to OCS3)
TCDT
OCCP
OCS
IPCP
TCCS
ICS
16-bit free-run timer
Control logic
16-bit timer
Compare register 0
Compare register 1
Compare register 2
Compare register 3
Capture register 0
Capture register 1
Output compare 0
Output compare 1
Output compare 2
Output compare 3
Input capture 0
TQ
TQ
TQ
TQ
Edge selection
Edge selection
Interrupt
To each block
OUT0
OUT1
OUT2
OUT3
IN0
IN1
Clear
Internal data bus
MB90650A Series
54
(1) 16-bit Free-run Timer
The 16-bit free-run timer consists of a 16-bit up-counter, a control register, and a prescaler. The output of the
timer/counter is used as the base time for the input capture and output compare.
The operating clock for the counter can be selected from four different clocks.
Four internal clocks (φ/4, φ/16, φ/32, φ/64)
Interrupts can be generated when a counter v alue ov erflow or compare match with compare register 0 occurs
(the appropriate mode must be set for a compare match).
The counter can be initialized to 0000H b y a reset, software clear, or compare match with compare register 0.
Register details
The count v alue of the 16-bit free-run timer can be read from this register. The count is cleared to “0000B” by a
reset. Writing to this register sets the timer value. However, only write to the register when the timer is halted
(STOP = “1”). Always use word access.
The 16-bit free-run timer is initialized by the following.
Reset
The clear bit (CLR) of the control status register
A match between the timer/counter value and compare register 0 of the output compare (if the appropr iate
mode is set)
•Block diagram
Address : 000067HT15 T14 T13 T12 T11 T10 T09 T08
R/W R/W R/W R/W R/W R/W R/W R/W
Initial value
00000000B
Upper timer data register (TCDTH)
bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8
R/W : Readable and writable
Address : 000066HT07 T06 T05 T04 T03 T02 T01 T00
R/W R/W R/W R/W R/W R/W R/W R/W
Initial value
00000000B
Lower timer data register (TCDTL)
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
IVF IVFE STOP MODE CLR CLK1 CLK0
16-bit up-counter
Divider
Comparator 0
Clock
φ
Count value output T15 to T00
Interrupt request
Internal data bus
MB90650A Series
55
(2) Output Compare
The output compare consists of two 16-bit compare registers, compare output latches, and control registers.
The modules can inv ert the output le vel and generate an interrupt when the 16-bit free-run timer value matches
the compare register value.
The four compare registers can be operated independently.
Each compare register has a corresponding output pin and interrupt flag.
The four compare registers can be paired to control the output pins.
Invert the output pins using the four compare registers.
Initial values can be set for the output pins.
An interrupt can be generated when a compare match occurs.
Register configuration
OCCP0 : 000050H
OCCP1 : 000052H
OCCP2 : 000054H
OCCP3 : 000056H
OCCP0 : 000051H
OCCP1 : 000053H
OCCP2 : 000055H
OCCP3 : 000057H
Upper compare register channel 0 to channel 3 (OCCP0 to OCCP3)
Lower compare register channel 0 to channel 3 (OCCP0 to OCCP3)
Compare control status register channel 0 to channel 3 (OCS0 to OCS3)
Initial value
XXXXXXXXB
X : Unused
: Indeterminate
C15 C14 C13 C12 C11 C10 C09 C08
bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8
R/W R/W R/W R/W R/W R/W R/W R/W
Initial value
XXXXXXXXB
C07 C06 C05 C04 C03 C02 C01 C00
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
R/W R/W R/W R/W R/W R/W R/W R/W
Initial value
---00000B
CMOD OTE1 OTE0 OTDI OTD0
bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8
R/W R/W R/W R/W R/W
———
——
OCS1 : 000059H
OCS3 : 00005BH
OCS1 : 000059H
OCS3 : 00005BH
Initial value
0000--00B
ICE0 CST1 CST0
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
R/WR/WR/WR/W R/W R/W
ICP1 ICP0 ICE1
OCS0 : 000058H
OCS2 : 00005AH
——
: Readable and writableR/W
MB90650A Series
56
•Block diagram
ICP1 ICP0 ICE1 ICE0
Compare control TQ
Control blocks
Compare 1 interrupt (3)
Compare register 0 (2)
Compare control
Compare register 1 (3)
Controller
16-bit timer/counter value (T15 to T00)
16-bit timer/counter value (T15 to T00)
TQ
CMOD
OTE1
OTEO
Compare 0 interrupt (2)
OUT0
(OUT2)
OUT1
(OUT3)
Internal data bus
MB90650A Series
57
(3) Input Capture
The input capture consists of two independent external input pins, their corresponding capture registers, and
a control register. The value of the 16-bit free-run timer can be stored in the capture register and an interrupt
generated when the specified edge is detected on the signal from the external input pin.
The edge to detect on the external input signal is selectable.
Detection of rising edges, falling edges, or either edge can be specified.
The two input capture channels can operate independently.
An interrupt can be generated on detection of the specified edge on the external input signal.
The input capture interrupt can activate the intelligent I/O service.
Register details
The 16-bit free-run timer value is stored in these registers when the specified edge is detected on the input
waveform from the corresponding external pin. (Always use word access. Writing is prohibited.)
IPCP0 : 000060H
IPCP1 : 000062H
: Read only
: Indeterminate
CP07 CP06 CP05 CP04 CP03 CP02 CP01 CP00
RR R
R
RR RRR
Initial value
XXXXXXXXB
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
IPCP0 : 000061H
IPCP1 : 000063H CP15 CP14 CP13 CP12 CP11 CP10 CP09 CP08
R R R R R R R R
Initial value
XXXXXXXXB
X
Input capture register channel 0, channel 1 (IPCP0, IPCP1)
bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8
000064H ICP1 ICP0 ICE1 ICE0 EG11 EG10 EG01 EG00
R/W
R/W R/W R/W R/W R/W R/W R/W R/W
Initial value
00000000B
Input capture control status register (ICS0, 1)
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
: Readable and writable
MB90650A Series
58
•Block diagram
Capture data register 0 Edge detection
Interrupt
16-bit timer/counter value (T15 to T00)
Interrupt
IN0
Capture data register 1 Edge detection
EG11 EG10 EG01 EG00
ICP1 ICP0 ICE1 ICE0
IN1
Internal data bus
MB90650A Series
59
11. Watchdog Timer, Timebase Timer, and Watch Timer
The watchdog timer consists of a 2-bit watchdog counter that uses the carr y signal from the 18-bit timebase
timer or the 15-bit watch timer as a clock source, a control register, and a watchdog reset controller.
The timebase timer consists of an 18-bit timer and a circuit that controls interval interrupts. Note that the timebase
timer uses the main clock, regardless of the setting of the MCS bit and SCS bit in CKSCR.
The watch timer consists of a 15-bit timer and a circuit that controls interval interrupts. Note that the w atch timer
uses the sub clock, regardless of the setting of the MCS bit SCS bit in CKSCR.
(1) Register Configuration
Address : 0000A9H
Reserved
TBIE TBOF TBR TBC1 TBC0
— R/W R/W W R/W R/W
Initial value
1--00000B
Timebase timer control register (TBTC)
Watch timer control register (WTC)
bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8
Address : 0000AAHWDCS SCE WTIE WTOF WTR WTC2 WTC1 WTC0
R/W R R/W R/W R R/W R/W R/W
Initial value
1X000000B
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
Watchdog timer control register (WDTC)
Address : 0000A8HPONR WRST ERST SRST WTE WT1 WT0
R R R R W W W
Initial value
XXXXX111B
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
R/W
R
W
X
: Readable and writable
: Read only
: Write only
: Unused
: Indeterminate
MB90650A Series
60
(2) Bloc k Diagram
SRST
ERST
WRST
PONR
WDTC
From power-on generation
RST pin
From RST bit in
the STBYC register
Sub clock
WTC
WDCS
SCE
WTC1
WTC0
WTR
WTIE
WTOF
AND QS
R
Selector
QS
R
AND
210
WTRES
210 213 214 215
Watch timer
Clock input
SCM
WDGRST
To internal reset
generator
Watchdog reset
generator
CLR
2-bit counter
OF
CLR
Selector
WDTC
WT1
WT0
WTE
Timebase
interrupt
TBTC
TBC1
TBC0
TBIE
TBR
TBOF
AND QS
R
Selector Timebase timer
Clock input
Main clock
212
214
216
219
TBTRES 212 214 216 219
Internal data bus
Power-on reset
sub clock stops
Timer
interrupt
213
214
215
MB90650A Series
61
12. I2C Interface
The I2C interface is a serial I/O port that supports the Inter-IC bus and operates as a master/slave device on the
I2C bus. This module has the following features:
Master/slave transmission/reception
Arbitration function
Clock synchronization function
Slave address/general call address detection function
Transfer direction detection function
Start condition repeat generation and detection function
Bus error detection function
(1) Register Configuration
Address : 000083HA6A5A4A3A2A1A0
R/W R/W R/W R/W R/W R/W R/W
Initial value
-XXXXXXXB
I2C bus address register (IADR)
I2C bus data register (IDAR)
bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8
Address : 000084HD7 D6 D5 D4 D3 D2 D1 D0
R/W R/W R/W R/W R/W R/W R/W R/W
Initial value
XXXXXXXXB
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
I2C bus clock control register (ICCR)
Address : 000082H EN CS4 CS3 CS2 CS1 CS0
R/W R/W R/W R/W R/W R/W
Initial value
--0XXXXXB
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
R/W
R
X
Address : 000081HBER BEIE SCC MSS ACK GCAA INTE INT
R/W R/W R/W R/W R/W R/W R/W R/W
Initial value
00000000B
00000000B
I2C bus control register (IBCR)
bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8
I2C bus status register (IBSR)
Address : 000080HBB RSC AL LRB TRX AAS GCA FBT
R R R R R R R R
Initial value
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
: Readable and writable
: Read only
: Unused
: Indeterminate
MB90650A Series
62
(2) Bloc k Diagram
BB
RSC
LRB
TRX
FBT
AL
IBSR
CS4
CS3
CS2
CS1
CS0
ICCR
ICCR
EN
IADR
BER
BEIE
INTE
INT
IBCR
SCC
MSS
ACK
GCAA
AAS
GCA
IBSR
IDAR
Interrupt request
Slave address
comparison
Start/stop
condition generation
IBCR
Slave
Global call
Start
Master
ACK enable
GC-ACK enable
Arbitration lost detection
Clock selection 2
Clock divider 2
Start/stop
condition generation
Shift clock generation
Bus busy
Repeat start
Last bit
First byte
Error
2 8 16 32 64 128 2564
Clock selection 1
Clock divider 1
5678
I2C enable
Peripheral clock
IRQ
End
SCL
SDA
Sync
Shift clock edge
change timing
Transmit/receive
Internal data bus
MB90650A Series
63
13. External Bus Pin Control Circuit
The e xternal bus pin control circuit controls the e xternal bus pins required to e xtend the CPU’ s address/data bus
outside the device.
(1) Register Configuration
(2) Bloc k Diagram
Address : 0000A7HCKE RYE HDE ICBS HMBS WRE LMBS
WWWWWWW
Initial value
0000*00-B
Bus control signal selection register (ECSR)
bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8
External address output control register (HACR)
Address : 0000A6HE23 E22 E21 E20 E19 E18 E17 E16
WWWWWWWW
Initial value
00000000B
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
W
*
Address : 0000A5HICR1 ICR0 HMR1 HMR0 LMR1 LMR0
WWWW—WW
Initial value
0011--00B
Auto-ready function selection register (ARSR)
bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8
: Write only
: Unused
: “1” or “0”
P3
P2
P1
P0
Access control
Access control
P0
Address control
Data control
P0 data
P0 direction
P3
RB
MB90650A Series
64
14. Low-power Consumption Mode (CPU Intermittent Operation Function, Oscillation
Stabilization Delay Time, Clock Multiplier Function)
The following are the operating modes: PLL clock mode, PLL sleep mode, PLL watch mode, pseudo-watch
mode, main clock mode, main sleep mode, main watch mode, main stop mode, sub clock mode, sub sleep
mode, sub watch mode, and sub stop mode. Aside from the PLL clock mode, all of the other operating modes
are low-power consumption modes.
In main clock mode and main sleep mode, the main clock (main OSC oscillation clock) and the sub clock (sub
OSC oscillation clock) operate. In these modes, the main clock divided by 2 is used as the operation clock, the
sub clock (sub OSC oscillation clock) is used as the timer clock, and the PLL clock (VCO oscillation clock) is
stopped.
In sub clock mode and sub sleep mode, only the sub clock operates. In these modes, the sub clock is used as
the operation clock, and the main clock and PLL clock are stopped.
In PLL sleep mode and main sleep mode, only the CPU’s operation clock is stopped; all clocks other than the
CPU clock operate.
In pseudo-watch mode, only the watch timer and timebase timer operate.
In PLL watch mode, main watch mode, and sub w atch mode, only the watch timer operates . In this mode, only
the sub clock is used for operation, while the main clock and the PLL cloc k are stopped (the diff erence between
the PLL watch mode, the main watch mode and the sub watch mode is that it resumes operation after an interrupt
in the PLL clock mode, the main clock mode, and the sub clock mode respectively, and there is no reference
concerning about clock mode operation).
The main stop mode, sub stop mode , and hardware standby mode stop oscillation, making it possib le to retain
data while consuming the least amount of pow er . (The difference betw een the main stop mode and the sub stop
mode is that it resumes operation in the main clock mode and the sub clock mode respectiv ely, and there is no
reference concerning about stop mode operation).
The CPU intermittent operation function intermittently runs the clock supplied to the CPU when accessing
registers, on-chip memory, on-chip resources, and the exter nal bus. Processing is possible with lower power
consumption by reducing the e x ecution speed of the CPU while supplying a high-speed clock and using on-chip
resources.
The PLL clock multiplier can be selected as either 2, 4, 6, or 8 by setting the CS1 and CS0 bits. These clocks
are divided by 2 to be used as a machine clock.
The WS1 and WS0 bits can be used to set the main clock oscillation stabilization dela y time f or when stop mode
is woken up.
MB90650A Series
65
(1) Register Configuration
Address : 0000A1
H
SCM MCM WS1 WS0 SCS MCS CS1 CS0
R R R/W R/W R/W R/W R/W R/W
Initial value
11111100
B
Clock selection register (CKSCR)
bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8
Low-power consumption mode control register (LPMCR)
Address : 0000A0
H
STP SLP SPL RST TMD CG1 CG0 Re-
served
W W R/W W W R/W R/W
Initial value
00011000
B
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
R/W
R
W
Ñ
: Readable and writable
: Read only
: Write only
: Unused
( )
MB90650A Series
66
(2) Bloc k Diagram
Low-power consumption control circuit and clock generator
CKSCR
SCM
SCS
CS1
CS0
CG1
CG0
LPMCR
MCM
MCS
CKSCR
CKSCR
SLP
STP
LPMCR
TMD
WS1
WS0
SPL
LPMCR
CKSCR
RST
LPMCR Internal reset
generator
Pin high-impedance controller
Oscillation
stabilization
delay time
selector
24
213
215
218
Clock input
Timebase timer
212 214 216 219
Pin Hi-Z
RST pin
Internal RST
To watchdog timer
WDGRST
Interrupt request
or RST
Sub OSC stop
Main OSC stop
Peripheral clock
Peripheral
clock
generation
SCM
Standby
controller
SLEEP
MSTP
STOP
RST cancel
CPU intermittent
operation function
Cycle count
selection circuit
CPU
Clock selector
1/2 S
PLL multiplier
circuit
2134
Sub clock Sub clock divided by 4
(OSC oscillation)
Main clock
(OSC oscillation)
CPU clock
CPU
system clock
generation
0/9/17/33
intermittent cycle selection
Internal data bus
switching control
MB90650A Series
67
State transition diagram for clock selection (1)
Main
SCS = 1, MCS = 1
SCM = 1, MCM = 1
CS1/0 = ××
Sub PLL×
SCS = 1, MCS = 0
SCM = 0, MCM = 1
CS1/0 = ××
Main Sub
SCS = 0, MCS = ×
MCM = 1
SCM = 1
Main
PLL
×
SCS = 1, MSC = 0
SCM = 1, MCM = 1
CS1/0 =
××
PLL1
Main
SCS = 0 or MCS = 0
SCM = 1, MCM = 0
CS1/0 = 00
PLL2
Main
SCS = 0 or MCS = 1
SCM = 1, MCM = 0
CS1/0 = 01
PLL3
Main
SCS = 0 or MCS = 1
SCM = 1, MCM = 0
CS1/0 = 10
PLL4
Main
SCS = 0 or MCS = 1
SCM = 1, MCM = 0
CS1/0 = 11
PLL 1 multiplier
SCS = 1, MSC = 0
SCM = 1, MCM = 0
CS1/0 = 00
PLL 2 multiplier
SCS = 1, MSC = 0
SCM = 1, MCM = 0
CS1/0 = 01
PLL 3 multiplier
SCS = 1, MSC = 0
SCM = 1, MCM = 0
CS1/0 = 10
PLL 4 multiplier
SCS = 1, MSC = 0
SCM = 1, MCM = 0
CS1/0 = 11
<1> <2>
<3>
<7>
<7>
<7>
<7>
<6>
<6>
<8>
<8>
<8>
<8>
<9> <6>
<5>
<6>
<1> MCS bit cleared and SCS bit set
<2> PLL clock oscillation stabilization delay complete and CS1/0 = 00
<3> PLL clock oscillation stabilization delay complete and CS1/0 = 01
<4> PLL clock oscillation stabilization delay complete and CS1/0 = 10
<5> PLL clock oscillation stabilization delay complete and CS1/0 = 11
<6> MCS bit set or SCS bit cleared
<7> PLL clock and main clock synchronized timing and SCS = 1
<8> PLL clock and main clock synchronized timing and SCS = 0
<9> Main clock oscillation stabilization delay complete and MCS = 0
Power-on
<4>
MB90650A Series
68
State transition diagram for clock selection (2)
Main
SCS = 1, MCS = 1
SCM = 1
MCM = 1
PLL× → Sub
SCS = 0, MCS = ×
SCM = 1, MCM = 0
CS1/0 = ××
Main PLL×
SCS = 1, MCS = 0
SCM = 1, MCM = 1
CS1/0 = ××
Main Sub
SCS = 0
SCM = 1
MCM = 1
Sub Main
SCS = 1
SCM = 0
MCM = 1
Sub
SCS = 0
SCM = 0
MCM = 1
<1>
<2>
<3>
<4>
<5>
<6>
<1> SCS bit cleared
<2> Sub clock edge detection timing
<3> SCS bit set
<4> Main clock oscillation stabilization delay complete and MCS = 1
<5> PLL clock and main clock synchronized timing and SCS = 0
<6> Main clock ascillation stabilization delay complete and MCS = 0
Power-on
MB90650A Series
69
15. Delayed Interrupt Generation Module
The delayed interrupt generation module is used to generate the task switching interr upt. Interr upt requests to
the F2MC-16L CPU can be generated and cleared by software using this module.
(1) Register Details
The DIRR register controls generation and clearing of delayed interrupt requests. Writing “1” to the register
generates a delayed interrupt request. Writing “0” to the register clears the delayed interrupt request. The register
is set to the interrupt cleared state by a reset. Either “0” or “1” can be written to the reser ved bits. However,
considering possible future e xtensions , it is recommended that the set bit and clear bit instructions are used f or
register access.
(2) Bloc k Diagram
Address : 00009FH———————R0
R/W
Initial value
-------0B
Delayed interrupt generation /release register (DIRR)
bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8
R/W
: Readable and writable
: Unused
Delayed interrupt generation/release decoder
Interrupt latch
Internal data bus
MB90650A Series
70
16. DTMF Generator
The DTMF (dual tone multifrequency) generator is a module that can gener ate a series of audio tones as heard
from a push-button telephone or a radio transceiver with a keypad. It has the following features:
Capabl e of generating DTMF tones continuously (or even a single tone)
Capable of generating all CCITT tones: 0 to 9, *, #, A to D
(1) Register list
(2) Bloc k diagram
DTMF control register (DTMC)
Address : 000088H CSL2 CSL1 CSL0 CDIS RDIS OUTE
R/W
Initial value
00000000B
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
R/W R/W
R/W R/W
R/W
DTMF data register (DTMD)
Address : 000089H————DDAT3 DDAT2 DDAT1
R/W
Initial value
000X0000B
bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8
R/W
R/W
R/W
: Read/write enabled
: Unused
X : Undefined
DDAT0
R/W
——
DTMF
Internal clock
Frequency divider
ROW/COL
decoder
Preset counter
DTMF data register (DTMD)
Clock pulse
Frequency
select
Frequency
select
Terminate
Control signal generator
Count clock
COL staircase
generator
ROW staircase
generator
DTMF control register (DTMC)
Internal bus
Voltage data
Adder
Frequency
divider
Frequency
select
MB90650A Series
71
ELECTRICAL CHARACTERISTICS
1. Absolute Maximu m Ratings (VSS = AVSS = 0.0 V)
*1 : AVCC, A VRH, A VRL and D VRH shall never exceed VCC (VCC1 and VCC2 are contained). A VRH, A VRL shall never
exceed AVCC. Also, AVRL shall never exceed AVRH.
*2 : VI and VO must not exceed VCC (VCC1 and VCC2 are contained) + 0.3 V.
*3 : Maximum output current specifies the peak value or one corresponding pin.
*4 : The average output current is the rating for the current from an individual pin averaged over 100 ms.
*5 : The average total output current is the rating for the current from all pins averaged over 100 ms.
(Continued)
Parameter Symbol Rating Unit Remarks
Min Max
Power supply voltage
VCC1VSS – 0.3 VSS + 4.0 V without MB90V650A
VCC2VSS – 0.3 VSS + 7.0 V
AVCC VSS – 0.3 VSS + 4.0 V without MB90V650A *1
AVRH
AVRL VSS – 0.3 VSS + 4.0 V without MB90V650A
DVRH VSS – 0.3 VSS + 4.0 V without MB90V650A
Input voltage VIVSS – 0.3 VSS + 4.0 V without MB90V650A *2
VIC VSS – 0.3 VSS + 7.0 V P47, P70/SDA, P71/SLC,
P72 (N-ch open-drain pins)
Output voltage VOVSS – 0.3 VSS + 4.0 V without MB90V650A *2
Maximum clamp current ICLAMP 2.0 +2.0 mA *6
Total maximum clamp current ∑ICLAMP+20 mA *6
“L” level maximum
output current IOL 10 mA without MB90V650A *3
“L” level average output current IOLAV 3 mA without MB90V650A *4
“L” level total maximum
output current ΣIOL 60 mA without MB90V650A
“L” level total average
output current ΣIOLAV 30 mA without MB90V650A *5
“H” level maximum
output current IOH –10 mA without MB90V650A *3
“H” level average
output current IOHAV –3 mA without MB90V650A *4
“H” level total maximum
output current ΣIOH –60 mA without MB90V650A
“H” level total average
output current ΣIOHAV –30 mA *5
Power consumption PD 200 mW
Operating temperature TA–40 +85 °C
Storage temperature Tstg –55 +150 °C
MB90650A Series
72
(Continued)
*6 : Applicab le to pins : P00 to P07, P10 to P17, P20 to P27, P30 to P37, P40 to P47, P50 to P57, P60 to P67,
P70 to P74, P80 to P86, P90 to P97, PA0 to PA2
Use within recommended operating conditions.
Use at DC voltage (current).
The +B signal should always be applied with a limiting resistance placed between the +B signal and the
microcontroller.
The value of the limiting resistance should be set so that when the +B signal is applied the input current to
the microcontroller pin does not exceed rated values, either instantaneously or for prolonged periods.
Note that when the microcontroller drive current is low, such as in the power saving modes, the +B input
potential may pass through the protective diode and increase the potential at the VCC pin, and this may
affect other devices.
Note that if a +B signal is input when the microcontroller current is off (not fixed at 0 V), the power supply
is provided from the pins, so that incomplete operation may result.
Note that if the +B input is applied during power-on, the power supply is provided from the pins and the
resulting supply voltage may not be sufficient to operate the power-on reset.
Care must be taken not to leave the +B input pin open.
Note that analog system input/output pins other than the A/D input pins (LCD drive pins, comparator input
pins, etc.) cannot accept +B signal input.
Sample recommended circuits :
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
P-ch
N-ch
R
VCC
Input/Output Equivalent circuits
Protective diode
Limiting
resistance
+B input (0 V to 16 V)
MB90650A Series
73
2. Recommended Operating Conditions (VSS = AVSS = 0.0 V)
Note : I2C must be used at above 2.7 V.
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the
semiconductor device. All of the device's electrical characteristics are warranted when the device is
operated within these ranges.
Always use semiconductor de vices within their recommended oper ating condition r anges . Oper ation
outside these ranges may adversely affect reliability and could result in device failure.
No warr anty is made with respect to uses, operating conditions, or combinations not represented on
the data sheet. Users considering application outside the listed conditions are advised to contact their
FUJITSU representatives beforehand.
Parameter Symbol Value Unit Remarks
Min Max
Power supply voltage
VCC12.2 3.6 V For normal operation
(MB90652A/653A/654A)
2.4 3.6 V For normal operation (MB90F654A)
VCC22.2 5.5 V For normal operation
(MB90652A/653A/654A)
2.4 5.5 V For normal operation (MB90F654A)
VCC11.8 3.6 V To maintain statuses in stop mode
(MB90652A/653A/654A)
1.8 3.6 V To maintain statuses in stop mode
(MB90F654A)
VCC21.8 5.5 V To maintain statuses in stop mode
(MB90652A/653A/654A)
1.8 5.5 V To maintain statuses in stop mode
(MB90F654A)
“H” level input voltage
VIH 0.7 VCC VCC + 0.3 V Pins other than VIHS and VIHM
VIH2 0.7 VCC VCC + 0.3 V P70/SDA, P71/SLC (only I2C pin)
VIHS 0.8 VCC VCC + 0.3 V Hysteresis input pins
VIHM VCC – 0.3 VCC + 0.3 V MD pin input
VIHT 2.4 VCC + 0.3 V TTL input pins
“L” level input voltage
VIL VSS – 0.3 0.3 VCC V PIns other than VILS and VILM
VIL2 VSS – 0.3 0.3 VCC VP70/SDA, P71/SLC (only I2C pin)
VILS VSS – 0.3 0.2 VCC V Hysteresis input pins
VILM VSS – 0.3 VSS + 0.3 V MD pin input
VILT VSS – 0.3 0.8 V TTL input pins
Operating temperature TA–40 +85 °C
MB90650A Series
74
3. DC Characteristics (MB90652A/653A/654A: VCC = 2.2 V to 3.6 V, VSS = 0.0 V, TA = –40°C to +85°C)
(MB92F654A: VCC = 2.4 V to 3.6 V, VSS = 0.0 V, TA = –40°C to +85°C)
(Continued)
Parameter Symbol Pin name Condition Value Unit Remarks
Min Typ Max
“H” level
output
voltage*2 VOH Pins except
P47,
P70 to P72
VCC2 = 4.5 V,
IOH = –4.0 mA VCC2– 0.5 V When the 5-V power
supply is used
VCC = 2.7 V,
IOH = –1.6 mA VCC1– 0.3 V When the 3-V power
supply is used *1
“L” le vel output
voltage*2 VOL All output
pins
VCC2 = 4.5 V,
IOL = 4.0 mA ——0.4V
When the 5-V power
supply is used
VCC = 2.7 V,
IOL = 2.0 mA ——0.4V
When the 3-V power
supply is used
Input leakage
current IIL Except P50
to P57,
P90, P91 VCC = 3.3 V,
VSS < VI < VCC –10 10 µA
Pull-up resistor RPULL When VCC = 3.0 V,
TA = +25°C20 65 200 kwithout MB90V650A
Open-drain
output leakage
current Ileak P40 to P47,
P70 to P72 ——0.110µA
Power supply
current
ICC
When VCC = 3.0 V
Internal 8 MHz
operation
—1020mA
MB90652A/653A/654A:
During normal operation
ICC —1724mA
MB90652A/653A/654A:
In A/D operation
ICC —1926mA
MB90652A/653A/654A:
In D/A operation
ICCS —2.55mA
MB90652A/653A/654A:
During sleep
ICC
When VCC = 3.0 V
Internal 12 MHz
operation
—1631mA
MB90652A/653A/654A:
During normal operation
ICC —2139mA
MB90F654A:
During normal operation
ICC —3744mA
MB90F654A:
Flash write/erase
ICC —2737mA
MB90652A/653A/654A:
In A/D operation
ICC —3242mA
MB90F654A:
In A/D operation
ICC —3038mA
MB90652A/653A/654A:
In D/A operation
ICC —3038mA
MB90F654A:
In D/A operation
MB90650A Series
75
(Continued)
(MB90652A/653A/654A: VCC = 2.2 V to 3.6 V, VSS = 0.0 V, TA = –40°C to +85°C)
(MB90F654A: VCC = 2.4 V to 3.6 V, VSS = 0.0 V, TA = –40°C to +85°C)
* 1 : P40 to P46 are N-ch open-drain pins to be controlled and are usually used as CMOS devices.
* 2 : When the device is used with dual pow er supplies , the P20 to P27, P30 to P37, P40 to P47, and P70 to P72
are the 5 V pins and the rest are the 3 V pins.
Note : VCC = VCC1 = VCC2
Parameter Symbol Pin name Condition Value Unit Remarks
Min Typ Max
Power supply
current
ICCS When VCC = 3.0 V
Internal 12 MHz
operation
—3.59mA
MB90652A/653A/654A:
During sleep
ICCS —4.810mA
MB90F654A:
During sleep
ICCH TA = +25°C
When VCC = 3.0 V
—0.120µAMB90652A/653A/654A:
During stop
ICCH —0.240µAMB90F654A:
During stop
ICCL
VCC = 3.0 V,
TA = +25°C
External 32 kHz
operation
(Internal 8 MHz
operation)
16 140 µAwithout MB90V650A:
In sub operation
ICCT VCC = 3.0 V,
TA = +25°C
External 32 kHz
operation
—1030µAMB90652A/653A/654A:
In watch mode
ICCT —1530µAMB90F654A:
In watch mode
Input
capacitance CIN Except AVCC,
AVSS, VCC,
VSS ——515pF
MB90650A Series
76
4. AC Characteristics
(1) Cloc k Timing (VCC = 2.7 V to 3.6 V, VSS = 0.0 V, TA = –40°C to +85°C)
Because the PLL frequency fluctuates around the set frequency with a certain cycle [approximately CLK × (1 CYC
to 50 CYC)], the worst v alue is not maintained for long. (The pulse, if featured with the long period, would produce
practically no error.)
* : The duty ratio should be in the range 30% to 70%.
Note : VCC = VCC1 = VCC2
Parameter Symbol Pin
name Condition Value Unit Remarks
Min Typ Max
Clock frequency FCH X0, X1 3 24 MHz
FCL X0A, X1A 32.768 kHz
Clock cycle time tCX0, X1 41.67 333 ns
tCL X0A, X1A 30.5 µs
Input clock pulse
width
PWH
PWL X0 5 ns *
PWLH
PWLL X0A 15.2 µs*
Input clock rise
time and fall time tcr
tcf X0 5 ns External clock
Internal
operating clock
frequency
fCP 1.5 12 MHz
fCPL ——8.192kHz
Internal
operating clock
cycle time
tCP 83.3 666 ns
tCPL 122.1 µs
MB90650A Series
77
Main clock timing condition (X0, X1)
0.8 VCC
0.2 VCC
tcf tcr
tC
PWH
X0
PWL
Subcloc k timing condition (X0A, X1A)
0.8 VCC
0.2 VCC
tCL
PWHL
X0A
PWLL
MB90650A Series
78
PLL operation assurance range
3.6
2.7
2.2
512
Power supply voltage (VCC)
Normal operation range
2.5
31.5 Internal clock (fCP)
34 6 12 24
12
9
8
4
Multiply by 3 No multiplier
Oscillation clock (FC)
Internal clock (fCP)
Relationship between the oscillation frequency and internal operating clock frequency
Relationship between the internal operating clock frequency and power supply voltage
(MB90652A/653A/654A, MB90F654A)
Multiply by 1
(V)
(MHz)
PLL operation assurance range
3.6
2.7
312
Power supply voltage (VCC)
Normal operation range
1.5 Internal clock (fCP)
Relationship between the internal oprating clock frequency and power supply voltage
(MB90PV650A)
(V)
(MHz)
PLL operation
assurance range
(MHz)
(MHz)
Multiply by 2
Multiply by 4
6
8
MB90650A Series
79
The AC characteristics are for the following measurement reference voltages.
Input signal waveform Output signal waveform
Hysteresis input pins
0.8 VCC
0.2 VCC
Other than hysteresis or MD input pins
0.7 VCC
0.3 VCC
Output pins
2.4 V
0.2 V
MB90650A Series
80
(2) Clock Output Timing (VCC = 2.7 V to 3.6 V, VSS = 0.0 V, TA = –40°C to +85°C)
* : For tCP see “(1) Clock Timing.”
Note : VCC = VCC1 = VCC2
(3) Reset Input Specifications (VCC = 2.7 V to 3.6 V, VSS = 0.0 V, TA = –40°C to +85°C)
* : For tCP see “(1) Clock Timing.”
Note : VCC = VCC1 = VCC2
Parameter Symbol Pin
name Condition Value Unit Remarks
Min Max
Cycle time tCYC CLK tCP*—ns
CLK ↑ → CLKtCHCL CLK VCC = 3.0 V
±10%
tCP* / 2 – 20 tCP* / 2 + 20 ns
tCP* / 2 – 64 tCP* / 2 + 64 ns In the external
frequency of
5 MHz
Parameter Symbol Pin
name Condition Value Unit Remarks
Min Max
Reset input time tRSTL RST 16 tCP*— ns
tCYC
tCHCL
CLK 0.8 V 2.4 V
2.4 V
0.2 VCC
0.2 VCC
RST
t RSTL
AC characteristics measurement conditions
CL
Pin
CLK, ALE: CL = 30 pF
AD15 to AD00 (address/data bus), RD, WR: CL = 80 pF
CL : Load capacitance at testing
MB90650A Series
81
(4) Power on Supply Specifications (Power-on Reset) (VCC = 2.7 V to 3.6 V, VSS = 0.0 V, TA = –40°C to +85°C)
* : When the power rising, VCC must be less than 0.2 V.
Notes : The above standards are the values needed in order to activate a power-on reset.
Activate a power-on reset by turning on the power supply again this in device.
VCC = VCC1 = VCC2
Parameter Symbol Pin name Condition Value Unit Remarks
Min Max
Power supply rising time tRVCC ——30ms*
Power supply cut-off time tOFF VCC —1ms
Due to
repeat
operation
Holding RAM data
2.7 V
tR
0.2 V
VCC
Main power supply voltage
Sub-power supply voltage
VSS
VCC It is recommended that the rate of
increase in the voltage be kept to
no more than 50 mV/ms.
Abrupt changes in the power supply voltage may cause a power-on reset.
When changing the power supply voltage during operation, suppress variations in the voltage and
ensure that the voltage rises smoothly, as shown in the following figure.
tOFF
MB90650A Series
82
(5) Bus Read Timing (VCC = 2.7 V to 3.6 V, VSS = 0.0 V, TA = –40°C to +85°C)
* : For tCP see “(1) Clock Timing.”
Note : VCC = VCC1 = VCC2
Parameter Symbol Pin name Condition Value Unit Remarks
Min Max
ALE pulse width tLHLL ALE tCP* /2 – 20 ns MASK/FLASH
Valid address ALE time tAVLL Multiplexed
address —t
CP* / 2 – 25 ns MASK/FLASH
ALE ↓ → address valid time tLLAX Multiplexed
address —t
CP* / 2 – 15 ns
Valid address RD time tAVRL Multiplexed
address —t
CP* – 15 ns
Valid address valid data
input tAVDV Multiplexed
address ——5 t
CP* / 2 – 60 ns MASK/FLASH
RD pulse width tRLRH RD —3 tCP* / 2 – 20 ns
RD ↓ → valid data input tRLDV D15 to D00 5 tCP* / 2 – 60 ns MASK/FLASH
RD ↑ → data hold time tRHDX D15 to D00 0 ns
RD ↑ → ALE time tRHLH RD, ALE tCP* / 2 – 15 ns
RD ↑ → address valid time tRHAX Address,
RD —tCP* / 2 – 10 ns
Valid address CLK time tAVCH Address,
CLK —t
CP* / 2 –20 ns
RD ↓ → CLK time tRLCH RD, CLK tCP* / 2 – 20 ns
MB90650A Series
83
CLK
ALE
RD
tRHDX
2.4 V 2.4 V
2.4 V 2.4 V 0.8 V 2.4 V
0.8 V 2.4 V
0.8 V
2.4 V 0.8 V
2.4 V
0.8 V
2.4 V 0.8 V
2.4 V 0.7 VCC
0.3 VCC
0.7 VCC
0.3 VCC
A23 to
A16
D15 to
D00
tAVCH tRLCH
tAVLL tLLAX
tLHLL
tAVRL tRLRH
tAVDV tRLDV
tRHAX
tRHLH
Address Read data
MB90650A Series
84
(6) Bus Write Timing (VCC = 2.7 V to 3.6 V, VSS = 0.0 V, TA = –40°C to +85°C)
* : For tCP see “(1) Clock Timing.”
Note : VCC = VCC1 = VCC2
Parameter Symbol Pin name Condition Value Unit Remarks
Min Max
Valid address WR time tAVWL A23 to A00 tCP* – 15 ns
WR pulse width tWLWH WR —3 tCP* / 2 – 20 ns
Valid data output WR
time tDVWH D15 to D00 3 tCP* / 2 – 20 ns
WR data hold time tWHDX D15 to D00 20 ns MASK/FLASH
WR address valid time tWHAX A23 to A00 tCP* / 2 – 10 ns
WR ALE time tWHLH WR, ALE tCP* / 2 – 15 ns
WR CLK time tWLCH WR, ALE tCP* / 2 – 20 ns
CLK
ALE
WR
(WRL, WRH) 0.8 V
2.4 V
A23 to
A16
D15 to
D00
2.4 V
2.4 V
2.4 V
0.8 V
2.4 V
0.8 V
2.4 V
0.8 V
2.4 V
0.8 V
2.4 V
0.8 V
tWLCH
tWHLH
tAVWL tWLWH
tWHAX
tDVWH tWHDX
Address Write data
MB90650A Series
85
(7) Ready Input Timing (VCC = 2.7 V to 3.6 V, VSS = 0.0 V, TA = –40°C to +85°C)
Notes: Use the auto-ready function if the RDY setup time is too short
VCC = VCC1 = VCC2.
Parameter Symbol Pin name Condition Value Unit Remarks
Min Max
RDY setup time tRYHS RDY 45 ns MASK/FLASH
RDY hold time tRYHH RDY 0 ns
CLK
ALE
RD/WR
RDY (When
one wait states
are inserted)
RDY (When
wait states are
not inserted)
2.4 V 2.4 V
0.2 VCC 0.2 VCC
0.8 VCC 0.8 VCC
tRYHH
tRYHS
tRYHS
MB90650A Series
86
(8) Hold Timing (VCC = 2.7 V to 3.6 V, VSS = 0.0 V, TA = –40°C to +85°C)
* : For tCP see “(1) Clock Timing.”
Notes: After reading HRQ, more than one cycle is required before changing HAK.
VCC = VCC1 = VCC 2
Parameter Symbol Pin name Condition Value Unit Remarks
Min Max
Pin floating HAK time tXHAL HAK —30tCP*ns
HAK ↑ → pin valid time tHAHV HAK —tCP*2 tCP*ns
HAK
tXHAL tHAHV
Pin High impedance
0.8 V 2.4 V
MB90650A Series
87
(9) UART Timing (VCC = 2.7 V to 3.6 V, VSS = 0.0 V, TA = –40°C to +85°C)
* : For tCP see “(1) Clock Timing.”
Notes: These are the AC characteristics for CLK synchronous mode.
•C
L is the load capacitance connected to the pin at testing.
•V
CC = VCC1 = VCC 2
Parameter Symbol Pin
name Condition Value Unit Remarks
Min Max
Serial clock cycle time tSCYC CL = 80 pF + 1 TTL
for the internal shift
clock mode output
pin
8 tCP*—ns
SCK SOT delay time tSLOV –80 +80 ns MASK/FLASH
Valid SIN SCK t
IVSH 100 ns MASK/FLASH
SCK ↑ → valid SIN hold
time tSHIX —tCP*—ns
Serial clock “H” pulse
width tSHSL
CL = 80 pF + 1 TTL
for the external
shift clock mode
output pin
4 tCP*—ns
Serial clock “L” pulse
width tSLSH —4 tCP*—ns
SCK ↓ → SOT delay time tSLOV 150 ns MASK/FLASH
Valid SIN SCK t
IVSH 60 ns MASK/FLASH
SCK ↑ → valid SIN hold
time tSHIX 60 ns MASK/FLASH
MB90650A Series
88
Internal shift clock mode
External shift clock mode
SCK
SOT
SIN
tSCYC
tSLOV
tIVSH tSHIX
2.4 V
0.8 VCC
0.8 V 0.8 V
2.4 V
0.8 V
0.2 VCC 0.8 VCC
0.2 VCC
SCK
SOT
SIN
tSLSH
tSLOV
tIVSH tSHIX
tSHSL
0.8 VCC
2.4 V
0.2 VCC 0.8 VCC
0.2 VCC
0.8 V
0.8 VCC
0.2 VCC 0.2 VCC
0.8 VCC
MB90650A Series
89
(10) I/O Extended Serial Timing (VCC = 2.7 V to 3.6 V, VSS = 0.0 V, TA = –40°C to +85°C)
* : For tCP see “(1) Clock Timing.”
Notes: These are the AC characteristics for CLK synchronous mode.
•C
L is the load capacitance connected to the pin at testing.
•V
CC = VCC1 = VCC 2
Parameter Symbol Pin
name Condition Value Unit Remarks
Min Max
Serial clock cycle time tSCYC CL = 80 pF + 1 TTL
for the internal shift
clock mode output
pin
8 tCP*—ns
SCK SOT delay time tSLOV –80 +80 ns MASK/FLASH
Valid SIN SCK t
IVSH 100 ns MASK/FLASH
SCK ↑ → valid SIN hold
time tSHIX —tCP*—ns
Serial clock “H” pulse
width tSHSL
CL = 80 pF + 1 TTL
for the external
shift clock mode
output pin
4 tCP*—ns
Serial clock “L” pulse
width tSLSH —4 tCP*—ns
SCK ↓ → SOT delay time tSLOV 150 ns MASK/FLASH
Valid SIN SCK t
IVSH 60 ns MASK/FLASH
SCK ↑ → valid SIN hold
time tSHIX 60 ns MASK/FLASH
MB90650A Series
90
Internal shift clock mode
External shift clock mode
SCK
SOT
SIN
tSCYC
tSLOV
tIVSH tSHIX
2.4 V
0.8 VCC
0.8 V 0.8 V
2.4 V
0.8 V
0.2 VCC 0.8 VCC
0.2 VCC
SCK
SOT
SIN
tSLSH
tSLOV
tIVSH tSHIX
tSHSL
0.8 VCC
2.4 V
0.2 VCC 0.8 VCC
0.2 VCC
0.8 V
0.8 VCC
0.2 VCC 0.2 VCC
0.8 VCC
MB90650A Series
91
(11) I2C Timing (VCC = 2.7 V to 3.6 V, VSS = 0.0 V, TA = –40°C to +85°C)
Note : VCC = VCC1 = VCC2
Parameter Symbol Pin name Condition Value Unit Remarks
Min Max
SCL clock frequency fSCL 0 100 kHz
Bus free time between stop
and start conditions tBUS ——4.7µs
Hold time (re-send) start tHDSTA ——4.0µsThe first clock
pulse is
generated after
this period.
SCL clock L state hold time tLOW ——4.7µs
SCL clock H state hold
time tHIGH ——4.0µs
Re-send start condition
setup time tSUSTA ——4.7µs
Data hold time tHDDAT ——0µs
Data setup time tSUDAT ——40ns
SDA and SCL signal rising
time tR——1000ns
SD A and SCL signal f alling
time tF 300 ns
Stop condition setup time tSUSTO ——4.0µs
tLOW
tRtF
tHDSTA tHDDAT tHIGH tSUDAT tSUSTA
tHDSTA
tSUSTO
0.8 VCC
0.2 VCC
0.2 VCC
0.8 VCC
SDA
SCL
tBUS
MB90650A Series
92
(12) Timer Input Timing (VCC = 2.7 V to 3.6 V, VSS = 0.0 V, TA = –40°C to +85°C)
* : For tCP see “(1) Clock Timing.”
Note : VCC = VCC1 = VCC2
(13) Timer Output Timing (VCC = 2.7 V to 3.6 V, VSS = 0.0 V, TA = –40°C to +85°C)
Note : VCC = VCC1 = VCC2
(14) Trigger Input Timing (VCC = 2.7 V to 3.6 V, VSS = 0.0 V, TA = –40°C to +85°C)
* : For tCP see “(1) Clock Timing.”
Note : VCC = VCC1 = VCC2
Parameter Symbol Pin name Condition Value Unit Remarks
Min Max
Input pulse width tTIWH, tTIWL IN0, IN1 4 tCP*—ns
Parameter Symbol Pin name Condition Value Unit Remarks
Min Max
CLK TOUT change time tTO PPG00 to PPG11
OUT0 to OUT3 80 pF load 30 ns
Parameter Symbol Pin name Condition Value Unit Remarks
Min Max
Input pulse width tTRGH
tTRGL ADTG,
IRQ0 to IRQ7 5 tCP* ns During normal operation
1 ms During stop
IN0 , IN1 0.8 VCC 0.8 VCC
0.2 VCC 0.2 VCC
tTIWH tTIWL
CLK
TOUT
0.7 VCC
tTO
0.7 VCC
0.3 VCC
IRQ2 to IRQ7 0.8 VCC 0.8 VCC
0.2 VCC 0.2 VCC
tTRGH tTRGL
MB90650A Series
93
(15) Up/down Counter Timing (VCC = 2.7 V to 3.6 V, VSS = 0.0 V, TA = –40°C to +85°C)
* : For tCP see “(1) Clock Timing.”
Note : VCC = VCC1 = VCC2
Parameter Symbol Pin name Condition Value Unit Remarks
Min Max
AIN input “H” pulse width tAHL
AIN0, AIN1
BIN0, BIN1 80 pF load
8 tCP*—ns
AIN input “L” pulse width tALL 8 t CP*—ns
BIN input “H” pulse width tBHL 8 tCP*—ns
BIN input “L” pulse width tBLL 8 t CP*—ns
AIN BIN time tAUBU 4 tCP*—ns
BIN AIN time tBUAD 4 tCP*—ns
AIN BIN time tADBD 4 tCP*—ns
BIN AIN time tBDAU 4 tCP*—ns
BIN AIN time tBUAU 4 tCP*—ns
AIN BIN time tAUBD 4 tCP*—ns
BIN AIN time tBDAD 4 tCP*—ns
AIN BIN time tADBU 4 tCP*—ns
ZIN input “H” pulse width tZHL ZIN0, ZIN1 4 tCP*—ns
ZIN input “L” pulse width tZLL 4 tCP*—ns
MB90650A Series
94
0.2 VCC
0.2 VCC 0.2 VCC
0.8 VCC
0.8 VCC 0.8 VCC
0.8 VCC
0.2 VCC
tALL
tBLLtBHL
tAHL
tAUBU tBUAD tADBD tBDAU
AIN
BIN
0.2 VCC
0.2 VCC
0.8 VCC 0.8 VCC
0.2 VCC 0.2 VCC
0.8 VCC
0.8 VCC
0.8 VCC
0.2 VCC
tBUAU tAUBD
tZHL
tZLL
tBDAD tADBU
BIN
AIN
ZIN
MB90650A Series
95
5. A/D Converter Electrical Characteristics
(MB90652A/653A/654A: VCC = 2.2 V to 3.6 V, VSS = AVSS =0.0V, 2.7 V AVRH – AVRL, TA = –40°C to +85°C)
(MB90F654A: VCC = 2.4 V to 3.6 V, VSS = AVSS = 0.0 V, 2.7 V AVRH – AVRL, TA = –40°C to +85°C)
*1: For a 12 MHz machine clock
*2: The current when the A/D conv erter is not operating or the CPU is in stop mode (f or VCC = A VCC = AVRH = 3.0 V).
Notes: The error increases proportionally as |AVRH – AVRL| decreases.
The output impedance of the external circuits connected to the analog inputs should be in the following
range.
The output impedance of the external circuit should be less than approximately 7 kΩ.
When using an external capacitor, it is recommended to have several thousand times the capacitance of
the internal capacitor as a guide, if one takes into consideration the effect of the divided capacitance
between the external capacitor and the internal capacitor.
If the output impedance of the external circuit is too high, the sampling time might be insufficient (sampling
time = 3.75 µs at a machine clock of 16 MHz).
•V
CC = VCC1 = VCC2
Parameter Symbol Pin name Value Unit Remarks
Min Typ Max
Resolution 10 10 bit
Total error ±3.0 LSB
Linearity error ±2.0 LSB
Differential
linearity error —— ±1.9 LSB MASK/FLASH
Zero transition
voltage VOT AN0 to AN7 AVRL
– 1.5 LSB AVRL
+ 0.5 LSB AVRL
+ 2.5 LSB mV
Full scale
transition voltage VFST AN0 to AN7 AVRH
– 4.5 LSB AVRH
– 1.5 LSB AVRH
+ 0.5 LSB mV
Conversion time 8.167*1——µs MASK/FLASH
Analog port input
current IAIN AN0 to AN7 0.1 10 µA
Analog input
voltage VAIN AN0 to AN7 AVRL AVRH V
Reference voltage AVRH AVRL + 2.7 AVCC V
AVRL 0 AVRH –
2.7 V
Power supply
current IAAVCC —3mA
IAH AVCC ——
5*2µA
Reference voltage
supply current IRAVRH 200 µA
IRH AVRH 5*2µA
Variation between
channels AN0 to AN7 4 LSB
MB90650A Series
96
RON1 RON2 RON3
C1
C0
RON4
Analog input Sample hold circuit
Comparator
Analog input circuit model diagram
RON1: Approx. 5 k
RON2: Approx. 617
RON3: Approx. 617
RON4: Approx. 473
C0: Approx. 35 pF
C1: Approx. 2 pF
Note : Use the values shown as guides only.
MB90650A Series
97
6. D/A Converter Electrical Characteristics
(MB90652A/653A: VCC = 2.2 V to 3.6 V, VSS = DVSS = 0.0 V, 2.2 V DVRH DVSS, TA = –40°C to +85°C)
(MB90F654A: VCC = 2.4 V to 3.6 V, VSS = DVSS = 0.0 V, 2.4 V DVRH DVSS, TA = –40°C to +85°C)
*1: Conversion time is the value at the load capacitance = 20 pF.
*2: DVRH – DVSS (AVSS)
*3: Current value at conversion
*4: Current value when stopped
Note : VCC = VCC1 = VCC2
Parameter Symbol Pin
name Value Unit Remarks
Min Typ Max
Resolution 8 8 bit
Differential
linearity error —— ±0.9 LSB
Absolute
accuracy —— 1%
Linearity error ±1.5 LSB
Conversion time 10.0 20.0 µs*1
Analog
reference power
supply voltage —DVRH 2.2 VCC V MB90652A/653A/654A*2
2.4 VCC V MB90F654A *2
Reference
voltage supply
current
IDVR DVRH 100 µA*3
IDVRS —— 5µA*4
Analog output
impedance —— 28 k
MB90650A Series
98
7. DTMF Electrical characteristics
(MB90652A/653A: VCC = 2.2 V to 3.6 V, VSS = DVSS = 0.0 V, 2.2 V DVRH DVSS, TA = –40°C to +85°C)
(MB90F654A: VCC = 2.4 V to 3.6 V, VSS = DVSS = 0.0 V, 2.4 V DVRH DVSS, TA = –40°C to +85°C)
Note : VCC =VCC1 = VCC2
Parameter Symbol Condition Value Unit Remarks
Min Typ Max
Output load
condition RO
VCC = 3 V
TA = +25°C
Machine clock
f = 12 MHz
30 k To be specified with DTMF
pin pull-down resistor
DTMF output
offset voltage
(At signal output) VMOF —0.4— V
When DTMF terminal is
opened
RO = 200 k
DTMF output
amplitude
(COL single tone) VMFC 450 530 600 mVP-P
DTMF output
amplitude
(ROW single tone) VMFOR 330 440 500 mVP-P
COL/ROW level
difference RMF 1.6 2.0 2.4 dB
VCC
VSS
X0
X1
RO
DTMF
48 dB / oct
Audio
Analizer
Output level measurement circuit
Output level
Low-pass filter
16MHz
MB90650A Series
99
8. Flash Memory Programming/Erase Characteristics
Parameter Conditions Value Unit Remarks
Min Typ Max
Sector erase time
TA = +25 °C
VCC = 3.0 V
115s
Excludes 00H
programming prior
erasure
Chip erase time 7sExcludes 00H
programming prior
erasure
Word (16-bit width)
programming time 16 3600 µsExcludes system-
level overhead
Program/Erase cycle 10,000 cycle
Data holding time 100,000 h
MB90650A Series
100
EXAMPLE CHARACTERISTICS
VIHS: Threshold when input voltage in hysteresis
characteristics is set to “H” level
VILS: Threshold when input voltage in hysteresis
characteristics is set to “L” level
VIH: Threshold when input voltage is set to “H” level
VIL: Threshold when input voltage is set to “L” level
(1) “H” Level Output Voltage (2) “L” Level Output Voltage
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0 –1 –2 –3 –4 –5
VCC = 2.4 V
VCC = 2.5 V
VCC = 2.7 V
VCC = 3.0 V
VCC = 3.3 V
VCC = 3.6 V
V
OH
vs. I
OH
T
A
= +25
°C
IOH (mA)
VOH (V)
VCC = 2.4 V
VCC = 2.5 V
VCC = 2.7 V
VCC = 3.0 V
VCC = 3.3 V
VCC = 3.6 V
T
A
= +25
°C
IOL (mA)
V
OL
vs. I
OL
VOL (V)
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.0 12345
V
IN
vs.
VCC
T
A
= +25
°C
VCC (V)
VIN (V)
VIH
VIL
2.4
2.2
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.42.4 2.7 3.0 3.3 3.6
V
IN
vs.
VCC
T
A
= +25
°C
VCC (V)
VIN (V)
VIHS
VILS
2.4
2.2
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.42.4 2.7 3.0 3.3 3.6
(3) “H” Level Input Voltage/“L” Level Input Voltage
(COMS Input) (4) “H” Level Input Voltage/“L” Level Input Voltage
(Hysteresis Input)
MB90650A Series
101
(5) Power Supply Current (fCP = Internal Operating Clock Frequency)
Mask ROM products
I
CC
vs.
V
CC
T
A
= +25
°C
VCC (V)
ICC (mA)
fCP = 12 MHZ
fCP = 10 MHZ
fCP = 8 MHZ
fCP = 5 MHZ
30
28
26
24
22
20
18
16
14
12
10
8
6
4
2
02.4 2.7 3 3.3 3.6
I
CCS
vs.
V
CC
T
A
= +25
°C
VCC (V)
ICCS (mA)
fCP = 12 MHZ
fCP = 10 MHZ
fCP = 8 MHZ
fCP = 5 MHZ
10
9
8
7
6
5
4
3
2
1
02.4 2.7 3 3.3 3.6
I
CCH
vs.
V
CC
T
A
= +25
°C
VCC (V)
ICCH (µA)
0.50
0.45
0.40
0.35
0.30
0.25
0.20
0.15
0.10
0.05
0.002.4 2.7 3 3.3 3.6
I
A
vs. A
V
CC
T
A
= +25
°C
AVCC (V)
IA (mA)
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.02.4 2.7 3 3.3 3.6
I
CCL
vs.
V
CC
T
A
= +25
°C
VCC (V)
ICCL (µA)
50
45
40
35
30
25
20
15
10
5
02.4 2.7 3 3.3 3.6
I
R
vs. A
V
CC
T
A
= +25
°C
AVCC (V)
IR (mA)
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.02.4 2.7 3 3.3 3.6
MB90650A Series
102
FLASH products
I
CC
vs.
VCC
VCC (V)
ICC (mA)
fCP
=
12 MHZ
fCP
=
10 MHZ
fCP
=
8 MHZ
fCP
=
5 MHZ
2.4 2.7 3 3.3 3.6
I
CCS
vs.
VCC
T
A
= +25
°C
VCC (V)
ICCS (mA)
fCP
=
12 MHZ
fCP
=
10 MHZ
fCP
=
8 MHZ
fCP
=
5 MHZ
10
9
8
7
6
5
4
3
2
1
02.4 2.7 3 3.3 3.6
I
CCH
vs.
VCC
VCC (V)
ICCH (µA)
2.4 2.7 3 3.3 3.6
I
CCL
vs.
VCC
T
A
= +25
°C
VCC (V)
ICCL (µA)
50
45
40
35
30
25
20
15
10
5
02.4 2.7 3 3.3 3.6
38
36
34
32
30
28
26
24
22
20
18
16
14
12
10
8
6
4
2
0
T
A
= +25
°C
0.80
0.75
0.70
0.65
0.60
0.55
0.50
0.45
0.40
0.35
0.30
0.25
0.20
0.15
0.10
0.05
0.00
T
A
= +25
°C
MB90650A Series
103
(6) Pull-up Resistance
Mask ROM products FLASH products
R
vs.
VCC
VCC (V)
R (k)
2.4 32.7 3.3 3.6
1000
100
10
T
A
= +25
°C
R
vs.
VCC
VCC (V)
R (k)
2.4 32.7 3.3 3.6
1000
100
10
T
A
= +25
°C
MB90650A Series
104
ORDERING INFORMATION
Part number Package Remarks
MB90652APFV
MB90653APFV
MB90654APFV
MB90F654APFV
100-pin plastic LQFP
(FPT-100P-M05)
MB90652APF
MB90653APF
MB90654APF
MB90F654APF
100-pin plastic QFP
(FPT-100P-M06)
MB90650A Series
105
PACKAGE DIMENSIONS
100-pin plastic LQFP
(FPT-100P-M05)
100-pin plastic QFP
(FPT-100P-M06)
C
2000 FUJITSU LIMITED F100007S-3c-5
14.00±0.10(.551±.004)SQ
16.00±0.20(.630±.008)SQ
125
26
51
76 50
75
100
0.50(.020) 0.20±0.05
(.008±.002) M
0.08(.003) 0.145±0.055
(.0057±.0022)
0.08(.003)
"A"
INDEX .059 –.004
+.008
–0.10
+0.20
1.50
(Mounting height)
0°~8°
0.50±0.20
(.020±.008)
0.60±0.15
(.024±.006)
0.25(.010)
0.10±0.10
(.004±.004)
Details of "A" part
(Stand off)
Dimensions in mm (inches)
C
2001 FUJITSU LIMITED F100008S-c-4-4
1 30
31
50
5180
81
100
20.00±0.20(.787±.008)
23.90±0.40(.941±.016)
14.00±0.20
(.551±.008)
17.90±0.40
(.705±.016)
INDEX
0.65(.026) 0.32±0.05
(.013±.002) M
0.13(.005)
"A"
0.17±0.06
(.007±.002)
0.10(.004)
Details of "A" part
0~8°
(.035±.006)
0.88±0.15
(.031±.008)
0.80±0.20
0.25(.010)
3.00 +0.35
–0.20
+.014
–.008
.118
(Mounting height)
0.25±0.20
(.010±.008)
(Stand off)
Dimensions in mm (inches)
MB90650A Series
FUJITSU LIMITED
All Rights Reserved.
The contents of this document are subject to change without notice.
Customers are advised to consult with FUJITSU sales
representatives before ordering.
The information and circuit diagrams in this document are
presented as examples of semiconductor device applications, and
are not intended to be incorporated in devices for actual use. Also,
FUJITSU is unable to assume responsibility for infringement of
any patent rights or other rights of third parties arising from the use
of this information or circuit diagrams.
The products described in this document are designed, developed
and manufactured as contemplated for general use, including
without limitation, ordinary industrial use, general office use,
personal use, and household use, but are not designed, developed
and manufactured as contemplated (1) for use accompanying fatal
risks or dangers that, unless extremely high safety is secured, could
have a serious effect to the public, and could lead directly to death,
personal injury, severe physical damage or other loss (i.e., nuclear
reaction control in nuclear facility, aircraft flight control, air traffic
control, mass transport control, medical life support system, missile
launch control in weapon system), or (2) for use requiring
extremely high reliability (i.e., submersible repeater and artificial
satellite).
Please note that Fujitsu will not be liable against you and/or any
third party for any claims or damages arising in connection with
above-mentioned uses of the products.
Any semiconductor devices have an inherent chance of failure. You
must protect against injury, damage or loss from such failures by
incorporating safety design measures into your facility and
equipment such as redundancy, fire protection, and prevention of
over-current levels and other abnormal operating conditions.
If any products described in this document represent goods or
technologies subject to certain restrictions on export under the
Foreign Exchange and Foreign Trade Law of Japan, the prior
authorization by Japanese government will be required for export
of those products from Japan.
F0209
FUJITSU LIMITED Printed in Japan