ees AT \V2500H/L. Features Third Generation Programmable Logic Structure Easily Achieves Gate Utilization Factors of 80 Percent e Increased Logic Flexibility 86 Inputs and 72 Sum Terms Flexible Output Macrocell 48 Flip-Flops - 2 per Macrocell 3 Sum Terms - Can Be ORed and Shared High Speed Low Power - Less than 0.5 mA Typical (ATV2500L) Multiple Feedback Paths Provide for Buried State Machines and I/O Bus Compatibility Asynchronous Clocks and Resets Multiple Synchronous Presets - One per Four or Eight Flip-Flops Proven and Reliable High Speed CMOS EPROM Process 2000 V ESD Protection 200 mA Latchup Immunity e Reprogrammable - Tested 100% for Programmability e 40-pin Dual-in-line and 44-Lead Surface Mount Packages Block Diagram al Programmable (Control Lines) Interconnect hn nt => and _ 48 lel 24 Le Ping Combinatorial Flip-Flops Output 24 VO Logic Array ( > Macros Pins Description The ATV2500H/L is the most powerful programmable logic device available in a 40 pin package. Increased Product terms, Sum Terms, and Flip-Flops translate into many more usable gates. High gate utilization is easily obtainable. The ATV2500H/L is organized around a global bus. All pin and feedback terms are always available to every Logic Cell. Each of the 38 logic pins and their complements are array inputs, as well as the true and false outputs of each of the 48 Flip-Flops. There are 416 Product Terms available. Four Product Terms are input to each Sum Term. The three Sum terms per Logic Cell can be combined to provide up to 12 Product Terms, Combi- natorial and Registered. Independent of output configuration, the two Flip-Flops are always usable, and always have at least four Product Term inputs. Product terms are available providing Asynchronous Resets, Flip-Flop clocks, and Output Enables. One reset and one clock term are provided per Flip-Flop, with one Enable term per output. Eight product terms provide local Synchronous Presets, divided up into banks of four and eight Flip-Flops. Register Preload and buried register observability simplify testing. The device has an internal power up clear function. IN 1 40 IN IN iN . . . IN iN Pin Configurations iN vot vos woe PinName Function ee hoe toe IN Logic Inputs tos Voto ne op . Veo 10 VON ve vo Bidirectional Buffers | yo17 20 f ano vor? vO16 O23 vO" 10,0,2,4.. |"Even"/OButfers | tors voz ots vO14 vo2t Vow VO,1,3,5.. |"Odd" /O Buffers vo1s vo20 vO13 VOI? vos * No Internal IN vors n 4 IN IN Connection N N vos voc +5 V Supply ING 2 2p IN * = No Comet AIMEL High Density UV Erasable Programmable Logic Device 7-83AIET Functional Logic Diagram ATV2500H/L INPUT TERMS 0,1,2,3,4,5,.... 86.91 169,170,174 4 / PIN # | (DIP,JLCc) (17,19) 1s | (18,20) 1 > | (19,21) 1 fs r (20,22) | Ss | iolriude) (21,23) 1 Ce HES (22,24) 1 Se i" (28,32) (23,25) 1 Ss ; r 1 63) 1s t |} 72 (2.2) 122...195 | Gat | (40,44) 1 Ss (g943) 1 s] GLOBAL BUS | (38,42) |) =o e724) 1 | 36...49 | 8 ! 6 les seo7 pe 22 (28,31) J___ry gp - i Te TT TTI 3 98-103 7 a 4 | uo28 (27,30) 104-108 6 172 : -fito-20 (25.2) HOS a7] 8 rcs 4 6 489 (25,28) 116121 172 J00-18 (24,27) . ee ars Pia e] 2 (11,13) 26 pe ee 17 (11 160-165) st yt , * 172,86 <a St (12,14) 154-150 es) I ses oo fo Te 148-153 "og [ae ss (13,15) aaa 6 pee (14,18) < a ae] 1013 (15,17) 196-144 | 6 i726] ey rr | J-12 (18,18) J____ yO T spy Os 6 . eee Sse ese eee eee 7 6 ley 6-411 6 | 172 | |vo-14 (31,35) fa (32,36) : ], . 7 18-23 6 } 172 | {ide (33,37) ov 24-20 6 i - 08 (34.38) ej] 30-95 uz ter (35,39) | 17278 | oa 06 = (36,40) - i sO 4 17276 4 2 80-85 6 Pa] Ws (8,10) oan oe te JT spy 68-73, 6 ---eCo ee +] ea 6267 6 - 3 178) oO Ta ea 661 8 pa ee 67) . 6 50-85 6 pe (5,6) | 1728 | too (43) 7-84 ATV2500H/L cumeen AT \25(00H/L Functional Logic Diagram Description Absolute Maximum Ratings* The ATV2S500H/L Functional Logic Diagram describes the in- . o 3 terconnections between the input, feedback pins and Logic Temperature Under Bias ................ -55C to +125C Cells. All interconnections are routed through the Global Bus. , Storage Temperature... -65C to +150C The ATV2500H/L is a straightforward and uniform EPLD. The 9 pe * 24 Macrocells are numbered 0 through 23. Each Macrocell con- Voltage on Any Pin with tains 17 AND gates. All AND gates have 172 inputs. The five Respect to Ground... -2.0 V to +7.0 Vi) lower product terms provide AR1, CK1, CK2, AR2, and OE. . These are: one asynchronous reset and clock per Flip-Flop, and Voltage on Input Pins an Output Enable. The top 12 product terms are grouped into with Respect to Ground 4) three sum terms, which are used as shown in the Macrocell dia- During Programming................... -2.0 Vio +14.0V ah ams. . . Programming Voltage with Eight Synchronous Preset terms are distributed in a 2/4 pattern. Respect to Ground... -2.0 V to +14.0 V") The first four Macrocells share Preset 0, the next two share Pre- set 1, and so on, ending with the last two Macrocells sharing Integrated UV Erase Dose.............. 7258 W.sec/cm? Preset 7. The 14 dedicated inputs and their complements use the num- *NOTICE: Stresses beyond those listed under "Absolute Maxi- bered positions in the global bus as shown. Each Macrocell pro- mum Ratings may cause permanent damage to the device. vides six inputs to the global bus: (left to right) Flip-Flop Q2 This is a stress rating only and functional operation of the de- true and false, Flip-Flop Q1 true and false, and the pin true and vice at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended 7 periods may affect device reliability. false. The positions occupied by these signals in the Global Bus are the six numbers in the bus diagram next to each Macrocell. Note: 1. Minimum voltage is -0.6 V dc which may undershoot to -2.0 V for pulses of less than 20 ns. Maximurn output pin voltage is Vec+0.75 V de which may overshoot to +7.0 V for pulses of less than 20 ns. Operating Modes 40-Pin DIP 21 2 3 23 20 Voc(10) Odd Even Mode 44-Pin JLCC 8=23 2 42isi85 22 Vcc(11,12) Os Os "EPLD" x) XY xX xX Xx 5V vO vO Program Vpp X x Vu @ 6V DIN NG. PGM Verify Vpp X X X VIL 6V Dout Vou PGM Inhibit Vpep X X X Vin 6V High Z High Z Preload Q1 SUL X Va VV Vi 5V Din(Ever/Odd) Vin Preload Q2 Ju X VA WV Vin 5V Din(Ever/Odd) Vin Observe Q2 X VH X xX xX 5V DouT DouT Notes: 1. X can be Vy. or Vin. 2. Vo = 11.0 V to 14.0 V AIMEL 7-5Aliniet Output Logic, Registered Output Logic, Combinatorial 2 gee seman Note: 1. These diagrams shows equivalent logic functions, not necessarily the actual circuit implementation. Terms In Terms in $2. Si___S0 D1 D2 | Output Configuration S2. Si so D1 02 Output Configuration 0 0 0 8 4 Registered (Q1) 1 0 0 a 4 Combinatorial (8 Terms) 0 1 0 12. 4! | Registered (Q1) 1 0 1 4 4 Combinatorial (4 Terms) Note: 1. These 4 terms are shared with D1. 1 1 o | 4 4 | Combinatorial (12 Terms) Note: 1. These 4 terms are shared with D1. $3 Output Configuration $3 Output Configuration 0 Active Low 9 Active Low 1 Active High 1 Active High D.C. and A.C. Operating Conditions ATV2500H-25 ATV2500H/L-30 ATV2500H/L-35 ATV2500L-40 ATV2500L-45 0, 3 oC. o o, 0, Oo, fe) Operating Com. 0C - 70C 0C - 70C 0C - 70C 0c - 70C (ca Ind. -40C - 85C -40C - 85C -40C - 85C -40C - 85C -40C - 85C Mil. -55C-125C = -55C - 125C = 55C - 125C = -55C - 125C ~ -55C - 125C Voc Power Supply 5 V+ 10% 5V+ 10% 5V+ 10% 5V+10% 5V+ 10% 7-86 ATV2500H/L summersees AT \25()(0 1-1/1 D.C. Characteristics Symbol Parameter Condition Min Typ Max Units lu Input Load Current Vin =-0.1 Vto Vec+1V 10 pA k: lo Cutbut Lea age Vout = -0.1 Vto Voc40.1 V 10 pA Com. 1.0 5 mA Voc = MAX, ATV2500L - loc cower Supply Vin = GND or Voc Ind.,Mil. 1.0 10 mA Outputs Open Com. 80 160 mA ATV2500H Ind.,Mil. 80 180 mA Clocked Power t = 1MHz, Com. 10 15 mA Ioc2 Supply Current Voc = MAX (ATV2500L) Outputs Open Ind.,Mil. 10 20 mA (1) | Output Short _ Z los Circuit Current Vout = 0.5V 90 mA ViL Input Low Voltage -0.6 0.8 Vv VIH Input High Voltage 2.0 Voc+0.75 Vv Vot Output Low Voltage VIN = Vin or Vit, 0.5 v P 9 lol = 8 MA Com, Ind: 6 mA Mil. : loH = -100pA Vec-0.3 Vv VoH Output High Voltage OH ce loH = -4.0 mA 2.4 Notes: 1. Not more than one output at a time should be shorted. Duration of short circuit test should not exceed 30 sec.This parameter is only sampled and is not 100% tested. See Absolute Maximum Ratings. Pin Capacitance (f = 1 MHz, T = 25C) Typ Max Units Conditions CIN 4 6 pF VIN=0V Cout 8 12 pF Vout =0V Note: 1. Typical values for nominal supply voltage. This parameter is only sampled and is not 100% tested. ANMEL 7-87A.C. Waveforms INPUTS,VO REG. FEEDBACK SYNCH. PRESET PS yet a ce wv __} 4 w 1P t tAR -| ASYNCH. RESET AW | rtcO tAP = tER REGISTERED OUTPUT OUTPUT OUTPUT OUTPUTS VALID VALID K1PD L ca COMBINATORIAL OUTPUT OUTPUT OUTPUTS VALID VALID Note: 1. Timing measurement reference is 1.5 V. Input AC driving levels are 0.0 V and 3.0 V, unless otherwise specified. A.C. Characteristics for the ATV2500L ATV2500L-30 | ATV2500L-35 | ATV2500L-40 | ATV2500L-45 Symbol Parameter Min Max Min Max Min Max Min Max Units Input or Feedback to to Non-Registered Output 30 35 40 45 ns tea Input to Output Enable 30 35 40 45 ns tER Input to Output Disable 30 35 40 45 ns tco Clock to Output 5 30 5 35 5 40 5 45 ns tcrF Clock to Feedback 10 20 15 20 15 22 15 25 ns Input Setup Time, Output tsi Register 20 22 25 30 ns Input Setup 'si2_ | Time, Buried Register"? S 5 $ 5 ns isF Feedback Setup Time 10 15 18 20 ns tH Hold Time, Output Register 10 15 15 15 ns tHe Hold Time, Buried Register!) 5 5 5 5 ns tw Clock Width 12 15 17 20 ns tp Clock Period 30 35 40 45 ns Faax | Maximum Frequency (1/tp) 33 28 25 22 MHz taw Asynchronous Reset Width 18 20 22 25 ns Asynchronous Reset TAR Recovery Time 18 20 22 25 ns Asynchronous Reset to lap Registered Output Reset 30 35 40 45 ns Note: 1. Buried registers include all 24 Q2 registers and any of the 24 Q1 registers in macrocells configured as combinatorial. 7-88 ATV2500H/L cummmeesees AT \V/2500H/L A.C. Characteristics for the ATV2500H ATV2500H-25 ATV2500H-30 ATV2500H-35 Symbol | Parameter Min Max Min Max Min Max Units Input or Feedback to {Pp Non-Registered Output 25 30 35 ns tEA Input to Output Enable 25 30 35 ns {ER Input to Output Disable 25 30 35 ns tco Clock to Output 10 25 12 30 15 35 ns tcr Clock to Feedback 10 18 12 20 15 20 ns Input Setup sit | Time, Output Register 10 12 15 ns Input Setup siz | Time, Buried Register!) 5 5 5 ns tsF Feedback Setup Time 7 10 15 ns tH1 Hold Time 5 5 5 ns tw Clock Width 10 12 15 ns tp Clock Period 25 30 35 ns Fmax | Maximum Frequency (1/p) 40 33 28 MHz Asynchronous Reset taw Width 15 18 20 ns Asynchronous Reset tan Recovery Time 15 18 20 ns Asynchronous Reset to lap Registered Output Reset 25 30 3 ns Note: 1. Buried registers include all 24 Q2 registers and any of the 24 Q1 registers in macrocells configured as combinatorial. input Test Waveforms and Output Test Load Measurement Levels 5.0V 3.0V R1=450 AC AC DRIVING < MEASUREMENT (580 MIL.) OTE N LEVELS cov LEVEL R2=250 CL=50pF (260 MIL.) tL iR,tF<Sns (10% to 90%) AIMEL 7.69 esAIMEL Preload and Observability of Registered Outputs The ATV2500H/Ls registers are provided with circuitry to allow loading of each register asynchronously with either a high ora low. This feature will simplify testing since any state can be forced into the registers to control test sequencing. A ViH level on the Odd I/O pins will force the appropriate register high; a Vin will force it low, independent of the polarity or other con- figuration bit settings. The PRELOAD state is entered by placing an 11 V to 14 V sig- nal on pin 38 on the DIP and pin 42 on the SMP. When the clock term is pulsed high, (pin 21 on the DIP, pin 23 on the SMP) the data on the I/O pins is placed into the 12 registers chosen by the Q Select and Even/Odd Select Pins. Register 2 Observability Mode is entered by placing an 11 V to 14 V signal on pin 2 (DIP or SMP). In this mode, the contents of the Buried Register bank wil! appear on the associated out- puts when the OE control signals are active. D D DB b iD = VM t t! t t t tomin = 100 ns PRELOAD CLOCK REGISTERED OUTPUTS OUTPUT PRELOAD ENA. | FORCE I/0'S PRELOAD DATA VOLTAGE PRELOAD OUTPUTS DIS. TOVIHORVIL CLOCKED IN REMOVED DISABLED Level forced on Q Select Even/ Even Q1 Even Q2 Odd Q1 Odd Q2 Odd I/O pin during Pin Odd state after stateafter stateafter state after PRELOAD cycle. State Select cycle cycle cycle cycle VIH Low Low High x X Xx VIL Low Low Low xX x Xx ViH High Low xX High xX x Vit High Low Xx Low x X Vin Low High x xX High x Vit Low High xX x Low xX Vix High High xX xX x High VIL High High x Xx xX Low Power Up Reset 3.8V The registers in the ATV2500H/L are designed to reset during POWER power up. Ata point delayed slightly from Vcc crossing 3.8 V, tPR all registers will be reset to the low state. The output state will depend on the polarity of the output buffer. REGISTERED : so ates wee ee OUTPUTS tS This feature is critical for state machine initialization. However, due to the asynchronous nature of reset and the uncertainty of how Vcc actually rises in the system, the following conditions are required: 1) The Vcc rise must be monotonic, 2) After reset occurs, all input and feedback setup times must be met before driving the clock term high, and 3) The signals from which the clock is derived must remain stable during tpr. 7-30 ATV2500H/L TE tw CLOCK Parameter Description Min Typ Max Units Power-Up tPR Reset Time 600 1000 nsees ATV 25()0H/L Security Fuse Usage A single fuse is provided to prevent unauthorized copying of the ATV2S00H/L fuse patterns. Once programmed, the outputs will read programmed during verify. The security fuse should Atmel CMOS EPLDs Atmels Erasable Programmable Logic Devices utilize an ad- vanced 1.25-micron CMOS EPROM technology. This technologys state of the art features are the optimum combina- tion for EPLDs: * CMOS technology provides high speed, low power, and high noise immunity. * EPROM technology is the most cost effective method for producing EPLDs - surpassing bipolar fusible link technol- be programmed last, as its effect is immediate. The security fuse also inhibits Preload and Q2 observability. ogy in low cost, while providing the necessary reprogrammability. EPROM reprogrammability, which is 100% tested before shipment, provides inherently better programmability and re- liability than one-time fusible PLDs. * Atmels EPROM process has proven extremely reliable in the volume production of a full line of advanced EPROM memory products, from 64K to one-megabit devices. Using The ATV2500s Many Advanced Features The ATV2500H/Ls flexibility puts more usable gates in 40 pins than other EPLDs. Some of the ATV2500H/Ls key fea- tures are: * Asynchronous Clocks - Each of the Flip-Flops in the ATV2500H/L has a dedicated product term driving the clock. The user is no longer con- strained to using one clock for all the registers. Buried state ma- chines, counters, and registers can all coexist in one device, while running on separate clocks. The ATV2500H/L clock pe- riod matches that of similar synchronous devices. * A Total of 48 Registers - The ATV2500H/L provides two Flip-Flops for each Output Macrocell - a total of 48. Each register has its own clock and reset product terms, as well as its own SUM term. Independent I/O Pin and Feedback Paths - Each I/O pin on the ATV2500/H has a dedicated input path. Each of the 48 registers has individual feedback terms into the Programming Software Support Software which is capable of transforming Boolean equations, state machine descriptions and truth tables into JEDEC files for the ATV2500H/L is currently available from the following sources: Erasure Characteristics The entire memory array of an ATV2500H/L is erased after ex- posure to ultraviolet light at a wavelength of 2537 A. Complete erasure is assured after a minimum of 20 minutes exposure using 12,000 uW/em? intensity lamps spaced one inch away from the chip. Minimum erase time for lamps at other intensity ATmEt array. This feature, combined with individual product terms for each 1/Os Output Enable, facilitates designs using bi-direc- tional I/O buses. Three Sum Terms per Macrocell - The ATV2500H/L Macrocell can be configured with one Sum term feeding the output, and still have two Sum terms feeding the Flip-Flops. This is the simplest method for interfacing with an I/O bus, and no Flip-Flops need be sacrificed. Combinable Sum Terms - Each Output Macrocells three SUM terms can be combined in an OR gate before the Output or the Register. This provides up to 12 product terms per Output or Flip-Flop. When the Regis- tered Output configuration is chosen, eight terms are automati- cally available to D1. The four terms feeding D2 can also be shared with D1, giving it a total of 12. In the combinatorial mode, four, eight, or 12 terms can feed the output, with the mid- dle four still driving D1 and the bottom four still driving D2. Data I/O / Futurenet Corp. - ABEL 4,0 and above Logical Devices - CUPL 3.0 and above Atmel Corp. -Atmel-ABEL-4 ratings can be calculated from the minimum integrated erasure dose of 15 W-sec/cm*. To prevent unintentional erasure, an opaque label is recommended to cover the clear window on any UV erasable EPLD which will be subjected to continuous fluo- rescent indoor lighting or sunlight. 7-91AlmEt SUPPLY CURRENT vs. INPUT FREQUENCY NORMALIZED ICC vs. AMBIENT TEMP. 8 9 TA = 25, VCC = 5V f = 20 MHz, VCC =5V u 12 P N C 2 IN Y 60 m 14 Pr L u 140 MN, R z ~S : % D N 09 zo os pS 3 6 9 12 15 1 2k 55 25 5 35 65 95 125 INPUT FREQUENCY (MHz) AMBIENT TEMPERATURE (C) SUPPLY CURRENT vs. SUPPLY VOLTAGE SUPPLY CURRENT vs. SUPPLY VOLTAGE f=0HZ, TA=25C f = 20 MHz, TA = 25C gs 0.13 gs 120 u u P P 110 t L YY o.10 y a cw u u - 0.07 E c 70 T T 60 A 004 A 80 40 45 50 55 60 40 45 50 55 60 SUPPLY VOLTAGE (V) SUPPLY VOLTAGE (V) OUTPUT SINK CURRENT OUTPUT SINK CURRENT vs, SUPPLY VOLTAGE (VOL = 0.5V) vs. OUTPUT VOLTAGE (TA = 25C, VCC = SV) 7 T P P u u T T c c uv u R R R R E E N N t T A 40 45 50 55 60 a 0 1 2 3 4 5 SUPPLY VOLTAGE (V) OUTPUT VOLTAGE (V) OUTPUT SOURCE CURRENT OUTPUT SOURCE CURRENT vs. SUPPLY VOLTAGE (VOH = 2.4V) vs. OUTPUT VOLTAGE (TA = 25C, VCC = 5V) v o Y 0 Pp WN Pp -10 u u T 45 he 1 % u > U ., _ MN . E ~ E -50 N N T mm N wp m 45 m= -70 A 40 45 5.0 55 60 a 0 1 2 3 4 5 SUPPLY VOLTAGE (V) OUTPUT VOLTAGE () 7-92 ATV2500H/Lees AT \ 2500 1/1 NORMALIZED TPD NORMALIZED TPD vs. SUPPLY VOLTAGE - vs. TEMPERATURE N xy : m 12 L. 1 z 1 a Y d : 10 a P 5 La i D 09 4.0 45 5.0 55 60 55 25 5 35 65 95 125 Supply Voltage (V) Ambient Temperature (C) NORMALIZED TCO NORMALIZED TCO vs. SUPPLY VOLTAGE ; vs. TEMPERATURE 4 3 : ane L ' VY ' 2 4 A 4 10 T G 5 | og 40 45 50 55 6.0 55 +25 5 35 65 95 125 Supply Voltage (V) Ambient Temperature (C) DELTA TPD vs. OUTPUT LOADING DELTA TCO vs. OUTPUT LOADING TA = 25C, VCC = 5V TA = 25C, VCC = 5V D D \ \ t t T T Pp c D 0 100 200 300 400 , 0 100 200 300 400 Output Load (jig incld) Capacitance pF Output Load (jig incld) Capacitance pF AIMEL 7-93AINE? Ordering Information t t fMax (ns) (ns) (MHz) Ordering Code Package Operation Range 26 25 40 ATV2500H-25DC 40DW6 Commercial ATV2500H-25JC 44J (0C to 70C) ATV2500H-25KC 44KW ATV2500H-25LC 44LW ATV2500H-25PC 40P6 ATV2500H-25DI 40DW6 Industrial ATV2500H-25J1 44J (-40C to 85C) ATV2500H-25KI 44KW ATV2500H-25L1 44LW ATV2500H-25PI 40P6 ATV2500H-25DM 40DW6 Military ATV2500H-25KM 44KW (-55C to 125C) ATV2500H-25LM 44LW ATV2500H-25DM/883 40DW6 Military/883C ATV2500H-25KM/883 44KW (-55C to 125C) ATV2500H-25LM/883 44LW Class B, Fully Compliant 30 30 33 ATV2500H-30DC 40DW6 Commercial ATV2500H-30JC 44J (0C to 70C) ATV2500H-30KC 44kKw ATV2500H-30LC 44LW ATV2500H-30PC 40P6 ATV2500H-30DI 40DW6 Industrial ATV2500H-30JI 44J (-40C to 85C) ATV2500H-30kKI 44KW ATV2500H-30LI 44LW ATV2500H-30PI 40P6 ATV2500H-30DM 40DW6 Military ATV2500H-30KM 44KW (-55C to 125C) ATV2500H-30LM 44LW ATV2500H-30DM/883 40DW6 Military/883C ATV2500H-30KM/883 44KW (-55C to 125C) ATV2500H-30LM/883 44LW Class B, Fully Compliant 35 35 28 ATV2500H-35DC 40DW6 Commercial ATV2500H-35JC 44J (0C to 70C) ATV2500H-35KC 44KW ATV2500H-35LC 44LW ATV2500H-35PC 40P6 ATV2500H-35DI 40DW6 Industrial ATV2500H-35uI 44J (-40C to 85C) ATV2500H-35KI 44KW ATV2500H-35L! 44LW ATV2500H-35PI 40P6 ATV2500H-35DM 40DW6 Military ATV2500H-35KM 44KW (-85C to 125C) ATV2500H-35LM 44LW ATV2500H-35DM/883 40DW6 Military/883C ATV2500H-35KM/883 44KW (-55C to 125C) ATV2500H-35LM/883 44LW Class B, Fully Compliant 7-94 ATV2500H/L. enummemes A TV 25()0 1/1 Ordering Information tPD tco fMax . . (ns) (ns) (MHz) Ordering Code Package Operation Range 25 25 40 5962-91545 02M QX 40DW6 Military/833C 5962-91545 02M XX 44LW (-55C to 125C) 6962-91545 02M YX 44KW Class B, Fully Compliant 30 30 33 5962-91545 01M QX 40DW6 Military/833C 5962-91545 01M XX 44LW (-55C to 125C) 5962-91545 01M YX 44KW Class B, Fully Compliant Package Type 40DW6 40 Lead, 0.600" Wide Windowed, Ceramic Dual Inline Package (Cerdip) 44J 44 Lead, Plastic J-Leaded Chip Carrier OTP (PLCC) 44KW 44 Lead, Windowed, Ceramic J-Leaded Chip Carrier (JLCC) 44Lw 44 Pad, Windowed, Ceramic Leadless Chip Carrier (LCC) 40P6 40 Lead, 0.600" Wide Plastic Dual Inline Package OTP (PDIP) AIMEL 795ADE Ordering Information t t f (ns) (ns) (MHz) Ordering Code Package Operation Range 30 30 33 ATV2500L-30DC 40DW6 Commercial ATV2500L-30JC 44] (0C to 70C) ATV2500L-30KC 44KW ATV2500L-30LC 44LW ATV2500L-30PC 40P6 ATV2500L-30DI 40DW6 industrial ATV2500L-30JI 44J (-40C to 85C) ATV2500L-30KI 44KW ATV2500L-30LI 44LW ATV2500L-30Pi 40P6 ATV2500L-30DM 40DW6 Military ATV2500L-30KM 44KW (-55C to 125C) ATV2500L-30LM 44LW ATV2500L-30DM/883 40DW6 Military ATV2500L-30KM/883 44KW (-55C to 125C) ATV2500L-30LM/883 44LW Class B, Fully Compliant 35 35 28 ATV2500L-35DC 40DW6 Commercial ATV2500L-35JC 44J (0C to 70C) ATV2500L-35KC 44KW ATV2500L-35LC 44LW ATV2500L-35PC 40P6 ATV2500L-35DI 40DW6 Industrial ATV2500L-35JI 44J (-40C to 85C) ATV2500L-35KI 44KW ATV2500L-35Li 44LW ATV2500L-35PI 40P6 ATV2500L-35DM 40DW6 Military ATV2500L-35KM 44KW (-55C to 125C) ATV2500L-35LM 44LW ATV2500L-35DM/883 40DW6 Military ATV2500L-35KM/883 44KW (-55C to 125C) ATV2500L-35LM/883 44LW Class B, Fully Compliant 40 40 25 ATV2500L-40DC 40DW6 Commercial ATV2500L-40JC 44J (0C to 70C) ATV2500L-40KC 44KW ATV2500L-40LC 44LW ATV2500L-40PC 40P6 ATV2500L-40DI 40DW6 Industrial ATV2500L-40JI 44J (-40C to 85C) ATV2500L-40KI 44KW ATV2500L-40LI 44LW ATV2500L-40PI 40P6 ATV2500L-40DM 40DW6 Military ATV2500L-40KM 44KW (-55C to 125C) ATV2500L-40LM 44LW ATV2500L-40DM/883 40DW6 Military/883C ATV2500L-40KM/883 44KW (-55C to 125C) ATV2500L-40LM/883 44LW Class B, Fully Compliant 7-96 ATV2500H/L cueees A 1 \2500H/L Ordering Information tp t {Max (ns) (ns) (MHz) Ordering Code Package Operation Range 45 45 22 ATV2500L-45D! 40DW6 Industrial ATV2500L-45JI 44J (-40C to 85C) ATV2500L-45KI 44KW ATV2500L-45LI 44LW ATV2500L-45PI 40P6 ATV2500L-45DM 40DW6 Military ATV2500L-45KM 44KW (-55C to 125C) ATV2500L-45LM 44Lw ATV2500L-45DM/883 40DW6 Military/883C ATV2500L-45KM/883 44KW (-55C to 125C) ATV2500L-45LM/883 44LW Class B, Fully Compliant 30 30 33 5962-91545 03M QX 40DW6 Military/833C 5962-91545 03M XX 44LW (-55C to 125C) 5962-91545 03M YX 44KW Class B, Fully Compliant Package Type 40DW6 40 Lead, 0.600" Wide Windowed, Ceramic Dual Inline Package (Cerdip) 44J 44 Lead, Plastic J-Leaded Chip Carrier OTP (PLCC) 44KW 44 Lead, Windowed, Ceramic J-Leaded Chip Carrier (JLCC) 44LW 44 Pad, Windowed, Ceramic Leadiess Chip Carrier (LCC) 40P6 40 Lead, 0.600" Wide Plastic Dual Inline Package OTP (PDIP) AIMEL 797AIMEL 7-98