©2009 Integrated Device Technology, Inc.
JANUARY 2009
DSC-5652/6
1
HIGH-SPEED 2.5V
512/256/128K X 18
SYNCHRONOUS
DUAL-PORT STATIC RAM
WITH 3.3V OR 2.5V INTERFACE
IDT70T3339/19/99S
Functional Block Diagram
– Self-timed write allows fast cycle time
◆Separate byte controls for multiplexed bus and bus
matching compatibility
◆Dual Cycle Deselect (DCD) for Pipelined Output Mode
◆2.5V (±100mV) power supply for core
◆LVTTL compatible, selectable 3.3V (±150mV) or 2.5V
(±100mV) power supply for I/Os and control signals on
each port
◆Industrial temperature range (-40°C to +85°C) is
available at 166MHz and 133MHz
◆Available in a 256-pin Ball Grid Array (BGA), a 144-pin Thin
Quad Flatpack (TQFP) and 208-pin fine pitch Ball Grid Array
(fpBGA)
◆Supports JTAG features compliant with IEEE 1149.1
◆Due to limited pin count JTAG, Collision Detection and
Interrupt are not supported on the 144-pin TQFP package
◆Green parts available, see ordering information
Features:
◆True Dual-Port memory cells which allow simultaneous
access of the same memory location
◆High-speed data access
– Commercial: 3.4 (200MHz)/3.6ns (166MHz)/
4.2ns (133MHz)(max.)
– Industrial: 3.6ns (166MHz)/4.2ns (133MHz) (max.)
◆Selectable Pipelined or Flow-Through output mode
◆Counter enable and repeat features
◆Dual chip enables allow for depth expansion without
additional logic
◆Interrupt and Collision Detection Flags
◆Full synchronous operation on both ports
– 5ns cycle time, 200MHz operation (14Gbps bandwidth)
– Fast 3.4ns clock to data out
– 1.5ns setup to clock and 0.5ns hold on all control, data, and
address inputs @ 200MHz
– Data input, address, byte enable and control registers
1. Address A18 is a NC for the IDT70T3319. Also, Addresses A18 and A17 are NC's for the IDT70T3399.
2. The sleep mode pin shuts off all dynamic inputs, except JTAG inputs, when asserted. All static inputs, i.e., PL/FTx and
OPTx and the sleep mode pins themselves (ZZx) are not affected during sleep mode.
NOTES:
Dout0-8_L
B
W
0
L
B
W
1
L
Din_L
OE
L
UB
L
LB
L
R/W
L
CE
0L
CE
1L
ab
FT/PIPE
L0/1
1b 0b 1a 0a
1
0
1/0
0b 1b0a 1a
ab
FT /PIPE
L1/0
REPEAT
R
A
0R
CNTEN
R
AD S
R
Dout0-8_R
Dout9-17_R
I/O
0R
-I/O
17R
Din_R
ADDR_R
OE
R
UB
R
LB
R
R/W
R
CE
0R
CE
1R
FT/PIPE
R
CLK
R
,
Counter/
Address
Reg.
B
W
1
R
B
W
0
R
FT/PIPE
R
Counter/
Address
Reg.
CNTEN
L
ADS
L
REPEAT
L
Dout9-17_L
I/O
0L
-I/O
17L
A
18L
(1)
A
0L
ADDR_L
5652 drw 01
512/256/128K x 18
MEMORY
ARRAY
CLK
L
,
ba
0/1
0b
1b
0a 1a
1
0
1/0
1b 0b 1a 0a
ab
1/0
INTERRUPT
COLLISION
DETECTION
LOGIC
INT
L
COL
L
INT
R
COL
R
R/
W
L
R/
W
R
CE
0L
CE1L
CE
0R
CE1R
ZZ
CONTROL
LOGIC
ZZ
L(2)
ZZ
R(2)
JTAG
TCK
TRST
TMS
TDO
TDI
A
18R(1)
6.42
IDT70T3339/19/99S
High-Speed 2.5V 512/256/128K x 18 Dual-Port Static RAM Industrial and Commercial Temperature Ranges
2
Description:
The IDT70T3339/19/99 is a high-speed 512/256/128k x 18 bit
synchronous Dual-Port RAM. The memory array utilizes Dual-Port
memory cells to allow simultaneous access of any address from both ports.
Registers on control, data, and address inputs provide minimal setup and
hold times. The timing latitude provided by this approach allows systems
to be designed with very short cycle times. With an input data register, the
IDT70T3339/19/99 has been optimized for applications having unidirec-
tional or bidirectional data flow in bursts. An automatic power down feature,
controlled by CE0 and CE1, permits the on-chip circuitry of each port to
enter a very low standby power mode.
The IDT70T3339/19/99 can support an operating voltage of either
3.3V or 2.5V on one or both ports, controllable by the OPT pins. The power
supply for the core of the device (VDD) is at 2.5V.
6.42
IDT70T3339/19/99S
High-Speed 2.5V 512/256/128K x 18 Dual-Port Static RAM Industrial and Commercial Temperature Ranges
3
70T3339/19/99BC
BC-256(8)
256-Pin BGA
Top View (9)
Pin Configuration (3,4,5,6,9)
NOTES:
1. Pin is a NC for IDT70T3319 and IDT70T3399.
2. Pin is a NC for IDT70T3399.
3. All VDD pins must be connected to 2.5V power supply.
4. All VDDQ pins must be connected to appropriate power supply: 3.3V if OPT pin for that port is set to VDD (2.5V), and 2.5V if OPT pin for that port is
set to VSS (0V).
5. All VSS pins must be connected to ground supply.
6. Package body is approximately 17mm x 17mm x 1.4mm, with 1.0mm ball-pitch.
7. This package code is used to reference the package diagram.
8. This text does not indicate orientation of the actual part-marking.
9. Pins A15 and T15 will be VREFL and VREFR respectively for future HSTL device.
E16
I/O
7R
D16
I/O
8R
C16
I/O
8L
B16
NC
A16
NC
A15
NC
B15
NC
C15
NC
D15
NC
E15
I/O
7L
E14
NC
D14
NC
D13
V
DD
C12
A
6L C14
OPT
L
B14
V
DD
A14
A
0L
A12
A
5L
B12
A
4L
C11
ADS
L
D12
V
DDQR
D11
V
DDQR
C10
CLK
L
B11
REPEAT
L
A11
CNTEN
L
D8
V
DDQR
C8
NC
A9
CE
1L
D9
V
DDQL
C9
LB
L
B9
CE
0L
D10
V
DDQL
C7
A
7L
B8
UB
L
A8
NC
B13
A
1L
A13
A
2L
A10
OE
L
D7
V
DDQR
B7
A
9L
A7
A
8L
B6
A
12L
C6
A
10L
D6
V
DDQL
A5
A
14L
B5
A
15L
C5
A
13L
D5
V
DDQL
A4
A
17L
(2)
B4
A
18L
(1)
C4
A
16L
D4
PIPE/
FT
L
A3
NC
B3
TDO
C3
V
SS
D3
NC
D2
I/O
9R
C2
I/O
9L
B2
NC
A2
TDI
A1
NC
B1
INT
L
C1
COL
L
D1
NC
E1
I/O
10R
E2
I/O
10L
E3
NC
E4
V
DDQL
F1
I/O
11L F2
NC
F4
V
DDQL
G1
NC
G2
NC
G3
I/O
12L
G4
V
DDQR
H1
NC
H2
I/O
12R
H3
NC
H4
V
DDQR
J1
I/O
13L J2
I/O
14R J3
I/O
13R J4
V
DDQL
K1
NC
K2
NC
K3
I/O
14L
K4
V
DDQL
L1
I/O
15L L2
NC
L3
I/O
15R L4
V
DDQR
M1
I/O
16R M2
I/O
16L M3
NC
M4
V
DDQR
N1
NC
N2
I/O
17R N3
NC
N4
PIPE/
FT
R
P1
COL
RP2
I/O
17L P3
TMS
P4
A
16R
R1
INT
RR2
NC
R3
TRST
R4
A
18R
(1)
T1
NC
T2
TCK
T3
NC
T4
A
17R
(2)
P5
A
13R
R5
A
15R
P12
A
6R
P8
NC
P9
LB
R
R8
UB
R
T8
NC
P10
CLK
R
T11
CNTEN
R
P11
ADS
R
R12
A
4R
T12
A
5R
P13
A
3R
P7
A
7R
R13
A
1R
T13
A
2R
R6
A
12R
T5
A
14R T14
A
0R
R14
OPT
R
P14
NC
P15
NC
R15
NC
T15
NC
T16
NC
R16
NC
P16
I/O
0L
N16
NC
N15
I/O
0R
N14
NC
M16
NC
M15
I/O
1L
M14
I/O
1R
L16
I/O
2R
L15
NC
L14
I/O
2L
K16
I/O
3L
K15
NC
K14
NC
J16
I/O
4L
J15
I/O
3R
J14
I/O
4R
H16
I/O
5R
H15
NC
H14
NC
G16
NC
G15
NC
G14
I/O
5L
F16
I/O
6L
F14
I/O
6R F15
NC
R9
CE
0R R11
REPEAT
R
T6
A
11R
T9
CE
1R
A6
A
11L
B10
R/W
L
C13
A
3L
P6
A
10R
R10
R/W
R
R7
A
9R
T10
OE
R
T7
A
8R
,
E5
V
DD
E6
V
DD
E7
NC
E8
V
SS
E9
V
SS
E10
V
SS
E11
V
DD
E12
V
DD
E13
V
DDQR
F5
V
DD F6
NC
F8
V
SS
F9
V
SS F10
V
SS F12
V
DD F13
V
DDQR
G5
V
SS G6
V
SS G7
V
SS
G8
V
SS
G9
V
SS G10
V
SS G11
V
SS
G12
V
SS
G13
V
DDQL
H5
V
SS
H7
V
SS H8
V
SS H9
V
SS H10
V
SS
H11
V
SS H12
V
SS H13
V
DDQL
J5
ZZ
RJ6
V
SS J7
V
SS J8
V
SS J9
V
SS J10
V
SS J11
V
SS J12
ZZ
L
J13
V
DDQR
K5
V
SS
K6
V
SS K7
V
SS
K8
V
SS
L5
V
DD L6
NC
L7
NC
L8
V
SS
M5
V
DD
M6
V
DD
M7
NC
M8
V
SS
N5
V
DDQR N6
V
DDQR N7
V
DDQL
N8
V
DDQL
K9
V
SS
K10
V
SS K11
V
SS
K12
V
SS
L9
V
SS L10
V
SS
L11
V
SS L12
V
DD
M9
V
SS
M10
V
SS
M11
V
DD
M12
V
DD
N9
V
DDQR N10
V
DDQR N11
V
DDQL
N12
V
DDQL
K13
V
DDQR
L13
V
DDQL
M13
V
DDQL
N13
V
DD
F7
NC
F11
V
SS
5652 drw 02d
,
F3
I/O
11R
0
1
/
1
3
/
0
3
H6
V
SS
6.42
IDT70T3339/19/99S
High-Speed 2.5V 512/256/128K x 18 Dual-Port Static RAM Industrial and Commercial Temperature Ranges
4
Pin Configuration(con't)(3,4,5,6,9,10)
NOTES:
3. All VDD pins must be connected to 2.5V power supply.
4. All VDDQ pins must be connected to appropriate power supply: 3.3V if OPT pin for that port is set to VDD (2.5V), and 2.5V if OPT pin for that port is set to V SS (0V).
5. All VSS pins must be connected to ground supply.
6. Package body is approximately 20mm x 20mm x 1.4mm.
7. This package code is used to reference the package diagram.
8. This text does not indicate orientation of the actual part-marking.
9. Due to limited pin count, JTAG, Collison Detection and Interrupt are not supported in the DD-144 package.
10. Pins 109 and 72 will be VREFL and VREFR respectively for future HSTL device.
1. Pin is a NC for IDT70T3319 and IDT70T3399.
2. Pin is a NC for IDT70T3399.
V
SS
V
DDQR
V
SS
I/O
9L
I/O
9R
I/O
10L
I/O
10R
I/O
11L
I/O
11R
V
DDQL
V
SS
I/O
12L
I/O
12R
V
DDQR
ZZ
R
V
DD
V
DD
V
SS
V
SS
V
DDQL
V
SS
I/O
13R
I/O
13L
I/O
14R
I/O
14L
V
DDQR
V
SS
I/O
15R
I/O
15L
I/O
16R
I/O
16L
I/O
17R
I/O
17L
V
SS
V
DDQL
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
PL/FT
R
NC
NC
A
18R
(1)
A
17R
(2)
A
16R
A
15R
A
14R
A
13R
A
12R
A
11R
A
10R
A
9R
A
8R
A
7R
UB
R
LB
R
CE
1R
CE
0R
V
DD
V
SS
CLK
R
OE
R
R/W
R
ADS
R
CNTEN
R
REPEAT
R
A
6R
A
5R
A
4R
A
3R
A
2R
A
1R
A
0R
V
DD
NC
OPT
L
V
DDQR
V
SS
I/O
8L
I/O
8R
I/O
7L
I/O
7R
I/O
6L
I/O
6R
V
SS
V
DDQL
I/O
5L
I/O
5R
V
SS
V
DDQR
V
DD
V
DD
V
SS
V
SS
ZZ
L
V
DDQL
I/O
4R
I/O
4L
I/O
3R
I/O
3L
V
SS
V
DDQR
I/O
2R
I/O
2L
I/O
1R
I/O
1L
I/O
0R
I/O
0L
V
SS
V
DDQL
OPT
R
PL/FT
L
NC
NC
A
18L
(1)
A
17L
(2)
A
16L
A
15L
A
14L
A
13L
A
12L
A
11L
A
10L
A
9L
A
8L
A
7L
UB
L
LB
L
CE
1L
CE
0L
V
DD
V
SS
CLK
L
OE
L
R/W
L
ADS
L
CNTEN
L
REPEAT
L
A
6L
A
5L
A
4L
A
3L
A
2L
A
1L
A
0L
V
DD
NC
70T3339/19/99DD
DD-144
(7)
144-Pin TQFP
Top View
(8)
5652 drw 02a
,
01/07/03
6.42
IDT70T3339/19/99S
High-Speed 2.5V 512/256/128K x 18 Dual-Port Static RAM Industrial and Commercial Temperature Ranges
5
Pin Configurations(con't)(3,4,5,6,9)
1716
15
1412 13
10
9876543
21 11
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
I/O
9L
INT
L
V
SS
TDO
A
2L
A
4L
CLK
L
A
8L
A
12L
A
16L
NC
OPT
L
NC V
SS
COL
L
TDI A
1L
A
5L
A
9L
A
13L
A
17L(2)
V
DDQL
I/O
9R
V
DDQR
PIPE/
FT
L
A
3L
A
6L
NC
A
10L
A
14L
A
18L(1)
NC
NC V
SS
I/O
10L
NC
NC
I/O
11L
NC V
DDQR
I/O
10R
NC
I/O
11R
NC V
SS
V
DD
NC I/O
12L
V
DD
V
SS
NC
V
SS
I/O
12R
REPEAT
R
NC I/O
14L
V
DDQR
V
DDQL
I/O
15R
NC V
SS
NCNC
A
15L
A
11L
A
7L
A
0L
NC
I/O
7L
NC
I/O
6L
I/O
8R
UB
L
NC
I/O
8L
V
DDQL
CE
0L
CE
1L
LB
L
REPEAT
L
OE
L
I/O
0L
I/O
2L
I/O
1R
ADS
R
R/W
R
NC
I/O
16R
I/O
15L
TRST
A
13R
A
12R
NC V
DD
CLK
R
I/O
0R
NC
NC
NC
NC A
17R(2)
TCK
TMS
A
5R
A
9R
CE
0R
CE
1R
V
DD
V
SS
NC
NC
NC
A
16R
NC
A
18R(1)
A
14R
A
10R
UB
R
V
SS
V
DDQL
I/O
1L
I/O
2R
NC
INT
R
NC A
15R
A
11R
A
7R
LB
R
OE
R
V
SS
NC
V
DDQL
OPT
R
NC
70T3339/19/99BF
BF-208
(7)
208-Pin fpBGA
Top View
(8)
5652 drw 02c
I/O
14R
V
DDQL
V
SS
V
DDQR
NC
COL
R
NC
NC I/O
7R
NC
R/W
L
NC
ADS
L
V
DDQL
I/O
13R
CNTEN
L
ZZ
R
I/O
13L
V
SS
I/O
16L
V
DDQR
V
SS
I/O
17R
I/O
17L
V
DDQL
V
SS
PIPE/
FT
R
A
8R
CNTEN
R
A
6R
A
3R
A
1R
A
2R
A
0R
I/O
3L
I/O
4L
A
4R
V
DD
V
SS
V
SS
V
DDQR
V
DDQL
V
SS
V
DDQR
V
SS
I/O
3R
I/O
4R
V
SS
V
DDQR
V
SS
V
DD
V
DD
V
SS
I/O
5R
I/O
5L
V
DDQR
I/O
6R
V
SS
V
SS
V
DDQL
V
DD
V
SS
V
DDQR
V
SS
V
DD
V
DD
V
SS
V
DD
V
SS
NC
ZZ
L
NC
V
SS
01/13/03
NOTES:
3. All VDD pins must be connected to 2.5V power supply.
4. All VDDQ pins must be connected to appropriate power supply: 3.3V if OPT pin for that port is set to VDD (2.5V), and 2.5V if OPT pin for that port is
set to VSS (0V).
5. All VSS pins must be connected to ground supply.
6. Package body is approximately 15mm x 15mm x 1.4mm with 0.8mm ball pitch.
7. This package code is used to reference the package diagram.
8. This text does not indicate orientation of the actual part-marking.
9. Pins B14 and R14 will be VREFL and VREFR respectively for future HSTL device.
1. Pin is a NC for IDT70T3319 and IDT70T3399.
2. Pin is a NC for IDT70T3399.
6.42
IDT70T3339/19/99S
High-Speed 2.5V 512/256/128K x 18 Dual-Port Static RAM Industrial and Commercial Temperature Ranges
6
Pin Names
NOTES:
1. VDD, OPTX, and VDDQX must be set to appropriate operating levels prior to
applying inputs on the I/Os and controls for that port.
2. OPTX selects the operating voltage levels for the I/Os and controls on that port.
If OPTX is set to VDD (2.5V), then that port's I/Os and controls will operate at 3.3V
levels and VDDQX must be supplied at 3.3V. If OPT X is set to VSS (0V), then that
port's I/Os and address controls will operate at 2.5V levels and VDDQX must be
supplied at 2.5V. The OPT pins are independent of one another—both ports can
operate at 3.3V levels, both can operate at 2.5V levels, or either can operate
at 3.3V with the other at 2.5V.
3. When REPEATX is asserted, the counter will reset to the last valid address loaded
via ADSX.
4. The sleep mode pin shuts off all dynamic inputs, except JTAG inputs, when
asserted. All static inputs, i.e., PL/FTx and OPTx and the sleep mode pins
themselves (ZZx) are not affected during sleep mode. It is recommended that
boundry scan not be operated during sleep mode.
5. Due to limited pin count, JTAG, Collision Detection and Interrupt are not supported
in the DD-144 package.
6. Address A18x is a NC for the IDT70T3319. Also, Addresses A18x and A17x are
NC's for the IDT70T3399.
7 . Chip Enables and Byte Enables are double buffered when PL/FT = VIH, i.e., the
signals take two cycles to deselect.
Left Port Right P ort Names
CE
0L
,
CE
1L
CE
0R
,
CE
1R
Chip E nab l e s (Inp ut)
(7)
R/W
L
R/W
R
Re ad / Write E nab le (Inp ut)
OE
L
OE
R
Outp ut Enab l e (Inp ut)
A
0L
- A
18L
(6)
A
0R
- A
18R
(6)
Address (Input)
I/O
0L
- I/O
17L
I/O
0R
- I/O
17R
Data Input/ O utput
CLK
L
CLK
R
Clo c k (Inp ut)
PL/FT
L
PL/FT
R
Pipeline/Flow-Through (Input)
ADS
L
ADS
R
Address Strobe Enable (Input)
CNTEN
L
CNTEN
R
Co unte r Enab l e (Input)
REPEAT
L
REPEAT
R
Counter Repeat
(3)
UB
L
UB
R
Upper Byte Enable (I/O
9
- I/O
17
)
(7)
LB
L
LB
R
Lo we r B y te E nab le (I/ O
0
- I/O
8
)
(7)
V
DDQL
V
DDQR
P o we r (I/O B us ) (3.3V o r 2. 5V)
(1)
(Input
)
OPT
L
OPT
R
Opti o n fo r s el e ctin g V
DDQX
(1,2)
(Input)
ZZ
L
ZZ
R
Sleep Mode pin
(4)
(Input)
V
DD
P o we r (2. 5V)
(1)
(Input)
V
SS
Gro und (0V ) (Inp ut)
TDI
(5)
Tes t Data In p u t
TDO
(5)
Tes t Data O utput
TCK
(5)
Te s t Lo g i c Cl o c k (10MHz ) (Inp ut)
TMS
(5)
Test Mode Select (Input)
TRST
(5)
Re s e t (Initiali z e TA P Co ntro l le r) (Input)
INT
L
(5)
INT
R
(5)
Interru p t F l ag ( Ou tp u t)
COL
L
(5)
COL
R
(5)
Collisio n Ale rt (Outp ut)
5652 tbl 01
6.42
IDT70T3339/19/99S
High-Speed 2.5V 512/256/128K x 18 Dual-Port Static RAM Industrial and Commercial Temperature Ranges
7
NOTES:
1 . "H" = VIH, "L" = VIL, "X" = Don't Care.
2. ADS, CNTEN, REPEAT = X.
3. OE and ZZ are asynchronous input signals.
4. It is possible to read or write any combination of bytes during a given access. A few representative samples have been illustrated here.
Truth Table I—Read/Write and Enable Control (1,2,3,4)
Truth Table II—Address Counter Control (1,2)
NOTES:
1 . "H" = VIH, "L" = VIL, "X" = Don't Care.
2. Read and write operations are controlled by the appropriate setting of R/W, CE0, CE1, UB, LB and OE.
3. Outputs configured in flow-through output mode: if outputs are in pipelined mode the data out will be delayed by one cycle.
4. ADS and REPEAT are independent of all other memory control signals including CE0, CE1, UB and LB.
5. The address counter advances if CNTEN = VIL on the rising edge of CLK, regardless of all other memory control signals including CE0, CE1, UB and LB.
6. When REPEAT is asserted, the counter will reset to the last valid address loaded via ADS. This value is not set at power-up: a known location should be loaded
via ADS during initialization if desired. Any subsequent ADS access during operations will update the REPEAT address location.
OE CLK CE
0
CE
1
UB LB R/WZZ Up pe r By te
I/O
9-17
Lower Byte
I/O
0-8
MODE
X↑H X X X X L High-Z High-Z Deselected–Power Down
X↑X L X X X L High-Z High-Z Deselected–Power Down
X↑L H H H X L Hig h-Z Hig h-Z B oth By te s De s elec te d
X↑LHHLLL High-Z D
IN
Wri te to L o we r B y te Only
X↑LHLHLL D
IN
High-Z Write to Upper Byte Only
X↑LHLLLL D
IN
D
IN
Wri te to B o th Byte s
L↑LHHLHL High-Z D
OUT
Re ad Lowe r By te Only
L↑LHLHHL D
OUT
High-Z Read Upper Byte Only
L↑LHLLHL D
OUT
D
OUT
Re ad B o th B y te s
H↑L H L L X L High-Z High-Z Outputs Disab led
X X X X X X X H High-Z High-Z Sleep Mode
5652 tbl 02
Address
Previous
Internal
Address
Internal
Address
Used CLK ADS CNTEN REPEAT
(6)
I/O
(3)
MODE
An X An ↑ L
(4)
XHD
I/O
(n) External Ad dress Used
XAnAn + 1
↑H L
(5)
HD
I/O
(n+1) Counter Enabled—Internal Address generation
X A n + 1 A n + 1 ↑HH HD
I/O
(n+1) External Address Blo cked—Co unter disab led (An + 1 reus ed)
XXAn
↑XX L
(4)
D
I/O
(n) Co unter Se t to last v alid ADS load
5652 tb l 03
6.42
IDT70T3339/19/99S
High-Speed 2.5V 512/256/128K x 18 Dual-Port Static RAM Industrial and Commercial Temperature Ranges
8
Recommended DC Operating
Conditions with VDDQ at 3.3V
Symbol Parameter Min. Typ. Max. Unit
V
DD
Co re S up p ly Vo ltag e 2. 4 2. 5 2. 6 V
V
DDQ
I/O Supply Vo ltage
(3)
3.15 3.3 3.45 V
V
SS
Ground 0 0 0 V
V
IH
Inp ut Hig h Vo l tag e
(Ad dress , Control
& D at a I/ O In puts)
(3)
2.0
____
V
DDQ
+ 150mV
(2)
V
V
IH
Inp ut Hig h Vo l tag e
_
JTAG 1.7
____
V
DD
+ 100m V
(2)
V
V
IH
Input High Voltage -
ZZ, OPT, PIPE/FT V
DD
- 0.2V
____
V
DD
+ 100m V
(2)
V
V
IL
Inp ut Lo w Vol tag e -0. 3
(1)
____
0.8 V
V
IL
Inp ut Lo w Vol tag e -
ZZ, OPT, PIPE/FT -0.3
(1)
____
0.2 V
5652 tb l 05b
NOTES:
1. VIL (min.) = -1.0V for pulse width less than tCYC/2, or 5ns, whichever is less.
2. VIH (max.) = VDDQ + 1.0V for pulse width less than tCYC/2 or 5ns, whichever is less.
3 . To select operation at 3.3V levels on the I/Os and controls of a given port, the OPT
pin for that port must be set to VDD (2.5V), and VDDQX for that port must be supplied
as indicated above.
Recommended DC Operating
Conditions with VDDQ at 2.5V
Symbol Parameter Min. Typ. Max. Unit
V
DD
Co re Sup p ly Vo ltag e 2. 4 2.5 2. 6 V
V
DDQ
I/O Supply Voltage
(3)
2.4 2.5 2.6 V
V
SS
Ground 0 0 0 V
V
IH
Input High Volltag e
(Address, Control &
Data I/O Inp u ts )
(3)
1.7
____
V
DDQ
+ 100m V
(2)
V
V
IH
Input High Voltage
_
JTAG 1.7
____
V
DD
+ 100m V
(2)
V
V
IH
Input High Voltage -
ZZ, OPT, PIPE/FT V
DD
- 0.2V
____
V
DD
+ 100m V
(2)
V
V
IL
Input Lo w Vo ltag e -0.3
(1)
____
0.7 V
V
IL
Input Low Voltage -
ZZ, OPT, PIPE/FT -0.3
(1)
____
0.2 V
5652 tbl 05a
NOTES:
1. VIL (min.) = -1.0V for pulse width less than tCYC/2 or 5ns, whichever is less.
2. VIH (max.) = VDDQ + 1.0V for pulse width less than tCYC/2 or 5ns, whichever is less.
3. To select operation at 2.5V levels on the I/Os and controls of a given port, the OPT
pin for that port must be set to Vss(0V), and VDDQX for that port must be supplied as
indicated above.
Maximum Operating
Temperature and Supply Voltage(1)
Grade Ambient
Temperature GND V
DD
Commercial 0
O
C to + 70
O
C0V2.5V
+
100m V
Industrial -40
O
C to + 85
O
C0V2.5V
+
100m V
5652 tb l 0 4
NOTES:
1. This is the parameter TA. This is the "instant on" case temperature.
6.42
IDT70T3339/19/99S
High-Speed 2.5V 512/256/128K x 18 Dual-Port Static RAM Industrial and Commercial Temperature Ranges
9
Absolute Maximum Ratings(1)
Symbol Rating Commercial
& I ndu strial Unit
V
TERM
(V
DD
)V
DD
Te rm inal Vo ltage
wi th R e s p e c t to G ND -0.5 to 3.6 V
V
TERM
(2)
(V
DDQ
)V
DDQ
Te rm inal Vo ltag e
wi th R e s p e c t to G ND -0.3 to V
DDQ
+ 0.3 V
VTERM
(2)
(INP UTS an d I/ O's ) In p ut an d I/ O Te r mi n al
Vo l tag e wi th Re s pe c t to GN D -0.3 to V
DDQ
+ 0.3 V
T
BIAS
(3)
Te m p e rature Unde r B ias -55 to + 125
o
C
T
STG
S tora g e Te mp e rature -65 to + 150
o
C
T
JN
J unc tio n Te m p e rature + 150
o
C
I
OUT
(F or V DDQ = 3. 3V) DC Outp ut Current 50 mA
I
OUT
(F or V DDQ = 2. 5V) DC Outp ut Current 40 mA
5652 tb l 06
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation of the
device at these or any other conditions above those indicated in the operational sections
of this specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect reliability.
2. This is a steady-state DC parameter that applies after the power supply has reached its
nominal operating value. Power sequencing is not necessary; however, the voltage on
any Input or I/O pin cannot exceed VDDQ during power supply ramp up.
3. Ambient Temperature under DC Bias. No AC Conditions. Chip Deselected.
DC Electrical Characteristics Over the Operating
T emperature and Supply Voltage Range (VDD = 2.5V ± 100mV)
Symbol Parameter Test Conditions
70T3339/19/99S
UnitMin. Max.
|I
LI
| Inp ut Le ak ag e Curre nt
(1)
V
DDQ
= Max., V
IN
= 0V to V
DDQ
___
10 µA
|I
LI
| J TA G & ZZ Inp ut Le ak ag e Curre nt
(1,2)
V
DD =
Max.
,
V
IN
= 0V to V
DD
___
±30 µA
|I
LO
| Outp ut Le akag e Curre nt
(1,3)
CE
0
= V
IH
or CE
1
= V
IL
, V
OUT
= 0V to V
DDQ
___
10 µA
V
OL
(3. 3V ) Outp ut Lo w Vo ltag e
(1)
I
OL
= +4mA, V
DDQ
= Min.
___
0.4 V
V
OH
(3. 3V) Outp ut Hig h Vo ltag e
(1)
I
OH
= -4mA, V
DDQ
= Mi n. 2. 4
___
V
V
OL
(2. 5V ) Outp ut Lo w Vo ltag e
(1)
I
OL
= +2mA, V
DDQ
= Min.
___
0.4 V
V
OH
(2. 5V) Outp ut Hig h Vo ltag e
(1)
I
OH
= -2mA, V
DDQ
= Mi n. 2. 0
___
V
5652 t b l 08
NOTES:
1. VDDQ is selectable (3.3V/2.5V) via OPT pins. Refer to p.6 for details.
2. Applicable only for TMS, TDI and TRST inputs.
3. Outputs tested in tri-state mode.
Capacitance(1)
(TA = +25°C, f = 1.0MHz) PQFP ONLY
Symbol Parameter Conditions(2) Max. Unit
C
IN
In p ut C ap a ci tanc e V
IN
= 3dV 8 pF
C
OUT
(3) Output Capacitance V
OUT
= 3dV 10.5 p F
5652 tbl 07
NOTES:
1. These parameters are determined by device characterization, but are not
production tested.
2. 3dV references the interpolated capacitance when the input and output switch
from 0V to 3V or from 3V to 0V.
3. COUT also references CI/O.
6.42
IDT70T3339/19/99S
High-Speed 2.5V 512/256/128K x 18 Dual-Port Static RAM Industrial and Commercial Temperature Ranges
10
DC Electrical Characteristics Over the Operating
T emperature and Supply Voltage Range (3)(VDD = 2.5V ± 100mV)
70T3339/19/99
S200
Com'l Only
(8)
70T3339/19/99
S166
Com'l
& Ind
(7)
70T3339/19/99
S133
Com'l
& I nd
Symbol P arameter Test Conditi on Version Typ.
(4)
Max. Typ.
(4)
Max. Typ.
(4)
Max. Unit
I
DD
Dynamic Ope rating
Current (B o th
Ports Active)
CE
L
and CE
R
= V
IL
,
Outp uts Disab led ,
f = f
MAX
(1)
COM'L S 375 525 320 450 260 370 mA
IND S
___ ___
320 510 260 450
I
SB1
(6)
S tand b y Curre nt
(Bo th Ports - TTL
Le v e l Inp uts )
CE
L
= CE
R
= V
IH
f = f
MAX
(1)
COM'L S 205 270 175 230 140 190 mA
IND S
___ ___
175 275 140 235
I
SB2
(6)
S tand b y Curre nt
(One P o rt - TTL
Le v e l Inp uts )
CE
"A"
= V
IL
and CE
"B"
= V
IH
(5)
A c ti v e P o r t Outputs D i sa b l e d,
f=f
MAX
(1)
COM'L S 300 375 250 325 200 250 mA
IND S
___ ___
250 365 200 310
I
SB3
Full Standby Current
(Bo th Ports - CMOS
Le v e l Inp uts )
Both Ports CE
L
and
CE
R
> V
DDQ
- 0.2V, V
IN
> V
DDQ
- 0. 2V
or V
IN
< 0.2V, f = 0
(2)
COM'L S 515 5 15 5 15 mA
IND S
___ ___
520520
I
SB4
(6)
Full Standby Current
(One P o rt - CM OS
Le v e l Inp uts )
CE
"A"
< 0.2V and CE
"B"
> V
DDQ
- 0. 2V
(5)
V
IN
> V
DDQ
- 0.2V or V
IN
< 0.2V
A c ti v e P o r t, Outputs D i sa b l e d, f = f
MAX
(1)
COM'L S 300 375 250 325 200 250 mA
IND S
___ ___
250 365 200 310
Izz Sleep Mode Current
(Bo th Ports - TTL
Le v e l Inp uts )
ZZ
L =
ZZ
R =
V
IH
f=f
MAX
(1)
COM'L S 515 5 15 5 15 mA
IND S
___ ___
520520
5652 tb l 09
NOTES:
1. At f = fMAX, address and control lines (except Output Enable) are cycling at the maximum frequency clock cycle of 1/tCYC, using "AC TEST CONDITIONS".
2. f = 0 means no address, clock, or control lines change. Applies only to input at CMOS level standby.
3. Port "A" may be either left or right port. Port "B" is the opposite from port "A".
4. VDD = 2.5V, TA = 25°C for Typ, and are not production tested. IDD DC(f=0) = 15mA (Typ).
5. CEX = VIL means CE0X = VIL and CE1X = VIH
CEX = VIH means CE0X = VIH or CE1X = VIL
CEX < 0.2V means CE0X < 0.2V and CE1X > VDDQ - 0.2V
CEX > VDDQ - 0.2V means CE0X > V DDQ - 0.2V or CE1X - 0.2V
"X" represents "L" for left port or "R" for right port.
6. ISB1, ISB2 and ISB4 will all reach full standby levels (ISB3) on the appropriate port(s) if ZZL and/or ZZR = VIH.
7. 166MHz I-Temp is not available in the BF-208 package.
8. 200Mhz is not available in the BF-208 and DD-144 packages.
6.42
IDT70T3339/19/99S
High-Speed 2.5V 512/256/128K x 18 Dual-Port Static RAM Industrial and Commercial Temperature Ranges
11
Inp ut P uls e Le v e l s (A d d re s s & Con trols )
In p u t P u l s e L ev els ( I/O s )
In p ut R ise / F all Ti me s
Inp ut Ti ming Refe re nce Le ve ls
Outp ut Refe re nce Lev els
Outp ut Lo ad
GND to 3
.
0V / GND to 2. 4V
GND to 3. 0 V/ GND to 2. 4V
2ns
1.5V/1.25V
1.5V/1.25V
Fig ures 1 and 2
5652 tb l 10
AC T est Conditions (VDDQ - 3.3V/2.5V)
Figure 1. AC Output Test load.
1.5V/1.25
50Ω
50
Ω
5652 drw 03
10pF
(Tester)
D
ATA
OUT
,
∆
Capacitance (pF) from AC Test Load
5652 drw 04
∆
tCD
(
Typical, ns)
6.42
IDT70T3339/19/99S
High-Speed 2.5V 512/256/128K x 18 Dual-Port Static RAM Industrial and Commercial Temperature Ranges
12
AC Electrical Characteristics Over the Operating Temperature Range
(Read and Write Cycle Timing) (2,3) (VDD = 2.5V ± 100mV, TA = 0°C to +70°C)
NOTES:
1. The Pipelined output parameters (tCYC2, tCD2) apply to either or both left and right ports when FT/PIPEX = VDD (2.5V). Flow-through parameters (tCYC1, tCD1)
apply when FT/PIPE = Vss (0V) for that port.
2. All input signals are synchronous with respect to the clock except for the asynchronous Output Enable (OE), FT/PIPE and OPT. FT/PIPE and OPT should be
treated as DC signals, i.e. steady state during operation.
3. These values are valid for either level of VDDQ (3.3V/2.5V). See page 6 for details on selecting the desired operating voltage levels for each port.
4. 166MHz I-Temp is not available in the BF-208 package.
5. 200Mhz is not available in the BF-208 and DD-144 packages.
6. Guaranteed by design (not production tested).
70T3339/19/99
S200
Com'l Only
(5)
70T3339/19/99
S166
Com'l
& I n d
(4)
70T3339/19/99
S133
Com'l
& I n d
Symbol Parameter Min.Max.Min.Max.Min.Max.Unit
t
CYC1
Clock Cycle Time (Flow-Through)
(1)
15
____
20
____
25
____
ns
t
CYC2
Clock Cycle Time (Pipelined)
(1)
5
____
6
____
7.5
____
ns
t
CH1
Clock High Time (Flow-Through)
(1)
6
____
8
____
10
____
ns
t
CL1
Clo ck Lo w Ti me (F lo w-Throug h)
(1)
6
____
8
____
10
____
ns
t
CH2
Clock High Time (Pipelined)
(2)
2
____
2.4
____
3
____
ns
t
CL2
Clock Low Time (Pipelined)
(1)
2
____
2.4
____
3
____
ns
t
SA
Address Setup Time 1.5
____
1.7
____
1.8
____
ns
t
HA
Address Ho ld Time 0.5
____
0.5
____
0.5
____
ns
t
SC
Chip Enable Setup Time 1.5
____
1.7
____
1.8
____
ns
t
HC
Chip Enable Ho ld Time 0.5
____
0.5
____
0.5
____
ns
t
SB
By te Enab le Se tup Time 1.5
____
1.7
____
1.8
____
ns
t
HB
By te Enable Ho ld Time 0.5
____
0.5
____
0.5
____
ns
t
SW
R/W Setup Time 1.5
____
1.7
____
1.8
____
ns
t
HW
R/W Hold Time 0.5
____
0.5
____
0.5
____
ns
t
SD
Inp ut D ata S e tup Ti me 1. 5
____
1.7
____
1.8
____
ns
t
HD
Inp ut D ata Hold Tim e 0. 5
____
0.5
____
0.5
____
ns
t
SAD
ADS Setup Time 1.5
____
1.7
____
1.8
____
ns
t
HAD
ADS Hol d Ti me 0.5
____
0.5
____
0.5
____
ns
t
SCN
CNTEN Setup Time 1.5
____
1.7
____
1.8
____
ns
t
HCN
CNTEN Ho ld Time 0.5
____
0.5
____
0.5
____
ns
t
SRPT
REPEAT Se tup Ti me 1.5
____
1.7
____
1.8
____
ns
t
HRPT
REPEAT Hold Tim e 0.5
____
0.5
____
0.5
____
ns
t
OE
Ou tp ut E nable to D ata Val id
____
4.4
____
4.4
____
4.6 ns
t
OLZ
(6)
Ou tp ut E nable to O utput Lo w-Z 1
____
1
____
1
____
ns
t
OHZ
(6)
Ou tp ut E nable to O utput High-Z 1 3. 4 1 3. 6 1 4 . 2 ns
t
CD1
Clo ck to Data Valid (Fl ow-Thro ug h)
(1)
____
10
____
12
____
15 ns
t
CD2
Clock to Data Valid (Pipelined)
(1)
____
3.4
____
3.6
____
4.2 ns
t
DC
Data Outp ut H o l d A fte r Clo ck High 1
____
1
____
1
____
ns
t
CKHZ
(6)
Clock High to Output High-Z 1 3.4 1 3.6 1 4.2 ns
t
CKLZ
(6)
Clock High to Output Low-Z 1
____
1
____
1
____
ns
t
INS
Inte rr up t F la g S e t Tim e
____
7
____
7
____
7ns
t
INR
Inte rr up t F la g Re s e t Ti me
____
7
____
7
____
7ns
t
COLS
Collision Flag S et Time
____
3.4
____
3.6
____
4.2 ns
t
COLR
Col lis io n Flag Res e t Tim e
____
3.4
____
3.6
____
4.2 ns
t
ZZSC
Sleep Mode Set Cycles 2
____
2
____
2
____
cycles
t
ZZRC
Sleep Mode Recovery Cycles 3
____
3
____
3
____
cycles
Port-to-Port Delay
t
CO
Cloc k -to -Cl o c k O ffs e t 4
____
5
____
6
____
ns
t
OFS
Clo ck-to-Clock Offset for Collision De tection Please refe r to Collision Detection Timing Table on Page 21
5652 tb l 11
6.42
IDT70T3339/19/99S
High-Speed 2.5V 512/256/128K x 18 Dual-Port Static RAM Industrial and Commercial Temperature Ranges
13
Timing W av eform of Read Cy c le for Pipelined Operation
(FT/PIPE'X' = VIH)(2)
Timing Wav eform of Read Cyc le for Flow-through Output
(FT/PIPE"X" = VIL)(2,6)
NOTES:
1. OE is asynchronously controlled; all other inputs depicted in the above waveforms are synchronous to the rising clock edge.
2. ADS = VIL, CNTEN and REPEAT = VIH.
3. The output is disabled (High-Impedance state) by CE0 = VIH, CE1 = VIL, UB, LB = VIH following the next rising edge of the clock. Refer to
Truth Table 1.
4. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers
are for reference use only.
5. If UB, LB was HIGH, then the appropriate Byte of DATAOUT for Qn + 2 would be disabled (High-Impedance state).
6. "x" denotes Left or Right port. The diagram is with respect to that port.
An An + 1 An + 2 An + 3
t
CYC2
t
CH2
t
CL2
R/
W
ADDRESS
CE
0
CLK
CE
1
UB,LB
(3)
DATA
OUT
OE
t
CD2
t
CKLZ
Qn Qn + 1 Qn + 2
t
OHZ
t
OLZ
t
OE
5652 drw 05
(1)
(1)
t
SC
t
HC
t
SB
t
HB
t
SW
t
HW
t
SA
t
HA
t
DC
t
SC
t
HC
t
SB
t
HB
(4)
(1 Latency)
(5)
(5)
,
An An + 1 An + 2 An + 3
tCYC1
tCH1 tCL1
R/
W
ADDRESS
DATAOUT
CE
0
CLK
OE
tSC tHC
tCD1
tCKLZ
Qn Qn + 1 Qn + 2
tOHZ tOLZ
tOE
tCKHZ
5652 drw 06
(5)
(1)
CE1
UB,LB
(3)
tSB tHB
tSW tHW
tSA tHA
tDC
tDC
(4)
tSC tHC
tSB tHB
,
6.42
IDT70T3339/19/99S
High-Speed 2.5V 512/256/128K x 18 Dual-Port Static RAM Industrial and Commercial Temperature Ranges
14
Timing Waveform of a Multi-Device Pipelined Read(1,2)
NOTES:
1. B1 Represents Device #1; B2 Represents Device #2. Each Device consists of one IDT70T3339/19/99 for this waveform,
and are setup for depth expansion in this example. ADDRESS(B1) = ADDRESS(B2) in this situation.
2. UB, LB, OE, and ADS = VIL; CE1(B1), CE1(B2), R/W, CNTEN, and REPEAT = VIH.
Timing Waveform of a Multi-Device Flow-Through Read(1,2)
,
t
SC
t
HC
CE
0(B1)
A
DDRESS
(B1)
A
0
A
1
A
2
A
3
A
4
A
5
t
SA
t
HA
CLK
Q
0
Q
1
Q
3
DATA
OUT(B1)
t
CH2
t
CL2
t
CYC2
A
DDRESS
(B2)
A
0
A
1
A
2
A
3
A
4
A
5
t
SA
t
HA
CE
0(B2)
DATA
OUT(B2)
Q
2
Q
4
t
CD2
t
CD2
t
CKHZ
t
CD2
t
CKLZ
t
DC
t
CKHZ
t
CD2
t
CKLZ
t
SC
t
HC
t
CKHZ
t
CKLZ
t
CD2
A
6
A
6
t
DC
t
SC
t
HC
t
SC
t
HC
5652 drw 07
t
SC
t
HC
CE
0(B1)
ADDRESS
(B1)
A
0
A
1
A
2
A
3
A
4
A
5
t
SA
t
H
A
CLK
5652 drw 08
D
0
D
3
t
CD1
t
CKLZ
t
CKHZ
(1) (1)
D
1
DATA
OUT(B1)
t
CH1
t
CL1
t
CYC1
(1)
ADDRESS
(B2)
A
0
A
1
A
2
A
3
A
4
A
5
t
SA
t
HA
CE
0(B2)
DATA
OUT(B2)
D
2
D
4
t
CD1
t
CD1
t
CKHZ
t
DC
t
CD1
t
CKLZ
t
SC
t
HC
(1)
t
CKHZ
(1)
t
CKLZ
(1)
t
CD1
A
6
A
6
t
DC
t
SC
t
HC
t
SC
t
HC
D
5
t
CD1
t
CKLZ
(1)
t
CKHZ
(1)
,
6.42
IDT70T3339/19/99S
High-Speed 2.5V 512/256/128K x 18 Dual-Port Static RAM Industrial and Commercial Temperature Ranges
15
Timing Wa vef orm of Left Port Write to Pipelined Right P ort R ead(1,2,4)
Timing Waveform with Port-to-Port Flow-Through Read(1,2,4)
NOTES:
1. CE0, UB, LB, and ADS = VIL; CE1, CNTEN, and REPEAT = VIH.
2. OE = VIL for the Right Port, which is being read from. OE = VIH for the Left Port, which is being written to.
3. If tCO < minimum specified, then data from Port "B" read is not valid until following Port "B" clock cycle (i.e., time from write to valid read on opposite port will be
tCO + tCYC + tCD1). If tCO > minimum, then data from Port "B" read is available on first Port "B" clock cycle (i.e., time from write to valid read on opposite port will
be tCO + tCD1).
4. All timing is the same for both left and right ports. Port "A" may be either left or right port. Port "B" is the opposite of Port "A".
CLK
"A"
R/W
"A
"
ADDRESS
"A"
DATA
IN"A"
CLK
"B"
R/W
"B"
ADDRESS
"B"
DATA
OUT"B"
t
SW
t
HW
t
SA
t
HA
t
SD
t
HD
t
SW
t
HW
t
SA
t
HA
t
CO
(3)
t
CD2
NO
MATCH
VALID
NO
MATC
H
MATC
H
MATC
H
VALID
5652 drw 09
t
DC
,
DATA
IN "A"
CLK
"B"
R/W
"B"
ADDRESS
"A"
R/W
"A"
CLK
"A"
ADDRESS
"B"
NO
MATCH
MATCH
NO
MATCH
MATCH
VALID
t
CD1
t
DC
DATA
OUT "B"
5652 drw 10
VALID
VALID
t
SW
t
HW
t
SA
t
HA
t
SD
t
HD
t
HW
t
CD1
t
CO
t
DC
t
SA
t
SW
t
HA
(3)
,
NOTES:
1. CE0, UB, LB, and ADS = VIL; CE1, CNTEN, and REPEAT = VIH.
2. OE = VIL for Port "B", which is being read from. OE = VIH for Port "A", which is being written to.
3. If tCO < minimum specified, then data from Port "B" read is not valid until following Port "B" clock cycle (ie, time from write to valid read on opposite port will be
tCO + 2 tCYC2 + tCD2). If tCO > minimum, then data from Port "B" read is available on first Port "B" clock cycle (ie, time from write to valid read on opposite port
will be tCO + tCYC2 + tCD2).
4. All timing is the same for Left and Right ports. Port "A" may be either Left or Right port. Port "B" is the opposite of Port "A"
6.42
IDT70T3339/19/99S
High-Speed 2.5V 512/256/128K x 18 Dual-Port Static RAM Industrial and Commercial Temperature Ranges
16
Timing Waveform of Pipelined Read-to-Write-to-Read
(OE = VIL)(2)
Timing Waveform of Pipelined Read-to-Write-to-Read (OE Controlled)(2)
NOTES:
1. Output state (High, Low, or High-impedance) is determined by the previous cycle control signals.
2. CE0, UB, LB, and ADS = VIL; CE1, CNTEN, and REPEAT = VIH.
3. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers are for reference
use only.
4. This timing does not meet requirements for fastest speed grade. This waveform indicates how logically it could be done if timing so allows.
R/
W
ADDRESS An An +1 An + 2 An + 2 An + 3 An + 4
DATA
IN
Dn + 2
CE
0
CLK
5652 drw 11
Qn Qn + 3
DATA
OUT
CE
1
UB,LB
t
CD2
t
CKHZ
t
CKLZ
t
CD2
t
SC
t
HC
t
SB
t
HB
t
SW
t
HW
t
SA
t
HA
t
CH2
t
CL2
t
CYC2
READ NOP READ
t
SD
t
HD
(3)
(1)
t
SW
t
HW
WRITE
(4)
,
R/
W
ADDRESS An An +1 An + 2 An + 3 An + 4 An + 5
DATA
IN
Dn + 3Dn + 2
CE
0
CLK
5652 drw 12
DATA
OUT
Qn Qn + 4
CE
1
UB,LB
OE
t
CH2
t
CL2
t
CYC2
t
CKLZ
t
CD2
t
OHZ
t
CD2
t
SD
t
HD
READ WRITE READ
t
SC
t
HC
t
SB
t
HB
t
SW
t
HW
t
SA
t
HA
(3)
(1)
t
SW
t
HW
(4)
,
NOTES:
1. Output state (High, Low, or High-impedance) is determined by the previous cycle control signals.
2. CE0, UB, LB, and ADS = VIL; CE1, CNTEN, and REPEAT = VIH. "NOP" is "No Operation".
3. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers
are for reference use only.
4. "NOP" is "No Operation." Data in memory at the selected address may be corrupted and should be re-written to guarantee data integrity.
6.42
IDT70T3339/19/99S
High-Speed 2.5V 512/256/128K x 18 Dual-Port Static RAM Industrial and Commercial Temperature Ranges
17
Timing Wav eform of Flow-Through Read-to-Write-to-R ead (OE = VIL)(2)
Timing Waveform of Flow-Through Read-to-Write-to-Read (OE Controlled)(2)
NOTES:
1. Output state (High, Low, or High-impedance) is determined by the previous cycle control signals.
2. CE0, UB, LB, and ADS = VIL; CE1, CNTEN, and REPEAT = VIH.
3. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers are for
reference use only.
4. "NOP" is "No Operation." Data in memory at the selected address may be corrupted and should be re-written to guarantee data integrity.
R/
W
ADDRESS An An +1 An + 2 An + 2 An + 3 An + 4
DATA
IN
Dn + 2
CE
0
CLK
5652 drw 13
Qn
DATA
OUT
CE
1
UB,LB
t
CD1
Qn + 1
t
CH1
t
CL1
t
CYC1
t
SD
t
HD
t
CD1
t
CD1
t
DC
t
CKHZ
Qn + 3
t
CD1
t
DC
t
SC
t
HC
t
SB
t
HB
t
SW
t
HW
t
SA
t
HA
READ NOP READ
t
CKLZ
(3)
(1)
t
SW
t
HW
WRITE
(4)
,
R/
W
ADDRESS An An +1 An + 2 An + 3 An + 4 An + 5
(3)
DATAIN Dn + 2
CE
0
CLK
5652 drw 14
Qn
DATAOUT
CE1
UB,LB
tCD1
tCH1 tCL1
t
CYC1
tSD tHD
tCD1 tDC
Qn + 4
tCD1
tDC
tSC tHC
tSB tHB
tSW tHW
tSA tHA
READ WRITE READ
tCKLZ
(1)
Dn + 3
tOHZ
tSW tHW
OE
tOE
,
6.42
IDT70T3339/19/99S
High-Speed 2.5V 512/256/128K x 18 Dual-Port Static RAM Industrial and Commercial Temperature Ranges
18
Timing Waveform of Pipelined Read with Address Counter Advance(1)
ADDRESS An
CLK
DATA
OUT
Qx - 1
(2)
Qx Qn Qn + 2
(2)
Qn + 3
ADS
CNTEN
t
CYC2
t
CH2
t
CL2
5652 drw 15
t
SA
t
HA
t
SAD
t
HAD
t
CD2
t
DC
READ
EXTERNAL
ADDRESS READ WITH COUNTER COUNTER
HOLD
t
SAD
t
HAD
t
SCN
t
HCN
READ
WITH
COUNTER
Qn + 1
,
NOTES:
1. CE0, OE, UB, LB = VIL; CE1, R/W, and REPEAT = VIH.
2. If there is no address change via ADS = VIL (loading a new address) or CNTEN = VIL (advancing the address), i.e. ADS = VIH and CNTEN = VIH, then
the data output remains constant for subsequent clocks.
Timing Waveform of Flow-Through Read with Address Counter Advance(1)
ADDRESS An
CLK
DATA
OUT
Qx
(2)
Qn Qn + 1 Qn + 2 Qn + 3
(2)
Qn + 4
ADS
CNTEN
t
CYC1
t
CH1
t
CL1
5652 drw 16
t
SA
t
HA
t
SAD
t
HAD
READ
EXTERNAL
ADDRESS
READ WITH COUNTER COUNTER
HOLD
t
CD1
t
DC
t
SAD
t
HAD
t
SCN
t
HCN
READ
WITH
COUNTER
,
6.42
IDT70T3339/19/99S
High-Speed 2.5V 512/256/128K x 18 Dual-Port Static RAM Industrial and Commercial Temperature Ranges
19
Timing Waveform of Write with Address Counter Advance
(Flow-through or Pipelined Inputs)(1)
Timing Waveform of Counter Repeat(2)
NOTES:
1. CE0, UB, LB, and R/W = VIL; CE1 and REPEAT = VIH.
2. CE0, UB, LB = VIL; CE1 = VIH.
3. The "Internal Address" is equal to the "External Address" when ADS = VIL and equals the counter output when ADS = VIH.
4. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers are for reference
use only.
5. Output state (High, Low, or High-impedance) is determined by the previous cycle control signals.
6. No dead cycle exists during REPEAT operation. A READ or WRITE cycle may be coincidental with the counter REPEAT cycle: Address loaded by last valid
ADS load will be accessed. Extra cycles are shown here simply for clarification. For more information on REPEAT function refer to Truth Table II.
7. CNTEN = VIL advances Internal Address from ‘An’ to ‘An +1’. The transition shown indicates the time required for the counter to advance. The ‘An +1’Address is
written to during this cycle.
ADDRESS An
CLK
DATA
IN
Dn Dn + 1 Dn + 1 Dn + 2
ADS
CNTEN
t
CH2
t
CL2
t
CYC2
5652 drw 17
INTERNAL
(3)
ADDRESS An
(7)
An + 1 An + 2 An + 3 An + 4
Dn + 3 Dn + 4
t
SA
t
HA
t
SAD
t
HAD
WRITE
COUNTER HOLD WRITE WITH COUNTER
WRITE
EXTERNAL
ADDRESS WRITE
WITH COUNTER
t
SD
t
HD
t
SCN
t
HC
N
,
ADDRESS An
D
0
t
CH2
t
CL2
t
CYC2
Q
LAST
Q
LAST+1
LAST ADS LOAD
CLK
DATA
IN
R/
W
REPEAT
5652 drw 18
INTERNAL
(3)
ADDRESS
ADS
CNTEN
t
SRPT
t
HRPT
t
SD
t
HD
t
SW
t
HW
EXECUTE
REPEAT WRITE
LAST ADS
ADDRESS
READ
LAST ADS
ADDRESS
READ
LAST ADS
ADDRESS + 1
READ
ADDRESS n
Qn
An + 1 An + 2
READ
ADDRESS n+1
DATA
OUT
t
SA
t
HA
LAST ADS +1 An An + 1
(4)
(5)
(6)
Ax
t
SAD
t
HAD
t
SCN
t
HCN
,
6.42
IDT70T3339/19/99S
High-Speed 2.5V 512/256/128K x 18 Dual-Port Static RAM Industrial and Commercial Temperature Ranges
20
Waveform of Interrupt Timing (2)
NOTES:
1. CE0 = VIL and CE1 = VIH
2. All timing is the same for Left and Right ports.
3. Address is for internal register, not the external bus, i.e., address needs to be qualified by one of the Address counter control signals.
t
SW
t
HW
7FFFF
CLK
R
CE
R
(1)
ADDRESS
R
(3)
t
SA
t
HA
7FFFF
t
SC
t
HC
t
INR
CLK
L
R/W
L
ADDRESS
L
(3)
CE
L
(1)
t
SA
t
HA
t
SC
t
HC
5652 drw 19
INT
R
t
INS
R/W
R
t
SW
t
HW
T ruth T able III — Interrupt Flag (1)
Left Port Right Port
FunctionCLK
L
R/W
L
(2)
CE
L
(2)
A
18L
-A
0L
(3,4,5)
INT
L
CLK
R
R/W
R
(2)
CE
R
(2)
A
18R
-A
0R
(3,4,5)
INT
R
↑L L 7FFFF X ↑XX X LSet Right INT
R
Flag
↑XX X X↑H L 7FFFF H Re se t Righ t INT
R
Flag
↑XX X L↑L L 7FFFE X Se t Le ft INT
L
Flag
↑H L 7FFFE H ↑X X X X Res e t L e ft INT
L
Flag
5652 tbl 12
NOTES:
1. INTL and INTR must be initialized at power-up by Resetting the flags.
2. CE0 = VIL and CE1 = VIH. R/W and CE are synchronous with respect to the clock and need valid set-up and hold times.
3. A18X is a NC for IDT70T3319, therefore Interrupt Addresses are 3FFFF and 3FFFE.
4. A18X and A17X are NC's for IDT70T3399, therefore Interrupt Addresses are 1FFFF and 1FFFE.
5. Address is for internal register, not the external bus, i.e., address needs to be qualified by one of the Address counter control signals.
6.42
IDT70T3339/19/99S
High-Speed 2.5V 512/256/128K x 18 Dual-Port Static RAM Industrial and Commercial Temperature Ranges
21
t
SA
t
HA
(3)
t
COLS
t
COLR
A
3
HA
t
SA
t
t
COLS
t
COLR
5652 drw 20
COL
R
COL
L
(4)
CLK
R
A
DDRESS
R
A
0
A
1
A
2
t
OFS
(4)
CLK
L
ADDRESS
L
A
0
A
1
A
2
A
3
t
OFS
Wavef orm of Collision Timing (1,2)
Both P orts Writing with Left P ort Clock Leading
Collision Detection Timing(3,4)
Cycle T ime
t
OFS
(ns)
Region 1 (ns)
(1)
Region 2 (ns)
(2)
5ns 0 - 2.8 2.81 - 4.6
6ns 0 - 3.8 3.81 - 5.6
7.5ns 0 - 5.3 5.31 - 7.1
5652 tb l 13
NOTES:
1. Region 1
Both ports show collision after 2nd cycle for Addresses 0, 2, 4 etc.
2. Region 2
Leading port shows collision after 3rd cycle for addresses 0, 3, 6, etc.
while trailing port shows collision after 2nd cycle for addresses 0, 2, 4 etc.
3. All the production units are tested to midpoint of each region.
4. These ranges are based on characterization of a typical device.
Left P ort Ri ght P ort
FunctionCLK
L
R/W
L
(1) CE
L
(1) A
18L
-A
0L
(2) COL
L
CLK
R
R/W
R
(1) CE
R
(1) A
18R
-A
0R
(2) COL
R
↑HLMATCHH↑HLMATCHH
Bo th po rts reading. Not a valid c ollisio n.
No fl ag o utput on e ith e r po rt.
↑HLMATCHL↑LLMATCHH
Left port reading, Right port writing.
Valid co llision, flag o utput on Left po rt.
↑LLMATCHH↑HLMATCHL
Right port reading, Left port writing.
Valid co llision, flag o utput on Right po rt.
↑LLMATCHL↑LLMATCHL
Bo th po rts writing . Valid collisio n. Flag
output on both p orts.
5652 tb l 14
Truth Table IV — Collision Detection Flag
NOTES:
1. CE0 = VIL and CE1 = VIH. R/W and CE are synchronous with respect to the clock and need valid set-up and hold times.
2. Address is for internal register, not the external bus, i.e., address needs to be qualified by one of the Address counter control signals.
NOTES:
1. CE0 = VIL, CE1 = VIH.
2. For reading port, OE is a Don't care on the Collision Detection Logic. Please refer to Truth Table IV for specific cases.
3 . Leading Port Output flag might output 3tCYC2 + tCOLS after Address match.
4. Address is for internal register, not the external bus, i.e., address needs to be qualified by one of the Address counter control signals.
6.42
IDT70T3339/19/99S
High-Speed 2.5V 512/256/128K x 18 Dual-Port Static RAM Industrial and Commercial Temperature Ranges
22
(3)
R/W
DATA
OUT
R/W
OE
(4)
Dn Dn+1
An+1An
(5)
(5)
Timing Wa v eform - Entering Sleep Mode (1,2)
Timing W av eform - Exiting Sleep Mode (1,2)
NOTES:
1. CE1 = VIH.
2. All timing is same for Left and Right ports.
3. CE0 has to be deactivated (CE0 = VIH) three cycles prior to asserting ZZ (ZZx = VIH) and held for two cycles after asserting ZZ (ZZx = VIH).
4. CE0 has to be deactivated (CE0 = VIH) one cycle prior to de-asserting ZZ (ZZx = VIL) and held for three cycles after de-asserting ZZ (ZZx = VIL).
5. The device must be in Read Mode (R/W High) when exiting sleep mode. Outputs are active but data is not valid until the following cycle.
6.42
IDT70T3339/19/99S
High-Speed 2.5V 512/256/128K x 18 Dual-Port Static RAM Industrial and Commercial Temperature Ranges
23
Functional Description
The IDT70T3339/19/99 provides a true synchronous Dual-Port Static
RAM interface. Registered inputs provide minimal set-up and hold times
on address, data, and all critical control inputs. All internal registers are
clocked on the rising edge of the clock signal, however, the self-timed
internal write pulse width is independent of the cycle time.
An asynchronous output enable is provided to ease asyn-
chronous bus interfacing. Counter enable inputs are also provided to stall
the operation of the address counters for fast interleaved
memory applications.
A HIGH on CE0 or a LOW on CE1 for one clock cycle will power down
the internal circuitry to reduce static power consumption. Multiple chip
enables allow easier banking of multiple IDT70T3339/19/99s for depth
expansion configurations. Two cycles are required with CE0 LOW and
CE1 HIGH to re-activate the outputs.
Interrupts
If the user chooses the interrupt function, a memory location (mail
box or message center) is assigned to each port. The left port interrupt
flag (INTL) is asserted when the right port writes to memory location
7FFFE (HEX), where a write is defined as CER = R/WR = VIL per the
Truth Table. The left port clears the interrupt through access of
address location 7FFFE when CEL = VIL and R/WL = VIH. Likewise, the
right port interrupt flag (INTR) is asserted when the left
port writes to memory location 7FFFF (HEX) and to clear the interrupt
flag (INTR), the right port must read the memory location 7FFFF (3FFFF
or 3FFFE for IDT70T3319 and 1FFFF or 1FFFE for IDT70T3399). The
message (18 bits) at 7FFFE or 7FFFF (3FFFF or 3FFFE for IDT70T3319
and 1FFFF or 1FFFE for IDT70T3399) is user-defined since it is an
addressable SRAM location. If the interrupt function is not used, address
locations 7FFFE and 7FFFF (3FFFF or 3FFFE for IDT70T3319 and
1FFFF or 1FFFE for IDT70T3399) are not used as mail boxes, but as
part of the random access memory. Refer to Truth Table III for the interrupt
operation.
Collision Detection
Sleep Mode
The IDT70T3339/19/99 is equipped with an optional sleep or low
power mode on both ports. The sleep mode pin on both ports is
asynchronous and active high. During normal operation, the ZZ pin is
pulled low. When ZZ is pulled high, the port will enter sleep mode where
it will meet lowest possible power conditions. The sleep mode timing
diagram shows the modes of operation: Normal Operation, No Read/Write
Allowed and Sleep Mode.
For normal operation all inputs must meet setup and hold times prior
to sleep and after recovering from sleep. Clocks must also meet cycle high
and low times during these periods. Three cycles prior to asserting ZZ
(ZZx = VIH) and three cycles after de-asserting ZZ (ZZx = VIL), the device
must be disabled via the chip enable pins. If a write or read operation occurs
during these periods, the memory array may be corrupted. Validity of data
out from the RAM cannot be guaranteed immediately after ZZ is asserted
(prior to being in sleep). When exiting sleep mode, the device must be in
Read mode (R/Wx = VIH)when chip enable is asserted, and the chip
enable must be valid for one full cycle before a read will result in the output
of valid data.
During sleep mode the RAM automatically deselects itself. The RAM
disconnects its internal clock buffer. The external clock may continue to run
without impacting the RAMs sleep current (IZZ). All outputs will remain in
high-Z state while in sleep mode. All inputs are allowed to toggle. The RAM
will not be selected and will not perform any reads or writes.
Collision is defined as an overlap in access between the two ports
resulting in the potential for either reading or writing incorrect data to a
specific address. For the specific cases: (a) Both ports reading - no
data is corrupted, lost, or incorrectly output, so no collision flag is output
on either port. (b) One port writing, the other port reading - the end
result of the write will still be valid. However, the reading port might
capture data that is in a state of transition and hence the reading port’s
collision flag is output. (c) Both ports writing - there is a risk that the two
ports will interfere with each other, and the data stored in memory will
not be a valid write from either port (it may essentially be a random
combination of the two). Therefore, the collision flag is output on both
ports. Please refer to Truth Table IV for all of the above cases.
The alert flag (COLX) is asserted on the 2nd or 3rd rising clock
edge of the affected port following the collision, and remains low for
one cycle. Please refer to Collision DetectionTiming table on Page 21.
During that next cycle, the internal arbitration is engaged in resetting
the alert flag (this avoids a specific requirement on the part of the user
to reset the alert flag). If two collisions occur on subsequent clock
cycles, the second collision may not generate the appropriate alert
Collision detection on the IDT70T3339/19/99 represents a
significant advance in functionality over current sync multi-ports, which
have no such capability. In addition to this functionality the
IDT70T3339/19/99 sustains the key features of bandwidth and
flexibility. The collision detection function is very useful in the case of
bursting data, or a string of accesses made to sequential addresses, in
that it indicates a problem within the burst, giving the user the option of
either repeating the burst or continuing to watch the alert flag to see
whether the number of collisions increases above an acceptable
threshold value. Offering this function on chip also allows users to
reduce their need for arbitration circuits, typically done in CPLD’s or
FPGA’s. This reduces board space and design complexity, and gives
the user more flexibility in developing a solution.
flag. A third collision will generate the alert flag as appropriate. In the
event that a user initiates a burst access on both ports with the same
starting address on both ports and one or both ports writing during
each access (i.e., imposes a long string of collisions on contiguous
clock cycles), the alert flag will be asserted and cleared every other
cycle. Please refer to the Collision Detection timing waveform on page
21.
6.42
IDT70T3339/19/99S
High-Speed 2.5V 512/256/128K x 18 Dual-Port Static RAM Industrial and Commercial Temperature Ranges
24
Depth and Width Expansion
The IDT70T3339/19/99 features dual chip enables (refer to Truth
Table I) in order to facilitate rapid and simple depth expansion with no
requirements for external logic. Figure 4 illustrates how to control the
various chip enables in order to expand two devices in depth.
The IDT70T3339/19/99 can also be used in applications requiring
expanded width, as indicated in Figure 4. Through combining the control
signals, the devices can be grouped as necessary to accommodate
applications needing 36-bits or wider.
NOTE:
1. A19 is for IDT70T3339, A18 is for IDT70T3319, A17 is for IDT70T3399.
5652 drw 23
IDT70T3339/19/99
CE
0
CE
1
CE
1
CE
0
CE
0
CE
1
CE
1
CE
0
V
DD
V
DD
IDT70T3339/19/99
IDT70T3339/19/99
IDT70T3339/19/99
Control Inputs
Control Inputs
Control Inputs
Control Inputs UB,LB,
R/W,
OE,
CLK,
ADS,
REPEAT
,
CNTEN
A
19
/A
18/
A
17(1)
Figure 4. Depth and Width Expansion with IDT70T3339/19/99
6.42
IDT70T3339/19/99S
High-Speed 2.5V 512/256/128K x 18 Dual-Port Static RAM Industrial and Commercial Temperature Ranges
25
JT AG AC Electrical
Characteristics (1,2,3,4)
JTAG Timing Specifications
NOTES:
1. Guaranteed by design.
2. 30pF loading on external output signals.
3. Refer to AC Electrical Test Conditions stated earlier in this document.
4. JTAG operations occur at one speed (10MHz). The base device may run at
any speed specified in this datasheet.
TCK
Device Inputs
(1)
/
TDI/TMS
D
evice Outputs
(2)
/
TDO
TRST
t
JCD
t
JDC
t
JRST
t
JS
t
JH
t
JCYC
t
JRSR
t
JF
t
JCL
t
JR
t
JCH
5652 drw 23
,
NOTES:
1. Device inputs = All device inputs except TDI, TMS, and TRST.
2. Device outputs = All device outputs except TDO.
70T3339/19/99
Symbol Parameter Min. Max. Units
t
JCYC
JTAG Clock Input Period 100
____
ns
t
JCH
J TA G Clo ck HIGH 40
____
ns
t
JCL
JTAG Clock Low 40
____
ns
t
JR
J TA G Cl o c k Ris e Tim e
____
3
(1)
ns
t
JF
JTAG Clock Fall Time
____
3
(1)
ns
t
JRST
JTAG Res et 50
____
ns
t
JRSR
JTAG Re set Re cove ry 50
____
ns
t
JCD
JTAG Data Output
____
25 ns
t
JDC
J TA G Data Outp ut Ho ld 0
____
ns
t
JS
JTAG Setup 15
____
ns
t
JH
JTAG Hold 15
____
ns
5652 tb l 1 5
6.42
IDT70T3339/19/99S
High-Speed 2.5V 512/256/128K x 18 Dual-Port Static RAM Industrial and Commercial Temperature Ranges
26
Identification Register Definitions
System Interface Parameters
NOTES:
1. Device outputs = All device outputs except TDO.
2. Device inputs = All device inputs except TDI, TMS, and TRST.
3. The Boundary Scan Descriptive Language (BSDL) file for this device is available on the IDT website (www.idt.com), or by contacting your local
IDT sales representative.
NOTE:
1. Device ID for IDT70T3319 is 0x334. Device ID for IDT70T3399 is 0x335.
Instruction Field Value Description
Revision Number (31:28) 0x0 Reserved for version number
IDT De vice ID (27:12) 0x333
(1)
De fine s IDT part numbe r
IDT JEDEC ID (11:1) 0x 33 All o ws uni que id e ntific atio n o f de vice v endo r as IDT
ID Register Indicator Bit (Bit 0) 1 Indicates the presence of an ID register
5652 tb l 16
Scan Register Sizes
Register Nam e Bit Size
Ins tructi o n (IR) 4
Bypass (BYR) 1
Identifi c ati o n (ID R) 32
Bound ary Scan (BSR) No te (3)
5 652 tb l 17
Instruction Code Description
EXTEST 0000 Forces contents of the boundary scan cells onto the device outputs
(1)
.
Places the boundary scan register (BSR) between TDI and TDO.
BYPASS 1111 Places the bypass register (BYR) between TDI and TDO.
IDCODE 0010 Loads the ID register (IDR) with the vendor ID code and places the
register between TDI and TDO.
HIGHZ 0100 Places the bypass register (BYR) between TDI and TDO. Forces all
device output drivers to a High-Z state except COLx & INTx outp uts.
CLAMP 0011 Uses BYR. Forces contents of the boundary scan cells onto the device
outputs. Places the bypass register (BYR) between TDI and TDO.
SAMPLE/PRELOAD 0001 Places the bound ary sc an re gister (BSR) betwee n TDI and TDO.
SAMPLE allo ws data from device inputs
(2)
to be captured in the
b oundary s can ce l ls a nd s hi fte d s e ri all y thro ugh TDO . P RE LOA D a ll o ws
data to be input serially into the boundary scan cells via the TDI.
RESERVED 0101, 0111, 1000, 1001,
1010, 1011, 1100 Se ve ral c o mb inatio ns are re s erve d. Do no t us e co d e s o the r than tho se
identified above.
P R I VATE 0 11 0,111 0 , 11 0 1 F or in ter n a l use on l y .
5652 tb l 18
6.42
IDT70T3339/19/99S
High-Speed 2.5V 512/256/128K x 18 Dual-Port Static RAM Industrial and Commercial Temperature Ranges
27
Ordering Information
NOTES:
1. 166MHz I-Temp is not available in the BF-208 package.
2. 200Mhz is not available in the BF-208 and DD-144 packages.
3. Green parts available. For specific speeds, packages and powers contact your local sales office.
A
Power 999
Speed A
Package A
Process/
Temperature
Range
Blank
ICommercial (0°C to +70°C)
Industrial (-40°C to +85°C)
BC
DD
BF
256-pin BGA (BC-256)
144-pin TQFP (DD-144)
208-pin fpBGA (BF-208)
200
166
133
5652 drw 25
70T3339
70T3319
70T3399
9Mbit (512K x 18-Bit) Synchronous Dual-Port RAM
4Mbit (256K x 18-Bit) Synchronous Dual-Port RAM
2Mbit (128K x 18-Bit) Synchronous Dual-Port RAM
S
XXXXX
Device
Type
Speed in Megahertz
Standard Power
Commercial Only
(2)
Commercial & Industrial
(1)
Commercial & Industrial
A
G
(3)
Green
IDT Clock Solution for IDT70T3339/19/99 Dual-Port
IDT Dua l-Por t
Part Nu mb e r
Dua l-Port I/ O Spec iti ca tions C lock S p ec ific ati on s IDT
PLL
Clock Device
IDT
Non-PLL
Clock Device
Voltage I/O Input
Capacitance
Inp ut Duty
Cycle
Requirement
Maximum
Frequency Jitter
Tolerance
70T3339/19/99 2.5 LVTTL 8pF 40% 200 75ps 5T2010 5T9010
5T 90 5, 5 T 9 05 0
5T 90 7, 5 T 9 07 0
5652 tbl 19
6.42
IDT70T3339/19/99S
High-Speed 2.5V 512/256/128K x 18 Dual-Port Static RAM Industrial and Commercial Temperature Ranges
28
Datasheet Document History:
01/20/03: Initial Datasheet
04/25/03: Page 11 Added Capacitance Derating drawing
Page 12 Changed t INS and tINR specs in AC Electrical Characteristics table
11/11/03: Page 10 Updated power numbers in DC Electrical Characteristics table
Page 12 Added tOFS symbol and parameter to AC Electrical Characteristics table
Page 21 Updated Collision Timing waveform
Page 22 Added Collision Detection Timing table and footnotes
Page 26 Updated HIGHZ function in System Interface Parameters table
Page 27 Added IDT Clock Solution table
04/08/04: Page 22 & 23 Clarified Sleep Mode Text and Waveforms
Page 1 & 28 Removed Preliminary status
Page 6 Added another sentence to footnote 4 to recommend that boundary scan not be operated during sleep mode
02/07/06: Page 1 Added green availability to features
Page 7 Changed footnote 2 for Truth Table I from ADS, CNTEN, REPEAT = VIH to ADS, CNTEN, REPEAT = X
Page 27 Added green indicator to ordering information
07/28/08: Page 10 Corrected a typo in the DC Chars table footnotes
01/19/09: Page 28 Removed "IDT" from orderable part number
CORPORATE HEADQUARTERS for SALES: for Tech Support:
6024 Silver Creek Valley Road 800-345-7015 or 408-284-8200 408-284-2794
San Jose, CA 95138 fax: 408-284-2775 DualPortHelp@idt.com
www.idt.com
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
