GS1574ACNE3TH - SEMTECH INTERNATIONAL

1 of 16GS1574A HD-LINX® II Adaptive Cable Equalizer

Data Sheet

33416 - 10 August 2011

GS1574A HD-LINX® II Adaptive Cable Equalizer

www.gennum.com

Features

• SMPTE 292M and SMPTE 259M compliant

•Automatic cable equalization

• Multi-standard operation from 143Mb/s to 1.485Gb/s

• Supports DVB-ASI at 270Mb/s

• Small footprint (4mm x 4mm)

• Pb-free and RoHS compliant

• Manual bypass (useful for low data rates with slow

rise/fall times)

• Performance optimized for 270Mb/s and 1.485Gb/s

• Typical equalized length of Belden 1694A cable: 200m

at 1.485Gb/s, 350m at 270Mb/s

•50Ω differential output (with internal 50Ω pull-ups)

• Manual output mute or programmable mute based on

max cable length adjust

• Single 3.3V power supply operation

• Operating temperature range: 0°C to +70°C

Application

• SMPTE 292M and SMPTE 259M Coaxial Cable Serial

Digital Interfaces

Description

The GS1574A is a second-generation high-speed BiCMOS

integrated circuit designed to equalize and restore signals

received over 75

co-axial cable

The GS1574A is designed to support SMPTE 292M and

SMPTE 259M, and is optimized for performance at 270Mb/s

and 1.485Gb/s.

The GS1574A features DC restoration to compensate for

the DC content of SMPTE pathological test patterns.

A voltage programmable mute threshold (MCLADJ) is

included to allow muting of the GS1574A output when an

approximate selected cable length is reached for SMPTE

259M signals. This feature allows the GS1574A to

distinguish between low amplitude SD-SDI signals and

noise at the input of the device. The serial digital outputs of

the GS1574A may be forced to a mute state by applying a

voltage to the MUTE pin.

Power consumption is typically 215mW using a 3.3V

power supply. The GS1574A is lead-free, and the

encapsulation compound does not contain halogenated

flame retardant.

This component and all homogeneous subcomponents are

RoHS compliant.

Figure A: GS1574A Functional Block Diagram

CABLE LENGTH ADJUSTOR

CARRIER DETECT

MUTE

EQUALIZER DC RESTORE OUTPUT

AGC

MUTE

SDO

BYPASS

SDOSDI

SDI

MCLADJ

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Data Sheet

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Revision History

Version ECR PCN Date Changes and/or Modifications

10 156775 – August 2011 Added the tape and reel part number to Table 9-1: GS1574A Ordering

Information

9 153754 – September 2009 Updated to latest Gennum template.

8 144435 – March 2007 Added maximum power consumption to DC Electrical Characteristics.

7 141758 40438 August 2006 Modified 200m cable length in front page Features section and Detailed

Description.

6 141576 40438 August 2006 Added 200m output cable length jitter data at 1.485Gb/s in AC Electrical

Characteristics.

5 139634 38695 March 2006 Corrected pad standoff height and tolerances for pad width & package

dimension. Corrected pad shape.

4 137744 – September 2005 Convert to Data Sheet. Corrected typing errors. Corrected process to BiCMOS.

3 137321 – June 2005 Amended notes on use of MCLADJ above 360 Mb/s.

2 137167 – June 2005 Rephrased RoHS compliance statement.

1 136885 – May 2005 Corrected description of connection for AGC and AGC pins in the Pin

Description table. Clarified solder reflow profile descriptions. Corrected

minor typing errors.

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Data Sheet

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Contents

Features.................................................................................................................................................................1

Application...........................................................................................................................................................1

Description...........................................................................................................................................................1

Revision History .................................................................................................................................................2

1. Pin Out...............................................................................................................................................................4

1.1 GS1574A Pin Assignment ..............................................................................................................4

1.2 GS1574A Pin Descriptions .............................................................................................................4

2. Electrical Characteristics ............................................................................................................................6

2.1 Absolute Maximum Ratings ..........................................................................................................6

2.2 DC Electrical Characteristics ........................................................................................................6

2.3 AC Electrical Characteristics ........................................................................................................7

3. Solder Reflow Profiles..................................................................................................................................9

4. Test Circuit .................................................................................................................................................... 10

5. Input / Output Circuits ............................................................................................................................. 11

6. Detailed Description.................................................................................................................................. 13

6.1 Serial Digital Inputs ...................................................................................................................... 13

6.2 Cable Equalization ........................................................................................................................ 13

6.3 Programmable Mute Output ...................................................................................................... 14

6.4 Mute and Carrier Detect .............................................................................................................. 14

7. Application Information .......................................................................................................................... 15

7.1 PCB Layout ....................................................................................................................................... 15

7.2 Typical Application Circuit ........................................................................................................ 15

8. Package and Ordering Information...................................................................................................... 16

8.1 Package Dimensions ..................................................................................................................... 16

8.2 Recommended PCB Footprint ................................................................................................... 17

8.3 Packaging Data ............................................................................................................................... 17

8.4 Ordering Information ................................................................................................................... 18

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Data Sheet

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1. Pin Out

1.1 GS1574A Pin Assignment

Figure 1-1: 16-Pin QFN

1.2 GS1574A Pin Descriptions

GS1574A

(top view)

VEE_A

SDI

SDI 2

SDO

VEE_D

AGC

BYPASS

MCLADJ

VCC_A

MUTE

VCC_D

Center Pad

(bottom of package, internally

bonded to VEE_A)

Table 1-1: GS1574A Pin Descriptions

Number Name Timing Ty p e Description

1, 4 VEE_A Analog Power Most negative power supply for analog circuitry.

Connect to GND.

2, 3 SDI, SDI Analog Input Serial digital differential input.

5, 6 AGC, AGC Analog – External AGC capacitor.

Connect pin 5 and pin 6 together as shown in the Typical Application

Circuit on page 13.

7BYPASS Not

Synchronous

Input Forces the Equalizing and DC RESTORE stages into bypass mode when

HIGH. No equalization occurs in this mode.

8 MCLADJ Analog Input Maximum cable length adjust.

Adjusts the approximate maximum amount of cable to be equalized

(from 0m to the maximum cable length). The output is muted (latched to

the last state) when the maximum cable length is achieved.

NOTE: MCLADJ is only recommended for data rates up to 360Mb/s. For

data rates above this, MCLADJ should be left floating.

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Data Sheet

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9 VEE_D Analog Power Most negative power supply for the digital circuitry and output buffer.

Connect to GND.

10, 11 SDO, SDO Analog Output Equalized serial digital differential output.

12 VEE_D Analog Power Most negative power supply for the digital circuitry and output buffer.

Connect to GND.

13 VCC_D Analog Power Most positive power supply for the digital I/O pins of the device.

Connect to +3.3V DC.

14 MUTE Not

Synchronous

Input CONTROL SIGNAL INPUT

levels are LVCMOS/LVTTL compatible. (3.3V Tolerant)

When the MUTE pin is set HIGH by the application interface, the serial

digital output of the device will be forced to a steady state.

When the MUTE pin is set LOW, the serial digital output of the device will

be active.

NOTE: This pin may be connected directly to the CD pin to allow mute on

loss of carrier.

15 CD Not

Synchronous

Output STATUS SIGNAL OUTPUT

Signal levels are LVCMOS/LVTTL compatible.

Indicates the presence of a good input signal.

When the CD pin is LOW, a good input signal has been detected.

When this pin is HIGH, the input signal is invalid.

This pin will indicate loss of carrier for data rates > 19Mb/s.

16 VCC_A Analog Power Most positive power supply for the analog circuitry of the device.

Connect to +3.3V DC.

– Center Pad – Power Internally bonded to VEE_A.

Table 1-1: GS1574A Pin Descriptions (Continued)

Number Name Timing Ty p e Description

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Data Sheet

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2. Electrical Characteristics

2.1 Absolute Maximum Ratings

2.2 DC Electrical Characteristics

Table 2-1: Absolute Maximum Ratings

Parameter Value

Supply Voltage -0.5V to +3.6 VDC

Input ESD Voltage 2kV

Storage Temperature Range -50°C < Ts < 125°C

Input Voltage Range (any input) -0.3 to (VCC +0.3)V

Operating Temperature Range 0°C to 70°C

Solder Reflow Temperature 260°C

Table 2-2: DC Electrical Characteristics

VCC = 3.3V ±5%, TA = 0°C to 70°C, unless otherwise shown

Parameter Symbol Conditions Min Ty p Max Units Notes

Supply Voltage VCC – 3.135 3.3 3.465 V ±5%

Power Consumption PDTA = 25°C – 215 – mW –

–––343mW–

Supply Current IsTA = 25°C – 65 – mA –

Output Common Mode

Voltage

VCMOUT TA = 25°C – VCC - ΔVSDO/2 – V –

Input Common Mode Voltage VCMIN TA = 25°C – 1.75 – V –

MCLADJ DC Voltage (to mute

signal)

–0m, T

A = 25°C – 1.3 – V –

MCLADJ Range – TA = 25°C – 0.5 – V –

CD Output Voltage VCD(OH) Carrier not

present

2.4 – – V –

VCD(OL) Carrier present – – 0.4 V –

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2.3 AC Electrical Characteristics

Mute Input Voltage Required

to Force Outputs to Mute

VMute Min to Mute 2.0 – – V –

Mute Input Voltage Required

to Force Outputs Active

VMute Max to

Activate

––0.8V–

Table 2-2: DC Electrical Characteristics (Continued)

VCC = 3.3V ±5%, TA = 0°C to 70°C, unless otherwise shown

Parameter Symbol Conditions Min Ty p Max Units Notes

Table 2-3: AC Electrical Characteristics

VCC = 3.3V ±5%, TA = 0°C to 70°C, unless otherwise shown

Parameter Symbol Conditions Min Typ Max Units Notes

Serial input data rate DRSDO – 143 – 1485 Mb/s –

Input Voltage Swing ΔVSDI TA =25°C, differential 720 800 950 mVp-p 1

Output Voltage Swing ΔVSDO 100Ω load, TA =25°C,

differential

– 750 – mVp-p –

Output Jitter for Various

Cable Lengths and Data

Rates

– 270Mb/s

Belden 1694A: 0-350m

Belden 8281: 0-280m

– 0.2 – UI 2,5

– 1.485Gb/s

Belden 1694A: 0-140m

Belden 8281: 0-100m

–0.25– UI2,5

– 1.485Gb/s

Belden 1694A: 140-200m

– 0.3 – UI 4,5

Output Rise/Fall time – 20% - 80% – 80 220 ps –

Mismatch in rise/fall time – – – – 30 ps –

Duty cycle distortion – – – – 30 ps –

Overshoot – – – – 10 % –

Input Return Loss – – 15 – – dB 3

Input Resistance – single ended – 1.64 – kΩ–

Input Capacitance – single ended – 1 – pF –

Output Resistance – single ended – 50 – Ω–

NOTES:

1. 0m cable length.

2. All parts production tested. In order to guarantee jitter over the full range of specification (VCC = 3.3V ±5%, TA = 0°C to 70°C, and

720-880mV launch swing from the SDI cable driver) the recommended applications circuit must be used.

3. Tested on CB1574A board from 5MHz to 2GHz.

4. Based on characterization data using the recommended applications circuit, at VCC = 3.3V, TA = 25°C, and 800mV launch swing from the SDI

cable driver.

5. Equalizer Pathological test signal is used.

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Data Sheet

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3. Solder Reflow Profiles

The device is manufactured with Matte-Sn terminations and is compatible with both

standard eutectic and Pb-free solder reflow profiles. MSL qualification was performed

using the maximum Pb-free reflow profile shown in Figure 3-1. The recommended

standard Pb reflow profile is shown in Figure 3-2.

Figure 3-1: Maximum Pb-free Solder Reflow Profile (Preferred)

Figure 3-2: Standard Pb Solder Reflow Profile

25°C

150°C

200°C

217°C

260°C

250°C

Time

Temperature

8 min. max

60-180 sec. max

60-150 sec.

20-40 sec.

3°C/sec max

6°C/sec max

25°C

100°C

150°C

183°C

230°C

220°C

Time

Temperature

6 min. max

120 sec. max

60-150 sec.

10-20 sec.

3°C/sec max

6°C/sec max

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Data Sheet

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4. Test Circuit

Figure 4-1: Test Circuit

5. Input / Output Circuits

Figure 5-1: Input Equivalent Circuit

Figure 5-2: MCLADJ Equivalent Circuit

GigaBERT

1400

EXT.

CLOCK

OUT

DATA

OUT

EXT.

CLOCK

1.485GHz/270MHz

GS1574A

TEST BOARD TDS 820

CH. 1

CH. 2

OUTIN

OUT

EXT. TRIGGER

50/75

8281 or 1694A CABLE

3.6k

SDI SDI

VCC

MCLADJ

12.2k

150µ

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Data Sheet

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Figure 5-3: Output Circuit

Figure 5-4: MUTE and BYPASS Circuits

Figure 5-5: CD Circuit

SDOSDO

MUTE,

BYPASS

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6. Detailed Description

The GS1574A is a high speed BiCMOS IC designed to equalize serial digital signals.

The GS1574A can equalize both HD and SD serial digital signals, and will typically

equalize 200m of Belden 1694A cable at 1.

485Gb/

s and 350m at 270Mb/s.

The GS1574A is powered from a single +3.3V power supply and consumes

approximately 215mW of power.

6.1 Serial Digital Inputs

The serial data signal may be connected to the input pins (SDI/SDI) in either a

differential or single ended configuration. AC coupling of the inputs is recommended, as

the SDI and SDI inputs are internally biased at approximately 1.8V.

6.2 Cable Equalization

The input signal passes through a variable gain equalizing stage whose frequency

response closely matches the inverse of the cable loss characteristic. In addition, the

variation of the frequency response with control voltage imitates the variation of the

inverse cable loss characteristic with cable length.

The edge energy of the equalized signal is monitored by a detector circuit which

produces an error signal corresponding to the difference between the desired edge

energy and the actual edge energy. This error signal is integrated by both an internal and

an external AGC filter capacitor providing a steady control voltage for the gain stage. As

the frequency response of the gain stage is automatically varied by the application of

negative feedback, the edge energy of the equalized signal is kept at a constant level

which is representative of the original edge energy at the transmitter. The equalized

signal is also DC restored, effectively restoring the logic threshold of the equalized signal

to its correct level independent of shifts due to AC coupling. The digital output signals

have a nominal voltage of 750mVpp differential, or 375mVpp single ended when

terminated with 50Ω as shown in Figure 6-1.

Figure 6-1: Typical Output Voltage Levels

50 50

SDO

+187.5mV

-187.5mV

VCM = 2.925V

typical

+187.5mV

-187.5mV

VCM = 2.925V

typical

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6.3 Programmable Mute Output

For SMPTE 259M inputs, the GS1574A incorporates a programmable threshold output

mute (MCLADJ).

In applications where there are multiple input channels using the GS1574A, it is

advantageous to have a programmable mute output to avoid signal crosstalk.

The output of the GS1574A can be muted when the input signal decreases below a

certain input level. This threshold is determined using the input voltage applied to the

MCLADJ pin. The MCLADJ pin may be left unconnected for applications where output

muting is not required.

This feature has been designed for use in applications such as routers where signal

crosstalk and circuit noise cause the equalizer to output erroneous data when no input

signal is present. The use of a Carrier Detect function with a fixed internal reference

does not solve this problem since the signal to noise ratio on the circuit board could be

significantly less than the default signal detection level set by the on chip reference.

NOTE: MCLADJ is only recommended for data rates up to 360Mb/s. For data rates above

this, MCLADJ should be left floating.

6.4 Mute and Carrier Detect

The GS1574A includes a MUTE input pin that allows the application interface to mute

the serial digital output at any time. Set the MUTE pin HIGH to mute SDO and SDO. In

this case, the outputs will mute regardless of the setting of the BYPASS pin.

A Carrier Detect output pin (CD) indicates the presence of a valid signal at the input of

the GS1574A. When CD is LOW, the device has detected a valid input on SDI and SDI.

When CD is HIGH, the device has not detected a valid input.

NOTE: CD will only detect loss of carrier for data rates greater than 19Mb/s. The CD

output pin may be connected directly to the MUTE input pin to enable automatic muting

of the GS1574A when no valid input signal has been detected.

NOTE: If the maximum cable length is exceeded and the device is not in bypass mode

the GS1574A will not assert the CD pin even if a carrier is present.

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7. Application Information

7.1 PCB Layout

Special attention must be paid to component layout when designing serial digital

interfaces for HDTV. An FR-4 dielectric can be used, however, controlled impedance

transmission lines are required for PCB traces longer than approximately 1cm. Note the

following PCB artwork features used to optimize performance:

• PCB trace width for HD rate signals is closely matched to SMT component width to

minimize reflections due to change in trace impedance.

• The PCB ground plane is removed under the GS1574A input components to

minimize parasitic capacitance.

• The PCB ground plane is removed under the GS1574A output components to

minimize parasitic capacitance.

• High speed traces are curved to minimize impedance changes.

7.2 Typical Application Circuit

Figure 7-1: GS1574A Typical Application Circuit

GS1574A

SDI

VEE_D

MUTE

VCC_D

AGC

BYPASS

MCLADJ

VEE_A

NOTE: All resistors in Ohms, capacitors in Farads,

and inductors in Henrys, unless otherwise noted.

VEE_A

AGC

VCC_A

SDO

VEE_D

10n

10nF

SDO

4.7μF

SDO

MUTE

VCC

BYPASS

MCLADJ

470nF

6.2nH

75Ω

SDI

1μF

75Ω

1μF

37.4Ω

VCC

1415

470nF

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8. Package and Ordering Information

8.1 Package Dimensions

Figure 8-1: Package Dimensions

4.00+/-0.05

0.15

0.10 C

16X

0.08 C

SEATING PLANE

0.85+/-0.05

0.00-0.05

0.65/2

0.65

DETAIL B

SCALE:NTS

DATUM A OR B

TERMINAL TIP

0.20 REF

DATUM B

DETAIL B

0.65

16X

0.35+/-0.05

0.10

0.05 C

DATUM A

2.76+/-0.10

0.40+/-0.05

2.76+/-0.10

DETAIL B

CENTER TAB

PIN 1 AREA

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8.2 Recommended PCB Footprint

The Center Pad should be connected to the most negative power supply plane for analog

circuitry in the device (VEE_A) by a minimum of 5 vias.

Note: Suggested dimensions only. Final dimensions should conform to customer design

rules and process optimizations.

8.3 Packaging Data

0.35

0.55

2.76

3.70

2.763.70

NOTE: All dimensions

are in millimeters.

0.65

CENTER PAD

Table 8-1: Packaging Data

Parameter Value

Package Type 4mm x 4mm 16-pin QFN

Package Drawing Reference JEDEC M0220

Moisture Sensitivity Level 3

Junction to Case Thermal Resistance, θj-c 31.0°C/W

Junction to Air Thermal Resistance, θj-a (at zero airflow) 43.8°C/W

Psi 11.0°C/W

Pb-free and RoHS compliant Yes

CANADA

Suite 320, 3553 31st St. N.W.

Calgary, Alberta T2L 2K7

Canada

Phone: +1 (403) 284-2672

Fax: +1 (905) 632-2055

415 Legget Drive, Suite 200

Kanata, Ontario K2K 2B2

Canada

Phone: +1 (613) 270-0458

Fax: +1 (613) 270-0429

GERMANY

Gennum Canada Limited

Niederlassung Deutschland

München, Germany

Phone: +49 89 309040 290

Fax: +49 89 309040 293

E-mail: gennum-germany@gennum.com

INDIA

#208(A), Nirmala Plaza,

Airport Road, Forest Park Square

Bhubaneswar 751009

India

Phone: +91 (674) 65304815

Fax: +91 (674) 259-5733

JAPAN KK

Shinjuku Green Tower Building 27F

6-14-1, Nishi Shinjuku

Shinjuku-ku, Tokyo, 160-0023

Japan

Phone: +81 (03) 3349-5501

Fax: +81 (03) 3349-5505

E-mail: gennum-japan@gennum.com

Web Site: http://www.gennum.co.jp

MEXICO

Venustiano Carranza 122 Int. 1

Centro, Aguascalientes

Mexico CP 20000

Phone: +1 (416) 848-0328

NORTH AMERICA WESTERN REGION

691 South Milpitas Blvd., Suite #200

Milpitas, CA 95035

United States

Phone: +1 (408) 934-1301

Fax: +1 (408) 934-1029

E-mail: naw_sales@gennum.com

NORTH AMERICA EASTERN REGION

4281 Harvester Road

Burlington, Ontario L7L 5M4

Canada

Phone: +1 (905) 632-2996

Fax: +1 (905) 632-2055

E-mail: nae_sales@gennum.com

TAIWAN

6F-4, No.51, Sec.2, Keelung Rd.

Sinyi District, Taipei City 11502

Taiwan R.O.C.

Phone: (886) 2-8732-8879

Fax: (886) 2-8732-8870

E-mail: gennum-taiwan@gennum.com

UNITED KINGDOM

South Building, Walden Court

Parsonage Lane,

Bishop’s Stortford Hertfordshire, CM23 5DB

United Kingdom

Phone: +44 1279 714170

Fax: +44 1279 714171

2, West Point Court, Great Park Road

Bradley Stoke, Bristol BS32 4PY

Great Britain

Phone: +44 1454 462200

Fax: +44 1454 462201

SNOWBUSH IP - A DIVISION OF GENNUM

439 University Ave. Suite 1700

Toronto, Ontario M5G 1Y8

Canada

Phone: +1 (416) 925-5643

Fax: +1 (416) 925-0581

E-mail: sales@snowbush.com

Web Site: http://www.snowbush.com

DOCUMENT IDENTIFICATION

DATA SHEET

The product is in production. Gennum reserves the right to make changes to

the product at any time without notice to improve reliability, function or

design, in order to provide the best product possible.

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Gennum Corporation assumes no liability for any errors or omissions in this document, or for the use of the circuits or devices described herein. The sale of

the circuit or device described herein does not imply any patent license, and Gennum makes no representation that the circuit or device is free from patent

infringement.

All other trademarks mentioned are the properties of their respective owners.

GENNUM and the Gennum logo are registered trademarks of Gennum Corporation.

www.gennum.com

GENNUM CORPORATE HEADQUARTERS

4281 Harvester Road, Burlington, Ontario L7L 5M4 Canada

Phone: +1 (905) 632-2996 Fax: +1 (905) 632-2055

E-mail: corporate@gennum.com www.gennum.com

CAUTION

ELECTROSTATIC SENSITIVE DEVICES

DO NOT OPEN PACKAGES OR HANDLE EXCEPT AT A

STATIC-FREE WORKSTATION

9. Ordering Information

Table 9-1: GS1574A Ordering Information

Part Number Package Temperature Range

GS1574ACNE3 16-pin QFN 0°C to 70°C

GS1574ACTE3 16-pin QFN

(250pc tape and reel) 0°C to 70°C