To our customers, Old Company Name in Catalogs and Other Documents On April 1st, 2010, NEC Electronics Corporation merged with Renesas Technology Corporation, and Renesas Electronics Corporation took over all the business of both companies. Therefore, although the old company name remains in this document, it is a valid Renesas Electronics document. We appreciate your understanding. Renesas Electronics website: http://www.renesas.com April 1st, 2010 Renesas Electronics Corporation Issued by: Renesas Electronics Corporation (http://www.renesas.com) Send any inquiries to http://www.renesas.com/inquiry. Notice 1. 2. 3. 4. 5. 6. 7. All information included in this document is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please confirm the latest product information with a Renesas Electronics sales office. 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Please contact a Renesas Electronics sales office if you have any questions regarding the information contained in this document or Renesas Electronics products, or if you have any other inquiries. (Note 1) "Renesas Electronics" as used in this document means Renesas Electronics Corporation and also includes its majorityowned subsidiaries. (Note 2) "Renesas Electronics product(s)" means any product developed or manufactured by or for Renesas Electronics. M16C/28 Group (M16C/28, M16C/28B) SINGLE-CHIP 16-BIT CMOS MCU REJ03B0201-0050 Rev.0.50 2006.09.15 1. Overview The M16C/28 Group (M16C/28 and M16C/28B) MCU are single-chip control MCU, fabricated using highperformance silicon gate CMOS technology with the M16C/60 series CPU core. The M16C/28 Group (M16C/28 and M16C/28B) are housed in 64-pin and 80-pin plastic molded LQFP packages and also in 85pin plastic molded TFLGA (Thin Fine Pitch Land Grid Array) package. With a 1-Mbyte address space, this MCU combines advanced instruction manipulation capabilities to process complex instructions by less bytes and execute instructions at higher speed. It includes a multiplier and DMAC adequate for office automation, communication devices and other high-speed processing applications. The M16C/28 has Normal-ver., T-ver., and V-ver.. The M16C/28B has Normal-ver. only. This hardware manual describes the Normal-ver. only. Please contact Renesas Technology Corp. for T-ver./V-ver. information. 1.1 Applications Audio, cameras, office equipment, communication equipment, portable equipment, home appliances (inverter solution), motor control, industrial equipment, etc. Rev. 0.50 Sep.15, 2006 page 1 of 33 1. Overview M16C/28 Group (M16C/28, M16C/28B) 1.2 Performance Overview Table 1.1 and 1.2 outline performance overview of the M16C/28 Group (M16C/28, M16C/28B). Table 1.1 M16C/28 Group (M16C/28, M16C/28) Performance (80/85-Pin Package) CPU Peripheral Function Item Number of basic instructions Minimum instruction excution time Operation mode Address space Memory capacity I/O port Multifunction timer Serial I/O A/D converter DMAC Watchdog timer Interrupt Clock generation circuit Oscillation Stop Detect Function Voltage detection circuit Power supply voltage Performance 91 instructions 41.7 ns (f(BCLK) = 24 MHZ, VCC = 4.2 V to 5.5 V) (M16C/28B) 50 ns (f(BCLK) = 20 MHZ, VCC = 3.0 V to 5.5 V) (M16C/28, M16C/28B) 100 ns (f(BCLK) = 10 MHZ, VCC= 2.7 V to 5.5 V) (M16C/28, M16C/28B) Single chip mode 1M bytes See Table 1.3 Input/Output : 71 lines TimerA:16 bits x 5 channels, TimerB:16 bits x 3 channels Three-phase Motor Control Timer TimerS (Input Capture/Output Compare) : 16bit base timer x 1 channel (Input/Output x 8 channels) 2 channels (UART0, UART1) UART, clock synchronous 1 channel (UART2) UART, clock synchronous, I2C bus(1), or IEbus(2) 2 channels (SI/O3, SI/O4) Clock synchronous 1 channel (Multi-Master I2C bus(1)) 10 bits x 24 channels 2 channels 15 bits x 1 (with prescaler) 25 internal and 8 external sources, 4 software sources, 7 levels 4 circuits * Main clock (*) * Sub-clock (*) * On-chip oscillator * PLL frequency synthesizer (*) Equipped with a built-in feedback resistor Main clock oscillation stop, re-oscillation detect function Operating Ambient Temperature Available VCC = 4.2 V to 5.5 V (f(BCLK) = 24 MHZ) (M16C/28B) VCC = 3.0 V to 5.5 V (f(BCLK) = 20 MHZ) (M16C/28, M16C/28B) VCC = 2.7 V to 5.5 V (f(BCLK) = 10 MHZ) (M16C/28, M16C/28B) 16 mA (VCC = 5V, f(BCLK) = 20 MHz) 25 A (f(XCIN) = 32 KHz on RAM) 3.0 A (VCC = 3V, f(XCIN) = 32 KHz, in wait mode) 0.7 A (VCC = 3V, in stop mode) 2.7 V to 5.5 V 100 times (all space) or 1,000 times (Blocks 0 to 5) /10,000 times (Block A, Block B(3)) -20 to 85C/-40 to 85C(3) Package 80-pin plastic mold LQFP, 85-pin plastic mold TFLGA Electrical Characteristics Power consumption Flash Memory Program/erase supply voltage Program and erase endurance NOTES: 1. I2C bus is a trademark of Koninklijke Philips Electronics N. V. 2. IEBus is a trademark of NEC Electronics Corporation. 3. Refer to Table 1.5 to 1.7 for number of program/erase. 4. Use PLL frequency synthesizer to use M16C/28B at f(BCLK) = 24 MHz. Rev. 0.50 Sep.15, 2006 page 2 of 33 1. Overview M16C/28 Group (M16C/28, M16C/28B) Table 1.2 M16C/28 Group (M16C/28, M16C/28) (64-Pin Package) CPU Peripheral Function Item Number of basic instructions Minimum instruction excution time Operation mode Address space Memory capacity I/O Port Multifunction timer Serial I/O A/D converter DMAC Watchdog timer Interrupt Clock generation circuit Electrical Characteristics Oscillation Stop Detect Function Voltage detection circuit Power supply voltage Power consumption Flash Memory Program/erase supply voltage Program and erase endurance Operating Ambient Temperature Package Performance 91 instructions 41.7 ns (f(BCLK) = 24 MHZ, VCC = 4.2 V to 5.5 V) (M16C/28B) 50 ns (f(BCLK) = 20 MHZ, VCC = 3.0V to 5.5V) (M16C/28, M16C/28B) 100 ns (f(BCLK) = 10 MHZ, VCC = 2.7V to 5.5V) (M16C/28, M16C/28B) Single chip mode 1M bytes See Table 1.3 Input/Output : 55 lines TimerA:16 bits x 5 channels, TimerB:16 bits x 3 channels Three-phase Motor Control Timer TimerS (Input Capture/Output Compare) : 16bit base timer x 1 channel (Input/Output x 8 channels ) 2 channels (UART0, UART1) UART, clock synchronous 1 channel (UART2) UART, clock synchronous, I2C bus(1), or IEbus(2) 1 channels (SI/O3, SI/O4) Clock synchronous 1 channel (Multi-Master I2C bus(1)) 10 bits x 13 channels 2 channels 15 bits x 1 (with prescaler) 24 internal and 8 external sources, 4 software sources, 7 levels 4 circuits * Main clock(*) * Sub-clock(*) * On-chip oscillator * PLL frequency synthesizer (*) Equipped with a built-in feedback resistor Main clock oscillation stop, re-oscillation detect function Available VCC = 4.2 V to 5.5 V (f(BCLK) = 24 MHZ) (M16C/28) VCC = 3.0 V to 5.5 V (f(BCLK) = 20 MHZ) (M16C/28, M16C/28B) VCC = 2.7 V to 5.5 V (f(BCLK) = 10 MHZ) (M16C/28, M16C/28B) 16 mA (VCC = 5 V, f(BCLK) = 20 MHz) 25 A (f(XCIN) = 32 KHz on RAM) 3.0 A (VCC = 3 V, f(XCIN) = 32 KHz, in wait mode) 0.7 A (VCC = 3 V, in stop mode) 2.7 V to 5.5 V 100 times (all space) or 1,000 times (Blocks 0 to 5) /10,000 times (Block A, Block B(3)) -20 to 85C/-40 to 85C(3) 64-pin plastic mold LQFP NOTES: 1. I2C bus is a trademark of Koninklijke Philips Electronics N. V. 2. IEBus is a trademark of NEC Electronics Corporation. 3. Refer to Table 1.5 to 1.7 for number of program/erase. 4. Use PLL frequency synthesizer to use M16C/28B at f(BCLK) = 24 MHz. Rev. 0.50 Sep.15, 2006 page 3 of 33 1. Overview M16C/28 Group (M16C/28, M16C/28B) 1.3 Block Diagram Figure 1.1 is a block diagram of the M16C/28 Group (M16C/28, M16C/28B), 80-pin and 85-pin package. Figure 1.2 is a block diagram of the M16C/28 Group (M16C/28, M16C/28B), 64-pin package. 8 I/O Ports Port P0 8 8 Port P1 Port P2 8 Port P3 M16C/60 Series CPU Core Memory R0L R1L USP ISP INTB A0 A1 FB FLG AAAA AAAA AAAA Multiplier NOTES: 1. ROM size depends on MCU type. 2. RAM size depends on MCU type. Figure 1.1 M16C/28 Group (M16C/28, M16C/28B), 80-Pin/85-Pin Block Diagram Rev. 0.50 Sep.15, 2006 page 4 of 33 8 DMAC (2 channels) PC Port P10 Watchdog timer (15 bits) RAM(2) 7 R2 R3 SB Port P9 ROM(1) R0H R1H 8 ) A/D converter (10 bits x 24 channels) 8 XIN-XOUT XCIN-XCOUT On-chip oscillator PLL frequency synthesizer Multi-master I2C bus Timer S Input capture/ Output compare Time measurement : 8 channels Waveform generating : 8 channels ( System clock generator Clock synchronous SI/O (8 bits x 2 channels) 3-phase PWM 8 Output (Timer A) : 5 Input (Timer B) : 3 Port P8 UART/clock synchronous SI/O (8 bits x 3 channels) Port P7 Timer (16 bits) Port P6 Internal Peripheral Functions 1. Overview M16C/28 Group (M16C/28, M16C/28B) 4 I/O Ports Port P0 3 8 Port P1 4 Port P3 Port P2 M16C/60 Series CPU Core R2 R3 USP ISP INTB FLG AAAA AAAA Multiplier NOTES: 1. ROM size depends on MCU type. 2. RAM size depends on MCU type. Figure 1.2 M16C/28 Group (M16C/28, M16C/28B), 64-Pin Block Diagram Rev. 0.50 Sep.15, 2006 page 5 of 33 8 DMAC (2 channels) PC RAM(2) Port P10 A0 A1 FB Watchdog timer (15 bits) ROM(1) SB 4 A/D converter (10 bits x 13 channels) R0L R1L Memory Port P9 R0H R1H 8 ) 8 XIN-XOUT XCIN-XCOUT On-chip oscillator PLL frequency synthesizer Multi-master I2C bus Timer S Input capture/ Output compare Time measurement : 8 channels Waveform generating : 8 channels ( System clock generator Clock synchronous SI/O (8 bits x 1 channel) 3-phase PWM 8 Output (Timer A) : 5 Input (Timer B) : 3 Port P8 UART/Clock synchronous SI/O (8 bits x 3 channels) Port P7 Timer (16 bits) Port P6 Internal Peripheral Functions 1. Overview M16C/28 Group (M16C/28, M16C/28B) 1.4 Product Information Tables 1.3 and 1.4 list the M16C/28 Group product information and Figure 1.3 shows the product numbering system. The specifications are partially different between normal-ver.and T/ V-ver.. Table 1.3 M16C/28 Product List -Normal-ver. Type Number ROM Capacity RAM Capacity M30280F6WG (N) 48 K + 4 K 4K M30280F8WG (N) 64 K + 4 K 4K M30280FAWG (N) 96 K + 4 K 8K M30280F6HP (N) 48 K + 4 K 4K M30280F8HP (N) 64 K + 4 K 4K M30280FAHP (N) 96 K + 4 K 8K M30280FCHP (N ) 128 K + 4 K 12 K M30281F6HP (N ) 48 K + 4 K 4K M30281F8HP (N ) 64 K + 4 K 4K M30281FAHP (N ) 96 K + 4 K 8K M30281FCHP (N ) 128 K + 4 K 12 K M30280M8-XXXHP (N ) 64 K 4K M30280MA-XXXHP (N) 96 K 8K M30280MC-XXXHP (N) 128 K 12 K M30281M8-XXXHP (N) 64 K 4K M30281MA-XXXHP (N) 96 K 8K 128 K 12 K M30281MC-XXXHP (N) As of September, 2006 Package Type Remarks Product Code Flash Memory U3, U5, U7, U9 Mask ROM U3, U5 PTLG0085JB-A (85F0G) PLQP0080KB-A (80P6Q-A) PLQP0064KB-A (64P6Q-A) PLQP0080KB-A (80P6Q-A) PLQP0064KB-A (64P6Q-A) (N): New Table 1.4 M16C/28B Product List -Normal-ver. Type Number As of September, 2006 ROM Capacity RAM Capacity Package Type Remarks Product Code Flash memory U7 M30280FCBHP (D) 128 K + 4 K 12 K PLQP0080KB-A (80P6Q-A) M30281FCBHP (D) 128 K + 4 K 12 K PLQP0064KB-A (64P6Q-A) (D): Under development Rev. 0.50 Sep.15, 2006 page 6 of 33 1. Overview M16C/28 Group (M16C/28, M16C/28B) Type No. M3028 0 FCBHP-U7 Product code Package type: HP : Package WG : Package PLQP0080KB-A(80P6Q-A) PLQP0064KB-A(64P6Q-A) PTLG0085JB-A(85F0G) Version (no): M16C/28 Group Normal-ver. B: M16C/28B Group ROM capacity / RAM capacity (1): 6 : (48K+4K) bytes / 4K bytes 8 : (64K + 4K) bytes / 4K bytes A : (96K + 4K) bytes / 8K bytes C : (128K + 4K) bytes / 12K bytes Memory type: F : Flash memory version M : Mask ROM version Pin count (The value itself has no specific meaning) M16C/28 Group, M16C/28B Group M16C Family NOTE: 1. "+4K bytes" is available only in flash memory ver.. Figure 1.3 Product Numbering System Rev. 0.50 Sep.15, 2006 page 7 of 33 1. Overview M16C/28 Group (M16C/28, M16C/28B) Table 1.5 Product Code (Flash Memory-ver.) - M16C/28 Normal-ver., 64-Pin(1)/80-Pin(1)/85-Pin Package Product Code Internal ROM (User Program Space) Package Program and Erase Endurance U3 U5 Temperature Range 100 Lead free Internal ROM (Data Space) Program and Erase Endurance 100 Temperature Range 0 to 60C 0 to 60C U7 1,000 U9 10,000 Operating Ambient Temperature -40 to 85C -20 to 85C -40 to 85C -40 to 85C -20 to 85C -20 to 85C NOTE: 1. The lead contained products, D3, D5, D7 and D9, are put together with U3, U5, U7 and U9 respectively. Leadfree (Sn-Ag-Cu plating) products can be mounted by both conventional Sn-Pb paste and Lead-free paste. Table 1.6 Product Code (Flash Memory-ver.) - M16C/28B Normal-ver., 64-Pin/85-Pin Package Product Code U7 Internal ROM (User Program Space) Package Program and Erase Endurance Lead-free 1,000 Temperature Range 0 to 60C Internal ROM (Data Space) Program and Erase Endurance 10,000 Temperature Range -40 to 85C Operating Ambient Temperature -40 to 85C Table 1.7 Product Code (Mask ROM ver.) - M16C/28B Normal-ver., 64-Pin/80-Pin/85-Pin Package Product Code U3 Package Lead-free U5 Rev. 0.50 Sep.15, 2006 Operating Ambient Temperature -40 to 85C -20 to 85C page 8 of 33 1. Overview M16C/28 Group (M16C/28, M16C/28B) (1) Flash Memory Version, PTLG0085JB-A (85F0G), Normal-ver. M30280FA B U5 XXXXXXX Type No. M30280FAWG Chip version and product code B : Chip version. The first edition is shown to be blank and continues with A, B, and C. U5 : Product code. (See Table 1.5) Date code seven digits Manufacturing management code (2) Flash Memory Version, PLQP0080KB-A (80P6Q-A), Normal-ver. M16C M30280FAHP A U5 XXXXXXX Type No. M30280FAHP Chip version and product code A : Chip version and product code(1) The first edition is shown to be blank and continues with A, B and C. U5 : Product code. (Table 1.4) Date code seven digits Manufacturing management code (3) Flash Memory Version, PLQP0064KB-A (64P6Q-A), Normal-ver. 30281FA Type No. M30281FAHP Chip version and product code A U5 A : Chip version and product code(1) The first edition is shown to be blank and continues with A, B and C. U5 : Product code. (Table 1.4) XXXXXXX Date code seven digits Manufacturing management code (4) Mask ROM Version, PLQP0080KB-A (80P6Q-A), Normal-ver. M16C M30280MAXXXHP A U5 XXXXXXX Type No. M30280MAHP Chip version and product code XXX : ROM No. A : Chip version and product code(1) The first edition is shown to be blank and continues with A, B and C. U5 : Product code. (Table 1.6) Date code seven digits Manufacturing management code (5) Mask ROM Version, PLQP0064-KB-A (64P6Q-A), Normal-ver. Date code seven digits Manufacturing management code XXXXXXX M30281MA- Type No. M30281MAHP Chip version and product code XXX: ROM No. XXXHP A U5 A : Chip version and product code(1) The first edition is shown to be blank and continues with A, B and C. U5 : Product code. (Table 1.6) NOTES: 1. The following functinos are not available in the first version and version A products. -Delay trigger mode 0 of A/D conversion -Delay trigger mode 1 of A/D conversion Figure 1.4 Marking Diagram-M16C/28 Normal-ver. Rev. 0.50 Sep.15, 2006 page 9 of 33 1. Overview M16C/28 Group (M16C/28, M16C/28B) 1.5 Pin Assignment Figures 1.5 to 1.7 show the pin Assignments (top view). A 10 9 8 7 6 5 4 2 1 C D E F G H J K 61 60 58 5 52 50 47 44 42 38 P06 P07 P11 P14 P17 P21 P24 P27 P61 P31 62 63 59 5 53 51 48 45 43 39 P05 P04 P10 P13 P16 P20 P23 P26 P60 P30 64 65 66 5 P03 P02 P01 P12 67 68 P00 P107 70 71 P105 P104 74 73 P101 P102 77 76 VREF 3 B P100 54 P15 (11) (Vss)(2) 49 46 41 40 P22 P25 P62 P63 69 37 36 35 P106 P32 P33 P34 (11) (Vss)(2) 72 AVss 33 32 P36 P37 31 30 P64 P65 29 28 27 P66 P67 P70 (11) P103 75 34 P35 (Vss)(2) (11) (Vss)(2) 78 79 4 9 AVcc P97 P91 RESET 80 2 5 7 P96 P93 P90 P87/XCIN 11 14 17 26 25 24 Vss P85 P82 P71 P72 P73 12 13 16 19 23 22 XIN Vcc P83 P80 P74 P75 1 3 6 8 10 13 15 18 21 20 P95 P92 CNVss P86/XCOUT XOUT Vcc P84 P81 P76 P77 NOTES : 1. The numbers in each grid (circle) show the pin numbers of the M30280FAHP (80P6Q-A package) 2. Connect grids written as (Vss) to Vss(GND) or leave them open. 3. Set PACR2 to PACR0 bits in the PACR register to "0112" before you input and output it after resetting to each pin. When the PACR register is not set, the input and output function of some pins are disabled. Package: PTLG0085JB-A(85F0G) Figure 1.5 Pin Assignment (Top View) of 85-pin Package Rev. 0.50 Sep.15, 2006 page 10 of 33 1. Overview M16C/28 Group (M16C/28, M16C/28B) Table 1.8 Pin Characteristics for 85-pin Package Pi n No. Control Pin A1 A2 Port Interrupt Pi n Timer Pin Timer S Pin U AR T Pi n Multi-master I2C bus Pin Analog Pin PLQP0080KB-A Pin Number P95 CLK4 AN 2 5 1 P96 SOUT4 AN 2 6 80 A3 AVc c 78 A4 VREF 77 A5 P101 A6 P105 A7 AN 1 KI 1 74 AN 5 70 P00 AN 0 0 67 A8 P03 AN 0 3 64 A9 P05 AN 0 5 62 A10 P06 AN 0 6 61 B1 P92 B2 P93 B3 P97 B4 B5 B6 P104 B7 P107 B8 P02 B9 B1 0 C1 C3 2 AN 2 7 79 P100 AN 0 76 P102 AN 2 73 KI 0 AN 4 71 KI 3 AN 7 68 AN 0 2 65 P04 AN 0 4 63 P07 AN 0 7 60 SIN4 6 P90 TB0IN P91 TB1IN 5 4 AVss C5 C6 3 AN 2 4 CNVss C2 C4 TB2IN 75 AN 3 P103 (1) 72 (11) Vss AN 6 69 P01 AN 0 1 66 C9 P10 AN 2 0 59 C10 P11 P8 6 AN 2 1 58 C7 P106 C8 D1 XCOUT D2 XCIN D3 RESET D4 KI 2 8 P8 7 7 9 (1) (11) Vs s D8 P12 AN 2 2 57 D9 P13 AN 2 3 56 D10 55 P14 E1 XOUT 10 E2 XIN 12 E3 Vss 11 Rev. 0.50 Sep.15, 2006 page 11 of 33 1. Overview M16C/28 Group (M16C/28, M16C/28B) Table 1.8 Pin Characteristics for 85-pin Package (continued) Pin No. Control Pin Port Interrupt Pin Timer Pin E8 P15 INT3 IDV E9 P16 INT4 IDW E10 P17 INT5 IDU Timer S Pin UART Pin Multi-master I2C bus Pin Analog Pin A D TR G PLQP0080KB-A Pin Number 54 53 INPC17 52 F1 Vcc 13 F2 Vcc 13 F3 P85 NMI SD 14 F8 Vss(1) (11) F9 P20 F10 P21 OUTC10 / INPC10 OUTC11 / INPC11 G1 P84 INT2 G2 P8 3 INT1 G3 P82 INT0 ZP SDAMM 51 SCLMM 50 15 16 17 OUTC12 / INPC12 OUTC13 / INPC13 OUTC14 / INPC14 G8 P22 G9 P23 G10 P24 H1 P81 TA4IN / U H2 P80 TA4OUT / U H3 P71 TA0IN H4 P66 49 48 47 18 19 RXD2 / SCL2 / CLK1 RXD1 H5 Vss(1) 26 29 (11) H6 P35 H7 P32 34 SOUT3 OUTC15 / INPC15 OUTC16 / INPC16 OUTC17 / INPC17 37 46 H8 P25 H9 P26 H10 P27 J1 P76 TA3OUT 21 J2 P74 TA2OUT / W 23 J3 P72 TA1OUT / V J4 P67 45 44 CLK2 / RXD1 25 TXD1 RTS1 / CTS1/ CTS0 / CLKS1 28 31 J5 P64 J6 P36 J7 P33 J8 P62 RXD0 41 J9 P60 RTS0 / CTS0 43 J10 P61 CLK0 42 K1 P77 TA3IN 20 K2 P75 TA2IN / W 22 K3 P73 TA1IN / V K4 P70 TA0OUT 33 36 CTS2 / RTS2 / TXD1 TXD2 / SDA2 / RTS1 / CTS1 / CTS0 / CLKS1 24 CLK1 30 27 K5 P65 K6 P37 K7 P34 K8 P63 TXD0 40 K9 P30 CLK3 39 K10 P31 SIN3 38 Rev. 0.50 Sep.15, 2006 32 35 page 12 of 33 1. Overview P61/CLK0 P62/RxD0 P60/CTS0/RTS0 P26/OUTC16/INPC16 P27/OUTC17/INPC17 P25/OUTC15/INPC15 P24/OUTC14/INPC14 P22/OUTC12/INPC12 P23/OUTC13/INPC13 P21/OUTC11/INPC11/SCLMM P17/INT5/INPC17/IDU P20/OUTC10/INPC10/SDAMM P14 P15/INT3/ADTRG/IDV P16/INT4/IDW P12/AN22 P13/AN23 P11/AN21 P07/AN07 P10/AN20 M16C/28 Group (M16C/28, M16C/28B) 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 P06/AN06 P05/AN05 P04/AN04 P03/AN03 61 40 62 39 63 38 64 37 P02/AN02 65 36 P01/AN01 P00/AN00 P107/AN7/KI3 P106/AN6/KI2 P105/AN5/KI1 P104/AN4/KI0 P103/AN3 P102/AN2 P101/AN1 AVSS P100/AN0 VREF AVcc P97/AN27/SIN4 P96/AN26/SOUT4 66 35 67 34 68 33 69 32 70 31 71 30 72 29 73 28 74 27 75 26 76 25 77 24 78 23 79 22 80 3 P93/AN24 P92/TB2IN P91/TB1IN P90/TB0IN CNVss P87/XCIN P86/XCOUT 4 5 6 7 8 P32/SOUT3 P33 P34 P35 P36 P37 P64/CTS1/RTS1/CTS0/CLKS1 P65/CLK1 P66/RxD1 P67/TXD1 P70/TXD2/SDA2/TA0OUT/CTS1/RTS1/CTS0/CLKS1 P71/RXD2/SCL2/TA0IN/CLK1 P72/CLK2/TA1OUT/V/RxD1 P73/CTS2/RTS2/TA1IN/V/TxD1 P74/TA2OUT/W P75/TA2IN/W P76/TA3OUT 9 10 11 12 13 14 15 16 17 18 19 20 RESET XOUT VSS XIN VCC P85/NMI/SD P84/INT2/ZP P83/INT1 P82/INT0 P81/TA4IN/U P80/TA4OUT/U P77/TA3IN 2 P95/AN25/CLK4 21 1 P63/TXD0 P30/CLK3 P31/SIN3 NOTES: 1.Set PACR2 to PACR0 bit in the PACR register to "0112" before you input and output it after resetting to each pin. When the PACR register isn't set up, the input and output function of some of the pins are disabled. Package: PLQP0080KB-A(80P6Q-A) Figure 1.5 Pin Assignment (Top View) of 80-Pin Package Rev. 0.50 Sep.15, 2006 page 13 of 33 1. Overview M16C/28 Group (M16C/28, M16C/28B) Table 1.9 Pin Characteristics for 80-Pin Package Pin No. Control P in Port 1 P95 2 P9 3 Interrupt Pin Timer Pin P9 2 TB2IN P9 1 TB1IN 5 P9 0 TB0IN CNVss XCIN P87 8 XCOUT P86 9 RESET 10 XOUT 11 Vss 12 XIN 13 Vcc 14 P8 5 NMI SD 15 P84 INT2 ZP 16 P83 INT1 17 P82 INT0 18 P81 TA4IN / U 19 P80 TA4OUT / U 20 P7 7 TA3IN 21 P76 TA3OUT 22 P75 TA2IN / W 23 P74 TA2OUT / W 24 P7 3 TA1IN / V CTS2 / RTS2 / TXD1 25 P72 TA1OUT / V CLK2 / RXD1 26 P71 TA0IN RXD2 / SCL2 / CLK1 27 P70 TA0OUT TXD2 / SDA2 / RTS1 / CTS1 / CTS0 / CLKS1 28 P67 TXD1 29 P66 RXD1 30 P65 CLK1 31 P64 RTS1 / CTS1/ CTS0 / CLKS1 32 P37 33 P36 34 P35 35 P34 36 P33 37 P32 SOUT3 38 P31 SIN3 39 P30 CLK3 40 P63 TXD0 Rev. 0.50 Sep.15, 2006 Multi-master I2C bus Pin Analog Pin AN25 AN24 3 7 UART Pin CLK4 4 6 Timer S Pin page 14 of 33 1. Overview M16C/28 Group (M16C/28, M16C/28B) Table 1.9 Pin Characteristics for 80-Pin Package (Continued) P in No. Control Pin Port Interrupt P in Timer Pin Timer S Pin UART Pin 41 P62 RXD0 42 P61 CLK0 Multi-master I2C bus Pin 43 P60 44 P27 OUTC17 / INPC17 45 P26 OUTC16 / INPC16 46 P2 5 OUTC15 / INPC15 47 P2 4 OUTC14 / INPC14 48 P23 OUTC13 / INPC13 49 P22 OUTC12 / INPC12 50 P21 OUTC11 / INPC11 SCLMM OUTC10 / INPC10 SDAMM Analog Pin RTS0 / CTS0 51 P20 52 P17 INT5 IDU 53 P16 INT4 IDW 54 P15 INT3 IDV INPC17 ADTRG 55 P14 56 P1 3 AN23 57 P1 2 AN22 58 P11 AN21 59 P10 AN20 60 P07 AN07 61 P06 AN06 62 P05 AN05 63 P04 AN04 64 P03 AN03 65 P02 AN02 66 P0 1 AN01 67 P0 0 AN00 68 P107 KI3 AN 7 69 P106 KI2 AN 6 70 P105 KI1 AN 5 71 P104 KI0 AN 4 72 P103 AN 3 73 P102 AN 2 74 P101 AN 1 P100 AN 0 75 AVss 76 77 VREF 78 AVcc 79 P97 SIN4 AN27 80 P96 SOUT4 AN26 Rev. 0.50 Sep.15, 2006 page 15 of 33 1. Overview P61/CLK0 P62/RxD0 P63/TxD0 34 33 P60/CTS0/RTS0 36 35 P26/OUTC16/INPC16 P27/OUTC17/INPC17 38 37 P24/OUTC14/INPC14 P25/OUTC15/INPC15 39 P23/OUTC13/INPC13 41 40 P21/OUTC11/INPC11/SCLMM P22/OUTC12/INPC12 42 P20/OUTC10/INPC10/SDAMM 44 43 P16/INT4/IDW P17/INT5/INPC17/IDU 46 45 P03/AN03 P15/INT3/ADTRG/IDV 48 47 M16C/28 Group (M16C/28, M16C/28B) P02/AN02 49 32 P30/CLK3 P01/AN01 50 31 P31/SIN3 P00/AN00 51 30 P32/SOUT3 P107/AN7/KI3 52 29 P33 P106/AN6/KI2 53 28 P64/CTS1/RTS1/CTS0/CLKS1 P77/TA3IN P81/TA4IN/U P80/TA4OUT/U P82/INT0 P83/INT1 16 P76/TA3OUT 17 15 18 64 13 63 14 P93/AN24 P92/TB2IN 12 P75/TA2IN/W 11 19 P85/NMI/SD 62 P84/INT2/ZP P74/TA2OUT/W AVCC 10 P73/CTS2/RTS2/TA1IN/V/TxD1 20 VCC 21 61 9 60 VREF 8 P100/AN0 XIN P72/CLK2/TA1OUT/V/RxD1 VSS P71/RxD2/SCL2/TA0IN/CLK1 22 7 23 59 XOUT 58 AVSS 6 P101/AN1 5 P70/TxD2/SDA2/TA0OUT/RTS1/CTS1/CTS0/CLKS1 RESET 24 P86/XCOUT 57 4 P67/TxD1 P102/AN2 3 25 CNVSS 56 P87/XCIN P66/RxD1 P103/AN3 2 P65/CLK1 26 1 27 55 P90/TB0IN 54 P91/TB1IN P105/AN5/KI1 P104/AN4/KI0 NOTES: 1.Set PACR2 to PACR0 bit in the PACR register to "0102" before you input and output it after resetting to each pin. When the PACR register isn't set up, the input and output function of some of the pins are disabled. Package: PLQP0064KB-A(64P6Q-A) Figure 1.6 Pin Assignment (Top View) of 64-Pin Package Rev. 0.50 Sep.15, 2006 page 16 of 33 1. Overview M16C/28 Group (M16C/28, M16C/28B) Table 1.10 Pin Characteristics for 64-Pin Package Pin N o. Control Pin Port Interrupt Pin Timer Pin 1 P91 TA1IN 2 P9 0 TB0IN 3 CNVss 4 XCIN P87 5 XCOUT P86 6 RESET 7 XOUT 8 Vss 9 XIN 10 Vcc P8 5 NMI SD 12 P84 INT2 ZP 13 P83 INT1 14 P8 2 INT0 15 P8 1 TA4IN / U 11 16 P80 TA4OUT / U 17 P77 TA3IN 18 P7 6 TA3OUT 19 P7 5 TA2IN / W 20 P74 TA2OUT / W Timer S Pin UART Pin 21 P73 TA1IN / V CTS2 / RTS2 / TXD1 22 P72 TA1OUT / V CLK2 / RXD1 23 P71 TA0IN RXD2 / SCL2 / CLK1 24 P70 TA0OUT TXD2 / SDA2 / RTS1 / CTS1 / CTS0 / CLKS1 25 P67 TXD1 26 P66 RXD1 27 P65 28 P64 CLK1 RTS1 / CTS1/ CTS0 / CLKS1 29 P33 30 P32 SOUT3 31 P3 1 SIN3 32 P30 CLK3 33 P63 TXD0 34 P6 2 RXD0 35 P61 CLK0 36 P60 RTS0 / CTS0 37 P27 OUTC17 / INPC17 38 P26 OUTC16 / INPC16 39 P25 OUTC15 / INPC15 40 P24 OUTC14 / INPC14 Rev. 0.50 Sep.15, 2006 page 17 of 33 Mult-master I2C bus Pin Analog Pin 1. Overview M16C/28 Group (M16C/28, M16C/28B) Table 10 Pin Characteristics for 64-Pin Package (Continued) Pin No. Control Pin Port Interrupt Pi n Timer Pin Timer S Pin UART Pin Multi-master I2C bus Pin Analog Pin 41 P23 OUTC13 / INPC13 42 P22 OUTC12 / INPC12 43 P21 OUTC11 / INPC11 SCLMM 44 P20 OUTC10 / INPC10 SDAMM 45 P17 INT5 IDU 46 P16 INT4 IDW 47 P15 INT3 IDV 48 P03 AN03 49 P02 AN02 50 P01 AN01 51 P00 AN00 52 P107 KI3 AN 7 53 P106 KI2 AN 6 54 P105 KI1 AN 5 INPC17 ADTRG 55 P104 KI0 AN 4 56 P103 AN 3 57 P102 AN 2 58 P101 AN 1 P100 AN 0 59 AVss 60 61 VREF 62 AVcc 63 P93 64 P92 Rev. 0.50 Sep.15, 2006 AN24 TB2IN page 18 of 33 1. Overview M16C/28 Group (M16C/28, M16C/28B) 1.6 Pin Description Table 1.10 Pin Description (64-Pin, 80-Pin and 85-Pin Packages) Classification Symbol Power Supply VCC, VSS Analog Power AVCC Supply AVSS I/O Type Function I Apply 2.7 to 5.5V to the Vcc pin. Apply 0V to the Vss pin. I Supplies power to the A/D converter. Connect the AVCC pin to VCC and the AVSS pin to VSS. ____________ Reset Input CNVSS RESET Main Clock ___________ CNVSS I I The MCU is in a reset state when "L" is applied to the RESET pin Connect the CNVSS pin to VSS. XIN I I/O pins for the main clock oscillation circuit. Connect a ceramic resonator Input or crystal oscillator between XIN and XOUT. To apply external clock, apply Main Clock O it to XIN and leave XOUT open. If XIN is not used (for external oscillator or I I/O pins for the sub clock oscillation circuit. Connect a crystal oscillator O I between XCIN and XCOUT. ______ ________ Input pins for the INT interrupt. INT2 can be used for Timer A Z-phase I function. _______ _______ Input pin for the NMI interrupt. NMI cannot be used as I/O port while the three- XOUT Output external clock) connect XIN pin to VCC and leave XOUT open. Sub Clock Input XCIN Sub Clock Output XCOUT ______ ________ ________ INT0 to INT5 INT Interrupt Input _______ _______ NMI Interrupt Input NMI _______ phase motor control is enabled. Apply a stable "H" to NMI after setting it's direction register to "0" when the three-phase motor control is enabled. _____ _____ Key Input Interrupt KI0 to KI3 TA0OUT to Timer A I I/O Input pins for the key input interrupt I/O pins for the timer A0 to A4 TA4OUT TA0IN to I Input pins for the timer A0 to A4 TA4IN ZP I I Input pin for Z-phase Input pins for the timer B0 to B2 Timer B TB0IN to TB2IN Three-phase U, U, V, V, ___ W, W O Output pins for the three-phase motor control timer IDU, IDW, _____ IDV, SD I/O Input and output pins for the three-phase motor control timer CTS0 to CTS2 _________ _________ RTS0 to RTS2 I O Input pins for data transmission control CLK0 to CLK3 RxD0 to RxD2 I/O I TxD0 to TxD2 CLKS1 O O SDA2 SCL2 I/O Output pin for transfer clock Inputs and outputs serial data SDAMM SCLMM I/O Inputs and outputs the transfer clock Inputs and outputs serial data VREF I Inputs and outputs the transfer clock Applies reference voltage to the A/D converter I Analog input pins for the A/D converter ___ Motor Control Timer Output _________ Serial I/O I2C Mode Multi-master I2C bus Reference ___ _________ Voltage Input A/D Converter AN0 to AN7 AN00 to AN03 AN24 ___________ ADTRG I : Input Inputs serial data Outputs serial data Input pin for an external A/D trigger O : Output Rev. 0.50 Sep.15, 2006 Output pins for data reception control Inputs and outputs the transfer clock I/O : Input and output page 19 of 33 1. Overview M16C/28 Group (M16C/28, M16C/28B) Table 1.10 Pin Description (64-Pin, 80-Pin and 85-Pin Packages) (Continued) Classification Timer S Symbol I/O Type Function INPC10 to INPC17 I Input pins for the time measurement function Output pins for the waveform generating function OUTC10 to OUTC17 O I/O Ports P00 to P03 I/O P15 to P17 P20 to P27 I/O ports for CMOS. Each port can be programmed for input or output under the control of the direction register. An input port can be set, by program, for a pull-up resistor available or for no pull-up resister available in 4-bit units P30 to P33 P60 to P67 P70 to P77 P80 to P87 P100 to P107 P90 to P93 I : Input O : Output Rev. 0.50 Sep.15, 2006 I/O I/O ports having equivalent functions to P0 I/O : Input and output page 20 of 33 1. Overview M16C/28 Group (M16C/28, M16C/28B) Table 1.10 Pin Description (80-Pin and 85-Pin Packages only) (Continued) Classification Serial I/O Symbol CLK4 SIN4 SOUT4 A/D Converter AN04 to AN07 I/O Type Function I/O Inputs and outputs the transfer clock I O Inputs serial data Outputs serial data I Analog input pins for the A/D converter AN20 to AN23 AN25 to AN27 I/O Ports P04 to P07 P10 to P14 P34 to P37 P95 to P97 I : Input O : Output Rev. 0.50 Sep.15, 2006 I/O I/O ports for CMOS. Each port can be programmed for input or output under the control of the direction register. An input port can be set, by program, for a pullup resistor available or for no pull-up resister available in 4-bit units I/O I/O ports having equivalent functions to P0 I/O : Input and output page 21 of 33 2. Central Processing Unit(CPU) M16C/28 Group (M16C/28, M16C/28B) 2. Central Processing Unit (CPU) Figure 2.1 shows the CPU registers. The register bank is comprised of 7 registers (R0, R1, R2, R3, A0, A1 and FB) out of 13 CPU registers. Two sets of register banks are provided. b31 b15 b8 b7 b0 R2 R0H(R0's high bits) R0L(R0's low bits) R3 R1H(R1's high bits) R1L(R1's low bits) R2 Data registers (1) R3 A0 b19 (1) A1 Address registers FB Frame base registers b15 (1) b0 INTBH INTBL Interrupt table register The upper 4 bits of INTB are INTBH and the lower 16 bits of INTB are INTBL. b19 b0 PC Program counter b15 b0 US P User stack pointer IS P Interrupt stack pointer SB Static base register b15 b0 FL G b15 b8 b7 b Flag register b0 Carry flag Debug flag Zero flag Sign flag Register bank select flag Overflow flag Interrupt enable flag Stack pointer select flag Reserved space Processor interrupt priority level Reserved space NOTES: 1. The register bank is comprised of these registers. Two sets of register banks are provided. Figure 2.1 Central Processing Unit Register 2.1 Data Registers (R0, R1, R2 and R3) The R0, R1, R2 and R3 registers are 16 bit registers for transfer and arithmetic/logic operations. The R0 and R1 registers can be split into high-order bits(R0H, R1H) and low-order bits (R0L, R1L) to be used seperately as 8-bit data registers. Conversely, R2 and R0 can be combined with R2 to be used as a 32-bit data register (R2R0). The same applies to R1 and R2. 2.2 Address Registers (A0 and A1) The register A0 consists of 16 bits, and is used for address register indirect addressing and address register relative addressing. They also are used for transfers and arithmetic/logic operations. A1 is the same as A0. In some instructions, registers A1 and A0 can be combined for use as a 32-bit address register (A1A0). Rev. 0.50 Sep.15, 2006 page 22 of 33 M16C/28 Group (M16C/28, M16C/28B) 2. Central Processing Unit(CPU) 2.3 Frame Base Register (FB) FB is configured with 16 bits, and is used for FB relative addressing. 2.4 Interrupt Table Register (INTB) INTB is configured with 20 bits, indicating the start address of an interrupt vector table. 2.5 Program Counter (PC) PC is configured with 20 bits, indicating the address of an instruction to be executed. 2.6 User Stack Pointer (USP) and Interrupt Stack Pointer (ISP) Stack pointer (SP) comes in two types: USP and ISP, each configured with 16 bits. Your desired type of stack pointer (USP or ISP) can be selected by the U flag of FLG. 2.7 Static Base Register (SB) SB is configured with 16 bits, and is used for SB relative addressing. 2.8 Flag Register (FLG) FLG consists of 11 bits, indicating the CPU status. 2.8.1 Carry Flag (C Flag) This flag retains a carry, borrow, or shift-out bit that has occurred in the arithmetic/logic unit. 2.8.2 Debug Flag (D Flag) The D flag is used exclusively for debugging purpose. During normal use, it must be set to 0. 2.8.3 Zero Flag (Z Flag) This flag is set to 1 when an arithmetic operation resulted in 0; otherwise, it is 0. 2.8.4 Sign Flag (S Flag) This flag is set to 1 when an arithmetic operation resulted in a negative value; otherwise, it is 0. 2.8.5 Register Bank Select Flag (B Flag) Register bank 0 is selected when this flag is 0 ; register bank 1 is selected when this flag is 1. 2.8.6 Overflow Flag (O Flag) This flag is set to 1 when the operation resulted in an overflow; otherwise, it is 0. 2.8.7 Interrupt Enable Flag (I Flag) This flag enables a maskable interrupt. Maskable interrupts are disabled when the I flag is 0, and are enabled when the I flag is 1. The I flag is cleared to 0 when the interrupt request is accepted. 2.8.8 Stack Pointer Select Flag (U Flag) ISP is selected when the U flag is 0; USP is selected when the U flag is 1. The U flag is cleared to 0 when a hardware interrupt request is accepted or an INT instruction for software interrupt Nos. 0 to 31 is executed. 2.8.9 Processor Interrupt Priority Level (IPL) IPL is configured with three bits, for specification of up to eight processor interrupt priority levels from level 0 to level 7. If a requested interrupt has priority greater than IPL, the interrupt is enabled. 2.8.10 Reserved Area When write to this bit, write 0. When read, its content is indeterminate. Rev. 0.50 Sep.15, 2006 page 23 of 33 3. Memory M16C/28 Group (M16C/28, M16C/28B) 3. Memory Figure 3.1 is a memory map of the M16C/28 Group (M16C/28, M16C/28B). M16C/28 Group provides 1Mbyte address space from addresses 0000016 to FFFFF16. The internal ROM is allocated lower addresses beginning with address FFFFF16. For example, 64 Kbytes internal ROM is allocated addresses F000016 to FFFFF16. Two 2-Kbyte internal ROM areas, block A and block B, are available in the flash memory version. The blocks are allocated addresses F00016 to FFFF16. The fixed interrupt vector tables are allocated addresses FFFDC16 to FFFFF16. It stores the starting address of each interrupt routine. See the section on interrupts for details. The internal RAM is allocated higher addresses beginning with address 0040016. For example, 4-Kbytes internal RAM is allocated addresses 0040016 to 013FF16. Besides storing data, it becomes stacks when the subroutine is called or an interrupt is acknowledged. SFR, consisting of control registers for peripheral functions such as I/O port, A/D converter, serial I/O, timers is allocated addresses 0000016 to 003FF16. All blank spaces within SFR are reserved and cannot be accessed by users. The special page vector table is allocated to the addresses FFE0016 to FFFDB16. This vector is used by the JMPS or JSRS instruction. For details, refer to the M16C/60 and M16C/20 Series Software Manual. Internal RAM area 0000016 SFR Area Internal ROM area Memory size YYYYY16 013FF16 48K bytes F400016 6K bytes 01AFF16 64K bytes F000016 8K bytes 023FF16 96K bytes E800016 12K bytes 033FF16 128K bytes E000016 Memory size XXXXX16 4K bytes 0040016 Internal RAM Area FFE0016 XXXXX16 RESERVED 0F00016 Special Page Vector Table Internal ROM Area (data space)(1) 0FFFF16 FFFDC16 Undefined Instruction FFFFF16 Overflow BRK Instruction Address Match Single Step Watchdog Timer DBC NMI Reset RESERVED YYYYY16 Internal ROM Area (program space) FFFFF16 NOTES: 1. The block A (2K bytes) and block B (2K bytes) are shown (only flash memory). 2. Do not write to the internal ROM area in Mask ROM ver.. Figure 3.1 Memory Map Rev. 0.50 Sep.15, 2006 page 24 of 33 M16C/28 Group (M16C/28, M16C/28B) 4. Special Function Register (SFR) 4. Special Function Register (SFR) SFR (Special Function Register) is the control register of peripheral functions. Tables 4.1 to 4.7 list the SFR information. Table 4.1 SFR Information(1)(1) Address Register Symbol After Reset 000016 000116 000216 000316 000416 000516 000616 000716 Processor mode register 0 Processor mode register 1 System clock control register 0 System clock control register 1 PM0 PM1 CM0 CM1 0016 000010002 010010002 001000002 000816 000916 000A16 Address match interrupt enable register Protect register AIER PRCR XXXXXX002 XX0000002 CM2 0X0000102 Watchdog timer start register Watchdog timer control register Address match interrupt register 0 WDTS WDC RMAD0 XX16 00XXXXXX2 0016 0016 X016 Address match interrupt register 1 RMAD1 0016 0016 X016 000B16 000C16 Oscillation stop detection register (2) 000D16 000E16 000F16 001016 001116 001216 001316 001416 001516 001616 001716 001816 001916 001A16 Voltage detection register 1 (3) Voltage detection register 2 (3) VCR1 VCR2 000010002 0016 PLL control register 0 PLC0 0001X0102 Processor mode register 2 Low voltage detection interrupt register DMA0 source pointer PM2 D4INT SAR0 XXX000002 0016 XX16 XX16 XX16 DMA0 destination pointer DAR0 XX16 XX16 XX16 DMA0 transfer counter TCR0 XX16 XX16 DMA0 control register DM0CON DMA1 source pointer SAR1 XX16 XX16 XX16 DMA1 destination pointer DAR1 XX16 XX16 XX16 DMA1 transfer counter TCR1 XX16 XX16 DMA1 control register DM1CON 001B16 001C16 001D16 001E16 001F16 002016 002116 002216 002316 002416 002516 002616 002716 002816 002916 002A16 002B16 002C16 00000X002 002D16 002E16 002F16 003016 003116 003216 003316 003416 003516 003616 003716 003816 003916 003A16 003B16 003C16 003D16 003E16 003F16 NOTES: 1.The blank spaces are reserved. No access is allowed. 2. The CM20, CM21, and CM27 bits do not change at oscillation stop detection reset. 3. This register does not change at software reset, watchdog timer reset and oscillation stop detection reset. X : Undefined Rev. 0.50 Sep.15, 2006 page 25 of 33 00000X002 M16C/28 Group (M16C/28, M16C/28B) 4. Special Function Register (SFR) Table 4.2 SFR Information(2)(1) Register Address Symbol After Reset 004016 004116 004216 004316 004416 004516 004616 004716 004816 004916 004A16 004B16 004C16 004D16 004E16 004F16 005016 005116 005216 005316 005416 005516 005616 005716 005816 005916 005A16 005B16 005C16 005D16 005E16 005F16 INT3 interrupt control register IC/OC 0 interrupt control register IC/OC 1 interrupt control register, I2C bus interface interrupt control register IC/OC base timer interrupt control register, SCLSDA interrupt control register SI/O4 interrupt control register, INT5 interrupt control register SI/O3 interrupt control register, INT4 interrupt control register UART2 Bus collision detection interrupt control register DMA0 interrupt control register DMA1 interrupt control register Key input interrupt control register A/D conversion interrupt control register UART2 transmit interrupt control register UART2 receive interrupt control register UART0 transmit interrupt control register UART0 receive interrupt control register UART1 transmit interrupt control register UART1 receive interrupt control register Timer A0 interrupt control register Timer A1 interrupt control register Timer A2 interrupt control register Timer A3 interrupt control register Timer A4 interrupt control register Timer B0 interrupt control register Timer B1 interrupt control register Timer B2 interrupt control register INT0 interrupt control register INT1 interrupt control register INT2 interrupt control register 006016 006116 006216 006316 006416 006516 006616 006716 006816 006916 006A16 006B16 006C16 006D16 006E16 006F16 007016 007116 007216 007316 007416 007516 007616 007716 007816 007916 007A16 007B16 007C16 007D16 007E16 007F16 Note 1: The blank spaces are reserved. No access is allowed. X : Undefined Rev. 0.50 Sep.15, 2006 page 26 of 33 INT3IC ICOC0IC ICOC1IC, IICIC BTIC, SCLDAIC S4IC, INT5IC S3IC, INT4IC BCNIC DM0IC DM1IC KUPIC ADIC S2TIC S2RIC S0TIC S0RIC S1TIC S1RIC TA0IC TA1IC TA2IC TA3IC TA4IC TB0IC TB1IC TB2IC INT0IC INT1IC INT2IC XX00X0002 XXXXX0002 XXXXX0002 XXXXX0002 XX00X0002 XX00X0002 XXXXX0002 XXXXX0002 XXXXX0002 XXXXX0002 XXXXX0002 XXXXX0002 XXXXX0002 XXXXX0002 XXXXX0002 XXXXX0002 XXXXX0002 XXXXX0002 XXXXX0002 XXXXX0002 XXXXX0002 XXXXX0002 XXXXX0002 XXXXX0002 XXXXX0002 XX00X0002 XX00X0002 XX00X0002 M16C/28 Group (M16C/28, M16C/28B) 4. Special Function Register (SFR) Table 4.3 SFR Information(3)(1) Register Address Symbol After Reset ~ ~ ~ 01B016 01B116 01B216 01B316 Flash memory control register 4 (2) FMR4 010000002 Flash memory control register 1 (2) FMR1 000XXX0X2 Flash memory control register 0 (2) FMR0 000000012 01B416 01B516 01B616 01B716 01B816 01B916 ~ ~ ~ 021016 Low-power Consumption Control 0 LPCC0 X00000012 021116 021216 021316 021416 021516 021616 021716 021816 021916 ~ ~ ~ 025016 025116 025216 025316 025416 025516 025616 025716 025816 025916 025A16 025B16 025F16 On-chip oscillator control register Pin assignment control register Peripheral clock select register Low-power Consumption Control 1 02E016 I2C0 025C16 025D16 025E16 ROCR PACR PCLKR LPCC1 X00001012 0016 000000112 0016 ~ ~ ~ data shift register S00 XX16 02E116 02E216 02E316 02E416 02E516 02E616 02E716 02E816 I2C0 address register I2C0 control register 0 I2C0 clock control register I2C0 start/stop condition control register I2C0 control register 1 I2C0 control register 2 I2C0 status register S0D0 S1D0 S20 S2D0 S3D0 S4D0 S10 0016 0016 0016 000110102 001100002 0016 0001000X2 02E916 02EA16 ~ ~ ~ 02FE16 02FF16 Note 1:The blank spaces are reserved. No access is allowed. Note 2:This register is included in the flash memory version. X : Undefined Rev. 0.50 Sep.15, 2006 page 27 of 33 M16C/28 Group (M16C/28, M16C/28B) 4. Special Function Register (SFR) Table 4.4 SFR Information(4)(1) TM, WG register 0 Register Symbol G1TM0, G1PO0 Divider register G1DV After Reset XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 0X00XX002 0X00XX002 0X00XX002 0X00XX002 0X00XX002 0X00XX002 0X00XX002 0X00XX002 0016 0016 0016 0016 0016 0016 0016 0016 XX16 XX16 0016 0016 0016 0016 0016 0016 XX16 XX16 0016 TM, WG register 1 G1TM1, G1PO1 TM, WG register 2 G1TM2, G1PO2 TM, WG register 3 G1TM3, G1PO3 TM, WG register 4 G1TM4, G1PO4 TM, WG register 5 G1TM5, G1PO5 TM, WG register 6 G1TM6, G1PO6 TM, WG register 7 G1TM7, G1PO7 Interrupt request register Interrupt enable register 0 Interrupt enable register 1 G1IR G1IE0 G1IE1 XX16 0016 0016 NDDR P17DDR FF16 FF16 Address 030016 030116 030216 030316 030416 030516 030616 030716 030816 030916 030A16 030B16 030C16 030D16 030E16 030F16 031016 031116 031216 031316 031416 031516 031616 031716 031816 031916 031A16 031B16 031C16 031D16 031E16 031F16 032016 WG control register 0 WG control register 1 WG control register 2 WG control register 3 WG control register 4 WG control register 5 WG control register 6 WG control register 7 TM control register 0 TM control register 1 TM control register 2 TM control register 3 TM control register 4 TM control register 5 TM control register 6 TM control register 7 Base timer register G1POCR0 G1POCR1 G1POCR2 G1POCR3 G1POCR4 G1POCR5 G1POCR6 G1POCR7 G1TMCR0 G1TMCR1 G1TMCR2 G1TMCR3 G1TMCR4 G1TMCR5 G1TMCR6 G1TMCR7 G1BT 032116 032216 032316 032416 032516 032616 032716 032816 Base timer control register 0 Base timer control register 1 TM prescale register 6 TM prescale register 7 Function enable register Function select register Base timer reset register G1BCR0 G1BCR1 G1TPR6 G1TPR7 G1FE G1FS G1BTRR 032916 032A16 032B16 032C16 032D16 032E16 032F16 033016 033116 033216 033316 033416 033516 033616 033716 033816 033916 033A16 033B16 033C16 033D16 033E16 033F16 NMI digital debounce register P17 digital debounce register Note 1:The blank spaces are reserved. No access is allowed. X : Undefined Rev. 0.50 Sep.15, 2006 page 28 of 33 M16C/28 Group (M16C/28, M16C/28B) 4. Special Function Register (SFR) Table 4.5 SFR Information(5)(1) Register Address Symbol After Reset 034016 034116 034216 Timer A1-1 register TA11 Timer A2-1 register TA21 Timer A4-1 register TA41 Three-phase PWM control register 0 Three-phase PWM control register 1 Three-phase output buffer register 0 Three-phase output buffer register 1 Dead time timer Timer B2 interrupt occurrence frequency set counter Position-data-retain function control register INVC0 INVC1 IDB0 IDB1 DTT ICTB2 PDRF XX16 XX16 XX16 XX16 XX16 XX16 0016 0016 001111112 001111112 XX16 XX16 XXXX00002 Interrupt request cause select register 2 Interrupt request cause select register SI/O3 transmit/receive register IFSR2A IFSR S3TRR 00XXXXX02(2) 0016 XX16 SI/O3 control register SI/O3 bit rate generator SI/O4 transmit/receive register S3C S3BRG S4TRR 010000002 XX16 XX16 SI/O4 control register SI/O4 bit rate generator S4C S4BRG 010000002 XX16 U2SMR4 U2SMR3 U2SMR2 U2SMR U2MR U2BRG U2TB 0016 000X0X0X2 X00000002 X00000002 0016 XX16 XX16 XX16 000010002 000000102 XX16 XX16 034316 034416 034516 034616 034716 034816 034916 034A16 034B16 034C16 034D16 034E16 034F16 035016 035116 035216 035316 035416 035516 035616 035716 035816 035916 035A16 035B16 035C16 035D16 035E16 035F16 036016 036116 036216 036316 036416 036516 036616 036716 036816 036916 036A16 036B16 036C16 036D16 036E16 036F16 037016 037116 037216 037316 037416 037516 037616 037716 037816 037916 037A16 UART2 special mode register 4 UART2 special mode register 3 UART2 special mode register 2 UART2 special mode register UART2 transmit/receive mode register UART2 bit rate generator UART2 transmit buffer register 037B16 037C16 037D16 037E16 UART2 transmit/receive control register 0 UART2 transmit/receive control register 1 UART2 receive buffer register 037F16 Note 1: The blank spaces are reserved. No access is allowed. Note 2: Write 1 to bit 0 after reset. X : Undefined Rev. 0.50 Sep.15, 2006 page 29 of 33 U2C0 U2C1 U2RB M16C/28 Group (M16C/28, M16C/28B) 4. Special Function Register (SFR) Table 4.6 SFR Information(6)(1) Register Address 038016 038116 038216 038316 038416 Count start flag Clock prescaler reset flag One-shot start flag Trigger select register Up-down flag Symbol TABSR CPSRF ONSF TRGSR UDF After Reset 0016 0XXXXXXX2 0016 0016 0016 038516 038616 Timer A0 register TA0 Timer A1 register TA1 Timer A2 register TA2 Timer A3 register TA3 Timer A4 register TA4 Timer B0 register TB0 Timer B1 register TB1 Timer B2 register TB2 038716 038816 038916 038A16 038B16 038C16 038D16 038E16 038F16 039016 039116 039216 039316 039416 039516 039616 039716 039816 039916 039A16 039B16 039C16 039D16 039E16 Timer A0 mode register Timer A1 mode register Timer A2 mode register Timer A3 mode register Timer A4 mode register Timer B0 mode register Timer B1 mode register Timer B2 mode register Timer B2 special mode register TA0MR TA1MR TA2MR TA3MR TA4MR TB0MR TB1MR TB2MR TB2SC UART0 transmit/receive mode register UART0 bit rate generator UART0 transmit buffer register U0MR U0BRG U0TB XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 0016 0016 0016 0016 0016 00XX00002 00XX00002 00XX00002 X00000002 039F16 03A016 03A116 03A216 UART1 transmit/receive control register 0 UART1 transmit/receive control register 1 UART1 receive buffer register U1C0 U1C1 U1RB UART transmit/receive control register 2 UCON 0016 XX16 XX16 XX16 000010002 000000102 XX16 XX16 0016 XX16 XX16 XX16 000010002 000000102 XX16 XX16 X00000002 DMA0 request cause select register DM0SL 0016 DMA1 request cause select register DM1SL 0016 03A316 03A416 03A516 03A616 UART0 transmit/receive control register 0 UART0 transmit/receive control register 1 UART0 receive buffer register U0C0 U0C1 U0RB 03A716 03A816 03A916 03AA16 UART1 transmit/receive mode register UART1 bit rate generator UART1 transmit buffer register U1MR U1BRG U1TB 03AB16 03AC16 03AD16 03AE16 03AF16 03B016 03B116 03B216 03B316 03B416 03B516 03B616 03B716 03B816 03B916 03BA16 03BB16 03BC16 03BD16 03BE16 03BF16 Note 1:The blank spaces are reserved. No access is allowed. X : Undefined Rev. 0.50 Sep.15, 2006 page 30 of 33 M16C/28 Group (M16C/28, M16C/28B) 4. Special Function Register (SFR) Table 4.7 SFR Information(7)(1) Address 03C016 A/D register 0 Register Symbol AD0 A/D register 1 AD1 A/D register 2 AD2 A/D register 3 AD3 A/D register 4 AD4 A/D register 5 AD5 A/D register 6 AD6 A/D register 7 AD7 03C116 03C216 03C316 03C416 03C516 03C616 03C716 03C816 03C916 03CA16 03CB16 03CC16 03CD16 03CE16 03CF16 After Reset XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 03D016 03D116 03D216 03D316 03D416 A/D trigger control register A/D convert status register 0 A/D control register 2 ADTRGCON ADSTAT0 ADCON2 0016 00000X002 0016 ADCON0 ADCON1 00000XXX2 0016 03D516 03D616 03D716 A/D control register 0 A/D control register 1 03D816 03D916 03DA16 03DB16 03DC16 03DD16 03DE16 03DF16 03E016 03E116 03E216 03E316 03E416 03E516 03E616 03E716 Port P0 register Port P1 register Port P0 direction register Port P1 direction register Port P2 register Port P3 register Port P2 direction register Port P3 direction register P0 P1 PD0 PD1 P2 P3 PD2 PD3 XX16 XX16 0016 0016 XX16 XX16 0016 0016 Port P6 register Port P7 register Port P6 direction register Port P7 direction register Port P8 register Port P9 register Port P8 direction register Port P9 direction register Port P10 register P6 P7 PD6 PD7 P8 P9 PD8 PD9 P10 XX16 XX16 0016 0016 XX16 XX16 0016 000X00002 XX16 Port P10 direction register PD10 0016 PUR0 PUR1 PUR2 PCR 0016 0016 0016 0016 03E816 03E916 03EA16 03EB16 03EC16 03ED16 03EE16 03EF16 03F016 03F116 03F216 03F316 03F416 03F516 03F616 03F716 03F816 03F916 03FA16 03FB16 Pull-up control register 0 Pull-up control register 1 03FE16 Pull-up control register 2 03FF16 Port control register Note 1:The blank spaces are reserved. No access is allowed. 03FC16 03FD16 X : Undefined Rev. 0.50 Sep.15, 2006 page 31 of 33 Appendix 1. Package Dimensions M16C/28 Group (M16C/28, M16C/28B) Appendix 1. Package Dimensions JEITA Package Code P-LQFP64-10x10-0.50 RENESAS Code PLQP0064KB-A Previous Code 64P6Q-A / FP-64K / FP-64KV MASS[Typ.] 0.3g HD *1 D NOTE) 1. *2" 2. INCLUDE TRIM OFFSET. c1 Reference Symbol c E *2 HE p D E A HD ZE Terminal cross section E A A1 Z p b1 c c1 c A1 A A2 F e x y ZD ZE L L1 L L1 Detail F JEITA Package Code P-LQFP80-12x12-0.50 RENESAS Code PLQP0080KB-A Previous Code 80P6Q-A Min Nom Max 9.9 10.0 10.1 9.9 10.0 10.1 11.8 12.0 12.2 11.8 12.0 1.7 0.05 0.1 0.15 0.15 0.20 0.18 0.09 0.145 0.20 0.125 0 8 0.5 0.08 0.08 1.25 1.25 0.35 0.5 0.65 1.0 MASS[Typ.] 0.5g HD *1 D 41 NOTE) 1. DIMENSIONS "*1" AND "*2" 0 2. DIMENSION "*3" DOES NOT INCLUDE TRIM OFFSET. E *2 HE c1 1 Reference Dimension in Millimeters Symbol Terminal cross section ZE D E A HD E 20 A1 F c A2 A1 A p L L1 Detail F Rev. 0.50 Sep.15, 2006 page 32 of 33 b1 c c1 e x y ZD ZE L L1 Min Nom Max 11.9 12.0 12.1 11.9 12.0 12.1 1.4 13.8 14.0 14.2 13.8 14.0 14.2 1.7 0.1 0.2 0 0.15 0.20 0.25 0.18 0.09 0.145 0.20 0.125 0 10 0.5 0.08 0.08 1.25 1.25 0.3 0.5 0.7 1.0 Appendix 1. Package Dimensions M16C/28 Group (M16C/28, M16C/28B) JEITA Package Code P-TFLGA85-7x7-0.65 RENESAS Code PTLG0085JB-A Previous Code 85F0G MASS[Typ.] 0.1g b1 D S AB B w S A w AB A A e K J H G B E F E D C B A y S x4 1 2 3 Rev. 0.50 Sep.15, 2006 page 33 of 33 S 4 5 6 7 8 9 10 Reference Symbol Index mark (Laser mark) Index mark D E v w A e b b1 x y Dimension in Millimeters Min Nom Max 7.0 7.0 0.15 0.20 1.05 0.65 0.31 0.35 0.39 0.39 0.43 0.47 0.08 0.10 REVISION HISTORY Rev. M16C/28 Group (M16C/28, M16C/28B) Shortsheet Date Description Summary Page 0.50 09/15/06 - First edition A-1 Sales Strategic Planning Div. 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