Semiconductor Components Industries, LLC, 2001
July, 2001 – Rev. 10 1Publication Order Number:
SN74LS640/D
SN74LS640, SN74LS641,
SN74LS642, SN74LS645
Octal Bus Transceivers
These octal bus transceivers are designed for asynchronous
two-way communication between data buses. Control function
implementation minimizes external timing requirements. These
circuits allow data transmission from the A bus to B or from the B bus
to A bus depending upon the logic level of the direction control (DIR)
input. Enable input (G) can disable the device so that the buses are
effectively isolated.
DEVICE OUTPUT LOGIC
LS640 3-State Inverting
LS641 Open-Collector True
LS642 Open-Collector Inverting
LS645 3-State True
FUNCTION TABLE
CONTROL
INPUTS
OPERATION
INPUTS
LS640
LS641
G DIR
LS640
LS642
LS641
LS645
L L B data to A bus B data to A bus
L H A data to B bus A data to B bus
H X Isolation Isolation
H = HIGH Level, L = LOW Level, X = Irrelevant
GUARANTEED OPERATING RANGES (SN74LS640, SN74LS645)
Symbol Parameter Min Typ Max Unit
VCC Supply Voltage 4.75 5.0 5.25 V
TAOperating Ambient
Temperature Range 0 25 70 °C
IOH Output Current – High –3.0 mA
–15 mA
IOL Output Current – Low 24 mA
GUARANTEED OPERATING RANGES (SN74LS641, SN74LS642)
Symbol Parameter Min Typ Max Unit
VCC Supply Voltage 4.75 5.0 5.25 V
TAOperating Ambient
Temperature Range 0 25 70 °C
VOH Output Voltage – High 5.5 V
IOL Output Current – Low 24 mA
LOW
POWER
SCHOTTKY
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PDIP–20
N SUFFIX
CASE 738
20 1
20
1
x = 0, 1, 2, or 5
y = 0, 1, or 2
A = Assembly Location
WL = Wafer Lot
Y, YY= Year
WW = Work Week
SN74LS64xN
AWLYYWW
MARKING
DIAGRAMS
LS64y
AWLYYWW
SOIC–20
DW SUFFIX
CASE 751D
1
1
20 1
SOEIAJ–20
M SUFFIX
CASE 967
74LS64y
AWLYWW
1
See detailed ordering and shipping information in the package
dimensions section on page 5 of this data sheet.
ORDERING INFORMATION
1
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2
CONNECTION DIAGRAMS DIP (TOP VIEW)
18 17 16 15 14 13
1234 567
20 19
8
VCC
DIR
B1 B2 B3 B5B4 B6
A1 A2 A3 A4 A5 A6 A7
910
A8 GND
12 11
B7 B8
18 17 16 15 14 13
123 4 567
20 19
8
VCC
DIR
B1 B2 B3 B5B4 B6
A1 A2 A3 A4 A5 A6 A7
910
A8 GND
12 11
B7 B8
Figure 1. SN74LS640
SN74LS642 Figure 2. SN74LS641
SN74LS645
ENABLE
G
ENABLE
G
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3
SN74LS640 •SN74LS645
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
Limits
Symbol Parameter Min Typ Max Unit Test Conditions
VIH Input HIGH Voltage 2.0 V Guaranteed Input HIGH Voltage for
All Inputs
VIL Input LOW Voltage 0.6 VGuaranteed Input LOW Voltage for
All Inputs
VIK Input Clamp Diode Voltage –0.65 –1.5 V VCC = MIN, IIN = –18 mA
V
Out
p
ut HIGH Voltage
2.4 3.4 V VCC = MIN, IOH = 3.0 mA
VOH Output HIGH Voltage 2.0 V VCC = MIN, IOH = MAX
V
Out
p
ut LOW Voltage
0.25 0.4 V IOL = 12 mA VCC = VCC MIN,
V V or V
VOL Output LOW Voltage 0.35 0.5 V IOL = 24 mA VIN = VIL or VIH
per Truth Table
IOZH Output Off Current HIGH 20 µA VCC = MAX, VOUT = 2.7 V
IOZL Output Off Current LOW –400 µA VCC = MAX, VOUT = 0.4 V
A or B, DIR or G 20 µA VCC = MAX, VIN = 2.7 V
IIH Input HIGH Current DIR or G 0.1 mA VCC = MAX, VIN = 7.0 V
IH
uGCue
A or B 0.1 mA VCC = MAX, VIN = 5.5 V
IIL Input LOW Current –0.4 mA VCC = MAX, VIN = 0.4 V
IOS Output Short Circuit Current (Note 1) –40 –225 mA VCC = MAX
I
Power Supply Current
Total Output HIGH 70
A
VMAX
ICC Total, Output LOW 90 mA VCC = MAX
Total at HIGH Z 95
1. Not more than one output should be shorted at a time, nor for more than 1 second.
AC CHARACTERISTICS (TA = 25°C, VCC = 5.0 V) Limits
LS640 LS645
Symbol Parameter Min Typ Max Min Typ Max Unit Test Conditions
tPLH
tPHL Propagation Delay
A to B 6.0
8.0 10
15 8.0
11 15
15 ns
tPLH
tPHL Propagation Delay
B to A 6.0
8.0 10
15 8.0
11 15
15 ns C
= 45 pF,
tPZL
tPZH Output Enable Time
G, DIR to A 31
23 40
40 31
26 40
40 ns
,
RL = 667 Ω
tPZL
tPZH Output Enable Time
G, DIR to B 31
23 40
40 31
26 40
40 ns
tPLZ
tPHZ Output Disable Time
G, DIR to A 15
15 25
25 15
15 25
25 ns
p
tPLZ
tPHZ Output Disable Time
G, DIR to B 15
15 25
25 15
15 25
25 ns CL = 5.0 pF
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4
SN74LS641 •SN74LS642
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
Limits
Symbol Parameter Min Typ Max Unit Test Conditions
VIH Input HIGH Voltage 2.0 V Guaranteed Input HIGH Voltage for
All Inputs
VIL Input LOW Voltage 0.6 VGuaranteed Input LOW Voltage for
All Inputs
VIK Input Clamp Diode Voltage –0.65 –1.5 V VCC = MIN, IIN = –18 mA
IOH Output HIGH Current 100 µA VCC = MIN, VOH = MAX
V
Out
p
ut LOW Voltage
0.25 0.4 V IOL = 12 mA VCC = VCC MIN,
V V or V
VOL Output LOW Voltage 0.35 0.5 V IOL = 24 mA VIN = VIL or VIH
per Truth Table
I
In
p
ut HIGH Current
20 µA VCC = MAX, VIN = 2.7 V
IIH Input HIGH Current –0.1 mA VCC = MAX, VIN = 7.0 V
IIL Input LOW Current –0.4 mA VCC = MAX, VIN = 0.4 V
Power Supply Current
Total, Output HIGH 70
ICC Total, Output LOW 90 mA VCC = MAX
Total at HIGH Z 95
AC CHARACTERISTICS (TA = 25°C, VCC = 5.0 V)
Limits
LS641 LS642
Symbol Parameter Min Typ Max Min Typ Max Unit Test Conditions
tPLH
tPHL Propagation Delay,
A to B 17
16 25
25 19
14 25
25 ns
tPLH
tPHL Propagation Delay,
B to A 17
16 25
25 19
14 25
25 ns CL = 45 pF,
tPLH
tPHL Propagation Delay,
G, DIR to A 23
34 40
50 26
43 40
60 ns
,
RL = 667 Ω
tPLH
tPHL Propagation Delay,
G, DIR to B 25
37 40
50 28
39 40
60 ns
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5
DEVICE ORDERING INFORMATION
Device Order Number Package Type Tape and Reel Size
SN74LS640N PDIP–20 1440 Units/Box
SN74LS640DW SOIC–WIDE 2500/Tape and Reel
SN74LS640DWR2 SOIC–WIDE 2500/Tape and Reel
SN74LS640M SOEIAJ–20 See Note 2
SN74LS640MEL SOEIAJ–20 See Note 2
SN74LS641N PDIP–20 1440 Units/Box
SN74LS641DW SOIC–WIDE 2500/Tape and Reel
SN74LS641DWR2 SOIC–WIDE 2500/Tape and Reel
SN74LS641M SOEIAJ–20 See Note 2
SN74LS641MEL SOEIAJ–20 See Note 2
SN74LS642N PDIP–20 1440 Units/Box
SN74LS642DW SOIC–WIDE 2500/Tape and Reel
SN74LS642DWR2 SOIC–WIDE 2500/Tape and Reel
SN74LS642M SOEIAJ–20 See Note 2
SN74LS642MEL SOEIAJ–20 See Note 2
SN74LS645N PDIP–20 1440 Units/Box
2. For ordering information on the EIAJ version of the SOIC package, please contact your local ON Semiconductor representative.
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6
PACKAGE DIMENSIONS
N SUFFIX
PLASTIC PACKAGE
CASE 738–03
ISSUE E
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD
FLASH.
M
L
J20 PL
M
B
M
0.25 (0.010) T
DIM MIN MAX MIN MAX
MILLIMETERSINCHES
A25.66 27.171.010 1.070
B6.10 6.600.240 0.260
C3.81 4.570.150 0.180
D0.39 0.550.015 0.022
G2.54 BSC0.100 BSC
J0.21 0.380.008 0.015
K2.80 3.550.110 0.140
L7.62 BSC0.300 BSC
M0 15 0 15
N0.51 1.010.020 0.040

E
1.27 1.770.050 0.070
1
11
10
20
–A–
SEATING
PLANE
K
N
FG
D20 PL
–T–
M
A
M
0.25 (0.010) T
E
B
C
F
1.27 BSC0.050 BSC
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7
PACKAGE DIMENSIONS
D SUFFIX
PLASTIC SOIC PACKAGE
CASE 751D–05
ISSUE F
20
1
11
10
B20X
H10X
C
L
18X A1
A
SEATING
PLANE
hX 45
E
D
M
0.25 M
B
M
0.25 S
AS
B
T
eT
B
A
DIM MIN MAX
MILLIMETERS
A2.35 2.65
A1 0.10 0.25
B0.35 0.49
C0.23 0.32
D12.65 12.95
E7.40 7.60
e1.27 BSC
H10.05 10.55
h0.25 0.75
L0.50 0.90
0 7
NOTES:
1. DIMENSIONS ARE IN MILLIMETERS.
2. INTERPRET DIMENSIONS AND TOLERANCES
PER ASME Y14.5M, 1994.
3. DIMENSIONS D AND E DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.
5. DIMENSION B DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE PROTRUSION SHALL
BE 0.13 TOTAL IN EXCESS OF B DIMENSION AT
MAXIMUM MATERIAL CONDITION.

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8
PACKAGE DIMENSIONS
M SUFFIX
SOEIAJ PACKAGE
CASE 967–01
ISSUE O
DIM MIN MAX MIN MAX
INCHES
--- 2.05 --- 0.081
MILLIMETERS
0.05 0.20 0.002 0.008
0.35 0.50 0.014 0.020
0.18 0.27 0.007 0.011
12.35 12.80 0.486 0.504
5.10 5.45 0.201 0.215
1.27 BSC 0.050 BSC
7.40 8.20 0.291 0.323
0.50 0.85 0.020 0.033
1.10 1.50 0.043 0.059
0
0.70 0.90 0.028 0.035
--- 0.81 --- 0.032
A1
HE
Q1
LE
10 0
10
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS D AND E DO NOT INCLUDE MOLD
FLASH OR PROTRUSIONS AND ARE MEASURED
AT THE PARTING LINE. MOLD FLASH OR
PROTRUSIONS SHALL NOT EXCEED 0.15 (0.006)
PER SIDE.
4. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
5. THE LEAD WIDTH DIMENSION (b) DOES NOT
INCLUDE DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08 (0.003)
TOTAL IN EXCESS OF THE LEAD WIDTH
DIMENSION AT MAXIMUM MATERIAL CONDITION.
DAMBAR CANNOT BE LOCATED ON THE LOWER
RADIUS OR THE FOOT. MINIMUM SPACE
BETWEEN PROTRUSIONS AND ADJACENT LEAD
TO BE 0.46 ( 0.018).
HE
A1
LEQ1
c
A
ZD
E
20
110
11
b
M
0.13 (0.005)
e
0.10 (0.004)
VIEW P
DETAIL P
M
L
A
b
c
D
E
e
L
M
Z
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without further notice to any products herein. SCILLC makes no warranty , representation or guarantee regarding the suitability of its products for any particular
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PUBLICATION ORDERING INFORMATION
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4–32–1 Nishi–Gotanda, Shinagawa–ku, Tokyo, Japan 141–0031
Phone: 81–3–5740–2700
Email: r14525@onsemi.com
ON Semiconductor Website: http://onsemi.com
For additional information, please contact your local
Sales Representative.
SN74LS640/D
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P.O. Box 5163, Denver, Colorado 80217 USA
Phone: 303–675–2175 or 800–344–3860 Toll Free USA/Canada
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