ADS8557IPMR - Texas Instruments High-Performance Analog

CDAC1

CDAC2

SARRegister1/2

S/H

Comparator

CDAC3

CDAC4

SARRegister3/4

S/H

Comparator

CDAC5

CDAC6

SARRegister5/6

StringDAC

Clock

Generator

S/H

Comparator

Internal2.5V

Reference

I/O

Control

Logic

Config

CH_A0

CONVST_A

CH_A1

AGND

REFC_A

CH_B0

CONVST_B

CH_B1

AGND

REFC_B

CH_C0

CONVST_C

CH_C1

AGND

REFC_C

REF IO_

HVSS

AVDD

AGND

ADS8556

ADS8557

ADS8558

Buffer

HVDD

BVDD

BGND

HW/SW

REF /WR

STBY

RESET

RANGE/XCLK

BUSY/INT

DB[15:0]

WORD/BYTE

PAR/SER

CS/FS

ADS8556

ADS8557

ADS8558

www.ti.com

SBAS404B –OCTOBER 2006–REVISED JANUARY 2012

16-, 14-, 12-Bit, Six-Channel, Simultaneous Sampling

ANALOG-TO-DIGITAL CONVERTERS

Check for Samples: ADS8556,ADS8557,ADS8558

1FEATURES DESCRIPTION

The ADS8556/7/8 contain six low-power, 16-, 14-, or

2•Family of 16-, 14-, 12-Bit, Pin- and 12-bit, successive approximation register (SAR)

Software-Compatible ADCs based analog-to-digital converters (ADCs) with true

•Six SAR ADCs Grouped in Three Pairs bipolar inputs. Each channel contains a

•Maximum Data Rate Per Channel with Internal sample-and-hold circuit that allows simultaneous

high-speed multi-channel signal acquisition.

Conversion Clock and Reference:

ADS8556: 630kSPS (PAR) or 450kSPS (SER) The ADS8556/7/8 support data rates of up to

ADS8557: 670kSPS (PAR) or 470kSPS (SER) 730kSPS in parallel interface mode or up to 500kSPS

ADS8558: 730kSPS (PAR) or 500kSPS (SER) if the serial interface is used. The bus width of the

parallel interface can be set to eight or 16 bits. In

•Maximum Data Rate with External Conversion serial mode, up to three output channels can be

Clock and Reference: activated.

800kSPS (PAR) or 530kSPS (SER) The ADS8556/7/8 is specified over the full industrial

•Pin-Selectable or Programmable Input Voltage temperature range of –40°C to +125°C and is

Ranges: Up to ±12V available in an LQFP-64 package.

•Excellent Signal-to-Noise Performance:

91.5dB (ADS8556)

85dB (ADS8557)

73.9dB (ADS8558)

•Programmable and Buffered Internal

Reference: 0.5V to 2.5V and 0.5V to 3.0V

•Comprehensive Power-Down Modes:

Deep Power-Down (Standby Mode)

Partial Power-Down

Auto-Nap Power-Down

•Selectable Parallel or Serial Interface

•Operating Temperature Range:

–40°C to +125°C

•LQFP-64 Package

APPLICATIONS

•Power Quality Measurement

•Protection Relays

•Multi-Axis Motor Control

•Programmable Logic Controllers

•Industrial Data Acquisition

1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2All trademarks are the property of their respective owners.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

ADS8556

ADS8557

ADS8558

SBAS404B –OCTOBER 2006–REVISED JANUARY 2012

www.ti.com

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with

appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more

susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

PACKAGE/ORDERING INFORMATION(1)

RESOLUTION PACKAGE- PACKAGE ORDERING TRANSPORT

PRODUCT (Bits) LEAD DESIGNATOR NUMBER MEDIA, QUANTITY

ADS8556IPM Tray, 160

ADS8556I 16 LQFP-64 PM ADS8556IPMR Tape and Reel, 1000

ADS8557IPM Tray, 160

ADS8557I 14 LQFP-64 PM ADS8557IPMR Tape and Reel, 1000

ADS8558IPM Tray, 160

ADS8558I 12 LQFP-64 PM ADS8558IPMR Tape and Reel, 1000

(1) For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TI

web site at www.ti.com.

ABSOLUTE MAXIMUM RATINGS(1)

Over operating free-air temperature range, unless otherwise noted. ADS8556, ADS8557, ADS8558 UNIT

Supply voltage, HVDD to AGND –0.3 to +18 V

Supply voltage, HVSS to AGND –18 to +0.3 V

Supply voltage, AVDD to AGND –0.3 to +6 V

Supply voltage, BVDD to BGND –0.3 to +6 V

Analog input voltage HVSS –0.3 to HVDD + 0.3 V

Reference input voltage with respect to AGND AGND –0.3 to AVDD + 0.3 V

Digital input voltage with respect to BGND BGND –0.3 to BVDD + 0.3 V

Ground voltage difference AGND to BGND ±0.3 V

Input current to all pins except supply –10 to +10 mA

Maximum virtual junction temperature, TJ+150 °C

Human body model (HBM) ±2000 V

JEDEC standard 22, test method A114-C.01, all pins

ESD ratings Charged device model (CDM) ±500 V

JEDEC standard 22, test method C101, all pins

(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings

only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating

conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

ADS8556

ADS8557

ADS8558

www.ti.com

SBAS404B –OCTOBER 2006–REVISED JANUARY 2012

RECOMMENDED OPERATING CONDITIONS MIN TYP MAX UNIT

Supply voltage, AVDD to AGND 4.5 5 5.5 V

Low-voltage levels 2.7 3.0 3.6 V

Supply voltage, BVDD to BGND 5V logic levels 4.5 5 5.5 V

Range 1 (±2×VREF) 2 ×VREF 16.5 V

Input supply voltage, HVDD to AGND Range 2 (±4×VREF) 4 ×VREF 16.5 V

Range 1 (±2×VREF)–16.5 –2×VREF V

Input supply voltage, HVSS to AGND Range 2 (±4×VREF)–16.5 –4×VREF V

Reference input voltage (VREF) 0.5 2.5 3.0 V

Range 1 (±2×VREF)–2×VREF +2 ×VREF V

Analog inputs

(also see the Analog Inputs section) Range 1 (±4×VREF)–4×VREF +4 ×VREF V

Operating ambient temperature range, TA–40 +125 °C

DISSIPATION RATINGS(1)

DERATING FACTOR TA≤+25°C TA= +70°C TA= +85°C TA= +125°C

PACKAGE ABOVE TA= +25°C POWER RATING POWER RATING POWER RATING POWER RATING

LQFP-64 20.8mW/°C 2.60W 1.66W 1.35W 0.52W

(1) Based on High-K θJA.

THERMAL CHARACTERISTICS

Over recommended operating conditions, unless otherwise noted. ADS8556, ADS8557, ADS8558

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Low-K thermal resistance(1) 74 °C/W

θJA Junction-to-air thermal resistance High-K thermal resistance(1) 48 °C/W

Junction-to-case thermal

θJC 16 °C/W

resistance

ADS8556, HVDD = +15V, HVSS = –15V, AVDD = 5V, 251.7 298.5 mW

BVDD = 3V, and fDATA = maximum

ADS8557, HVDD = +15V, HVSS = –15V, AVDD = 5V,

PDDevice power dissipation 253.2 303.0 mW

BVDD = 3V, and fDATA = maximum

ADS8558, HVDD = +15V, HVSS = –15V, AVDD = 5V, 262.2 318.0 mW

BVDD = 3V, and fDATA = maximum

(1) Modeled in accordance with the Low-K or High-K thermal metric definitions of EIA/JESD51-3.

ADS8556

ADS8557

ADS8558

SBAS404B –OCTOBER 2006–REVISED JANUARY 2012

www.ti.com

ELECTRICAL CHARACTERISTICS: ADS8556

Over recommended operating free-air temperature range of –40°C to +125°C, AVDD = 4.5V to 5V, BVDD = 2.7V to 5.5V,

HVDD = 10V to 15V, HVSS = –15V to –10V, VREF = 2.5V (internal), and fDATA = 630kSPS in parallel mode or 450kSPS in

serial mode, unless otherwise noted. ADS8556

PARAMETER CONDITIONS MIN TYP(1) MAX UNIT

DC ACCURACY

Resolution 16 Bits

No missing codes 16 Bits

At TA=–40°C to +85°C–3±1.5 3 LSB

Integral linearity error INL At TA=–40°C to +125°C–4±1.5 4 LSB

At TA=–40°C to +85°C–1±0.75 1.5 LSB

Differential linearity error DNL At TA=–40°C to +125°C–1±0.75 2 LSB

Offset error –4.0 ±0.8 4.0 mV

Offset error drift ±3.5 μV/°C

Gain error Referenced to voltage at REFIO –0.75 ±0.25 0.75 %FSR

Gain error drift Referenced to voltage at REFIO ±6 ppm/°C

Power-supply rejection ratio PSRR At output code FFFFh, related to AVDD 60 dB

SAMPLING DYNAMICS

Acquisition time tACQ 280 ns

Conversion time per ADC tCONV 1.26 μs

18.5 tCCLK

Internal conversion clock period tCCLK 68.0 ns

Parallel interface, 630 kSPS

internal clock and reference

Throughput rate fDATA Serial interface, 450 kSPS

internal clock and reference

AC ACCURACY

At fIN = 10kHz, TA=–40°C to +85°C 90 91.5 dB

Signal-to-noise ratio SNR At fIN = 10kHz, TA=–40°C to +125°C 89 91.5 dB

At fIN = 10kHz, TA=–40°C to +85°C 87 89.5 dB

Signal-to-noise ratio + distortion SINAD At fIN = 10kHz, TA=–40°C to +125°C 86.5 89.5 dB

At fIN = 10kHz, TA=–40°C to +85°C–94 –90 dB

Total harmonic distortion(2) THD At fIN = 10kHz, TA=–40°C to +125°C–94 –89.5

At fIN = 10kHz, TA=–40°C to +85°C 90 95 dB

Spurious-free dynamic range SFDR At fIN = 10kHz, TA=–40°C to +125°C 89.5 95 dB

Channel-to-channel isolation At fIN = 10kHz 100 dB

In 4 ×VREF mode 48 MHz

–3dB small-signal bandwidth In 2 ×VREF mode 24 MHz

(1) All values are at TA= +25°C.

(2) Calculated on the first nine harmonics of the input frequency.

ADS8556

ADS8557

ADS8558

www.ti.com

SBAS404B –OCTOBER 2006–REVISED JANUARY 2012

ELECTRICAL CHARACTERISTICS: ADS8557

Over recommended operating free-air temperature range of –40°C to +125°C, AVDD = 4.5V to 5.5V, BVDD = 2.7V to 5.5V,

HVDD = 10V to 15V, HVSS = –15V to –10V, VREF = 2.5V (internal), and fDATA = 670kSPS in parallel mode or 470kSPS in

serial mode, unless otherwise noted. ADS8557

PARAMETER CONDITIONS MIN TYP(1) MAX UNIT

DC ACCURACY

Resolution 14 Bits

No missing codes 14 Bits

Integral linearity error INL –1±0.4 1 LSB

Differential linearity error DNL –1±0.25 1 LSB

Offset error –4±0.8 4 mV

Offset error drift ±3.5 μV/°C

Gain error Referenced to voltage at REFIO –0.75 ±0.25 0.75 %FSR

Gain error drift Referenced to voltage at REFIO ±6 ppm/°C

Power-supply rejection ratio PSRR At output code FFFFh, related to AVDD 60 dB

SAMPLING DYNAMICS

Acquisition time tACQ 280 ns

Conversion time per ADC tCONV 1.19 μs

18.5 tCCLK

Internal conversion clock period tCCLK 64.1 ns

Parallel interface, 670 kSPS

internal clock and reference

Throughput rate fDATA Serial interface, 470 kSPS

internal clock and reference

AC ACCURACY

Signal-to-noise ratio SNR At fIN = 10kHz 84 85 dB

Signal-to-noise ratio + distortion SINAD At fIN = 10kHz 83 84 dB

Total harmonic distortion(2) THD At fIN = 10kHz –91 –86 dB

Spurious-free dynamic range SFDR At fIN = 10kHz 86 92 dB

Channel-to-channel isolation At fIN = 10kHz 100 dB

In 4 ×VREF mode 48 MHz

–3dB small-signal bandwidth In 2 ×VREF mode 24 MHz

(1) All values are at TA= +25°C.

(2) Calculated on the first nine harmonics of the input frequency.

ADS8556

ADS8557

ADS8558

SBAS404B –OCTOBER 2006–REVISED JANUARY 2012

www.ti.com

ELECTRICAL CHARACTERISTICS: ADS8558

Over recommended operating free-air temperature range of –40°C to +125°C, AVDD = 4.5V to 5V, BVDD = 2.7V to 5.5V,

HVDD = 10V to 15V, HVSS = –15V to –10V, VREF = 2.5V (internal), and fDATA = 730kSPS in parallel mode or 500kSPS in

serial mode, unless otherwise noted. ADS8558

PARAMETER CONDITIONS MIN TYP(1) MAX UNIT

DC ACCURACY

Resolution 12 Bits

No missing codes 12 Bits

Integral linearity error INL –0.75 ±0.2 0.75 LSB

Differential linearity error DNL –0.5 ±0.2 0.5 LSB

Offset error –4±0.8 4 mV

Offset error drift ±3.5 μV/°C

Gain error Referenced to voltage at REFIO –0.75 ±0.25 0.75 %FSR

Gain error drift Referenced to voltage at REFIO ±6 ppm/°C

Power-supply rejection ratio PSRR At output code FFFFh, related to AVDD 60 dB

SAMPLING DYNAMICS

Acquisition time tACQ 280 ns

Conversion time per ADC tCONV 1.09 μs

18.5 tCCLK

Internal conversion clock period tCCLK 58.8 ns

Parallel interface, 730 kSPS

internal clock and reference

Throughput rate fDATA Serial interface, 500 kSPS

internal clock and reference

AC ACCURACY

Signal-to-noise ratio SNR At fIN = 10kHz 73 73.9 dB

Signal-to-noise ratio + distortion SINAD At fIN = 10kHz 73 73.8 dB

Total harmonic distortion(2) THD At fIN = 10kHz –89 –84 dB

Spurious-free dynamic range SFDR At fIN = 10kHz 84 92 dB

Channel-to-channel isolation At fIN = 10kHz 100 dB

In 4 ×VREF mode 48 MHz

–3dB small-signal bandwidth In 2 ×VREF mode 24 MHz

(1) All values are at TA= +25°C.

(2) Calculated on the first nine harmonics of the input frequency.

ADS8556

ADS8557

ADS8558

www.ti.com

SBAS404B –OCTOBER 2006–REVISED JANUARY 2012

ELECTRICAL CHARACTERISTICS: GENERAL

Over recommended operating free-air temperature range of –40°C to +125°C, AVDD = 4.5V to 5.5V, BVDD = 2.7V to 5.5V,

HVDD = 10V to 15V, HVSS = –15V to –10V, VREF = 2.5V (internal), and fDATA = maximum, unless otherwise noted.

ADS8556, ADS8557, ADS8558

PARAMETER CONDITIONS MIN TYP(1) MAX UNIT

ANALOG INPUT

RANGE pin/RANGE bit = 0 –4×VREF +4 ×VREF V

Bipolar full-scale range CHXX RANGE pin/RANGE bit = 1 –2×VREF +2 ×VREF V

Input range = ±4×VREF 10 pF

Input capacitance Input range = ±2×VREF 20 pF

Input leakage current No ongoing conversion ±1μA

Aperture delay 5 ns

Aperture delay matching Common CONVST for all channels 250 ps

Aperture jitter 50 ps

EXTERNAL CLOCK INPUT (XCLK)

External clock frequency fXCLK An external reference must be used for fXCLK >fCCLK 1 18 20 MHz

External clock duty cycle 45 55 %

REFERENCE VOLTAGE OUTPUT (REFOUT)

2.5V operation, REFDAC = 0x3FF 2.485 2.5 2.515 V

2.5V operation, REFDAC = 0x3FF at +25°C 2.496 2.5 2.504 V

Reference voltage VREF 3.0V operation, REFDAC = 0x3FF 2.985 3.0 3.015 V

3.0V operation, REFDAC = 0x3FF at +25°C 2.995 3.0 3.005 V

Reference voltage drift dVREF/dT ±10 ppm/°C

Power-supply rejection ratio PSRR 73 dB

Output current IREFOUT DC current –2 2 mA

Short-circuit current(2) IREFSC 50 mA

Turn-on settling time tREFON 10 ms

At CREF_x pins 4.7 10 μF

External load capacitance At REFIO pins 100 470 nF

Tuning range REFDAC Internal reference output voltage range 0.2 ×VREF VREF V

REFDAC resolution 10 Bits

REFDAC differential nonlinearity DNLDAC –1±0.1 1 LSB

REFDAC integral nonlinearity INLDAC –2±0.1 2 LSB

REFDAC offset error VOSDAC VREF = 0.5V (DAC = 0x0CC) –4±0.65 4 LSB

REFERENCE VOLTAGE INPUT (REFIN)

Reference input voltage VREFIN 0.5 2.5 3.025 V

Input resistance 100 MΩ

Input capacitance 5 pF

Reference input current 1 μA

SERIAL CLOCK INPUT (SCLK)

Serial clock input frequency fSCLK 0.1 36 MHz

Serial clock period tSCLK 0.0278 10 μs

Serial clock duty cycle 40 60 %

DIGITAL INPUTS(3)

Logic family CMOS with Schmitt-Trigger

High-level input voltage 0.7 ×BVDD BVDD + 0.3 V

Low-level input voltage BGND –0.3 0.3 ×BVDD V

Input current VI= BVDD to BGND –50 +50 nA

Input capacitance 5 pF

(1) All values are at TA= +25°C.

(2) Reference output current is not limited internally.

(3) Specified by design.

ADS8556

ADS8557

ADS8558

SBAS404B –OCTOBER 2006–REVISED JANUARY 2012

www.ti.com

ELECTRICAL CHARACTERISTICS: GENERAL (continued)

Over recommended operating free-air temperature range of –40°C to +125°C, AVDD = 4.5V to 5.5V, BVDD = 2.7V to 5.5V,

HVDD = 10V to 15V, HVSS = –15V to –10V, VREF = 2.5V (internal), and fDATA = maximum, unless otherwise noted.

ADS8556, ADS8557, ADS8558

PARAMETER CONDITIONS MIN TYP(1) MAX UNIT

DIGITAL OUTPUTS(4)

Logic family CMOS

High-level output voltage IOH = 100μA BVDD –0.6 BVDD V

Low-level output voltage IOH =–100μA BGND BGND + 0.4 V

High-impedance-state output current –50 50 nA

Output capacitance 5 pF

Load capacitance 30 pF

POWER-SUPPLY REQUIREMENTS

Analog supply voltage AVDD 4.5 5.0 5.5 V

Buffer I/O supply voltage BVDD 2.7 3.0 5.5 V

Input positive supply voltage HVDD 5.0 10.0 16.5 V

Input negative supply voltage HVSS –16.5 –10.0 –5.0 V

fDATA = maximum 30.0 36.0 mA

ADS8556, fDATA = 250kSPS (auto-NAP mode) 14.0 16.5 mA

ADS8557, fDATA = 250kSPS (auto-NAP mode) 14.0 17.0 mA

Analog supply current(5) IAVDD ADS8558, fDATA = 250kSPS (auto-NAP mode) 14.0 18.0 mA

Auto-NAP mode, no ongoing conversion, 4.0 6.0 mA

internal conversion clock

Power-down mode 0.1 50.0 μA

fDATA = maximum 0.9 2.0 mA

fDATA = 250kSPS (auto-NAP mode) 0.5 1.5 mA

Buffer I/O supply current(6) IBVDD Auto-NAP mode, no ongoing conversion, 0.1 10.0 μA

internal conversion clock

Power-down mode 0.1 10.0 μA

ADS8556, fDATA = maximum 3.0 3.5 mA

ADS8557, fDATA = maximum 3.1 3.6 mA

ADS8558, fDATA = maximum 3.3 4.0 mA

Input positive supply current(7) IHVDD fDATA = 250kSPS (auto-NAP mode) 1.6 2.0 mA

Auto-NAP mode, no ongoing conversion, 0.2 0.3 μA

internal conversion clock

Power-down mode 0.1 10.0 μA

ADS8556, fDATA = maximum 3.6 4.0 mA

ADS8557, fDATA = maximum 3.6 4.2 mA

ADS8558, fDATA = maximum 4.0 4.8 mA

Input negative supply current(8) IHVSS fDATA = 250kSPS (auto-NAP mode) 1.8 2.2 mA

Auto-NAP mode, no ongoing conversion, 0.2 0.25 μA

internal conversion clock

Power-down mode 0.1 10.0 μA

(4) Specified by design.

(5) At AVDD = 5V.

(6) At BVDD = 3V, parallel mode, load capacitance = 6pF/pin.

(7) At HVDD = 15V.

(8) At HVSS = –15V.

R =200

SER WR =130

SW W

R =200W

SER R =130

SW W

C =5pF

PAR

C =20pF

CH_XX

AGND

Inputrange: 2V±REF

VDC

R =200

SER WR =130

SW W

R =200W

SER R =130

SW W

C =5pF

PAR

C =10pF

CH_XX

AGND

Inputrange: 4V±REF

VDC

ADS8556

ADS8557

ADS8558

www.ti.com

SBAS404B –OCTOBER 2006–REVISED JANUARY 2012

ELECTRICAL CHARACTERISTICS: GENERAL (continued)

Over recommended operating free-air temperature range of –40°C to +125°C, AVDD = 4.5V to 5.5V, BVDD = 2.7V to 5.5V,

HVDD = 10V to 15V, HVSS = –15V to –10V, VREF = 2.5V (internal), and fDATA = maximum, unless otherwise noted.

ADS8556, ADS8557, ADS8558

PARAMETER CONDITIONS MIN TYP(1) MAX UNIT

POWER-SUPPLY REQUIREMENTS (continued)

ADS8556, fDATA = maximum 251.7 298.5 mW

ADS8557, fDATA = maximum 253.2 303.0 mW

ADS8558, fDATA = maximum 262.2 318.0 mW

ADS8556, fDATA = 250kSPS (auto-NAP mode) 122.5 150.0 mW

Power dissipation(9) ADS8557, fDATA = 250kSPS (auto-NAP mode) 122.5 152.5 mW

ADS8558, fDATA = 250kSPS (auto-NAP mode) 122.5 157.5 mW

Auto-NAP mode, no ongoing conversion, 26.0 38.3 mW

internal conversion clock

Power-down mode 3.8 580.0 μW

(9) At AVDD = 5V, BVDD = 3V, HVDD = 15V, and HVSS = –15V.

Figure 1. EQUIVALENT INPUT CIRCUITS

CH_C1

AVDD

CH_C0

AGND

CH_B1

AVDD

CH_B0

AGND

CH_A1

AVDD

CH_A0

DB14/REFBUFEN

DB13/SDI

DB12

DB11

DB10/SDO_C

DB9/SDO_B

DB8/SDO_A

BGND

BVDD

DB7/HB /DC

EN EN

DB6/SCLK

DB5/DCIN_A

DB4/DCIN_B

DB3/DCIN_C

DB2/SEL_C

DB1/SEL_B

DB15

DB0/SEL_A

REF /WR

BUSY/INT

HW/SW

CSFS/

PAR/SER

AVDD

CONVST_C

AGND

CONVST_B

REFC_C

CONVST_A

AGND

STBY

REFC_B

AGND

AVDD

REFC_A

RANGE/XCLK

AGND

RESET

AGND

WORD/BYTE

REFIO

HVSS

AVDD

HVDD

AGND

64 63 62 61 60 59 58 57 56 55 54

17 18 19 20 21 22 23 24 25 26 27

53 52 51 50 49

28 29 30 31 32

ADS8556

ADS8557

ADS8558

ADS8556

ADS8557

ADS8558

SBAS404B –OCTOBER 2006–REVISED JANUARY 2012

www.ti.com

PIN CONFIGURATION

PM PACKAGE

LQFP-64

(TOP VIEW)

ADS8556

ADS8557

ADS8558

www.ti.com

SBAS404B –OCTOBER 2006–REVISED JANUARY 2012

TERMINAL FUNCTIONS

DESCRIPTION

NAME PIN # TYPE(1) PARALLEL INTERFACE (PAR/SER = 0) SERIAL INTERFACE (PAR/SER = 1)

Hardware mode (HW/SW = 0):

Reference buffers enable input.

When low, all reference buffers are enabled (mandatory if

internal reference is used). When high, all reference buffers

Data bit 14 input/output

DB14/REFBUFEN 1 DIO/DI are disabled.

Output is '0'for the ADS8557/8 Software mode (HW/SW = 1):Connect to BGND or BVDD.

The reference buffers are controlled by bit C24 (REFBUF) in

control register (CR).

Data bit 13 input/output Hardware mode (HW/SW = 0): Connect to BGND

DB13/SDI 2 DIO/DI Output is MSB for the ADS8557 and '0'for the Software mode (HW/SW = 1): Serial data input

ADS8558

Data bit 12 input/output

DB12 3 DIO Connect to BGND

Output is '0'for the ADS8558

Data bit 11 input/output

DB11 4 DIO Connect to BGND

Output is MSB for the ADS8558

When SEL_C = 1, data output for channel C

DB10/SDO_C 5 DIO/DO Data bit 10 input/output When SEL_C = 0, this pin should be tied to BGND

When SEL_B = 1, data output for channel B

When SEL_B = 0, this pin should be tied to BGND

DB9/SDO_B 6 DIO/DO Data bit 9 input/output When SEL_C = 0, data from channel C1 are also available

on this output

Data output for channel A

When SEL_C = 0, data from channel C0 are also available

DB8/SDO_A 7 DIO/DO Data bit 8 input/output on this output

When SEL_C = 0 and SEL_B = 0, SDO_A acts as the single

data output for all channels

BGND 8 P Buffer IO ground, connect to digital ground plane

Buffer IO supply, connect to digital supply (2.7V to 5.5V). Decouple with a 1μF ceramic capacitor or a combination

BVDD 9 P of 100nF and 10μF ceramic capacitors to BGND.

Word mode (WORD/BYTE = 0):

Data bit 7 input/output Daisy-chain enable input.

Byte mode (WORD/BYTE = 1):

DB7/HBEN/DCEN 10 DIO/DI/DI When high, DB[5:3] serve as daisy-chain inputs DCIN[A:C].

High byte enable input. If daisy-chain mode is not used, connect to BGND.

When high, the high byte is output first on

DB[15:8]. When low, the low byte is output first on

DB[15:8].

Word mode (WORD/BYTE = 0):

Data bit 6 input/output

DB6/SCLK 11 DIO/DI Serial interface clock input (36MHz max)

Byte mode (WORD/BYTE = 1):

Connect to BGND or BVDD

Word mode (WORD/BYTE = 0):

Data bit 5 input/output When DCEN = 1, daisy-chain data input for channel A

DB5/DCIN_A 12 DIO/DI When DCEN = 0, connect to BGND

Byte mode (WORD/BYTE = 1):

Connect to BGND or BVDD

Word mode (WORD/BYTE = 0): When SEL_B = 1 and DCEN = 1, daisy-chain data input for

Data bit 4 input/output

DB4/DCIN_B 13 DIO/DI channel B

Byte mode (WORD/BYTE = 1): When DCEN = 0, connect to BGND

Connect to BGND or BVDD

Word mode (WORD/BYTE = 0): When SEL_C = 1 and DCEN = 1, daisy-chain data input for

Data bit 3 input/output

DB3/DCIN_C 14 DIO/DI channel C

Byte mode (WORD/BYTE = 1): When DCEN = 0, connect to BGND

Connect to BGND or BVDD

Word mode (WORD/BYTE = 0):

Data bit 2 input/output Select SDO_C input.

DB2/SEL_C 15 DIO/DI When high, SDO_C is active. When low, SDO_C is disabled.

Byte mode (WORD/BYTE = 1):

Connect to BGND or BVDD

Word mode (WORD/BYTE = 0):

Data bit 1 input/output Select SDO_B input.

DB1/SEL_B 16 DIO/DI When high, SDO_B is active. When low, SDO_B is disabled.

Byte mode (WORD/BYTE = 1):

Connect to BGND or BVDD

(1) AI = analog input; AIO = analog input/output; DI = digital input; DO = digital output; DIO = digital input/output; and P = power supply.

ADS8556

ADS8557

ADS8558

SBAS404B –OCTOBER 2006–REVISED JANUARY 2012

www.ti.com

TERMINAL FUNCTIONS (continued)

DESCRIPTION

NAME PIN # TYPE(1) PARALLEL INTERFACE (PAR/SER = 0) SERIAL INTERFACE (PAR/SER = 1)

Word mode (WORD/BYTE = 0): Select SDO_A input.

Data bit 0 (LSB) input/output

DB0/SEL_A 17 DIO/DI When high, SDO_A is active. When low, SDO_A is disabled.

Byte mode (WORD/BYTE = 1): Should always be high.

Connect to BGND or BVDD

When CR bit C21 = 0 (BUSY/INT), converter busy status output. Transitions high when a conversion has been

started and remains high during the entire process. Transitions low when the conversion data of all six channels

are latched to the output register and remains low thereafter.

In sequential mode (SEQ = 1 in the CR), the BUSY output transitions high when a conversion has been started

BUSY/INT 18 DO and goes low for a single conversion clock cycle (tCCLK) whenever a channel pair conversion is completed.

When bit C21 = 1 (BUSY/INT in CR), interrupt output. This bit transitions high after a conversion has been

completed and remains high until the conversion result has been read.

The polarity of BUSY/INT output can be changed using bit C20 (BUSY L/H) in the control register.

Chip select input. Frame synchronization.

CS/FS 19 DI/DI When low, the parallel interface is enabled. When The falling edge of FS controls the frame transfer.

high, the interface is disabled.

Read data input.

RD 20 DI When low, the parallel data output is enabled. Connect to BGND

When high, the data output is disabled.

Hardware mode (HW/SW = 0): Conversion start of channel pair C.

The rising edge of this signal initiates simultaneous conversion of analog signals at inputs CH_C[1:0]. CONVST_C

should remain high during the entire conversion cycle, otherwise both ADCs of channel C are put in partial

CONVST_C 21 DI power-down mode (see the Reset and Power-down Modes sections).

Software mode (HW/SW = 1): Conversion start of channel pair C in sequential mode (CR bit C23 = 1) only;

connect to BGND or BVDD otherwise

Hardware mode (HW/SW = 0): Conversion start of channel pair B.

The rising edge of this signal initiates simultaneous conversion of analog signals at inputs CH_B[1:0]. CONVST_B

should remain high during the entire conversion cycle; otherwise, both ADCs of channel B are put into partial

CONVST_B 22 DI power-down mode (see the Reset and Power-down Modes sections).

Software mode (HW/SW = 1): Conversion start of channel pair B in sequential mode (CR bit C23 = 1) only;

connect to BGND or BVDD otherwise

Hardware mode (HW/SW = 0): Conversion start of channel pair A.

The rising edge of this signal initiates simultaneous conversion of analog signals at inputs CH_A[1:0]. CONVST_A

should remain high during the entire conversion cycle; otherwise, both ADCs of channel A are put into partial

CONVST_A 23 DI power-down mode (see the Reset and Power-down Modes sections).

Software mode (HW/SW = 1): Conversion start of all selected channels except in sequential mode

(CR bit C23 = 1): Conversion start of channel pair A only

Standby mode input. When low, the entire device is powered-down (including the internal clock and reference).

STBY 24 DI When high, the device operates in normal mode.

25, 32,

37, 38, Analog ground, connect to analog ground plane

43, 44,

AGND P Pin 25 may have a dedicated ground if the difference between its potential and AGND is always kept within

49, 52, ±300mV.

53, 55,

57, 59

26, 34, Analog power supply (4.5V to 5.5V). Decouple each pin with a 100nF ceramic capacitor to AGND. Use an

35, 40, additional 10μF capacitor to AGND close to the device but without compromising the placement of the smaller

AVDD 41, 46, P capacitor. Pin 26 may have a dedicated power supply if the difference between its potential and AVDD is always

47, 50, kept within ±300mV.

Hardware mode (HW/SW = 0): Input voltage range select input.

When low, the analog input range is ±4VREF. When high, the analog input range is ±2VREF.

RANGE/XCLK 27 DI/DIO Software mode (HW/SW = 1): External conversion clock input, if CR bit C11 (CLKSEL) is set high or internal

conversion clock output, if CR bit C10 (CLKOUT_EN) is set high. If not used, connect to BVDD or BGND.

Reset input, active high. Aborts any ongoing conversions. Resets the internal control register to 0x000003FF. The

RESET 28 DI RESET pulse should be at least 50ns long.

Output mode selection input.

When low, data are transferred in word mode using

DB[15:0]. When high, data are transferred in byte

WORD/BYTE 29 DI Connect to BGND

mode using DB[15:8] with the byte order controlled

by HBEN pin while two accesses are required for a

complete 16-bit transfer.

Negative supply voltage for the analog inputs (–16.5V to –5V).

HVSS 30 P Decouple with a 100nF ceramic capacitor to AGND placed next to the device and a 10μF capacitor to AGND close

to the device but without compromising the placement of the smaller capacitor.

ADS8556

ADS8557

ADS8558

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SBAS404B –OCTOBER 2006–REVISED JANUARY 2012

TERMINAL FUNCTIONS (continued)

DESCRIPTION

NAME PIN # TYPE(1) PARALLEL INTERFACE (PAR/SER = 0) SERIAL INTERFACE (PAR/SER = 1)

Positive supply voltage for the analog inputs (5V to 16.5V). Decouple with a 100nF ceramic capacitor to AGND

HVDD 31 P placed next to the device and a 10μF capacitor to AGND close to the device but without compromising the

placement of the smaller capacitor.

Analog input of channel A0. The input voltage range is controlled by RANGE pin in hardware mode or CR bit C26

CH_A0 33 AI (RANGE_A) in software mode.

Analog input of channel A1. The input voltage range is controlled by RANGE pin in hardware mode or CR bit C26

CH_A1 36 AI (RANGE_A) in software mode.

Analog input of channel B0. The input voltage range is controlled by RANGE pin in hardware mode or CR bit C27

CH_B0 39 AI (RANGE_B) in software mode.

Analog input of channel B1. The input voltage range is controlled by RANGE pin in hardware mode or CR bit C27

CH_B1 42 AI (RANGE_B) in software mode.

Analog input of channel C0. The input voltage range is controlled by RANGE pin in hardware mode or CR bit C28

CH_C0 45 AI (RANGE_C) in software mode.

Analog input of channel C1. The input voltage range is controlled by RANGE pin in hardware mode or CR bit C28

CH_C1 48 AI (RANGE_C) in software mode.

Reference voltage input/output (0.5V to 3.025V).

The internal reference is enabled via REFEN/WR pin in hardware mode or CR bit C25 (REFEN) in software mode.

REFIO 51 AIO The output value is controlled by the internal DAC (CR bits C[9:0]). Connect a 470nF ceramic decoupling

capacitor between this pin and pin 52.

Decoupling capacitor for reference of channels A.

REFC_A 54 AI Connect a 10μF ceramic decoupling capacitor between this pin and pin 53.

Decoupling capacitor for reference of channels B.

REFC_B 56 AI Connect a 10μF ceramic decoupling capacitor between this pin and pin 55.

Decoupling capacitor for reference of channels C.

REFC_C 58 AI Connect a 10μF ceramic decoupling capacitor between this pin and pin 57.

Interface mode selection input.

PAR/SER 61 DI When low, the parallel interface is selected. When high, the serial interface is enabled.

Mode selection input.

HW/SW 62 DI When low, the hardware mode is selected and part works according to the settings of external pins. When high,

the software mode is selected in which the device is configured by writing into the control register.

Hardware mode (HW/SW = 0): Hardware mode (HW/SW = 0):

Internal reference enable input. Internal reference enable input.

When high, the internal reference is enabled (the When high, the internal reference is enabled (the reference

reference buffers are to be enabled). When low, buffers are to be enabled). When low, the internal reference

the internal reference is disabled and an external is disabled and an external reference should be applied at

REFEN/WR 63 DI reference is applied at REFIO. REFIO.

Software mode (HW/SW = 1): Write input.

The parallel data input is enabled, when CS and Software mode (HW/SW = 1): Connect to BGND or BVDD.

WR are low. The internal reference is enabled by The internal reference is enabled by CR bit C25 (REFEN).

the CR bit C25 (REFEN).

Data bit 15 (MSB) input/output

DB15 64 DIO Connect to BGND

Output is '0'for the ADS8557/8

CONVST_x

BUSY

(C20 = C21 = 0)

SCLK

ADS8556

SDO_x

tD1

tD2 tH2

tD4

SDI or

DCIN_x

tS1

tH1

Don’t Care Don’t

Care

tSCLK

132

CH_x0

MSB

tD3

CH_x1

LSB

CH_x1

D31 D0

D1D2

tCONV tACQ

tS3

XCLK

(C11 = 1)

tS3

ADS8556

ADS8557

ADS8558

SBAS404B –OCTOBER 2006–REVISED JANUARY 2012

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TIMING CHARACTERISTICS

Figure 2. Serial Operation Timing Diagram (All Three SDOs Active)

Serial Interface Timing Requirements(1)

Over recommended operating free-air temperature range at –40°C to +125°C, AVDD = 5V, and BVDD = 2.7V to 5.5V, unless

otherwise noted. ADS8556, ADS8557, ADS8558

TEST

PARAMETER CONDITION MIN TYP MAX UNIT

tACQ Acquisition time 280 ns

ADS8556 1.26 µs

tCONV Conversion time ADS8557 1.19 µs

ADS8558 1.09 µs

t1CONVST_x low time 20 ns

t2BUSY low to FS low time 0 ns

ADS8556 40 ns

t3Bus access finished to next conversion start time ADS8557 20 ns

ADS8558 0 ns

tD1 CONVST_x high to BUSY high delay 5 20 ns

tD2 FS low to SDO_x active delay 5 12 ns

tD3 SCLK rising edge to new data valid delay 15 ns

tD4 FS high to SDO_x 3-state delay 10 ns

tH1 Input data to SCLK falling edge hold time 5 ns

tH2 Output data to SCLK rising edge hold time 5 ns

tS1 Input data to SCLK falling edge setup time 3 ns

CONVST_x high to XCLK falling or rising edge setup

tS3 6 ns

time

tSCLK Serial clock period 0.0278 10 μs

(1) All input signals are specified with tR= tF= 1.5ns (10% to 90% of BVDD) and timed from a voltage level of (VIL + VIH)/2.

CONVST_A

CONVST_B

CONVST_C

BUSY

(C20 = C21 = 0)

DB[15:0]

tD1

tD5

tH3

tACQ

tCONV

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ADS8557

ADS8558

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SBAS404B –OCTOBER 2006–REVISED JANUARY 2012

Figure 3. Parallel Read Access Timing Diagram

Parallel Interface Timing Requirements (Read Access)(1)

Over recommended operating free-air temperature range at –40°C to +125°C, AVDD = 5V, and BVDD = 2.7V to 5.5V, unless

otherwise noted. ADS8556, ADS8557, ADS8558

TEST

PARAMETER CONDITION MIN TYP MAX UNIT

tACQ Acquisition time 280 ns

ADS8556 1.26 µs

tCONV Conversion time ADS8557 1.19 µs

ADS8558 1.09 µs

t1CONVST_x low time 20 ns

t2BUSY low to CS low time 0 ns

ADS8556 40 ns

Bus access finished to next conversion

t3ADS8557 20 ns

start time(2) ADS8558 0 ns

t4CS low to RD low time 0 ns

t5RD high to CS high time 0 ns

t6RD pulse width 30 ns

t7Minimum time between two read accesses 10 ns

tD1 CONVST_x high to BUSY high delay 5 20 ns

tD5 RD falling edge to output data valid delay 20 ns

tH3 Output data to RD rising edge hold time 5 ns

(1) All input signals are specified with tR= tF= 1.5ns (10% to 90% of BVDD) and timed from a voltage level of (VIL + VIH)/2.

(2) Refer to CS signal or RD, whichever occurs first.

DB[15:0]

tH4

tS2

[31:16]

t11

t10

[15:0]

[31:24]

[23:16]

[15:8]

[7:0]

WordMode

(WORD/BYTE=0)

By dte Mo e

(WORD/BYTE=1)

Don’t

Care

ADS8556

ADS8557

ADS8558

SBAS404B –OCTOBER 2006–REVISED JANUARY 2012

www.ti.com

Figure 4. Parallel Write Access Timing Diagram

Parallel Interface Timing Requirements (Write Access)(1)

Over recommended operating free-air temperature range at –40°C to +125°C, AVDD = 5V, and BVDD = 2.7V to 5.5V, unless

otherwise noted. ADS8556, ADS8557, ADS8558

PARAMETER MIN TYP MAX UNIT

t8CS low to WR low time 0 ns

t9WR low pulse width 15 ns

t10 WR high pulse width 10 ns

t11 WR high to CS high time 0 ns

tS2 Output data to WR rising edge setup time 5 ns

tH4 Data output to WR rising edge hold time 5 ns

(1) All input signals are specified with tR= tF= 1.5ns (10% to 90% of BVDD) and timed from a voltage level of (VIL + VIH)/2.

3.0

2.5

2.0

1.5

1.0

0.5

1.0

1.5

2.0

2.5

3.0

IntegralNonlinearity(LSB)

0 8190 16380 24570 32760 40950 49140 57330 65520

Code

AVDD =BVDD=5V

HVSS= 15V

HVDD=15V

f =Max

InternalReference

DATA

3.0

2.5

2.0

1.5

1.0

0.5

1.0

1.5

2.0

2.5

3.0

IntegralNonlinearity(LSB)

0 8190 16380 24570 32760 40950 49140 57330 65520

Code

AVDD =BVDD=5V

HVSS= 15V

HVDD=15V

f =Max

InternalReference

DATA

1.5

1.0

0.5

1.0

DifferentialNonlinearity(LSB)

0 8190 16380 24570 32760 40950 49140 57330 65520

Code

AVDD =BVDD=5V

HVSS= 15V

HVDD=15V

f =Max

InternalReference

DATA

1.5

1.0

0.5

1.0

DifferentialNonlinearity(LSB)

0 8190 16380 24570 32760 40950 49140 57330 65520

Code

AVDD =BVDD=5V

HVSS= 15V

HVDD=15V

f =Max

InternalReference

DATA

1.0

0.8

0.6

0.4

0.2

0.4

0.6

0.8

1.0

IntegralNonlinearity(LSB)

0 2000 4000 6000 8000 10000 12000 14000 16000

Code

AVDD =BVDD=5V

HVSS= 15V

HVDD=15V

f =Max

InternalReference

DATA

1.0

0.8

0.6

0.4

0.2

0.4

0.6

0.8

1.0

IntegralNonlinearity(LSB)

0 2000 4000 6000 8000 10000 12000 14000 16000

Code

AVDD =BVDD=5V

HVSS= 15V

HVDD=15V

f =Max

InternalReference

DATA

ADS8556

ADS8557

ADS8558

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SBAS404B –OCTOBER 2006–REVISED JANUARY 2012

TYPICAL CHARACTERISTICS

At +25°C, over entire supply voltage range, VREF = 2.5V (internal), and fDATA = maximum, unless otherwise noted.

INL vs CODE INL vs CODE

(ADS8556 ±10VIN Range) (ADS8556 ±5VIN Range)

Figure 5. Figure 6.

DNL vs CODE DNL vs CODE

(ADS8556 ±10VIN Range) (ADS8556 ±5VIN Range)

Figure 7. Figure 8.

INL vs CODE INL vs CODE

(ADS8557 ±10VIN Range) (ADS8557 ±5VIN Range)

Figure 9. Figure 10.

1.0

0.8

0.6

0.4

0.2

0.4

0.6

0.8

1.0

DifferentialNonlinearity(LSB)

0 2000 4000 6000 8000 10000 12000 14000 16000

Code

AVDD =BVDD=5V

HVSS= 15V

HVDD=15V

f =Max

InternalReference

DATA

1.0

0.8

0.6

0.4

0.2

0.4

0.6

0.8

1.0

DifferentialNonlinearity(LSB)

0 2000 4000 6000 8000 10000 12000 14000 16000

Code

AVDD =BVDD=5V

HVSS= 15V

HVDD=15V

f =Max

InternalReference

DATA

0.75

0.50

0.25

0.50

0.75

IntegralNonlinearity(LSB)

0 500 1000 1500 2000 2500

3000

3500 4000

Code

AVDD =BVDD=5V

HVSS= 15V

HVDD=15V

f =Max

InternalReference

DATA

0.5

0.4

0.3

0.2

0.1

0.2

0.3

0.4

0.5

DifferentialNonlinearity(LSB)

0 500 1000 1500 2000 2500

3000

3500 4000

Code

AVDD =BVDD=5V

HVSS= 15V

HVDD=15V

f =Max

InternalReference

DATA

OffsetError(mV)

-40 -25 -10 5 20 35

65 125

Temperature( C)°

80 95 110

0.75

0.50

0.25

0.50

0.75

GainError(%)

-40 -25 -10 5 20 35

65 125

Temperature( C)°

80 95 110

ADS8556

ADS8557

ADS8558

SBAS404B –OCTOBER 2006–REVISED JANUARY 2012

www.ti.com

TYPICAL CHARACTERISTICS (continued)

At +25°C, over entire supply voltage range, VREF = 2.5V (internal), and fDATA = maximum, unless otherwise noted.

DNL vs CODE DNL vs CODE

(ADS8557 ±10VIN Range) (ADS8557 ±5VIN Range)

Figure 11. Figure 12.

INL vs CODE DNL vs CODE

(ADS8558) (ADS8558)

Figure 13. Figure 14.

OFFSET ERROR vs TEMPERATURE GAIN ERROR vs TEMPERATURE

Figure 15. Figure 16.

Power-SupplyRejectionRatio(dB)

0 20 40 60 80 100

120

140 200

AVDDNoiseFrequency(kHz)

160 180

C =100nFonAVDD

SUPPLY

1.40

1.35

1.30

1.25

1.20

1.15

1.10

1.05

1.00

0.95

0.90

ConversionTime( s)m

-40 -25 -10 5 20 35

65 125

Temperature( C)°

80 95 110

ADS8556

ADS8557

ADS8558

5500

5000

4500

4000

3500

3000

2500

2000

1500

1000

500

NumberofOccurrences

-3-2-1 0 1

Code

AVDD=BVDD=5V

HVSS= 15V

HVDD=15V

8192Samples

Range=+4 V

InternalReference

T=+25 C

´REF

Signal-to-NoiseRatio(dB)

-40 -25 -10 5 20 35

65 125

Temperature( C)°

80 95 110

ADS8556

ADS8558

ADS8557

AVDD=BVDD=5V

HVSS= 15V,HVDD=15V

f =10kHz,f =Max

Range= 4 V

InternalReference

± ´

SIGNAL DATA

REF

Signal-to-NoiseRatioandDistortion(dB)

-40 -25 -10 5 20 35

65 125

Temperature( C)°

80 95 110

ADS8556

ADS8558

ADS8557

AVDD=BVDD=5V

HVSS= 15V,HVDD=15V

f =10kHz,f =Max

Range= 4 V

InternalReference

± ´

SIGNAL DATA

REF

-86

TotalHarmonicDistortion(dB)

-40 -25 -10 5 20 35

65 125

Temperature( C)°

80 95 110

ADS8556

ADS8558

ADS8557

AVDD=BVDD=5V,HVSS= 15V,HVDD=15V

f =10kHz,f =Max,Range= 4 V

InternalReference

± ´

SIGNAL DATA REF

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SBAS404B –OCTOBER 2006–REVISED JANUARY 2012

TYPICAL CHARACTERISTICS (continued)

At +25°C, over entire supply voltage range, VREF = 2.5V (internal), and fDATA = maximum, unless otherwise noted.

PSRR vs AVDD NOISE FREQUENCY CONVERSION TIME vs TEMPERATURE

Figure 17. Figure 18.

CODE HISTOGRAM

(8192 Hits) SNR vs TEMPERATURE

Figure 19. Figure 20.

SINAD vs TEMPERATURE THD vs TEMPERATURE

Figure 21. Figure 22.

100

Spurious-FreeDynamicRange(dB)

-40 -25 -10 5 20 35

65 125

Temperature( C)°

80 95 110

ADS8556

ADS8558

ADS8557

AVDD=BVDD=5V

HVSS= 15V,HVDD=15V

f =10kHz,f =Max

Range= 4 V

InternalReference

± ´

SIGNAL DATA

REF

100

120

140

160

180

Amplitude(dB)

0 25 50 75 100 125

150

175 250

Frequency(kHz)

200 225

AVDD=BVDD=5V

HVSS= 15V

HVDD=15V

f =500kSPS

f =10kHz

Range= 4 V

InternalReference

T=+25 C

± ´

SAMPLE

SIGNAL

REF

100

120

140

160

180

Amplitude(dB)

0 25 50 75 100 125

150

175 250

Frequency(kHz)

200 225

AVDD=BVDD=5V

HVSS= 15V,HVDD=15V

f =500kSPS

f =10kHz

Range= 2 V

InternalReference

T=+25 C

± ´

SAMPLE

SIGNAL

REF

120

115

110

105

100

Isolation(dB)

030 60 90 120 150

180

210 300

NoiseFrequency(kHz)

240 270

AVDD=BVDD=5V

HVSS= 15V

HVDD=15V

f =Max

Range= 2 V

InternalReference

± ´

DATA

REF

2.504

2.503

2.502

2.501

2.500

2.499

2.498

2.497

2.496

V (V)

REF

4.5 4.6 4.7 4.8 4.9 5.0

5.1

5.2 5.5

AVDD(V)

5.3 5.4

VREF

2.504

2.503

2.502

2.501

2.500

2.499

2.498

2.497

2.496

V (V)

REF

-40 -25 -10 5 20 35

65 125

Temperature( C)°

80 95 110

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TYPICAL CHARACTERISTICS (continued)

At +25°C, over entire supply voltage range, VREF = 2.5V (internal), and fDATA = maximum, unless otherwise noted.

FREQUENCY SPECTRUM

SFDR vs TEMPERATURE (2048-Point FFT, fIN = 10kHz, ±10VIN Range)

Figure 23. Figure 24.

FREQUENCY SPECTRUM CHANNEL-TO-CHANNEL ISOLATION vs

(2048-Point FFT, fIN = 10kHz, ±5VIN Range) INPUT NOISE FREQUENCY

Figure 25. Figure 26.

INTERNAL REFERENCE VOLTAGE vs INTERNAL REFERENCE VOLTAGE vs TEMPERATURE

ANALOG SUPPLY VOLTAGE (2.5V Mode) (2.5V Mode)

Figure 27. Figure 28.

3.005

3.004

3.003

3.002

3.001

3.000

2.999

2.998

2.997

2.996

2.995

V (V)

REF

-40 -25 -10 5 20 35

65 125

Temperature( C)°

80 95 110

IAVDD(mA)

-40 -25 -10 5 20 35

65 125

Temperature( C)°

80 95 110

f =Max

DATA

f =250kSPS(A-NAP)

DATA

AVDD=5V

InternalReference

IAVDD(mA)

0 45 90 135 180 225

270

315 630

SampleRate(kSPS)

360 405 450

NormalOperation

A-NAPMode

AVDD=5V

InternalReference

495 540 585

2.0

1.8

1.6

1.4

1.2

1.0

0.8

0.6

0.4

0.2

IBVDD(mA)

-40 -25 -10 5 20 35

65 125

Temperature( C)°

80 95 110

f =Max

DATA

f =250kSPS(A-NAP)

DATA

BVDD=5V

4.00

3.75

3.50

3.25

3.00

2.75

2.50

2.25

2.00

1.75

1.50

1.25

1.00

InputSupplyCurrent(mA)

-40 -25 -10 5 20 35

65 125

Temperature( C)°

80 95 110

IHVSS(f =Max)

DATA

HVSS= 15V

HVDD=15V

Range= 4 V

InternalReference

± ´ REF

IHVDD(f =Max)

DATA

IHVSS( )250kSPSA-NAP

IHVDD( )250kSPSA-NAP

4.5

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

InputSupplyCurrent(mA)

5 6 7 8 9 10

12 15

HVDD,|HVSS|(V)

13 14

IHVSS(f =Max)

DATA

IHVDD(f =Max)

DATA

IHVSS( )250kSPSA-NAP

IHVDD( )250kSPSA-NAP

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SBAS404B –OCTOBER 2006–REVISED JANUARY 2012

TYPICAL CHARACTERISTICS (continued)

At +25°C, over entire supply voltage range, VREF = 2.5V (internal), and fDATA = maximum, unless otherwise noted.

INTERNAL REFERENCE VOLTAGE vs TEMPERATURE

(3.0V Mode) ANALOG SUPPLY CURRENT vs TEMPERATURE

Figure 29. Figure 30.

ADS8556

ANALOG SUPPLY CURRENT vs DATA RATE BUFFER I/O SUPPLY CURRENT vs TEMPERATURE

Figure 31. Figure 32.

ADS8556 ADS8556

INPUT SUPPLY CURRENT vs TEMPERATURE INPUT SUPPLY CURRENT vs INPUT SUPPLY VOLTAGE

Figure 33. Figure 34.

3.6

3.3

3.0

2.7

2.4

2.1

1.8

1.5

1.2

0.9

0.6

0.3

IHVxx(mA)

090 180 270 630

DataRate(kSPS)

HVSS= 15V

HVDD=15V

Range= 4 V

± ´ REF

360 450 540

IHVSS(A-NAP)

IHVDD(A-NAP)

IHVSS

IHVDD

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TYPICAL CHARACTERISTICS (continued)

At +25°C, over entire supply voltage range, VREF = 2.5V (internal), and fDATA = maximum, unless otherwise noted.

ADS8556

INPUT SUPPLY CURRENT vs DATA RATE

Figure 35.

f =

-3dB

ln(2) (n+1)´

2 tp ´ ACQ

R <

SOURCE

tACQ

C ln(2) (n+1)´

-(R +R )

SER SW

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SBAS404B –OCTOBER 2006–REVISED JANUARY 2012

GENERAL DESCRIPTION

period, there is no further input current flow and the

The ADS8556/7/8 series include six 16-, 14-, and input impedance is greater than 1MΩ. To ensure a

12-bit analog-to-digital converters (ADCs) defined start condition, the sampling capacitors of the

respectively that operate based on the successive ADS8556/7/8 are pre-charged to a fixed internal

approximation register (SAR) principle. The voltage, before switching into sampling mode.

architecture is designed on the charge redistribution

principle, which inherently includes a To maintain the linearity of the converter, the inputs

sample-and-hold function. The six analog inputs are should always remain within the specified range of

grouped into three channel pairs. These channel HVSS –0.2V to HVDD + 0.2V.

pairs can be sampled and converted simultaneously, The minimum –3dB bandwidth of the driving

preserving the relative phase information of the operational amplifier can be calculated using

signals of each pair. Separate conversion start Equation 1:

signals allow simultaneous sampling on each channel

pair: on four channels or on all six channels.

These devices accept single-ended, bipolar analog

input signals in the selectable ranges of ±4VREF or where:

±2VREF with an absolute value of up to ±12V; see the n = 16, 14, or 12; nis the resolution of the

Analog Inputs section. ADS8556/7/8 (1)

The devices offer an internal 2.5V/3V reference With a minimum acquisition time of tACQ = 280ns, the

source followed by a 10-bit digital-to-analog converter required minimum bandwidth of the driving amplifier

(DAC) that allows the reference voltage VREF to be is 6.7MHz for the ADS8556, 6MHz for the ADS8557,

adjusted in 2.44mV or 2.93mV steps, respectively. or 5.2MHz for the ADS8558. The required bandwidth

The ADS8556/7/8 also offer a selectable parallel or can be lower if the application allows a longer

serial interface that can be used in hardware or acquisition time. A gain error occurs if a given

software mode; see the Device Configuration section application does not fulfill the bandwidth requirement

for details. shown in Equation 1.

A driving operational amplifier may not be required, if

ANALOG the impedance of the signal source (RSOURCE) fulfills

the requirement of Equation 2:

This section addresses the analog input circuit, the

ADCs and control signals, and the reference design

of the device.

Analog Inputs where:

n = 16, 14, or 12; nis the resolution of the ADC,

The inputs and the converters are of single-ended,

bipolar type. The absolute voltage range can be CS= 10pF is the sample capacitor value for VIN =

selected using the RANGE pin (in hardware mode) or ±4×VREF mode,

RANGE_x bits (in software mode) in the control RSER = 200Ωis the input resistor value,

reference set to 2.5V (CR bit C18 = 0), the input (2)

voltage range can be ±10V or ±5V. With the

reference source set to 3V (CR bit C18 = 1), an input With tACQ = 280ns, the maximum source impedance

voltage range of ±12V or ±6V can be configured. The should be less than 2.0kΩfor the ADS8556, 2.3kΩ

logic state of the RANGE pin is latched with the for the ADS8557, and 2.7kΩfor the ADS8558 in VIN

falling edge of BUSY (if CR bit C20 = 0). =±4VREF mode or less than 0.8kΩfor the ADS8556,

1.0kΩfor the ADS8557, and 1.2kΩfor the ADS8558

The input current on the analog inputs depends on in VIN =±2VREF mode. The source impedance can be

the actual sample rate, input voltage, and signal higher if the application allows longer acquisition time.

source impedance. Essentially, the current into the

analog inputs charges the internal capacitor array Analog-to-Digital Converter (ADC)

only during the sampling period (tACQ). The source of

the analog input voltage must be able to charge the The devices include six ADCs that operate with either

input capacitance of 10pF in ±4VREF mode or 20pF in an internal or an external conversion clock. The

±2VREF to a 12-, 14-, 16-bit accuracy level within the conversion time can be as low as 1.09μs with internal

acquisition time of 280ns at maximum data rate; see conversion clock (ADS8558). When an external clock

the Equivalent Input Circuit. During the conversion and reference are used, the minimum conversion

time is 925ns.

CONVST_A

CONVST_C

BUSY

(C20=C21=0)

DB[15:0]

CONVST_B

DB[15:0]

CONVST_A

CONVST_B

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Conversion Clock next edge of the conversion clock. CONVST_x should

remain high during the entire conversion cycle; this is

The device uses either an internally-generated or an while the BUSY signal remains active. A falling edge

external (XCLK) conversion clock signal (in software during an ongoing conversion puts the related ADC

mode only). In default mode, the device generates an pair into partial power-down mode (see the Reset and

internal clock. When the CLKSEL bit is set high (bit Power-Down Modes section for more details).

C11 in the CR), an external conversion clock of up to

20MHz (max) can be applied on pin 27. In both For simultaneous sampling, it is recommended to

cases, 18.5 clock cycles are required for a complete connect all associated CONVST_x pins together. If

conversion including the pre-charging of the sample the CONVST_x signals are not tied together, a

capacitors. The external clock can remain low maximum skew of 4 ns must be ensured for all three

between conversions. signals in any order. A CONVST_x signal issued

during an ongoing conversion on any channel is

The conversion clock duty cycle should be 50%. blocked, except in sequential mode (see the

However, the ADS8556/7/8 function properly with a Sequential Mode section for more details).

duty cycle between 45% and 55%. If a parallel interface is used, the behavior of the

CONVST_x output port depends on which CONVST_x signals

have been issued. Figure 36 shows examples of

The analog inputs of each channel pair (CH_x0/1) are different scenarios.

held with the rising edge of the corresponding

CONVST_x signal. Only in software mode (except

sequential mode), CONVST_A is used for all six

ADCs. The conversion automatically starts with the

NOTE: Boxed areas indicate the minimum required frame to acquire all data.

Figure 36. Data Output versus CONVST_x

f =

-3dB

ln(2)

2 tp ´ CONV

V =

REF

Range (Code+1)´

1024

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BUSY/INT Table 1 lists some examples of internal reference

DAC settings with a reference range set to 2.5V.

The BUSY signal indicates if a conversion is in However, to ensure proper performance, the DAC

progress. It goes high with a rising edge of any output voltage should not be programmed below

CONVST_x signal and goes low when the output 0.5V.

data of the last channel pair are available in the

respective output register. The readout of the data The buffered output of the DAC should be decoupled

can be initiated immediately after the falling edge of with a 100nF capacitor (minimum); for best

BUSY. A falling edge of a CONVST_x input during an performance, a 470nF capacitor is recommended. If

ongoing conversion (when BUSY is high) powers the internal reference is placed into power-down

down the corresponding ADC pair. (default), an external reference voltage can drive the

REFIO pin.

In sequential mode, the BUSY signal goes low only

for one clock cycle. See the Sequential Mode section The voltage at the REFIO pin is buffered with three

for more details. internal amplifiers, one for each ADC pair. The output

of each buffer needs to be decoupled with a 10μF

The polarity of the BUSY/INT signal can be changed capacitor between pin pairs 53 and 54, 55 and 56,

using CR bit C20. and 57 and 58. The 10μF capacitors are available as

ceramic 0805-SMD components and in X5R quality.

Reference The internal reference buffers can be powered down

The ADS8556/7/8 provides an internal, low-drift 2.5V to decrease the power dissipation of the device. In

reference source. To increase the input voltage this case, external reference drivers can be

range, the reference voltage can be switched to 3V connected to REFC_A, REFC_B, and REFC_C pins.

mode using the VREF bit (bit C18 in the CR). The With 10μF decoupling capacitors, the minimum

reference feeds a 10-bit string-DAC controlled by bits required bandwidth can be calculated using

C[9:0] in the control register. The buffered DAC Equation 4:

output is connected to the REFIO pin. In this way, the

voltage at this pin is programmable in 2.44mV

(2.92mV in 3V mode) steps and adjustable to the (4)

application needs without additional external With the minimum tCONV of 1.09μs, the external

components. The actual output voltage can be reference buffers require a minimum bandwidth of

calculated using Equation 3:102kHz.

Table 1. DAC Setting Examples (2.5V Operation)

where: DECIMAL BINARY HEXADECIMAL

VREF OUT (V) CODE CODE CODE

Range = the chosen maximum reference voltage 0.500 204 00 1100 1100 CC

output range (2.5V or 3V), 1.25 511 01 1111 1111 1FF

Code = the decimal value of the DAC register

content (3) 2.500 1023 11 1111 1111 3FF

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DIGITAL significant bit (MSB), the output data are changed at

the rising edge of SCLK, so that the host processor

This section describes the digital control and the can read it at the following falling edge. Output data

timing of the device in detail. of the ADS8557 and ADS8558 maintain the 16-bit

format with leading zeros.

Device Configuration Serial data input SDI are latched at the falling edge of

Depending on the desired mode of operation, the SCLK.

ADS8556/7/8 can be configured using the external

pins and/or the control register ( CR), as shown in The serial interface can be used with one, two, or

Table 2. three output ports. These ports are enabled with pins

SEL_A, SEL_B, and SEL_C. If all three serial data

Parallel Interface output ports (SDO_A, SDO_B, and SDO_C) are

selected, the data can be read with either two 16-bit

To use the device with the parallel interface, the data transfers or with one 32-bit data transfer. The

PAR/SER pin should be held low. The maximum data of channels CH_x0 are available first, followed

achievable data throughput rate using the internal by data from channels CH_x1. The maximum

clock is 630kSPS for the ADS8556, 670kSPS for the achievable data throughput rate is 450kSPS for the

ADS8557, and 730kSPS for the ADS8558 in this ADS8556, 470kSPS for the ADS8557, and 500kSPS

case. for the ADS8558 in this case.

Access to the ADS8556/7/8 is controlled as illustrated If the application allows a data transfer using two

in Figure 3 and Figure 4.ports only, SDO_A and SDO_B outputs are used.

The device outputs data from channel CH_A0

The device can either operate with a 16-bit followed by CH_A1 and CH_C0 on SDO_A, while

(WORD/BYTE pin set low) or an 8-bit (WORD/BYTE data from channel CH_B0 followed by CH_B1 and

pin set high) parallel interface. If 8-bit operation is CH_C1 occurs on SDO_B. In this case, a data

used, the HBEN pin selects if the low-byte (DB7 low) transfer of three consecutive 16-bit words or one

or the high-byte (DB7 high) is available on the data continuous 48-bit word is supported. The maximum

output DB[15:8] first. achievable data throughput rate is 375kSPS for the

ADS8556, 390kSPS for the ADS8557, and 400kSPS

Serial Interface for the ADS8558.

The serial interface mode is selected by setting the The output SDO_A is selected if only one serial data

PAR/SER pin high. In this case, each data transfer port is used in the application. The data are available

starts with the falling edge of the frame in the following order: CH_A0, CH_A1, CH_B0,

synchronization input (FS). The conversion results CH_B1, CH_C0, and, finally CH_C1. Data can be

are presented on the serial data output pins SDO_A, read using six 16-bit transfers, three 32-bit transfers,

SDO_B, and SDO_C depending on the selections or a single 96-bit transfer. The maximum achievable

made using the SEL_x pins. Starting with the most data throughput rate is 250kSPS for the ADS8556/7

and 260kSPS for the ADS8558 in this case.

Figure 2 (the serial operation timing diagram) and

Figure 37 show all possible scenarios in more detail.

Table 2. ADS8556/7/8 Configuration Settings

HARDWARE MODE (HW/SW = 0) SOFTWARE MODE (HW/SW = 1)

CONVERSION START CONTROLLED BY SEPARATE CONVERSION START CONTROLLED BY CONVST_A

INTERFACE MODE CONVST_x PINS PIN ONLY, EXCEPT IN SEQUENTIAL MODE

Configuration using control register bits C[31:0] only;

Parallel Configuration using pins, optionally, control bits C[22:18], status of pins 27 (only if used as RANGE input) and 63 is

(PAR/SER = 0) C[15:13], and C[9:0] disregarded

Configuration using control register bits C[31:0] only;

status of pins 1, 27 (only if used as RANGE input), and

Serial Configuration using pins, optionally, control bits C[22:18], 63 is disregarded; each access requires a control register

(PAR/SER = 1) C[15:13], and C[9:0]; bits C[31:24] are disregarded update via SDI (see the Serial Interface section for

details)

CONVST_A

CONVST_B

CONVST_C

BUSY

(C20=C21=0)

SDO_A

CHA0

CHB0

CHA1

CHB1

CHC0

CHC1

CHA0 CHA1 CHB0 CHB1 CHC0 CHC1

SDO_A

SDO_B

SEL_A =1,SEL B=_ SEL_C 0=

SEL_A =SEL_B 1,= SEL_C 0= 4 SCLK8 s

9 SCLK6 s

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SBAS404B –OCTOBER 2006–REVISED JANUARY 2012

Figure 37. Serial Interface: Data Output with One or Two Active SDOs

word and byte modes. In word mode, the first write

Hardware Mode access updates only the upper eight bits and stores

the lower eight bits (C[23:16]) for an update that

With the HW/SW input (pin 62) set low, the device takes place with the second write access along with

functions are controlled via the pins and, optionally, C[15:0].

control register bits C[22:18], C[15:13], and C[9:0]. If the serial interface is used, input data containing

It is possible to generally use the part in hardware control register contents are required with each read

mode but to switch it into software mode to initialize access to the device in this mode (combined

or adjust the control register settings (for example, read/write access). For initialization purposes, all 32

the internal reference DAC) and back to hardware bits of the register should be set (bit C16 must be set

mode thereafter. to '1' during that access to allow the update of the

entire register content). To minimize switching noise

Software Mode on the interface, an update of the first eight bits

When the HW/SW input is set high, the device (C[31:24]) with the remaining bits held low can be

operates in software mode with functionality set only performed thereafter.

by the control register bits (corresponding pin settings Figure 38 illustrates the different control register

are ignored). update options.

If parallel interface is used, an update of all control

write accesses on pins DB[15:0] in word mode or four Default Value = 0x000003FF

8-bit accesses on pins DB[15:8] in byte mode (to The control register settings can only be changed in

avoid losing data, the entire sequence must be software mode and are not affected when switching

finished before starting a new conversion). CS should to hardware mode thereafter. The register values are

be held low during the two or four write accesses to independent from input pin settings. Changes are

completely update the configuration register. It is also active with the rising edge of WR in parallel interface

possible to update only the upper eight bits (C[31:24]) mode or with the 32nd falling SCLK edge of the

using a single write access and pins DB[15:8] in both access in which the register content has been

updated in serial mode. Optionally, the register can

also be partially updated by writing only the upper

eight bits (C[31:24]). The CR content is defined in

Table 3.

RESET

(orPower-Up)

BUSY

(C20=C21=0)

SDI C[31:0]

InitializationData

[31:24]

DB[15:0] C

[31:16]

[15:0]

[31:24]

[23:16]

DB[15:8] C

[15:8]

[7:0]

[31:24]

PAR/SER=1

PAR/SER=0;WORD/BYTE=0

PAR/SER=0;WORD/BYTE=1

[15:0]

[23:16]

InitializationData

ContinuousUpdate ContinuousUpdate

Update

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Figure 38. Control Register Update Options

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Table 3. Control Register (CR)

ACTIVE IN

BIT NAME DESCRIPTION HARDWARE MODE

0 = Channel pair C disabled for next conversion (default)

C31 CH_C No

1 = Channel pair C enabled

0 = Channel pair B disabled for next conversion (default)

C30 CH_B No

1 = Channel pair B enabled

0 = Channel pair A disabled for next conversion (default)

C29 CH_A No

1 = Channel pair A enabled

0 = Input voltage range selection for channel pair C: 4VREF (default)

C28 RANGE_C No

1 = Input voltage range selection for channel pair C: 2VREF

0 = Input voltage range selection for channel pair B: 4VREF (default)

C27 RANGE_B No

1 = Input voltage range selection for channel pair B: 2VREF

0 = Input voltage range selection for channel pair A: 4VREF (default)

C26 RANGE_A No

1 = Input voltage range selection for channel pair A: 2VREF

0 = Internal reference source disabled (default)

C25 REFEN No

1 = Internal reference source enabled

0 = Internal reference buffers enabled (default)

C24 REFBUF No

1 = Internal reference buffers disabled

0 = Sequential convert start mode disabled (default)

C23 SEQ No

1 = Sequential convert start mode enabled (bit 11 must be '1' in this case)

0 = Normal operation (default)

C22 A-NAP Yes

1 = Auto-NAP feature enabled

0 = BUSY/INT pin in normal mode (BUSY) (default)

C21 BUSY/INT Yes

1 = BUSY/INT pin in interrupt mode (INT)

0 = BUSY active high while INT active low (default)

C20 BUSY L/H Yes

1 = BUSY active low while INT active high

C19 Don’t use This bit is always set to '0' —

0 = Internal reference voltage: 2.5V (default)

C18 VREF Yes

1 = Internal reference voltage: 3V

0 = Normal operation (conversion results available on SDO_x) (default)

C17 READ_EN Yes

1 = Control register contents output on SDO_x with next access

0 = Control register bits C[31:24] update only (serial mode only) (default)

C16 C23:0_EN Yes

1 = Entire control register update enabled (serial mode only)

0 = Normal operation (default)

C15 PD_C Yes

1 = Power-down for channel pair Cenabled (bit 31 must be '0' in this case)

0 = Normal operation (default)

C14 PD_B Yes

1 = Power-down for channel pair Benabled (bit 30 must be '0' in this case)

0 = Normal operation (default)

C13 PD_A Yes

1 = Power-down for channel pair Aenabled (bit 29 must be '0' in this case)

C12 Don't use This bit is always '0' —

0 = Normal operation with internal conversion clock (mandatory in hardware mode) (default)

C11 CLKSEL No

1 = External conversion clock (applied through pin 27) used

0 = Normal operation (default)

C10 CLKOUT_EN No

1 = Internal conversion clock available at pin 27

C9 REFDAC[9] Bit 9 (MSB) of reference DAC value; default = 1 Yes

C8 REFDAC[8] Bit 8 of reference DAC value; default = 1 Yes

C7 REFDAC[7] Bit 7 of reference DAC value; default = 1 Yes

C6 REFDAC[6] Bit 6 of reference DAC value; default = 1 Yes

C5 REFDAC[5] Bit 5 of reference DAC value; default = 1 Yes

C4 REFDAC[4] Bit 4 of reference DAC value; default = 1 Yes

C3 REFDAC[3] Bit 3 of reference DAC value; default = 1 Yes

C2 REFDAC[2] Bit 2 of reference DAC value; default = 1 Yes

C1 REFDAC[1] Bit 1 of reference DAC value; default = 1 Yes

C0 REFDAC[0] Bit 0 (LSB) of reference DAC value; default = 1 Yes

CONV TS _A

CONV TS _B

CONV TS _C

BUSY

(C20=0)

tCCLK

EOC(1)

CHAx

EOC(1)

CHBx

EOC(1)

CHCx

D[15:0]

XCLK

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Daisy-Chain Mode (in Serial Mode Only)

The serial interface of the ADS8556/7/8 supports a

daisy-chain feature that allows cascading of multiple

devices to minimize the board space requirements

and simplify routing of the data and control lines. In

this case, pins DB5/DCIN_A, DB4/DCIN_B, and

DB3/DCIN_C are used as serial data inputs for

channels A, B, and C, respectively. Figure 40 shows

an example of a daisy-chain connection of three

devices sharing a common CONVST line to allow

simultaneous sampling of 18 analog channels along

with the corresponding timing diagram. To activate

the daisy-chain mode, the DCEN pin must be pulled

high. As a result of the time specifications tS1, tH1, and

tD3, the maximum SCLK frequency that may be used

in daisy-chain mode is 27.78MHz (assuming 50%

duty cycle).

Sequential Mode (in Software Mode with External (1) EOC = end of conversion (internal signal).

Conversion clock Only) Figure 39. Sequential Mode Timing

The three channel pairs of the ADS8556/7/8 can be

run in sequential mode, with the corresponding

CONVST_x signals interleaved, when an external Output Data Format

clock is used. To activate the device in sequential The data output format of the ADS8556/7/8 is binary

mode, CR bits C11 (CLKSEL) and C23 (SEQ) must twos complement, as shown in Table 4.

be asserted. In this case, the BUSY output indicates

a finished conversion by going low (when C20 = 0) or For the ADS8557, which delivers 14-bit conversion

high (when C20 = 1) for only a single conversion results, the leading two bits of the 16-bit frame are '0'

clock cycle in case of ongoing conversions of any in the serial interface mode. In parallel interface

other channel pairs. Figure 39 shows the behavior of mode, the output pins DB[15:14] are held low.

the BUSY output in this mode. Each conversion start Respectively, as the ADS8558 outputs 12 bits of

should be initiated during the high phase of the data, the first four bits of a serial 16-bit frame are

external clock, as shown in Figure 39. The minimum zeros, in parallel interface mode the output pins

time required between two CONVST_x pulses is the DB[15:12] are held low.

time required to read the conversion result of a

channel (pair).

Table 4. Output Data Format

BINARY CODE (HEXADECIMAL CODE)

DESCRIPTION INPUT VOLTAGE VALUE ADS8556 ADS8557 ADS8558

0111 1111 1111 1111 0001 1111 1111 1111 0000 0111 1111 1111

Positive full-scale +4VREF or +2VREF (7FFF) (1FFF) (7FF)

0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000

Midscale + 0.5LSB VREF/(2 ×resolution) (0000) (0000) (0000)

1111 1111 1111 1111 0011 1111 1111 1111 0000 1111 1111 1111

Midscale –0.5LSB –VREF/(2 ×resolution) (FFFF) (3FFF) (FFF)

1000 0000 0000 0000 0010 0000 0000 0000 0000 1000 0000 0000

Negative full-scale –4VREF or –2VREF (8000) (2000) (800)

CONVST

BUSY

(C20 = C21 = 0)

SDO_x #3 Don’t Care 16-Bit Data CHx0

ADS8556 #3

ADS8556

CONVST_A

SCLK

SDO_A

SDO_B

SDO_C

ADS8556

SDO_A

SDO_B

SDO_C

ADS8556

SDO_A

SDO_B

SDO_C

DCIN_A

DCIN_B

DCIN_C

DC = 0

CONVST_A

SCLK

CONVST_A

SCLK

CONVST

SCLK

16-Bit Data CHx1

ADS8556 #3

16-Bit Data CHx0

ADS8556 #2

16-Bit Data CHx1

ADS8556 #2

16-Bit Data CHx0

ADS8556 #1

16-Bit Data CHx1

ADS8556 #1

DCIN_A

DCIN_B

DCIN_C

Processing

Unit

DC = 1

EN DC = 1

UndefinedZone

0.400

0.125

AVDD(V)

t(s)

5.500

5.000

4.000

3.000

2.000

1.000

1.500

SpecifiedSupply

VoltageRange

POR

TriggerLevel

0.350

4.500

ADS8556

ADS8557

ADS8558

www.ti.com

SBAS404B –OCTOBER 2006–REVISED JANUARY 2012

Figure 40. Example of Daisy-Chaining Three ADS8556s

Reset and Power-Down Modes

The device supports two reset mechanisms: a

power-on reset (POR) and a pin-controlled reset

(RESET) that can be issued using pin 28. Both the

POR and RESET act as a master reset that causes

any ongoing conversion to be interrupted, the control

channels to be switched into sample mode.

When the device is powered up, the POR sets the

device in default mode when AVDD reaches 1.5V.

When the device is powered down, the POR circuit

requires AVDD to remain below 125mV at least

350ms to ensure proper discharging of internal

capacitors and to ensure correct behavior of the

device when powered up again. If the AVDD drops

below 400mV but remains above 125mV (see the

undefined zone in Figure 41), the internal POR

capacitor does not discharge fully and the device

requires a pin-controlled reset to perform correctly Figure 41. POR: Relevant Voltage Levels

after the recovery of AVDD.

BUSY

ADCCH_Bx

CONVST_A/C

ACQ CONV Power-Down ACQ CONV ACQ

ACQ CONV ACQ CONV ACQ

ADCCH_Ax/Cx

RESET

6 t´CCLK Min

CONVST_B

ADS8556

ADS8557

ADS8558

SBAS404B –OCTOBER 2006–REVISED JANUARY 2012

www.ti.com

The entire device, except the digital interface, can be results). The next rising edge of the CONVST_x

powered down by pulling the STBY pin low (pin 24). signal should be issued at least six conversion cycle

As the digital interface section remains active, data periods after the reset pulse and starts a new

can be retrieved while in stand-by mode. To power conversion, as shown in Figure 42. The internal

the part on again, the STBY pin must be brought reference remains active during the partial

high. The device is ready to start a new conversion power-down mode.

after 10ms required to activate and settle the internal The auto-NAP power-down mode is enabled by

circuitry. This user-controlled approach can be used asserting the A-NAP bit (C22) in the control register.

in applications that require lower data throughput If the auto-NAP mode is enabled, the ADS8556/7/8

rates and lowest power dissipation. The content of automatically reduce the current requirement to 6mA

CR is not changed during standby mode. It is not after finishing a conversion; thus, the end of

required to perform a pin-controlled reset after conversion actually activates the power-down mode.

returning to normal operation. Triggering a new conversion by applying a positive

While the standby mode impacts the entire device, CONVST_x edge puts the device back into normal

each device channel pair can also be individually operation, starts the acquisition of the analog input,

switched off by setting control register bits C[15:13] and automatically starts a new conversion six

(PD_x). When reactivated, the relevant channel pair conversion clock cycles later. Therefore, a complete

requires 10ms to fully settle before starting a new conversion cycle takes 24.5 conversion clock cycles;

conversion. The internal reference remains active, thus, the maximum throughput rate in auto-NAP

except all channels are powered down at the same power-down mode is reduced to a maximum of

time. 380kSPS for the ADS8556, 395kSPS for the

ADS8557, and 420kSPS for the ADS8558 in serial

In partial power-down mode, each of the three mode. In parallel mode, the maximum data rates are

channel pairs of the ADS8556/7/8 can be individually 500kSPS for the ADS8556, 530kSPS for the

put into a power-saving condition that reduces the ADS8557, and 580kSPS for the ADS8558. The

current requirement to 2mA per channel pair by internal reference remains active during the auto-NAP

bringing the corresponding CONVST_x signal low mode. Table 5 compares the analog current

during an ongoing conversion when BUSY is high. requirements of the devices in the different modes.

The relevant channel pair is activated again by

issuing a RESET pulse (to avoid loss of data from the

active channels, this RESET pulse should be

generated after retrieving the latest conversion

Figure 42. Partial Power-Down

ADS8556

ADS8557

ADS8558

www.ti.com

SBAS404B –OCTOBER 2006–REVISED JANUARY 2012

Table 5. Maximum Analog Current (IAVDD) Demand of the ADS8556/7/8

NORMAL

OPERATION POWER-UP POWER-UP

ANALOG TO TO NORMAL TO NEXT

OPERATIONAL CURRENT ACTIVATED POWER- OPERATION CONVERSION

MODE (IAVDD) ENABLED BY BY DOWN DELAY RESUMED BY DELAY START TIME DISABLED BY

12mA/channel

Normal operation pair (maximum Power on CONVST_x ————Power off

data rate)

Partial CONVST_x

2mA (channel At falling edge

power-down of Power on low while RESET pulse Immediate 6 ×tCCLK Power off

pair x) of BUSY

channel pair x BUSY is high

A-NAP = 1 (CR Each end of At falling edge A-NAP = 0 (CR

Auto-NAP 6mA CONVST_x Immediate 6 ×tCCLK

bit) conversion of BUSY bit)

Immediate after

Power-down of 16μA (channel PD_x = 1 (CR PD_x = 0 (CR

HW/SW = 1 Immediate completing 10ms HW/SW = 0

channel pair x pair x) bit) bit) register update

Stand-by 50μA Power on STBY = 0 Immediate STBY = 1 Immediate 10ms Power off

The AVDD supply provides power to the internal

circuitry of the ADC. It can be set in the range of 4.5V

GROUNDING to 5.5V. Because the supply current of the device is

All GND pins should be connected to a clean ground typically 30mA, it is not possible to use a passive

reference. This connection should be kept as short as filter between the digital board supply of the

possible to minimize the inductance of this path. It is application and the AVDD pin. A linear regulator is

recommended to use vias connecting the pads recommended to generate the analog supply voltage.

directly to the ground plane. In designs without Each AVDD pin should be decoupled to AGND with a

ground planes, the ground trace should be kept as 100nF capacitor. In addition, a single 10μF capacitor

wide as possible. Avoid connections that are too should be placed close to the device but without

close to the grounding point of a microcontroller or compromising the placement of the smaller capacitor.

digital signal processor. Optionally, each supply pin can be decoupled using a

1μF ceramic capacitor without the requirement for a

Depending on the circuit density on the board, 10μF capacitor.

placement of the analog and digital components, and

the related current loops, a single solid ground plane The BVDD supply is only used to drive the digital I/O

for the entire printed circuit board (PCB) or a buffers and can be set in the range of 2.7V to 5.5V.

dedicated analog ground area may be used. In case This range allows the device to interface with most

of a separated analog ground area, ensure a state-of-the-art processors and controllers. To limit

low-impedance connection between the analog and the noise energy from the external digital circuitry to

digital ground of the ADC by placing a bridge the device, BVDD should be filtered. A 10Ωresistor

underneath (or next) to the ADC. Otherwise, even can be placed between the external digital circuitry

short undershoots on the digital interface lower and the device, because the current drawn is typically

than –300mV lead to the conduction of ESD diodes below 2mA (depending on the external loads). A

causing current flow through the substrate and bypass ceramic capacitor of 1μF (or alternatively, a

degrading the analog performance. pair of 100nF and 10μF capacitors) should be placed

between the BVDD pin and pin 8.

During PCB layout, care should be taken to avoid any

return currents crossing sensitive analog areas or The high-voltage supplies (HVSS and HVDD) are

signals. connected to the analog inputs. Noise and glitches on

these supplies directly couple into the input signals.

SUPPLY Place a 100nF ceramic decoupling capacitor, located

as close to the device as possible, between each of

The ADS8556/7/8 require four separate supplies: the pins 30, 31, and AGND. An additional 10μF capacitor

analog supply for the ADC (AVDD), the buffer I/O is used that should be placed close to the device but

supply for the digital interface (BVDD), and the without compromising the placement of the smaller

high-voltage supplies driving the analog input circuitry capacitor.

(HVDD and HVSS). Generally, there are no specific

requirements with regard to the power sequencing of Figure 43 shows a layout recommendation for the

the device. However, when HVDD is supplied before ADS8556/7/8 along with the proper decoupling and

AVDD, the internal ESD structure conducts, reference capacitor placement and connections.

increasing IHVDD beyond the specified value.

ADS8556/7/8

TopView

BVDD

ToAVDD

HVSS/HVDD

0.1 Fm

ToAVDD ToAVDD

AVDD

0.1 Fm

ToAVDD

0.1

ToA DVD

0.1 Fm

10 Fm

0.1 Fm

10 Fm

LEG DEN

TOPlayer;copperpourandtraces

Lower layer;AGNDarea

Lower layer;BGNDarea

Via

10 Fm10 Fm10 Fm

AVDD

AGND

AVDD

AGND

AVDD

64 63 62 61

AVDD

AGND

AVDD

AGND

BGND

BVDD

17 18 19 20 23 29

AVDD

AGND

HVSS

HVDD

AGND

21 22

0.1

AVDDSource

ToDUT

0.1 Fm

0.47 Fm

ADS8556

ADS8557

ADS8558

SBAS404B –OCTOBER 2006–REVISED JANUARY 2012

www.ti.com

(1) All 0.1μF, 0.47μF, and 1μF capacitors should be placed as close to the ADS8556/7/8 as possible.

(2) All 10μF capacitors should be close to the device but without compromising the placement of the smaller capacitors.

Figure 43. Layout Recommendation

OPA2211

HVDD

BVDD

AGND

Input #1

Input #2

HVSS

AGND

CH_A0

CH_A1 RANGE

STBY

REF /WR

10 Fm

AGND

REFC_A

REFC_B CONVST_B

CONVST_C

RESET

DB[15:0]

CONVST_A

0.47 Fm

10 Fm

AGND

REFIO

REFC_C

OPA2211

HVDD

AGND

Input #3

Input #4

HVSS

AGND

CH_B0

CH_B1

OPA2211

HVDD

AGND

Input #5

Input #6

HVSS

AGND

CH_C0 PAR/SER

CH_C1

HW/SW

WORD/BYTE

BGND

Host

Controller

ADS8556

AVDD

AGND

AVDD

BVDD

BGND

HVSS

AGND

HVDD

AVDD

BGND

AVDD

0.1 Fm

10 Fm

0.1 Fm

0.1 FmAGND

1 Fm

10 Fm

AGND

BVDD

HVSS

ADS8556

ADS8557

ADS8558

www.ti.com

SBAS404B –OCTOBER 2006–REVISED JANUARY 2012

APPLICATION INFORMATION The actual values of the resistors and capacitors

The minimum configuration of the ADS8556/7/8 in depend on the bandwidth and performance

parallel mode is shown in Figure 44. In this case, the requirements of the application. For highest data rate,

BUSY signal is not used while the SW generates the it is recommended to use a filter capacitor value of

required signals in a timely manner. TI’sOPA2211 is 1nF and a series resistor of 22Ωto fulfill the settling

used as an input driver, supporting bandwidth that requirements to an accuracy level of 16 bits within the

allows running the device at the maximum data rate. acquisition time of 280ns.

Figure 44. Minimum Configuration in Parallel Interface Mode

ADS8556

ADS8557

ADS8558

SBAS404B –OCTOBER 2006–REVISED JANUARY 2012

www.ti.com

REVISION HISTORY

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision A (August 2009) to Revision B Page

•Updated Figure 2 ................................................................................................................................................................ 14

•Changed unit column for all tCONV rows in the Serial Interface Timing Requirements table ............................................... 14

•Added tS3 row to Serial Interface Timing Requirements table ............................................................................................ 14

•Updated Figure 3 ................................................................................................................................................................ 15

•Changed unit column for all tCONV rows in Parallel Interface Timing Requirements (Read Access) table ......................... 15

•Changed second paragraph of CONVST_x section ........................................................................................................... 24

•Changed minimum bandwidth value in last sentence of Reference section ...................................................................... 25

•Updated Figure 40 .............................................................................................................................................................. 31

•Updated Figure 44 .............................................................................................................................................................. 35

PACKAGE OPTION ADDENDUM

www.ti.com 30-Nov-2011

Addendum-Page 1

PACKAGING INFORMATION

Orderable Device Status (1) Package Type Package

Drawing Pins Package Qty Eco Plan (2) Lead/

Ball Finish MSL Peak Temp (3) Samples

(Requires Login)

ADS8556IPM ACTIVE LQFP PM 64 160 Green (RoHS

& no Sb/Br) CU NIPDAU Level-3-260C-168 HR

ADS8556IPMR ACTIVE LQFP PM 64 1000 Green (RoHS

& no Sb/Br) CU NIPDAU Level-3-260C-168 HR

ADS8557IPM ACTIVE LQFP PM 64 160 Green (RoHS

& no Sb/Br) CU NIPDAU Level-3-260C-168 HR

ADS8557IPMR ACTIVE LQFP PM 64 1000 Green (RoHS

& no Sb/Br) CU NIPDAU Level-3-260C-168 HR

ADS8558IPM ACTIVE LQFP PM 64 160 Green (RoHS

& no Sb/Br) CU NIPDAU Level-3-260C-168 HR

ADS8558IPMR ACTIVE LQFP PM 64 1000 Green (RoHS

& no Sb/Br) CU NIPDAU Level-3-260C-168 HR

(1) The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability

information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that

lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between

the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight

in homogeneous material)

(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

PACKAGE OPTION ADDENDUM

www.ti.com 30-Nov-2011

Addendum-Page 2

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package

Type Package

Drawing Pins SPQ Reel

Diameter

(mm)

Reel

Width

W1 (mm)

(mm) B0

(mm) K0

(mm) P1

(mm) W

(mm) Pin1

Quadrant

ADS8556IPMR LQFP PM 64 1000 330.0 24.4 13.0 13.0 2.1 16.0 24.0 Q2

ADS8557IPMR LQFP PM 64 1000 330.0 24.4 13.0 13.0 2.1 16.0 24.0 Q2

ADS8558IPMR LQFP PM 64 1000 330.0 24.4 13.0 13.0 2.1 16.0 24.0 Q2

PACKAGE MATERIALS INFORMATION

www.ti.com 14-Jul-2012

Pack Materials-Page 1

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

ADS8556IPMR LQFP PM 64 1000 367.0 367.0 45.0

ADS8557IPMR LQFP PM 64 1000 367.0 367.0 45.0

ADS8558IPMR LQFP PM 64 1000 367.0 367.0 45.0

PACKAGE MATERIALS INFORMATION

www.ti.com 14-Jul-2012

Pack Materials-Page 2

MECHANICAL DATA

MTQF008A – JANUARY 1995 – REVISED DECEMBER 1996

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PM (S-PQFP-G64) PLASTIC QUAD FLATPACK

4040152/C 11/96

17 0,13 NOM

0,25

0,45

0,75

Seating Plane

0,05 MIN

Gage Plane

0,27

0,17

10,20

11,80

12,20

9,80

7,50 TYP

1,60 MAX

1,45

1,35

0,08

0,50 M

0,08

0°–7°

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.

C. Falls within JEDEC MS-026

D. May also be thermally enhanced plastic with leads connected to the die pads.

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