FSTD32211GX - Fairchild Semiconductor

September 2001

Revised July 2002

FSTD32211 40/48-Bit Bus Switch with Level Shifting

FSTD32211

40/48 - Bit Bus Switch wi th Level Shif ting

General Description

The Fairchild Switch FSTD32211 provides up to 48-bits of

high-sp eed CMOS TTL- compatibl e bus switchin g. The low

on resistance of the switch allows inputs to be connected to

outputs without adding propagation delay or generating

addition al ground boun ce noise. A diode to VCC has been

integrated into the circuit t o a llow for leve l shifting b etween

5V inputs and 3.3V outputs.

The device can be organized as four 12-bit, two 24-b it, or

one 48-b i t bu s swi t ch. When ro uted as a 40 -b it bu s sw itch,

the device can be organized as four 10-bit, two 20-bit or

one 40-bit bus switch. When OE1 is LOW, the switch is ON

and Port 1A is connected to Port 1B. When OE2 is LOW,

the switch is ON and Port 2A is connected to Port 2B.

When OE3 is LOW, the switch is ON and Port 3A is con-

nected to Port 3B. When OE4 is LOW, the switch is ON and

Port 4A is connected to Port 4B. When OE1, OE2, OE3, or

OE4 are HIGH , a hig h i m pe dan ce stat e e x ists be tw ee n t he

A and B Ports.

Features

■4Ω switch connection between two ports

■Voltage level shifting

■Minimal propagation delay through the switch

■Low lCC

■Zero bounce in flow-through mode

■Control inputs compatible with TTL level

■Packaged in plastic Fine-Pitch Ball Grid Array (FBGA)

Ordering Code:

Note 1: Order ing code “G” indicat es T r a ys.

Note 2: Devices also availab le in Tape and Reel. Specif y by append ing the suffix let t er “X” to the or dering c ode.

Logic Diagram

Order Number Package Number Package Description

FSTD32211G

(Note 1)(Note 2) BGA114A 114-Ball Fine- Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide

www.fairchildsemi.com 2

FSTD32211

Connection Diagram

(Top Thru View)

Pin Descriptions

FBGA Pin Assignments

(40-Bit Routing)

Truth Tables

Pin Name Description

OE1, OE2, OE3, OE4Bus Switch Enables

1A, 2A, 3A, 4A Bus A

1B, 2B, 3B, 4B Bus B

123 4 56

A1A21A1NC OE21B11B2

B1A41A3GND OE11B31B4

C1A61A5GND GND 1B51B6

D1A81A7GND GND 1B71B8

E1A10 1A9VCC VCC 1B91B10

F2A22A1VCC VCC 2B12B2

G2A42A3VCC GND 2B32B4

H2A62A5GND GND 2B52B6

J2A82A72A92B92B72B8

K2A10 3A10 GND GND 3B10 2B10

L3A93A8GND GND 3B83B9

M3A73A6GND VCC 3B63B7

N3A53A4VCC VCC 3B43B5

P3A33A2VCC VCC 3B23B3

R3A14A10 GND GND 4B10 3B1

T4A94A8GND GND 4B84B9

U4A74A6GND 4B14B64B7

V4A54A44A1OE44B44B5

W4A34A2OE3NC 4B24B3

Inputs Inputs/Outputs

OE1OE21A, 1B 2A, 2B

LL1A = 1B 2A = 2B

LH1A = 1B Z

HLZ2A

= 2B

HHZZ

Inputs Inputs/Outputs

OE3OE43A, 3B 4A, 4B

LL3A

= 3B 4A = 4B

LH3A

= 3B Z

HLZ4A

= 4B

HHZZ

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FSTD32211

Connection Diagram

(To p Thru View)

Pin Descriptions

FBGA Pin Assignments

(48-Bit Routing)

Truth Tables

Pin Name Description

OE1, OE2, OE3, OE4Bus Switch Enables

1A, 2A, 3A, 4A Bus A

1B, 2B, 3B, 4B Bus B

123 4 56

A1A21A1NC OE21B11B2

B1A41A31A7OE11B31B4

C1A61A5GND 1B71B51B6

D1A10 1A91A81B81B91B10

E1A12 1A11 2A12B11B11 1B12

F2A42A32A22B22B32B4

G2A62A5VCC GND 2B52B6

H2A82A7GND GND 2B72B8

J2A10 2A92A11 2B11 2B92B10

K2A12 3A12 GND GND 3B12 2B12

L3A11 3A10 GND GND 3B10 3B11

M3A93A8GND VCC 3B83B9

N3A73A63A23B23B63B7

P3A53A43A13B13B43B5

R3A34A12 4A84B84B12 3B3

T4A11 4A10 4A74B74B10 4B11

U4A94A6GND 4B14B64B9

V4A54A44A1OE44B44B5

W4A34A2OE3NC 4B24B3

Inputs Inputs/Outputs

OE1OE21A, 1B 2A, 2B

LL1A

= 1B 2A = 2B

LH1A = 1B Z

HLZ2A

= 2B

HHZZ

Inputs Inputs/Outputs

OE3OE43A, 3B 4A, 4B

LL3A

= 3B 4A = 4B

LH3A

= 3B Z

HLZ4A

= 4B

HHZZ

www.fairchildsemi.com 4

FSTD32211

Absolute Maximum Ratings(Note 3) Recommended Operating

Conditions (Note 6)

Note 3: The “Absolute Maximum Ratings” are thos e values bey ond which

the saf ety of the device cannot be gu aranteed. Th e device shoul d not be

operated at these limits. The parametric values defined in the Electrical

Characteristics tables are not guaranteed at the absolute maximum rating.

The “R ecomm ended Oper ating Co ndition s” table will def ine the condit ions

for actu al device operation.

Note 4: VS is the vol t age o bs erved/a pplie d at eith er A or B Ports across t he

switch.

Note 5: The inpu t and outpu t negati ve voltag e ratings m ay be ex ceede d if

the input and output diode current ratings are observed.

Note 6: Unused control inputs must be held HIGH or LOW. They may not

float.

DC Electrical Characteristi cs

Note 7: Typical values are at VCC = 5.0V and TA= +25°C

Note 8: Measured by the v olt age drop between A and B pins at th e indica te d c urrent thro ugh the swit c h. On Res is t ance is de te rm ined by the lower of the

voltages on the two (A or B) pi ns .

Supply Voltage (VCC) 0.5V to +7.0V

DC Switch Voltage (VS) (Note 4) −0.5V to +7.0V

DC Input Control Pin Voltage (VIN)(Note 5) −0.5V to +7.0V

DC Input Diode Current (lIK) VIN < 0V −50 mA

DC Output (IOUT) 128 mA

DC VCC/GND Current (ICC/IGND)+/− 100 mA

Storage Temperature Range (TSTG)−65°C to +150 °C

Power Supply Operating (VCC) 4.5V to 5.5V

Input Voltage (VIN)0V to 5.5V

Output Voltage (VOUT)0V to 5.5V

Input Rise and Fall Time (tr, tf)

Switch Control Input 0 ns/V to 5 ns/V

Switch I/O 0 ns/V to DC

Free Air Operating Temperature (TA)-40 °C to +85 °C

Symbol Parameter VCC

(V)

TA = −40 °C to +85 °CUnits Conditions

Min Typ

(Note 7) Max

VIK Clamp Diode Voltage 4.5 −1.2 V IIN = −18 mA

VIH HIGH Level Input Voltage 4.5 - 5.5 2.0 V

VIL LOW Level Input Voltage 4.5 - 5.5 0.8 V

VOH HIGH Level 4.5 - 5.5 See Figure 3 V

IIInput Leakage Current 5.5 ±1.0 µA0 ≤ VIN ≤ 5.5V

010µAV

IN = 5.5 V

IOZ OFF-STATE Leakage Current 5.5 ±1.0 µA0 ≤ A, B ≤ VCC

RON Switch On Resistance 4.5 4 7 ΩVIN = 0V, IIN = 64 mA

(Note 8) 4.5 4 7 ΩVIN = 0V, IIN = 30 mA

4.5 35 50 ΩVIN = 2.4V, IIN = 15 mA

ICC Quiescent Supply Current

5.5 1.5 mA OE1 = OE2 = GND

VIN = VCC or GND, IOUT = 0

10 µAOE1 = OE2 = VCC

VIN = VCC or GND, IOUT = 0

∆ ICC Increase in ICC per Input 5.5 2.5 mA One Input at 3.4V

Other Inputs at VCC or GND

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FSTD32211

AC Electrical Characteristics

Note 9: T his par ameter is guara nt eed by design but is not te s t ed. The bus s wi tch contribut es no propag at ion delay other tha n t h e R C delay of the typical On

Resistance of th e s w it c h and the 50pF load capacit ance, when driven by an ideal v oltage so urc e (zero out put impedance).

Capacitance (Note 10)

Note 10: TA = +25°C, f = 1 MHz, Capacitance is characterized but not tested.

AC Loading and Waveforms

Note: Input driven by 50Ω source terminated in 50Ω

Note: CL includes load and stray capacitance

Note: Input PRR = 1.0 M H z, t W = 500 ns

FIGURE 1. AC Test Circuit

FIGURE 2. AC Waveforms

Symbol Parameter

TA = −40 °C to +85 °C,

Units Conditions Figure

Number

CL = 50pF, RU = RD = 500Ω

VCC = 4.5 – 5.5V

Min Max

tPHL, tPLH Propagation Delay Bus to Bus (Note 9) 0.25 ns VI = OPEN Figures

1, 2

tPZH, tPZL Output Enable Time 1.5 10.0 ns VI = 7V for tPZL Figures

1, 2

VI = OPEN for tPZH

tPHZ, tPLZ Output Disable Time 1.5 9.0 ns VI = 7V for tPLZ Figures

1, 2

VI = OPEN for tPHZ

Symbol Parameter Typ Max Units Conditions

CIN Control Pin Input Capacitance 3 pF VCC = 5.0V

CI/O Input/Output Capacitance 6 pF VCC, OE = 5.0V

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FSTD32211

Output Voltage HIGH vs. Supply Voltage

FIGURE 3.

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FSTD32211 40/48-Bit Bus Switch with Level Shifting

Physical Dimensions inches (millimeters) unless otherwise noted

114-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide

Package Number BGA114A

Technology Description

The Fairchild Switch family derives fro m and embodies Fairchild’s proven switch t echnology used for several years in its

74LVX3L384 (FST3384) bus switch product.

Fairchild does not assume an y responsibility for u se of any circuitry descr ibed, no circuit pat ent licenses are implied and

Fairchild reserves the right at any time without notice to change said circuitry and specifications.

LIFE SUPPORT POLICY

FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT

DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD

SEMICONDUCTOR CORPORATION. As used herein:

1. Life suppor t de vices o r syst ems are dev ic es or syste ms

which, (a) are intended for surgical implant into the

body, or (b) support or sustain life, and (c) whose failure

to perform when properly used in accordance with

instruct ions fo r use pr ovi de d in the l abe ling, can be rea-

sonably expected to result in a significant injury to the

user.

2. A crit ical componen t in any com ponen t of a life s uppor t

device or system whose failure to perform can be rea-

sonabl y e xpec ted to cause th e fa i lure of the l ife s upport

device or system, or to affect its safety or effectiveness.