The Allegro ACS71020 power monitoring IC greatly simplifies
the addition of power monitoring to many AC powered systems.
The sensor may be powered from the same supply as the
system’s MCU, eliminating the need for multiple power supplies
and expensive digital isolation ICs. The device’s construction
includes a copper conduction path that generates a magnetic field
proportional to applied current. The magnetic field is sensed
differentially to reject errors introduced by common mode fields.
Allegro’s Hall-effect-based galvanically isolated current
sensing technology achieves reinforced isolation ratings in a
small PCB footprint. These features enable isolated current
sensing without expensive Rogowski coils, oversized current
transformers, isolated operational amplifiers, or the power loss
of shunt resistors.
The ACS71020 power monitoring IC offers key power
measurement parameters that can easily be accessed through its
SPI or I2C digital protocol interfaces. Dedicated and configurable
I/O pins for voltage zero crossing, undervoltage and overvoltage
reporting, and overcurrent fault detection are also available (in
I2C mode). The thresholds for overvoltage, undervoltage, and
overcurrent are all user-programmable via EEPROM.
The ACS71020 is provided in a small low-profile surface mount
SOIC16 wide-body package, is lead (Pb) free, and is fully
calibrated prior to shipment from the Allegro factory. Customer
calibration can further increase accuracy in application.
ACS71020-DS, Rev. 9
MCO-0000459
• Accurate power monitoring for AC applications
• UL certification for reinforced isolation up to 517 VRMS in
a single package
• Accurate measurements of active, reactive, and apparent
power, as well as power factor
• Separate RMS and instantaneous measurements for both
voltage and current channels
• 0.85 mΩ primary conductor resistance for low power loss
and high inrush current withstand capability
• Dedicated voltage zero crossing pin
• Overcurrent fault output pin
• Hall-effect-based current measurement with common-
mode stray field rejection
• User-programmable undervoltage and overvoltage thresholds
for input voltage as well as overcurrent fault thresholds
• 1 kHz bandwidth
• Current-sensing range from 0 to 90 A
• Options for I2C or SPI digital interface protocols
• User-programmable EEPROM and integrated charge pump
• 16-bit voltage and current ADCs
Single Phase, Isolated, AC Power Monitoring IC
with Voltage Zero Crossing and Overcurrent Detection
PACKAGE
Figure 1: Typical Application
FEATURES AND BENEFITS DESCRIPTION
Not to scale
ACS71020
IP
IP+
IP+
IP+
IP+
VINP
VINN
IP-
IP-
IP-
IP-
VCC
GND
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
L (N) N (L)
1 MΩ1 MΩ
1 MΩ1 MΩ
RSENSE MCU
VCC
GND
To User
(
REINFORCED
ISOLATION
Linear
Regulator
ACS71020
SDA / MISO
SCL / SCLK
DIO_0 / MOSI
DIO_1 / CS
Isolated Power
Single Output
Supply
, etc.)Flyback
RPULLUP
RPULLUP
I2C
Only
16-pin SOICW (suffix MA)
November 21, 2019
CB Certicate Number:
US-32210-M1-UL
Single Phase, Isolated, AC Power Monitoring IC
with Voltage Zero Crossing and Overcurrent Detection
ACS71020
2
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
SELECTION GUIDE
Part Number VCC(NOM) (V) IPR (A) Communication
Protocol TA (°C) Packing [1]
ACS71020KMABTR-015B5-SPI 5 ±15 SPI
–40 to 125
Tape and reel,
1000 pieces per reel,
3000 pieces per box
ACS71020KMABTR-030B3-SPI 3.3 ±30
ACS71020KMABTR-030B3-I2C 3.3 ±30 I2C
ACS71020KMABTR-090B3-I2C 3.3 ±90
[1] Contact Allegro for additional packing options.
ACS 71020 K MAB - 015 B 5
Supply Voltage:
5 – VCC = 5 V
3 – VCC = 3.3 V
Output Directionality:
B – Bidirectional (positive and negative current)
Current Sensing Range (A)
Package Designator
Operating Temperature Range
5 Digit Part Number
Allegro Current Sensor
TR
Packing Designator
Communication Protocol
- SPI
Single Phase, Isolated, AC Power Monitoring IC
with Voltage Zero Crossing and Overcurrent Detection
ACS71020
3
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
ISOLATION CHARACTERISTICS
Characteristic Symbol Notes Rating Unit
Dielectric Strength Test Voltage VISO
Agency type-tested for 60 seconds per UL 60950-1
(edition 2). Production tested at 3000 VRMS for 1 second, in
accordance with UL 60950-1 (edition 2).
4800 VRMS
Working Voltage for Basic Isolation VWVBI
Maximum approved working voltage for basic (single) isolation
according to UL 60950-1 (edition 2).
1480 VPK or VDC
1047 VRMS
Working Voltage for Reinforced Isolation VWVRI
Maximum approved working voltage for reinforced isolation
according to UL 60950-1 (edition 2).
730 VPK or VDC
517 VRMS
Clearance Dcl Minimum distance through air from IP leads to signal leads. 7.5 mm
Creepage Dcr
Minimum distance along package body from IP leads to signal
leads 7.9 mm
Distance Through Insulation DTI Minimum internal distance through insulation 90 μm
Comparative Tracking Index CTI Material Group II 400 to 599 V
ABSOLUTE MAXIMUM RATINGS
Characteristic Symbol Notes Rating Units
Supply Voltage VCC 6.5 V
Reverse Supply Voltage VRCC –0.5 V
Input Voltage VINP
, VINN VCC + 0.5 V
Reverse Input Voltage VRNP
, VRNN –0.5 V
Digital I/O Voltage VDIO SPI, I2C, and general purpose I/O 6 V
Reverse Digital I/O Voltage VRDIO –0.5 V
Maximum Continuous Current ICMAX TA = 25°C 60 A
Operating Ambient Temperature TARange K –40 to 125 °C
Junction Temperature TJ(max) 165 °C
Storage Temperature Tstg –65 to 170 °C
THERMAL CHARACTERISTICS
Characteristic Symbol Test Conditions* Value Units
Package Thermal Resistance
(Junction to Ambient) RθJA
Mounted on the Allegro 85-0738 evaluation board with 700 mm2 of 4 oz.
copper on each side, connected to pins 1 and 2, and to pins 3 and 4, with
thermal vias connecting the layers. Performance values include the power
consumed by the PCB.
23 °C/W
Package Thermal Resistance
(Junction to Lead) RθJL Mounted on the Allegro ACS71020 evaluation board. 5 °C/W
*Additional thermal information available on the Allegro website. See https://www.allegromicro.com/en/Design-Center/Technical-Documents/Hall-E󰀨ect-Sensor-IC-Publica-
tions/DC-and-Transient-Current-Capability-Fuse-Characteristics.aspx.
ESD RATINGS
Characteristic Symbol Test Conditions Value Unit
Human Body Model VHBM Per AEC-Q100 ±4.5 kV
Charged Device Model VCDM Per AEC-Q100 ±1 kV
Single Phase, Isolated, AC Power Monitoring IC
with Voltage Zero Crossing and Overcurrent Detection
ACS71020
4
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
FUNCTIONAL BLOCK DIAGRAM
Bandgap
Reference
Fault Logic
Temperature
Sensor
IP+
IP–
VCC
GND
To All
Subcircuits
Hall Sensor Array
Metrology
Engine
I2C/SPI
Communication
EEPROM +
Charge Pump
Temperature
Compensation
Logic
DIGITAL SYSTEM
VINN
VINP
ADC
ADC
SDA / MISO
SCL / SCLK
DIO_0 / MOSI
DIO_1 / CS
V
I
R
2R
Table of Contents
Features and Benefits ........................................................... 1
Description .......................................................................... 1
Package ............................................................................. 1
Typical Application ................................................................ 1
Selection Guide ................................................................... 2
Absolute Maximum Ratings ................................................... 3
Isolation Characteristics ........................................................ 3
Thermal Characteristics ........................................................ 3
Functional Block Diagram ..................................................... 4
Pinout Diagram and Terminal List ........................................... 5
Digital I/O ............................................................................ 5
Electrical Characteristics ....................................................... 6
Data Acquisition ................................................................. 13
ADCs ............................................................................ 13
Raw Signal Sensitivity and Offset Trim ............................... 13
Phase Compensation ...................................................... 13
Zero Crossing ................................................................. 13
Power Calculations ............................................................. 14
Digital Communication ........................................................ 17
Registers and EEPROM .................................................. 17
EEPROM Error Checking and Correction (ECC) ................. 19
Memory Map .................................................................. 20
Volatile Memory Map ....................................................... 28
Voltage Input Application Connections .................................. 36
Recommended PCB Layout ................................................ 37
Package Outline Drawing .................................................... 38
Single Phase, Isolated, AC Power Monitoring IC
with Voltage Zero Crossing and Overcurrent Detection
ACS71020
5
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
Terminal List Table
Number Name Description
I2C SPI
1, 2, 3, 4 IP+ Terminals for current being sensed; fused internally
5, 6, 7, 8 IP- Terminals for current being sensed; fused internally
9DIO_1 / CS Digital I/O 1 Chip Select (CS)
10 DIO_0 / MOSI Digital I/O 0 MOSI
11 SCL / SCLK SCL SCLK
12 SDA / MISO SDA MISO
13 VCC Device power supply terminal
14 GND Device Power and Signal ground terminal
15 VINN Negative Input Voltage
16 VINP Positive Input Voltage
Pinout Diagram
1
IP+
2
IP+
3
IP+
4
IP+
5
IP-
6
IP-
7
IP-
8
IP-
9
10
DIO_0 / MOSI
11 SCL / SCLK
12 SDA / MISO
13 VCC
14 GND
15 VINN
16 VINP
DIO_1 / CS
PINOUT DIAGRAM AND TERMINAL LIST
OVRMS
UVRMS
OVRMS
UVRMS
OCF_LAT
OCF
VZC DIO_0
DIO_1
CS
MOSI
DIO_1 / CS
DIO_0 / MOSI
DIO_0_Sel[0..1] Comm_Sel
DIO_1_Sel[0..1] Comm_Sel
DIGITAL I/O
The Digital I/O can be programmed to represent the following
functions (Digital Output pins are low true):
DIO_0:
0. VZC: Voltage zero crossing
1. OVRMS: The VRMS overvoltage ag
2. UVRMS: The VRMS undervoltage ag
3. The OR of OVRMS and UVRMS (if either ag is triggered,
the DIO_0 pin will be asserted)
DIO_1:
0. OCF: Overcurrent fault
1. UVRMS: The VRMS undervoltage ag
2. OVRMS: The VRMS overvoltage ag
3. The OR of OVRMS, UVRMS, and OCF_LAT [Latched
Overcurrent fault] (if any of the three ags are triggered, the
DIO_1 pin will be asserted)
Single Phase, Isolated, AC Power Monitoring IC
with Voltage Zero Crossing and Overcurrent Detection
ACS71020
6
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
Characteristic Symbol Test Conditions Min. Typ. Max. Unit
ELECTRICAL CHARACTERISTICS
Supply Voltage VCC VCC(nom) × 0.9 VCC(nom) VCC(nom) × 1.1 V
Supply Current ICC
VCC(min) ≤ VCC ≤ VCC(max), no load
on output pins – 12 14 mA
Power-On Time tPO – 90 – µs
VOLTAGE INPUT BUFFER
Differential Input Range ΔVIN VINP – VINN –275 – 275 mV
Common Mode Input Voltage VIN(CM)
2/3 × VCC
– 0.275 –2/3 × VCC
+ 0.275 V
VOLTAGE CHANNEL ADC
Sample Frequency fS – 32 – kHz
Number of Bits NADC(V) – 16 – bits
Voltage ADC Power Supply Rejection V_PSRR Ratio of change on VCC to change in
ADC internal reference at DC 60 70 – dB
VOLTAGE CHANNEL
Noise VN– 10 – LSB
Internal Bandwidth BW – 1 – kHz
Linearity Error ELIN – ±0.2 – %
CURRENT CHANNEL ADC
Sample Frequency fS – 32 – kHz
Number of Bits NADC(I) – 16 – bits
Current Channel ADC Power Supply Rejection I_PSRR Ratio of change on VCC to change in
ADC internal reference at DC 60 70 – dB
CURRENT CHANNEL
Internal Bandwidth BW – 1 – kHz
Primary Conductor Resistance RIP TA = 25°C – 0.85 – mΩ
Noise VN – 100 – LSB
Linearity Error ELIN – ±1.5 – %
OVERCURRENT FAULT CHARACTERISTICS
Fault Response Time tRF
Time from IP rising above IFAULT until
VFAULT < VFAULT(max) for a current
step from 0 to 1.2 × IFAULT; 10 kΩ and
100 pF from DIO_1 to ground;
fltdly = 0
–5–μs
Internal Bandwidth BW – 200 – kHz
Fault Hysteresis [2] IHYST – 0.05 × IPR – A
Fault Range IFAULT Set using FAULT field in EEPROM 0.5 × IPR – 1.75 × IPR A
VOLTAGE ZERO CROSSING
Voltage Zero Crossing Delay td– 350 – µs
COMMON ELECTRICAL CHARACTERISTICS [1]: Valid through the full range of TA and VCC
= VCC(nom), unless otherwise specied
Continued on next page...
Single Phase, Isolated, AC Power Monitoring IC
with Voltage Zero Crossing and Overcurrent Detection
ACS71020
7
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
Characteristic Symbol Test Conditions Min. Typ. Max. Unit
DIO PINS
DIO Output High Level VCC = 3.3 V 3 – – V
DIO Output Low Level VCC = 3.3 V – – 0.3 V
DIO Input Voltage for Address Selection 0 VCC = 3.3 V – 0 – V
DIO Input Voltage for Address Selection 1 VCC = 3.3 V – 1.1 – V
DIO Input Voltage for Address Selection 2 VCC = 3.3 V – 2.2 – V
DIO Input Voltage for Address Selection 3 VCC = 3.3 V – 3.3 – V
[1] Device may be operated at higher primary current levels, IP
, ambient, TA, and internal leadframe temperatures, TA, provided that the Maximum Junction Temperature,
TJ(max), is not exceeded.
[2] After IP goes above IFAULT, tripping the internal fault comparator, IP must go below IFAULT – IHYST, before the internal fault comparator will reset.
COMMON ELECTRICAL CHARACTERISTICS [1] (continued): Valid through the full range of TA and VCC
= VCC(nom),
unless otherwise specied
Single Phase, Isolated, AC Power Monitoring IC
with Voltage Zero Crossing and Overcurrent Detection
ACS71020
8
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
Characteristic Symbol Test Conditions Min. Typ. Max. Unit
I2C INTERFACE CHARACTERISTICS [1]
Bus Free Time Between Stop and Start tBUF 1.3 – – µs
Hold Time Start Condition thdSTA 0.6 – – µs
Setup Time for Repeated Start Condition tsuSTA 0.6 – – µs
SCL Low Time tLOW 1.3 – – µs
SCL High Time tHIGH 0.6 – – µs
Data Setup Time tsuDAT 100 – – µs
Data Hold Time thdDAT 0 – 900 µs
Setup Time for Stop Condition tsuSTO 0.6 – – µs
Logic Input Low Level (SDA, SCL pins) VIL – – 30 %VCC
Logic Input High Level (SDA, SCL pins) VIH 70 –– %VCC
Logic Input Current IIN Input voltage on SDA or SCL = 0 V to VCC –1 –1 µA
Output Low Voltage (SDA) VOL SDA sinking = 1.5 mA – –0.36 V
Clock Frequency (SCL pin) fCLK ––400 kHz
Output Fall Time (SDA pin) tfREXT = 2.4 kΩ, CB = 100 pF – –250 ns
I2C Pull-Up Resistance REXT 2.4 10 – kΩ
Total Capacitive Load for Each of SDA and
SCL Buses CB– – 20 pF
[1] These values are ratiometric to the supply voltage, I2C Interface Characteristics are ensured by design and not factory tested.
xKMATR-I2C OPERATING CHARACTERISTICS: Valid through the full range of TA, VCC
= VCC(nom), REXT = 10 kΩ,
unless otherwise specied
tsuSTA tsuDAT
tLOW
tsuSTO
thdSTA thdDAT
tHIGH
tBUF
SDA
SCL
Figure 2: I2C Interface Timing
Single Phase, Isolated, AC Power Monitoring IC
with Voltage Zero Crossing and Overcurrent Detection
ACS71020
9
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
Characteristic Symbol Test Conditions Min. Typ. Max. Unit
SPI INTERFACE CHARACTERISTICS
Digital Input High Voltage VIH
MOSI, SCLK, CS pins, VCC (nom) = 3.3 V 2.8 – 3.63 V
MOSI, SCLK, CS pins, VCC (nom) = 5 V 4 – 5.5 V
Digital Input Low Voltage VIL MOSI, SCLK, CS pins – – 0.5 V
SPI Output High Voltage VOH
MISO pin, CL = 20 pF, TA = 25°C,
VCC (nom) = 3.3 V 2.8 3.3 3.8 V
MISO pin, CL = 20 pF, TA = 25°C,
VCC (nom) = 5 V 4 5 5.5 V
SPI Output Low Voltage VOL MISO pin, CL = 20 pF, TA = 25°C – 0.3 0.5 V
SPI Clock Frequency fSCLK MISO pin, CL = 20 pF 0.1 – 10 MHz
SPI Frame Rate tSPI 5.8 – 588 kHz
Chip Select to First SCLK Edge tCS
Time from CS going low to SCLK falling
edge 50 – – ns
Data Output Valid Time tDAV Data output valid after SCLK falling edge – 40 – ns
MOSI Setup Time tSU Input setup time before SCLK rising edge 25 – – ns
MOSI Hold Time tHD Input hold time after SCLK rising edge 50 – – ns
SCLK to CS Hold Time tCHD
Hold SCLK high time before CS rising
edge 5 – – ns
Load Capacitance CLLoading on digital output (MISO) pin – – 20 pF
[1] The ACS71020 MISO pin continues to drive the MISO line when CS goes high. This may prevent other devices from communicating properly.
It is recommended that the ACS71020 be the only device on the SPI bus if using SPI communication.
xKMATR-SPI OPERATING CHARACTERISTICS [1]: Valid through the full range of TA, VCC
= VCC(nom), unless otherwise specied
Figure 3: SPI Timing
Single Phase, Isolated, AC Power Monitoring IC
with Voltage Zero Crossing and Overcurrent Detection
ACS71020
10
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
Characteristic Symbol Test Conditions Min. Typ. [1] Max. Unit
GENERAL CHARACTERISTICS
Nominal Supply Voltage VCC (nom) – 5 – V
NOMINAL PERFORMANCE – CURRENT CHANNEL
Current Sensing Range IPR –15 – 15 A
Sensitivity Sens(I) IPR (min) < IP < IPR (max) – 2184 – LSB/A
ACCURACY PERFORMANCE – CURRENT CHANNEL
Total Output Error ETOT(I)
Measured at IP = IPR (max), TA = 25°C to 125°C – ±2 – %
Measured at IP = IPR (max), TA = –40°C to 25°C – ±3 – %
TOTAL OUTPUT ERROR COMPONENTS – CURRENT CHANNEL
Sensitivity Error ESENS(I)
Measured at IP = IPR (max), TA = 25°C to 125°C – ±1 – %
Measured at IP = IPR (max), TA = –40°C to 25°C – ±1.5 – %
Offset Error EO(I)
IP = 0 A, TA = 25°C to 125°C – ±300 – LSB
IP = 0 A, TA = –40°C to 25°C – ±500 – LSB
NOMINAL PERFORMANCE – VOLTAGE CHANNEL
Sensitivity Sens(V) VPR (min) < VP < VPR (max) – 238 – LSB/mV
ACCURACY PERFORMANCE – VOLTAGE CHANNEL
Total Output Error ETOT(V)
Measured at VP = VPR (max), TA = 25°C to 125°C – ±1.2 – %
Measured at VP = VPR (max), TA = –40°C to 25°C – ±1.3 – %
TOTAL OUTPUT ERROR COMPONENTS – VOLTAGE CHANNEL
Sensitivity Error ESENS(V)
Measured at VP = VPR (max), TA = 25°C to 125°C – ±1 – %
Measured at VP = VPR (max), TA = –40°C to 25°C – ±1 – %
Offset Error EO(V)
VP = 0 mV, TA = 25°C to 125°C – ±100 – LSB
VP = 0 mV, TA = –40°C to 25°C – ±150 – LSB
ACCURACY PERFORMANCE – ACTIVE POWER
Total Output Error ETOT(P)
Measured at VP = VPR (max), TA = 25°C to 125°C – ±2.3 – %
Measured at VP = VPR (max), TA = –40°C to 25°C – ±3.3 – %
[1] Typical values are based on mean ±3 sigma.
ACS71020KMA-015B5 PERFORMANCE CHARACTERISTICS: Valid through the full operating temperature range, TA = –40°C to 125°C,
CBYPASS = 0.1 µF, and VCC = 5 V, unless otherwise specied
Single Phase, Isolated, AC Power Monitoring IC
with Voltage Zero Crossing and Overcurrent Detection
ACS71020
11
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
Characteristic Symbol Test Conditions Min. Typ. [1] Max. Unit
GENERAL CHARACTERISTICS
Nominal Supply Voltage VCC (nom) – 3.3 – V
NOMINAL PERFORMANCE – CURRENT CHANNEL
Current Sensing Range IPR –30 – 30 A
Sensitivity Sens(I) IPR (min) < IP < IPR (max) – 1092 – LSB/A
ACCURACY PERFORMANCE – CURRENT CHANNEL
Total Output Error ETOT(I)
Measured at IP = IPR (max), TA = 25°C to 125°C – ±2 – %
Measured at IP = IPR (max), TA = –40°C to 25°C – ±3 – %
TOTAL OUTPUT ERROR COMPONENTS – CURRENT CHANNEL
Sensitivity Error ESENS(I)
Measured at IP = IPR (max), TA = 25°C to 125°C – ±1 – %
Measured at IP = IPR (max), TA = –40°C to 25°C – ±1.5 – %
Offset Error EO(I)
IP = 0 A, TA = 25°C to 125°C – ±500 – LSB
IP = 0 A, TA = –40°C to 25°C – ±700 – LSB
NOMINAL PERFORMANCE – VOLTAGE CHANNEL
Sensitivity Sens(V) VPR (min) < VP < VPR (max) – 238 – LSB/mV
ACCURACY PERFORMANCE – VOLTAGE CHANNEL
Total Output Error ETOT(V)
Measured at VP = VPR (max), TA = 25°C to 125°C – ±1.2 – %
Measured at VP = VPR (max), TA = –40°C to 25°C – ±1.3 – %
TOTAL OUTPUT ERROR COMPONENTS – VOLTAGE CHANNEL
Sensitivity Error ESENS(V)
Measured at VP = VPR (max), TA = 25°C to 125°C – ±1 – %
Measured at VP = VPR (max), TA = –40°C to 25°C – ±1 – %
Offset Error EO(V)
VP = 0 mV, TA = 25°C to 125°C – ±60 – LSB
VP = 0 mV, TA = –40°C to 25°C – ±80 – LSB
ACCURACY PERFORMANCE – ACTIVE POWER
Total Output Error ETOT(P)
Measured at VP = VPR (max), TA = 25°C to 125°C – ±2.3 – %
Measured at VP = VPR (max), TA = –40°C to 25°C – ±3.3 – %
[1] Typical values are based on mean ±3 sigma.
ACS71020KMA-030B3 PERFORMANCE CHARACTERISTICS: Valid through the full operating temperature range, TA = –40°C to 125°C,
CBYPASS = 0.1 µF, and VCC = 3.3 V, unless otherwise specied
Single Phase, Isolated, AC Power Monitoring IC
with Voltage Zero Crossing and Overcurrent Detection
ACS71020
12
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
Characteristic Symbol Test Conditions Min. Typ. [1] Max. Unit
GENERAL CHARACTERISTICS
Nominal Supply Voltage VCC (nom) – 3.3 – V
NOMINAL PERFORMANCE – CURRENT CHANNEL
Current Sensing Range IPR –90 – 90 A
Sensitivity Sens(I) IPR (min) < IP < IPR (max) – 364 – LSB/A
ACCURACY PERFORMANCE – CURRENT CHANNEL
Total Output Error ETOT(I)
Measured at IP = IPR (max), TA = 25°C to 125°C – ±2 – %
Measured at IP = IPR (max), TA = –40°C to 25°C – ±3 – %
TOTAL OUTPUT ERROR COMPONENTS – CURRENT CHANNEL
Sensitivity Error ESENS(I)
Measured at IP = IPR (max), TA = 25°C to 125°C – ±1 – %
Measured at IP = IPR (max), TA = –40°C to 25°C – ±1.5 – %
Offset Error EO(I)
IP = 0 A, TA = 25°C to 125°C – ±300 – LSB
IP = 0 A, TA = –40°C to 25°C – ±500 – LSB
NOMINAL PERFORMANCE – VOLTAGE CHANNEL
Sensitivity Sens(V) VPR (min) < VP < VPR (max) – 238 – LSB/mV
ACCURACY PERFORMANCE – VOLTAGE CHANNEL
Total Output Error ETOT(V)
Measured at VP = VPR (max), TA = 25°C to 125°C – ±1.2 – %
Measured at VP = VPR (max), TA = –40°C to 25°C – ±1.3 – %
TOTAL OUTPUT ERROR COMPONENTS – VOLTAGE CHANNEL
Sensitivity Error ESENS(V)
Measured at VP = VPR (max), TA = 25°C to 125°C – ±1 – %
Measured at VP = VPR (max), TA = –40°C to 25°C – ±1 – %
Offset Error EO(V)
VP = 0 mV, TA = 25°C to 125°C – ±100 – LSB
VP = 0 mV, TA = –40°C to 25°C – ±150 – LSB
ACCURACY PERFORMANCE – ACTIVE POWER
Total Output Error ETOT(P)
Measured at VP = VPR (max), TA = 25°C to 125°C – ±2.3 – %
Measured at VP = VPR (max), TA = –40°C to 25°C – ±3.3 – %
[1] Typical values are based on mean ±3 sigma.
ACS71020KMA-090B3 PERFORMANCE CHARACTERISTICS: Valid through the full operating temperature range, TA = –40°C to 125°C,
CBYPASS = 0.1 µF, and VCC = 3.3 V, unless otherwise specied
Single Phase, Isolated, AC Power Monitoring IC
with Voltage Zero Crossing and Overcurrent Detection
ACS71020
13
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
ADCs
Both the Current and Voltage channels are sampled at a high
frequency and then digitally filtered and decimated to avoid large
anti-aliasing filters. The final sample rate will be near 32 kHz
for an 8 MHz clock. The digital low-pass filters have a cutoff of
1 kHz. The digital word from the ADC is 16 bits for both the cur-
rent and the voltage.
Raw Signal Sensitivity and Offset Trim
The gain and offset for both current and voltage channels use a
shared temperature compensation engine which is trimmed in
production. The fine sensitivity and offset are also trimmed in
production at the factory; however, the user has access to the fine
sensitivity field for the current channel should they want to trim
the gain in application.
Phase Compensation
Phase delay may be introduced on either the voltage or current
channels. The range is EEPROM selectable, either 5° of delay
(step size of 0.67°) or 40° of delay (step size of 5.36°).
Zero Crossing
The zero crossings are only detected on the voltage signal. Both
the high-to-low and low-to-high transitions will be detected
with time-based hysteresis that removes the possibility of noise
causing multiple zero crossings to be reported at each true zero
crossing.
The zero crossing output can be a square wave that transitions
at each zero crossing or a pulse with a fixed width at each zero
crossing. When in pulse mode, the width of the pulse is tP
(see
delaycnt_sel; nominal setting is 32 µs). There will be a fixed
delay, tD, from the time that a true zero crossing has occurred
to the time that it is reported. This delay helps to keep the zero
crossing detection more precise.
DATA ACQUISITION
Figure 4: Zero Crossing
Voltage
Input
Pulse
Mode
Square
Wave
Mode
VZC
tP
tD
Single Phase, Isolated, AC Power Monitoring IC
with Voltage Zero Crossing and Overcurrent Detection
ACS71020
14
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POWER CALCULATIONS
IRMS / VRMS
Half cycle-by-cycle calculation of the root mean square of both
the current and voltage channels:
IRMS = ∑
N
n = N – 1
n = 0In2
VRMS = ∑
N
n = N – 1
n = 0Vn2
where In (Icodes) and Vn (Vcodes) are the instantaneous mea-
surements of current and voltage, respectively. The figure below
represents how the calculation is performed. Each voltage zero
crossing determines end of the rms calculation window and also
starts the next rms calculation window.
Figure 5
Apparent Power
The magnitude of the complex power being measured; calculated
at the end of each cycle:
|S| = IRMS × VRMS
Active Power
The real component of power being measured; calculated cycle
by cycle:
PACTIVE = ∑
N
n = N – 1
n = 0PnPn = In × Vn
Reactive Power
Imaginary component of power being measured; calculated at the
end of each cycle:
Q = S2 – PACTIVE
2
Power Factor
The magnitude of the ratio of real power to apparent power;
calculated at the end of each cycle:
|PF| = |S|
PACTIVE
Lead/Lag
The voltage leading or lagging the current will be communicated
as a single bit. This bit also represents the sign of the Reactive
Power. This is stored in the register field “posangle”.
Leading or lagging is determined by comparing the zero cross-
ings of the voltage and current channels.
Imaginary
Real
POSPF = 1
POSANG = 1
POSPF = 0
POSANG = 0
POSPF = 0
POSANG = 1
POSPF = 1
POSANG = 0
Lagging
Leading
Figure 6
Single Phase, Isolated, AC Power Monitoring IC
with Voltage Zero Crossing and Overcurrent Detection
ACS71020
15
Allegro MicroSystems
955 Perimeter Road
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Apparent Power, S = VI
Active Power, P = VI cosФ
Reactive Power, Q = VI sinФ
Ф
S = P 2 + Q 2
Figure 7: Power Triangle
Single Phase, Isolated, AC Power Monitoring IC
with Voltage Zero Crossing and Overcurrent Detection
ACS71020
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Allegro MicroSystems
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Figure 8: ACS71020 Trim Diagram
RMS Calcula�ons
VRMS/IRMS Averaging
Ac�ve Power Averaging
icodes
RMS Calcula�on
n
Averaging Block 1Averaging Block 2
rms_avg_1 rms_avg_2
Averaging Block 1Averaging Block 2
pinstant
vcodes
RMS Calcula�on
iavgselen
RMS Calcula�on
pac�ve
Overcurrent Fault
The overcurrent fault threshold may be set from 50% to 175% of
IP. The user sets the trip point with an 8-bit word. The user also
has the ability to set the trip level digital delay. This allows for up
to a 32 µs delay on the Fault.
Averaging Over Time
IRMS or VRMS and PACTIVE may be averaged over a program-
mable number of updates. Note that either VMRS and IRMS can
be averaged, not both.
The number of averages is controlled by two different registers.
There is an accumulator that averages the above values. A 7-bit
number, rms_avg_1, is used to determine the number of averages.
There is an additional accumulator that will be used to average
the output of the first accumulator. There is a 10-bit number,
rms_avg_2, that will be used to determine the number of averages
for this accumulator. For optimal performance, setting an even
number of averages for both accumulators is recommended. The
combination of the two accumulator allows the user to select how
long to average for as well as how often the values are updated.
The exact time this averages over depends on n (the number of
samples per cycle). Averages could be read in Reg 0x26 to 0x29.
Over/Undervoltage Detection
There are two flags that can be used to detect undervoltage and
overvoltage. These flags have a programmable voltage trip level.
Refer to the Digital I/O section for all possible configurations.
Single Phase, Isolated, AC Power Monitoring IC
with Voltage Zero Crossing and Overcurrent Detection
ACS71020
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DIGITAL COMMUNICATION
Communication Interfaces
The ACS71020 supports communication over 1 MHz I2C and
10 MHz SPI. However, the communication protocol is fixed during
factory programming. Refer to the Selection Guide for more infor-
mation. The ACS71020 MISO pin continues to drive the MISO
line when CS goes high. This may prevent other devices from com-
municating properly. It is recommended that the ACS71020 be the
only device on the SPI bus if using SPI communication.
SPI
The SPI frame consists of:
• The Master writes on the MOSI line the 7-bit address of the
register to be read from or written to.
• The next bit on the MOSI line is the read/write (RW) indicator.
A high state indicates a Read and a low state indicates a Write.
• The device sends a 32-bit response on the MISO line. The
contents correspond to the previous command.
• On the MOSI line, if the current command is a write, the 32
bits correspond to the Write data, and in the case of a read, the
data is ignored.
Registers and EEPROM
WRITE ACCESS
The ACS71020 supports factory and customer EEPROM space as
well as volatile registers. The customer access code must be sent
prior to writing these customer EEPROM spaces. In addition, the
device includes a set of free space EEPROM registers that are
accessible with or without writing the access code.
READ ACCESS
All EEPROM and volatile registers may be read at any time
regardless of the access code.
EEPROM
At power up all shadow registers are loaded from EEPROM
including all configuration parameters. The shadow registers can
be written to in order to change the device behavior without hav-
ing to perform an EEPROM write. Any changes made it shadow
memory are volatile and do not persist through a reset event.
WRITING
The Timing Diagram for an EEPROM write is shown in Figure 9
and Figure 10.
CSN
SCLK
MOSI
MISO
REGISTER ADDRESS WRITE DATA OR DCRW
PREVIOUS CMD DATA
0 1 5 6 0 1 30 31
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
SPST 0Slave
address
Register
address
Register
Data
[7:0]
Register
Data
[15:8]
Register
Data
[23:16]
Register
Data
[31:24]
W
SA[6:0] A[6:0] D[7:0] D[7:0] D[7:0] D[7:0]
SDA
Figure 9: EEPROM Write – SPI Mode
Figure 10: EEPROM Write – I2C Mode
Blue represents data sent by the master and
orange is the data sent by the slave.
Single Phase, Isolated, AC Power Monitoring IC
with Voltage Zero Crossing and Overcurrent Detection
ACS71020
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READING
The timing diagram for an EEPROM read is shown in Figure 11
and Figure 12.
CSN
SCLK
MOSI
MISO
REGISTER ADDRESS WRITE DATA OR DCRW
PREVIOUS CMD DATA
0 1 5 6 0 1 30 31
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
N
A
C
K
SPST 0Slave
address
Register
address
Register
Data
[7:0]
Register
Data
[15:8]
Register
Data
[23:16]
Register
Data
[31:24]
W
SA[6:0]A[6:0] D[7:0] D[7:0] D[7:0] D[7:0]
SDA SA[6:0]
Slave
address
A
C
K
ST R
Figure 11: EEPROM Read – SPI Mode
For SPI, the read data will be sent out
during the above command.
Figure 12: EEPROM Read – I2C Mode
Blue represents data sent by the master and
orange is the data sent by the slave.
Single Phase, Isolated, AC Power Monitoring IC
with Voltage Zero Crossing and Overcurrent Detection
ACS71020
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EEPROM Error Checking and Correction (ECC)
Hamming code methodology is implemented for EEPROM
checking and correction (ECC). ECC is enabled after power-up.
The ACS71020 analyzes message data sent by the controller and
the ECC bits are added. The first 6 bits sent from the device to
the controller are dedicated to ECC. The device always returns 32
bits.
EEPROM ECC Errors
Bits Name Description
31:28 – No meaning
27:26 ECC
00 = No Error
01 = Error detected and message corrected
10 = Uncorrectable error
11 = No meaning
25:0 D[25:0] EEPROM data
Single Phase, Isolated, AC Power Monitoring IC
with Voltage Zero Crossing and Overcurrent Detection
ACS71020
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EEPROM/Shadow Memory
Address
Bits
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EEPROM
0x0B ECC
iavgselen
crs_sns sns_fine qvo_fine
0x0C ECC rms_avg_2 rms_avg_1
0x0D ECC
squarewave_en
halfcycle_en
fltdly fault
chan_del_sel
ichan_del_en
pacc_trim
0x0E ECC
delaycnt_sel
undervreg overvreg
vadc_rate_set
vevent_cycs
0x0F ECC
dio_1_sel
dio_0_sel
i2c_dis_slv_addr
i2c_slv_addr
Shadow
0x1B
iavgselen
crs_sns sns_fine qvo_fine
0x1C rms_avg_2 rms_avg_1
0x1D
squarewave_en
halfcycle_en
fltdly fault
unused
chan_del_sel
unused
ichan_del_en
pacc_trim
0x1E
delaycnt_sel
undervreg overvreg
vadc_rate_set
vevent_cycs
0x1F
dio_1_sel
dio_0_sel
i2c_dis_slv_addr
i2c_slv_addr
MEMORY MAP
Single Phase, Isolated, AC Power Monitoring IC
with Voltage Zero Crossing and Overcurrent Detection
ACS71020
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Figure 13: Voltage Channel Trim Flow
Device Trim Flow
The trim process for voltage, current, and power channels are
depicted in Figure 13 through Figure 15. Refer to the “Register
Details” Section for more information regarding trim fields.
Figure 14: Current Channel Trim Flow
Figure 15: Power Channel Trim Flow
Delay
Z-x
chan_del_sel
ichan_del_en
Satura�onGain Trim
VchanGainSel
Offset Trim
+
+
+
+
vqvo
vqvo_tc
vcodes
adc_out_v
Factory
Trim
Satura�on
Gain Trim
sns_fine
sns_tc
Offset Trim
+
+
+
+
qvo_fine
qvo_tc
Delay
Z-x
chan_del_sel
ichan_del_en
icod es
adc_out_i
Factory
Trim
Offset Trim
++
pacc_trim
pac�ve_int
pac�ve
Single Phase, Isolated, AC Power Monitoring IC
with Voltage Zero Crossing and Overcurrent Detection
ACS71020
22
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Register Details – EEPROM
Register 0x0B/0x1B
Bits Name Default Value Description
8:0 qvo_fine – Offset fine trimming on current channel
17:9 sns_fine – Fine gain trimming on the current channel
20:18 crs_sns – Coarse gain setting
21 iavgselen – Current Averaging selection
25:22 unused – Unused
31:26 ecc – Error Code Correction
qvo_ne
Offset adjustment for the current channel. This is a signed
9-bit number with an input range of –256 to 255. With a step
size of 64 LSB, this equates to an offset trim range of –16384
to 16320 LSB, which is added to the icodes value. The trim is
implemented as shown in Figure 14. The current channel’s offset
trim should be applied before the gain is trimmed. “qvo_fine” is
further described in Table 1.
Table 1: qvo_fine
Range Value Units
–256 to 255 –16,384 to 16,320 LSB
sns_ne
Gain adjustment for the current channel. This is a signed 9-bit
number with an input range of –256 to 255. This gain adjustment
is implemented as a percentage multiplier centered around 1 (i.e.
writing a 0 to this field multiplies the gain by 1, leaving the gain
unaffected). The fine sensitivity parameter ranges from 50% to
150% of IP. The current channel’s offset trim should be applied
before the gain is trimmed. “sns_fine” is further described in
Table 2.
Table 2: sns_fine
Range Value Units
–256 to 255 50 to 100 %
crs_sns
Coarse gain adjustment for the current channel. This gain is
implemented in the analog domain before the ADC. This is a
3-bit number that allows for 8 gain selections. Adjustments to
“crs_sns” may impact the device’s performance over temperature.
Datasheet limits apply only to the factory settings for “crs_sns”.
The gain settings map to 1×, 2×, 3×, 3.5×, 4×, 4.5×, 5.5×, and 8×.
“crs_sns” is further described in Table 3.
Table 3: crs_sns
Range Value Units
0 1× –
1 2× –
2 3× –
3 3.5× –
4 4× –
5 4.5× –
6 5.5× –
7 8× –
iavgselen
Current Averaging selection enable. 0 will select vrms for averag-
ing. 1 will select irms for averaging. See Figure 8.
Single Phase, Isolated, AC Power Monitoring IC
with Voltage Zero Crossing and Overcurrent Detection
ACS71020
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Register 0x0C/0x1C
Bits Name Default Value Description
6:0 rms_avg_1 0 Average of the rms voltage or current – stage 1
16:7 rms_avg_2 0 Average of the rms voltage or current – stage 2
25:17 – 0 Reserved
31:26 ecc – Error Code Correction
rms_avg_1
Number of averages for the first averaging stage (vrmsavgonesec
or irmsavgonesec). The value written into this field directly maps
to the number of averages ranging from 0 to 127. For optimal
performance, an even number of averages should be used. The
channel to be averaged is selected by the “current average select
enable” bit (iavgselen). “rms_avg_1” is further described in Table
4.
Table 4: rms_avg_1
Range Value Units
0 to 127 0 to 127 number of averages
rms_avg_2
Number of averages for the second averaging stage (vrmsavgo-
nemin or irmsavgonemin). This stage averages the outputs of the
first averaging stage. The value written into this field directly maps
to the number of averages ranging from 0 to 1023. For optimal
performance, an even number of averages should be used. The
channel to be averaged is selected by the “current average select
enable” bit (iavgselen). “rms_avg_2” is further described in Table
5.
Table 5: rms_avg_2
Range Value Units
0 to 1023 0 to 1023 number of averages
Single Phase, Isolated, AC Power Monitoring IC
with Voltage Zero Crossing and Overcurrent Detection
ACS71020
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Register 0x0D/0x1D
Bits Name Default Value Description
6:0 pacc_trim – Trims the active power
7 ichan_del_en 0 Enable phase delay on voltage or current channel
8 unused 0 unused
11:9 chan_del_sel 0 Sets phase delay on voltage or current channel
12 unused 0 unused
20:13 fault 255 Sets the overcurrent fault threshold
23:21 fltdly 0 Sets the overcurrent fault delay
24 halfcycle_en 0 Outputs pulses at every zero crossing when enabled, and every rising edge when disabled
25 squarewave_en 0 Selects pulse or square wave output for the zero crossing reporting
31:26 ecc – Error Code Correction
pacc_trim
Offset trim in the active power calculation, and is implemented
as shown in Figure 15. This is a signed 7-bit number with an
input range of –64 to 63. This equates to a trim range of –384 to
378 LSB, which is added to the “pactive” value. “pacc_trim” is
further described in Table 6.
Table 6: pacc_trim
Range Value Units
–64 to 63 –384 to 378 LSB
ichan_del_en
Enables delay for either the voltage or current channel. Setting to 1
enables delay for the current channel. This behavior is depicted in Fig-
ure 13 and Figure 14. “ichan_del_en” is further described in Table 7.
Table 7: ichan_del_en
Range Value Units
0 0 – voltage channel LSB
1 1 – current channel LSB
chan_del_sel
Sets the amount of delay applied to the voltage or current channel (set
by ichan_del_en). The step size of this field is determined by the value
of vadc_rate_sel. “chan_del_sel” is further described in Table 8.
Table 8: chan_del_sel
vadc_rate_sel Range Value Units
0 0 to 7 0 to 219 µs
1 0 to 7 0 to 875 µs
fault
Overcurrent fault threshold. This is an usigned 8-bit number with
an input range of 0 to 255, which equates to a fault range of 50%
to 175% of IP. The factory setting of this field is 0. “fault” is
further described in Table 9.
Table 9: fault
Range Value Units
0 to 255 50 to 175 % of IP
tdly
Fault delay setting of the amount of delay applied before flagging
a fault condition. “fltdly” is further described in Table 10.
Table 10: fltdly
Range Value Units
0 0 µs
1 0 µs
2 4.75 µs
3 9.25 µs
4 13.75 µs
5 18.5 µs
6 23.25 µs
7 27.75 µs
halfcycle_en
Setting for the voltage zero-crossing detection. When set to 0,
the voltage zero-crossing will be indicated on every rising edge.
When set to 1, the voltage zero-crossing will be indicated on both
rising and falling edges.
Single Phase, Isolated, AC Power Monitoring IC
with Voltage Zero Crossing and Overcurrent Detection
ACS71020
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squarewave_en
Setting for the Voltage Zero-Crossing Detection. When set to 0,
the zero-crossing event will be indicated by a pulse on the DIO
pin. When set to 1, the zero-crossing event will be indicated by a
level change on the DIO pin. Note that the device must be config-
ured to report Voltage-Zero-Crossing detection on the DIO pin.
Single Phase, Isolated, AC Power Monitoring IC
with Voltage Zero Crossing and Overcurrent Detection
ACS71020
26
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Register 0x0E/0x1E
Bits Name Default Value Description
5:0 vevent_cycs 0 Sets the number of qualifying cycles needed to flag overvoltage or undervoltage
6 vadc_rate_set 0 Sample Frequency Selection
7 – 0 Reserved
13:8 overvreg 32 Sets the overvoltage fault threshold
19:14 undervreg 32 Sets the undervoltage fault threshold
20 delaycnt_sel 0 Sets the width of the voltage zero-crossing output pulse
25:21 unused 0 Unused
31:26 ecc – Error Code Correction
vevent_cycs
Sets the number of cycles required to assert the OVRMS flag
or the UVRMS. This is an unsigned 6-bit number with an input
range of 0 to 63. The value in this field directly maps to the num-
ber of cycles. “vevent_cycs” is further described in Table 11.
Table 11: vevent_cycs
Range Value Units
0 to 63 1 to 64 cycles
vadc_rate_set
Sets the voltage ADC update rate. Setting this field to a 0 selects
a 32 kHz update. Setting this field to a 1 selects a 4 kHz update,
which will reduce the number of samples used in each rms calcu-
lation, but will allow for a larger phase delay correction between
channels (see chan_del_sel). “vadc_rate_set” is further described
in Table 12.
Table 12: vadc_rate_set
Range Value Units
0 32 kHz
1 4 kHz
overvreg
Sets the threshold of the overvoltage rms flag (ovrms). This is a
6-bit number ranging from 0 to 63. This trip level spans the entire
range of the vrms register. The flag is set if the rms value is above
this threshold for the number of cycles selected in vevent_cycs.
“overvreg” is further described in Table 13.
Table 13: overvreg
Range Value Units
0 to 63 0 to 32,768 LSB
undervreg
Sets the threshold of the undervoltage rms flag (uvrms). This is
a 6-bit number ranging from 0 to 63. This trip level spans one
entire range of the vrms register. The flag is set if the rms value is
below this threshold for the number of cycles selected in vevent_
cycs. “undervreg” is further described in Table 14.
Table 14: undervreg
Range Value Units
0 to 63 0 to 32,768 LSB
delaycnt_sel
Selection bit for the width of pulse for a voltage zero-crossing
event. When set to 0, the pulse is 32 µs. When set to 1, the
pulse is 256 µs. When the squarewave_en bit is set, this field is
ignored. “delaycnt_sel” is further described in Table 15.
Table 15: delaycnt_sel
Range Value Units
0 32 µs
1 256 µs
Single Phase, Isolated, AC Power Monitoring IC
with Voltage Zero Crossing and Overcurrent Detection
ACS71020
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Register 0x0F/0x1F
Bits Name Default Value Description
1:0 unused 0 Unused
8:2 i2c_slv_addr 0 I2C slave address selection
9 i2c_dis_slv_addr 0 Disable I2C slave address selection circuit
15:10 unused 0 Unused
17:16 dio_0_sel 0 Digital output 0 multiplexor selection bits
19:18 dio_1_sel 0 Digital output 1 multiplexor selection bits
25:20 unused 0 Unused
31:26 ecc – Error Code Correction
i2c_slv_addr
Settings for the I2C Slave Address. The Voltage on the DIO pins
are measured at power and are used to set the device’s slave
address.
Each DIO pin has 4 voltage “bins” which may be used to set
the I2C slave address. These voltages may be set using resistor
divider circuits from VCC to Ground. “i2c_slv_addr” is further
described in Table 16.
Table 16: i2c_slv_addr
DIO_1
(decimal)
DIO_0
(decimal)
Slave Address
(decimal)
0 0 96
0 1 97
0 2 98
0 3 99
1 0 100
1 1 101
1 2 102
1 3 103
2 0 104
2 1 105
2 2 106
2 3 107
3 0 108
3 1 109
3 2 110
3 3 EEPROM value
Ratio of VCC on DIO Pin
i2c_dis_slv_addr
Enables or disables the analog I2C slave address feature at power
on. When this bit is set, the I2C slave address will map directly to
i2c_slv_addr.
dio_0_sel
Determines which flags are output on the DIO0 pin. Only used
when the device is in I2C programming mode. “dio_0_sel” is
further described in Table 17.
Table 17: dio_0_sel
Value Selection
0 VZC: Voltage zero crossing
1 OVRMS: The VRMS overvoltage flag
2 UVRMS: The VRMS undervoltage flag
3 The OR of OVRMS and UVRMS (if either flag is
triggered, the DIO_0 pin will be asserted)
dio_1_sel
Determines which flags are output on the DIO1 pin. Only used
when the device is in I2C programming mode. “dio_1_sel” is
further described in Table 18.
Table 18: dio_1_sel
Value Selection
0 OCF: Overcurrent fault
1 UVRMS: The VRMS undervoltage flag
2 OVRMS: The VRMS overvoltage flag
3 The OR of OVRMS, UVRMS, and OCF (if any of
the three flags are triggered, the DIO_0 pin will be
asserted).
Single Phase, Isolated, AC Power Monitoring IC
with Voltage Zero Crossing and Overcurrent Detection
ACS71020
28
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Volatile Memory
Address
Bits
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
VOLATILE
0x20 irms vrms
0x21 pactive
0x22 papparent
0x23 pimag
0x24 pfactor
0x25 numptsout
0x26 irmsavgonesec vrmsavgonesec
0x27 irmsavgonemin vrmsavgonemin
0x28 pactavgonesec
0x29 pactavgonemin
0x2A vcodes
0x2B icodes
0x2C pinstant
0x2D
pospf
posangle
undervoltage
overvoltage
faultlatched
faultout
vzerocrossout
0x2E
0x2F access_code
0x30
customer_access
0x31
Single Phase, Isolated, AC Power Monitoring IC
with Voltage Zero Crossing and Overcurrent Detection
ACS71020
29
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Register Details – Volatile
Register 0x20
Bits Name Description
14:0 vrms Voltage RMS value
30:16 irms Current RMS value
vrms
RMS voltage output. This field is an unsigned 15-bit fixed point
number with 15 fractional bits. It ranges from 0 to ~1 with a step
size of 1/215. This number should be multiplied by the overall full
scale of the voltage path in order to get to volts. For example, the
device is trimmed to a full scale input of 275 mV, and if a resis-
tor divider network is used to create 275 mV when it has 250 V
across it, then the multiplier should be 250 V. “vrms” is further
described in Table 19.
Table 19: vrms
Range Value Units
0 to ~1 [0 to ~1] × ΔVIN(MAX) V
irms
RMS current output. This field is an unsigned 15-bit fixed point
number with 14 fractional bits. It ranges from 0 to ~2 with a step
size of 1/214. This number should be multiplied by the overall full
scale of the current path in order to get to amps. For example, if
the device is trimmed to a full scale input of 30 A, then the multi-
plier should be 30 A. “irms” is further described in Table 20.
Table 20: irms
Range Value Units
0 to ~2 [0 to ~2] × IPR(MAX) A
Register 0x21
Bits Name Description
16:0 pactive Active power
pactive
Active power output. This field is a signed 17-bit fixed point
number with 15 fractional bits. It ranges from -2 to ~2 with a step
size of 1/215. This number should be multiplied by the overall
full-scale power in order to get to watts. For example, if full-scale
voltage is 250 V and IPR is 30 A, the multiplier will be 7500 W.
“pactive” is further described in Table 21.
Table 21: pactive
Range Value Units
–2 to ~2 [–2 to ~2] × MaxPow W
Single Phase, Isolated, AC Power Monitoring IC
with Voltage Zero Crossing and Overcurrent Detection
ACS71020
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Register 0x22
Bits Name Description
15:0 papparent Apparent power
papparent
Apparent power output. This field is an unsigned 16-bit fixed
point number with 15 fractional bits. It ranges from 0 to ~2 with
a step size of 1/215. This number should be multiplied by the
overall full-scale power in order to get to VA. For example, if full
scale voltage is 250 V and IPR is 30 A, then the multiplier will be
7500 VA. “papparent” is further described in Table 22.
Table 22: papparent
Range Value Units
0 to ~2 [0 to ~2] × MaxPow VA
Register 0x23
Bits Name Description
15:0 pimag Reactive power
pimag
Reactive power output. This field is an unsigned 16-bit fixed
point number with 15 fractional bits. It ranges from 0 to ~2 with
a step size of 1/215. This number should be multiplied by the
overall full-scale power in order to get to VAR. For example, if
full-scale voltage is 250 V and IPR is 30 A, then the multiplier
will be 7500 VAR. “pimag” is further described in Table 23.
Table 23: pimag
Range Value Units
0 to ~2 [0 to ~2] × MaxPow VAR
Single Phase, Isolated, AC Power Monitoring IC
with Voltage Zero Crossing and Overcurrent Detection
ACS71020
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Register 0x24
Bits Name Description
10:0 pfactor Power factor
pfactor
Power factor output. This field is an signed 11-bit fixed point
number with 9 fractional bits. It ranges from –2 to ~2 with a step
size of 1/29. “pfactor” is further described in Table 24.
Table 24: pfactor
Range Value Units
–2 to ~2 –2 to ~2 –
Register 0x25
Bits Name Description
8:0 numptsout Number of samples of current and voltage used for calculations
numptsout
Number of points used in the rms calculation. This will be the
dynamic value that is evaluated internal to the device based on
zero crossings of the voltage channel. “numptsout” is further
described in Table 25.
Table 25: numptsout
Range Value Units
0 to 511 0 to 511 –
Single Phase, Isolated, AC Power Monitoring IC
with Voltage Zero Crossing and Overcurrent Detection
ACS71020
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Register 0x26
Bits Name Description
14:0 vrmsavgonesec Averaged voltage RMS value – duration set by rms_avg_1 –
This register will be zero if iavgselen = 1
30:16 irmsavgonesec Averaged current RMS value – duration set by rms_avg_1 –
This register will be zero if iavgselen = 0
vrmsavgonesec
Voltage RMS value averaged according to rms_avg_1. This regis-
ter will be zero if iavgselen = 1.
irmsavgonesec
Current RMS value averaged according to rms_avg_1. This regis-
ter will be zero if iavgselen = 0.
Register 0x27
Bits Name Description
14:0 vrmsavgonemin Averaged voltage RMS value – duration set by rms_avg_2 – This register will be zero if
iavgselen = 1
30:16 irmsavgonemin Averaged current RMS value – duration set by rms_avg_2 – This register will be zero if
iavgselen = 0
vrmsavgonemin
Voltage RMS value averaged according to rms_avg_2. This regis-
ter will be zero if iavgselen = 1.
irmsavgonemin
Current RMS value averaged according to rms_avg_2. This regis-
ter will be zero if iavgselen = 0.
Register 0x28
Bits Name Description
16:0 pactavgonesec Active Power value averaged over up to one second — duration set by rms_avg_1
pactavgonesec
Active power value averaged according to rms_avg_1.
Register 0x29
Bits Name Description
16:0 pactavgonemin Active Power value averaged over up to one minute — duration set by rms_avg_2
pactavgonemin
Active power value averaged according to rms_avg_2.
Single Phase, Isolated, AC Power Monitoring IC
with Voltage Zero Crossing and Overcurrent Detection
ACS71020
33
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Register 0x2A
Bits Name Description
16:0 vcodes Instantaneous voltage measurement
vcodes
This field contains the instantaneous voltage measurement before
any rms calculations are done. It is a 17-bit signed fixed point
number with 16 fractional bits. It ranges from –1 to ~1 with a step
size of 1/216. This number should be multiplied by the overall full
scale of the voltage path in order to get volts. For example, the
device is trimmed to a full-scale input of 275 mV, and if a resis-
tor divider network is used to create 275 mV, when it has 250 V
across it, then the multiplier should be 250 V. “vcodes” is further
described in Table 26.
Table 26: vcodes
Range Value Units
–1 to ~1 [–1 to ~1] × ΔVIN(MAX) V
Register 0x2B
Bits Name Description
16:0 icodes Instantaneous current measurement
icodes
This field contains the instantaneous current measurement before
any rms calculations are done. This field is a signed 17-bit fixed
point number with 15 fractional bits. It ranges from –2 to ~2
with a step size of 1/215. This number should be multiplied by
the overall full scale of the current path in order to get amps. For
example, the device is trimmed to a full-scale input of 30 A, then
the multiplier should be 30 A. “icodes” is further described in
Table 27.
Table 27: icodes
Range Value Units
–2 to ~2 [–2 to ~2] × IPR(MAX) A
Single Phase, Isolated, AC Power Monitoring IC
with Voltage Zero Crossing and Overcurrent Detection
ACS71020
34
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Register 0x2C
Bits Name Description
31:0 pinstant Instantaneous power – Multiplication of Vcodes and Icodes
pinstant
This field contains the instantaneous power measurement before
any rms calculations are done. This field is a signed 32-bit fixed
point number with 29 fractional bits. It ranges from –4 to ~4 with
a step size of 1/229. This number should be multiplied by the
overall full-scale power in order to get to watts. For example, if
full scale voltage is 250 V and IPR is 30 A, then the multiplier will
be 7500 W. “pinstant” is further described in Table 28.
Table 28: pinstant
Range Value Units
–4 to ~4 [–4 to ~4] × MaxPow W
Register 0x2D
Bits Name Description
0 vzerocrossout Voltage zero-crossing output
1 faultout Current fault output
2 faultlatched Current fault output latched
3 overvoltage Overvoltage flag
4 undervoltage Undervoltage flag
5 posangle Sign of the power angle
6 pospf Sign of the power factor
vzerocrossout
Flag for the voltage zero-crossing events. Will be present and
active regardless of DIO_0_Sel and DIO_1_Sel. This flag will
still follow the halfcycle_en and squarewave_en settings.
faultout
Flag for the overcurrent events. Will be present and active regard-
less of DIO_0_Sel and DIO_1_Sel. Will only be set when fault is
present.
faultlatched
Flag for the overcurrent events. This bit will latch and will remain
1 as soon as an overcurrent event is detected. This can be reset by
writing a 1 to this field. Will be present and active regardless of
DIO settings.
overvoltage
Flag for the overvoltage events. Will be present and active
regardless of DIO_0_Sel and DIO_1_Sel. Will only be set when
fault is present.
undervoltage
Flag for the undervoltage events. Will be present and active
regardless of DIO_0_Sel and DIO_1_Sel. Will only be set when
fault is present.
posangle
Bit to represent leading or lagging. A 0 represents the current
leading and a 1 represents the current lagging.
pospf
Sign bit to represent if the power is being generated (0) or con-
sumed (1).
Single Phase, Isolated, AC Power Monitoring IC
with Voltage Zero Crossing and Overcurrent Detection
ACS71020
35
Allegro MicroSystems
955 Perimeter Road
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Register 0x2F
Bits Name Description
31:0 access_code Access code register:
Customer code: 0x4F70656E
Register 0x30
Bits Name Description
0 customer_access Customer write access enabled.
0 = Non Customer mode.
1 = Customer mode.
Single Phase, Isolated, AC Power Monitoring IC
with Voltage Zero Crossing and Overcurrent Detection
ACS71020
36
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
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VOLTAGE INPUT APPLICATION CONNECTIONS
Figure 16: Floating AC voltage source (device ground is isolated)
Figure 17: Ground referenced AC voltage source (device GND is common with voltage source GND)
R1
1 MΩ 1 MΩ
1 MΩ 1 MΩ
R2
R3 R4
RSENSE
VINP
VINN
Vin
R1
1 MΩ 1 MΩ
R2
R5
1 MΩ
VINP
VINN
RSENSE Vin
C1
C2
1 µF
1 µF 1 MΩ 1 MΩ
Optional
Due to the input buffer Common Mode Input Voltage requirement
there are possible two circuit configurations:
1. In Figure 16: the neutral line must be isolated from the
ground powering the device to allow the common mode
voltage of VINN to sit at 2/3 VCC.
2. In Figure 17: capacitors block the DC component of the
voltage input and allow the internal resistor divider to bias
VINN to 2/3 VCC. If the isolation state of the application is
unknown, this schematic works in both cases.
RSENSE should be sized according to the full-scale signal level
that can be applied to the voltage channel ±275 mV and expected
maximum measured voltage.
RSENSE values used in figures below are examples for AC
240 Vrms input signal.
Single Phase, Isolated, AC Power Monitoring IC
with Voltage Zero Crossing and Overcurrent Detection
ACS71020
37
Allegro MicroSystems
955 Perimeter Road
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APPLICATION INFORMATION
Thermal Rise vs. Primary Current
Self-heating due to the flow of current should be considered dur-
ing the design of any current sensing system. The sensor, printed
circuit board (PCB), and contacts to the PCB will generate heat
as current moves through the system.
The thermal response is highly dependent on PCB layout, copper
thickness, cooling techniques, and the profile of the injected current.
The current profile includes peak current, current “on-time”, and
duty cycle. While the data presented in this section was collected
with direct current (DC), these numbers may be used to approximate
thermal response for both AC signals and current pulses.
The plot in Figure 18 shows the measured rise in steady-state die
temperature of the ACS71020 versus continuous current at an ambi-
ent temperature, TA, of 25 °C. The thermal offset curves may be
directly applied to other values of TA. Conversely, Figure 19 shows
the maximum continuous current at a given TA. Surges beyond the
maximum current listed in Figure 19 are allowed given the maxi-
mum junction temperature, TJ(MAX) (165℃), is not exceeded.
0
20
40
60
80
100
120
140
0 10 20 30 40 50 60 70
Change in Die Temperature
(°C)
Continuous Current (A)
Figure 18: Self Heating in the MA Package
Due to Current Flow
0
10
20
30
40
50
60
70
80
25 50 75 100 125 150 175
Continuous Current (A)
Ambient Temperature (°C)
Figure 19: Maximum Continuous Current at a Given TA
The thermal capacity of the ACS71020 should be verified by the
end user in the application’s specific conditions. The maximum
junction temperature, TJ(MAX) (165℃), should not be exceeded.
Further information on this application testing is available in
the DC and Transient Current Capability application note on the
Allegro website.
ASEK71020 Evaluation Board Layout
Thermal data shown in Figure 18 and Figure 19 was collected
using the ASEK71020 Evaluation Board (TED-0002170). This
board includes 1500 mm2 of 2 oz. copper (0.0694 mm) connected
to pins 1 through 4, and to pins 5 through 8, with thermal vias
connecting the layers. Top and Bottom layers of the PCB are
shown below in Figure 20.
Figure 20: Top and Bottom Layers
for ASEK71020 Evaluation Board
Gerber files for the ASEK71020 evaluation board are available
for download from the Allegro website. See the technical docu-
ments section of the ACS71020 device webpage.
Single Phase, Isolated, AC Power Monitoring IC
with Voltage Zero Crossing and Overcurrent Detection
ACS71020
38
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
RECOMMENDED PCB LAYOUT
7.25
2.25
3.56
1.27
1.27
0.65
15.75
9.54
17.27
21.51
Package Outline
Slot in PCB to maintain >8 mm creepage
once part is on PCB
Current
In
Current
Out
Perimeter holes for stitching to the other,
matching current trace design, layers of
the PCB for enhanced thermal capability.
NOT TO SCALE
All dimensions in millimeters.
Figure 21: Recommended PCB Layout
Single Phase, Isolated, AC Power Monitoring IC
with Voltage Zero Crossing and Overcurrent Detection
ACS71020
39
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
Figure 22: Package MA, 16-Pin SOICW
PACKAGE OUTLINE DRAWING
For Reference Only – Not for Tooling Use
(Reference MS-013AA)
NOT TO SCALE
Dimensions in millimeters
Dimensions exclusive of mold flash, gate burrs, and dambar protrusions
Exact case and lead configuration at supplier discretion within limits shown
C
1.27 BSC
A
B
C
B
21
1
16
Branding scale and appearance at supplier discretion
C
SEATING
PLANE
C0.10
16
×
0.25 BSC
1.40 REF
2.65 MAX
10.30 ±0.20
7.50 ±0.10 10.30 ±0.33
0.51
0.31
0.30
0.10
0.33
0.20
1.27
0.40
8°
0°
A
Standard Branding Reference View
Branded Face
SEATING PLANE
GAUGE PLANE
XXXXXXX
Lot Number
Lines 1, 2 = 12 characters
Line 1: Part Number
Line 2: First 8 characters of Assembly Lot Number
Terminal #1 mark area
C
2
1
16
0.65 1.27
9.50
2.25
PCB Layout Reference View
Reference land pattern layout (reference IPC7351 SOIC127P600X175-8M);
all pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary
to meet application process requirements and PCB layout tolerances
0.90
D
DHall elements (D1, D2), not to scale
D
D1
D2
E
Active Area Depth 0.293 mm
E
Single Phase, Isolated, AC Power Monitoring IC
with Voltage Zero Crossing and Overcurrent Detection
ACS71020
40
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
For the latest version of this document, visit our website:
www.allegromicro.com
Revision History
Number Date Description
– June 20, 2018 Initial release
1 September 19, 2018
Updated Features and Benefits, Description (page 1), Isolation Characteristics, Thermal Characteristics (page
3), Power Calculations section (pages 13-14), Digital Communication (page 15), Register Details (pages 20-33),
Applications Connections (page 34), and Package Outline Drawing (page 36).
2 December 14, 2018 Updated certification
3 January 10, 2019 Updated register defaults (pages 20-22, 24-25), Voltage Input Application Connections section (page 34),
bypass_n_en description (page 24), and pfactor description (page 29).
4 March 15, 2019
Updated Title (all pages), Voltage Zero Crossing (page 6), ADCs section (page 12), Communication Interfaces section
(page 15), Memory Map (page 18), Register 0x0C/0x1C (page 21), Register 0x0E/0x1E (page 24), Register 0x25
(page 29), and Application Connections (page 34). Added Operating Characteristics footnote (page 8).
5 April 29, 2019
Updated Figure 1 (page 1), Power Calculations section (page 14-16), Register 0x0C/0x1C (page 23),
Table 16 (page 27), Volatile Memory table (page 28), Register 28 (page 30), Register 0x2C (page 34),
and Figure 17 (page 36); added Power-On Time (page 6) and DIO Pins characteristics (page 7).
6 May 15, 2019 Updated Creepage (page 3); added TUV certificate mark.
7 June 3, 2019 Updated Table 12 (page 26), register 0x28, and register 0x29 (page 32).
8 June 17, 2019 Updated posangle and pospf (page 34).
9 November 21, 2019
Added Maximum Continuous Current to Absolute Maximum Ratings table, Distance Through Insulation and
Comparative Tracking Index to Isolation Characteristics table, ESD ratings table (page 3), and thermal data
section (page 37)
Copyright 2019, Allegro MicroSystems.
Allegro MicroSystems reserves the right to make, from time to time, such departures from the detail specifications as may be required to permit
improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the
information being relied upon is current.
Allegro’s products are not to be used in any devices or systems, including but not limited to life support devices or systems, in which a failure of
Allegro’s product can reasonably be expected to cause bodily harm.
The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems assumes no responsibility for its use; nor
for any infringement of patents or other rights of third parties which may result from its use.
Copies of this document are considered uncontrolled documents.