Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
March 25, 1997 – Re vised July 29, 1997
CY2305 and CY2309 as PCI and SDRAM Buffers
Introduction to Cypress Zero Delay Buffer s
What is a Zero Delay Buffer?
A zero delay b uffer is a de vice that can fan out 1 clock signal
into multiple clock signals with zero delay and ver y low skew
between the outputs. This device is well suited as a buffer for
PCI or SDRAM due to its zero input to out put delay and very
low output to output skew.
A simplified diagram of the CY2308 zero delay buffer is shown
in Figure 1. The CY2308 is built using a PLL that uses a ref-
erence input and a feedback input. The feedback loop is
closed by driving the feedback input (FBK) from one of the
outputs. The phase detector in the PLL adjusts the output
frequency of the VCO so that the two inputs have no phase
difference. Since an output is one of the inputs to the PLL,
zero phase difference is maintained from REF to the output
driving FBK. Now if all outputs are uniformly loaded, zero
phase difference will be maintained from REF to all outputs.
This is a simple zero delay buffer. Introducing additional de-
vices (e.g., dividers) between the output and FBK can give
rise to some innovative applications for the PLL, and for fur-
ther information on these refer to the Cypress Application
Note “CY2308 Zero Delay Buffer”. Since many bufferi ng ap-
pli cations require only a simple closur e of t he feedbac k loop,
Cypress has designed zero delay buffers with Internal Feed-
back Loops: the CY2305 and CY2309.
What are the CY2305 and CY2309?
Cypres s h as d esigned z ero de la y b u ff er s especial ly suited f or
use with PCI or SDRAM buffering. The CY2305 and CY2309
have been designed with the feedback path integrated for
simpler system design. A simplified block diagram of the
CY2309 zero delay buffer is shown Figur e 2. Thi s zero delay
buffer uses a input/output pad on CLKOUT so that the feed-
back signal can be sensed direc tly from the output itself.
Drive Capabi li ty
The CY2305 and CY2309 have high drive outputs designed
to meet the JEDEC SDRAM specifications of 30 pF capaci-
tance on each DIMM clock input.
Since the typi cal CMOS input is 7 pF and the CY2305/0 9 are
designed to dri ve up to 30 pF; thi s m eans that up to 4 CMOS
inputs can be driven from a single output of a CY2305/09.
How ever t he ou tput loadi ng o n the CY2305/ 09 mu st be equal
on all outputs to maintain zer o delay from the input .
Power Down
The CY2305 and CY2309 ha ve a un ique power-down mode:
if t he in put r ef ere nce is st oppe d, th e part au tomati call y enter s
a shutdown state, shutting down the PLL and three-stating the
output s. Whe n the part is i n shutdo wn mode i t dra ws less than
50 µA, and can come out of shutdown mode with the PLL
locked in les s than 1 m s. This power down mode can also be
entered by three-stating the input refere nce dri ver and allow-
ing the internal pull-down to pull the input LOW (the input
does not have to go LO W, it only has to stop).
5 Volt to 3.3 Volt Level Shifting
The CY2305 and CY2309 can ac t as a 5-volt to 3.3-volt lev el
shifter. The reference input pad is 5-volt signal-compatible.
Since many system components still operate at 5 volts, this
feature provides the capability to generate multiple 3.3-volt
clocks from a single 5-volt reference clock. This 5-volt sig-
nal-compatibility is only available on the reference pad; the
other i nput pads on the CY2309 are not 5-volt com patible.
Figure 1. Simplified Block Diagr am of CY2308
VCO
REF CLKA1
CLKA2
CLKA3
CLKA4
FBK
Loop
Filter
Phase
Detector PLL MUX
Select Input
Decoding
S2
S1 CLKB1
CLKB2
CLKB3
CLKB4
Figure 2. Simplified Block Di agram of CY2309
VCO
REF CLKA1
CLKA2
CLKA3
CLKA4
CLKOUT
Loop
Filter
Phase
Detector PLL MUX
Select Input
Decoding
S2
S1 CLKB1
CLKB2
CLKB3
CLKB4