LH28F016SA 16M (1M x 16/2M x 8) Flash Memory FEATURES DESCRIPTION * User-Selectable 3.3 V or 5 V VCC SHARP's LH28F016SA 16M Flash Memory is a revolutionary architecture which enables the design of truly mobile, high-performance, personal computing and communication products. With innovative capabilities, low power operation and very high read/write performance, the LH28F016SA is also the ideal choice for designing embedded mass storage flash memory systems. * User-Configurable x8 or x16 Operation * Access Times: For 3.3 V Read: 120/150 ns For 5 V Read: 70/100 ns * 0.43 MB/sec Write Transfer Rate * 1 Million Erase Cycles per Block * 56-Lead, 1.2 mm x 14 mm x 20 mm TSOP Package * Revolutionary Architecture - Pipelined Command Execution - Write During Erase - Command Superset of SHARP's LH28F008SA * 1 mA Typical ICC in Static Mode * 1 A Typical Deep Power-Down * 32 Independently Lockable Blocks * State-of-the-Art 0.6 m ETOX Technology 1 TM 1 The LH28F016SA is a very high density, highest performance non-volatile read/write solution for solid-state storage applications. Its symmetrically blocked architecture (100% compatible with the LH28F008SA 8M Flash memory), extended cycling, low power 3.3 V operation, very fast write and read performance and selective block locking provide a highly flexible memory component suitable for high-density memory cards, Resident Flash Arrays and PCMCIA-ATA Flash Drives. The LH28F016SA's dual read voltage enables the design of memory cards which can interchangeably be read/written in 3.3 V and 5.0 V systems. Its x8/x16 architecture allows the optimization of memory to processor interface. The flexible block locking option enables bundling of executable application software in a Resident Flash Array or memory card. Manufactured on SHARP's 0.6 m ETOXTM 1 process technology, the LH28F016SA is the most cost-effective, high-density 3.3 V flash memory. Flash ETOX is a trademark of Intel Corporation. 7-69 LH28F016SA 1.0 INTRODUCTION The documentation of the SH ARP LH28F016SA memory device includes this data sheet, a detailed user's manual, and a number of application notes, all of which are referenced at the end of this data sheet. The data sheet is intended to give an overview of the chip feature-set and of the operating AC/DC specifications. The LH28F016SA User's Manual provides complete descriptions of the user modes, system interface examples, and detailed descriptions of all principles of operation. It also contains the full list of software algorithm flowcharts, and a brief section on compatibility with SHARP LH28F008SA. 1.1 Product Overview The LH28F016SA is a high-performance 16M (16,777,216 bit) block erasable non-volatile random access memory organized as either 1 Mword x 16 or 2 Mbyte x 8. The LH28F016SA includes thirty-two 64KB (65,536) blocks or thirty-two 32-KW (32,768) blocks. A chip memory map is shown in Figure 3. The implementation of a new architecture, with many enhanced features, will improve the device operating characteristics and results in greater product reliability and ease of use. Some significant enhancements of the LH28F016SA include: * 3.3 V Low Power Capability * Improved Write Performance * Dedicated Block Write/Erase Protection A 3/5# input pin reconfigures the device internally for optimized 3.3 V or 5.0 V read/write operation. The LH28F016SA will be available in a 56-lead, 1.2 mm thick, 14 mm x 20 mm TSOP type 1 package. This form factor and pinout allow for very high board layout densities. A Command User Interface (CUI) serves as the system interface between the microprocessor or microcontroller and the internal memory operation. Internal Algorithm Automation allows Byte/Word Writes and Block Erase operations to be executed using a Two-Write command sequence to the CUI in the same way as the LH28F008SA 8M Flash memory. 7-70 16M (1M x 16/2M x 8) Flash Memory A Superset of commands have been added to the basic LH28F008SA command-set to achieve higher write performance and provide additional capabilities. These new commands and features include: * Page Buffer Writes to Flash * Command Queuing Capability * Automatic Data Writes During Erase * Software Locking of Memory Blocks * Two-Byte Successive Writes in 8-bit Systems * Erase All Unlocked Blocks Writing of memory data is performed in either byte or word increments typically within 6 sec, a 33% improvement over the LH28F008SA. A Block Erase operation erases one of the 32 blocks in typically 0.6 sec, independent of the other blocks, which is about 65% improvement over the LH28F008SA. Each block can be written and erased a minimum of 100,000 cycles. Systems can achieve 1 million Block Erase Cycles by providing wear-leveling algorithms and graceful block retirement. These techniques have already been employed in many flash file systems and Hard Disk Drive designs. The LH28F016SA incorporates two Page Buffers of 256 Bytes (128 Words) each to allow page data writes. This feature can improve a system write performance by up to 4.8 times over previous flash memory devices. All operations are started by a sequence of Write commands to the device. Three Status Registers (described in detail later) and a RY/BY# output pin provide information on the progress of the requested operation. While the LH28F008SA requires an operation to complete before the next operation can be requested, the LH28F016SA allows queuing of the next operation while the memory executes the current operation. This eliminates system overhead when writing several bytes in a row to the array or erasing several blocks at the same time. The LH28F016SA can also perform write operations to one block of memory while performing erase of another block. The LH28F016SA provides user-selectable block locking to protect code or data such as Device Drivers, PCMCIA card information, ROM-Executable O/S or Application Code. Each block has an associated nonvolatile lock-bit which determines the lock status of the block. In addition, the LH28F016SA has a master Write Protect pin (WP#) which prevents any modifications to memory blocks whose lock-bits are set. 16M (1M x 16/2M x 8) Flash Memory The LH28F016SA contains three types of Status Registers to accomplish various functions: * A Compatible Status Register (CSR) which is 100% compatible with the LH28F008SA Flash memory's Status Register. This register, when used alone, provides a straightforward upgrade capability to the LH28F016SA from a LH28F008SA-based design. * A Global Status Register (GSR) which informs the system of command Queue status, Page Buffer status, and overall Write Status Machine (WSM) status. * 32 Block Status Registers (BSRs) which provide block-specific status information such as the block lock-bit status. The GSR and BSR memory maps for Byte-Wide and Word-Wide modes are shown in Figures 4.1 and 4.2. The LH28F016SA incorporates an open drain RY/BY# output pin. This feature allows the user to OR-tie many RY/BY# pins together in a multiple memory configuration such as a Resident Flash Array. Other configurations of the RY/BY# pin are enabled via special CUI commands and are described in detail in the LH28F016SA User's Manual. The LH28F016SA also incorporates a dual chip-enable function with two input pins, CE0# and CE 1#. These pins have exactly the same functionality as the regular chip-enable pin CE# on the LH28F008SA. For minimum chip designs, CE1# may be tied to ground and use CE0# as the chip enable input. The LH28F016SA uses the logical combination of these two signals to enable or disable the entire chip. Both CE0# and CE1# must be active low to enable the device and if either one becomes inactive, thechip will be di sabled. This feature, along with the open drain RY/BY# pin, allows the system designer to reduce the number of control pins used in a large array of 16M devices. LH28F016SA mode with address A0 selecting between low byte and high byte. On the other hand, BYTE# at logic high enables 16-bit operation with address A1 becoming the lowest order address and address A0 is not used (don't care). A device diagram is shown in Figure 1. The LH28F016SA is specified for a maximum access time of 70 ns (tACC) at 5.0 V operation (4.75 V to 5.25 V) over the commercial temperature range (0C to +70C). A corresponding maximum access time of 120 ns at 3.3 V (3.0 V to 3.6 V and 0C to +70C) is achieved for reduced power consumption applications. The LH28F016SA incorporates an Automatic Power Saving (APS) feature which substantially reduces the active current when the device is in static mode of operation (addresses not switching). In APS mode, the typical ICC current is 1 mA at 5.0 V (0.8 mA at 3.3 V). A Deep Power-Down mode of operation is invoked when the RP# (called PWD on the LH28F008SA) pin transitions low. This mode brings the device power consumption to less than 1.0 A, typically, and provides additional write protection by acting as a device reset pin during power transitions. A reset time of 400 ns is required from RP# switching high until outputs are again valid. In the Deep Power-Down state, the WSM is reset (any current operation will abort) and the CSR, GSR, and BSR registers are cleared. A CMOS Standby mode of operation is enabled when either CE 0# or CE1# transitions high and RP# stays high with all input control pins at CMOS levels. In this mode, the device typically draws an ICC standby current of 50 A. 2.0 DEVICE PINOUT The LH28F016SA 56L-TSOP Type I pinout configuration is shown in Figure 2. The BYTE# pin allows either x8 or x16 read/writes to the LH28F016SA. BYTE# at logic low selects 8-bit 7-71 16M (1M x 16/2M x 8) Flash Memory LH28F016SA DQ 8-15 DQ 0-7 Output Buffer Output Buffer Input Buffer Input Buffer I/O Logic 3/5# BYTE# OUTPUT MULTIPLEXER ID Register DATA QUEUE REGISTERS CSR PAGE BUFFERS CE0# CE1# OE# ESRs CUI WE# A0-20 Data Comparator WP# RP# Input Buffer Y-DECODER Y GATING/SENSING 64-KBYTE Block 31 64-KBYTE Block 30 64-KBYTE Block 1 X-DECODER 64-KBYTE Block 0 RY/BY# ADDRESS QUEUE LATCHES WSM Program/Erase Voltage Switch VPP 3/5# VCC ADDRESS COUNTER Figure 1. LH28F016SA Block Diagram Architectural Evolution Includes Page Buffers, Queue Registers, and Extended Status Registers 7-72 GND 16M (1M x 16/2M x 8) Flash Memory LH28F016SA 2.1 Lead Descriptions Symbol Type Name and Function A0 INPUT BYTE-SELECT ADDRESS: Selects between high and low byte when device is in x8 mode. This address is latched in x8 Data Writes. Not used in x16 mode (i.e., the A0 input buffer is turned off when BYTE# is high). A1-A15 INPUT WORD-SELECT ADDRESSES: Select a word within one 64-Kbyte block. A6-15 selects 1 of 1024 rows, and A1-5 selects 16 of 512 columns. These addresses are latched during Data Writes. A16-A20 INPUT BLOCK-SELECT ADDRESSES: Select 1 of 32 Erase blocks. These addresses are latched during Data Writes, Erase and Lock-Block operations. DQ0-DQ7 INPUT/OUTPUT LOW-BYTE DATA BUS: Inputs data and commands during CUI write cycles. Outputs array, buffer, identifier or status data in the appropriate Read mode. Floated when the chip is de-selected or the outputs are disabled. DQ8-DQ15 INPUT/OUTPUT HIGH-BYTE DATA BUS: Inputs data during x16 Data-Write operations. Outputs array, buffer or identifier data in the appropriate Read mode; not used for Status register reads. Floated when the chip is de-selected or the outputs are disabled. CE0#, CE1# INPUT CHIP ENABLE INPUTS: Activate the device's control logic, input buffers, decoders and sense amplifiers. With either CE0# or CE1# high, the device is de-selected and power consumption reduces to Standby levels upon completion of any current Data-Write or Erase operations. Both CE0#, CE1# must be low to select the device. All timing specifications are the same for both signals. Device Selection occurs with the latter falling edge of CE0# or CE1#. The first rising edge of CE0# or CE1# disables the device. RP# INPUT RESET/POWER-DOWN: RP# low places the device in a Deep PowerDown state. All circuits that burn static power, even those circuits enabled in standby mode, are turned off. When returning from Deep Power-Down, a recovery time of 400 ns is required to allow these circuits to power-up. When RP# goes low, any current or pending WSM operation(s) are terminated, and the device is reset. All Status registers return to ready (with all status flags cleared). OE# INPUT OUTPUT ENABLE: Gates device data through the output buffers when low. The outputs float to tri-state off when OE# is high. NOTE: CEX# overrides OE#, and OE# overrides WE#. WE# INPUT WRITE ENABLE: Controls access to the CUI, Page Buffers, Data Queue Registers and Address Queue Latches. WE# is active low, and latches both address and data (command or array) on its rising edge. RY/BY# OPEN DRAIN OUTPUT READY/BUSY: Indicates status of the internal WSM. When low, it indicates that the WSM is busy performing an operation. RY/BY# high indicates that the WSM is ready for new operations (or WSM has completed all pending operations), or Erase is Suspended, or the device is in deep power-down mode. This output is always active (i.e., not floated to tri-state off when OE# or CE0#, CE1# are high), except if a RY/BY# Pin Disable command is issued. 7-73 16M (1M x 16/2M x 8) Flash Memory LH28F016SA 2.1 Lead Descriptions (Continued) Symbol Type Name and Function WP# INPUT WRITE PROTECT: Erase blocks can be locked by writing a non-volatile lock-bit for each block. When WP# is low, those locked blocks as reflected by the Block-Lock Status bits (BSR.6), are protected from inadvertent Data Writes or Erases. When WP# is high, all blocks can be Written or Erased regardless of the state of the lockbits. The WP# input buffer is disabled when RP# transitions low (deep power-down mode). BYTE# INPUT BYTE ENABLE: BYTE# low places device in x8 mode. All data is then input or output on DQ0-7, and DQ8-15 float. Address A0 selects between the high and low byte. BYTE# high places the device in x16 mode, and turns off the A0 input buffer. Address A1, then becomes the lowest order address. 3/5# INPUT 3.3/5.0 VOLT SELECT: 3/5# high configures internal circuits for 3.3V operation. 3/5# low configures internal circuits for 5.0V operation. NOTES: Reading the array with 3/5# high in a 5.0V system could damage the device. There is a significant delay from 3/5# switching to valid data. VPP SUPPLY ERASE/WRITE POWER SUPPLY: For erasing memory array blocks or writing words/ bytes/pages into the flash array. VCC SUPPLY DEVICE POWER SUPPLY (3.3V 0.3V, 5.0V 0.5V): Do not leave any power pins floating. GND SUPPLY GROUND FOR ALL INTERNAL CIRCUITRY: Do not leave any ground pins floating. NC 3/5# CE1# NC A20 A19 A18 A17 A16 VCC A15 A14 A13 A12 CE0# VPP RP# A11 A10 A9 A8 GND A7 A6 A5 A4 A3 A2 A1 NO CONNECT: No internal connection to die, lead may be driven or left floating. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 LH28F016SA 56-LEAD TSOP PINOUT 14mm x 20mm TOP VIEW Figure 2. TSOP Configuration NOTE: 56-LEAD TSOP Mechanical Diagrams and Dimensions are shown at the end of this specification 7-74 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 WP# WE# OE# RY/BY# DQ15 DQ7 DQ14 DQ6 GND DQ13 DQ5 DQ12 DQ4 V CC GND DQ11 DQ3 DQ10 DQ2 V CC DQ9 DQ1 DQ8 DQ0 A0 BYTE# NC NC 16M (1M x 16/2M x 8) Flash Memory LH28F016SA 3.0 MEMORY MAPS 1FFFFF 1F0000 1EFFFF 1E0000 1DFFFF 1D0000 1CFFFF 1C0000 1BFFFF 1B0000 1AFFFF 1A0000 19FFFF 190000 18FFFF 180000 17FFFF 170000 16FFFF 160000 15FFFF 150000 14FFFF 140000 13FFFF 130000 12FFFF 120000 11FFFF 110000 10FFFF 100000 0FFFFF 0F0000 0EFFFF 0E0000 0DFFFF 0D0000 0CFFFF 0C0000 0BFFFF 0B0000 0AFFFF 0A0000 09FFFF 090000 08FFFF 080000 07FFFF 070000 06FFFF 060000 05FFFF 050000 04FFFF 040000 03FFFF 030000 02FFFF 020000 01FFFF 010000 00FFFF 000000 64 KByte Block 31 64 KByte Block 30 64 KByte Block 29 64 KByte Block 28 64 KByte Block 27 64 KByte Block 26 64 KByte Block 25 64 KByte Block 24 64 KByte Block 23 64 KByte Block 22 64 KByte Block 21 64 KByte Block 20 64 KByte Block 19 64 KByte Block 18 64 KByte Block 17 64 KByte Block 16 64 KByte Block 15 64 KByte Block 14 64 KByte Block 13 64 KByte Block 12 64 KByte Block 11 64 KByte Block 10 64 KByte Block 9 64 KByte Block 8 64 KByte Block 7 64 KByte Block 6 64 KByte Block 5 64 KByte Block 4 64 KByte Block 3 64 KByte Block 2 64 KByte Block 1 64 KByte Block 0 Figure 3. LH28F016SA Memory Map (Byte-Wide Mode) 7-75 16M (1M x 16/2M x 8) Flash Memory LH28F016SA 3.1 Extended Status Registers Memory Map X8 MODE A[20:0] RESERVED GSR RESERVED BSR31 RESERVED RESERVED 1F0006H 1F0005H 1F0004H 1F0003H 1F0002H 1F0001H 1F0000H X16 MODE A[20:1] RESERVED GSR RESERVED BSR31 RESERVED RESERVED 010002H RESERVED RESERVED GSR RESERVED BSR0 RESERVED RESERVED F8002H F8001H F8000H 08001H RESERVED 000006H 000005H RESERVED 000004H GSR 000003H RESERVED 000002H BSR0 000001H RESERVED 000000H RESERVED Figure 4.1. Extended Status Register Memory Map (Byte-Wide Mode) 7-76 F8003H 00003H 00002H 00001H 00000H Figure 4.2. Extended Status Register Memory Map (Word-Wide Mode) 16M (1M x 16/2M x 8) Flash Memory LH28F016SA 4.0 BUS OPERATIONS, COMMANDS AND STATUS REGISTER DEFINITIONS 4.1 Bus Operations for Word-Wide Mode (BYTE# = VIH) Mode Notes RP# CE 1# CE 0# OE# WE# A 1 DQ0-15 RY/BY# Read 1,2,7 VIH VIL VIL VIL VIH X DOUT X Output Disable 1,6,7 VIH VIL VIL VIH VIH X High Z X Standby 1,6,7 VIH VIL VIH VIH VIH VIL VIH X X X High Z X 1,3 VIL X X X X X High Z VOH Manufacturer ID 4 VIH VIL VIL VIL VIH VIL 0089H VOH Device ID 4 VIH VIL VIL VIL VIH VIH 66A0H VOH 1,5,6 VIH VIL VIL VIH VIL X DIN X DQ0-7 RY/BY# Deep Power-Down Write 4.2 Bus Operations For Byte-Wide Mode (BYTE# =VIL) Mode Notes RP# CE 1# CE 0# OE# WE# A 0 Read 1,2,7 VIH VIL VIL VIL VIH X DOUT X Output Disable 1,6,7 VIH VIL VIL VIH VIH X High Z X 1,6,7 VIH VIL VIH VIH VIH VIL VIH X X X High Z X 1,3 VIL X X X X X High Z VOH Manufacturer ID 4 VIH VIL VIL VIL VIH VIL 89H VOH Device ID 4 VIH VIL VIL VIL VIH VIH A0H VOH 1,5,6 VIH VIL VIL VIH VIL X DIN X Standby Deep Power-Down Write NOTES: 1. X can be VIH or VIL for address or control pins except for RY/BY#, which is either VOL or VOH. 2. RY/BY# output is open drain. When the WSM is ready, Erase is suspended or the device is in deep power-down mode, RY/BY# will be at VOH if it is tied to VCC through a resistor. When the RY/BY# at VOH is independent of OE# while a WSM operation is in progress. 3. RP# at GND 0.2 V ensures the lowest deep power-down current. 4. A0 and A1 at VIL provide manufacturer ID codes in x8 and x16 modes respectively. A0 and A1 at VIH provide device ID codes in x8 and x16 modes respectively. All other addresses are set to zero. 5. Commands for different Erase operations, Data Write operations of Lock-Block operations can only be successfully completed when VPP = VPPH. 6. While the WSM is running, RY/BY# in Level-Mode (default) stays at VOL until all operations are complete. RY/BY# goes to VOH when the WSM is not busy or in erase suspend mode. 7. RY/BY# may be at VOL while the WSM is busy performing various operations. For example, a status register read during a write operation. 7-77 16M (1M x 16/2M x 8) Flash Memory LH28F016SA 4.3 LH28F008SA-Compatible Mode Command Bus Definitions Command Notes Read Array First Bus Cycle Data Second Bus Cycle Oper Addr Oper Addr Data Write X FFH Read AA AD Intelligent Identifier 1 Write X 90H Read IA ID Read Compatible Status Register 2 Write X 70H Read X CSRD Clear Status Register 3 Write X 50H Word/Byte Write Write X 40H Write WA WD Alternate Word/Byte Write Write X 10H Write WA WD Block Erase/Confirm Write X 20H Write BA D0H Erase Suspend/Resume Write X B0H Write X D0H ADDRESS AA = Array Address BA = Block Address IA = Identifier Address WA = Write Address X = Don't Care DATA AD = Array Data CSRD = CSR Data ID = Identifier Data WD = Write Data NOTES: 1. Following the intelligent identifier command, two Read operations access the manufacturer and device signature codes. 2. The CSR is automatically available after device enters Data Write, Erase, or Suspend operations. 3. Clears CSR.3, CSR.4 and CSR.5. Also clears GSR.5 and all BSR.5 and BSR.2 bits. See Status register definitions. 7-78 16M (1M x 16/2M x 8) Flash Memory LH28F016SA 4.4 LH28F016SA-Performance Enhancement Command Bus Definitions First Bus Cycle Command Mode Second Bus Cycle Third Bus Cycle Notes Oper Addr Data Oper Addr Data Read RA GSRD BSRD Read PA PD Oper Addr Data Read Extended Status Register 1 Write X 71H Page Buffer Swap 7 Write X 72H Read Page Buffer Write X Single Load to Page Buffer Write X 74H Write PA PD Write X E0H Write X BCL Write X BCH x16 4,5,6,10 Write X E0H Write X WCL Write X WCH x8 3,4,9,10 Write X 0CH Write A0 WA BC(H,L) Write WA WCH WD(L,H) Write WA WD(H,L) Sequential Load to Page Buffer Page Buffer Write to Flash x8 4,6,10 75H BC(L,H) Write x16 4,5,10 Write X 0CH Write X x8 3 Write X FBH Write A0 Write X 77H Write BA D0H Write X 97H Write X D0H Write X 99H Write X D0H Write X A7H Write X D0H 8 Write X 96H Write X 01H 8 Write X 96H Write X 02H 8 Write X 96H Write X 03H 8 Write X 96H Write X 04H Sleep Write X F0H Abort Write X 80H Two-Byte Write Lock Block/Confirm Upload Status Bits/Confirm Upload Device Information Erase All Unlocked Blocks/Confirm RY/BY# Enable to Level-Mode RY/BY# Pulse-OnWrite RY/BY# Pulse-OnErase RY/BY# Disable ADDRESS BA = Block Address PA = Page Buffer Address RA = Extended Register Address WA = Write Address X = Don't Care 2 DATA AD = Array Data PD = Page Buffer Data BSRD = BSR Data GSRD = GSR Data WCL WC (L.H) = Word Count (Low, High) BC (L.H) = Byte Count (Low, High) WD (L.H) = Write Data (Low, High) 7-79 16M (1M x 16/2M x 8) Flash Memory LH28F016SA NOTES: 1. RA can be the GSR address or any BSR address. See Figure 4.1 and 4.2 for Extended Status Register Memory Maps. 2. Upon device power-up, all BSR lock-bits come up locked. The Upload Status Bits command must be written to reflect the actual lock-bit status. 3. A0 is automatically complemented to load second byte of data. BYTE# must be at VIL. A0 value determines which WD/BC is supplied first: A0 = 0 looks at the WDL/BCL, A0 = 1 looks at the WDH/BCH. 4. BCH/WCH must be at 00H for this product because of the 256-Byte (128 Word) Page Buffer size and to avoid writing the Page Buffer contents into more than one 256-Byte segment within an array block. They are simply shown for future Page Buffer expandability. 5. In x16 mode, only the lower byte DQ0-7 is used for WCL and WCH. The upper byte DQ8-15 is a don't care. 6. PA and PD (Whose count is given in cycles 2 and 3) are supplied starting in the 4th cycle which is not shown. 7. This command allows the user to swap between available Page Buffers (0 or 1). 8. These commands reconfigure RY/BY# output to one of two pulse-modes or enable and disable the RY/BY# function. 9. Write address, WA, is the Destination address in the flash array which must match the Source address in the Page Buffer. Refer to the LH28F016SA User's Manual. 10. BCL = 00H corresponds to a Byte count of 1. Similarly, WCL = 00H corresponds to a Word count of 1. 4.5 Compatible Status Register WSMS ESS ES DWS VPPS R R R 7 6 5 4 3 2 1 0 NOTES: CSR.7 = WRITE STATE MACHINE STATUS 1 = Ready 0 = Busy RY/BY# output or WSMS bit must be checked to determine completion of an operation (Erase Suspend, Erase or Data Write) before the appropriate Status bit (ESS, ES or DWS) is checked for success. CSR.6 = ERASE-SUSPEND STATUS 1 = Erase Suspended 0 = Erase in Progress/Completed CSR.5 = ERASE STATUS 1 = Error in Block Erasure 0 = Successful Block Erase If DWS and ES are set to "1" during an erase attempt, an improper command sequence was entered. Clear the CSR and attempt the operation again. CSR.4 = DATA-WRITE STATUS 1 = Error in Data Write 0 = Data Write Successful CSR.3 = V PP STATUS 1 = V PP Low Detect, Operation Abort 0 = V PP OK The VPPS bit, unlike an A/D converter, does not provide continuous indication of VPP level. The WSM interrogates VPP's level only after the DataWrite or Erase command sequences have been entered, and informs the system if VPP has not been switched on. VPPS is not guaranteed to report accurate feedback between VPPL and VPPH. CSR.2-0 = RESERVED FOR FUTURE ENHANCEMENTS These bits are reserved for future use: mask them out when polling the CSR. 7-80 16M (1M x 16/2M x 8) Flash Memory LH28F016SA 4.6 Global Status Register WSMS OSS DOS DSS QS PBAS PBS PBSS 7 6 5 4 3 2 1 0 NOTES: GSR.7 = WRITE STATE MACHINE STATUS 1 = Ready 0 = Busy [1] RY/BY# output or WSMS bit must be checked to determine completion of an operation (Block Lock, Suspend, any RY/BY# reconfiguration, Upload Status Bits, Erase or Data Write) before the appropriate Status bit (OSS or DOS) is checked for success. GSR.6 = OPERATION SUSPEND STATUS 1 = Operation Suspended 0 = Operation in Progress/Completed GSR.5 = DEVICE OPERATION STATUS 1 = Operation Unsuccessful 0 = Operation Successful or Currently Running GSR.4 = DEVICE SLEEP STATUS 1 = Device in Sleep 0 = Device Not in Sleep MATRIX 5/4 00 = Operation Successful or Currently Running 01 = Device in Sleep Mode or Pending Sleep 10 = Operation Unsuccessful 11 = Operation Unsuccessful or Aborted If operation currently running, then GSR.7 = 0. If device pending sleep, then GSR.7 = 0. Operation aborted: Unsuccessful due to Abort command. GSR.3 = QUEUE STATUS 1 = Queue Full 0 = Queue Available GSR.2 = PAGE BUFFER AVAILABLE STATUS 1 = One or Two Page Buffers Available 0 = No Page Buffer Available GSR.1 = PAGE BUFFER STATUS 1 = Selected Page Buffer Ready 0 = Selected Page Buffer Busy The device contains two Page Buffers. Selected Page Buffer is currently busy with WSM operation. GSR.0 = PAGE BUFFER SELECT STATUS 1 = Page Buffer 1 Selected 0 = Page Buffer 0 Selected NOTE: 1. When multiple operations are queued, checking BSR.7 only provides indication of completion for that particular block. GSR.7 provides indication when all queued operations are completed. 7-81 16M (1M x 16/2M x 8) Flash Memory LH28F016SA 4.7 Block Status Register BS BLS 7 6 BOS BOAS 5 4 QS 3 VPPS 2 R 1 R 0 NOTES: BSR.7 = BLOCK STATUS 1 = Ready 0 = Busy [1] RY/BY# output or BS bit must be checked to determine completion of an operation (Block Lock, Suspend, Erase or Data Write) before the appropriate Status bits (BOS, BLS) is checked for success. BSR.6 = BLOCK-LOCK STATUS 1 = Block Unlocked for Write/Erase 0 = Block Locked for Write/Erase BSR.5 = BLOCK OPERATION STATUS 1 = Operation Unsuccessful 0 = Operation Successful or Currently Running BSR.4 = BLOCK OPERATION ABORT STATUS 1 = Operation Aborted 0 = Operation Not Aborted MATRIX 5/4 00 = Operation Successful or Currently Running 01 = Not a valid Combination 10 = Operation Unsuccessful 11 = Operation Aborted The BOAS bit will not be set until BSR.7 = 1. Operation halted via Abort command. BSR.3 = QUEUE STATUS 1 = Queue Full 0 = Queue Available BSR.2 = V PP STATUS 1 = V PP Low Detect, Operation Abort 0 = V PP OK NOTES: BSR.1-0 = RESERVED FOR FUTURE ENHANCEMENTS These bits are reserved for future use; mask them out when polling the BSRs. 1. When multiple operations are queued, checking BSR.7 only provides indication of completion for that particular block. GSR.7 provides indication when all queued operations are completed. 7-82 16M (1M x 16/2M x 8) Flash Memory LH28F016SA 5.0 ELECTRICAL SPECIFICATIONS 5.1 Absolute Maximum Ratings * Temperature Under Bias 0C to + 80C Storage Temperature -65C to + 125C * WARNING: Stressing the device beyond the "Absolute Maximum Ratings" may cause permanent damage. These are stress ratings only. Operation beyond the "Operating Conditions" is not recommended and extended exposure beyond the "Operating Conditions" may affect device reliability. V CC = 3.3 V 0.3 V Systems Symbol (5) Parameter Notes Min Max Units TA Operating Temperature, Commercial 1 0 70 C VCC VCC with Respect to GND 2 - 0.2 7.0 V VPP VPP Supply Voltage with Respect to GND 2,3 - 0.2 14.0 V V Voltage on any Pin (except VCC, VPP) with Respect to GND 2 - 0.5 VCC + 0.5 V I Current into any Non-Supply Pin 30 mA IOUT Output Short Circuit Current 100 mA V CC = 5.0 V 0.5 V, VCC = 5.0 V 0.25 V Systems Symbol 4 Test Conditions Ambient Temperature (5,6) Parameter Notes Min Max Units TA Operating Temperature, Commercial 1 0 70 C VCC VCC with Respect to GND 2 - 0.2 7.0 V VPP VPP Supply Voltage with Respect to GND 2,3 - 0.2 14.0 V V Voltage on any Pin (except VCC, VPP) with Respect to GND 2 - 2.0 7.0 V I Current into any Non-Supply Pin 30 mA IOUT Output Short Circuit Current 100 mA 4 Test Conditions Ambient Temperature NOTES: 1. Operating temperature is for commercial product defined by this specification. 2. Minimum DC voltage is - 0.5 V on input/output pins. During transitions, this level may undershoot to - 2.0 V for periods <20 ns. Maximum DC voltage on input/output pins is VCC + 0.5 V which, during transitions, may overshoot to VCC + 2.0 V for periods <20 ns. 3. Maximum DC voltage on VPP may overshoot to + 14.0 V for periods <20 ns. 4. Output shorted for no more than one second. No more than one output shorted at a time. 5. AC specifications are valid at both voltage ranges. See DC Characteristics tables for voltage range-specific specifications. 6. 5% VCC specifications refer to the LH28F016SA-70 in its High Speed Test configuration. 7-83 16M (1M x 16/2M x 8) Flash Memory LH28F016SA 5.2 Capacitance For a 3.3 V System: Symbol Parameter Note Typ Max Units Test Conditions CIN Capacitance Looking into an Address/Control Pin 1 6 8 COUT Capacitance Looking into an Output Pin 1 8 12 pF TA = 25C, f = 1.0 MHz CLOAD Load Capacitance Driven by Outputs for Timing Specifications 1 50 pF For VCC = 3.3V 0.3V 2.5 ns 50 transmission line delay Equivalent Testing Load Circuit pF TA = 25C, f = 1.0 MHz For a 5.0 V System: Symbol Parameter Note Typ Max Units Test Conditions CIN Capacitance Looking into an Address/Control Pin 1 6 8 COUT Capacitance Looking into an Output Pin 1 8 12 pF TA = 25C, f = 1.0 MHz CLOAD Load Capacitance Driven by Outputs for Timing Specifications 1 100 pF For VCC = 5.0V 0.5V 30 pF For VCC = 5.0V 0.25V Equivalent Testing Load Circuit for VCC 10% 2.5 ns 25 transmission line delay Equivalent Testing Load Circuit for VCC 5% 2.5 ns 83 transmission line delay NOTE: 1. Sampled, not 100% tested. 7-84 pF TA = 25C, f = 1.0 MHz 16M (1M x 16/2M x 8) Flash Memory LH28F016SA 5.3 Timing Nomenclature All 3.3 V system timings are measured from where signals cross 1.5 V. For 5.0 V systems use the standard JEDEC cross point definitions. Each timing parameter consists of 5 characters. Some common examples are defined below: tCE tOE tACC tAS tDH tELQV time(t) from CE# (E) going low (L) to the outputs (Q) becoming valid (V) tGLQV time(t) from OE# (G) going low (L) to the outputs (Q) becoming valid (V) tAVQV time(t) from address (A) valid (V) to the outputs (Q) becoming valid (V) tAVWH time(t) from address (A) valid (V) to WE# (W) going high (H) tWHDX time(t) from WE# (W) going high (H) to when the data (D) can become undefined (X) Pin Characters Pin States A Address Inputs H High D Data Inputs L Low Q Data Outputs V Valid E CE# (Chip Enable) X Driven, but not necessarily valid G OE# (Output Enable) Z High Impedance W WE# (Write Enable) P RP# (Deep Power-Down Pin) R RY/BY# (Ready Busy) V Any Voltage Level Y 3/5# Pin 5V VCC at 4.5V Minimum 3V VCC at 3.0V Minimum 2.4 2.0 INPUT 2.0 TEST POINTS OUTPUT 0.8 0.45 0.8 Figure 5. Transient Input/Output Reference Waveform (VCC = 5.0 V) for Standard Test Configuration (1) AC test inputs are driven at VOH (2.4 VTTL) for a Logic "1" and VOL (0.45 VTTL) for a Logic "0." Input timing begins at VIH (2.0 VTTL) and VIL (0.8 VTTL). Output timing ends at VIH and VIL. Input rise and fall times (10% to 90%) <10 ns. 3.0 INPUT 1.5 TEST POINTS 1.5 OUTPUT 0.0 Figure 6. Transient Input/Output Reference Waveform (VCC = 3.3 V) High Speed Reference Waveform (2) (VCC = 5.0 V 5%) AC test inputs are driven at 3.0 V for a Logic "1" and 0.00 V for a Logic "0." Input timing begins, and output timing ends, at 1.5 V. Input rise and fall times (10% to 90%) <10 ns. NOTES: 1. Testing characteristics for LH28F016SA-080/LH28F016SA-100. 2. Testing characteristics for LH28F016SA-070/LH28F016SA-120/LH28F016SA-150. 7-85 16M (1M x 16/2M x 8) Flash Memory LH28F016SA 2.5 ns of 25 Transmission Line From Output Test Under Test Point Total Capacitance = 100 pF Figure 7. Transient Equivalent Testing Load Circuit (V CC = 5.0 V) 2.5 ns of 50 Transmission Line From Output Test Under Test Point Total Capacitance = 50 pF Figure 8. Transient Equivalent Testing Load Circuit (V CC = 3.3 V) 2.5 ns of 83 Transmission Line From Output Test Under Test Point Total Capacitance = 30 pF Figure 9. High Speed Transient Equivalent Testing Load Circuit (VCC = 5.0 V 5%) 7-86 16M (1M x 16/2M x 8) Flash Memory LH28F016SA 5.4 DC Characteristics V CC = 3.3 V 0.3 V, TA = 0C to + 70C 3/5# = Pin Set High for 3.3 V Operations Symbol Parameter Notes Min Typ Max Units IIL Input Load Current 1 1 A ILO Output Leakage Current 1 10 A ICCS VCC Standby Current 50 100 A 1 4 ICCD VCC Deep Power-Down Current ICCR1 1,5 mA Test Conditions VCC = VCC Max, VIN = VCC or GND V CC = VCC Max, VIN = VCC or GND VCC = VCC Max, CE0#, CE1#, RP# = VCC 0.2V BYTE#, WP#, 3/5# = VCC 0.2V or GND 0.2V VCC = VCC Max, CE0#, CE1#, RP# = VIH BYTE#, WP#, 3/5# = VIH or VIL 1 1 5 A RP# = GND 0.2V V CC Read Current 1,4,5 30 35 mA VCC = VCC Max, CMOS: CE0#, CE1# = GND 0.2V BYTE# = GND 0.2V or VCC 0.2V Inputs = GND 0.2V or VCC 0.2V, TTL: CE0#, CE1# = VIL, BYTE# = VIL or VIH Inputs = VIL or VIH, f = 8 MHz, IOUT = 0 mA ICCR2 V CC Read Current 1,4,5 15 20 mA VCC = VCC Max, CMOS: CE0#, CE1# = GND 0.2V, BYTE# = VCC 0.2V or GND 0.2V Inputs = GND 0.2V or VCC 0.2V, TTL: CE0#, CE1# = VIL BYTE# = VIH or VIL Inputs = VIL or VIH, f = 4 MHz, IOUT = 0 mA ICCW VCC Write Current 1 8 12 mA ICCE VCC Block Erase Current 1 6 12 mA Block Erase in Progress ICCES VCC Erase Suspend Current 1,2 3 6 mA CE0#, CE1# =VIH Block Erase Suspended IPPS VPP Standby Current 1 1 10 A VPP < VCC IPPD VPP Deep Power-Down Current 1 0.2 5 A RP# = GND 0.2V Word/Byte Write in Progress 7-87 16M (1M x 16/2M x 8) Flash Memory LH28F016SA 5.4 DC Characteristics (Continued) V CC = 3.3 V 0.3 V, TA = 0C to + 70C 3/5# = Pin Set High for 3.3 V Operations Symbol Parameter Notes IPPR VPP Read Current 1 IPPW VPP Write Current 1 IPPE VPP Erase Current 1 IPPES VPP Erase Suspend Current 1 VIL Input Low Voltage VIH Input High Voltage VOL Output Low Voltage VOH1 Output High Voltage Min Typ Max A 10 15 mA 4 10 mA VPP = VPPH, Block Erase in Progress 200 A V PP = VPPH, Block Erase Suspended - 0.3 0.8 V 2.0 VCC + 0.3 V 0.4 V VPPL VPP during Normal Operations VPPH VPP during Write/ Erase Operations 11.4 VLKO VCC Erase/Write Lock Voltage 2.0 VPP > VCC V PP = VPPH, Word/Byte Write in Progress V CC = VCC Min and IOL = 4 mA IOH = - 2.0 mA VCC = VCC Min V V CC - 0.2 3 Test Conditions 200 2.4 VOH2 Units IOH = - 100 A VCC = VCC Min 0.0 6.5 12.0 12.6 V V V NOTES: 1. All currents are in RMS unless otherwise noted. Typical values at VCC = 3.3 V, VPP = 12.0 V, T = 25C. These currents are valid for all product versions (package and speeds). 2. I CCES is specified with the device de-selected. If the device is read while in erase suspend mode, current draw is the sum of ICCES and I CCR. 3. Block Erases, Word/Byte Writes, and Lock Block operations are inhibited when VPP = VPPL and not guaranteed in the range between VPPH and VPPL. 4. Automatic Power Saving (APS) reduces ICCR to less than 1 mA in static operation. 5. CMOS Inputs are either VCC 0.2 V or GND 0.2 V. TTL Inputs are either VIL or VIH. 7-88 16M (1M x 16/2M x 8) Flash Memory LH28F016SA 5.5 DC Characteristics V CC = 5.0 V 0.5 V, TA = 0C to + 70C 3/5# Pin Set Low for 5 V Operations Symbol Parameter Notes Min Typ Max Units IIL Input Load Current 1 1 A ILO Output Leakage Current 1 10 A ICCS VCC Standby Current 50 100 A 2 4 ICCD VCC Deep Power-Down Current ICCR1 1,5 mA Test Conditions VCC = VCC Max VIN = VCC or GND V = VCC Max VIN = VCC or GND CC VCC = VCC Max CE0#, CE1#, RP# = VCC 0.2V BYTE#, WP#, 3/5# = VCC 0.2V or GND 0.2V VCC = VCC Max CE0#, CE1#, RP# = VIH BYTE#, WP#, 3/5# = VIH or VIL 1 1 5 A V CC Read Current 1,4,5 50 60 mA VCC = VCC Max, CMOS: CE0#, CE1# = GND 0.2V BYTE# = GND 0.2V or VCC 0.2V Inputs = GND 0.2V or VCC 0.2V, TTL: CE0#, CE1# = VIL, BYTE# = VIL or VIH Inputs = VIL or VIH, f = 10 MHz, IOUT = 0 mA ICCR2 V CC Read Current 1,4,5 30 35 mA VCC = VCC Max, CMOS: CE0#, CE1# = GND 0.2V BYTE# = VCC 0.2V or GND 0.2V Inputs = GND 0.2V or VCC 0.2V TTL: CE0#, CE1# = VIL, BYTE# = VIH or VIL, Inputs = VIL or VIH, f = 5 MHz, IOUT = 0 mA ICCW VCC Write Current 1 25 35 mA ICCE VCC Block Erase Current 1 18 25 mA Block Erase in Progress ICCES VCC Erase Suspend Current 1,2 5 10 mA CE0#, CE1# =VIH Block Erase Suspended IPPS VPP Standby Current 10 A VPP < VCC 1 RP# = GND 0.2V Word/Byte in Progress 7-89 16M (1M x 16/2M x 8) Flash Memory LH28F016SA 5.5 DC Characteristics (Continued) V CC = 5.0 V 0.5 V, TA = 0C to + 70C 3/5# Pin Set Low for 5 V Operations Symbol Parameter Notes Min Typ Max Units Test Conditions IPPD VPP Deep PowerDown Current 1 0.2 5 A RP# = GND 0.2V IPPR VPP Read Current 1 65 200 A VPP > VCC IPPW VPP Write Current 1 7 12 mA IPPE VPP Block Erase Current 1 5 10 mA VPP = VPPH Block Erase in Progress IPPES VPP Erase Suspend Current 1 65 200 A V PP = VPPH Block Erase Suspended VIL Input Low Voltage - 0.5 0.8 V VIH Input High Voltage 2.0 VCC + 0.5 V VOL Output Low Voltage 0.45 V V CC = VCC Min IOL = 5.8 mA VOH1 Output High Voltage V IOH = - 2.5 mA VCC = VCC Min 0.85 VCC VOH2 V CC - 0.4 VPPL VPP during Normal Operations 3 VPPH VPP during Erase/ Write Operations 11.4 VLKO VCC Erase/Write Lock Voltage 2.0 V PP = VPPH Word/Byte Write in Progress IOH = - 100 A VCC = VCC Min 0.0 6.5 12.0 12.6 V V V NOTES: 1. All currents are in RMS unless otherwise noted. Typical values at VCC = 5.0 V, VPP = 12.0 V, T = 25C. These currents are valid for all product versions (package and speeds). 2. I CCES is specified with the device deselected. If the device is read while in erase suspend mode, current draw is the sum of ICCES and ICCR. 3. Block Erases, Word/Byte Writes, and Lock Block operations are inhibited when VPP = VPPL and not guaranteed in the range between VPPH and VPPL. 4. Automatic Power Saving (APS) reduces ICCR to less than 2 mA in Static operation. 5. CMOS Inputs are either VCC 0.2 V or GND 0.2 V. TTL Inputs are either VIL or VIH. 7-90 16M (1M x 16/2M x 8) Flash Memory LH28F016SA 5.6 AC Characteristics - Read Only Operations (1) V CC = 3.3 V 0.3 V, TA = 0C to +70C Versions(5) Symbol Parameter LH28F016SA-120 Notes Min Max LH28F016SA-150 Min Max Units tAVAV Read Cycle Time 120 150 tAVEL Address Setup to CE# Going Low 3,4 10 10 ns tAVGL Address Setup to OE# Going Low 3,4 0 0 ns tAVQV Address to Output Delay tELQV CE# to Output Delay tPHQV RP# High to Output Delay tGLQV OE# to Output Delay 2 tELQX CE# to Output in Low Z 3 tEHQZ CE# to Output in High Z 3 tGLQX OE# to Output in Low Z 3 tGHQZ OE# to Output in High Z 3 tOH Output Hold from Address, CE# or OE# Change, Whichever Occurs First 3 tFLQV tFHQV BYTE# to Output Delay 3 120 150 ns tFLQZ BYTE# Low to Output in High Z 3 30 40 ns tELFL tELFH CE# Low to BYTE# High or Low 3 5 5 ns 2 ns 120 150 ns 120 150 ns 620 750 ns 45 50 ns ns 0 0 55 50 ns 0 0 40 30 ns ns 0 0 ns 7-91 16M (1M x 16/2M x 8) Flash Memory LH28F016SA 5.6 AC Characteristics - Read Only Operations (1) (Continued) V CC = 5.0 V 0.5 V, TA = 0C to +70C VCC 5% LH28F016SA-070(6) LH28F016SA-080(7) LH28F016SA-100(6) Units VCC 10% Symbol Parameter Notes Max Min Max Min Max Min tAVAV Read Cycle Time 70 ns 80 100 Address Setup 10 ns tAVEL 3,4 10 10 to CE# Going Low Versions(5) tAVGL Address Setup to OE# Going Low tAVQV Address to Output Delay tELQV CE# to Output Delay tPHQV RP# to Output Delay tGLQV OE# to Output Delay 2 tELQX CE# to Output in Low Z 3 tEHQZ CE# to Output in High Z 3 tGLQX OE# to Output in Low Z 3 tGHQZ OE# to Output in High Z 3 tOH Output Hold from Address, CE# or OE# Change, Whichever Occurs First BYTE# to Output Delay 3 3 70 80 100 ns tFLQZ BYTE# Low to Output in High Z 3 25 30 30 ns tELFL tELFH CE# Low to BYTE# High or Low 3 5 5 5 ns tELQV tFHQV 3,4 0 2 0 0 ns 70 80 100 ns 70 80 100 ns 400 480 550 ns 30 35 40 ns NOTES: 1. See AC Input/Output Reference Waveforms for timing measurements, Figures 5 and 6. 2. OE# may be delayed up to tELQV - t GLQV after the falling edge of CE# without impact on tELQV. 3. Sampled, not 100% tested. 4. This timing parameter is used to latch the correct BSR data onto the outputs. 5. Device Speeds are defined as: 70/80 ns at VCC = 5.0 V equivalent to 120 ns at VCC = 3.3 V 100 ns at VCC = 5.0 V equivalent to 150 ns at VCC = 3.3 V 6. See AC Input/Output Reference Waveforms and AC Testing Load Circuits for High Speed Test Configuration. 7. See Standard AC Input/Output Reference Waveforms and AC Testing Load Circuit. 7-92 ns ns 0 0 0 35 30 25 ns ns 0 0 0 35 30 25 ns 0 0 0 16M (1M x 16/2M x 8) Flash Memory VIH LH28F016SA OUTPUTS ENABLED DEVICE AND VCC POWER-UP STANDBY ADDRESS SELECTION STANDBY DATA VALID V CC POWER-DOWN ADDRESSES STABLE ADDRESSES (A) VIL tAVAV VIH CEx# (E) (1) VIL tAVEL tEHQZ VIH OE# (G) tAVGL VIL tGHQZ VIH WE# (W) tGLQV VIL tELQV tGLQX tELQX VOH DATA (D/Q) HIGH Z tOH VALID OUTPUT HIGH Z VOL tAVQV 5.0 V VCC GND tPHQV VIH RP# (P) VIL NOTE: CEX# is defined as the latter of CE0# or CE1# going Low or the first of CE0# or CE1# going High. Figure 10. Read Timing Waveforms 7-93 16M (1M x 16/2M x 8) Flash Memory LH28F016SA VIH ADDRESSES (A) ADDRESSES STABLE VIL tAVAV CEx# (E)(1) VIH VIL tAVFL = tELFL tEHQZ VIH OE# (G) tAVEL VIL tGHQZ tELFL tAVGL VIH BYTE# (F) tFLQV = tAVQV tGLQV VIL tELQV tGLQX tELQX VOH DATA (DQ0 - DQ7) tOH HIGH Z DATA OUTPUT VOL DATA OUTPUT tAVQV tFLQZ DATA (DQ8 - DQ15) VOH VOL HIGH Z DATA OUTPUT NOTE: CEX# is defined as the latter of CE0# or CE1# going Low or the first of CE0# or CE1# going High. Figure 11. BYTE# Timing Waveforms 7-94 HIGH Z HIGH Z 16M (1M x 16/2M x 8) Flash Memory LH28F016SA 5.7 Power-Up and Reset Timings VCC POWER UP RP# (P) tYHPH tYLPH 3/5# (Y) tPLYL 5.0V 4.5V 3.3V VCC 0V (3V, 5V) tPL5V Address VALID VALID (A) tAVQV tAVQV Data VALID 3.3V OUTPUTS (Q) VALID 5.0V OUTPUTS tPHQV tPHQV Figure 12. V CC Power-Up and RP# Reset Waveforms Symbol Parameter Min Max 0 Unit s 1 2 s RP# Low to VCC at 4.5V Minimum (to VCC at 3.0V min or 3.6V max) 2 0 s tAVQV Address Valid to Data Valid for VCC = 5V 10% 3 80 ns tPHQV RP# High to Data Valid for VCC = 5V 10% 3 480 ns tPLYL tPLYH RP# Low to 3/5 # Low (High) tYLPH tYHPH 3/5# Low (High) to RP # High tPL5V tPL3V Note NOTES: CE0#, CE1#, and OE# are switched low after Power-Up. 1. Minimum of 2 s is required to meet the specified tPHQV times. 2. The power supply may start to switch concurrently with RP# going Low. 3. The address access time and RP# high to data valid time are shown for 5 V VCC operation. Refer to the AC Characteristics Read Only Operations 3.3 V VCC operation and all other speed options. 7-95 16M (1M x 16/2M x 8) Flash Memory LH28F016SA 5.8 AC Characteristics for WE# - Controlled Command Write Operations (1) V CC = 3.3 V 0.3 V, TA = 0C to + 70C Versions Symbol Parameter tAVAV Write Cycle Time tVPWH VPP Setup to WE# Going High tPHEL LH28F016SA-120 Notes Min Typ Max LH28F016SA-150 Min Typ Max Unit 120 150 ns 100 100 ns RP# Setup to CE# Going Low 480 480 ns tELWL CE# Setup to WE# Going Low 10 10 ns tAVWH Address Setup to WE# Going High 2,6 75 75 ns tDVWH Data Setup to WE# Going High 2,6 75 75 ns tWLWH WE# Pulse Width 75 75 ns tWHDX Data Hold from WE# High 2 10 10 ns tWHAX Address Hold from WE# High 2 10 10 ns tWHEH CE# Hold from WE# High 10 10 ns tWHEL WE# Pulse Width High 45 75 ns tGHWL Read Recovery before Write 0 0 ns tWHRL WE# High to RY/BY# Going Low tRHPL RP# Hold from Valid Status Register (CSR, GSR, BSR) Data and RY/BY# High tPHWL 3 100 100 ns 0 0 ns RP# High Recovery to WE# Going Low 1 1 s tWHGL Write Recovery before Read 95 120 ns tQVVL VPP Hold from Valid Status Register (CSR, GSR, BSR) Data and RY/BY# High 0 0 s tWHQV1 Duration of Word/Byte Write Operation tWHQV2 Duration of Block Erase Operation 7-96 3 4,5 5 4 0.3 9 5 0.3 9 s s 16M (1M x 16/2M x 8) Flash Memory LH28F016SA AC Characteristics for WE# - Controlled Command Write Operations (1) (Continued) V CC = 5.0 0.5 V, TA = 0C to + 70C Versions VCC 5% LH28F016SA-070 LH28F016SA-080 LH28F016SA-100 Unit VCC 10% Symbol Parameter Notes Min Typ Max Min Typ Max Min Typ Max 70 80 100 ns 100 100 100 ns 480 480 480 ns 0 0 0 ns 2,6 50 50 50 ns 2,6 50 50 50 ns 40 50 50 ns 2 0 0 0 ns 2 10 10 10 ns CE# Hold from WE# High 10 10 10 ns tWHWL WE# Pulse Width High 30 30 50 ns tGHWL Read Recovery before Write 0 0 0 ns tWHRL WE# High to RY/BY# Going Low tRHPL RP# Hold from Valid Status Register (CSR, GSR, BSR) Data and RY/BY# High tPHWL tAVAV Write Cycle Time tVPWH VPP Setup to WE# Going High tPHEL RP# Setup to CE# Going Low tELWL CE# Setup to WE# Going Low tAVWH Address Setup to WE# Going High tDVWH Data Setup to WE# Going High tWLWH WE# Pulse Width tWHDX Data Hold from WE# High tWHAX Address Hold from WE# High tWHEH 3 100 100 100 ns 0 0 0 ns RP# High Recovery to WE# Going Low 1 1 1 s tWHGL Write Recovery before Read 60 65 80 ns tQVVL VPP Hold from Valid Status Register (CSR, GSR, BSR) Data and RY/BY# High 0 0 0 s tWHQV1 Duration of Word/Byte Write Operation tWHQV2 Duration of Block Erase Operation 3 4,5 4.5 4 0.3 6 4.5 6 0.3 4.5 0.3 6 s s NOTES: CE# is defined as the latter of CE0# or CE1# going Low or the first of CE0# or CE1# going High. 1. Read timing during write and erase are the same as for normal read. 2. Refer to command definition tables for valid address and data values. 3. Sampled, but not 100% tested. 4. Write/Erase durations are measured to valid Status Register (CSR) Data. 5. Word/Byte write operations are typically performed with 1 Programming Pulse. 6. Address and Data are latched on the rising edge of WE# for all Command Write operations. 7-97 16M (1M x 16/2M x 8) Flash Memory LH28F016SA WRITE VALID ADDRESS DEEP WRITE DATA-WRITE OR & DATA (DATA-WRITE) OR AUTOMATED DATA-WRITE WRITE READ EXTENDED POWER-DOWN ERASE SETUP COMMAND ERASE CONFIRM COMMAND OR ERASE DELAY REGISTER COMMAND VIH ADDRESSES (A) NOTE 1 AIN VIL A=RA tAVAV tWHAX tAVWH READ COMPATIBLE STATUS REGISTER DATA VIH ADDRESSES (A) NOTE 2 READ EXTENDED STATUS REGISTER DATA NOTE 3 A=RA AIN VIL tAVAV tWHAX tAVWH VIH CEx# (E) NOTE 4 VIL tELWL tWHEH tWHGL VIH OE# (G) VIL tWHQV 1, 2 tWHWL tGHWL VIH WE# (W) VIL VIH tWLWH tDVWH HIGH Z DATA (D/Q) VIL tWHDX DIN DIN DIN DOUT DIN tPHWL tWHRL VOH RY/BY# (R) VOL tRHPL VIH NOTE 5 RP# (P) VIL tVPWH VPPH VPP (V) VPPL VIH VIL Figure 13. AC Waveforms for Command Write Operations NOTES: 1. This address string depicts Data-Write/Erase cycles with corresponding verification via ESRD. 2. This address string depicts Data-Write/Erase cycles with corresponding verification via CSRD. 3. This cycle is invalid when using CSRD for verification during Data-Write/Erase operations. 4. CEX# is defined as the latter of CE0# or CE1# going Low or the first of CE0# or CE1# going High. 5. RP# low transition is only to show t RHPL; not valid for above Read and Write cycles. 7-98 tQVVL 16M (1M x 16/2M x 8) Flash Memory LH28F016SA 5.9 AC Characteristics for CE# - Controlled Command Write Operations (1) V CC = 3.3 V 0.3 V, TA = 0C to 70C Versions Symbol Parameter LH28F016SA-120 Notes Min Typ Max LH28F016SA-150 Min Typ Max Unit tAVAV Write Cycle Time 120 150 ns tPHWL RP# Setup to WE# Going Low 480 480 ns tVPEH VPP Setup to CE# Going High 100 100 ns tWLEL WE# Setup to CE# Going Low 0 0 ns tAVEH Address Setup to CE# Going High 2,6 75 75 ns tDVEH Data Setup to CE# Going High 2,6 75 75 ns tELEH CE# Pulse Width 75 75 ns tEHDX Data Hold from CE# High 2 10 10 ns tEHAX Address Hold from CE# High 2 10 10 ns tEHWH WE# Hold from CE# High 10 10 ns tEHEL CE# Pulse Width High 45 75 ns tGHEL Read Recovery before Write 0 0 ns tEHRL CE# High to RY/BY# Going Low 0 tRHPL RP# Hold from Valid Status Register (CSR, GSR, BSR) Data and RY/BY# High tPHEL 3 100 100 ns 0 0 ns RP# High Recovery to CE# Going Low 1 1 s tEHGL Write Recovery before Read 95 120 ns tQVVL VPP Hold from Valid Status Register (CSR, GSR, BSR) Data and RY/BY# High 0 0 s tEHQV1 Duration of Word/Byte Write Operation tEHQV2 Duration of Block Erase Operation 3 4,5 5 4 0.3 9 5 0.3 9 s s 7-99 16M (1M x 16/2M x 8) Flash Memory LH28F016SA AC Characteristics for CE# - Controlled Command Write Operations (1) (Continued) V CC = 5.0 V 0.5 V, TA = 0C to 70C Versions VCC 5% LH28F016SA-070 LH28F016SA-080 LH28F016SA-100 Unit VCC 10% Symbol Parameter Notes Min Typ Max Min Typ Min Typ Max 70 80 100 ns 3 480 480 480 ns 3 100 100 100 ns 0 0 0 ns 2,6 50 50 50 ns 2,6 50 50 50 ns 40 50 50 ns 2 0 0 0 ns 2 10 10 10 ns WE# Hold from CE# High 10 10 10 ns tEHEL CE# Pulse Width High 30 30 50 ns tGHEL Read Recovery before Write 0 0 0 ns tEHRL CE# High to RY/BY# Going Low tRHPL RP# Hold from Valid Status Register (CSR, GSR, BSR) Data and RY/BY# High tPHEL tAVAV Write Cycle Time tPHWL RP# Setup to WE# Going Low tVPEH VPP Setup to CE# Going High tWLEL WE# Setup to CE# Going Low tAVEH Address Setup to CE# Going High tDVEH Data Setup to CE# Going High tELEH CE# Pulse Width tEHDX Data Hold from CE# High tEHAX Address Hold from CE# High tEHWH 100 100 100 ns 0 0 0 ns RP# High Recovery to CE# Going Low 1 1 1 s tEHGL Write Recovery before Read 60 65 80 ns tQVVL VPP Hold from Valid Status Register (CSR, GSR, BSR) Data and RY/BY# High 0 0 0 s tEHQV1 Duration of Word/Byte Write Operation tEHQV2 Duration of Block Erase Operation 3 4,5 4.5 4 0.3 6 4.5 6 0.3 NOTES: CE# is defined as the latter of CE0# or CE1# going Low or the first of CE0# or CE1# going High. 1. Read timing during write and erase are the same as for normal read. 2. Refer to command definition tables for valid address and data values. 3. Sampled, but not 100% tested. 4. Write/Erase durations are measured to valid Status Data. 5. Word/Byte write operations are typically performed with 1 Programming Pulse. 6. Address and Data are latched on the rising edge of CE# for all Command Write Operations. 7-100 Max 4.5 0.3 6 s s 16M (1M x 16/2M x 8) Flash Memory DEEP WRITE DATA-WRITE OR POWER-DOWN ERASE SETUP COMMAND VIH LH28F016SA WRITE VALID ADDRESS AUTOMATED DATA-WRITE WRITE READ EXTENDED & DATA (DATA-WRITE) OR OR ERASE DELAY REGISTER COMMAND ERASE CONFIRM COMMAND ADDRESSES (A) NOTE 1 AIN VIL A=RA tAVAV tEHAX tAVEH READ COMPATIBLE STATUS REGISTER DATA VIH ADDRESSES (A) NOTE 2 READ EXTENDED STATUS REGISTER DATA NOTE 3 AIN VIL tAVAV tEHAX tAVEH VIH WE# (W) VIL tWLEL tEHWH tEHGL VIH OE# (G) VIL tEHQV 1, 2 tEHEL tGHEL VIH CEx# (E) NOTE 4 VIL tELEH VIH HIGH Z DATA (D/Q) VIL tEHDX tDVEH DIN DIN DIN DOUT DIN tPHEL tEHRL VOH RY/BY# (R) VOL tRHPL VIH NOTE 5 RP# (P) VIL tVPEH tQVVL VPPH VPP (V) VPPL VIH VIL Figure 14. Alternate AC Waveforms for Command Write Operations NOTES: 1. This address string depicts Data-Write/Erase cycles with corresponding verification via ESRD. 2. This address string depicts Data-Write/Erase cycles with corresponding verification via CSRD. 3. This cycle is invalid when using CSRD for verification during Data-Write/Erase operations. 4. CEX# is defined as the latter of CE0# or CE1# going Low or the first of CE0# or CE1# going High. 5. RP# low transition is only to show t RHPL; not valid for above Read and Write cycles. 7-101 16M (1M x 16/2M x 8) Flash Memory LH28F016SA 5.10 AC Characteristics for Page Buffer Write Operations (1) V CC = 3.3 V 0.3 V, TA = 0C to + 70C Versions Symbol LH28F016SA-120 Parameter Notes Min Typ Max LH28F016SA-150 Min Typ Max Unit tAVAV Write Cycle Time 120 150 ns tELWL CE# Setup to WE# Going Low 10 10 ns tAVWL Address Setup to WE# Going Low 3 0 0 ns tDVWH Data Setup to WE# Going High 2 75 50 ns tWLWH WE# Pulse Width 75 75 ns tWHDX Data Hold from WE# High 2 10 10 ns tWHAX Address Hold from WE# High 2 10 10 ns tWHEH CE# Hold from WE# High 10 10 ns tWHWL WE# Pulse Width High 45 75 ns tGHWL Read Recovery before Write 0 0 ns tWHGL Write Recovery before Read 95 120 ns V CC = 5.0 V 0.5 V, TA = 0C to + 70C Versions Symbol Parameter Notes LH28F016SA-070 LH28F016SA-080 LH28F016SA-100 Min Min Min Typ Max Typ Max Max Unit tAVAV Write Cycle Time 70 80 100 ns tELWL CE# Setup to WE# Going Low 0 0 0 ns tAVWL Address Setup to WE# Going Low 3 0 0 0 ns tDVWH Data Setup to WE# Going High 2 50 50 50 ns tWLWH WE# Pulse Width 40 50 50 ns tWHDX Data Hold from WE# High 2 0 0 0 ns tWHAX Address Hold from WE# High 2 10 10 10 ns tWHEH CE# Hold from WE# High 10 10 10 ns tWHWL WE# Pulse Width High 30 30 50 ns tGHWL Read Recovery before Write 0 0 0 ns tWHGL Write Recovery before Read 60 65 80 ns NOTES: CE# is defined as the latter of CE0# or CE1# going Low or the first of CE0# or CE1# going High. 1. These are WE#-controlled write timings, equivalent CE#-controlled write timings apply. 2. Sampled, but not 100% tested. 3. Address must be valid during the entire WE# Low pulse. 7-102 Typ 16M (1M x 16/2M x 8) Flash Memory LH28F016SA CEx# (E) tWHEH tELWL WE# (W) tWHWL tAVWL tWLWH tWHAX ADDRESSES VALID tDVWH DATA (D/Q) HIGH Z tWHDX DIN Figure 15. Page Buffer Write Timing Waveforms 7-103 16M (1M x 16/2M x 8) Flash Memory LH28F016SA 5.11 Erase and Word/Byte Write Performance (3) V CC = 3.3 V 0.3 V, TA = 0C to + 70C Symbol Parameter Notes Min Typ(1) Max Units Test Conditions tWHRH1 Word/Byte Write Time 2 9 s tWHRH2 Block Write Time 2 0.6 2.1 s Byte Write Mode tWHRH3 Block Write Time 2 0.3 1.0 s Word Write Mode Block Erase Time 2 0.8 10 s Full Chip Erase Time 2 25.6 s V CC = 5.0 V 0.5 V, TA = 0C to + 70C Symbol Parameter Notes Min Typ(1) Max Units Test Conditions tWHRH1 Word/Byte Write Time 2 6 tWHRH2 Block Write Time 2 0.4 2.1 s Byte Write Mode tWHRH3 Block Write Time 2 0.2 1.0 s Word Write Mode Block Erase Time 2 0.6 10 s Full Chip Erase Time 2 19.2 NOTES: 1. 25C, VPP = 12.0 V. 2. Excludes System-Level Overhead. 3. These performance numbers are valid for all speed versions. 7-104 s s 16M (1M x 16/2M x 8) Flash Memory LH28F016SA PACKAGE DIAGRAM 56 28 29 0.125 +0.05 -0.05 1.19 MAX. +0.1 0.995 -0.1 +0.05 0.125 0.435 -0.05 +0.2 18.4 -0.2 +0.1 +0.3 20.0 -0.3 0.115 -0.1 40-0.2 -0.08 +0.08 0.08 M 14.0 -0.2 +0.2 0.10 P-0.5TYP. 1 PACKAGE BASE PLANE +0.3 19.0 -0.3 56-Lead TSOP (Type I) ORDERING INFORMATION LH28F016SA Device Type T Package -## Speed 70 ns, 5 V Read 100 ns, 5 V Read 120 ns, 3.3 V Read 150 ns, 3.3 V Read 56-pin TSOP (Type I) 16M Dual Volt (5/12) Flash Memory Example: LH28F016SAT-70 (16M Dual Volt (5/12) Flash Memory, 70 ns, 56-pin TSOP (Type I)) FLASH-2 7-105