1
Features
•Serial Peripheral Interface (SPI) Compatib le
•Supports SPI Modes 0 (0,0) and 3 (1,1)
•128-byte Page Mode Only for Write Operations
•Low-voltage and Standard-voltage Operation
– 2.7 (VCC = 2.7V to 5.5V)
– 1.8 (VCC = 1.8V to 5.5V)
•10 MHz (5V), 5MHz (2.7 V) and 2 MHz (1.8 V) Cloc k Rate
•Block Write Pr otection
•Protect 1/4 , 1/2, or Entire Array
•Write Protect (WP) Pin and Write Disable Instructions for
both Hardware and Software Data Protection
•High Reliability
– Enduranc e: 100K Write Cycles
– Data Retention: >40 Years
•8-l ead PDIP, 8-lead EIAJ SOIC, 16- lead JEDEC SOIC and 8-lead Leadl ess Arr ay Pa c kage
Description
The AT25HP2 56/512 provides 262,144/524, 288 bits of serial electrically erasable pro-
grammabl e read only memory (EEPROM) organized as 32,768/65,536 words of 8-bits
each. The d evice is opt imized for use in many indust rial and comm ercial applica tions
where high-speed, low-power, and low-voltage operation are essential. The
AT25HP256 /512 is available i n a sp ace s aving 8-lea d PD IP (AT25HP 256/512), 8-le ad
EIAJ SOIC (AT25HP256), 16-lead JEDEC SOIC (AT25HP512) and 8-lead Leadless
Rev. 1113I–SEEPR–6/03
SPI Serial
EEPROMs
256K (32,768 x 8)
512K (65,536 x 8)
AT25HP256
AT25HP512
Pin Configurations
Pin Name Function
CS Chip Select
SC K Se r ia l D a ta Clock
SI Serial Data Input
SO Serial Data Output
GND Ground
VCC Power Supply
WP Write Protect
HOLD Suspends Serial Input
8-lead SOIC
CS
SCK
SO
WP HOLD
GND
VCC
1
2
3
4
8
7
6
5SI
8-l ead PDIP
CS
SCK
SO
WP HOLD
GND
VCC
1
2
3
4
8
7
6
5SI
8-lead Leadles s Arr ay
Bottom View
1
2
3
4
8
7
6
5
VCC
HOLD
SCK
SI
CS
SO
WP
GND
16-lead SOIC
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
CS
SO
NC
NC
NC
NC
WP
GND
VCC
HOLD
NC
NC
NC
NC
SCK
SI
2AT25HP256/512 1113I–SEEPR–6/03
Array (AT25 HP256/512) packages. In addition, the entire family is availa ble in 2.7V (2.7V to 5 .5V) and 1.8 V (1.8V to 5 .5V)
versions.
The AT25HP 256/512 is ena bled throu gh the Chip Sel ect pin (CS) and acc essed via a 3-wire interface consisting of Se rial
Data Input (SI), Serial Data Output (SO), and Serial Cloc k (SCK). All programming cycles are completely self-timed, and no
separate ERASE cycle is required before WRITE.
BLOCK WR ITE protection i s enabled by program ming the status register with t op ¼, top ½ or entire array of w rite protec-
tion. Separate program enable and progra m disable instruct ions are provided for addi tional data prot ection. Hardware data
protection is provided via the WP pin to protect against inadvertent write attempts to the status register. The HOLD pin may
be used to suspend any serial communication without resetting the ser ial sequence.
Figu re 1. Block Diagram
Absolute Maximum Ratings*
Operating Temperature.................................. -55°C to +125°C*NO TICE: Stresses beyond those listed under “Absol ute Max i-
mum Ratings” ma y cause permane nt damage to the
device. This is a stress rating only and functional
operation of the device at these or any other condi-
tions beyond those indicated in the operational sec-
tions of thi s specification is not implied. Exposure to
absolute maximum rating cond itions for e xtended
periods may affect devic e rel iability.
Storage Temperature... ...... ....... .. ....... ...... ...... -65°C to +15 0°C
Volt age on Any Pin
wit h R e spe ct to Gr o und ............. .......... .......... ....-1.0V to +7.0 V
Maximum Operating Voltage .......................................... 6.25V
DC Output Current........................................................ 5.0 mA
32,768/65,536 x 8
3
AT25HP256/512
1113I–SEEPR–6/03
Note: 1. This parameter is characteri zed and is not 100% tes ted.
Note: 1. VIL and VIH max are reference only and are not te sted.
Pin C apacitance(1)
Applicable over recomme nded operat ing range from TA = 25°C, f = 1.0 MHz, VCC = +5. 0V (unless otherwise noted).
Symbol Test Conditions Max Units Conditi ons
COUT Output Capacitance (SO) 8 pF VOUT = 0V
CIN Input Capacitance (CS, SCK, SI, WP, HOL D)6pFV
IN = 0 V
DC Characteristics
Applicable over recomme nded operat ing range from: TAI = -40 °C to +85°C, VCC = +1.8V to +5. 5V ,
TAC = 0°C to +70°C, VCC = +1.8V to +5.5V (unless otherwise noted).
Symbol P arameter Test Conditi on Min Typ Max Un it s
VCC1 Supply Voltage 1.8 3.6 V
VCC2 Supply Voltage 2.7 5.5 V
VCC3 Supply Voltage 4.5 5.5 V
ICC1 Supply Current VCC = 5.0V at 5 MHz, SO = Open Read 6.0 10.0 mA
ICC2 Supply Current VCC = 5.0V at 5 MHz, SO = Open Write 4.0 7.0 mA
ISB1 Standby Current VCC = 1. 8 V, CS = VCC 0.1 2.0 µA
ISB2 Standby Current VCC = 2.7 V, CS = VCC 0.2 2.0 µA
ISB3 Standby Current VCC = 5.0 V, CS = VCC 2.0 5.0 µA
IIL Input Leakage VIN = 0V to VCC -3.0 3.0 µA
IOL Output Leakage VIN = 0V to VCC, TAC = 0°C to 70°C -3.0 3.0 µA
VIL(1) Input Low Vol tage -0.6 VCC x 0. 3 V
VIH(1) I nput High Volt age VCC x 0.7 VCC + 0.5 V
VOL1 Out p u t Lo w Vol tag e 4.5V ≤ VCC ≤ 5.5V IOL = 3.0 mA 0.4 V
VOH1 Output High Voltage IOH = -1.6 mA VCC - 0.8 V
VOL2 Out p u t Lo w Vol tag e 1.8V ≤ VCC ≤ 3.6V IOL = 0.15 mA 0.2 V
VOH2 Output High Voltage IOH = -100 µA VCC - 0.2 V
4AT25HP256/512 1113I–SEEPR–6/03
AC Characteristics
Applicable over recomme nded operat ing range from TA = -40°C to +85°C, VCC = As Spec ified,
CL = 1 T TL Gate and 30 pF (unless oth erwise noted ).
Symbol Parameter Voltage Min Max Units
fSCK SCK Clo ck F requency 4.5 - 5.5
2.7 - 5.5
1.8 - 5.5
0
0
0
10
5
2MHz
tRI Input Rise Time 4.5 - 5.5
2.7 - 5.5
1.8 - 5.5
2
2
2µs
tFI Input Fall Time 4.5 - 5.5
2.7 - 5.5
1.8 - 5.5
2
2
2µs
tWH SCK High Time 4.5 - 5.5
2.7 - 5.5
1.8 - 5.5
40
80
200 ns
tWL SCK Lo w Time 4.5 - 5.5
2.7 - 5.5
1.8 - 5.5
40
80
200 ns
tCS CS High Time 4.5 - 5.5
2.7 - 5.5
1.8 - 5.5
50
100
250 ns
tCSS CS Setup Time 4.5 - 5.5
2.7 - 5.5
1.8 - 5.5
50
100
250 ns
tCSH CS Hold Time 4.5 - 5.5
2.7 - 5.5
1.8 - 5.5
50
100
250 ns
tSU Data In Setup Time 4.5 - 5.5
2.7 - 5.5
1.8 - 5.5
12
20
50 ns
tH Data In Hold Time 4.5 - 5.5
2.7 - 5.5
1.8 - 5.5
10
20
50 ns
tHD Hold Setup Time 4.5 - 5.5
2.7 - 5.5
1.8 - 5.5
25
50
100 ns
tCD Hold Hol d Time 4.5 - 5.5
2.7 - 5.5
1.8 - 5.5
25
50
100 ns
tVOutput Valid 4.5 - 5.5
2.7 - 5.5
1.8 - 5.5
0
0
0
40
80
200 ns
tHO Output Hold Time 4.5 - 5.5
2.7 - 5.5
1.8 - 5.5
0
0
0ns
5
AT25HP256/512
1113I–SEEPR–6/03
Note: 1. This parameter is characteri zed and is not 100% tes ted.
tLZ Hold to Output Low Z 4.5 - 5.5
2.7 - 5.5
1.8 - 5.5
0
0
0
100
200
300 ns
tHZ Hold to Output High Z 4.5 - 5.5
2.7 - 5.5
1.8 - 5.5
100
200
300 ns
tDIS Output Disable Time 4.5 - 5.5
2.7 - 5.5
1.8 - 5.5
100
100
250 ns
tWC Write Cycle Time 4.5 - 5.5
2.7 - 5.5
1.8 - 5.5
10
10
10 ms
Endurance(1) 5.0V, 25°C, Page Mode 4.5 - 5.5
2.7 - 5.5
1.8 - 5.5 100K Write Cycles
AC Characteristics (Continued)
Applicable over recomme nded operat ing range from TA = -40°C to +85°C, VCC = As Spec ified,
CL = 1 T TL Gate and 30 pF (unless oth erwise noted ).
Symbol Parameter Voltage Min Max Units
6AT25HP256/512 1113I–SEEPR–6/03
Serial Interface
Description MASTER: The device th at gene rates the serial clock.
SLAVE: Bec aus e the S eri al C loc k pin (S CK ) is a lwa ys an i npu t, th e A T25 HP 256/5 1 2
always operates as a slave.
TRANSMITTER/RECEIVER: The AT25HP256/512 has separate pins designated for
data transmission (SO) and reception (SI).
MSB: The Most S ig nificant Bit (MSB) is the f irst bit trans mitted and received.
SERIAL O P-CO DE: After the device is selected with CS go ing l o w , the firs t byt e will be
receive d. This byte contains the op-code that defines the operations to be performed.
INVALID OP -CO DE: If an inv alid op- code is rec eive d, no data wi ll be shif te d int o the
AT 25H P25 6/5 12, an d th e se rial ou tpu t pi n (SO ) will rem ain in a h igh im peda nc e sta te
until the falling edge of CS is detected again. This will reinitialize the serial
communication.
CHIP SELECT: T he AT25HP256/512 is selected when t he CS pin is l ow. When the
devic e is n ot selecte d, dat a wil l not b e ac cept ed via the S I pin, a nd t he serial ou tput pi n
(SO) will remain in a high impedanc e state.
HOLD: The HOLD pin is used in conjunction with the CS pin to select the
AT25HP256/51 2. When the devi ce is selected an d a serial sequence is underway,
HOLD can be used to pause the serial communication with the master device without
r eset ting th e s erial sequ en ce. To pa us e, th e H OLD p in mu st be b rough t low whil e th e
SCK pin is low. To resume serial communication, the HOLD pin is brought high while the
SCK pi n is low (SCK ma y still toggle duri ng HO LD). Inputs to the SI pin wil l be ignored
while the SO pin is in the high impedance s tate.
WRITE PROTECT: The write protec t pin (WP) w ill allow n orm al re ad/ write ope rati ons
w hen he ld hi gh. Wh en the W P pin is brought low and WPEN bit is “1”, all write opera-
tions to the status register are inhibited. WP going low while CS is still low will interrupt a
write to the status register. If the internal write cycle has already been initiated, WP
goi ng lo w will ha ve n o ef fe ct on any write o perat ion to the status regi ster . The WP pin
fu nct ion is b loc ke d w hen th e WP E N bi t in the st atu s r egi ste r is “ 0” . Thi s will all ow t he
user to install the AT25HP256/512 in a system with the WP pin tied t o groun d and s till
be able to write to the status register. All WP pin functions are enabled when the WPE N
bit i s se t to “1 ” .
7
AT25HP256/512
1113I–SEEPR–6/03
SPI Se rial Interface Functi onal Description
AT25HP256/512
8AT25HP256/512 1113I–SEEPR–6/03
The AT25HP256/512 is designed to interface directly with the synchronous serial
peripheral interface (SPI) of the 6800 type series of microcontrollers.
The AT25HP256/512 utilizes an 8-bit instruction register. The list of instructions and
their operation codes are contained in Table 1. All instructions, addresses, and data are
transferred with the MSB first and start with a high-to-low CS transition.
WRITE ENABLE (WREN): The device will power up in the write disable state when VCC
is appl ied. Al l programm ing instruct ions must t herefor e be precede d by a Wri te Enable
instruction.
WR ITE DIS ABLE (W RDI): To protect the device against inadvertent writes, the Write
D isable inst ruction d isab les all prog ramm ing mode s. Th e WR DI instructi on is ind epen-
dent of the status of the WP pin.
READ STATUS REGISTER (RDSR): The Read Status Register instruction provides
access to the s tatus register. The READY /BUSY and W rite Enable status of the dev ice
can be determined by the RDSR instruction. Similarly, the Block Write Protection bits
ind ica te the e xtent of protection e mployed . These bits are set by using the WRSR
instruction.
Table 1. Instruction Set for the AT25HP 256/512
Instr ucti on Nam e Instr u cti on For m at Ope rat ion
WREN 0000 X110 Set Write Enabl e Latc h
WRDI 0000 X100 Reset Wri te Enable La tch
RDSR 0000 X101 Read Status Register
WRSR 0000 X001 W rite Status Register
READ 0000 X011 Read Data from Memory Array
WRITE 0000 X010 Write Data to Memory Array
Table 2. Status Register Format
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
WPEN X X X BP1 BP0 WEN RDY
9
AT25HP256/512
1113I–SEEPR–6/03
WRITE STATUS REGIS TER (WRSR): The WRSR instruction all ows the user to select
one of four levels of protection. The AT25HP256/512 is divided into four array seg-
ments. Top quarter (1/4), top half (1/2), or all of the memory segments can be protected.
Any of the data within any selected segment will therefore be READ only. The block
write protection l evels and c orresponding statu s register con trol bits are s hown in Table
4.
The three bi ts, BP 0, BP1, and WPEN are nonvolatile cells that have the same properties
and functions as the regular memory cells (e.g. WREN, tWC, RDSR).
The WRSR instruc tion al so allows the us er to enab le or di sable the write protect (W P)
pin through the use of the Write Protect Enable (WPEN) bit. Hardware write protection is
enab led wh en the WP p in is lo w and the WPEN b it is “1”. Hardware write prote ction is
disabled when
either
the WP pin is high or the WPEN bit is “0.” When the device is hard-
ware write prot ected, writes to the Status Regi ster, including t he Block Prot ect bits and
the WPEN bit, and the block-p rotected section s in the m emory array are disabled.
W rites are only allowed to se ctions of the memory which are not block-protected.
NOTE: Whe n the WPEN bit is ha rdwa re write p rote cted, it cann ot be chan ged ba ck to
“0”, as long as the WP pin is held low.
Table 3. Read Status Register Bit Definition
Bit Definition
Bit 0 (RDY)Bit 0 = 0 (RDY) indicates the de vice is READY. Bit 0 = 1 indicates the write
cy cle is in progress.
Bit 1 (WEN) Bit 1= 0 indicates the devi ce
is not
WRITE ENABLED. Bit 1 = 1 indicates the
device is WRITE ENABLED.
Bit 2 (BP0) See Table 4 .
Bit 3 (BP1) See Table 4 .
Bits 4-6 are 0s when device is not in an internal write cycle.
Bit 7 (WPEN) See Table 5.
Bits 0-7 are 1s during an intern al write cycle.
Table 4. Block Write Protect Bits
Level
Status Register Bits Array Addresses Protected
BP1 BP0 AT25HP256/512
000 None
1(1/4) 0 1 6000 - 7FFF/C000 - FFFF
2(1/2) 1 0 4000 - 7FFF/8000 - FFFF
3(All) 1 1 0000 - 7FFF/0000 - FFFF
Table 5. WPEN Operation
WPEN WP WEN ProtectedBlocks UnprotectedBlocks Status Register
0 X 0 Protected Protected Protected
0 X 1 Protected Writable Writable
1 Low 0 Protected Protected Protected
10 AT25HP256/512 1113I–SEEPR–6/03
READ SEQUENCE (READ): Reading the AT25HP256/512 via the SO (Serial Output)
pin requires the following sequence. After the CS line is pulled low to select a device,
the REA D op-c ode is trans m itted via the SI line followed by t he by te addres s to be read
( Refer to Tabl e 6). Upo n co mplet ion , any data o n the S I line will b e ign ore d. Th e dat a
(D7-D0) at the specified address is then shifted out onto the SO line. If o nly o ne b yte is
to be read, the CS line should be driven high a fter the d ata comes out. The READ
sequence can be continued since the byte address is automatically increment ed and
dat a will cont inue to be s hifted out. Wh en the hi ghes t addr ess is reac hed, t he add ress
coun ter will roll over to the lowest address allowing the en tire mem ory to be read in o ne
continuous READ cycle.
WRITE SEQ UEN CE (WRITE): In orde r to prog ram the AT2 5HP2 56/512, two se parat e
instructions must be executed. First, the device must be write enabled via the Write
En able (W REN) Instru ction . Then a W rite (WRI TE) Inst ruction m ay be ex ecuted . Also,
the address of the me mory location(s) to be programm ed mu st be outside the protected
address field location selected by the Block Write Protection Level. During an internal
write cycle, all commands will be ignored except the RDSR i nstruction.
A Write Inst ruction requires the following sequence. After the CS line is pulled low to
selec t the dev ice, t he WRI TE op-cod e is transm itte d via th e S I lin e f ollowed by th e by te
addre ss and the data (D7-D0 ) to be pr ogramme d (Refe r to T able 6). Pro grammi ng will
start a fter the CS pin is brought high. (The LOW to High transition of the CS pin m us t
occur during the SCK low time immediately after clocking in the D0 (LSB) data bit.
The READY/BUSY status of the devic e can be determined by initiating a READ STA-
TUS REGIST ER (RD SR) Instruction. If Bit 0 = 1, the WRITE cycle is still in progress. If
Bit 0 = 0, th e W RITE cycle has ended. Only the READ STATUS REGIST ER in struction
is enabled during the WR ITE programming cycle.
The A T2 5HP 256/512 is c apa ble of a 128-byte PA GE WR ITE operat ion. A fter each byt e
of data is received, the se ven low orde r address bits are internally increm ented by one;
the high order bits of the address will remain constant. If more than 128-bytes of data
are tran smitt ed, the address c ou nte r will roll over and the prev io usly written data wi ll be
ov erwritten. The A T25HP2 56/51 2 is auto matically ret urned to th e write disab le state at
the comp letion of a WRITE cycle.
NOTE: If the device is not Write enab led (WREN), the devi ce will ignore the W rite
instruction a nd wi ll return to the s tandby st ate, when CS is brought high. A new CS fall-
ing edge is required to re-initiate the serial communicat ion.
NOTE: 128-byte PAGE W RITE operation only. Cont ent of th e page in the array will not
be guaranteed if less than 128 bytes of data is received (byte write is not supported).
1 Low 1 Protected Writable Protected
X High 0 Protected Protected Protected
X High 1 Protected Writable Writable
Table 6. Address Key
Address AT25HP256/512
ANA14 - A0 / A15 - A0
Don’t Care Bits A15 / none
Table 5. WPEN Operation
WPEN WP WEN ProtectedBlocks UnprotectedBlocks Status Register
11
AT25HP256/512
1113I–SEEPR–6/03
Timing Diagrams (for SPI Mode 0 (0,0))
Synchronous Data Timing
WREN Timing
WRDI Timing
SO V
OH
V
OL
HI-Z HI-Z
SI V
IH
V
IL
SKC
V
IH
V
IL
CS V
IH
V
IL
VALID IN
t
CSS
t
SU
t
H
t
WH
t
WL
t
V
t
CS
t
CSH
t
DIS
t
HO
SCK
CS
SI
SO
CS
SCK
SI
SO HI-Z
WRDI OP-CODE
12 AT25HP256/512 1113I–SEEPR–6/03
RDSR Timing
WRSR Timing
READ Timing
CS
SCK 0 1234567891011121314
SI INSTRUCTION
SO 76543210
DATA OUT
MSB
HIGH IMPEDANCE
15
13
AT25HP256/512
1113I–SEEPR–6/03
WRI TE Ti m in g ( AT25H P2 5 6)
PAGE WRITE Timing (AT25HP512)
HO LD Ti m i ng
SCK
SI
SO
CS
01234567891011202122
23 24 25 26
INSTRUCTION
HIGH IMPEDANCE
BYTE ADDRESS
15 14 13 321076543210
1ST BYTE DATA IN
27 28 29 30 31
...
10431044 1045 1046 1047
SCK
SI
SO
CS
01234567891011202122
23 24 25 26
INSTRUCTION
HIGH IMPEDANCE
BYTE ADDRESS
15 14 13 321076543210
128th BYTE DATA IN
12
1st BYTE DATA IN
SO
SCK
HOLD
CS
tCD
tHD
tHZ
tHD
tCD
tLZ
14 AT25HP256/512 1113I–SEEPR–6/03
AT25H P25 6 Orderin g Informat ion
tWC (max)
(ms) ICC (max)
(µA) ISB (max)
(µA) fMAX
(kHz) Ordering Co de P ackage Operation Range
10 4000 2.0 5000 AT25HP256-10CI-2.7
AT25HP256-10PI-2.7
AT25HP256W-10SI-2.7
8CN3
8P3
8S2
Industrial
(-40°C to 85°C)
10 3000 2.0 2000 AT25HP256-10CI-1.8
AT25HP256-10PI-1.8
AT25HP256W-10SI-1.8
8CN3
8P3
8S2
Industrial
(-40°C to 85°C)
Package Type
8CN3 8-lead, 0.230 " Wide, Leadless Array P ackage (LAP)
8P3 8-lead, 0.300" Wide, Plastic Dual In-line Package (PDIP)
8S2 8-lead, 0.200 " Wide , Plastic Sma ll Ou tl ine Package (EIAJ)
Options
-2.7 Low Voltage (2.7V to 5.5V)
-1.8 Low Voltage (1.8V to 5.5V)
15
AT25HP256/512
1113I–SEEPR–6/03
Note: For 2.7V devices used in t he 4.5V to 5.5V r ange, please ref er to per formance values in the AC and DC Charac teristics tables.
AT25H P51 2 Orderin g Informat ion
Ordering Code Package Operation Range
AT25HP512-10CI-2.7
AT25HP512C1-10CI-2.7
AT25HP512-10PI-2.7
AT25HP512W2-10SI-2.7
8CN3
8CN1
8P3
16S2
Industrial
(-40°C to 85°C)
AT25HP512-10CI-1.8
AT25HP512C1-10CI-1.8
AT25HP512-10PI-1.8
AT25HP512W2-10SI-1.8
8CN3
8CN1
8P3
16S2
Industrial
(-40°C to 85°C)
Package Type
8CN3 8-lead, 0.230 " Wide, Leadless Array P ackage (LAP)
8CN1 8-lead, 0.300 " Wide, Leadless Array P ackage (LAP)
8P3 8-lead, 0.300" Wide, Plastic Dual In-line Package (PDIP)
16S2 16-lead, 0.300" Wide, Plastic Gull Wing Smal l Outline Pac kage (JEDEC SOIC)
Options
-2.7 Low Voltage (2.7V to 5.5V)
-1.8 Low Voltage (1.8V to 5.5V)
16 AT25HP256/512 1113I–SEEPR–6/03
Packaging Information
8CN3 – LAP
2325 Orchard Parkway
San Jose, CA 95131
TITLE DRAWING NO.
R
REV.
8CN3, 8-lead, (6 x 5 x 1.04 mm Body), Lead Pitch 1.27 mm,
Leadless Array Package (LAP) A
8CN3
11/14/01
Pin1 Corner
Marked Pin1 Indentifier
0.10 mm
TYP
4
3
2
1
5
6
7
8
Top View
L
b
e
L1
e1
Side View
A1
A
Bottom View
E
D
COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL MIN NOM MAX NOTE
A 0.94 1.04 1.14
A1 0.30 0.34 0.38
b 0.36 0.41 0.46 1
D 5.89 5.99 6.09
E 4.83 4.93 5.03
e 1.27 BSC
e1 0.56 REF
L 0.62 0.67 0.72 1
L1 0.92 0.97 1.02 1
Note: 1. Metal Pad Dimensions.
17
AT25HP256/512
1113I–SEEPR–6/03
8CN1 – LAP
2325 Orchard Parkway
San Jose, CA 95131
TITLE DRAWING NO.
R
REV.
8CN1, 8-lead (8 x 5 x 1.04 mm Body), Lead Pitch 1.27 mm,
Leadless Array Package (LAP) A
8CN1
11/13/01
Pin1 Corner
Marked Pin1 Indentifier
0.10 mm
TYP
4
3
2
1
5
6
7
8
Top View
L
b
e
L1
e1
Side View
A1
A
Bottom View
E
D
COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL MIN NOM MAX NOTE
A 0.94 1.04 1.14
A1 0.30 0.34 0.38
b 0.36 0.41 0.46 1
D 7.90 8.00 8.10
E 4.90 5.00 5.10
e 1.27 BSC
e1 0.60 REF
L 0.62 0.67 0.72 1
L1 0.92 0.97 1.02 1
Note: 1. Metal Pad Dimensions.
18 AT25HP256/512 1113I–SEEPR–6/03
8P3 – PDIP
2325 Orchard Parkway
San Jose, CA 95131
TITLE DRAWING NO.
R
REV.
8P3, 8-lead, 0.300" Wide Body, Plastic Dual
In-line Package (PDIP)
01/09/02
8P3 B
D
D1
E
E1
e
L
b2
b
A2 A
1
N
eA
c
b3
4 PLCS
Top View
Side View
End View
COMMON DIMENSIONS
(Unit of Measure = inches)
SYMBOL MIN NOM MAX NOTE
Notes: 1. This drawing is for general information only; refer to JEDEC Drawing MS-001, Variation BA for additional information.
2. Dimensions A and L are measured with the package seated in JEDEC seating plane Gauge GS-3.
3. D, D1 and E1 dimensions do not include mold Flash or protrusions. Mold Flash or protrusions shall not exceed 0.010 inch.
4. E and eA measured with the leads constrained to be perpendicular to datum.
5. Pointed or rounded lead tips are preferred to ease insertion.
6. b2 and b3 maximum dimensions do not include Dambar protrusions. Dambar protrusions shall not exceed 0.010 (0.25 mm).
A 0.210 2
A2 0.115 0.130 0.195
b 0.014 0.018 0.022 5
b2 0.045 0.060 0.070 6
b3 0.030 0.039 0.045 6
c 0.008 0.010 0.014
D 0.355 0.365 0.400 3
D1 0.005 3
E 0.300 0.310 0.325 4
E1 0.240 0.250 0.280 3
e 0.100 BSC
eA 0.300 BSC 4
L 0.115 0.130 0.150 2
19
AT25HP256/512
1113I–SEEPR–6/03
8S2 – EIAJ SOIC
2325 Orchard Parkway
San Jose, CA 95131
TITLE DRAWING NO.
R
REV.
8S2, 8-lead, 0.209" Body, Plastic Small
Outline Package (EIAJ)
5/2/02
8S2 B
Top View
Side View
End View
H
1
N
C
E
A
b
L
A1
e
D
COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL MIN NOM MAX NOTE
Notes: 1. This drawing is for general information only; refer to EIAJ Drawing EDR-7320 for additional information.
2. Mismatch of the upper and lower dies and resin burrs aren't included.
3. It is recommended that upper and lower cavities be equal. If they are different, the larger dimension shall be regarded.
4. Determines the true geometric position.
5. Values b,C apply to pb/Sn solder plated terminal. The standard thickness of the solder layer shall be 0.010 +0.010/-0.005 mm.
A 1.78 2.03
A1 0.05 0.33
b 0.35 0.51 5
C 0.18 0.25 5
D 5.13 5.38
E 5.13 5.41 2, 3
H 7.62 8.38
L 0.51 0.89
e 1.27 BSC 4
20 AT25HP256/512 1113I–SEEPR–6/03
16S2 – JEDEC SOIC
2325 Orchard Parkway
San Jose, CA 95131
TITLE DRAWING NO.
R
REV.
16S2, 16-lead, 0.300" Wide Body, Plastic Gull
Wing Small Outline Package (SOIC)
1/9/02
16S2 A
L
A1
Side View
Top View End View
H
E
b
N
1
e
A
D
C
COMMON DIMENSIONS
(Unit of Measure = inches)
SYMBOL MIN NOM MAX NOTE
Notes: 1. This drawing is for general information only; refer to JEDEC Drawing MS-013, Variation AA for additional information.
2. Dimension "D" does not include mold Flash, protrusions or gate burrs. Mold Flash, protrusions and gate burrs shall not exceed
0.15 mm (0.006") per side.
3. Dimension "E" does not include inter-lead Flash or protrusion. Inter-lead Flash and protrusions shall not exceed 0.25 mm
(0.010") per side.
4. "L" is the length of the terminal for soldering to a substrate.
5. The lead width "B", as measured 0.36 mm (0.014") or greater above the seating plane, shall not exceed a maximum value of 0.61 mm
(0.024") per side.
A 0.0926 0.1043
A1 0.0040 0.0118
b 0.0130 0.0200 5
C 0.0091 0.0125
D 0.3977 0.4133 2
E 0.2914 0.2992 3
H 0.3940 0.4190
L 0.0160 0.050 4
e 0.050 BSC
Pr inted o n rec ycled pa per.
1113I–SEEPR–6/03 xM
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