CY2071A Single-PLL General-Purpose EPROM Programmable Clock Generator Features Benefits * Single phase-locked loop architecture * EPROM programmability * Factory-programmable (CY2071A, CY2071AI) or field-programmable (CY2071AF, CY2071AFI) device options * Up to three configurable outputs * Low skew, low jitter, high-accuracy outputs * Internal loop filter * Power management (OE) * Frequency select options * Configurable 5V or 3.3V operation * 8-pin 150-mil SOIC package * * * * * * * * * * Generates a custom frequency from an external source Easy customization and fast turnaround Programming support available for all opportunities Generates three related frequencies from a single device Meets critical industry standard timing requirements Alleviates the need for external components Supports low-power applications Three outputs with two user-selectable frequencies Supports industry standard design platforms Industry standard packaging saves on board space Selector Guide Part Number Outputs Input Frequency Range Output Frequency Range Specifics CY2071A 3 10 MHz-25 MHz (external crystal) 1 MHz-30 MHz (reference clock) 500 kHz-130 MHz (5V) 500 kHz-100 MHz (3.3V) Factory Programmable Commercial Temperature CY2071AI 3 10 MHz-25 MHz (external crystal) 1 MHz-30 MHz (reference clock) 500 kHz-100 MHz (5V) 500 kHz-80 MHz (3.3V) Factory Programmable Industrial Temperature CY2071AF 3 10 MHz-25 MHz (external crystal) 1 MHz-30 MHz (reference clock) 500 kHz-100 MHz (5V) 500 kHz-80 MHz (3.3V) Field Programmable Commercial Temperature CY2071AFI 3 10 MHz-25 MHz (external crystal) 1 MHz-30 MHz (reference clock) 500 kHz-90 MHz (5V) 500 kHz-66.6 MHz (3.3V) Field Programmable Industrial Temperature Logic Block Diagram for CY2071A XTALIN REFERENCE OSCILLATOR CLKA EPROMConfigurable Multiplexer and Divide Logic XTALOUT PLL Block CLKB CLKC OE / FS Pin Configuration 8-pin SOIC Top View CLKA GND XTALIN XTALOUT 1 2 3 4 8 7 6 5 Cypress Semiconductor Corporation Document #: 38-07139 Rev. *D OE/FS VDD CLKC CLKB * 198 Champion Court * San Jose, CA 95134-1709 * 408-943-2600 Revised August 3, 2006 CY2071A Pin Summary Name CLKA GND XTALIN [1] XTALOUT [1, 2] Number Description 1 Configurable Clock Output 2 Ground 3 Reference Crystal Input or External Reference Clock Input 4 Reference Crystal Feedback CLKB 5 Configurable Clock Output CLKC 6 Configurable Clock Output VDD 7 Voltage Supply OE / FS 8 Output Control Pin, either Output Enable or Frequency Select Input (Active HIGH, internal pull-up resistor to VDD) Functional Description CyClocks Software The CY2071A is a general-purpose clock synthesizer designed for use in applications such as modems, disk drives, CD-ROM drives, video CD players, games, set-top boxes, and data/telecommunications. The device offers up to three configurable clock outputs in an 8-pin, 150-mil SOIC package and can operate off either a 3.3V or 5V power supply. The on-chip reference oscillator is designed for 10 MHz to 25 MHz crystals. Alternatively, an external reference clock of frequency between 1 MHz and 30 MHz can be used. CyClocksTM is an easy-to-use software application that allows you to configure any one of the EPROM-Programmable Clocks offered by Cypress. You may specify the input frequency, PLL and output frequencies, and different functional options. Note the output frequency ranges in this data sheet when specifying them in CyClocks to ensure that you stay within the limits. You can download a copy of CyClocks free on the Cypress Semiconductor Corporation web site at www.cypress.com. The CY2071A has one PLL and outputs three factory-EPROM configurable clocks: CLKA, CLKB, and CLKC. The output clocks can originate either from the PLL or the reference, or selected dividers thereof. Additionally, pin 8 can be configured to be an Output Enable or a Select input. Use the CY2081 for applications that require unrelated output frequencies. Use the CY2291, CY2292, or CY2907 for applications that require more than three output clocks. The CY2071A can replace multiple Metal Can Oscillators (MCO) in a synchronous system, providing cost and board space savings to the manufacturer. Hence, these devices are ideally suited for applications that require multiple, accurate, and stable clocks synthesized from low-cost generators in small packages. A hard-disk drive is an example of such an application. In this case, CLKA drives the PLL in the Read Controller, while CLKB and CLKC drive the MCU and associated sequencers. The Cypress Frequency Timing Generator (FTG) Programmer is a portable programmer designed to custom program our family of EPROM Field Programmable Clock Devices. The FTG programmers connect to a PC serial port and allow users of CyClocks software to easily program any of the CY2291F, CY2292F, CY2071AF, and CY2907F devices. The ordering code for the Cypress FTG Programmer is CY3670. Cypress FTG Programmer Absolute Maximum Conditions[3, 4] Parameter Description Condition Min. VDD Analog Supply Voltage -0.5 VIN DC Input Voltage -0.5 TS Temperature, Storage Non-functional TA Temperature, Maximum Soldering (10 sec) Functional TJ Temperature, Junction Functional ESDHBM ESD Protection (Human Body Model) MIL-STD-883, Method 3015 Max. Unit 7.0 V VDD + 0.5 VDC -65 150 C - 260 C - 150 C 2000 - V Notes 1. For best accuracy, use a parallel-resonant crystal, CL = 17 pF. 2. Float XTALOUT pin if XTALIN is driven by reference clock (as opposed to an external crystal). 3. Stresses greater than those listed in this table may cause permanent damage to the device. 4. Multiple Supplies: The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required. Document #: 38-07139 Rev. *D Page 2 of 9 CY2071A Operating Conditions[5] Parameter Description Min. Max. Unit VDD Supply Voltage, 5.0V Operation 4.5 5.5 V VDD Supply Voltage, 3.3V Operation 3.0 3.6 V TA Commercial Operating Temperature, Ambient Industrial Operating Temperature, Ambient CL fREF tPU 0 70 C -40 85 C Max. Load Capacitance per Output (5V Operation) - 25 pF Max. Load Capacitance per Output (3.3V Operation) - 15 pF External Reference Crystal 10.0 25.0 MHz External Reference Clock[6, 7] 1.0 30.0 MHz Power-up time for all VDDs to reach minimum specified voltage (power ramps must be monotonic) 0.05 50 ms Electrical Characteristics, Commercial 5.0V: VDD = 5V 10%, TA = 0C to +70C[8] Parameter Description Conditions VOH HIGH-Level Output Voltage IOH = -4.0 mA VOL LOW-Level Output Voltage IOL = 4.0 mA VIH HIGH-Level Input Voltage[9] Except Crystal Pins Voltage[9] Min. Typ. Max. Unit 2.4 - - V - - 0.4 V 2.0 - - V VIL LOW-Level Output Except Crystal Pins - - 0.8 V IIH Input HIGH Current VIN = VDD - 0.5V - - 10 A IIL Input LOW Current VIN = 0.5V - - 150 A IOZ Output Leakage Current Three State Outputs - - 250 A 40 60 mA Min. Typ. Max. Unit 2.4 - - V - - 0.4 V 2.0 - - V IDD VDD Supply Current[10] VDD = VDD max. 5V operation, CL = 25 pF Electrical Characteristics, Commercial 3.3V: VDD = 3.3V 10%, TA = 0C to 70C[8] Parameter Description VOH HIGH-Level Output Voltage Conditions IOH = -4.0 mA VOL LOW-Level Output Voltage IOL = 4.0 mA VIH HIGH-Level Input Voltage[9] Except Crystal Pins VIL LOW-Level Output Voltage[9] Except Crystal Pins - - 0.8 V IIH Input HIGH Current VIN = VDD - 0.5V - - 10 A IIL Input LOW Current VIN = 0.5V - - 150 A IOZ Output Leakage Current Three State Outputs - - 250 A VDD = VDD max. 3.3V operation, CL = 15 pF - 24 40 mA IDD VDD Supply Current[10] Notes: 5. Electrical parameters are guaranteed with these operating conditions. Values for 3.3V operation are shown in parentheses. 6. External input reference clock must have a duty cycle between 40% and 60%, measured at VDD/2. 7. Please refer to application note "Crystal Oscillator Topics" for information on AC-coupling the external input reference clock. 8. See "CY2071A and CY2907 Clock Generators" Application Note for important customer clarification. 9. Xtal inputs have CMOS thresholds. 10. Load = max, typical configuration, fREF = 14.318 MHz. Specific configurations may vary. A close approximation of IDD can be derived by the following formula: IDD(mA) = VDD*(6.25+(0.055*FREF) + (0.0017*CLOAD*(FCLKA+FCLKB+FCLKC))). CLOAD is specified in pF and F is specified in MHz. Document #: 38-07139 Rev. *D Page 3 of 9 CY2071A Electrical Characteristics, Industrial 5.0V: VDD = 5.0V 10%, TA = -40C to 85C[8] Parameter Description Conditions VOH HIGH-Level Output Voltage IOH = -4.0 mA VOL LOW-Level Output Voltage IOL = 4.0 mA VIH HIGH-Level Input Voltage[9] Except Crystal Pins VIL LOW-Level Output Voltage[9] Except Crystal Pins Min. Typ. Max. Unit 0.4 V 2.4 V 2.0 V 0.8 V IIH Input HIGH Current VIN = VDD - 0.5V 10 A IIL Input LOW Current VIN = 0.5V 150 A IOZ Output Leakage Current Three State Outputs IDD VDD Supply Current[10] VDD = VDD max. 5V operation, CL = 25 pF 250 A 40 75 mA Typ. Max. Unit Electrical Characteristics, Industrial 3.3V VDD =3.3V 10%, TA = -40C to +85C[8] Parameter Description Conditions Min. VOH HIGH-Level Output Voltage VOL LOW-Level Output Voltage IOL = 4.0 mA VIH HIGH-Level Input Voltage[9] Except Crystal Pins VIL LOW-Level Output Voltage[9] Except Crystal Pins 0.8 V IIH Input HIGH Current VIN = VDD - 0.5V 10 A IIL Input LOW Current VIN = 0.5V 150 A IOZ Output Leakage Current Three State Outputs 250 A 50 mA IDD VDD Supply Current[10] IOH = -4.0 mA 2.4 V 0.4 2.0 V V VDD = VDD max. 3.3V operation, CL = 15 pF 24 Switching Characteristics, Commercial 5.0V[11] Parameter t1 Name Output Period Description Clock output range 5V operation 25-pF load Max. Unit CY2071A 7.692 [130 MHz] Min. Typ. 2000 [500 kHz] ns CY2071AF 10 [100 MHz] 2000 [500 kHz] ns t1A Clock Jitter Peak-to-peak period jitter (t1 max. - t1 min.), % of clock period, fOUT 16 MHz 0.8 1 % t1B Clock Jitter Peak-to-peak period jitter (16 MHz fOUT 50 MHz) 350 500 ps t1C Clock Jitter[12] Peak-to-peak period jitter (fOUT > 50 MHz) ps Output Duty Cycle Duty cycle[13, 14] for outputs, (t2 / t1) fOUT 60 MHz 250 350 45% 50% 55% 40% 50% 60% Output clock rise time 1.5 2.5 1.5 Output Duty Cycle[12] Duty cycle[14] for outputs, (t2 / t1), fOUT > 60 MHz t3 Rise Time[12] [12] t4 Fall Time Output clock fall time t5 Skew Skew delay between any two outputs with identical frequencies (generated by the PLL) ns 2.5 ns 0.5 ns Notes: 11. Guaranteed by design, not 100% tested. 12. When the output clock frequency is between 100 MHz and 130 MHz at 5V, the maximum capacitive load for these measurements is 15 pF. 13. Reference Output duty cycle depends on XTALIN duty cycle. 14. Measured at 1.4V. Document #: 38-07139 Rev. *D Page 4 of 9 CY2071A Switching Characteristics, Commercial 3.3V[11] Parameter t1 Name Output Period Description Min. Clock output range 3.3V operation CY2071AS 15-pF load CY2071AF Typ. Max. Unit 10 [100 MHz] 2000 [500 kHz] ns 12.50 [80 MHz] 2000 [500 kHz] ns t1A Clock Jitter Peak-to-peak period jitter (t1 max. - t1 min.), % of clock period, fOUT 16 MHz 0.8 1 % t1B Clock Jitter Peak-to-peak period jitter (16 MHz fOUT 50 MHz) 350 500 ps t1C Clock Jitter[12] Peak-to-peak period jitter (fOUT > 50 MHz) 250 350 ps Output Duty Cycle 45% 50% 55% Output Duty Cycle[12] Duty cycle[13, 14] for outputs, (t2 / t1) fOUT 60 MHz Duty cycle[14] for outputs, (t2 / t1), fOUT > 60 MHz 40% 50% 60% t3 Rise Time[12] Output clock rise time 1.5 2.5 ns t4 Fall Time[12] Output clock fall time 1.5 2.5 ns t5 Skew Skew delay between any two outputs with identical frequencies (generated by the PLL) 0.5 ns Switching Characteristics, Industrial 5.0V[11] Parameter t1 Name Output Period Description Min. Clock output range 5.0V operation CY2071AI 25-pF load CY2071AFI Max. Unit 10 [100 MHz] Typ. 2000 [500 kHz] ns 11.1 [90 MHz] 2000 [500 kHz] ns t1A Clock Jitter Peak-to-peak period jitter (t1 max. - t1 min.), % of clock period, fOUT 16 MHz 0.8 1 % t1B Clock Jitter Peak-to-peak period jitter (16 MHz fOUT 50 MHz) 350 500 ps t1C Clock Jitter[12] Peak-to-peak period jitter (fOUT > 50 MHz) 250 350 ps Output Duty Cycle Duty cycle[13, 14] for outputs, (t2 / t1) fOUT 60 MHz 45% 50% 55% Output Duty Cycle[12] Duty cycle[14] for outputs, (t2 / t1), fOUT > 60 MHz 40% 50% 60% t3 Rise time[12] Output clock rise time 1.5 2.5 ns t4 Fall time[12] Output clock fall time 1.5 2.5 ns t5 Skew Skew delay between any two outputs with identical frequencies (generated by the PLL) 0.5 ns Document #: 38-07139 Rev. *D Page 5 of 9 CY2071A Switching Characteristics, Industrial 3.3V[11] Parameter t1 Name Description Output Period Min. Clock output range 3.3V operation CY2071AI 15-pF load CY2071AFI Typ. Max. Unit 12.50 [80 MHz] 2000 [500 kHz] ns 15.0 [66.6 MHz] 2000 [500 kHz] ns t1A Clock Jitter Peak-to-peak period jitter (t1 max. - t1 min.), % of clock period, fOUT 16 MHz 0.8 1 % t1B Clock Jitter Peak-to-peak period jitter (16 MHz fOUT 50 MHz) 350 500 ps t1C Clock Jitter[12] Peak-to-peak period jitter (fOUT > 50 MHz) 250 350 ps Output Duty Cycle Duty cycle[13, 14] for outputs, (t2 / t1) fOUT 60 MHz 45% 50% 55% Output Duty Cycle[12] Duty cycle[14] for outputs, (t2 / t1), fOUT > 60 MHz 40% 50% 60% Rise time[12] Output clock rise time 1.5 2.5 Output clock fall time 1.5 t3 time[12] t4 Fall t5 Skew Skew delay between any two outputs with identical frequencies (generated by the PLL) ns 2.5 ns 0.5 ns Switching Waveforms Figure 1. All Outputs Duty Cycle and Rise/Fall Time t1 t2 OUTPUT 2.4V 0.4V VDD 2.4V 0.4V 0V t4 t3 Figure 2. Output-Output Clock Skew OUTPUT OUTPUT t5 Test Circuit VDD 7 0.1 F OUTPUTS CLK output CLOAD 2 GND Document #: 38-07139 Rev. *D Page 6 of 9 CY2071A Ordering Information Ordering Code Package Type Operating Range CY2071ASC-XXX 8-Pin (150-Mil) SOIC 5.0V, Commercial, Factory Programmable CY2071ASC-XXXT 8-Pin (150-Mil) SOIC - Tape and Reel 5.0V, Commercial, Factory Programmable CY2071ASL-XXX 8-Pin (150-Mil) SOIC 3.3V, Commercial, Factory Programmable CY2071ASL-XXXT 8-Pin (150-Mil) SOIC - Tape and Reel 3.3V, Commercial, Factory Programmable CY2071ASI-XXX 8-Pin (150-Mil) SOIC 5V/3.3V, Industrial, Factory Programmable CY2071ASI-XXXT 8-Pin (150-Mil) SOIC - Tape and Reel 5V/3.3V, Industrial, Factory Programmable CY2071AF 8-Pin (150-Mil) SOIC 5V/3.3V, Commercial, Field Programmable CY2071AFT 8-Pin (150-Mil) SOIC - Tape and Reel 5V/3.3V, Commercial, Field Programmable CY2071AFI 8-Pin (150-Mil) SOIC 5V/3.3V, Industrial, Field Programmable CY2071AFIT 8-Pin (150-Mil) SOIC - Tape and Reel 5V/3.3V, Industrial, Field Programmable CY3670 FTG Programmer Custom programming for Field Programmable Clocks Lead-Free CY2071ASXC-XXX 8-Pin (150-Mil) SOIC 5.0V, Commercial, Factory Programmable CY2071ASXC-XXXT 8-Pin (150-Mil) SOIC - Tape and Reel 5.0V, Commercial, Factory Programmable CY2071ASXL-XXX 8-Pin (150-Mil) SOIC 3.3V, Commercial, Factory Programmable CY2071ASXL-XXXT 8-Pin (150-Mil) SOIC- Tape and Reel 3.3V, Commercial, Factory Programmable CY2071ASXI-XXX 8-Pin (150-Mil) SOIC 5V/3.3V, Industrial, Factory Programmable CY2071ASXI-XXXT 8-Pin (150-Mil) SOIC- Tape and Reel 5V/3.3V, Industrial, Factory Programmable CY2071AFXC 8-Pin (150-Mil) SOIC 5V/3.3V, Commercial, Field Programmable CY2071AFXCT 8-Pin (150-Mil) SOIC- Tape and Reel 5V/3.3V, Commercial, Field Programmable CY2071AFXI 8-Pin (150-Mil) SOIC 5V/3.3V, Industrial, Field Programmable CY2071AFXIT 8-Pin (150-Mil) SOIC- Tape and Reel 5V/3.3V, Industrial, Field Programmable Package Characteristics Package JA (C/W) JC (C/W) Transistor Count 170 35 5436 8 Pin SOIC Document #: 38-07139 Rev. *D Page 7 of 9 CY2071A Package Drawing and Dimensions Figure 3. 8-lead (150-Mil) SOIC S8 8 Lead (150 Mil) SOIC - S08 PIN 1 ID 4 1 1. DIMENSIONS IN INCHES[MM] MIN. MAX. 2. PIN 1 ID IS OPTIONAL, ROUND ON SINGLE LEADFRAME RECTANGULAR ON MATRIX LEADFRAME 0.150[3.810] 0.157[3.987] 3. REFERENCE JEDEC MS-012 0.230[5.842] 0.244[6.197] 4. PACKAGE WEIGHT 0.07gms PART # S08.15 STANDARD PKG. 5 SZ08.15 LEAD FREE PKG. 8 0.189[4.800] 0.196[4.978] 0.010[0.254] 0.016[0.406] SEATING PLANE X 45 0.061[1.549] 0.068[1.727] 0.004[0.102] 0.050[1.270] BSC 0.004[0.102] 0.0098[0.249] 0~8 0.016[0.406] 0.035[0.889] 0.0075[0.190] 0.0098[0.249] 0.0138[0.350] 0.0192[0.487] 51-85066-*C CyClocks is a trademark of Cypress Semiconductor Corporation. All product and company names mentioned in this document are trademarks of their respective holders. Document #: 38-07139 Rev. *D Page 8 of 9 (c) Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. CY2071A Document History Page Document Title: CY2071A Single-PLL General-Purpose EPROM Programmable Clock Generator Document Number: 38-07139 REV. ECN NO. Issue Date Orig. of Change Description of Change ** 110248 12/17/01 SZV Change from Spec number: 38-00521 to 38-07139 *A 121827 12/14/02 RBI Power up requirements added to Operating Conditions Information *B 279389 See ECN RGL Added lead-free devices *C 296792 See ECN RGL Minor Typo: missed one letter (C) in the ordering code *D 492389 See ECN RGL Added a note on all Electrical specs table specifying the Application notes name for customer's clarification Reformatted using new template Document #: 38-07139 Rev. *D Page 9 of 9