1
ECL Pro®
SY100EP195V
Micrel, Inc.
M9999-120505
hbwhelp@micrel.com or (408) 955-1690
DESCRIPTION
■Pin-for-pin, plug-in compatible to the ON
Semiconductor MC100EP195
■Maximum frequency > 2.5GHz
■Programmable range: 2.2ns to 12.2ns
■10ps increments
■PECL mode operating range: VCC = 3.0V to 5.5V
with VEE = 0V
■NECL mode operating range: VCC = 0V
with VEE = –3.0V to –5.5V
■Open input default state
■Safety clamp on inputs
■A logic high on the /EN pin will force Q to logic low
■D[0:10] can accept either ECL, CMOS, or TTL inputs
■VBB output reference voltage
■Available in a 32-pin TQFP package
FEATURES
3.3V/5V 2.5GHz
PROGRAMMABLE DELAY
ECL Pro®
SY100EP195V
APPLICATIONS
■Clock de-skewing
■Timing adjustment
■Aperture centering
Rev.: D Amendment: /0
Issue Date: December 2005
Micrel Semiconductor ON Semiconductor
SY100EP195VTI MC100EP195FA
SY100EP195VTITR MC100EP195FAR2
CROSS REFERENCE TABLE
The SY100EP195V is a programmable delay line, varying
the time a logic signal takes to traverse from IN to Q. This
delay can vary from about 2.2ns to about 12.2ns. The input
can be PECL, LVPECL, NECL, or LVNECL.
The delay varies in discrete steps based on a control
word presented to SY100EP195V. The 10-bit width of this
latched control register allows for delay increments of
approximately 10ps.
An eleventh control bit allows the cascading of multiple
SY100EP195V devices, for a wider delay range. Each
additional SY100EP195V effectively doubles the delay range
available.
For maximum flexibility, the control register interface
accepts CMOS or TTL level signals, as well as the input
level at the IN± pins.
All support documentation can be found on Micrel’s web
site at: www.micrel.com.
TYPICAL APPLICATIONS CIRCUIT TYPICAL PERFORMANCE
IN
CONTROL
LOGIC
Data Signal
of Unknown Phase
CLOCK+
CLOCK– /IN
Q
/Q
D
CK
Q+
Q–
D[9:0]
SY100EP195V Flip-Flop
0
2000
4000
6000
8000
10000
12000
0 200 400 600 800 1000 1200
DELAY (ps)
TAP (DIGITAL WORD)
Delay vs. Tap
ECL Pro is a registered trademark of Micrel, Inc.
ECL Pro®
2
ECL Pro®
SY100EP195V
Micrel, Inc.
M9999-120505
hbwhelp@micrel.com or (408) 955-1690
PACKAGE/ORDERING INFORMATION
VEE
D4
D5
D6
D7
D3
D2
D1
VCC
SETMAX
SETMIN
LEN
VEE
/CASCADE
CASCADE
/EN
VEE
D0
VCC
Q
/Q
VCC
VCC
NC
D8
D9
D10
IN
/IN
VBB
VEF
VCF
32 31 30 29 28 27 26 25
910111213141516
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
32-Pin TQFP (T32-1)
FUNCTIONAL BLOCK DIAGRAM
512
GD
0
1
256
GD
0
1
128
GD
0
1
64
GD
0
1
32
GD
0
1
16
GD
D[9:0]
LEN
IN
/IN
/EN
SETMIN
SETMAX
D[10]
0
1
8
GD
0
1
4
GD
0
1
2
GD
0
1
1
GD
0
1
1
GD
Q
/Q
0
1
CASCADE
/CASCADE
10-bit
Latch
Latch
V
BB
V
CF
V
EF
Ordering Information(1)
Package Operating Package Lead
Part Number Type Range Marking Finish
SY100EP195VTI T32-1 Industrial SY100EP195V Sn-Pb
SY100EP195VTITR
(2)
T32-1 Industrial SY100EP195V Sn-Pb
SY100EP195VTG(3) T32-1 Industrial SY100EP195V with Pb-Free
Pb-Free bar-line indicator NiPdAu
SY100EP195VTGTR(2, 3) T32-1 Industrial SY100EP195V with Pb-Free
Pb-Free bar-line indicator NiPdAu
Notes:
1. Contact factory for die availability. Dice are guaranteed at TA = 25°C, DC Electricals only.
2. Tape and Reel.
3. Pb-Free package is recommended for new designs.
3
ECL Pro®
SY100EP195V
Micrel, Inc.
M9999-120505
hbwhelp@micrel.com or (408) 955-1690
PIN DESCRIPTION
Pin Number Pin Name Pin Function
23, 25, 26, 27, 29, D[0:9] CMOS, ECL, or TTL Select Inputs: These digital control signals adjust the amount of
30, 31, 32, 1, 2 delay from IN to Q. Please refer to the “Ac Electrical Table” (page 7) and Table 7 (page
17) for delay values. Figure 9 shows how to interface these inputs to various logic family
standards. These inputs default to logic low when left unconnected. Bit 0 is the least
significant bit, and bit 9 is the most significant bit.
3D[10] CMOS, ECL, or TTL Select Input: This input latches just like D[0:9] does. It drives the
CASCADE, /CASCADE differential pair. Use only when cascading two or more
SY100EP195V to extend the range of delays required.
4, 5 IN, /IN ECL Input: This is the signal to be delayed. If this input pair is left unconnected, this is
equivalent to a logic low input.
6 VBB Voltage Output: When using a single-ended logic source for IN and /IN, connect the
unused input of the differential pair to this pin. This pin can also re-bias AC-coupled inputs
to IN and /IN. When used, de-couple this pin to VCC through an 0.01µF capacitor. Limit
current sinking or sourcing to 0.5mA or less.
7VEF Voltage Output: Connect this pin to VCF when the D inputs are ECL. Refer to the
“Digital
Control Logic Standard”
section of the
“Functional Description”
to interface the D inputs to
CMOS or TTL.
8 VCF Voltage Input: The voltage at this pin sets the logic transition threshold for the D inputs.
9, 24, 28 VEE Most Negative Supply: Supply ground for PECL systems.
10 LEN ECL Control Input: When logic low, the D inputs flow through. Any changes to the D inputs
reflect in the delay between IN, /IN and Q, /Q. When logic high, the logic values at D are
latched, and these latched bits determine the delay.
11 SETMIN ECL Control Input: When logic high, the contents of the D register are reset. This sets the
delay to the minimum possible, equivalent to D[0:9] being set to 0000000000. When logic
low, the value of the D register, or the logic value of SETMAX determines the delay from
IN, /IN to Q, /Q. This input defaults to logic low when left unconnected.
12 SETMAX ECL Control Input: When logic high and SETMIN is logic low, the contents of the D
register are set high, and the delay is set to one step greater than the maximum possible
with D[0:9] set to 1111111111. When logic low, the value of the D register, or the logic
value of SETMIN determines the delay from IN, /IN to Q, /Q. This input defaults to logic
low when left unconnected.
13, 18, 19, 22 VCC Most Positive Supply: Supply ground for NECL systems. Bypass to VEE with 0.1µF and
0.01µF low ESR capacitors.
15, 14 CASCADE, 100 ECL Outputs: These outputs are used when cascading two or more SY100EP195V to
/CASCADE extend the delay range required.
16 /EN ECL Control Input: When set active low, Q, /Q are a delayed version of IN, /IN. When set
inactive high, IN, /IN are gated such that Q, /Q become a differential logic low. This input
defaults to logic low when left unconnected.
20, 21 Q, /Q 100k ECL Outputs: This signal pair is the delayed version of IN, /IN.
17 NC No Connect: Leave this pin unconnected.
4
ECL Pro®
SY100EP195V
Micrel, Inc.
M9999-120505
hbwhelp@micrel.com or (408) 955-1690
Absolute Maximum Ratings(1)
Supply Voltage (VCC)
PECL Mode (VEE=0V) ............................. –0.5V to +6.0V
Supply Voltage (VEE)
NECL Mode (VCC=0V) ............................ +0.5V to –6.0V
Any Input Voltage (VIN)
PECL Mode ....................................... –0.5V to VCC+0.5V
NECL Mode ....................................... +0.5V to VEE–0.5V
ECL Output Current (IOUT)
Continuous ............................................................. 50mA
Surge .................................................................... 100mA
IBB Sink/Source Current .......................................... ±0.5mA
Lead Temperature (soldering, 20 sec.) ................... +260°C
Storage Temperature (TS) ....................... –65°C to +150°C
ESD Rating(3) ........................................................... >1.5kV
Operating Ratings(2)
Supply Voltage (VCC)
PECL Mode (VEE=0V) ............................. +3.0V to +5.5V
Supply Voltage (VEE)
NECL Mode (VCC=0V) ............................ –3.0V to –5.5V
Ambient Temperature (TA) ......................... –40°C to +85°C
Package Thermal Resistance
TQFP-32 (θJA)
Still-air ............................................................. 50°C/W
500lfpm............................................................ 42°C/W
TQFP-32 (θJC) ..................................................... 20°C/W
TA = –40°C to +85°C.
Symbol Parameter Condition Min Typ Max Units
VCC Power Supply Voltage (PECL) 3.0 3.3 3.6 V
4.5 5.0 5.5 V
VEE Power Supply Voltage (NECL) –3.6 –3.3 –3.0 V
–5.5 –5.0 –4.5 V
IEE Power Supply Current(4) No load, over supply voltage 150 175 mA
Notes:
1. Permanent device damage may occur if absolute maximum ratings are exceeded. This is a stress rating only and functional operation is not implied
at conditions other than those detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.
2. The data sheet limits are not guaranteed if the device is operated beyond the operating ratings.
3. Devices are ESD sensitive. Handling precautions recommended.
4. Required 500lfpm air flow when using +5V or –5V power supply.
DC ELECTRICAL CHARACTERISTICS
5
ECL Pro®
SY100EP195V
Micrel, Inc.
M9999-120505
hbwhelp@micrel.com or (408) 955-1690
VCC = 3.3V, VEE = 0V; TA = –40°C to +85°C.(5, 6)
Symbol Parameter Condition Min Typ Max Units
VOH Output HIGH Voltage Figures 2, 3, 6 2155 2280 2405 mV
VOL Output LOW Voltage Figures 2, 3, 6 1355 1480 1605 mV
VIH Input HIGH Voltage Figures 1, 4
PECL 2075 2420 mV
CMOS 1815 mV
TTL 2000 mV
VIL Input LOW Voltage Figures 1, 4
PECL 1355 1675 mV
CMOS 1485 mV
TTL 800 mV
VBB Output Voltage Reference 1775 1875 1975 mV
VCF Input Select Voltage 1610 1720 1825 mV
VEF Mode Connection 1900 2000 2100 mV
VIHCMR Input HIGH Voltage Common Figure 5 2.0 3.3 V
Mode Range(7)
IIH Input HIGH Current 150 µA
IIL Input LOW Current
IN 0.5 µA
/IN –150 µA
Notes:
5. Device is guaranteed to meet the DC specifications, shown in the table below, after thermal equilibrium has been established. The device is tested in
a socket such that transverse airflow of ≥ 500lfpm is maintained.
6. Input and output parameters vary 1:1 with VCC. VEE can vary +0.3V to –2.2V.
7. VIHCMR maximum varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal.
LVPECL DC ELECTRICAL CHARACTERISTICS (100kEP)
6
ECL Pro®
SY100EP195V
Micrel, Inc.
M9999-120505
hbwhelp@micrel.com or (408) 955-1690
VCC = 5.0V, VEE = 0V; TA = –40°C to +85°C.(8, 9)
Symbol Parameter Condition Min Typ Max Units
VOH Output HIGH Voltage Figures 2, 3, 6 3855 3980 4105 mV
VOL Output LOW Voltage Figures 2, 3, 6 3055 3180 3305 mV
VIH Input HIGH Voltage Figures 1, 4
PECL 3775 4120 mV
CMOS 2750 mV
TTL 2000 mV
VIL Input LOW Voltage Figures 1, 4
PECL 3055 3375 mV
CMOS 2250 mV
TTL 800 mV
VBB Output Voltage Reference 3475 3575 3675 mV
VIHCMR Input HIGH Voltage Common Figure 5 2.0 5.0 V
Mode Range(10)
IIH Input HIGH Current 150 µA
IIL Input LOW Current
IN 0.5 µA
/IN –150 µA
PECL DC ELECTRICAL CHARACTERISTICS (100kEP)
VCC = 0V, VEE = –5.5V to –3.0V; TA = –40°C to +85°C.(8)
Symbol Parameter Condition Min Typ Max Units
VOH Output HIGH Voltage Figures 2, 3 –1145 –1020 –895 mV
VOL Output LOW Voltage Figures 2, 3 –1945 –1820 –1695 mV
VIH Input HIGH Voltage NECL Figures 1, 4 –1225 –880 mV
VIL Input LOW Voltage NECL Figures 1, 4 –1945 –1625 mV
VBB Output Voltage Reference –1525 –1425 –1325 mV
VIHCMR Input HIGH Voltage Common Figure 5 VEE+2.0 0.0 V
Mode Range(11)
IIH Input HIGH Current 150 µA
IIL Input LOW Current
IN 0.5 µA
/IN –150 µA
Notes:
8. Device is guaranteed to meet the DC specifications, shown in the table above, after thermal equilibrium has been established. The device is tested in
a socket such that transverse airflow of ≥500lfpm is maintained.
9. Input and output parameters vary 1:1 with VCC. VEE can vary +2.0V to –0.5V.
10. VIHCMR maximum varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal.
11. VIHCMR minimum varies 1:1 with VEE. The VIHCMR range is referenced to the most positive side of the differential input signal.
NECL DC ELECTRICAL CHARACTERISTICS (100kEP)
7
ECL Pro®
SY100EP195V
Micrel, Inc.
M9999-120505
hbwhelp@micrel.com or (408) 955-1690
AC ELECTRICAL CHARACTERISTICS
VCC = 3.0 to 5.5V, VEE = 0V or VCC = 0V, VEE = –3.0 to –5.5V; TA = –40°C to +85°C.(12, 13)
TA = –40°CT
A = +25°CT
A = +85°C
Symbol Parameter Min Typ Max Min Typ Max Min Typ Max Unit
fMAX Maximum Frequency(14) 2.5 2.5 2.5 GHz
tPD Propagation Delay
IN to Q; D[0-10]=0 1650 2000 2450 1800 2050 2600 1950 2250 2750 ps
IN to Q; D[0-10]=1023 9500 11500 13500 9800 12200 14000 10600 13300 15800 ps
/EN to Q: D[0-10]=0 1600 2150 2600 1800 2300 2800 2000 2500 3000 ps
D10 to CASCADE 300 420 500 325 450 550 325 525 625 ps
tRANGE Programmable Range
tPD(max)-tPD(min) 7850 9450 8200 10000 8850 10950 ps
∆tStep Delay(15)
D0 High 9 10 10 ps
D1 High 25 26 27 ps
D2 High 42 42 43 ps
D3 High 75 80 81 ps
D4 High 142 143 150 ps
D5 High 296 300 310 ps
D6 High 532 540 565 ps
D7 High 1080 1095 1140 ps
D8 High 2100 2150 2250 ps
D9 High 4250 4300 4500 ps
Lin Linearity(16) ±10 ±10 ±10 %LSB
tSKEW Duty Cycle Skew(17)
tPHL-tPLH 25 ps
tSSetup Time D to LEN 200 0 200 0 200 0 ps
D to IN(18) 300 140 300 160 300 180 ps
/EN to IN(19) 300 150 300 170 300 180 ps
tHHold Time LEN to D 200 60 200 100 200 80 ps
IN to /EN(20) 400 250 400 280 400 300 ps
tRRelease Time
/EN to IN(21) 500 ps
SETMAX to LEN 400 200 400 250 400 300 ps
SETMIN to LEN 350 275 350 200 350 335 ps
tJIT Cycle-to-Cycle Jitter(22) 0.2 < 1 0.2 < 1 0.2 < 1 psRMS
VPP Input Voltage Swing (Differential) 150 800 1200 150 800 1200 150 800 1200 mV
trOutput Rise/Fall Time
tf20% to 80% (Q) 180 250 210 300 230 325 ps
20% to 80% (CASCADE) 180 250 210 300 230 325 ps
Notes:
12. AC characteristics are guaranteed by design and characterization.
13. Measured using 750mV source, 50% duty cycle clock source, RL = 50Ω to VCC – 2V.
14. Refer to
“Typical Operating Characteristics”
for output swing performance.
15. The delays of the individual bits are cumulative.
16. Linearity is the deviation from the ideal delay.
17. Duty cycle skew guaranteed only for differential operation measured from the crosspoint of the input edge to the crosspoint of the corresponding
output edge.
18. Setup time defines the amount of time prior to an edge on IN, /IN that the D[0:9] bits must be set to guarantee the new delay will occur for that edge.
19. Setup time is the minimum that /EN must be asserted prior to the next transition of IN, /IN to prevent an output response greater than ±75mV to that
IN, /IN transition.
20. Hold time is the minimum time that /EN must remain asserted after a negative going IN or a positive going /IN to prevent an output response greater
than ±75mV to that IN, /IN transition.
21. Release time is the minimum time that /EN must be deasserted prior to the next IN, /IN transition to ensure an output response that meets the
specified IN to Q propagation delay and transition times.
22. This is the amount of generated jitter added to an otherwise jitter free clock signal, going from IN, /IN to Q, /Q, where the clock may be any frequency
between 0.0 and 2.5GHz.
8
ECL Pro®
SY100EP195V
Micrel, Inc.
M9999-120505
hbwhelp@micrel.com or (408) 955-1690
TYPICAL OPERATING CHARACTERISTICS
0
100
200
300
400
500
600
700
800
0 500 1000 1500 2000 2500 3000
OUTPUT SWING (mV)
FREQUENCY (MHz)
Q, /Q Output Swing
vs. Frequency
0
20
40
60
80
100
120
140
160
180
-40 -20 0 20 40 60 80 100
I
EE
(mA)
TEMPERATURE (°C)
Supply Current
vs. Temperature
V
CC
= 5.5V
V
CC
= 5.0V
V
CC
= 3.3V
V
CC
= 3.0V
9
ECL Pro®
SY100EP195V
Micrel, Inc.
M9999-120505
hbwhelp@micrel.com or (408) 955-1690
V
CC
IN
/IN
5;-2'#8
75k
9
75k
9
75k
9
Figure 1a. Differential Input Structure
VCC
/EN
LEN
SETMIN
SETMAX
D[0:10]
SY100EP195V
VBB
75k
9
Figure 1b. Single-Ended Input Structure
V
CC
Q, CASCADE
/Q, /CASCADE
SY100EP195V
Figure 2. Emitter Output Structure
VOH
VOL
0V
Q
/Q
CASCADE
/CASCADE
Figure 3a. Output Levels, PECL, LVPECL
VOH
VOL
0V
Q
/Q
CASCADE
/CASCADE
Figure 3b. Output Levels, NECL
10
ECL Pro®
SY100EP195V
Micrel, Inc.
M9999-120505
hbwhelp@micrel.com or (408) 955-1690
Invalid
Invalid
Invalid
V
CC
V
IH(MAX)
V
IH(MIN)
V
IL(MAX)
Logic High
V
IL(MIN)
0V
Logic Low
Figure 4a. Input Levels, PECL
Invalid
Invalid
Invalid
VCC
VIH(MIN)
VIL(MAX)
Logic High
0V
Logic Low
Figure 4b. Input Levels, CMOS, TTL
Invalid
Invalid
Invalid
0V
VIH(MAX)
VIH(MIN)
VIL(MAX)
Logic High
VIL(MIN)
VEE
Logic Low
Figure 4c. Input Levels, NECL
V
IHCMR
0V
IN
/IN
Figure 5a. Input Common Mode, PECL, LVPECL
V
IHCMR
V
IHCMR
0V
IN
/IN
Figure 5b. Input Common Mode, NECL
11
ECL Pro®
SY100EP195V
Micrel, Inc.
M9999-120505
hbwhelp@micrel.com or (408) 955-1690
R2
82Ω
R2
82Ω
ZO = 50Ω
ZO = 50Ω
+3.3V +3.3V
Vt = VCC –2V
R1
130Ω
R1
130Ω
+3.3V
Figure 6a. Parallel Termination—Thevenin Equivalent
Note:
1. For +5.0V systems: R1 = 82Ω, R2 = 130Ω.
Z = 50Ω
Z = 50Ω
50Ω50Ω
50Ω
+3.3V +3.3V
“Source” “Destination”
RbC1 (optional)
0.01µF
Figure 6b. Three-Resistor “Y-Termination”
Notes:
1. Power-saving alternative to Thevenin termination.
2. Place termination resistors as close to destination inputs as possible.
3. Rb resistor sets the DC bias voltage, equal to Vt. For +3.3V systems Rb = 46Ω to 50Ω. For +5V systems, Rb = 110Ω.
+3.3V +3.3V
Z
O
= 50Ω
R2
82Ω
+3.3V +3.3V
R1
130Ω
R1
130Ω
R2
82Ω
V
t
= V
CC
–2V
Q
/Q
50Ω
+3.3V
0.01µF
V
BB
Figure 6c. Terminating Unused I/O
Notes:
1. Unused output (/Q) must be terminated to balance the output.
2. Micrel's differential I/O logic devices include a VBB reference pin .
3. Connect unused input through 50Ω to VBB. Bypass with a 0.01µF capacitor to VCC, not GND, as PECL is referenced to VCC.
TERMINATING PECL
12
ECL Pro®
SY100EP195V
Micrel, Inc.
M9999-120505
hbwhelp@micrel.com or (408) 955-1690
PECL
Output
V
BB
V
CC
SY100EP195V
IN
0.01µF
/IN
Figure 7a. Interfacing to a
Single-Ended PECL Signal
PECL
Output
V
BB
V
CC
5;-2'#8
IN
0.01µF
/IN
Figure 7b. Interfacing to and Inverting
a Single-Ended PECL Signal
5050
V
BB
5;-2'#8
IN
/IN
V
CC
0.01µF
Figure 8. Re-Biasing an
AC-Coupled Signal
5;-2'#8
Figure 9a. Connecting PECL Signals
to the D Inputs
5;-2'#8
Figure 9b. Connecting LVPECL Signals
to the D Inputs
5;-2'#8
Figure 9c. Connecting CMOS Signals to the D Inputs
Note: VCF and VEF are not connected.
VEF
NC
VCF
SY100EP195V
D[0:10]
TTL
Inputs
VCC +3.3V
VEE 0V0V
1.5k
9
Figure 9d. Connecting TTL Signals
to the D Inputs, with VCC = 3.3V
5;-2'#8
9
Figure 9e. Connecting TTL Signals
to the D Inputs, with VCC = 5.0V
13
ECL Pro®
SY100EP195V
Micrel, Inc.
M9999-120505
hbwhelp@micrel.com or (408) 955-1690
FUNCTIONAL DESCRIPTION
SY100EP195V is a programmable delay line, varying the
delay of a PECL or NECL input signal by any amount between
about 2.2ns and 12.2ns. A 10-bit digital control register affords
delay steps of approximately 10ps.
SY100EP195V implements the delay using a multiplexer
chain and a set of fixed delay elements. Under digital control,
various subsets of the delay elements are included in the
signal chain. To simplify interfacing, the 10-bit digital delay
control word interfaces to PECL, CMOS, or TTL interface
standards.
Since multiplexers must appear in the delay path,
SY100EP195V has a minimum delay of about 2.2ns. Delays
below this value are not possible. In addition, when cascading
multiple SY100EP195V to extend the delay range, the
minimum delay is about 2.2ns times the number of
SY100EP195V in cascade. An eleventh control bit, D[10],
along with the CASCADE and /CASCADE outputs and the
SETMIN and SETMAX inputs, simplifies the task of cascading.
Signal Path Logic Standard
The signal path, from IN, /IN to Q, /Q, interfaces to PECL,
LVPECL, or NECL signals, as shown in Table 6. The choice
of signal path logic standard may limit possible choices for
the delay control inputs, D.
Input Enable
The /EN input gates the signal at IN, /IN. When disabled,
the input is effectively gated out, just as if a logic low was
being provided to SY100EP195V.
/EN Value at Q, /Q
LIN, /IN Delayed
HLogic Low Delayed
Table 1. /EN Truth Table
Digital Control Latch
SY100EP195V can capture the digital delay control word
into its internal 11-bit latch, 10 bits for D[0:9], and an extra bit
for the D[10] cascade control. The LEN input controls the
action of this latch, as per Table 2.
Note that the LEN input is always PECL, LVPECL, or
NECL, the same as the IN, /IN signal pair. The 11-bit delay
control word, however, may also be CMOS or TTL.
LEN Latch Action
LPass Through D[0:10]
HLatch D[0:10]
Table 2. LEN Truth Table
The nominal delay value is based on the binary value in
D[0:9], where D[0] is the least significant bit, and D[9] is the
most significant bit. This delay from IN, /IN to Q, /Q is about:
∆t 2200 10 value D 9:0 , ps=+×
[]
()
Digital Control Logic Standard
When used in systems where VEE connects to ground,
SY100EP195V may interface either to PECL, CMOS, or TTL
on its D[0:10] inputs. To this end, the VCF pin sets the threshold
at which the D inputs switch between logic low and logic high.
As shown in Table 3, connecting VCF to VEF sets the
threshold to PECL (if VCC is 5V) or LVPECL (if VCC is 3.3V).
Leaving VCF and VEF open yields a threshold suitable for
detecting CMOS output logic levels. Leaving VEF open and
connecting VCF to a 1.5V source allows the D inputs to accept
TTL signals.
Logic Standard VCF Connection
ECL, PECL VEF
CMOS No Connect
TTL 1.5V Source
Table 3. Digital Control Standard Truth Table
If a 1.5V source is not available, connecting VCF to VEE
through an appropriate resistor will bias VCF at about 1.5V.
The value of this resistor depends on the VCC supply, as
indicated in Table 4.
VCC Resistor Value
3.3V 1.5kΩ
5.0V 500Ω
Table 4. Resistor Values for TTL Input
Cascade Logic
SY100EP195V is designed to ease cascading multiple
devices in order to achieve a greater delay range. The SETMIN
and SETMAX pins accomplish this, as set out in the
applications section below. SETMIN and SETMAX override
the delay by changing the value in the D latch register. Table
5 lists the action of these pins.
SETMIN SETMAX Nominal Delay (ps)
LLAs per D Latch
LH2200 + 10 × 1024
HL 2200
HHNot Allowed
Table 5. SETMIN and SETMAX Action
14
ECL Pro®
SY100EP195V
Micrel, Inc.
M9999-120505
hbwhelp@micrel.com or (408) 955-1690
Signal Path Logic Standard VCC VEE Delay Control Input Choices
PECL +4.5V to +5.5V 0V PECL, CMOS, TTL
LVPECL +3.0V to +3.6V 0V LVPECL, CMOS, TTL
NECL 0V –3.0 to –5.5V NECL
Table 6. Signal Path Logic Standard
15
ECL Pro®
SY100EP195V
Micrel, Inc.
M9999-120505
hbwhelp@micrel.com or (408) 955-1690
For best performance, use good high frequency layout
techniques, filter VCC supplies, and keep ground connections
short. Use multiple vias where possible. Also, use controlled
impedance transmission lines to interface with the
SY100EP195V data inputs and outputs.
VBB Supply
The VBB pin is an internally generated supply, and is
available for use only by the SY100EP195V. When unused,
this pin should be left unconnected. The two common uses
for VBB are to handle a single-ended PECL input, and to re-
bias inputs for AC-coupling applications.
If IN, /IN is driven by a single-ended output, VBB is used
to bias the unused input. Please refer to Figures 7. The
PECL signal driving SY100EP195V may optionally be
inverted in this case.
When the signal is AC-coupled, VBB is used, as shown
in Figure 8, to re-bias IN, /IN. This ensures that
SY100EP195V inputs are within its acceptable common
mode range.
In all cases, VBB current sinking our sourcing must be
limited to 0.5mA or less.
APPLICATIONS INFORMATION
IN
/IN
Q
/Q
IN
/IN
Q
/Q
D[9:0]
SY100EP195V SY100EP195V
#2 #1
SETMIN
SETMAX
/CASCADE
CASCADE
D[10]
C[9:0]
C[10]
Control Word (11bits)
Figure 10a. Cascading Two SY100EP195V
IN
/IN
Q
/Q
IN
/IN
Q
/Q
SY100EP195V SY100EP195V
#3 #2
SETMIN
SETMAX
SETMIN
SETMAX
/CASCADE
CASCADE
D[10]
C[11]
IN
/IN
Q
/Q
D[9:0]
SY100EP195V
#1
/CASCADE
CASCADE
D[10]
C[9:0]
C[10]
Control Word (12bits)
Figure 10b. Cascading Three SY100EP195V
Setting D Input Logic Thresholds
As explained earlier, in all designs where the
SY100EP195V VEE supply is at zero volts, the D inputs
may accommodate CMOS and TTL level signals, as well as
PECL or LVPECL. Figures 9 show how to connect VCF and
VEF for all possible cases.
Cascading
Two or more SY100EP195V may be cascaded, in order
to extend the range of delays permitted. Each additional
SY100EP195V adds about 2200ps to the minimum delay,
and adds another 10240ps to the delay range.
Internal cascade circuitry has been included in the
SY100EP195V. Using this internal circuitry, SY100EP195V
may be cascaded without any external gating.
Examples of cascading 2, 3, or 4 SY100EP195V appear
in Figures 10. Table 7 lists the nominal delay for all the
cases that appear in Figures 10.
16
ECL Pro®
SY100EP195V
Micrel, Inc.
M9999-120505
hbwhelp@micrel.com or (408) 955-1690
IN
/IN
Q
/Q
IN
/IN
Q
/Q
SY100EP195V SY100EP195V
SETMIN
SETMAX
SETMIN
SETMAX
/CASCADE
CASCADE
D[10]
C[11]
IN
/IN
Q
/Q
SY100EP195V
SETMIN
SETMAX
IN
/IN
Q
/Q
D[9:0]
SY100EP195V
/CASCADE
CASCADE
D[10]
C[9:0]
C[10]
Control Word (12bits)
Figure 10c. Cascading Four SY100EP195V
Part Number Function Data Sheet Link
SY100EP196VTI 3.3V/5V Programmable Delay Chip http://www.micrel.com/product-info/products/sy100ep196v.shtml
with Fine Tune Control
SY55856UHI 2.5V/3.3V 2.5GHz Differential 2-Channel http://www.micrel.com/product-info/products/sy55856u.shtml
Precision CML Delay Line
RELATED PRODUCT AND SUPPORT DOCUMENTATION
17
ECL Pro®
SY100EP195V
Micrel, Inc.
M9999-120505
hbwhelp@micrel.com or (408) 955-1690
Control Inputs Nominal Delay (ps)
D[11] D[10] D[9:0] One Chip Two Chips Three Chips Four Chips
000000000000 2,200 4,400 6,600 8,800
000000000001 2,210 4,410 6,610 8,810
000000000010 2,220 4,420 6,620 8,820
000000000100 2,240 4,440 6,640 8,840
000000001000 2,280 4,480 6,680 8,880
000000010000 2,360 4,560 6,760 8,960
000000100000 2,520 4,720 6,920 9,120
000001000000 2,840 5,040 7,240 9,440
000010000000 3,480 5,680 7,880 10,080
000100000000 4,760 6,960 9,160 11,360
001000000000 7,320 9,520 11,720 13,920
001111111111 12,430 14,630 16,830 19,030
010000000000 14,640 16,840 19,040
010000000001 14,650 16,850 19,050
010000000010 14,660 16,860 19,060
010000000100 14,680 16,880 19,080
010000001000 14,720 16,920 19,120
010000010000 14,800 17,000 19,200
010000100000 14,960 17,160 19,360
010001000000 15,280 17,480 19,680
010010000000 15,920 18,120 20,320
010100000000 17,200 19,400 21,600
011000000000 19,760 21,960 24,160
011111111111 24,870 27,070 29,270
100000000000 27,080 29,280
100000000001 27,090 29,290
100000000010 27,100 29,300
100000000100 27,120 29,320
100000001000 27,160 29,360
100000010000 27,240 29,440
100000100000 27,400 29,600
100001000000 27,720 29,920
100010000000 28,360 30,560
100100000000 29,640 31,840
101000000000 32,200 34,400
101111111111 37,310 39,510
110000000000 27,080 39,520
110000000001 27,090 39,530
110000000010 27,100 39,540
110000000100 27,120 39,560
110000001000 27,160 39,600
110000010000 27,240 39,680
110000100000 27,400 39,840
110001000000 27,720 40,160
110010000000 28,360 40,800
110100000000 29,640 42,080
111000000000 32,200 44,640
111111111111 37,310 49,750
Table 7. List of Nominal Delay Values for Cascaded SY100EP195V
18
ECL Pro®
SY100EP195V
Micrel, Inc.
M9999-120505
hbwhelp@micrel.com or (408) 955-1690
Rev. 01
32-PIN TQFP (T32-1)
MICREL, INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131 USA
TEL + 1 (408) 944-0800 FAX + 1 (408) 474-1000 WEB http://www.micrel.com
The information furnished by Micrel in this data sheet is believed to be accurate and reliable. However, no responsibility is assumed by Micrel for its use.
Micrel reserves the right to change circuitry and specifications at any time without notification to the customer.
Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a product can
reasonably be expected to result in personal injury. Life support devices or systems are devices or systems that (a) are intended for surgical implant into
the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant injury to the user. A Purchaser’s
use or sale of Micrel Products for use in life support appliances, devices or systems is at Purchaser’s own risk and Purchaser agrees to fully indemnify
Micrel for any damages resulting from such use or sale.
© 2005 Micrel, Incorporated.
