LMH2180 www.ti.com SNAS419D - JANUARY 2008 - REVISED MARCH 2013 LMH2180 75 MHz Dual Clock Buffer Check for Samples: LMH2180 FEATURES DESCRIPTION * The LMH2180 is a high speed dual clock buffer designed for portable communications and applications requiring multiple accurate multi-clock systems. The LMH2180 integrates two 75 MHz low noise buffers with independent shutdown pins into a small package. The LMH2180 ensures superb system operation between the baseband and the oscillator signal path by eliminating crosstalk between the multiple clock signals. 1 2 * * * * * * * * * * * * (Typical Values are: VSUPPLY = 2.7V and CL = 10 pF, unless Otherwise Specified.) Small Signal Bandwidth 78 MHz Supply Voltage Range 2.4V to 5V Phase Noise (VIN = 1 VPP, fC = 38.4 MHz, f = 1 kHz) -123 dBc/Hz Slew Rate 106 V/s Total Supply Current 2.3 mA Shutdown Current 30 A Rail-to-Rail Input and Output Individual Buffer Enable Pins Rapid Ton Technology Crosstalk Rejection Circuitry Packages: - 8-Pin WSON, Solder Bump and no Pullback - 8-Bump DSBGA Temperature Range -40C to 85C Unique technology and design provides the LMH2180 with the ability to accurately drive both large capacitive and resistive loads. Low supply current combined with shutdown pins for each channel means the LMH2180 is ideal for battery powered applications. This part does not use an internal ground reference, thus providing additional system flexibility. The flexible buffers provide system designers the capacity to manage complex clock signals in the latest wireless applications. Each buffer delivers 106 V/s internal slew rate with independent shutdown and duty cycle precision. Each input is internally biased to 1V, removing the need for external resistors. Both channels have rail-to-rail inputs and outputs, a gain of one, and are AC coupled with the use of one capacitor. APPLICATIONS * * * * * 3G Mobile Applications WLAN-WiMAX Modules TD_SCDMA Multi-Mode MP3 and Camera GSM Modules Oscillator Modules Replacing a discrete buffer solution with the LMH2180 provides many benefits: simplified board layout, minimized parasitic components, simplified BOM, design durability across multiple applications, simplification of clock paths, and the ability to reduce the number of clock signal generators in the system. The LMH2180 is produced in the tiny packages minimizing the required PCB space. TYPICAL APPLICATION VCC Enable 1 EN1 8 IN1 2 VCTCXO 1 7 1 OUT1 LOAD1 Rload 10 nF Cload LMH2180 IN2 3 EN2 4 6 2 OUT2 LOAD2 Rload Cload 5 Enable 2 GND 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright (c) 2008-2013, Texas Instruments Incorporated LMH2180 SNAS419D - JANUARY 2008 - REVISED MARCH 2013 www.ti.com CONNECTION DIAGRAMS Top View Top View EN1 VDD 1 IN 1 2 8 ENABLE 1 7 OUT 1 VDD A3 IN1 A2 IN2 A1 DEVICE CODE IN 2 3 6 OUT 2 ENABLE 2 4 5 VSS B3 B1 C3 OUT1 C2 OUT2 C1 VSS EN2 Figure 1. 8-Pin WSON Package See Package Number NGW0008A or NGQ0008A Figure 2. 8-Bump DSBGA Package See Package Number YFQ0008AAA PIN DESCRIPTIONS Pin No. WSON Pin No. DSBGA 1 A3 VDD Voltage supply connection 2 A2 IN 1 Input 1 3 A1 IN 2 Input 2 4 B1 ENABLE 2 5 C1 VSS 6 C2 OUT 2 Output 2 7 C3 OUT 1 Output 1 8 B3 ENABLE 1 Pin Name Description Enable buffer 2 Ground connection Enable buffer 1 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. ABSOLUTE MAXIMUM RATINGS + (1) (2) - Supply Voltages (V - V ) 5.5V ESD Tolerance Human Body (3) Machine Model 2000V (4) 200V Charged Device Model 1000V -65C to 150C Storage Temperature Range Junction Temperature (5) 150C Soldering Information Infrared or Convection (35 sec.) (1) (2) (3) (4) (5) 2 235C "Absolute Maximum Ratings" indicate limits beyond which damage to the device may occur, including inoperability and degradation of the device reliability and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or other conditions beyond those indicated in the Recommended Operating Conditions is not implied. The Recommended Operating Conditions indicate conditions at which the device is functional and the device should not be operated beyond such conditions. All voltages are measured with respect to the ground pin, unless otherwise specified. If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and specifications. Human body model, applicable std. JESD22-A114C. Machine model, applicable std. JESD22-A115-A. The maximum power dissipation must be derated at elevated temperatures and is dictated by TJ(MAX), JA , and the ambient temperature TA. The maximum allowable power dissipation is PDMAX = (TJMAX - TA) / JA or the number given in the Absolute Maximum Ratings, whichever is lower. Submit Documentation Feedback Copyright (c) 2008-2013, Texas Instruments Incorporated Product Folder Links: LMH2180 LMH2180 www.ti.com SNAS419D - JANUARY 2008 - REVISED MARCH 2013 OPERATING RATINGS (1) Supply Voltage (V+ - V-) 2.4V to 5.0V (2) (3) -40C to 85C Temperature Range Package Thermal Resistance (2) (3) 8-Pin WSON (JA) 217C/W 8-Bump DSBGA (JA) (1) (2) (3) 90C/W "Absolute Maximum Ratings" indicate limits beyond which damage to the device may occur, including inoperability and degradation of the device reliability and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or other conditions beyond those indicated in the Recommended Operating Conditions is not implied. The Recommended Operating Conditions indicate conditions at which the device is functional and the device should not be operated beyond such conditions. All voltages are measured with respect to the ground pin, unless otherwise specified. The Electrical Characteristics tables show performance under the specified Recommended Operating Conditions except as otherwise modified by the Electrical Characteristics Conditions and/or Notes. Typical values represent typical performance as measured by production tests. Individual parts may vary. The maximum power dissipation must be derated at elevated temperatures and is dictated by TJ(MAX), JA , and the ambient temperature TA. The maximum allowable power dissipation is PDMAX = (TJMAX - TA) / JA or the number given in the Absolute Maximum Ratings, whichever is lower. 2.7V ELECTRICAL CHARACTERISTICS Unless otherwise specified, all limits are specified for TA = 25C, VDD = 2.7V, VSS = 0V, VCM = 1V, Enable1,2 = VDD, CL = 10 pF, RL = 30 k, Load is connected to VSS, CCOUPLING = 10 nF. Boldface limits apply at temperature range extremes of operating condition. (1) Parameter Test Conditions Min (2) Typ (3) Max (2) Units Frequency Domain Response SSBW Small Signal Bandwidth VIN = 100 mVPP; -3 dB LSBW Large Signal Bandwidth GFN Gain Flatness < 0.1 dB 78 MHz VIN = 1.0 VPP; -3 dB 60 MHz f > 100 kHz 4.9 MHz VIN = 1 VPP, fC = 38.4 MHz, f = 1 kHz -123 dBc/Hz VIN = 1 VPP, fC = 38.4 MHz, f = 10 kHz -132 dBc/Hz Distortion and Noise Performance n Phase Noise en Input-Referred Voltage Noise f = 1 MHz, RSOURCE = 50 13 nV/Hz ISOLATION Output to Input f = 1 MHz, RSOURCE = 50 84 dB CT Crosstalk Rejection f = 38.4 MHz, VIN = 1 VPP 41 dB 0.1 VPP Step (10-90%) 6 ns Time Domain Response tr Rise Time tf Fall Time 5 ns ts Settling Time to 0.1% 1 VPP Step 120 ns OS Overshoot 0.1 VPP Step 37 % VIN = 2 VPP 106 V/s Enable1,2 = VDD ; No Load 2.3 2.7 2.9 mA Enable1 = VDD , Enable2 = VSS , No Load 1.3 1.5 1.6 mA Enable1,2 = VSS ; No Load 30 41 46 A SR Slew Rate (4) Static DC Performance IS Supply Current PSRR (1) (2) (3) (4) Power Supply Rejection Ratio DC (3.0V to 5.0V) 65 64 68 dB The Electrical Characteristics tables show performance under the specified Recommended Operating Conditions except as otherwise modified by the Electrical Characteristics Conditions and/or Notes. Typical values represent typical performance as measured by production tests. Individual parts may vary. Datasheet min/max limits are specified by test or statistical analysis. Typical values represent the most likely parametric norms at TA = +25C, and at the Recommended Operation Conditions at the time of product characterization. Slew rate is the average of the rising and falling slew rates. Submit Documentation Feedback Copyright (c) 2008-2013, Texas Instruments Incorporated Product Folder Links: LMH2180 3 LMH2180 SNAS419D - JANUARY 2008 - REVISED MARCH 2013 www.ti.com 2.7V ELECTRICAL CHARACTERISTICS (continued) Unless otherwise specified, all limits are specified for TA = 25C, VDD = 2.7V, VSS = 0V, VCM = 1V, Enable1,2 = VDD, CL = 10 pF, RL = 30 k, Load is connected to VSS, CCOUPLING = 10 nF. Boldface limits apply at temperature range extremes of operating condition.(1) Parameter Test Conditions ACL Small Signal Voltage Gain VOS Output Offset Voltage TC VOS Temperature Coefficient Output Offset Voltage (5) ROUT Output Resistance Min VIN = 0.2 VPP (2) 0.95 Typ (3) Max (2) 1.05 V/V -0.5 17 18 mV 2.8 f = 100 kHz Units 1.0 V/C 0.6 f = 38.4 MHz 166 disabled High Impedance Miscellaneous Performance RIN Input Resistance per Buffer CIN Input Capacitance per Buffer ZIN Input Impedance VO ISC Enable = VDD 137 Enable = VSS 137 Enable = VDD 1.3 Enable = VSS 1.3 f = 38.4 MHz, Enable = VDD 4.5 f = 38.4 MHz, Enable = VSS 4.2 Output Swing Positive VIN = VDD Output Swing Negative VIN = VSS Output Short-Circuit Current (6) (7) 2.66 2.65 Sourcing, VIN = VDD, VOUT = VSS -21 -18 -25 Sinking, VIN = VSS, VOUT = VDD 23 15 25 V mV mA Enable High Active Minimum Voltage 1.2 Enable Low Inactive Maximum Voltage 0.6 (7) k 35 37 19 Ven_lmax (6) pF 2.69 Ven_hmin (5) k V Average Temperature Coefficient is determined by dividing the changing in a parameter at temperature extremes by the total temperature change. Short-Circuit test is a momentary test. Continuous short circuit operation at elevated ambient temperature can result in exceeding the maximum allowed junction temperature of 150C. Positive current corresponds to current flowing into the device. 5V ELECTRICAL CHARACTERISTICS Unless otherwise specified, all limits are specified for TA = 25C, VDD = 5V, VSS = 0V, VCM = 1V, Enable1,2 = VDD, CL = 10 pF, RL = 30 k, Load is connected to VSS, CCOUPLING = 10 nF. Boldface limits apply at temperature range extremes of operating condition. (1) Parameter Test Conditions Min (2) Typ (3) Max (2) Units Frequency Domain Response SSBW Small Signal Bandwidth VIN = 100 mVPP; -3 dB 87 MHz LSBW Large Signal Bandwidth VIN = 1.0 VPP; -3 dB 68 MHz GFN Gain Flatness < 0.1 dB f > 100 kHz 25 MHz VIN = 1 VPP, fC = 38.4 MHz, f = 1 kHz -123 dBc/Hz VIN = 1 VPP, fC = 38.4 MHz, f = 10 kHz -132 dBc/Hz Distortion and Noise Performance n (1) (2) (3) 4 Phase Noise The Electrical Characteristics tables show performance under the specified Recommended Operating Conditions except as otherwise modified by the Electrical Characteristics Conditions and/or Notes. Typical values represent typical performance as measured by production tests. Individual parts may vary. Datasheet min/max limits are specified by test or statistical analysis. Typical values represent the most likely parametric norms at TA = +25C, and at the Recommended Operation Conditions at the time of product characterization. Submit Documentation Feedback Copyright (c) 2008-2013, Texas Instruments Incorporated Product Folder Links: LMH2180 LMH2180 www.ti.com SNAS419D - JANUARY 2008 - REVISED MARCH 2013 5V ELECTRICAL CHARACTERISTICS (continued) Unless otherwise specified, all limits are specified for TA = 25C, VDD = 5V, VSS = 0V, VCM = 1V, Enable1,2 = VDD, CL = 10 pF, RL = 30 k, Load is connected to VSS, CCOUPLING = 10 nF. Boldface limits apply at temperature range extremes of operating condition.(1) Parameter Test Conditions Min (2) Typ (3) Max (2) Units en Input-Referred Voltage Noise f = 1 MHz, RSOURCE = 50 12 nV/Hz ISOLATION Output to Input f = 1 MHz, RSOURCE = 50 84 dB CT Crosstalk Rejection f = 38.4 MHz, PIN = 0 dBm 59 dB 0.1 VPP Step (10-90%) 6 ns Time Domain Response tr Rise Time tf Fall Time 6 ns ts Settling Time to 0.1% 1 VPP Step 70 ns OS Overshoot 0.1VPP Step 13 % SR Slew Rate VIN = 2 VPP 124 V/s Enable1,2 = VDD ; No Load 3.4 4.0 4.1 mA Enable1 = VDD, Enable2 = VSS ; No Load 1.8 2.2 2.3 mA Enable1,2 = VSS ; No Load 32 43 49 A (4) Static DC Performance IS Supply Current PSRR Power Supply Rejection Ratio DC (3.0V to 5.0V) ACL Small Signal Voltage Gain VIN = 0.2 VPP VOS Output Offset Voltage TC VOS Temperature Coefficient Output Offset Voltage (5) ROUT Output Resistance 65 64 68 0.95 1.0 1.05 V/V -1.4 21 22 mV dB 2.4 f = 100 kHz 0.5 f = 38.4 MHz 126 disabled V/C High Impedance Miscellaneous Performance RIN Input Resistance per Buffer CIN Input Capacitance per Buffer ZIN Input Impedance VO ISC Enable = VDD 138 Enable = VSS 138 Enable = VDD 1.3 Enable = VSS 1.3 f = 38.4 MHz, Enable = VDD 4.3 f = 38.4 MHz, Enable = VSS 4.2 Output Swing Positive VIN = VDD Output Swing Negative VIN = VSS Output Short-Circuit Current (6) (7) 4.96 4.95 10 Sourcing, VIN = VDD, VOUT = VSS -80 -62 -90 Sinking, VIN = VSS, VOUT = VDD 60 43 65 Enable High Active Minimum Voltage 1.2 Enable Low Inactive Maximum Voltage 0.6 (7) k V 35 50 mV mA Ven_lmax (6) pF 4.99 Ven_hmin (4) (5) k V Slew rate is the average of the rising and falling slew rates. Average Temperature Coefficient is determined by dividing the changing in a parameter at temperature extremes by the total temperature change. Short-Circuit test is a momentary test. Continuous short circuit operation at elevated ambient temperature can result in exceeding the maximum allowed junction temperature of 150C. Positive current corresponds to current flowing into the device. Submit Documentation Feedback Copyright (c) 2008-2013, Texas Instruments Incorporated Product Folder Links: LMH2180 5 LMH2180 SNAS419D - JANUARY 2008 - REVISED MARCH 2013 www.ti.com BLOCK DIAGRAM ENABLE 1 VDD IN 1 1 OUT 1 IN 2 2 OUT 2 ENABLE 2 6 VSS Submit Documentation Feedback Copyright (c) 2008-2013, Texas Instruments Incorporated Product Folder Links: LMH2180 LMH2180 www.ti.com SNAS419D - JANUARY 2008 - REVISED MARCH 2013 TYPICAL PERFORMANCE CHARACTERISTICS TA = 25C, VDD = 2.7V, VSS = 0V, Enable1,2 = VDD, CL = 10 pF, RL = 30 k and CCOUPLING = 10 nF, unless otherwise specified. Frequency Response Phase Response 6 0 2.7V 3 -30 2.7V 0 5V PHASE () GAIN (dB) -60 -3 5V -6 -90 -120 -9 -150 -12 VIN = 0.1VPP VIN = 0.1VPP -15 100k 1M 10M -180 100k 100M FREQUENCY (Hz) 1M 10M 100M FREQUENCY (Hz) Figure 3. Figure 4. Frequency Response Over Temperature Frequency Response Over Temperature 6 6 -40C -40C 3 3 25C 0 0 GAIN (dB) GAIN (dB) 85C -3 -6 85C -6 -9 -12 25C -3 -9 -12 V = 0.1V IN PP VS = 5V -15 100k 1M VIN = 0.1VPP VS = 2.7V -15 100k 1M 10M 100M FREQUENCY (Hz) 10M FREQUENCY (Hz) Figure 5. Figure 6. Phase Response Over Temperature Phase Response Over Temperature 0 0 -40C -40C -30 -30 -60 -60 25C -90 25C PHASE () PHASE () 100M 85C -120 -150 -90 85C -120 -150 -180 -180 -210 VIN = 0.1VPP VS = 2.7V -240 100k 1M -210 VIN = 0.1VPP VS = 5V -240 100k 1M 10M 100M FREQUENCY (Hz) 10M 100M FREQUENCY (Hz) Figure 7. Figure 8. Submit Documentation Feedback Copyright (c) 2008-2013, Texas Instruments Incorporated Product Folder Links: LMH2180 7 LMH2180 SNAS419D - JANUARY 2008 - REVISED MARCH 2013 www.ti.com TYPICAL PERFORMANCE CHARACTERISTICS (continued) TA = 25C, VDD = 2.7V, VSS = 0V, Enable1,2 = VDD, CL = 10 pF, RL = 30 k and CCOUPLING = 10 nF, unless otherwise specified. Large Signal Bandwidth Gain Flatness < 0.1 dB (GFN) 6 0.5 2.7V 0.4 NORMALIZED GAIN (dB) 3 GAIN (dB) 0 -3 5V -6 -9 -12 1M 10M 2.7V 0.2 0.1 0 -0.1 5V -0.2 -0.3 -0.4 VIN = 1VPP -15 100k 0.3 VIN = 0.1VPP -0.5 100k 100M 1M FREQUENCY (Hz) Figure 9. Phase Noise -70 180 -80 160 PHASE NOISE (dBc/Hz) VOLTAGE NOISE (nV/iHz) Voltage Noise 2.7V 120 100 80 60 5V -90 -100 -120 -130 1k 10k 100k Mean 3 -150 10 1M 1k 10k 100k Figure 11. Figure 12. Isolation Output to Input vs. Frequency Crosstalk Rejection vs. Frequency 100 1M 100 90 90 CROSSTALK REJECTION (dB) 2.7V 80 70 60 50 5V 40 30 20 10 0 100k 100 OFFSET FREQUENCY (Hz) FREQUENCY (Hz) ISOLATION (dB) Limited number of samples -110 -140 20 80 5V 70 60 50 2.7V 40 30 20 10 1M 10M 100M FREQUENCY (Hz) PIN = 0 dBm 0 100k 1M 10M 100M FREQUENCY (Hz) Figure 13. 8 VS = 2.7 or 5V VIN = 1VPP fC = 38.4 MHz 40 0 100 100M Figure 10. 200 140 10M FREQUENCY (Hz) Figure 14. Submit Documentation Feedback Copyright (c) 2008-2013, Texas Instruments Incorporated Product Folder Links: LMH2180 LMH2180 www.ti.com SNAS419D - JANUARY 2008 - REVISED MARCH 2013 TYPICAL PERFORMANCE CHARACTERISTICS (continued) TA = 25C, VDD = 2.7V, VSS = 0V, Enable1,2 = VDD, CL = 10 pF, RL = 30 k and CCOUPLING = 10 nF, unless otherwise specified. Transient Response Positive 1100 Transient Response Negative 1100 2.7V 1075 1075 1050 1050 1025 5V VOUT (mV) VOUT (mV) VIN = 0.1VPP 1000 975 950 1025 1000 5V 975 950 2.7V 925 900 0 20 40 60 80 VIN = 0.1VPP 925 100 120 140 160 900 0 20 40 TIME (ns) Small Signal Pulse Response Small Signal Pulse Response 1100 VS = 2.7V VIN = 0.1VPP f = 1 MHz VS = 5V VIN = 0.1VPP f = 1 MHz 1050 VOUT (mV) VOUT (mV) 1050 1000 950 1000 950 200 400 600 800 900 0 1000 200 TIME (ns) 400 600 800 1000 TIME (ns) Figure 17. Figure 18. Large Signal Response Large Signal Response 2.0 2.0 VS = 2.7V VIN = 1VPP f = 1 MHz VS = 5V VIN = 1VPP f = 1 MHz 1.5 VOUT (V) 1.5 VOUT (V) 100 120 140 160 Figure 16. 1100 1.0 0.5 0.0 0 80 TIME (ns) Figure 15. 900 0 60 1.0 0.5 200 400 600 800 0.0 0 1000 TIME (ns) 200 400 600 800 1000 TIME (ns) Figure 19. Figure 20. Submit Documentation Feedback Copyright (c) 2008-2013, Texas Instruments Incorporated Product Folder Links: LMH2180 9 LMH2180 SNAS419D - JANUARY 2008 - REVISED MARCH 2013 www.ti.com TYPICAL PERFORMANCE CHARACTERISTICS (continued) TA = 25C, VDD = 2.7V, VSS = 0V, Enable1,2 = VDD, CL = 10 pF, RL = 30 k and CCOUPLING = 10 nF, unless otherwise specified. ISUPPLY vs. VSUPPLY ISUPPLY vs. VSUPPLY 4.0 2.4 3.5 2.1 1.8 -40C 2.5 ISUPPLY (mA) ISUPPLY (mA) 3.0 25C 2.0 85C 1.5 1.5 85C 0.9 1.0 0.6 0.5 2.5 3.0 3.5 4.0 4.5 0.0 2.0 5.5 2.5 3.0 4.5 Figure 21. Figure 22. ISUPPLY vs. VSUPPLY PSRR vs. Frequency 80 5.0 5.5 5V 70 60 85C 50 PSRR (dB) -40C 25C 2.7V 40 30 20 No Load Enable1,2 = VSS 05 2.0 2.5 3.0 3.5 4.0 4.5 5.0 10 0 10 5.5 100 VSUPPLY (V) 1k 10k 100k 1M FREQUENCY (Hz) Figure 23. Figure 24. VOS vs. ROUT vs. Frequency VSUPPLY 2.0 300 1.5 250 5V 85C 25C 0.5 2.7V 200 ROUT (O) VOS (mV) 4.0 VSUPPLY (V) 35 40 30 35 30 25 25 20 20 15 15 10 5 10 0 1.0 3.5 VSUPPLY (V) 40 0 5.0 No Load Enable1 = VDD Enable2 = VSS 0.3 No Load Enable1,2 = VDD 0.0 2.0 ISUPPLY (eA) -40C 25C 1.2 -40C 0.0 -0.5 150 100 -1.0 50 -1.5 -2.0 2.5 3.0 3.5 4.0 4.5 0 10k 5.0 VSUPPLY (V) 1M 10M 100M FREQUENCY (Hz) Figure 25. 10 100k Figure 26. Submit Documentation Feedback Copyright (c) 2008-2013, Texas Instruments Incorporated Product Folder Links: LMH2180 LMH2180 www.ti.com SNAS419D - JANUARY 2008 - REVISED MARCH 2013 TYPICAL PERFORMANCE CHARACTERISTICS (continued) TA = 25C, VDD = 2.7V, VSS = 0V, Enable1,2 = VDD, CL = 10 pF, RL = 30 k and CCOUPLING = 10 nF, unless otherwise specified. Input Impedance vs. Frequency 150 VOUT vs. IOUT (Sourcing) 1.5 2.7V -40C 25C 120 90 VOUT (V) IMPEDANCE (kO) 1.0 5V 60 85C 0.5 0.0 30 Open Input VS = 2.7V 0 10k 100k 1M 10M -0.5 -25 100M -20 -15 Figure 27. Figure 28. VOUT vs. IOUT (Sourcing) VOUT vs. IOUT (Sinking) 3.0 1.5 3.0 2.5 VOUT (V) VOUT (V) 1.0 0.5 25C 0.0 85C 85C VS = 2.7V 2.5 2.0 2.0 25C 1.5 1.5 1.0 1.0 0.5 -0.5 0.0 0.5 Open Input VS = 5V -1.0 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 0.0 -40C 0 5 10 15 20 25 IOUT (mA) IOUT (mA) Figure 29. Figure 30. VOUT vs. IOUT (Sinking) ISC Sourcing vs. VSUPPLY Over Temperature 3.0 0 Open Input VS = 5V 85C -20 2.0 -40 85C 25C 1.5 25C ISC (mA) VOUT (V) 0 Open Input -40C -60 1.0 -80 -40C 0.5 0.0 0 -5 IOUT (mA) FREQUENCY (Hz) 2.5 -10 10 20 30 40 50 -100 60 -120 2.5 -40C VIN = VDD VOUT = VSS 3.0 3.5 4.0 4.5 5.0 VSUPPLY (V) IOUT (mA) Figure 31. Figure 32. Submit Documentation Feedback Copyright (c) 2008-2013, Texas Instruments Incorporated Product Folder Links: LMH2180 11 LMH2180 SNAS419D - JANUARY 2008 - REVISED MARCH 2013 www.ti.com TYPICAL PERFORMANCE CHARACTERISTICS (continued) TA = 25C, VDD = 2.7V, VSS = 0V, Enable1,2 = VDD, CL = 10 pF, RL = 30 k and CCOUPLING = 10 nF, unless otherwise specified. ISC Sinking vs. VSUPPLY Over Temperature 100 ISUPPLY vs. VENABLE 2.5 VIN = VSS 100 2.5 VOUT = VDD 2.0 2.0 -40C 60 60 40 40 ISUPPLY (mA) ISC (mA) 80 80 85C 25C 20 85C 1.5 1.5 25C 1.0 1.0 -40C 0.5 20 0 0.5 0.0 No Load VS = 2.7V 0.0 0 2.5 3.0 3.5 4.0 4.5 0.0 5.0 VSUPPLY (V) 0.4 0.8 1.2 1.6 2.0 VENABLE (V) Figure 33. Figure 34. ISUPPLY vs. VENABLE 4.0 -40C 25C 3.5 85C ISUPPLY (mA) 3.0 2.5 2.0 1.5 1.0 0.5 0.0 0.0 No Load VS = 5V 0.4 0.8 1.2 1.6 2.0 VENABLE (V) Figure 35. 12 Submit Documentation Feedback Copyright (c) 2008-2013, Texas Instruments Incorporated Product Folder Links: LMH2180 LMH2180 www.ti.com SNAS419D - JANUARY 2008 - REVISED MARCH 2013 APPLICATION INFORMATION GENERAL The LMH2180 is designed to minimize the effects of spurious signals from the base chip to the oscillator. Also the influence of varying load resistance and capacitance to the oscillator is minimized, while the drive capability is increased. The inputs of the LMH2180 are internally biased at 1V, making AC coupling possible without external bias resistors. To optimize current consumption, a buffer that is not in use can be disabled by connecting it's enable pin to VSS. The LMH2180 has no internal ground reference; therefore, either single or split supply configurations can be used. The LMH2180 is an easy replacement for discrete circuitry. It simplifies board layout and minimizes the effect of layout related parasitic components. INPUT CONFIGURATION The internal 1V input biasing allows AC coupling of the input signal. This biasing avoids the use of external resistors, as depicted in Figure 36. The biasing prevents a large DC load at the oscillators output that creates a load impedance and may affect it's oscillating frequency. As a result of this biasing, the maximum amplitude of the AC signal is 2VPP. The coupling capacitance C1 should be large enough to let the AC signal pass. This is a unity gain buffer with rail-to-rail inputs and outputs. VDD ENABLE 1V OSC IN OUT C1 VSS Figure 36. Input Configuration FREQUENCY PULLING Frequency pulling is the frequency variation of an oscillator caused by a varying load. In the typical application, the load of the oscillator is a fixed capacitor (C1) in series with the input impedance of the buffer. To keep the input impedance as constant as possible, the input is biased at 1V, even when the part is disabled. A simplified schematic of the input configuration is shown in Figure 36. ISOLATION AND CROSSTALK Output to input isolation prevents the clock signal of the oscillator from being affected by spurious signals generated by the digital blocks behind the output buffer. See Figure 13. A block diagram of the isolation is shown in Figure 37. Crosstalk rejection between buffers prevents signals from affecting each other. Figure 37 shows a Baseband IC and a Bluetooth module as an example. See Figure 14 for more information. Submit Documentation Feedback Copyright (c) 2008-2013, Texas Instruments Incorporated Product Folder Links: LMH2180 13 LMH2180 SNAS419D - JANUARY 2008 - REVISED MARCH 2013 www.ti.com LMH2180 Base band IC OUT 1 IN 1 C1 Isolation Crosstalk VCTCXO Bluetooth IN 2 OUT 2 WLAN Figure 37. Isolation Block Diagram DRIVING CAPACITIVE LOADS Each buffer can drive a capacitive load. Be aware that every capacitor directly connected to the output becomes part of the loop of the buffer. In most applications the load consists of the capacitance of copper tracks and the input capacitance of the application blocks. Capacitance reduces the gain/phase margin and decreases the stability. This leads to peaking in the frequency response and in extreme situations oscillations can occur. To drive a large capacitive load it is recommended to include a series resistor between the buffer and the load capacitor. The best value for this isolation resistance can be found by experimentation. The LMH2180 datasheet reflects measurements with capacitive loads of 10 pF at the output of the buffers. Most common applications will probably use a lower capacitive load, which will result in lower peaking and significantly greater bandwidth, see Figure 38. 9 33 pF 22 pF 10 pF 6 3 GAIN (dB) 0 -3 6.8 pF No C Load -6 -9 -12 -15 VIN = 0.1VPP -18 1M 10M 100M FREQUENCY (Hz) Figure 38. Bandwidth and Peaking PHASE NOISE A clock buffer adds noise to the clock signal. This noise causes uncertainty in the phase of the clock signal. This uncertainty is described by jitter (time domain) or phase noise (frequency domain). Communication systems, such as Wireless LAN, require a low jitter/phase noise clock signal to obtain a low Bit Error Rate. Figure 39 shows the frequency domain representation of a clock signal with frequency fC. Without Phase Noise the entire signal power would only be located at the frequency fC. Phase Noise spreads some of the power to adjacent frequencies. Phase Noise is usually specified in dBc/Hz at a given frequency offset f from the carrier, where dBc is the power level in dB relative to the carrier. The noise power is measured within a 1 Hz bandwidth. 14 Submit Documentation Feedback Copyright (c) 2008-2013, Texas Instruments Incorporated Product Folder Links: LMH2180 LMH2180 SNAS419D - JANUARY 2008 - REVISED MARCH 2013 POWER (dB) www.ti.com Phase Noise (dBc/Hz) Af BW = 1 Hz fC FREQUENCY (Hz) Figure 39. Phase Noise Figure 40 shows the setup used to measure the LMH2180 phase noise. The clock driving the LMH2180 is a state of the art 38.4MHz TCXO. Both the TCXO phase noise and the phase noise at the LMH2180 output were measured. At offset frequencies of 1 kHz and higher from the carrier, the TCXO phase noise is sufficiently low to accurately calculate the LMH2180 contribution to the phase noise at the output. The LMH6559, whose phase noise contribution can be neglected, is used to drive the 50 input impedance of the Signal Source Analyzer. LAYOUT DESIGN RECOMMENDATION Careful consideration during circuit design and PCB layout will eliminate problems and will optimize the performance of the LMH2180. It is best to have the same ground plane on the PCB for all decoupling and other ground connections. To ensure a clean supply voltage it is best to place decoupling capacitors close to the LMH2180, between VDD and VSS. Another important issue is the value of the components, because this also determines the sensitivity to disturbances. Resistor values have to be low enough to avoid a significant noise contribution and large enough to avoid a significant increase in power consumption while loading inputs or outputs to heavily. VDD Enable 1 EN1 8 E5052A/B LMH6559 1 10 nF IN1 2 TCXO 7 1 OUT1 50: 10 nF LMH2180 38.4 MHz Signal Source Analyzer IN2 3 EN2 4 Buffer for driving 50: 6 2 5 Enable 2 VSS Figure 40. Measurement Setup Submit Documentation Feedback Copyright (c) 2008-2013, Texas Instruments Incorporated Product Folder Links: LMH2180 15 LMH2180 SNAS419D - JANUARY 2008 - REVISED MARCH 2013 www.ti.com REVISION HISTORY Changes from Revision C (March 2013) to Revision D * 16 Page Changed layout of National Data Sheet to TI format .......................................................................................................... 15 Submit Documentation Feedback Copyright (c) 2008-2013, Texas Instruments Incorporated Product Folder Links: LMH2180 PACKAGE OPTION ADDENDUM www.ti.com 11-Apr-2018 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (C) Device Marking (4/5) LMH2180SD/NOPB ACTIVE WSON NGQ 8 1000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 2180S LMH2180SDE/NOPB ACTIVE WSON NGQ 8 250 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 2180S LMH2180TM/NOPB ACTIVE DSBGA YFQ 8 250 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM A LMH2180TMX/NOPB ACTIVE DSBGA YFQ 8 3000 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM A (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 11-Apr-2018 continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 30-Apr-2018 TAPE AND REEL INFORMATION *All dimensions are nominal Device LMH2180SD/NOPB Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 3.3 1.0 8.0 12.0 Q1 WSON NGQ 8 1000 178.0 12.4 LMH2180SDE/NOPB WSON NGQ 8 250 178.0 12.4 3.3 3.3 1.0 8.0 12.0 Q1 LMH2180TM/NOPB DSBGA YFQ 8 250 178.0 8.4 1.35 1.35 0.76 4.0 8.0 Q1 LMH2180TMX/NOPB DSBGA YFQ 8 3000 178.0 8.4 1.35 1.35 0.76 4.0 8.0 Q1 Pack Materials-Page 1 3.3 B0 (mm) PACKAGE MATERIALS INFORMATION www.ti.com 30-Apr-2018 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LMH2180SD/NOPB WSON NGQ 8 1000 210.0 185.0 35.0 LMH2180SDE/NOPB WSON NGQ 8 250 210.0 185.0 35.0 LMH2180TM/NOPB DSBGA YFQ 8 250 210.0 185.0 35.0 LMH2180TMX/NOPB DSBGA YFQ 8 3000 210.0 185.0 35.0 Pack Materials-Page 2 MECHANICAL DATA YFQ0008xxx D 0.6000.075 E TMD08XXX (Rev A) D: Max = 1.24 mm, Min = 1.18 mm E: Max = 1.24 mm, Min = 1.18 mm 4215076/A NOTES: A. All linear dimensions are in millimeters. Dimensioning and tolerancing per ASME Y14.5M-1994. B. This drawing is subject to change without notice. www.ti.com 12/12 PACKAGE OUTLINE NGQ0008A WSON - 0.8 mm max height SCALE 4.000 PLASTIC SMALL OUTLINE - NO LEAD 3.1 2.9 B A PIN 1 INDEX AREA 3.1 2.9 C 0.8 0.7 SEATING PLANE 0.08 C 1.6 0.1 (0.1) TYP SYMM EXPOSED THERMAL PAD 0.05 0.00 4 5 SYMM 9 2X 1.5 2 0.1 8 1 6X 0.5 8X PIN 1 ID 8X 0.5 0.3 0.3 0.2 0.1 0.05 C A B C 4214922/A 03/2018 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance. www.ti.com EXAMPLE BOARD LAYOUT NGQ0008A WSON - 0.8 mm max height PLASTIC SMALL OUTLINE - NO LEAD (1.6) SYMM 8X (0.6) 1 8 (0.75) 8X (0.25) 9 SYMM (2) 6X (0.5) 5 4 (R0.05) TYP ( 0.2) VIA TYP (2.8) LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:20X 0.07 MIN ALL AROUND 0.07 MAX ALL AROUND EXPOSED METAL EXPOSED METAL SOLDER MASK OPENING METAL METAL UNDER SOLDER MASK NON SOLDER MASK DEFINED (PREFERRED) SOLDER MASK OPENING SOLDER MASK DEFINED SOLDER MASK DETAILS 4214922/A 03/2018 NOTES: (continued) 4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271). 5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown on this view. It is recommended that vias under paste be filled, plugged or tented. www.ti.com EXAMPLE STENCIL DESIGN NGQ0008A WSON - 0.8 mm max height PLASTIC SMALL OUTLINE - NO LEAD 8X (0.6) SYMM 9 METAL TYP 8 1 8X (0.25) SYMM (1.79) 6X (0.5) 5 4 (R0.05) TYP (1.47) (2.8) SOLDER PASTE EXAMPLE BASED ON 0.1 mm THICK STENCIL EXPOSED PAD 9: 82% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE SCALE:20X 4214922/A 03/2018 NOTES: (continued) 6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. www.ti.com IMPORTANT NOTICE Texas Instruments Incorporated (TI) reserves the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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