LMH2180
VCC
GND
10 nF
EN1
IN1
IN2
EN2
1
1
2
3
4
5
6
7
8
OUT1
OUT2
VCTCXO
Rload
Rload
Cload
Cload
LOAD1
LOAD2
Enable 1
2
Enable 2
LMH2180
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SNAS419D –JANUARY 2008–REVISED MARCH 2013
LMH2180 75 MHz Dual Clock Buffer
Check for Samples: LMH2180
1FEATURES DESCRIPTION
The LMH2180 is a high speed dual clock buffer
2• (Typical Values are: VSUPPLY = 2.7V and CL= 10 designed for portable communications and
pF, unless Otherwise Specified.) applications requiring multiple accurate multi-clock
• Small Signal Bandwidth 78 MHz systems. The LMH2180 integrates two 75 MHz low
• Supply Voltage Range 2.4V to 5V noise buffers with independent shutdown pins into a
small package. The LMH2180 ensures superb
• Phase Noise (VIN =1VPP, fC= 38.4 MHz, Δf=1 system operation between the baseband and the
kHz) −123 dBc/Hz oscillator signal path by eliminating crosstalk between
• Slew Rate 106 V/μsthe multiple clock signals.
• Total Supply Current 2.3 mA Unique technology and design provides the LMH2180
• Shutdown Current 30 µA with the ability to accurately drive both large
capacitive and resistive loads. Low supply current
• Rail-to-Rail Input and Output combined with shutdown pins for each channel
• Individual Buffer Enable Pins means the LMH2180 is ideal for battery powered
• Rapid Ton Technology applications. This part does not use an internal
• Crosstalk Rejection Circuitry ground reference, thus providing additional system
flexibility.
• Packages: The flexible buffers provide system designers the
– 8-Pin WSON, Solder Bump and no Pullback capacity to manage complex clock signals in the
– 8-Bump DSBGA latest wireless applications. Each buffer delivers 106
• Temperature Range −40°C to 85°C V/μs internal slew rate with independent shutdown
and duty cycle precision. Each input is internally
APPLICATIONS biased to 1V, removing the need for external
resistors. Both channels have rail-to-rail inputs and
• 3G Mobile Applications outputs, a gain of one, and are AC coupled with the
• WLAN–WiMAX Modules use of one capacitor.
• TD_SCDMA Multi-Mode MP3 and Camera Replacing a discrete buffer solution with the
• GSM Modules LMH2180 provides many benefits: simplified board
layout, minimized parasitic components, simplified
• Oscillator Modules BOM, design durability across multiple applications,
simplification of clock paths, and the ability to reduce
the number of clock signal generators in the system.
The LMH2180 is produced in the tiny packages
minimizing the required PCB space.
TYPICAL APPLICATION
1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date. Copyright © 2008–2013, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
IN2
EN2
VSS
OUT1
EN1
VDD
IN1 OUT2
A3 B3 C3
C2
C1B1A1
A2
VDD
IN 1
IN 2
ENABLE 2
ENABLE 1
OUT 1
OUT 2
VSS
1
2
3
4 5
6
7
8
DEVICE
CODE
LMH2180
SNAS419D –JANUARY 2008–REVISED MARCH 2013
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CONNECTION DIAGRAMS
Top View Top View
Figure 1. 8-Pin WSON Package Figure 2. 8-Bump DSBGA Package
See Package Number NGW0008A or NGQ0008A See Package Number YFQ0008AAA
PIN DESCRIPTIONS
Pin No. Pin No. Pin Name Description
WSON DSBGA
1 A3 VDD Voltage supply connection
2 A2 IN 1 Input 1
3 A1 IN 2 Input 2
4 B1 ENABLE 2 Enable buffer 2
5 C1 VSS Ground connection
6 C2 OUT 2 Output 2
7 C3 OUT 1 Output 1
8 B3 ENABLE 1 Enable buffer 1
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
ABSOLUTE MAXIMUM RATINGS (1)(2)
Supply Voltages (V+– V−) 5.5V
ESD Tolerance
Human Body (3) 2000V
Machine Model (4) 200V
Charged Device Model 1000V
Storage Temperature Range −65°C to 150°C
Junction Temperature (5) 150°C
Soldering Information
Infrared or Convection (35 sec.) 235°C
(1) “Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur, including inoperability and degradation of
the device reliability and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or
other conditions beyond those indicated in the Recommended Operating Conditions is not implied. The Recommended Operating
Conditions indicate conditions at which the device is functional and the device should not be operated beyond such conditions. All
voltages are measured with respect to the ground pin, unless otherwise specified.
(2) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and
specifications.
(3) Human body model, applicable std. JESD22–A114C.
(4) Machine model, applicable std. JESD22–A115–A.
(5) The maximum power dissipation must be derated at elevated temperatures and is dictated by TJ(MAX),θJA , and the ambient temperature
TA. The maximum allowable power dissipation is PDMAX = (TJMAX −TA) / θJA or the number given in the Absolute Maximum Ratings,
whichever is lower.
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OPERATING RATINGS (1)
Supply Voltage (V+– V−) 2.4V to 5.0V
Temperature Range (2)(3) −40°C to 85°C
Package Thermal Resistance (2)(3)
8-Pin WSON (θJA) 217°C/W
8-Bump DSBGA (θJA) 90°C/W
(1) “Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur, including inoperability and degradation of
the device reliability and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or
other conditions beyond those indicated in the Recommended Operating Conditions is not implied. The Recommended Operating
Conditions indicate conditions at which the device is functional and the device should not be operated beyond such conditions. All
voltages are measured with respect to the ground pin, unless otherwise specified.
(2) The Electrical Characteristics tables show performance under the specified Recommended Operating Conditions except as otherwise
modified by the Electrical Characteristics Conditions and/or Notes. Typical values represent typical performance as measured by
production tests. Individual parts may vary.
(3) The maximum power dissipation must be derated at elevated temperatures and is dictated by TJ(MAX),θJA , and the ambient temperature
TA. The maximum allowable power dissipation is PDMAX = (TJMAX −TA) / θJA or the number given in the Absolute Maximum Ratings,
whichever is lower.
2.7V ELECTRICAL CHARACTERISTICS
Unless otherwise specified, all limits are specified for TA= 25°C, VDD = 2.7V, VSS = 0V, VCM = 1V, Enable1,2 = VDD, CL= 10
pF, RL= 30 kΩ, Load is connected to VSS, CCOUPLING = 10 nF. Boldface limits apply at temperature range extremes of
operating condition.(1)
Parameter Test Conditions Min (2) Typ (3) Max (2) Units
Frequency Domain Response
SSBW Small Signal Bandwidth VIN = 100 mVPP;−3 dB 78 MHz
LSBW Large Signal Bandwidth VIN = 1.0 VPP;−3 dB 60 MHz
GFN Gain Flatness < 0.1 dB f > 100 kHz 4.9 MHz
Distortion and Noise Performance
φnPhase Noise VIN = 1 VPP, fC= 38.4 MHz, Δf = 1 kHz −123 dBc/Hz
VIN = 1 VPP, fC= 38.4 MHz, Δf = 10 −132 dBc/Hz
kHz
enInput-Referred Voltage Noise f = 1 MHz, RSOURCE = 50Ω13 nV/√Hz
ISOLATION Output to Input f = 1 MHz, RSOURCE = 50Ω84 dB
CT Crosstalk Rejection f = 38.4 MHz, VIN = 1 VPP 41 dB
Time Domain Response
trRise Time 0.1 VPP Step (10-90%) 6 ns
tfFall Time 5 ns
tsSettling Time to 0.1% 1 VPP Step 120 ns
OS Overshoot 0.1 VPP Step 37 %
SR Slew Rate (4) VIN = 2 VPP 106 V/µs
Static DC Performance
ISSupply Current Enable1,2 = VDD ; No Load 2.7
2.3 mA
2.9
Enable1= VDD , Enable2= VSS , No 1.5
1.3 mA
Load 1.6
Enable1,2 = VSS ; No Load 41
30 μA
46
PSRR Power Supply Rejection Ratio DC (3.0V to 5.0V) 65 68 dB
64
(1) The Electrical Characteristics tables show performance under the specified Recommended Operating Conditions except as otherwise
modified by the Electrical Characteristics Conditions and/or Notes. Typical values represent typical performance as measured by
production tests. Individual parts may vary.
(2) Datasheet min/max limits are specified by test or statistical analysis.
(3) Typical values represent the most likely parametric norms at TA= +25°C, and at the Recommended Operation Conditions at the time of
product characterization.
(4) Slew rate is the average of the rising and falling slew rates.
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2.7V ELECTRICAL CHARACTERISTICS (continued)
Unless otherwise specified, all limits are specified for TA= 25°C, VDD = 2.7V, VSS = 0V, VCM = 1V, Enable1,2 = VDD, CL= 10
pF, RL= 30 kΩ, Load is connected to VSS, CCOUPLING = 10 nF. Boldface limits apply at temperature range extremes of
operating condition.(1)
Parameter Test Conditions Min (2) Typ (3) Max (2) Units
ACL Small Signal Voltage Gain VIN = 0.2 VPP 0.95 1.0 1.05 V/V
VOS Output Offset Voltage 17
-0.5 mV
18
TC VOS Temperature Coefficient Output Offset 2.8 µV/°C
Voltage (5)
ROUT Output Resistance f = 100 kHz 0.6
f = 38.4 MHz 166 Ω
disabled High Impedance
Miscellaneous Performance
RIN Input Resistance per Buffer Enable = VDD 137 kΩ
Enable = VSS 137
CIN Input Capacitance per Buffer Enable = VDD 1.3 pF
Enable = VSS 1.3
ZIN Input Impedance f = 38.4 MHz, Enable = VDD 4.5 kΩ
f = 38.4 MHz, Enable = VSS 4.2
VOOutput Swing Positive VIN = VDD 2.66 2.69 V
2.65
Output Swing Negative VIN = VSS 35
19 mV
37
ISC Output Short-Circuit Current (6)(7) Sourcing, VIN = VDD, VOUT = VSS −21 −25
−18 mA
Sinking, VIN = VSS, VOUT = VDD 23 25
15
Ven_hmin Enable High Active Minimum Voltage 1.2 V
Ven_lmax Enable Low Inactive Maximum Voltage 0.6
(5) Average Temperature Coefficient is determined by dividing the changing in a parameter at temperature extremes by the total
temperature change.
(6) Short−Circuit test is a momentary test. Continuous short circuit operation at elevated ambient temperature can result in exceeding the
maximum allowed junction temperature of 150°C.
(7) Positive current corresponds to current flowing into the device.
5V ELECTRICAL CHARACTERISTICS
Unless otherwise specified, all limits are specified for TA= 25°C, VDD = 5V, VSS = 0V, VCM = 1V, Enable1,2 = VDD, CL= 10 pF,
RL= 30 kΩ, Load is connected to VSS, CCOUPLING = 10 nF. Boldface limits apply at temperature range extremes of operating
condition.(1)
Parameter Test Conditions Min (2) Typ (3) Max (2) Units
Frequency Domain Response
SSBW Small Signal Bandwidth VIN = 100 mVPP;−3 dB 87 MHz
LSBW Large Signal Bandwidth VIN = 1.0 VPP;−3 dB 68 MHz
GFN Gain Flatness < 0.1 dB f > 100 kHz 25 MHz
Distortion and Noise Performance
φnPhase Noise VIN = 1 VPP, fC= 38.4 MHz, Δf = 1 kHz −123 dBc/Hz
VIN = 1 VPP, fC= 38.4 MHz, Δf = 10 −132 dBc/Hz
kHz
(1) The Electrical Characteristics tables show performance under the specified Recommended Operating Conditions except as otherwise
modified by the Electrical Characteristics Conditions and/or Notes. Typical values represent typical performance as measured by
production tests. Individual parts may vary.
(2) Datasheet min/max limits are specified by test or statistical analysis.
(3) Typical values represent the most likely parametric norms at TA= +25°C, and at the Recommended Operation Conditions at the time of
product characterization.
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5V ELECTRICAL CHARACTERISTICS (continued)
Unless otherwise specified, all limits are specified for TA= 25°C, VDD = 5V, VSS = 0V, VCM = 1V, Enable1,2 = VDD, CL= 10 pF,
RL= 30 kΩ, Load is connected to VSS, CCOUPLING = 10 nF. Boldface limits apply at temperature range extremes of operating
condition.(1)
Parameter Test Conditions Min (2) Typ (3) Max (2) Units
enInput-Referred Voltage Noise f = 1 MHz, RSOURCE = 50Ω12 nV/√Hz
ISOLATION Output to Input f = 1 MHz, RSOURCE = 50Ω84 dB
CT Crosstalk Rejection f = 38.4 MHz, PIN = 0 dBm 59 dB
Time Domain Response
trRise Time 0.1 VPP Step (10-90%) 6 ns
tfFall Time 6 ns
tsSettling Time to 0.1% 1 VPP Step 70 ns
OS Overshoot 0.1VPP Step 13 %
SR Slew Rate (4) VIN = 2 VPP 124 V/µs
Static DC Performance
ISSupply Current Enable1,2 = VDD ; No Load 4.0
3.4 mA
4.1
Enable1= VDD, Enable2= VSS ; No 2.2
1.8 mA
Load 2.3
Enable1,2 = VSS ; No Load 43
32 μA
49
PSRR Power Supply Rejection Ratio DC (3.0V to 5.0V) 65 68 dB
64
ACL Small Signal Voltage Gain VIN = 0.2 VPP 0.95 1.0 1.05 V/V
VOS Output Offset Voltage 21
−1.4 mV
22
TC VOS Temperature Coefficient Output Offset 2.4 µV/°C
Voltage (5)
ROUT Output Resistance f = 100 kHz 0.5
f = 38.4 MHz 126 Ω
disabled High Impedance
Miscellaneous Performance
RIN Input Resistance per Buffer Enable = VDD 138 kΩ
Enable = VSS 138
CIN Input Capacitance per Buffer Enable = VDD 1.3 pF
Enable = VSS 1.3
ZIN Input Impedance f = 38.4 MHz, Enable = VDD 4.3 kΩ
f = 38.4 MHz, Enable = VSS 4.2
VOOutput Swing Positive VIN = VDD 4.96 4.99 V
4.95
Output Swing Negative VIN = VSS 35
10 mV
50
ISC Output Short-Circuit Current (6)(7) Sourcing, VIN = VDD, VOUT = VSS −80 −90
−62 mA
Sinking, VIN = VSS, VOUT = VDD 60 65
43
Ven_hmin Enable High Active Minimum Voltage 1.2 V
Ven_lmax Enable Low Inactive Maximum Voltage 0.6
(4) Slew rate is the average of the rising and falling slew rates.
(5) Average Temperature Coefficient is determined by dividing the changing in a parameter at temperature extremes by the total
temperature change.
(6) Short−Circuit test is a momentary test. Continuous short circuit operation at elevated ambient temperature can result in exceeding the
maximum allowed junction temperature of 150°C.
(7) Positive current corresponds to current flowing into the device.
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FREQUENCY (Hz)
PHASE (°)
0
-30
-60
-90
-120
-150
-180
-210
-240
100k 1M 10M 100M
-40°C
25°C
85°C
VIN = 0.1VPP
VS = 2.7V
FREQUENCY (Hz)
PHASE (°)
0
-30
-60
-90
-120
-150
-180
-210
-240
100k 1M 10M 100M
-40°C
25°C
85°C
VIN = 0.1VPP
VS = 5V
FREQUENCY (Hz)
GAIN (dB)
6
3
0
-3
-6
-9
-12
-15
100k 1M 10M 100M
-40°C
25°C
85°C
VIN = 0.1VPP
VS = 2.7V
FREQUENCY (Hz)
GAIN (dB)
6
3
0
-3
-6
-9
-12
-15
100k 1M 10M 100M
-40°C
25°C
85°C
VIN = 0.1VPP
VS = 5V
FREQUENCY (Hz)
GAIN (dB)
6
3
0
-3
-6
-9
-12
-15
100k 1M 10M 100M
2.7V
5V
VIN = 0.1VPP
FREQUENCY (Hz)
PHASE (°)
0
-30
-60
-90
-120
-150
-180
100k 1M 10M 100M
2.7V 5V
VIN = 0.1VPP
LMH2180
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SNAS419D –JANUARY 2008–REVISED MARCH 2013
TYPICAL PERFORMANCE CHARACTERISTICS
TA= 25°C, VDD = 2.7V, VSS = 0V, Enable1,2 = VDD, CL= 10 pF, RL= 30 kΩand CCOUPLING = 10 nF, unless otherwise specified.
Frequency Response Phase Response
Figure 3. Figure 4.
Frequency Response Over Temperature Frequency Response Over Temperature
Figure 5. Figure 6.
Phase Response Over Temperature Phase Response Over Temperature
Figure 7. Figure 8.
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FREQUENCY (Hz)
ISOLATION (dB)
100
90
80
70
60
50
40
30
20
10
0
100k 1M 10M 100M
2.7V
5V
FREQUENCY (Hz)
CROSSTALK REJECTION (dB)
100
90
80
70
60
50
40
30
20
10
0
100k 1M 10M 100M
5V
2.7V
PIN = 0 dBm
FREQUENCY (Hz)
VOLTAGE NOISE (nV/íHz)
200
180
160
140
120
100
80
60
40
20
0
100 1k 10k 100k 1M
2.7V
5V
OFFSET FREQUENCY (Hz)
PHASE NOISE (dBc/Hz)
-70
-80
-90
-100
-110
-120
-130
-140
-150
10 100 1k 10k 100k 1M
fC= 38.4 MHz
VIN = 1VPP
VS= 2.7 or 5V
Mean ±3σ
Limited number
of samples
FREQUENCY (Hz)
GAIN (dB)
6
3
0
-3
-6
-9
-12
-15
100k 1M 10M 100M
2.7V
5V
VIN = 1VPP
FREQUENCY (Hz)
NORMALIZED GAIN (dB)
0.5
0.4
0.3
0.2
0.1
0
-0.1
-0.2
-0.3
-0.4
-0.5
100k 1M 10M 100M
2.7V
5V
VIN = 0.1VPP
LMH2180
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TYPICAL PERFORMANCE CHARACTERISTICS (continued)
TA= 25°C, VDD = 2.7V, VSS = 0V, Enable1,2 = VDD, CL= 10 pF, RL= 30 kΩand CCOUPLING = 10 nF, unless otherwise specified.
Large Signal Bandwidth Gain Flatness < 0.1 dB (GFN)
Figure 9. Figure 10.
Voltage Noise Phase Noise
Figure 11. Figure 12.
Isolation Output to Input Crosstalk Rejection
vs. vs.
Frequency Frequency
Figure 13. Figure 14.
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TIME (ns)
VOUT (V)
2.0
1.5
1.0
0.5
0.00 200 400 600 800 1000
VS = 2.7V f = 1 MHz
VIN = 1VPP
TIME (ns)
VOUT (V)
2.0
1.5
1.0
0.5
0.00 200 400 600 800 1000
VS = 5V f = 1 MHz
VIN = 1VPP
TIME (ns)
VOUT (mV)
1100
1050
1000
950
9000 200 400 600 800 1000
VS = 2.7V f = 1 MHz
VIN = 0.1VPP
TIME (ns)
VOUT (mV)
1100
1050
1000
950
9000 200 400 600 800 1000
VS = 5V VIN = 0.1VPP
f = 1 MHz
TIME (ns)
VOUT (mV)
1100
1075
1050
1025
1000
975
950
925
9000 20 40 60 80 100 120 140 160
2.7V
5V
VIN = 0.1VPP
TIME (ns)
VOUT (mV)
1100
1075
1050
1025
1000
975
950
925
9000 20 40 60 80 100 120 140 160
2.7V
5V
VIN = 0.1VPP
LMH2180
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SNAS419D –JANUARY 2008–REVISED MARCH 2013
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
TA= 25°C, VDD = 2.7V, VSS = 0V, Enable1,2 = VDD, CL= 10 pF, RL= 30 kΩand CCOUPLING = 10 nF, unless otherwise specified.
Transient Response Positive Transient Response Negative
Figure 15. Figure 16.
Small Signal Pulse Response Small Signal Pulse Response
Figure 17. Figure 18.
Large Signal Response Large Signal Response
Figure 19. Figure 20.
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VSUPPLY (V)
VOS (mV)
2.0
1.5
1.0
0.5
0.0
-0.5
-1.0
-1.5
-2.0
2.5 3.0 3.5 4.0 4.5 5.0
85°C 25°C
-40°C
FREQUENCY (Hz)
ROUT (Ö)
300
250
200
150
100
50
0
10k 100k 1M 10M 100M
2.7V
5V
FREQUENCY (Hz)
PSRR (dB)
80
70
60
50
40
30
20
10
0
10 100 1k 10k 100k 1M
5V
2.7V
VSUPPLY (V)
ISUPPLY (éA)
40
35
30
25
20
15
10
5
0
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
-40°C
25°C
85°C
No Load
Enable1,2 = VSS
40
35
30
25
20
15
10
05
0
VSUPPLY (V)
ISUPPLY (mA)
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
-40°C
85°C 25°C
Enable1,2 = VDD
No Load
VSUPPLY (V)
ISUPPLY (mA)
2.4
2.1
1.8
1.5
1.2
0.9
0.6
0.3
0.0
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
85°C
25°C -40°C
Enable1 = VDD
Enable2 = VSS
No Load
LMH2180
SNAS419D –JANUARY 2008–REVISED MARCH 2013
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TYPICAL PERFORMANCE CHARACTERISTICS (continued)
TA= 25°C, VDD = 2.7V, VSS = 0V, Enable1,2 = VDD, CL= 10 pF, RL= 30 kΩand CCOUPLING = 10 nF, unless otherwise specified.
ISUPPLY ISUPPLY
vs. vs.
VSUPPLY VSUPPLY
Figure 21. Figure 22.
ISUPPLY PSRR
vs. vs.
VSUPPLY Frequency
Figure 23. Figure 24.
VOS ROUT
vs. vs.
VSUPPLY Frequency
Figure 25. Figure 26.
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IOUT (mA)
VOUT (V)
3.0
2.5
2.0
1.5
1.0
0.5
0.00 10 20 30 40 50 60
85°C
25°C
-40°C
Open Input
VS = 5V
VSUPPLY (V)
ISC (mA)
0
-20
-40
-60
-80
-100
-120
2.5 3.0 3.5 4.0 4.5 5.0
85°C
25°C
-40°C
VIN = VDD
VOUT = VSS
IOUT (mA)
VOUT (V)
1.5
1.0
0.5
0.0
-0.5
-1.0
-90 -80 -70 -60 -50 -40 -30 -20 -10 0
-40°C
25°C
85°C
Open Input
VS = 5V
IOUT (mA)
VOUT (V)
3.0
2.5
2.0
1.5
1.0
0.5
0.0
0 5 10 15 20 25
85°C
25°C
-40°C
Open Input
VS = 2.7V
3.0
2.5
2.0
1.5
1.0
0.5
0.0
FREQUENCY (Hz)
IMPEDANCE (kÖ)
150
120
90
60
30
0
10k 100k 1M 10M 100M
2.7V
5V
IOUT (mA)
VOUT (V)
1.5
1.0
0.5
0.0
-0.5
-25 -20 -15 -10 -5 0
-40°C
25°C
85°C
Open Input
VS = 2.7V
LMH2180
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SNAS419D –JANUARY 2008–REVISED MARCH 2013
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
TA= 25°C, VDD = 2.7V, VSS = 0V, Enable1,2 = VDD, CL= 10 pF, RL= 30 kΩand CCOUPLING = 10 nF, unless otherwise specified.
Input Impedance VOUT
vs. vs.
Frequency IOUT (Sourcing)
Figure 27. Figure 28.
VOUT VOUT
vs. vs.
IOUT (Sourcing) IOUT (Sinking)
Figure 29. Figure 30.
VOUT ISC Sourcing
vs. vs.
IOUT (Sinking) VSUPPLY Over Temperature
Figure 31. Figure 32.
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Product Folder Links: LMH2180
VENABLE (V)
ISUPPLY (mA)
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
0.0 0.4 0.8 1.2 1.6 2.0
25°C
85°C
-40°C
No Load
VS = 5V
VSUPPLY (V)
ISC (mA)
100
80
60
40
20
0
2.5 3.0 3.5 4.0 4.5 5.0
25°C 85°C
-40°C
VIN = VSS
VOUT = VDD
100
80
60
40
20
0
VENABLE (V)
ISUPPLY (mA)
2.5
2.0
1.5
1.0
0.5
0.0
0.0 0.4 0.8 1.2 1.6 2.0
85°C
25°C
-40°C
No Load
VS = 2.7V
2.5
2.0
1.5
1.0
0.5
0.0
LMH2180
SNAS419D –JANUARY 2008–REVISED MARCH 2013
www.ti.com
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
TA= 25°C, VDD = 2.7V, VSS = 0V, Enable1,2 = VDD, CL= 10 pF, RL= 30 kΩand CCOUPLING = 10 nF, unless otherwise specified.
ISC Sinking ISUPPLY
vs. vs.
VSUPPLY Over Temperature VENABLE
Figure 33. Figure 34.
ISUPPLY
vs.
VENABLE
Figure 35.
12 Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated
Product Folder Links: LMH2180
VDD
IN
ENABLE
OUT
VSS
OSC 1V
C1
LMH2180
www.ti.com
SNAS419D –JANUARY 2008–REVISED MARCH 2013
APPLICATION INFORMATION
GENERAL
The LMH2180 is designed to minimize the effects of spurious signals from the base chip to the oscillator. Also
the influence of varying load resistance and capacitance to the oscillator is minimized, while the drive capability is
increased.
The inputs of the LMH2180 are internally biased at 1V, making AC coupling possible without external bias
resistors.
To optimize current consumption, a buffer that is not in use can be disabled by connecting it's enable pin to VSS.
The LMH2180 has no internal ground reference; therefore, either single or split supply configurations can be
used.
The LMH2180 is an easy replacement for discrete circuitry. It simplifies board layout and minimizes the effect of
layout related parasitic components.
INPUT CONFIGURATION
The internal 1V input biasing allows AC coupling of the input signal. This biasing avoids the use of external
resistors, as depicted in Figure 36. The biasing prevents a large DC load at the oscillators output that creates a
load impedance and may affect it's oscillating frequency. As a result of this biasing, the maximum amplitude of
the AC signal is 2VPP.
The coupling capacitance C1 should be large enough to let the AC signal pass. This is a unity gain buffer with
rail-to-rail inputs and outputs.
Figure 36. Input Configuration
FREQUENCY PULLING
Frequency pulling is the frequency variation of an oscillator caused by a varying load. In the typical application,
the load of the oscillator is a fixed capacitor (C1) in series with the input impedance of the buffer.
To keep the input impedance as constant as possible, the input is biased at 1V, even when the part is disabled.
A simplified schematic of the input configuration is shown in Figure 36.
ISOLATION AND CROSSTALK
Output to input isolation prevents the clock signal of the oscillator from being affected by spurious signals
generated by the digital blocks behind the output buffer. See Figure 13.
A block diagram of the isolation is shown in Figure 37. Crosstalk rejection between buffers prevents signals from
affecting each other. Figure 37 shows a Baseband IC and a Bluetooth module as an example. See Figure 14 for
more information.
Copyright © 2008–2013, Texas Instruments Incorporated Submit Documentation Feedback 13
Product Folder Links: LMH2180
FREQUENCY (Hz)
GAIN (dB)
9
6
3
0
-3
-6
-9
-12
-15
-18
1M 10M 100M
No C Load
6.8 pF
10 pF
22 pF
33 pF
VIN = 0.1VPP
IN 1
IN 2
OUT 1
OUT 2
VCTCXO
Crosstalk
LMH2180
Base
band IC
Bluetooth
WLAN
Isolation
C1
LMH2180
SNAS419D –JANUARY 2008–REVISED MARCH 2013
www.ti.com
Figure 37. Isolation Block Diagram
DRIVING CAPACITIVE LOADS
Each buffer can drive a capacitive load. Be aware that every capacitor directly connected to the output becomes
part of the loop of the buffer. In most applications the load consists of the capacitance of copper tracks and the
input capacitance of the application blocks. Capacitance reduces the gain/phase margin and decreases the
stability. This leads to peaking in the frequency response and in extreme situations oscillations can occur. To
drive a large capacitive load it is recommended to include a series resistor between the buffer and the load
capacitor. The best value for this isolation resistance can be found by experimentation.
The LMH2180 datasheet reflects measurements with capacitive loads of 10 pF at the output of the buffers. Most
common applications will probably use a lower capacitive load, which will result in lower peaking and significantly
greater bandwidth, see Figure 38.
Figure 38. Bandwidth and Peaking
PHASE NOISE
A clock buffer adds noise to the clock signal. This noise causes uncertainty in the phase of the clock signal. This
uncertainty is described by jitter (time domain) or phase noise (frequency domain). Communication systems,
such as Wireless LAN, require a low jitter/phase noise clock signal to obtain a low Bit Error Rate. Figure 39
shows the frequency domain representation of a clock signal with frequency fC. Without Phase Noise the entire
signal power would only be located at the frequency fC. Phase Noise spreads some of the power to adjacent
frequencies. Phase Noise is usually specified in dBc/Hz at a given frequency offset Δf from the carrier, where
dBc is the power level in dB relative to the carrier. The noise power is measured within a 1 Hz bandwidth.
14 Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated
Product Folder Links: LMH2180
LMH2180
VSS
10 nF
EN1
IN1
IN2
EN2
1
1
2
3
4
5
6
7
8
OUT1
LMH6559
TCXO
Enable 1
2
Enable 2
38.4 MHz
50:
10 nF
Buffer for
driving 50:
E5052A/B
Signal Source
Analyzer
VDD
POWER (dB)
FREQUENCY (Hz)
fC
Phase Noise
(dBc/Hz)
Âf
BW = 1 Hz
LMH2180
www.ti.com
SNAS419D –JANUARY 2008–REVISED MARCH 2013
Figure 39. Phase Noise
Figure 40 shows the setup used to measure the LMH2180 phase noise. The clock driving the LMH2180 is a
state of the art 38.4MHz TCXO. Both the TCXO phase noise and the phase noise at the LMH2180 output were
measured. At offset frequencies of 1 kHz and higher from the carrier, the TCXO phase noise is sufficiently low to
accurately calculate the LMH2180 contribution to the phase noise at the output. The LMH6559, whose phase
noise contribution can be neglected, is used to drive the 50Ωinput impedance of the Signal Source Analyzer.
LAYOUT DESIGN RECOMMENDATION
Careful consideration during circuit design and PCB layout will eliminate problems and will optimize the
performance of the LMH2180. It is best to have the same ground plane on the PCB for all decoupling and other
ground connections.
To ensure a clean supply voltage it is best to place decoupling capacitors close to the LMH2180, between VDD
and VSS.
Another important issue is the value of the components, because this also determines the sensitivity to
disturbances. Resistor values have to be low enough to avoid a significant noise contribution and large enough to
avoid a significant increase in power consumption while loading inputs or outputs to heavily.
Figure 40. Measurement Setup
Copyright © 2008–2013, Texas Instruments Incorporated Submit Documentation Feedback 15
Product Folder Links: LMH2180
LMH2180
SNAS419D –JANUARY 2008–REVISED MARCH 2013
www.ti.com
REVISION HISTORY
Changes from Revision C (March 2013) to Revision D Page
• Changed layout of National Data Sheet to TI format .......................................................................................................... 15
16 Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated
Product Folder Links: LMH2180
PACKAGE OPTION ADDENDUM
www.ti.com 11-Apr-2018
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead/Ball Finish
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
LMH2180SD/NOPB ACTIVE WSON NGQ 8 1000 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 2180S
LMH2180SDE/NOPB ACTIVE WSON NGQ 8 250 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 2180S
LMH2180TM/NOPB ACTIVE DSBGA YFQ 8 250 Green (RoHS
& no Sb/Br) SNAGCU Level-1-260C-UNLIM A
LMH2180TMX/NOPB ACTIVE DSBGA YFQ 8 3000 Green (RoHS
& no Sb/Br) SNAGCU Level-1-260C-UNLIM A
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
PACKAGE OPTION ADDENDUM
www.ti.com 11-Apr-2018
Addendum-Page 2
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
LMH2180SD/NOPB WSON NGQ 8 1000 178.0 12.4 3.3 3.3 1.0 8.0 12.0 Q1
LMH2180SDE/NOPB WSON NGQ 8 250 178.0 12.4 3.3 3.3 1.0 8.0 12.0 Q1
LMH2180TM/NOPB DSBGA YFQ 8 250 178.0 8.4 1.35 1.35 0.76 4.0 8.0 Q1
LMH2180TMX/NOPB DSBGA YFQ 8 3000 178.0 8.4 1.35 1.35 0.76 4.0 8.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 30-Apr-2018
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
LMH2180SD/NOPB WSON NGQ 8 1000 210.0 185.0 35.0
LMH2180SDE/NOPB WSON NGQ 8 250 210.0 185.0 35.0
LMH2180TM/NOPB DSBGA YFQ 8 250 210.0 185.0 35.0
LMH2180TMX/NOPB DSBGA YFQ 8 3000 210.0 185.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 30-Apr-2018
Pack Materials-Page 2
MECHANICAL DATA
YFQ0008xxx
www.ti.com
TMD08XXX (Rev A)
E
0.600±0.075
D
A
. All linear dimensions are in millimeters. Dimensioning and tolerancing per ASME Y14.5M-1994.
B. This drawing is subject to change without notice.
NOTES:
4215076/A 12/12
D: Max =
E: Max =
1.24 mm, Min =
1.24 mm, Min =
1.18 mm
1.18 mm
www.ti.com
PACKAGE OUTLINE
C
8X 0.3
0.2
2 0.1
8X 0.5
0.3
2X
1.5
1.6 0.1
6X 0.5
0.8
0.7
0.05
0.00
B3.1
2.9 A
3.1
2.9
(0.1) TYP
WSON - 0.8 mm max heightNGQ0008A
PLASTIC SMALL OUTLINE - NO LEAD
4214922/A 03/2018
PIN 1 INDEX AREA
SEATING PLANE
0.08 C
1
45
8
PIN 1 ID 0.1 C A B
0.05 C
THERMAL PAD
EXPOSED
9
SYMM
SYMM
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
SCALE 4.000
www.ti.com
EXAMPLE BOARD LAYOUT
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
(1.6)
6X (0.5)
(2.8)
8X (0.25)
8X (0.6)
(2)
(R0.05) TYP ( 0.2) VIA
TYP
(0.75)
WSON - 0.8 mm max heightNGQ0008A
PLASTIC SMALL OUTLINE - NO LEAD
4214922/A 03/2018
SYMM
1
45
8
SYMM
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:20X
9
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
SOLDER MASK
OPENING
SOLDER MASK
METAL UNDER
SOLDER MASK
DEFINED
EXPOSED METAL
METAL
SOLDER MASK
OPENING
SOLDER MASK DETAILS
NON SOLDER MASK
DEFINED
(PREFERRED)
EXPOSED METAL
www.ti.com
EXAMPLE STENCIL DESIGN
8X (0.25)
8X (0.6)
6X (0.5)
(1.79)
(1.47)
(2.8)
(R0.05) TYP
WSON - 0.8 mm max heightNGQ0008A
PLASTIC SMALL OUTLINE - NO LEAD
4214922/A 03/2018
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
SOLDER PASTE EXAMPLE
BASED ON 0.1 mm THICK STENCIL
EXPOSED PAD 9:
82% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:20X
SYMM
1
45
8
SYMM
METAL
TYP
9
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