DS070 (v4.0) August 9, 2013 www.xilinx.com
Product Specification 1
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Features
• Certified to MIL-PRF-38535 Appendix A QML
(Qualified Manufacturer Listing)
• Also available under the following Standard Microcircuit
Drawings (SMD): 5962-94717 and 5962-95617
• Configuration one-time programmable (OTP) read-only
memory designed to store configuration bitstreams of
Xilinx FPGA devices
• On-chip address counter, incremented by each rising
edge on the clock input
• Simple interface to the FPGA requires only one user
I/O pin
• Cascadable for storing longer or multiple bitstreams
• Programmable reset polarity (active High or active
Low) for compatibility with different FPGA solutions
• Low-power CMOS EPROM process
• Available in 5V version only
• Programming support by leading programmer
manufacturers.
• Design support using the Xilinx Alliance and
Foundation series software packages
Description
The XC1700D QPRO™ family of configuration PROMs
provide an easy-to-use, cost-effective method for storing
Xilinx FPGA configuration bitstreams.
When the FPGA is in Master Serial mode, it generates a
configuration clock that drives the PROM. A short access
time after the rising clock edge, data appears on the PROM
DATA output pin that is connected to the FPGA DIN pin. The
FPGA generates the appropriate number of clock pulses to
complete the configuration. Once configured, it disables the
PROM. When the FPGA is in Slave Serial mode, the PROM
and the FPGA must both be clocked by an incoming signal.
Multiple devices can be concatenated by using the CEO
output to drive the CE input of the following device. The
clock inputs and the DATA outputs of all PROMs in this
chain are interconnected. All devices are compatible and
can be cascaded with other members of the family.
For device programming, either the Xilinx Alliance™ or the
Foundation™ series development systems compiles the
FPGA design file into a standard HEX format which is then
transferred to most commercial PROM programmers.
11
QPRO Family of XC1700D QML
Configuration PROMs
DS070 (v4.0) August 9, 2013 Product Specification
X-Ref Target - Figure 1
Figure 1: Simplified Block Diagram (Does Not Show Programming Circuit)
EPROM
Cell
Matrix
Address Counter
CE
DATA
OE
Output
CLK
VCC VPP GND
DS070_01_111010
TC
RESET/OE
or
OE/RESET
CEO
QPRO Family of XC1700D QML Configuration PROMs
DS070 (v4.0) August 9, 2013 www.xilinx.com
Product Specification 2
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Pin Description
DATA
Data output, 3-stated when either CE or OE are inactive. During programming, the DATA pin is I/O.
Note: OE can be programmed to be either active High or active Low.
CLK
Each rising edge on the CLK input increments the internal address counter, if both CE and OE are active.
RESET/OE
When High, this input holds the address counter reset and 3-states the DATA output. The polarity of this input pin is
programmable as either RESET/OE or OE/RESET. To avoid confusion, this document describes the pin as RESET/OE,
although the opposite polarity is possible on all devices. When RESET is active, the address counter is held at zero, and the
DATA output is put in a high-impedance state. The polarity of this input is programmable. The default is active High RESET,
but the preferred option is active Low RESET, because it can be driven by the FPGAs INIT pin.
The polarity of this pin is controlled in the programmer interface. This input pin is easily inverted using the Xilinx HW-130
programmer software. Third-party programmers have different methods to invert this pin.
CE
When High, this pin disables the internal address counter, 3-states the DATA output, and forces the device into low-ICC
standby mode.
CEO
Chip enable output, to be connected to the CE input of the next PROM in the daisy chain. This output is Low when the CE
and OE inputs are both active AND the internal address counter has been incremented beyond its terminal count (TC) value.
In other words: when the PROM has been read, CEO will follow CE as long as OE is active. When OE goes inactive, CEO
stays High until the PROM is reset.
Note: OE can be programmed to be either active High or active Low.
VPP
Programming voltage. No overshoot above the specified maximum voltage is permitted on this pin. For normal read
operation, this pin must be connected to VCC. Failure to do so can lead to unpredictable, temperature-dependent operation
and severe problems in circuit debugging. Do not leave VPP floating!
VCC and GND
VCC is positive supply pin and GND is ground pin.
QPRO Family of XC1700D QML Configuration PROMs
DS070 (v4.0) August 9, 2013 www.xilinx.com
Product Specification 3
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PROM Pinouts
Capacity
Number of Configuration Bits, Including Header, for Xilinx FPGAs and Compatible PROMs
Controlling PROMs
Connecting the FPGA device with the PROM.
• The DATA output(s) of the PROM(s) drives the DIN input of the lead FPGA device.
• The Master FPGA CCLK output drives the CLK input(s) of the PROM(s).
•The CEO
output of a PROM drives the CE input of the next PROM in a daisy chain (if any).
• The RESET/OE input of all PROMs is best driven by the INIT output of the lead FPGA device. This connection assures
that the PROM address counter is reset before the start of any reconfiguration, even when a reconfiguration is initiated
by a VCC glitch. Other methods—such as driving RESET/OE from LDC or system reset—assume the PROM internal
power-on-reset is always in step with the FPGA’s internal power-on-reset. This might not be a safe assumption.
•The PROM CE
input can be driven from either the LDC or DONE pins. Using LDC avoids potential contention on the
DIN pin.
•The CE
input of the lead (or only) PROM is driven by the DONE output of the lead FPGA device, provided that DONE
is not permanently grounded. Otherwise, LDC can be used to drive CE, but must then be unconditionally High during
user operation. CE can also be permanently tied Low, but this keeps the DATA output active and causes an
unnecessary supply current of 10 mA maximum.
Table 1: PROM Pinouts
Pin Name 8-pin
DATA 1
CLK 2
RESET/OE (OE/RESET)3
CE 4
GND 5
CEO 6
VPP 7
VCC 8
Table 2: Capacity
Devices Configuration Bits
XC1736D 36,288
XC1765D 65,536
XC17128D 131,072
XC17256D 262,144
Table 3: Number of Configuration Bits, Including Header, for Xilinx FPGAs and Compatible PROMs
Device Configuration Bits PROM
XC3000/A series 14,819 to 94,984 XC1765D to XC17128D
XC4000 series 95,008 to 247,968 XC17128D to XC17256D
XQ4005E 95,008 XC17128D
XQ4010E 178,144 XC17256D
XQ4013E 247,968 XC17256D
QPRO Family of XC1700D QML Configuration PROMs
DS070 (v4.0) August 9, 2013 www.xilinx.com
Product Specification 4
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FPGA Master Serial Mode Summary
The I/O and logic functions of the configurable logic block (CLB) and their associated interconnections are established by a
configuration program. The program is loaded either automatically upon power up, or on command, depending on the state
of the three FPGA mode pins. In Master Serial mode, the FPGA automatically loads the configuration program from an
external memory. The Xilinx PROMs have been designed for compatibility with the Master Serial mode.
Upon power-up or reconfiguration, an FPGA enters the Master Serial mode whenever all three of the FPGA mode-select
pins are Low (M0=0, M1=0, M2=0). Data is read from the PROM sequentially on a single data line. Synchronization is
provided by the rising edge of the temporary signal CCLK, which is generated during configuration.
Master Serial Mode provides a simple configuration interface. Only a serial data line and two control lines are required to
configure an FPGA. Data from the PROM is read sequentially, accessed via the internal address and bit counters which are
incremented on every valid rising edge of CCLK.
If the user-programmable, dual-function DIN pin on the FPGA is used only for configuration, it must still be held at a defined
level during normal operation. Xilinx FPGAs take care of this automatically with an on-chip default pull-up resistor.
Programming the FPGA With Counters Unchanged Upon Completion
When multiple FPGA-configurations for a single FPGA are stored in a PROM, the OE pin should be tied Low. Upon
power-up, the internal address counters are reset and configuration begins with the first program stored in memory. Since
the OE pin is held Low, the address counters are left unchanged after configuration is complete. Therefore, to reprogram the
FPGA with another program, the DONE line is pulled Low and configuration begins at the last value of the address counters.
This method fails if a user applies RESET during the FPGA configuration process. The FPGA aborts the configuration and
then restarts a new configuration, as intended, but the PROM does not reset its address counter, since it never saw a High
level on its OE input. The new configuration, therefore, reads the remaining data in the PROM and interprets it as preamble,
length count etc. Since the FPGA is the master, it issues the necessary number of CCLK pulses, up to 16 million (224) and
DONE goes High. However, the FPGA configuration will be completely wrong, with potential contentions inside the FPGA
and on its output pins. This method must, therefore, never be used when there is any chance of external reset during
configuration.
Cascading Configuration PROMs
For multiple FPGAs configured as a daisy-chain, or for future FPGAs requiring larger configuration memories, cascaded
PROMs provide additional memory. After the last bit from the first PROM is read, the next clock signal to the PROM asserts
its CEO output Low and disables its DATA line. The second PROM recognizes the Low level on its CE input and enables its
DATA output. See Figure 2.
After configuration is complete, the address counters of all cascaded PROMs are reset if the FPGA RESET pin goes Low,
assuming the PROM reset polarity option has been inverted.
To reprogram the FPGA with another program, the DONE line goes Low and configuration begins where the address
counters had stopped. In this case, avoid contention between DATA and the configured I/O use of DIN.
QPRO Family of XC1700D QML Configuration PROMs
DS070 (v4.0) August 9, 2013 www.xilinx.com
Product Specification 5
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X-Ref Target - Figure 2
Figure 2: Master Serial Mode
DIN
DOUT
CCLK
INIT
DONE
PROM
DATA
CLK
CE CE
FPGA
(Low Resets the Address Pointer)
VCC
VCC
VCC
OPTIONAL
Daisy-chained
FPGAs with
Different
configurations
OPTIONAL
Slave FPGAs
with Identical
Configurations
RESET RESET
ds070_02_111010
CCLK
(Output)
DIN
DOUT
(Output)
OE/RESET
MODES(1)
VPP
Cascaded
Serial
Memory
DATA
CLK
CEO
OE/RESET
3.3V
4.7KΩ
Notes:
1. For mode pin connections, refer to the appropriate FPGA data sheet.
2. The one-time-programmable PROM supports automatic loading of configuration programs.
3. Multiple devices can be cascaded to support additional FPGAs.
4. An early DONE inhibits the PROM data output one CCLK cycle before the FPGA I/Os become active.
QPRO Family of XC1700D QML Configuration PROMs
DS070 (v4.0) August 9, 2013 www.xilinx.com
Product Specification 6
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Standby Mode
The PROM enters a low-power standby mode whenever CE is asserted High. The output remains in a high impedance state
regardless of the state of the OE input.
Programming
The devices can be programmed on programmers supplied by Xilinx or qualified third-party vendors. The user must ensure
that the appropriate programming algorithm and the latest version of the programmer software are used. The wrong choice
can permanently damage the device.
Note: Always tie the VPP pin to VCC in your application. Never leave VPP floating.
Table 4: Truth Table for XC1700 Control Inputs
Control Inputs Internal Address Outputs
RESET CE DATA CEO ICC
Inactive Low If address < TC: increment
If address > TC: don’t change
Active
High-Z
High
Low
Active
reduced
Active Low Held reset High-Z High Active
Inactive High Not changing High-Z High Standby
Active High Held reset High-Z High Standby
Notes:
1. The XC1700 RESET input has programmable polarity
2. TC = Terminal Count = highest address value. TC + 1 = address 0.
QPRO Family of XC1700D QML Configuration PROMs
DS070 (v4.0) August 9, 2013 www.xilinx.com
Product Specification 7
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XC1736D, XC1765D, XC17128D and XC17256D
Absolute Maximum Ratings
Operating Conditions
DC Characteristics Over Operating Condition
Table 5: Absolute Maximum Ratings
Symbol Description Range Units
VCC Supply voltage relative to GND –0.5 to +7.0 V
VPP Supply voltage relative to GND –0.5 to +12.5 V
VIN Input voltage relative to GND –0.5 to VCC +0.5 V
VTS Voltage applied to High-Z output –0.5 to VCC +0.5 V
TSTG Storage temperature (ambient) –65 to +150 °C
TSOL Maximum soldering temperature (10s @ 1/16 in.) +260 °C
Notes:
1. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only,
and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions is not implied.
Exposure to Absolute Maximum Ratings conditions for extended periods of time may affect device reliability.
Table 6: Operating Conditions
Symbol Description Min Max Units
VCC Supply voltage relative to GND (TC = –55°C to +125°C) Military 4.50 5.50 V
Notes:
1. During normal read operation VPP must be connected to VCC
Table 7: DC Characteristics Over Operating Condition
Symbol Description Min Max Units
VIH High-level input voltage 2.0 VCC V
VIL Low-level input voltage 0 0.8 V
VOH High-level output voltage (IOH = –4 mA) Military 3.7 – V
VOL Low-level output voltage (IOL = +4 mA) – 0.4 V
ICCA Supply current, active mode (at maximum frequency) – 10 mA
ICCS
Supply current, standby mode XC17128D, XC17256D – 50 µA
XC1736D, XC1765D – 1.5 mA
ILInput or output leakage current –10 10 µA
CIN Input capacitance (VIN = GND, f = 1.0 MHz) sample tested – 10 pF
COUT Output capacitance (VIN = GND, f = 1.0 MHz) sample tested – 10 pF
QPRO Family of XC1700D QML Configuration PROMs
DS070 (v4.0) August 9, 2013 www.xilinx.com
Product Specification 8
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AC Characteristics Over Operating Condition
X-Ref Target - Figure 3
Figure 3: AC Characteristics Over Operating Condition
Table 8: AC Characteristics Over Operating Condition(1)(2)
Symbol Description
XC1736D
XC1765D
XC17128D
XC17256D Units
Min Max Min Max
TOE OE to data delay – 45 – 25 ns
TCE CE to data delay – 60 – 45 ns
TCAC CLK to data delay – 150 – 50 ns
TOH Data hold from CE, OE, or CLK(3) 0–0 –ns
TDF CE or OE to data float delay(3)(4) –50–50ns
TCYC Clock periods 200 – 80 – ns
TLC CLK Low time(3) 100 – 20 – ns
THC CLK High time(3) 100 – 20 – ns
TSCE CE setup time to CLK (to guarantee proper counting) 25 – 20 – ns
THCE CE hold time to CLK (to guarantee proper counting) 0 – 0 – ns
THOE OE hold time (guarantees counters are reset) 100 – 20 – ns
Notes:
1. AC test load = 50 pF
2. All AC parameters are measured with VIL = 0.0V and VIH = 3.0V.
3. Guaranteed by design, not tested.
4. Float delays are measured with 5 pF AC loads. Transition is measured at ±200 mV from steady state active levels.
RESET/OE
CE
CLK
DATA
TCE
TOE
TLC
TSCE TSCE THCE
THOE
TCAC TOH TDF
TOH
THC
DS070_03_111010
TCYC
QPRO Family of XC1700D QML Configuration PROMs
DS070 (v4.0) August 9, 2013 www.xilinx.com
Product Specification 9
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AC Characteristics Over Operating Condition When Cascading
X-Ref Target - Figure 4
Figure 4: AC Characteristics Over Operating Condition When Cascading
Table 9: AC Characteristics Over Operating Condition When Cascading(1)(2)
Symbol Description
XC1736D
XC1765D
XC17128D
XC17256D Units
Min Max Min Max
TCDF CLK to data float delay(3)(4) –50–50ns
TOCK CLK to CEO delay(3) –65–30ns
TOCE CE to CEO delay(3) –45–35ns
TOOE RESET/OE to CEO delay(3) –40–30ns
Notes:
1. AC test load = 50 pF
2. All AC parameters are measured with VIL = 0.0V and VIH = 3.0V.
3. Guaranteed by design, not tested.
4. Float delays are measured with 5 pF AC loads. Transition is measured at ±200mV from steady state active levels.
RESET/OE
CLK
DATA
(First PROM)
DATA
(Cascaded
PROM)
CE
CEO
(First PROM)
CE
(Cascaded
PROM)
Last
Bit
Last
Bit
First
Bit
First
Bit
DS070_04_111010
nnn+1n–1
TCDF
TOOE TOCK TOCE TOCE
TCCE
TCCE
QPRO Family of XC1700D QML Configuration PROMs
DS070 (v4.0) August 9, 2013 www.xilinx.com
Product Specification 10
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Ordering Information
Valid Ordering Combinations
Marking Information
Due to the small size of the PROM package, the complete ordering part number cannot be marked on the package. The XC
prefix is deleted and the package code is simplified. Devices are marked as shown in Figure 6.
Revision History
The following table shows the revision history for this document:
X-Ref Target - Figure 5
Figure 5: Ordering Information
Table 10: Valid Ordering Combinations
XC17128DDD8M XC17256DDD8M XC1736DDD8M XC1765DDD8M
5962-9561701MPA 5962-9471701MPA
X-Ref Target - Figure 6
Figure 6: Marking Information
Date Version Revisions
02/08/1999 2.0 Removed the now obsolete Commercial and Industrial Grade part numbers and design support.
06/01/2000 2.1 Updated format and assigned data sheet number (DS070).
11/11/2010 3.0 Updated Notice of Disclaimer.
08/09/2013 4.0 The products in this data sheet are obsolete per XCN06002 and XCN10029.
XC17256DDD8M
Operating Range/Processing
M = Military (TC = –55° to +125°C)
B = Military (TC = –55° to +125°C)
QML certified to MIL-PRF-38535
Package Type
DD8 = 8-pin Ceramic DIP
Device Number
XC1736D
XC1765D
XC17128D
XC17256D
ds070_05_111010
17256D DD8M
Operating Range/Processing
M = Military (TC = –55° to +125°C)
B = Military (TC = –55° to +125°C)
QML certified to MIL-PRF-38535
Package Type
DD8 = 8-pin Ceramic DIP
Device Number
XC1736D
XC1765D
XC17128D
XC17256D
ds070_06_111010
QPRO Family of XC1700D QML Configuration PROMs
DS070 (v4.0) August 9, 2013 www.xilinx.com
Product Specification 11
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Notice of Disclaimer
THE XILINX HARDWARE FPGA AND CPLD DEVICES REFERRED TO HEREIN (“PRODUCTS”) ARE SUBJECT TO THE TERMS AND
CONDITIONS OF THE XILINX LIMITED WARRANTY WHICH CAN BE VIEWED AT http://www.xilinx.com/warranty.htm. THIS LIMITED
WARRANTY DOES NOT EXTEND TO ANY USE OF PRODUCTS IN AN APPLICATION OR ENVIRONMENT THAT IS NOT WITHIN THE
SPECIFICATIONS STATED IN THE XILINX DATA SHEET. ALL SPECIFICATIONS ARE SUBJECT TO CHANGE WITHOUT NOTICE.
PRODUCTS ARE NOT DESIGNED OR INTENDED TO BE FAIL-SAFE OR FOR USE IN ANY APPLICATION REQUIRING FAIL-SAFE
PERFORMANCE, SUCH AS LIFE-SUPPORT OR SAFETY DEVICES OR SYSTEMS, OR ANY OTHER APPLICATION THAT INVOKES
THE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
APPLICATIONS”). USE OF PRODUCTS IN CRITICAL APPLICATIONS IS AT THE SOLE RISK OF CUSTOMER, SUBJECT TO
APPLICABLE LAWS AND REGULATIONS.
CRITICAL APPLICATIONS DISCLAIMER
XILINX PRODUCTS (INCLUDING HARDWARE, SOFTWARE AND/OR IP CORES) ARE NOT DESIGNED OR INTENDED TO BE
FAIL-SAFE, OR FOR USE IN ANY APPLICATION REQUIRING FAIL-SAFE PERFORMANCE, SUCH AS IN LIFE-SUPPORT OR
SAFETY DEVICES OR SYSTEMS, CLASS III MEDICAL DEVICES, NUCLEAR FACILITIES, APPLICATIONS RELATED TO THE
DEPLOYMENT OF AIRBAGS, OR ANY OTHER APPLICATIONS THAT COULD LEAD TO DEATH, PERSONAL INJURY OR SEVERE
PROPERTY OR ENVIRONMENTAL DAMAGE (INDIVIDUALLY AND COLLECTIVELY, “CRITICAL APPLICATIONS”). FURTHERMORE,
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VEHICLE OR AIRCRAFT, UNLESS THERE IS A FAIL-SAFE OR REDUNDANCY FEATURE (WHICH DOES NOT INCLUDE USE OF
SOFTWARE IN THE XILINX DEVICE TO IMPLEMENT THE REDUNDANCY) AND A WARNING SIGNAL UPON FAILURE TO THE
OPERATOR. CUSTOMER AGREES, PRIOR TO USING OR DISTRIBUTING ANY SYSTEMS THAT INCORPORATE XILINX
PRODUCTS, TO THOROUGHLY TEST THE SAME FOR SAFETY PURPOSES. TO THE MAXIMUM EXTENT PERMITTED BY
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