ADS5103IPFBRG4 - Texas Instruments

ADS5102

ADS5103

SLAS351B – OCTOBER 2001 – REVISED DECEMBER 2001

1.8-V ANALOG SUPPLY, 10-BIT, 65/40 MSPS

ANALOG-TO-DIGITAL CONVERTERS WITH INTERNAL REFERENCE

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FEATURES

DADS5102 (65 MSPS) ADS5103 (40 MSPS)

DDifferential Input

D1.8 V Analog/Digital Supply

DDigital Outputs Compatible With 1.8 V or 3.3 V

Logic

DSignal-to-Noise: 58 dB at 20 MHz (ADS5103)

DSpurious Free Dynamic Range: 71 dB at

20 MHz (ADS5102)

D105-mW Power Dissipation (ADS5103)

D336 µW Power-Down Mode

APPLICATIONS

DUltrasound

DDigital Cameras

DImaging

DCommunications

DBaseband Digitization

DESCRIPTION

The ADS5102/3 are low-power CMOS, 10-bit, analog-

to-digital converters (ADC) that operate from a single

1.8-V supply. The internal reference can be bypassed

to use an external reference to suit the dc accuracy and

temperature drift requirements of the application. A

10-bit parallel output data bus is provided with 3-state

outputs. For power sensitive systems, a standby mode

is provided which reduces power consumption to

336 µW. Also, if using external voltage reference, then

the internal VREF circuit can be powered down. The

analog input is differential, which provides excellent

common-mode noise rejection as well as superior

performance from the ADS5102/3.

FUNCTIONAL BLOCK DIAGRAM

Timing Circuitry

AGND BG PDREF REFT REFB CML DRGND DGND

CLK

AIN+

AIN–

RBIAS

AVDD STBY DRVDD DVDD

D[0–9]

Sample

and Hold 10 Bit

ADC

3-State

Output

Buffers

Internal

Reference

Circuit

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

ADS5102

ADS5103

SLAS351B – OCTOBER 2001 – REVISED DECEMBER 2001

2www.ti.com

DRVDD

DVDD

DGND

CLK

STBY

PDREF

RBIAS

DRGND

DVDD

DGND

AVDD

AGND

AIN–

AIN+

AGND

AVDD

5678

35 34 33 32 3136 30

AGND

REFB

CML

AGND

28 27 2629

910 11 12

REFT

PFB PACKAGE

(TOP VIEW)

NC – No internal connection

ORDERING INFORMATION

48-TQFP (PFB)

Tape and Reel 48-TQFP (PFB)

Tray 48-TQFP (PFB)

Tape and Reel 48-TQFP (PFB)

Tray

40 MSPS 40 MSPS 65 MSPS 65 MSPS

0°C to 70°CADS5103CPFBR ADS5103CPFB ADS5102CPFBR ADS5102CPFB

–40°C to 85°CADS5103IPFBR ADS5103IPFB ADS5102IPFBR ADS5102IPFB

Evaluation module ADS5103EVM ADS5103EVM ADS5102EVM ADS5102EVM

ADS5102

ADS5103

SLAS351B – OCTOBER 2001 – REVISED DECEMBER 2001

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Terminal Functions

TERMINAL

I/O

DESCRIPTION

NAME NO. I/O DESCRIPTION

AVDD 2, 41, 46 IAnalog supply, 1.8V ±5%

AGND 3, 9, 42, 45 IAnalog ground

REFT 4 I/O Reference top

REFB 5 I/O Reference bottom

CML 6 O Common mode level output—nominally 1.0 V

BG 7 O Band-gap decoupling—decouple with 1 µF to GND and 100 kΩ to AVDD (refer to Figure 30)

PDREF 17 I Powerdown reference when using external voltage reference 0 = internal VREF, 1 = external VREF.

In external VREF mode, connect pins BG and REFT together.

RBIAS 14 O Connect a resistor between this pin and AGND. This resistor value is determined by speed grade

selected and is used to set amplifier internal bias currents. (see Table 2)

OE 18 I 1 = 3-state the data outputs , 0 = data bus enable

STBY 19 I 0 = power down mode, 1 = normal operation mode

CLK 20 I Clock Input

DGND 21, 40 IDigital ground

DVDD 22, 39 IDigital supply—1.8 V nominally

DRVDD 24 I Driver digital supply—1.8 V or 3.3 V nominally

D9 25 O Digital Bit 9 (MSB)

D8 26 O Digital Bit 8

D7 27 O Digital Bit 7

D6 28 O Digital Bit 6

D5 29 O Digital Bit 5

D4 30 O Digital Bit 4

D3 31 O Digital Bit 3

D2 32 O Digital Bit 2

D1 33 O Digital Bit 1

D0 34 O Digital Bit 0 (LSB)

DRGND 37 I Driver digital ground

AIN+ 44 I Positive analog input

AIN–43 I Negative analog input

NC 1,8,10,11,12,

13,15,16,23,35,

36, 38,47,48

NA No internal connection on this pin

ADS5102

ADS5103

SLAS351B – OCTOBER 2001 – REVISED DECEMBER 2001

4www.ti.com

absolute maximum ratings over operating free-air temperature (unless otherwise noted)†

Supply voltage: VDD to AGND, DVDD to DGND –0.3 V to 2.2 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

DRVDD to DRGND –0.3 V to 4 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

AGND to DGND –0.3 V to 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

AVDD to DVDD –2.2 V to 2.2 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Reference voltage input range REFT, REFB, to AGND –0.3 V to AVDD + 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

CML, analog input voltage range AIN to AGND –0.3 V to AVDD + 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Clock input CLK to DRGND –0.3 V to DRVDD + 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Digital inputs to DRGND –0.3 V to DRVDD + 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Digital outputs to DRGND –0.3 V to DRVDD + 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Operating junction temperature range, TJ0°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature range, Tstg –65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 300°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

†Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only , and

functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not

implied. Exposure to absolute-maximum-rated conditions for extended periods may af fect device reliability.

recommended operating conditions

MIN TYP MAX UNIT

Analog Inputs

Analog input voltage (AIN+, AIN–) REFB REFT V

Input voltage, differential full scale 1 Vpp

Input common-mode voltage, (REFT+REFB)/2 0.8 1.1 V

Input capacitance (Ci), measured to ground 5 pF

Overvoltage recovery time, 1.8-V input voltage 10 ns

Analog input bandwidth 950 MHz

Input impedance (switch capacitor)

ADS5102 38.5

kΩ

Input impedance (switch capacitor) ADS5103 62.5 kΩ

Supplies and References

Operating free-air temperature, TA–40 85 °C

Analog supply voltage, AVDD 1.65 1.80 2.00 V

Digital supply voltage, DVDD 1.65 1.80 2.00 V

Digital driver supply voltage, DRVDD 1.65 1.80 3.6 V

Reference top voltage, VREFT 1.30 1.34 1.39 V

Reference bottom voltage, VREFB 0.78 0.81 0.84 V

Common-mode voltage, VCML 0.85 1.05 1.15 V

Bandgap voltage, VBG 1.22 1.27 1.32 V

Clock Inputs CLK

Sampling rate

ADS5102 1 65

MSPS

Sampling rate ADS5103 1 40 MSPS

ADS5102

ADS5103

SLAS351B – OCTOBER 2001 – REVISED DECEMBER 2001

www.ti.com

electrical characteristics over recommended operating conditions, AVDD = DVDD = 1.8 V,

DRVDD = 3.3 V, Fs = 40, 65 MSPS (as appropriate)/50% duty cycle, –1 dBFS input span, CL = 10 pF

at D0–D9, internal reference, T(min) to T(max), typical data at 25°C (unless otherwise noted)

internal reference voltages

PARAMETER MIN TYP MAX UNIT

VREFT Reference top voltage 1.30 1.34 1.39 V

VREFB Reference bottom voltage 0.78 0.81 0.84 V

VCML Common-mode voltage 0.85 1.05 1.15 V

VBG Bandgap voltage 1.22 1.27 1.32 V

external reference voltages

PARAMETER MIN TYP MAX UNIT

REFT Reference input voltage (top) 1.15 1.25 1.35 V

REFB Reference input voltage (bottom) 0.70 0.75 0.85 V

REFT–REFB Differential input 0.45 0.50 0.55 V

Input resistance 200 Ω

digital outputs

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

High level output voltage

I50A

DRVDD = 1.8 V DRVDD – 0.1

VOH High-level output voltage IOH = 50 µADRVDD = 3.3 V DRVDD – 0.2 V

Low level output voltage

I50A

DRVDD = 1.8 V 0.1

VOL Low-level output voltage IOL = 50 µADRVDD = 3.3 V 0.2 V

CLExternal load capacitance 15 pF

digital inputs

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

High level input voltage

DRVDD = 1.8 V 0.8 × DRVDD

VIH High-level input voltage DRVDD = 3.3 V 0.8 × DRVDD V

Low level input voltage

DRVDD = 1.8 V 0.2 × DRVDD

VIL Low-level input voltage DRVDD = 3.3 V 0.2 × DRVDD V

IIH High-level input current VIH = DRVDD ±5µA

IIL Low-level input current VIL = 0 V ±5µA

dc accuracy

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

(INL)

Integral nonlinearity

ADS5102 ±1±2.5 LSB

(INL) Integral nonlinearity ADS5103 ±0.5 ±1.5 LSB

(DNL)

Differential nonlinearity

ADS5102 ±0.5 ±1 LSB

(DNL) Differential nonlinearity ADS5103 ±0.4 ±0.8 LSB

Missing code No missing code assured

Offset error REFT = 1.25 V, REFB = 0.75 V ±0.4 ±1.5 %FSR

Gain error REFT = 1.25 V, REFB = 0.75 V ±1.4 ±2 %FSR

ADS5102

ADS5103

SLAS351B – OCTOBER 2001 – REVISED DECEMBER 2001

6www.ti.com

electrical characteristics over recommended operating conditions, AVDD = DVDD = 1.8 V,

DRVDD = 3.3 V, Fs = 40, 65 MSPS (as appropriate)/50% duty cycle, –1 dBFS input span, CL = 10 pF

at D0–D9, internal reference, T(min) to T(max), typical data at 25°C (unless otherwise noted)

(continued)

dynamic performance

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

ADS5102

f = 3.5 MHz 8.7 9.2

Bits

ENOB

Effective number of bits

ADS5102 f = 20 MHz 9Bits

ENOB Effective number of bits

ADS5103

f = 3.5 MHz 9.0 9.3

Bits

ADS5103 f = 20 MHz 9.2 Bits

ADS5102

f = 3.5 MHz 58 73

dBc

SFDR

Spurious free dynamic range

ADS5102 f = 20 MHz 71 dBc

SFDR Spurious free dynamic range

ADS5103

f = 3.5 MHz 64 69

dBc

ADS5103 f = 20 MHz 66 dBc

ADS5102

f = 3.5 MHz –71 –55

dBc

THD

Total harmonic distortion

ADS5102 f = 20 MHz –71 dBc

THD Total harmonic distortion

ADS5103

f = 3.5 MHz –65 –62

dBc

ADS5103 f = 20 MHz –68 dBc

ADS5102

f = 3.5 MHz 56 58

dBc

SNR

Signal to noise ratio

ADS5102 f = 20 MHz 57 dBc

SNR Signal-to-noise ratio

ADS5103

f = 3.5 MHz 57 59

dBc

ADS5103 f = 20 MHz 58 dBc

ADS5102

f = 3.5 MHz 54 58

dBc

SINAD

Signal to noise and distortion

ADS5102 f = 20 MHz 57 dBc

SINAD Signal-to-noise and distortion

ADS5103

f = 3.5 MHz 56 58

dBc

ADS5103 f = 20 MHz 57 dBc

power supply†

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

AVDD 1.65 1.8 2

Operating voltage DVDD 1.65 1.8 2 V

O erating

voltage

DRVDD 1.65 1.8 3.6

I(AVDD)

Analog su

ly current

ADS5102

AVDD =DV

DD =18V DRV

DD =33V

70 80

I(AVDD)Analog supply current ADS5103 AVDD = DVDD = 1.8 V, DRVDD = 3.3 V 45 53 mA

I(DVDD)

Digital su

ly current

ADS5102

AVDD =DV

DD=18V DRV

DD =33V

8 9

I(DVDD)Digital supply current ADS5103 AVDD = DVDD= 1.8 V, DRVDD = 3.3 V 5 7 mA

I(DRVDD)

Out

ut driver su

ly current

ADS5102

AVDD =DV

DD =18V DRV

DD =33V

6.5 8

I(DRVDD)Output driver supply current ADS5103 AVDD = DVDD = 1.8 V, DRVDD = 3.3 V 4.8 5.5 mA

I(TOTAL)

Total current consum

tion

ADS5102

AVDD =DV

DD =18V DRV

DD =33V

84 97

I(TOTAL) Total current consumption ADS5103 AVDD = DVDD = 1.8 V, DRVDD = 3.3 V 54 66 mA

Power dissi

ation

ADS5102

AVDD =DV

DD =18V DRV

DD =33V

160 188

PDPower dissipation ADS5103 AVDD = DVDD = 1.8 V, DRVDD = 3.3 V 105 126 mW

Standby power CLK running 336 390 µW

Power supply rejection 0.25 %FS

†Sinewave input, fi = 3.5 MHz, –1 dBFS input span

ADS5102

ADS5103

SLAS351B – OCTOBER 2001 – REVISED DECEMBER 2001

www.ti.com

electrical characteristics over recommended operating conditions, AVDD = DVDD = 1.8 V,

DRVDD = 3.3 V, Fs = 40, 65 MSPS (as appropriate)/50% duty cycle, –1 dBFS input span, CL = 10 pF

at D0–D9, internal reference, T(min) to T(max), typical data at 25°C (unless otherwise noted)

(continued)

timing characteristics

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Clock duty cycle 50 ±10 %

td(o) Output propagation delay 9 12 ns

t(en) OE ↓ to outputs enabled time 6 ns

tdis OE ↑ rising to outputs 3-state disable time 10 ns

td(latency) Pipeline latency 5.5 cyc

td(ap) Aperture delay 1 ns

Aperture uncertainty 2ps rms

timing diagram

S2 S3

S1 S2 S3

12345678910

td(latency)

t(en) td(o) tdis

Analog

CLK

D[0–9] S1

ADS5102

ADS5103

SLAS351B – OCTOBER 2001 – REVISED DECEMBER 2001

8www.ti.com

TYPICAL CHARACTERISTICS

ADS5102

ANALOG SUPPLY CURRENT

TEMPERATURE

Figure 1

–40–30–20–100 102030405060708090

AVDD = DVDD = 1.8 V

DRVDD = 3.3 V

Fclk = 65 MHz

fi = 32.49 MHz at –1 dBFS

T – Temperature – °C

Analog Supply Current – mA

Figure 2

45.0

45.5

46.0

46.5

47.0

47.5

48.0

48.5

49.0

49.5

50.0

–40–30–20–100 102030405060708090

ADS5103

ANALOG SUPPLY CURRENT

TEMPERATURE

AVDD = DVDD = 1.8 V

DRVDD = 3.3 V

Fclk = 40 MHz

fi = 19.99 MHz at –1 dBFS

T – Temperature – °C

Analog Supply Current – mA

Figure 3

15.0

15.5

16.0

16.5

17.0

17.5

18.0

18.5

19.0

19.5

20.0

–40–30–20–100 102030405060708090

ADS5102

DIGITAL SUPPLY CURRENT

TEMPERATURE

AVDD = DVDD = 1.8 V

DRVDD = 3.3 V

Fclk = 65 MHz

fi = 32.49 MHz at –1 dBFS

T – Temperature – °C

Digital Supply Current – mA

Figure 4

–40–30–20–100 102030405060708090

ADS5103

DIGITAL SUPPLY CURRENT

TEMPERATURE

AVDD = DVDD = 1.8 V

DRVDD = 3.3 V

Fclk = 40 MHz

fi = 19.99 MHz at –1 dBFS

T – Temperature – °C

Digital Supply Current – mA

ADS5102

ADS5103

SLAS351B – OCTOBER 2001 – REVISED DECEMBER 2001

www.ti.com

TYPICAL CHARACTERISTICS

Figure 5

0.25

0.45

0.65

0.85

1.05

1.25

1.45

1.65

1.85

2.05

–40–30–20–100 102030405060708090

ADS5102

INTEGRAL NONLINEARITY

TEMPERATURE

AVDD = DVDD = 1.8 V

DRVDD = 3.3 V

Fclk = 65 MHz

T – Temperature – °C

INL – Integral Nonlinearity – LSB

Figure 6

0.25

0.45

0.65

0.85

1.05

1.25

1.45

1.65

1.85

2.05

–40–30–20–100 102030405060708090

ADS5103

INTEGRAL NONLINEARITY

TEMPERATURE

AVDD = DVDD = 1.8 V

DRVDD = 3.3 V

Fclk = 40 MHz

T – Temperature – °C

INL – Integral Nonlinearity – LSB

–0.3

–0.2

–0.1

0.1

0.2

0.3

0.4

0 64 128 192 256 320 384 448 512 576 640 704 768 832 896 960

DNL – Differential Nonlinearity – LSB

Code

ADS5102

DIFFERENTIAL NONLINEARITY

AVDD = DVDD = 1.8 V

DRVDD = 3.3 V

Fclk = 65 MHz

1024

Figure 7

ADS5102

ADS5103

SLAS351B – OCTOBER 2001 – REVISED DECEMBER 2001

10 www.ti.com

TYPICAL CHARACTERISTICS

–0.5

–0.4

–0.3

–0.2

–0.1

0.1

0.2

0.3

0 64 128 192 256 320 384 448 512 576 640 704 768 832 896 960

DNL – Differential Nonlinearity – LSB

Code

ADS5103

DIFFERENTIAL NONLINEARITY

AVDD = DVDD = 1.8 V

DRVDD = 3.3 V

Fclk = 40 MHz

1024

Figure 8

–0.8

–0.6

–0.4

–0.2

0.2

0.4

0.6

0.8

ADS5102

INTEGRAL NONLINEARITY

0 64 128 192 256 320 384 448 512 576 640 704 768 832 896 960

INL – Integral Nonlinearity – LSB

Code

AVDD = DVDD = 1.8 V

DRVDD = 3.3 V

Fclk = 65 MHz

1024

Figure 9

–0.6

–0.4

–0.2

0.2

0.4

0.6

0.8

ADS5103

INTEGRAL NONLINEARITY

0 64 128 192 256 320 384 448 512 576 640 704 768 832 896 960

INL – Integral Nonlinearity – LSB

Code

AVDD = DVDD = 1.8 V

DRVDD = 3.3 V

Fclk = 40 MHz

1024

Figure 10

ADS5102

ADS5103

SLAS351B – OCTOBER 2001 – REVISED DECEMBER 2001

www.ti.com

TYPICAL CHARACTERISTICS

Figure 11

0.25

0.50

0.75

1.00

1.25

1.50

1.75

2.00

1.65 1.70 1.75 1.80 1.85 1.90 1.95 2.00 2.05 2.10

ADS5102

INTERNAL VREF VALUES

ANALOG SUPPLY VOLTAGE

DVDD = 1.8 V

DRVDD = 3.3 V

Fclk = 65 MHz

fi = 32.49 MHz at –1 dBFS

Analog Supply Voltage – V

Internal Vref V alues – V

REFT-REFB

REFB

REFT

Figure 12

0.25

0.50

0.75

1.00

1.25

1.50

1.75

2.00

–40–30–20–100 102030405060708090

ADS5102

INTERNAL VREF VALUES

TEMPERATURE

AVDD = DVDD = 1.8 V

DRVDD = 3.3 V

Fclk = 65 MHz

fi = 32.49 MHz at –1 dBFS

T – Temperature – °C

Internal Vref V alues – V

REFT-REFB

REFB

REFT

Figure 13

–20 –18 –16 –14 –12 –10 –8–6–4–20

ADS5102

SPURIOUS FREE DYNAMIC RANGE

ANALOG INPUT LEVEL

AVDD = DVDD = 1.8 V

DRVDD = 3.3 V

Fclk = 65 MHz

fi = 32.49 MHz

Analog Input Level – dB

SFDR – Spurious Free Dynamic Range – dBc

Figure 14

–20 –18 –16 –14 –12 –10 –8–6–4–20

ADS5103

SPURIOUS FREE DYNAMIC RANGE

ANALOG INPUT LEVEL

AVDD = DVDD = 1.8 V

DRVDD = 3.3 V

Fclk = 40 MHz

fi = 19.99 MHz

Analog Input Level – dB

SFDR – Spurious Free Dynamic Range – dBc

ADS5102

ADS5103

SLAS351B – OCTOBER 2001 – REVISED DECEMBER 2001

12 www.ti.com

TYPICAL CHARACTERISTICS

Figure 15

–80

–78

–76

–74

–72

–70

–68

–66

0 4 8 12 16 20 24 28 32

ADS5102

TOTAL HARMONIC DISTORTION

ANALOG INPUT FREQUENCY

AVDD = DVDD = 1.8 V

DRVDD = 3.3 V

Fclk = 65 MHz

fi = 1–32 MHz at –1 dBFS

Analog Input Frequency – MHz

THD – Total Harmonic Distortion – dBc

Figure 16

–70

–68

–66

–64

–62

–60

02468101214161820

ADS5103

TOTAL HARMONIC DISTORTION

ANALOG INPUT FREQUENCY

AVDD = DVDD = 1.8 V

DRVDD = 3.3 V

Fclk = 40 MHz

fi = 1–19.99 MHz at –1 dBFS

Analog Input Frequency – MHz

THD – Total Harmonic Distortion – dBc

Figure 17

0 4 8 12 16 20 24 28 32

ADS5102

SIGNAL-TO-NOISE RATIO

ANALOG INPUT FREQUENCY

AVDD = DVDD = 1.8 V

DRVDD = 3.3 V

Fclk = 65 MHz

fi = 1–32 MHz at –1 dBFS

Analog Input Frequency – MHz

SNR – Signal-to-Noise Ratio – dBc

Figure 18

02468101214161820

ADS5103

SIGNAL-TO-NOISE RATIO

ANALOG INPUT FREQUENCY

AVDD = DVDD = 1.8 V

DRVDD = 3.3 V

Fclk = 40 MHz

fi = 1–19.99 MHz at –1 dBFS

Analog Input Frequency – MHz

SNR – Signal-to-Noise Ratio – dBc

ADS5102

ADS5103

SLAS351B – OCTOBER 2001 – REVISED DECEMBER 2001

www.ti.com

TYPICAL CHARACTERISTICS

Figure 19

0 4 8 12 16 20 24 28 32

ADS5102

SIGNAL-TO-NOISE RATIO and DISTORTION

ANALOG INPUT FREQUENCY

AVDD = DVDD = 1.8 V

DRVDD = 3.3 V

Fclk = 65 MHz

fi = 1–32 MHz at –1 dBFS

Analog Input Frequency – MHz

SINAD – Signal-to-Noise Ratio and Distortion – dBc

Figure 20

02468101214161820

ADS5103

SIGNAL-TO-NOISE RATIO and DISTORTION

ANALOG INPUT FREQUENCY

AVDD = DVDD = 1.8 V

DRVDD = 3.3 V

Fclk = 40 MHz

fi = 1–19.99 MHz at –1 dBFS

Analog Input Frequency – MHz

SINAD – Signal-to-Noise Ratio and Distortion – dBc

Figure 21

8.0

8.5

9.0

9.5

10.0

10.5

11.0

0 4 8 12 16 20 24 28 32

ADS5102

EFFECTIVE NUMBER OF BITS

ANALOG INPUT FREQUENCY

AVDD = DVDD = 1.8 V

DRVDD = 3.3 V

Fclk = 65 MHz

fi = 1–32 MHz at –1 dBFS

Analog Input Frequency – MHz

ENOB – Effective Number of Bits – Bits

Figure 22

8.0

8.5

9.0

9.5

10.0

10.5

11.0

02468101214161820

ADS5103

EFFECTIVE NUMBER OF BITS

ANALOG INPUT FREQUENCY

AVDD = DVDD = 1.8 V

DRVDD = 3.3 V

Fclk = 40 MHz

fi = 1–19.99 MHz at –1 dBFS

Analog Input Frequency – MHz

ENOB – Effective Number of Bits – Bits

ADS5102

ADS5103

SLAS351B – OCTOBER 2001 – REVISED DECEMBER 2001

14 www.ti.com

TYPICAL CHARACTERISTICS

Figure 23

0 4 8 12 16 20 24 28 32

ADS5102

SPURIOUS FREE DYNAMIC RANGE

ANALOG INPUT FREQUENCY

AVDD = DVDD = 1.8 V

DRVDD = 3.3 V

Fclk = 65 MHz

fi = 1–32 MHz at –1 dBFS

Analog Input Frequency – MHz

SFDR – Spurious Free Dynamic Range – dBc

Figure 24

02468101214161820

ADS5103

SPURIOUS FREE DYNAMIC RANGE

ANALOG INPUT FREQUENCY

AVDD = DVDD = 1.8 V

DRVDD = 3.3 V

Fclk = 40 MHz

fi = 1–19.99 MHz at –1 dBFS

Analog Input Frequency – MHz

SFDR – Spurious Free Dynamic Range – dBc

Figure 25

30 35 40 45 50 55 60 65 70

ADS5102

SFDR, SINAD

CLOCK DUTY CYCLE

AVDD = DVDD = 1.8 V

DRVDD = 3.3 V

Fclk = 65 MHz

fi = 3.58 MHz at –1 dBFS

Clock Duty Cycle – %

SFDR, SINAD – dBc

SINAD

SFDR

Figure 26

30 35 40 45 50 55 60 65 70

ADS5103

SFDR, SINAD

CLOCK DUTY CYCLE

AVDD = DVDD = 1.8 V

DRVDD = 3.3 V

Fclk = 40 MHz

fi = 3.58 MHz at –1 dBFS

Clock Duty Cycle – %

SFDR, SINAD – dBc

SINAD

SFDR

ADS5102

ADS5103

SLAS351B – OCTOBER 2001 – REVISED DECEMBER 2001

www.ti.com

TYPICAL CHARACTERISTICS

Figure 27

30 35 40 45 50 55 60 65 70

ADS5102

SFDR, SINAD

CLOCK DUTY CYCLE

AVDD = DVDD = 1.8 V

DRVDD = 3.3 V

Fclk = 65 MHz

fi = 32.49 MHz at –1 dBFS

Clock Duty Cycle – %

SFDR, SINAD – dBc

SINAD

SFDR

Figure 28

30 35 40 45 50 55 60 65 70

ADS5103

SFDR, SINAD

CLOCK DUTY CYCLE

AVDD = DVDD = 1.8 V

DRVDD = 3.3 V

Fclk = 40 MHz

fi = 19.99 MHz at –1 dBFS

Clock Duty Cycle – %

SFDR, SINAD – dBc

SINAD

SFDR

PRINCIPLES OF OPERATION

analog-to-digital converter

The ADS5102/3 is designed using a switched capacitor pipeline architecture fabricated in CMOS process. The

pipeline architecture is implemented with 10 stages, thus allowing for high conversion speed and exceptionally

low power . Each of these 10 stages produces one digital bit per stage. Both rising and falling edges of the clock

are used so the signal propagates thru the pipeline every half clock or five total clocks. Digital error correction

uses another 1/2 clock cycle at the end; thus the total pipeline latency is 5.5 clocks. (Refer to timing diagram

on page 7)

10-stage operation

The signal is sampled by the SHA. The first stage is digitized by 1.5 bits and sent to the digital error correction

block. This digitized value is then applied to a DAC, which recreates the analog value that has been digitized.

This value is then fed into a summing junction with the original input signal. The summing junction subtracts the

converted value from the original signal. This is known as the residue voltage. This residue voltage is then

amplified by a factor of 2x and transferred to the next stage. This is repeated for each of the 10 stages.

Each of the 10 pipeline stages, as well as the sample and hold amplifier, is differential in nature. This allows

rejection of any common mode signal. Thus a signal seen on Ain+ and Ain– is differentially seen as 0 V on the

output. This fully differential architecture allows higher ac performance of the ADC by reducing noise

susceptibility.

ADS5102

ADS5103

SLAS351B – OCTOBER 2001 – REVISED DECEMBER 2001

16 www.ti.com

PRINCIPLES OF OPERATION

analog input sample and hold amplifier circuit

The sample and hold amplifier is implemented using switch capacitor techniques. A simplified functional block

diagram is shown in Figure 29. The SHA is in sample mode when CLK is high and in hold mode when CLK is

low. In sample mode, the input switches, P1, are closed and the differential input signal is sampled onto caps

Cs. An internal common-mode voltage is applied to the sampling caps (Cs) when the two P1P switches are

closed. As the CLK falling edge occurs, the SHA is now placed into hold or amplification mode. In this mode,

P1 switches are now opened and switches P2 are closed. This is the amplification state and the signal is

transferred to the output of the amplifier with a nominal gain of 1. CL of Figure 29 represents the load

capacitance of the following stage. R-C values of the input determine the analog input bandwidth of the SHA

(and therefore the whole ADC) which is 950 MHz for the ADS5102/3. This wide bandwidth assures no distortion

to the Nyquist frequency of 32.5 MHz. In under sampling applications, it is common to require the analog input

bandwidth to be 5 times greater than the IF Nyquist frequency . As such, the ADS5102/3 supports IF frequencies

approaching 200 MHz in under sampling applications.

+P1 CL

P1P

VINP

VIN

Figure 29. Simplified Functional Block Diagram

Because the input to the sample and hold amplifier is a switched capacitor circuit, the input resistance is dynamic

and based on the sampling rate of the converter. The impedance of each input is defined by the equation:

ZI+1

F Cs

Where:

Cs = Sampling capacitor = 0.4 pF typical

F = CLK frequency in Hz

The key for selecting an amplifier to correctly drive the ADS5102/3 is to ensure that the output frequency of the

amplifier is much lower than the input impedance of the ADS5102/3, which at 65 MSPS is 38.46 kΩ . For system

accuracy comparable to 1 LSB, this means selecting an amplifier with output impedance of ~ 31 Ω for sampling

rates of 65 MSPS.

reference configurations

The ADS5102/3 provides an internal voltage reference which should be suitable for most 10 bit systems. The

typical full scale voltage for the device is determined by VFS = VREFT – VREFB. Since the input is fully

differential, the full scale input is twice the single ended value or 1 V differential. It is recommended to externally

de-couple both VREFT and VREFB with a 0.1 µF capacitor to bypass all high frequency noise to ground. It is

necessary to connect BG and AVDD with a 100 kΩ resistor and decouple with a 1 µF capacitor to AGND (refer

to Figure 30 for correct configuration).

ADS5102

ADS5103

SLAS351B – OCTOBER 2001 – REVISED DECEMBER 2001

www.ti.com

PRINCIPLES OF OPERATION

100 kΩ

1 µF

AVDD

Figure 30. BG Reference Configuration

For systems that require more absolute accuracy or lower temperature coefficient drift than provided by the

internal VREF, an external voltage reference can be applied to the VREFB and VREFT inputs. To use external

reference, connect the PDREF pin to a logic high and this internally disconnects the VREF from the ADC. In

this mode it is also necessary to connect the BG and REFT pins together on the PWB. It is recommended to

use the input levels of VREFB = 0.75 V and VREFB = 1.25 V to achieve optimum ADC performance. It is also

recommended to apply a common-mode voltage to the input of 1 V.

clock input

The clock input is designed for 1.8 V or 3.3 V CMOS logic levels (depends on DRVDD) and it is recommended

to use standard CMOS logic levels as inputs. The logic threshold internally is set to DRVDD/2 or nominally 1.65

V. Since both edges of the clock are used in the switch capacitor architecture, it is important to provide a clock

with (ideally) a 50% duty cycle. The performance variation with clock duty cycle can be examined from

Figures 25, 26, 27 and 28.

Clock jitter is also important for performance of the ADC to be maintained. Any clock jitter appears as noise when

sampling input frequencies. Clock Jitter reduces the signal to noise ratio (SNR) and is more severe as the input

frequency increases. The theoretical SNR limits based on clock jitter can be calculated as follows:

Theoretical SNR(clock jitter) (dB) +20 log ǒ1

2 p FI CLK(jitter)Ǔ

Where:

FI = Highest input frequency to the ADC in Hz

CLK(jitter) = the amount of jitter on the clock in sec

Therefore for a Nyquist frequency input of 32.5 MHz and a design trying to achieve the most available

performance from the ADS5102/3, the clock jitter must be less than 3.98 ps rms. In under sampling applications,

the same equations apply and clock jitter becomes more critical and may be the limiting factor in system

performance. The aperture jitter of the SHA also contributes to overall jitter. For worst case designs, the jitter

of clock and aperture can be considered to add in quadrature, i.e.

Total Jitter = Square root of ( CLKjitter2 + Aperturejitter 2)

The aperture jitter of the ADS5103 is 2 ps rms and at frequencies approaching Nyquist, the total jitter should

be accounted for.

ADS5102

ADS5103

SLAS351B – OCTOBER 2001 – REVISED DECEMBER 2001

18 www.ti.com

PRINCIPLES OF OPERATION

digital outputs

The outputs of the ADS5102/3 are also CMOS and are programmable for either 3.3 V or 1.8 V CMOS logic

levels. This is controlled by the DRVDD supply. Either 3.3 V or 1.8 V can be applied to DRVDD with excellent

results. The output format is offset binary with D0 (LSB) and D9 (MSB). See Table 1 for output coding with a

differential input signal applied. There is a 5.5 clock latency from the sampling to valid data output on D0–D9.

The outputs can be placed into active mode by taking OE low or 3-state by taking OE high. The timing relations

between OE and output bus enable/disable times are shown in the timing diagram (refer to page 7). The

capacitive loading on the digital outputs is very important to achieve best performance. The total load

capacitance is typically made up of two sources, next stage input capacitance and PWB etch run capacitance.

The total capacitance of these two loads should be held to less than 15 pF. If for some reason, this cannot be

met, it is recommended to use logic buffers such as ‘244 placed physically very close to the ADC output. This

isolates the ADC output from the load capacitance and performance specs are achieved. Another technique

is to place a small resistor in series with the outputs. This resistance dampens the current spikes into the

capacitive loads and thus improve ADC performance. The value of this resistor varies with sampling rate but

generally 22 Ω is a good value. Again this depends on the load capacitance.

The digital output of these devices is offset binary and follows the following format.

Table 1. Output Coding

ANALOG INPUT SIGNAL VOLTAGE

STEP

DIGITAL OUTPUT CODE

ANALOG

INPUT

IN +

SIGNAL

VOLTAGE

IN –STEP MSB LSB

REFT†REFB†1023 1 1 1 1 1 1 1 1 1 1

• • • • • • • • • • • • •

(REFT – REFB) / 2 (REFT – REFB) / 2 512 1 0 0 0 0 0 0 0 0 0

• • 511 0 1 1 1 1 1 1 1 1 1

• • • • • • • • • • • • •

REFB REFT 0 0 0 0 0 0 0 0 0 0 0

†Where there is either an internal voltage reference or an external voltage reference applied to the REFT and REFB pins.

driving the analog input

Since many real world signals are single ended and most modern high speed ADC’s employ dif ferential inputs,

it is necessary in many cases to perform single ended to differential conversion prior to the ADC. Also, the ADC

performs optimally if a differential signal is applied to the inputs. In some cases, signal conditioning is required

in the form of the amplification or filtering. The two preferred techniques for driving the ADC input are: 1) With

an active amplifier specifically designed to drive ADC’s; 2) With an RF transformer.

driving the analog input with a differential amplifier

Texas Instruments has developed a family of high quality operational amplifiers that have been designed

specifically for driving the input stage of modern ADC’s. These devices allow for amplification and filtering prior

to the ADC. This stage can be used to set the maximum signal voltage to match the full scale input of the ADC.

The best solution for driving the ADS5102/3 ADC’s is the THS4501 amplifier. Figure 31 shows how to use this

device with a gain of 2. The ADC common mode output voltage can be directly connected to the op amp to

provide the proper levels. The THS4501 provides optimum matching of op amp output to the input of the

ADS5102/3. This configuration provides signal amplification, filtering, and single-ended to differential

conversion. It is recommended to provide de-coupling capacitors of 0.1 µF and 0.001 µF on the CML output.

This filters out any high frequency noise prior the ADC input.

ADS5102

ADS5103

SLAS351B – OCTOBER 2001 – REVISED DECEMBER 2001

www.ti.com

PRINCIPLES OF OPERATION

+VO–

VO+

VOCM

THS4501

68 pF

49.9 Ω

AIN–

AIN+ CML

ADS5102,

ADS5103

750 Ω

374 Ω

374 ΩDigital

Outputs

V(source)

0.001 µF0.1 µF

Figure 31. Driving the ADS5102/3 With Differential Amp (Gain = 2)

driving the analog input with a transformer

When little or no signal conditioning is required, a simple transformer is an excellent way to drive the input of

the ADS5102/3 family. The transformer provides single-ended to differential conversion and at frequencies

under 200 MHz produces very little distortion of the incoming signal. Figure 32 shows the preferred circuit

diagram for implementing a transformer-coupled input. The signal source is ac-coupled and fed to the primary

side of the RF transformer . Since the ADC input must be biased to the correct common mode voltage, the CML

output of the ADC is connected to the secondary center tap. It is recommended to provide decoupling capacitors

of 0.1 µF and 0.001 µF on the CML output. This filters out any high frequency noise prior the ADC input.

AIN–

AIN+

ADS5102,

ADS5103

V(source)

0.1 µF0.001 µF

T1 – 1T-KK81

Mini-Circuits

49.9 Ω

0.1 µF

Digital

Outputs

CML

Figure 32. Driving the ADS5102/3 With a Transformer

ADS5102

ADS5103

SLAS351B – OCTOBER 2001 – REVISED DECEMBER 2001

20 www.ti.com

PRINCIPLES OF OPERATION

3 kΩ

REFT

AIN–

AIN+

REFB

AIN+

AIN–

ADS5102

ADS5103

Figure 33. Driving the Analog Inputs

setting the bias resistor—RBIAS

Each device in this family requires an external resistor be connected from pin 14 to ground. The value of this

resistor is determined by which device is being used. Refer to Table 2 for the correct resistor value. This resistor

only dissipates less than 1 mW of power. The resistor accuracy of 1% is adequate.

Table 2. Resistor Value

DEVICE RBIAS VALUE CONNECT FROM

ADS5103 8.25 kΩ

Pin 14 to AGND

ADS5102 4.42 kΩPin 14 to AGND

ADS5102

ADS5103

SLAS351B – OCTOBER 2001 – REVISED DECEMBER 2001

www.ti.com

DEFINITION OF SPECIFICATIONS

Analog Input Bandwidth—The analog input frequency at which the spectral power of the fundamental

frequency (as determined by the FFT analysis) is reduced by 3 dB.

Aperture Delay—The delay between the 50% point of the rising edge of the clock and the instant at which the

analog input is sampled.

Aperture Uncertainity (Jitter)—The sample-to-sample variation in aperture delay.

Differential Nonlinearity (DNL)—The maximum deviation of any single LSB transition at the digital output from

an ideal 1 LSB step at the analog input. Ideally, each transition step is 1 LSB wide. DNL is the measured error

from theoretical in step size. A DNL of less than –1 LSB implies no missing codes.

Integral Nonlinearity (INL)—is the summation of the differential nonlinearity errors and indicates the worst

case deviation from an best fit straight line that is drawn from 1/2 LSB of the first transition to 1/2 LSB above

the last transition. The best fit is determined using the least squares curve fitting method.

Duty Cycle—is the ratio of the clock time high over the full clock period (time high plus time low) and then also

the time low over the total clock period. At a given clock rate, these specs define the acceptable duty cycle

allowed on the clock.

Sampling Rate (Fs)—The rate at which the converter tested to ensure conversion of analog signals to digital.

The maximum rate specified is the rate and which the device is production tested to ensure performance specs

are met. Expressed in mega samples per second (MSPS).

Output Propagation Delay—The delay between the 50% point of the falling edge of clock signal and the time

when all output data bits are within valid logic levels.

Offset Error—In an ideal ADC the first transition from 0000000000 should occur at 1/2 LSB above REFB. Offset

Error is defined as the difference between this ideal first transition and the voltage level where the first transition

actually occurs. Expressed in % full scale range (%FSR) but may also be expressed in volts. This can be thought

of as shifting the transfer function either left or right along the X-axis.

Overvoltage Recovery Time—The amount of time required for the converter to recover to 0.2% accuracy after

an analog input signal 150% of full scale is reduced to midscale.

Power Supply Rejection Ratio—The ratio of a change in input offset voltage to a change in power supply

voltage.

Total Harmonic Distortion (THD)—The ratio of the peak signal amplitude to the summation of the harmonic

components. This is expressed in – dB. THD = 20 Log [input amplitude/(summation of harmonic bins)]. For

calculation purposes, the first 7 harmonics are included in the calculations.

Signal To Noise Distortion (SINAD)—The ratio of the rms signal amplitude (set 1 dB below full scale) to rms

value of the sum of all other spectral noise and harmonic components, but excluding dc.

Signal to Noise Ratio (SNR)—The ratio of the rms signal amplitude (set at 1 dB below full scale) to the rms

value of the the sum of all other spectral components, excluding the first five harmonics and dc. Reported in

dB.

Spurious Free Dynamic Range (SFDR)—The difference between the peak amplitude of a fundamental input

sine wave and the largest peak spurious component that appears, excluding dc and the input. The peak

spurious component may or may not be a harmonic frequency . May be reported in dBc (i.e., degrades as signal

levels is lowered), or in dBFS (always related back to converter full scale).

PACKAGE OPTION ADDENDUM

www.ti.com 30-Jul-2011

Addendum-Page 1

PACKAGING INFORMATION

Orderable Device Status (1) Package Type Package

Drawing Pins Package Qty Eco Plan (2) Lead/

Ball Finish MSL Peak Temp (3) Samples

(Requires Login)

ADS5103IPFB ACTIVE TQFP PFB 48 250 Green (RoHS

& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR

ADS5103IPFBG4 ACTIVE TQFP PFB 48 250 Green (RoHS

& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR

(1) The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability

information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that

lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between

the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight

in homogeneous material)

(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

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