4-40
CAUTION: These devices are sensitive to electrostatic discharge; follow proper ESD Handling Procedures.
UltraFET™ is a trademark of Intersil Corporation. PSPICE® is a trademark of MicroSim Corporation.
SABER is a Copyright of Analogy, Inc. http://www.intersil.com or 407-727-9207 |Copyright © Intersil Corporation 1999
HUF75307P3, HUF75307D3, HUF75307D3S
15A, 55V, 0.090 Ohm, N-Channel UltraFET
Power MOSFETs
These N-Channel power MOSFETs
are manufactured using the
innovative UltraFET™ process.
This advanced process technology
achieves the lowest possible on-resistance per silicon area,
resulting in outstanding performance. This device is capable
of withstanding high energy in the avalanche mode and the
diode exhibits very low reverse recovery time and stored
charge. It was designed for use in applications where power
efficiency is important, such as switching regulators,
switching converters, motor drivers, relay drivers, low-
voltage bus switches, and power management in portable
and battery-operated products.
Formerly developmental type TA75307.
Features
• 15A, 55V
• Simulation Models
- Temperature Compensated PSPICE® and SABER©
Models
- SPICE and SABER Thermal Impedance Models
Available on the WEB at:
www.semi.Intersil .com/families/models.htm
• Peak Current vs Pulse Width Curve
• UIS Rating Curve
• Related Literature
- TB334, “Guidelines for Soldering Surface Mount
Components to PC Boards”
Symbol
Packaging
Ordering Information
PART NUMBER PACKAGE BRAND
HUF75307P3 TO-220AB 75307P
HUF75307D3 TO-251AA 75307D
HUF75307D3S TO-252AA 75307D
NOTE: When ordering, use the entire part number. Add the suffix T to
obtain the TO-252AA variant in tape and reel, e.g., HUF75307D3ST.
D
G
S
JEDEC TO-220AB JEDEC TO-251AA
JEDEC TO-252AA
DRAIN
SOURCE
GATE
DRAIN
(FLANGE)
SOURCE
DRAIN
GATE
DRAIN
(FLANGE)
GATE
SOURCE
DRAIN
(FLANGE)
Data Sheet June 1999 File Number
4353.6
4-41
Absolute Maximum Ratings TC= 25oC, Unless Otherwise Specified UNITS
Drain to Source Voltage (Note 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .VDSS 55 V
Drain to Gate Voltage (RGS = 20kΩ) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .VDGR 55 V
Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .V
GS ±20 V
Drain Current
Continuous (Figure 2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .ID
Pulsed Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IDM 15
Figure 4 A
Pulsed Avalanche Rating. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EAS Figures 6, 14, 15
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PD
Derate Above 25oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
0.3 W
W/oC
Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ, TSTG -55 to 175 oC
Maximum Temperature for Soldering
Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TL
Package Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Tpkg 300
260
oC
oC
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operationofthe
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. TJ = 25oC to 150oC.
Electrical Specifications TC = 25oC, Unless Otherwise Specified
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
OFF STATE SPECIFICATIONS
Drain to Source Breakdown Voltage BVDSS ID = 250µA, VGS = 0V (Figure 11) 55 - - V
Zero Gate Voltage Drain Current IDSS VDS = 50V, VGS = 0V - - 1 µA
VDS = 45V, VGS = 0V, TC = 150oC - - 250 µA
Gate to Source Leakage Current IGSS VGS = ±20V - - ±100 nA
ON STATE SPECIFICATIONS
Gate to Source Threshold Voltage VGS(TH) VGS = VDS, ID = 250µA (Figure 10) 2 - 4 V
Drain to Source On Resistance rDS(ON) ID = 15A, VGS = 10V (Figure 9) - 0.075 0.090 Ω
THERMAL SPECIFICATIONS
Thermal Resistance Junction to Case RθJC (Figure 3) - - 3.3 oC/W
Thermal Resistance Junction to Ambient RθJA TO-220AB - - 62 oC/W
TO-251AA, TO-252AA - - 100 oC/W
SWITCHING SPECIFICATIONS (VGS = 10V)
Turn-On Time tON VDD = 30V, ID≅ 15A,
RL = 2.0Ω, VGS =10V,
RGS = 100Ω
- - 60 ns
Turn-On Delay Time td(ON) -7-ns
Rise Time tr-40- ns
Turn-Off Delay Time td(OFF) -35- ns
Fall Time tf-45- ns
Turn-Off Time tOFF - - 100 ns
GATE CHARGE SPECIFICATIONS
Total Gate Charge Qg(TOT) VGS = 0V to 20V VDD = 30V,
ID≅ 15A,
RL = 2.0Ω
Ig(REF) = 1.0mA
(Figure13)
-1620nC
Gate Charge at 10V Qg(10) VGS = 0V to 10V - 9 11 nC
Threshold Gate Charge Qg(TH) VGS = 0V to 2V - 0.6 0.8 nC
Gate to Source Gate Charge Qgs - 1.2 - nC
Reverse Transfer Capacitance Qgd -4-nC
HUF75307P3, HUF75307D3, HUF75307D3S
4-42
CAPACITANCE SPECIFICATIONS
Input Capacitance CISS VDS = 25V, VGS = 0V,
f = 1MHz
(Figure 12)
- 250 - pF
Output Capacitance COSS - 100 - pF
Reverse Transfer Capacitance CRSS -25-pF
Electrical Specifications TC = 25oC, Unless Otherwise Specified
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
Source to Drain Diode Specifications
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
Source to Drain Diode Voltage VSD ISD = 15A - - 1.25 V
Reverse Recovery Time trr ISD = 15A, dISD/dt = 100A/µs--45ns
Reverse Recovered Charge QRR ISD = 15A, dISD/dt = 100A/µs--55nC
Typical Performance Curves
FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE
TEMPERATURE FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs
CASE TEMPERATURE
FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE
TC, CASE TEMPERATURE (oC)
POWER DISSIPATION MULTIPLIER
00 25 50 75 100 150
0.2
0.4
0.6
0.8
1.0
1.2
125 175
5
10
15
20
50 75 100 125 150 175
025
ID, DRAIN CURRENT (A)
TC, CASE TEMPERATURE (oC)
0.1
1
101
100
10-1
10-2
10-3
10-4
0.01
2
10-5
t, RECTANGULAR PULSE DURATION (s)
SINGLE PULSE
NOTES:
DUTY FACTOR: D = t1/t2
PEAK TJ = PDM x ZθJC x RθJC + TC
PDM
t1t2
DUTY CYCLE - DESCENDING ORDER
0.5
0.2
0.1
0.05
0.01
0.02
ZθJC, NORMALIZED
THERMAL IMPEDANCE
HUF75307P3, HUF75307D3, HUF75307D3S
4-43
FIGURE 4. PEAK CURRENT CAPABILITY
FIGURE 5. FORWARD BIAS SAFE OPERATING AREA NOTE: Refer to Intersil Application Notes AN9321 and AN9322.
FIGURE 6. UNCLAMPED INDUCTIVE SWITCHING CAPABILITY
FIGURE 7. SATURATION CHARACTERISTICS FIGURE 8. TRANSFER CHARACTERISTICS
Typical Performance Curves
(Continued)
100
101
100
10-1
10-2
10-3
10-4
10-5
10
200 TC = 25oC
I = I25 175 - TC
150
FOR TEMPERATURES
ABOVE 25oC DERATE PEAK
CURRENT AS FOLLOWS:
VGS = 10V
IDM, PEAK CURRENT (A)
t, PULSE WIDTH (s)
TRANSCONDUCTANCE
MAY LIMIT CURRENT
IN THIS REGION
1
10
100
10 100
0.1
1 200
VDS, DRAIN TO SOURCE VOLTAGE (V)
ID, DRAIN CURRENT (A)
TJ = MAX RATED
TC = 25oC
100µs
10ms
1ms
VDSS(MAX) = 55V
LIMITED BY rDS(ON)
AREA MAY BE
OPERATION IN THIS
10
100
0.01 0.1 1 10
0.001
1
200
IAS, AVALANCHE CURRENT (A)
tAV, TIME IN AVALANCHE (ms)
tAV = (L)(IAS)/(1.3*RATED BVDSS - VDD)
If R = 0
If R ≠ 0
tAV = (L/R)ln[(IAS*R)/(1.3*RATED BVDSS - VDD) +1]
STARTING TJ = 25oC
STARTING TJ = 150oC
5
10
15
20
25
12345
0
0
ID, DRAIN CURRENT (A)
VDS, DRAIN TO SOURCE VOLTAGE (V)
VGS = 6V
PULSE DURATION = 80µs
TC = 25oC
VGS = 5V
VGS = 7V
VGS = 10V
VGS = 20V
DUTY CYCLE = 0.5% MAX
5
10
15
20
25
1.5 3.0 4.5 6.0 7.50
0
ID, DRAIN CURRENT (A)
VGS, GATE TO SOURCE VOLTAGE (V)
175oC
-55oC
25oC
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
VDD = 15V
HUF75307P3, HUF75307D3, HUF75307D3S
4-44
FIGURE 9. NORMALIZED DRAIN TO SOURCE ON
RESISTANCE vs JUNCTION TEMPERATURE FIGURE 10. NORMALIZED GATE THRESHOLD VOLTAGE vs
JUNCTION TEMPERATURE
FIGURE 11. NORMALIZED DRAIN TO SOURCE BREAKDOWN
VOLTAGE vs JUNCTION TEMPERATURE FIGURE 12. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE
NOTE: Refer to Intersil Application Notes AN7254 and AN7260.
FIGURE 13. GATE CHARGE WAVEFORMS FOR CONSTANT GATE CURRENT
Typical Performance Curves
(Continued)
1.0
1.5
2.0
2.5
-40 0 40 80 120 160 200
0.5
-80
NORMALIZED DRAIN TO SOURCE
TJ, JUNCTION TEMPERATURE (oC)
ON RESISTANCE
PULSE DURATION = 80µs
VGS = 10V, ID = 15A
DUTY CYCLE = 0.5% MAX
NORMALIZED GATE
TJ, JUNCTION TEMPERATURE (oC)
THRESHOLD VOLTAGE
VGS = VDS, ID = 250µA
0.8
1.0
1.2
-40 0 40 80 120 160 200-80
0.6
1.0
1.1
1.2
-40 0 40 80 120 160 200-80
0.9
TJ, JUNCTION TEMPERATURE (oC)
NORMALIZED DRAIN TO SOURCE
ID = 250µA
BREAKDOWN VOLTAGE
100
200
300
400
10 20 30 40 50 60
0
0
C, CAPACITANCE (pF)
VDS, DRAIN TO SOURCE VOLTAGE (V)
CISS
COSS
CRSS
VGS = 0, f = 1MHz
CISS = CGS + CGD
CRSS = CGD
COSS ≈ CDS + CGD
2
4
6
8
10
2468100
0
VGS, GATE TO SOURCE VOLTAGE (V)
VDD = 30V
Qg, GATE CHARGE (nC)
ID = 15A
ID = 12A
ID = 7.5A
ID= 4A
WAVEFORMS IN
DESCENDING ORDER:
HUF75307P3, HUF75307D3, HUF75307D3S
4-45
Test Circuits and Waveforms
FIGURE 14. UNCLAMPED ENERGY TEST CIRCUIT FIGURE 15. UNCLAMPED ENERGY WAVEFORMS
FIGURE 16. GATE CHARGE TEST CIRCUIT FIGURE 17. GATE CHARGE WAVEFORM
FIGURE 18. SWITCHING TIME TEST CIRCUIT FIGURE 19. RESISTIVE SWITCHING WAVEFORMS
tP
VGS
0.01Ω
L
IAS
+
-
VDS
VDD
RG
DUT
VARY tP TO OBTAIN
REQUIRED PEAK IAS
0V
VDD
VDS
BVDSS
tP
IAS
tAV
0
RL
VGS +
-
VDS
VDD
DUT
IG(REF)
VDD
Qg(TH)
VGS = 2V
Qg(10)
VGS = 10V
Qg(TOT)
VGS = 20V
VDS
VGS
Ig(REF)
0
0
Qgs Qgd
VGS
RL
RGS DUT
+
-VDD
VDS
VGS
tON
td(ON)
tr
90%
10%
VDS 90%
10%
tf
td(OFF)
tOFF
90%
50%
50%
10% PULSE WIDTH
VGS
0
0
HUF75307P3, HUF75307D3, HUF75307D3S
4-46
PSPICE Electrical Model
.SUBCKT HUF75307 2 1 3 ; rev June 1997
CA 12 8 4.5e-10
CB 15 14 4.1e-10
CIN 6 8 2.154e-10
DBODY 7 5 DBODYMOD
DBREAK 5 11 DBREAKMOD
DPLCAP 10 5 DPLCAPMOD
EBREAK 11 7 17 18 56
EDS 14 8 5 8 1
EGS 13 8 6 8 1
ESG 6 10 6 8 1
EVTHRES 6 21 19 8 1
EVTEMP 20 6 18 22 1
IT 8 17 1
LDRAIN 2 5 1e-9
LGATE 1 9 5.97e-10
LSOURCE 3 7 2.39e-9
K1 LGATE LSOURCE 0.131
MMED 16 6 8 8 MMEDMOD
MSTRO 16 6 8 8 MSTROMOD
MWEAK 16 21 8 8 MWEAKMOD
RBREAK 17 18 RBREAKMOD 1
RDRAIN 50 16 RDRAINMOD 1e-3
RGATE 9 20 1.9
RLDRAIN 2 5 10
RLGATE 1 9 60
RLSOURCE 3 7 24
RSLC1 5 51 RSLCMOD 1e-6
RSLC2 5 50 1e3
RSOURCE 8 7 RSOURCEMOD 5.5e-2
RVTHRES 22 8 RVTHRESMOD 1
RVTEMP 18 19 RVTEMPMOD 1
S1A 6 12 13 8 S1AMOD
S1B 13 12 13 8 S1BMOD
S2A 6 15 14 13 S2AMOD
S2B 13 15 14 13 S2BMOD
VBAT 22 19 DC 1
ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*35),4))}
.MODEL DBODYMOD D (IS=1.6e-13 RS=1.28e-2 IKF=5.5 N=0.985 TRS1=2.9e-3 TRS2=-4e-6 CJO=3.5e-10 TT=3.1e-8 M=0.45 XTI=6)
.MODEL DBREAKMOD D (RS=2.5e-1 IKF=0.1 TRS1=-4e-3 TRS2=3e-5)
.MODEL DPLCAPMOD D (CJO=5e-10 IS=1e-30 N=10 M=0.95)
.MODEL MMEDMOD NMOS (VTO=3.25 KP=2.2 IS=1e-30 N=10 TOX=1 L=1u W=1u RG=1.9)
.MODEL MSTROMOD NMOS (VTO=3.75 KP=14.75 IS=1e-30 N=10 TOX=1 L=1u W=1u)
.MODEL MWEAKMOD NMOS (VTO=2.88 KP=0.03 IS=1e-30 N=10 TOX=1 L=1u W=1u RG=19 RS=0.1)
.MODEL RBREAKMOD RES (TC1=1.12e-3 TC2=1e-6)
.MODEL RDRAINMOD RES (TC1=2.3e-1 TC2=6e-4)
.MODEL RSLCMOD RES (TC1=4e-3 TC2=1e-6)
.MODEL RSOURCEMOD RES (TC1=1e-3 TC2=6e-6)
.MODEL RVTHRESMOD RES (TC=-3.31e-3 TC2=-1.49e-5)
.MODEL RVTEMPMOD RES (TC1=-1.4e-3 TC2=1e-9)
.MODEL S1AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-8.1 VOFF=-4)
.MODEL S1BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-4 VOFF=-8.1)
.MODEL S2AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=0 VOFF=2)
.MODEL S2BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=2 VOFF=0)
.ENDS
NOTE: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global
Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank Wheatley.
18
22
+-
6
8
+
-
5
51
+
-
19
8
+-
17
18
6
8
+
-
5
8+
-
RBREAK
RVTEMP
VBAT
RVTHRES
IT
17 18
19
22
12
13
15
S1A
S1B
S2A
S2B
CA CB
EGS EDS
14
8
13
814
13
MWEAK
EBREAK DBODY
RSOURCE
SOURCE
11
73
LSOURCE
RLSOURCE
CIN
RDRAIN
EVTHRES 16
21
8
MMED
MSTRO
DRAIN
2
LDRAIN
RLDRAIN
DBREAK
DPLCAP
ESLC
RSLC1
10
5
51
50
RSLC2
1
GATE RGATE EVTEMP
9
ESG
LGATE
RLGATE 20
+
-
+
-
+
-
6
HUF75307P3, HUF75307D3, HUF75307D3S
4-47
SABER Electrical Model
REV February 1999
template huf75307 n2, n1, n3
electrical n2, n1, n3
{
var i iscl
d..model dbodymod = (is = 1.6e-13, xti = 6, cjo = 3.5e-10, tt = 3.1e-8, n = 0.985, m = 0.45)
d..model dbreakmod = ()
d..model dplcapmod = (cjo = 5e-10, is = 1e-30, n = 10, m = 0.95)
m..model mmedmod = (type=_n, vto = 3.25, kp = 2.2, is = 1e-30, tox = 1)
m..model mstrongmod = (type=_n, vto = 3.75, kp = 14.75, is = 1e-30, tox = 1)
m..model mweakmod = (type=_n, vto = 2.88, kp = 0.03, is = 1e-30, tox = 1)
sw_vcsp..model s1amod = (ron = 1e-5, roff = 0.1, von = -8.1, voff = -4)
sw_vcsp..model s1bmod = (ron = 1e-5, roff = 0.1, von = -4, voff = -8.1)
sw_vcsp..model s2amod = (ron = 1e-5, roff = 0.1, von = 0, voff = 2)
sw_vcsp..model s2bmod = (ron = 1e-5, roff = 0.1, von = 2, voff = 0)
c.ca n12 n8 = 4.5e-10
c.cb n15 n14 = 4.1e-10
c.cin n6 n8 = 2.154e-10
d.dbody n7 n71 = model=dbodymod
d.dbreak n72 n11 = model=dbreakmod
d.dplcap n10 n5 = model=dplcapmod
i.it n8 n17 = 1
l.ldrain n2 n5 = 1e-9
l.lgate n1 n9 = 5.97e-10
l.lsource n3 n7 = 2.39e-9
m.mmed n16 n6 n8 n8 = model=mmedmod, l = 1u, w = 1u
m.mstrong n16 n6 n8 n8 = model=mstrongmod, l = 1u, w = 1u
m.mweak n16 n21 n8 n8 = model=mweakmod, l = 1u, w = 1u
res.rbreak n17 n18 = 1, tc1 = 1.12e-3, tc2 = 1e-6
res.rdbody n71 n5 = 1.28e-2, tc1 = 2.9e-3, tc2 = -4e-6
res.rdbreak n72 n5 = 0.25, tc1 = -4e-3, tc2 = 3e-5
res.rdrain n50 n16 = 1e-3, tc1 = 2.31-1, tc2 = 6e-4
res.rgate n9 n20 = 1.9
res.rldrain n2 n5 = 10
res.rlgate n1 n9 = 60
res.rlsource n3 n7 = 24
res.rslc1 n5 n51 = 1e-6, tc1 = 4e-3, tc2 = 1e-6
res.rslc2 n5 n50 = 1e3
res.rsource n8 n7 = 5.5e-2, tc1 = 1e-3, tc2 = 6e-6
res.rvtemp n18 n19 = 1, tc1 = -1.4e-3, tc2 = 1e-9
res.rvthres n22 n8 = 1, tc1 = -3.31e-3, tc2 = -1.49e-5
spe.ebreak n11 n7 n17 n18 = 56
spe.eds n14 n8 n5 n8 = 1
spe.egs n13 n8 n6 n8 = 1
spe.esg n6 n10 n6 n8 = 1
spe.evtemp n20 n6 n18 n22 = 1
spe.evthres n6 n21 n19 n8 = 1
sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod
sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod
sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod
sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod
v.vbat n22 n19 = dc = 1
equations {
i (n51->n50) + = iscl
iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6/35))** 4))
}
}
18
22
+-
6
8
+
-
19
8
+-
17
18
6
8
+
-
5
8+
-
RBREAK
RVTEMP
VBAT
RVTHRES
IT
17 18
19
22
12
13
15
S1A
S1B
S2A
S2B
CA CB
EGS EDS
14
8
13
814
13
MWEAK
EBREAK DBODY
RSOURCE
SOURCE
11
73
LSOURCE
RLSOURCE
CIN
RDRAIN
EVTHRES 16
21
8
MMED
MSTRO
DRAIN
2
LDRAIN
RLDRAIN
DBREAK
DPLCAP
ISCL
RSLC1
10
5
51
50
RSLC2
1
GATE RGATE EVTEMP
9
ESG
LGATE
RLGATE 20
+
-
+
-
+
-
6
RDBODY
RDBREAK
72
71
HUF75307P3, HUF75307D3, HUF75307D3S
4-48
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time with-
out notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is gr anted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see w eb site http://www.intersil.com
SPICE Thermal Model
REV February 1999
HUF75307
CTHERM1 th 6 8.0e-4
CTHERM2 6 5 1.6e-3
CTHERM3 5 4 1.9e-3
CTHERM4 4 3 2.6e-3
CTHERM5 3 2 5.5e-3
CTHERM6 2 tl 1.8e-2
RTHERM1 th 6 8.0e-3
RTHERM2 6 5 2.1e-2
RTHERM3 5 4 2.2e-1
RTHERM4 4 3 6.4e-1
RTHERM5 3 2 7.7e-1
RTHERM6 2 tl 1.0
SABER Thermal Model
SABER thermal model HUF75307
template thermal_model th tl
thermal_c th, tl
{
ctherm.ctherm1 th 6 = 8.0e-4
ctherm.ctherm2 6 5 = 1.6e-3
ctherm.ctherm3 5 4 = 1.9e-3
ctherm.ctherm4 4 3 = 2.6e-3
ctherm.ctherm5 3 2 = 5.5e-3
ctherm.ctherm6 2 tl = 1.8e-2
rtherm.rtherm1 th 6 = 8.0e-3
rtherm.rtherm2 6 5 = 2.1e-2
rtherm.rtherm3 5 4 = 2.2e-1
rtherm.rtherm4 4 3 = 6.4e-1
rtherm.rtherm5 3 2 = 7.7e-1
rtherm.rtherm6 2 tl = 1.0
}
RTHERM4
RTHERM6
RTHERM5
RTHERM3
RTHERM2
RTHERM1
CTHERM4
CTHERM6
CTHERM5
CTHERM3
CTHERM2
CTHERM1
tl
2
3
4
5
6
th JUNCTION
CASE
HUF75307P3, HUF75307D3, HUF75307D3S
4-40
CAUTION: These devices are sensitive to electrostatic discharge; follow proper ESD Handling Procedures.
UltraFET™ is a trademark of Intersil Corporation. PSPICE® is a trademark of MicroSim Corporation.
SABER is a Copyright of Analogy, Inc. http://www.intersil.com or 407-727-9207 |Copyright © Intersil Corporation 1999
HUF75307P3, HUF75307D3, HUF75307D3S
15A, 55V, 0.090 Ohm, N-Channel UltraFET
Power MOSFETs
These N-Channel power MOSFETs
are manufactured using the
innovative UltraFET™ process.
This advanced process technology
achieves the lowest possible on-resistance per silicon area,
resulting in outstanding performance. This device is capable
of withstanding high energy in the avalanche mode and the
diode exhibits very low reverse recovery time and stored
charge. It was designed for use in applications where power
efficiency is important, such as switching regulators,
switching converters, motor drivers, relay drivers, low-
voltage bus switches, and power management in portable
and battery-operated products.
Formerly developmental type TA75307.
Features
• 15A, 55V
• Simulation Models
- Temperature Compensated PSPICE® and SABER©
Models
- SPICE and SABER Thermal Impedance Models
Available on the WEB at:
www.semi.Intersil .com/families/models.htm
• Peak Current vs Pulse Width Curve
• UIS Rating Curve
• Related Literature
- TB334, “Guidelines for Soldering Surface Mount
Components to PC Boards”
Symbol
Packaging
Ordering Information
PART NUMBER PACKAGE BRAND
HUF75307P3 TO-220AB 75307P
HUF75307D3 TO-251AA 75307D
HUF75307D3S TO-252AA 75307D
NOTE: When ordering, use the entire part number. Add the suffix T to
obtain the TO-252AA variant in tape and reel, e.g., HUF75307D3ST.
D
G
S
JEDEC TO-220AB JEDEC TO-251AA
JEDEC TO-252AA
DRAIN
SOURCE
GATE
DRAIN
(FLANGE)
SOURCE
DRAIN
GATE
DRAIN
(FLANGE)
GATE
SOURCE
DRAIN
(FLANGE)
Data Sheet June 1999 File Number
4353.6
4-41
Absolute Maximum Ratings TC= 25oC, Unless Otherwise Specified UNITS
Drain to Source Voltage (Note 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .VDSS 55 V
Drain to Gate Voltage (RGS = 20kΩ) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .VDGR 55 V
Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .V
GS ±20 V
Drain Current
Continuous (Figure 2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .ID
Pulsed Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IDM 15
Figure 4 A
Pulsed Avalanche Rating. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EAS Figures 6, 14, 15
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PD
Derate Above 25oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
0.3 W
W/oC
Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ, TSTG -55 to 175 oC
Maximum Temperature for Soldering
Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TL
Package Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Tpkg 300
260
oC
oC
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operationofthe
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. TJ = 25oC to 150oC.
Electrical Specifications TC = 25oC, Unless Otherwise Specified
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
OFF STATE SPECIFICATIONS
Drain to Source Breakdown Voltage BVDSS ID = 250µA, VGS = 0V (Figure 11) 55 - - V
Zero Gate Voltage Drain Current IDSS VDS = 50V, VGS = 0V - - 1 µA
VDS = 45V, VGS = 0V, TC = 150oC - - 250 µA
Gate to Source Leakage Current IGSS VGS = ±20V - - ±100 nA
ON STATE SPECIFICATIONS
Gate to Source Threshold Voltage VGS(TH) VGS = VDS, ID = 250µA (Figure 10) 2 - 4 V
Drain to Source On Resistance rDS(ON) ID = 15A, VGS = 10V (Figure 9) - 0.075 0.090 Ω
THERMAL SPECIFICATIONS
Thermal Resistance Junction to Case RθJC (Figure 3) - - 3.3 oC/W
Thermal Resistance Junction to Ambient RθJA TO-220AB - - 62 oC/W
TO-251AA, TO-252AA - - 100 oC/W
SWITCHING SPECIFICATIONS (VGS = 10V)
Turn-On Time tON VDD = 30V, ID≅ 15A,
RL = 2.0Ω, VGS =10V,
RGS = 100Ω
- - 60 ns
Turn-On Delay Time td(ON) -7-ns
Rise Time tr-40- ns
Turn-Off Delay Time td(OFF) -35- ns
Fall Time tf-45- ns
Turn-Off Time tOFF - - 100 ns
GATE CHARGE SPECIFICATIONS
Total Gate Charge Qg(TOT) VGS = 0V to 20V VDD = 30V,
ID≅ 15A,
RL = 2.0Ω
Ig(REF) = 1.0mA
(Figure13)
-1620nC
Gate Charge at 10V Qg(10) VGS = 0V to 10V - 9 11 nC
Threshold Gate Charge Qg(TH) VGS = 0V to 2V - 0.6 0.8 nC
Gate to Source Gate Charge Qgs - 1.2 - nC
Reverse Transfer Capacitance Qgd -4-nC
HUF75307P3, HUF75307D3, HUF75307D3S
4-42
CAPACITANCE SPECIFICATIONS
Input Capacitance CISS VDS = 25V, VGS = 0V,
f = 1MHz
(Figure 12)
- 250 - pF
Output Capacitance COSS - 100 - pF
Reverse Transfer Capacitance CRSS -25-pF
Electrical Specifications TC = 25oC, Unless Otherwise Specified
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
Source to Drain Diode Specifications
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
Source to Drain Diode Voltage VSD ISD = 15A - - 1.25 V
Reverse Recovery Time trr ISD = 15A, dISD/dt = 100A/µs--45ns
Reverse Recovered Charge QRR ISD = 15A, dISD/dt = 100A/µs--55nC
Typical Performance Curves
FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE
TEMPERATURE FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs
CASE TEMPERATURE
FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE
TC, CASE TEMPERATURE (oC)
POWER DISSIPATION MULTIPLIER
00 25 50 75 100 150
0.2
0.4
0.6
0.8
1.0
1.2
125 175
5
10
15
20
50 75 100 125 150 175
025
ID, DRAIN CURRENT (A)
TC, CASE TEMPERATURE (oC)
0.1
1
101
100
10-1
10-2
10-3
10-4
0.01
2
10-5
t, RECTANGULAR PULSE DURATION (s)
SINGLE PULSE
NOTES:
DUTY FACTOR: D = t1/t2
PEAK TJ = PDM x ZθJC x RθJC + TC
PDM
t1t2
DUTY CYCLE - DESCENDING ORDER
0.5
0.2
0.1
0.05
0.01
0.02
ZθJC, NORMALIZED
THERMAL IMPEDANCE
HUF75307P3, HUF75307D3, HUF75307D3S
4-43
FIGURE 4. PEAK CURRENT CAPABILITY
FIGURE 5. FORWARD BIAS SAFE OPERATING AREA NOTE: Refer to Intersil Application Notes AN9321 and AN9322.
FIGURE 6. UNCLAMPED INDUCTIVE SWITCHING CAPABILITY
FIGURE 7. SATURATION CHARACTERISTICS FIGURE 8. TRANSFER CHARACTERISTICS
Typical Performance Curves
(Continued)
100
101
100
10-1
10-2
10-3
10-4
10-5
10
200 TC = 25oC
I = I25 175 - TC
150
FOR TEMPERATURES
ABOVE 25oC DERATE PEAK
CURRENT AS FOLLOWS:
VGS = 10V
IDM, PEAK CURRENT (A)
t, PULSE WIDTH (s)
TRANSCONDUCTANCE
MAY LIMIT CURRENT
IN THIS REGION
1
10
100
10 100
0.1
1 200
VDS, DRAIN TO SOURCE VOLTAGE (V)
ID, DRAIN CURRENT (A)
TJ = MAX RATED
TC = 25oC
100µs
10ms
1ms
VDSS(MAX) = 55V
LIMITED BY rDS(ON)
AREA MAY BE
OPERATION IN THIS
10
100
0.01 0.1 1 10
0.001
1
200
IAS, AVALANCHE CURRENT (A)
tAV, TIME IN AVALANCHE (ms)
tAV = (L)(IAS)/(1.3*RATED BVDSS - VDD)
If R = 0
If R ≠ 0
tAV = (L/R)ln[(IAS*R)/(1.3*RATED BVDSS - VDD) +1]
STARTING TJ = 25oC
STARTING TJ = 150oC
5
10
15
20
25
12345
0
0
ID, DRAIN CURRENT (A)
VDS, DRAIN TO SOURCE VOLTAGE (V)
VGS = 6V
PULSE DURATION = 80µs
TC = 25oC
VGS = 5V
VGS = 7V
VGS = 10V
VGS = 20V
DUTY CYCLE = 0.5% MAX
5
10
15
20
25
1.5 3.0 4.5 6.0 7.50
0
ID, DRAIN CURRENT (A)
VGS, GATE TO SOURCE VOLTAGE (V)
175oC
-55oC
25oC
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
VDD = 15V
HUF75307P3, HUF75307D3, HUF75307D3S
4-44
FIGURE 9. NORMALIZED DRAIN TO SOURCE ON
RESISTANCE vs JUNCTION TEMPERATURE FIGURE 10. NORMALIZED GATE THRESHOLD VOLTAGE vs
JUNCTION TEMPERATURE
FIGURE 11. NORMALIZED DRAIN TO SOURCE BREAKDOWN
VOLTAGE vs JUNCTION TEMPERATURE FIGURE 12. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE
NOTE: Refer to Intersil Application Notes AN7254 and AN7260.
FIGURE 13. GATE CHARGE WAVEFORMS FOR CONSTANT GATE CURRENT
Typical Performance Curves
(Continued)
1.0
1.5
2.0
2.5
-40 0 40 80 120 160 200
0.5
-80
NORMALIZED DRAIN TO SOURCE
TJ, JUNCTION TEMPERATURE (oC)
ON RESISTANCE
PULSE DURATION = 80µs
VGS = 10V, ID = 15A
DUTY CYCLE = 0.5% MAX
NORMALIZED GATE
TJ, JUNCTION TEMPERATURE (oC)
THRESHOLD VOLTAGE
VGS = VDS, ID = 250µA
0.8
1.0
1.2
-40 0 40 80 120 160 200-80
0.6
1.0
1.1
1.2
-40 0 40 80 120 160 200-80
0.9
TJ, JUNCTION TEMPERATURE (oC)
NORMALIZED DRAIN TO SOURCE
ID = 250µA
BREAKDOWN VOLTAGE
100
200
300
400
10 20 30 40 50 60
0
0
C, CAPACITANCE (pF)
VDS, DRAIN TO SOURCE VOLTAGE (V)
CISS
COSS
CRSS
VGS = 0, f = 1MHz
CISS = CGS + CGD
CRSS = CGD
COSS ≈ CDS + CGD
2
4
6
8
10
2468100
0
VGS, GATE TO SOURCE VOLTAGE (V)
VDD = 30V
Qg, GATE CHARGE (nC)
ID = 15A
ID = 12A
ID = 7.5A
ID= 4A
WAVEFORMS IN
DESCENDING ORDER:
HUF75307P3, HUF75307D3, HUF75307D3S
4-45
Test Circuits and Waveforms
FIGURE 14. UNCLAMPED ENERGY TEST CIRCUIT FIGURE 15. UNCLAMPED ENERGY WAVEFORMS
FIGURE 16. GATE CHARGE TEST CIRCUIT FIGURE 17. GATE CHARGE WAVEFORM
FIGURE 18. SWITCHING TIME TEST CIRCUIT FIGURE 19. RESISTIVE SWITCHING WAVEFORMS
tP
VGS
0.01Ω
L
IAS
+
-
VDS
VDD
RG
DUT
VARY tP TO OBTAIN
REQUIRED PEAK IAS
0V
VDD
VDS
BVDSS
tP
IAS
tAV
0
RL
VGS +
-
VDS
VDD
DUT
IG(REF)
VDD
Qg(TH)
VGS = 2V
Qg(10)
VGS = 10V
Qg(TOT)
VGS = 20V
VDS
VGS
Ig(REF)
0
0
Qgs Qgd
VGS
RL
RGS DUT
+
-VDD
VDS
VGS
tON
td(ON)
tr
90%
10%
VDS 90%
10%
tf
td(OFF)
tOFF
90%
50%
50%
10% PULSE WIDTH
VGS
0
0
HUF75307P3, HUF75307D3, HUF75307D3S
4-46
PSPICE Electrical Model
.SUBCKT HUF75307 2 1 3 ; rev June 1997
CA 12 8 4.5e-10
CB 15 14 4.1e-10
CIN 6 8 2.154e-10
DBODY 7 5 DBODYMOD
DBREAK 5 11 DBREAKMOD
DPLCAP 10 5 DPLCAPMOD
EBREAK 11 7 17 18 56
EDS 14 8 5 8 1
EGS 13 8 6 8 1
ESG 6 10 6 8 1
EVTHRES 6 21 19 8 1
EVTEMP 20 6 18 22 1
IT 8 17 1
LDRAIN 2 5 1e-9
LGATE 1 9 5.97e-10
LSOURCE 3 7 2.39e-9
K1 LGATE LSOURCE 0.131
MMED 16 6 8 8 MMEDMOD
MSTRO 16 6 8 8 MSTROMOD
MWEAK 16 21 8 8 MWEAKMOD
RBREAK 17 18 RBREAKMOD 1
RDRAIN 50 16 RDRAINMOD 1e-3
RGATE 9 20 1.9
RLDRAIN 2 5 10
RLGATE 1 9 60
RLSOURCE 3 7 24
RSLC1 5 51 RSLCMOD 1e-6
RSLC2 5 50 1e3
RSOURCE 8 7 RSOURCEMOD 5.5e-2
RVTHRES 22 8 RVTHRESMOD 1
RVTEMP 18 19 RVTEMPMOD 1
S1A 6 12 13 8 S1AMOD
S1B 13 12 13 8 S1BMOD
S2A 6 15 14 13 S2AMOD
S2B 13 15 14 13 S2BMOD
VBAT 22 19 DC 1
ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*35),4))}
.MODEL DBODYMOD D (IS=1.6e-13 RS=1.28e-2 IKF=5.5 N=0.985 TRS1=2.9e-3 TRS2=-4e-6 CJO=3.5e-10 TT=3.1e-8 M=0.45 XTI=6)
.MODEL DBREAKMOD D (RS=2.5e-1 IKF=0.1 TRS1=-4e-3 TRS2=3e-5)
.MODEL DPLCAPMOD D (CJO=5e-10 IS=1e-30 N=10 M=0.95)
.MODEL MMEDMOD NMOS (VTO=3.25 KP=2.2 IS=1e-30 N=10 TOX=1 L=1u W=1u RG=1.9)
.MODEL MSTROMOD NMOS (VTO=3.75 KP=14.75 IS=1e-30 N=10 TOX=1 L=1u W=1u)
.MODEL MWEAKMOD NMOS (VTO=2.88 KP=0.03 IS=1e-30 N=10 TOX=1 L=1u W=1u RG=19 RS=0.1)
.MODEL RBREAKMOD RES (TC1=1.12e-3 TC2=1e-6)
.MODEL RDRAINMOD RES (TC1=2.3e-1 TC2=6e-4)
.MODEL RSLCMOD RES (TC1=4e-3 TC2=1e-6)
.MODEL RSOURCEMOD RES (TC1=1e-3 TC2=6e-6)
.MODEL RVTHRESMOD RES (TC=-3.31e-3 TC2=-1.49e-5)
.MODEL RVTEMPMOD RES (TC1=-1.4e-3 TC2=1e-9)
.MODEL S1AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-8.1 VOFF=-4)
.MODEL S1BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-4 VOFF=-8.1)
.MODEL S2AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=0 VOFF=2)
.MODEL S2BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=2 VOFF=0)
.ENDS
NOTE: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global
Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank Wheatley.
18
22
+-
6
8
+
-
5
51
+
-
19
8
+-
17
18
6
8
+
-
5
8+
-
RBREAK
RVTEMP
VBAT
RVTHRES
IT
17 18
19
22
12
13
15
S1A
S1B
S2A
S2B
CA CB
EGS EDS
14
8
13
814
13
MWEAK
EBREAK DBODY
RSOURCE
SOURCE
11
73
LSOURCE
RLSOURCE
CIN
RDRAIN
EVTHRES 16
21
8
MMED
MSTRO
DRAIN
2
LDRAIN
RLDRAIN
DBREAK
DPLCAP
ESLC
RSLC1
10
5
51
50
RSLC2
1
GATE RGATE EVTEMP
9
ESG
LGATE
RLGATE 20
+
-
+
-
+
-
6
HUF75307P3, HUF75307D3, HUF75307D3S
4-47
SABER Electrical Model
REV February 1999
template huf75307 n2, n1, n3
electrical n2, n1, n3
{
var i iscl
d..model dbodymod = (is = 1.6e-13, xti = 6, cjo = 3.5e-10, tt = 3.1e-8, n = 0.985, m = 0.45)
d..model dbreakmod = ()
d..model dplcapmod = (cjo = 5e-10, is = 1e-30, n = 10, m = 0.95)
m..model mmedmod = (type=_n, vto = 3.25, kp = 2.2, is = 1e-30, tox = 1)
m..model mstrongmod = (type=_n, vto = 3.75, kp = 14.75, is = 1e-30, tox = 1)
m..model mweakmod = (type=_n, vto = 2.88, kp = 0.03, is = 1e-30, tox = 1)
sw_vcsp..model s1amod = (ron = 1e-5, roff = 0.1, von = -8.1, voff = -4)
sw_vcsp..model s1bmod = (ron = 1e-5, roff = 0.1, von = -4, voff = -8.1)
sw_vcsp..model s2amod = (ron = 1e-5, roff = 0.1, von = 0, voff = 2)
sw_vcsp..model s2bmod = (ron = 1e-5, roff = 0.1, von = 2, voff = 0)
c.ca n12 n8 = 4.5e-10
c.cb n15 n14 = 4.1e-10
c.cin n6 n8 = 2.154e-10
d.dbody n7 n71 = model=dbodymod
d.dbreak n72 n11 = model=dbreakmod
d.dplcap n10 n5 = model=dplcapmod
i.it n8 n17 = 1
l.ldrain n2 n5 = 1e-9
l.lgate n1 n9 = 5.97e-10
l.lsource n3 n7 = 2.39e-9
m.mmed n16 n6 n8 n8 = model=mmedmod, l = 1u, w = 1u
m.mstrong n16 n6 n8 n8 = model=mstrongmod, l = 1u, w = 1u
m.mweak n16 n21 n8 n8 = model=mweakmod, l = 1u, w = 1u
res.rbreak n17 n18 = 1, tc1 = 1.12e-3, tc2 = 1e-6
res.rdbody n71 n5 = 1.28e-2, tc1 = 2.9e-3, tc2 = -4e-6
res.rdbreak n72 n5 = 0.25, tc1 = -4e-3, tc2 = 3e-5
res.rdrain n50 n16 = 1e-3, tc1 = 2.31-1, tc2 = 6e-4
res.rgate n9 n20 = 1.9
res.rldrain n2 n5 = 10
res.rlgate n1 n9 = 60
res.rlsource n3 n7 = 24
res.rslc1 n5 n51 = 1e-6, tc1 = 4e-3, tc2 = 1e-6
res.rslc2 n5 n50 = 1e3
res.rsource n8 n7 = 5.5e-2, tc1 = 1e-3, tc2 = 6e-6
res.rvtemp n18 n19 = 1, tc1 = -1.4e-3, tc2 = 1e-9
res.rvthres n22 n8 = 1, tc1 = -3.31e-3, tc2 = -1.49e-5
spe.ebreak n11 n7 n17 n18 = 56
spe.eds n14 n8 n5 n8 = 1
spe.egs n13 n8 n6 n8 = 1
spe.esg n6 n10 n6 n8 = 1
spe.evtemp n20 n6 n18 n22 = 1
spe.evthres n6 n21 n19 n8 = 1
sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod
sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod
sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod
sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod
v.vbat n22 n19 = dc = 1
equations {
i (n51->n50) + = iscl
iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6/35))** 4))
}
}
18
22
+-
6
8
+
-
19
8
+-
17
18
6
8
+
-
5
8+
-
RBREAK
RVTEMP
VBAT
RVTHRES
IT
17 18
19
22
12
13
15
S1A
S1B
S2A
S2B
CA CB
EGS EDS
14
8
13
814
13
MWEAK
EBREAK DBODY
RSOURCE
SOURCE
11
73
LSOURCE
RLSOURCE
CIN
RDRAIN
EVTHRES 16
21
8
MMED
MSTRO
DRAIN
2
LDRAIN
RLDRAIN
DBREAK
DPLCAP
ISCL
RSLC1
10
5
51
50
RSLC2
1
GATE RGATE EVTEMP
9
ESG
LGATE
RLGATE 20
+
-
+
-
+
-
6
RDBODY
RDBREAK
72
71
HUF75307P3, HUF75307D3, HUF75307D3S
4-48
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time with-
out notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
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SPICE Thermal Model
REV February 1999
HUF75307
CTHERM1 th 6 8.0e-4
CTHERM2 6 5 1.6e-3
CTHERM3 5 4 1.9e-3
CTHERM4 4 3 2.6e-3
CTHERM5 3 2 5.5e-3
CTHERM6 2 tl 1.8e-2
RTHERM1 th 6 8.0e-3
RTHERM2 6 5 2.1e-2
RTHERM3 5 4 2.2e-1
RTHERM4 4 3 6.4e-1
RTHERM5 3 2 7.7e-1
RTHERM6 2 tl 1.0
SABER Thermal Model
SABER thermal model HUF75307
template thermal_model th tl
thermal_c th, tl
{
ctherm.ctherm1 th 6 = 8.0e-4
ctherm.ctherm2 6 5 = 1.6e-3
ctherm.ctherm3 5 4 = 1.9e-3
ctherm.ctherm4 4 3 = 2.6e-3
ctherm.ctherm5 3 2 = 5.5e-3
ctherm.ctherm6 2 tl = 1.8e-2
rtherm.rtherm1 th 6 = 8.0e-3
rtherm.rtherm2 6 5 = 2.1e-2
rtherm.rtherm3 5 4 = 2.2e-1
rtherm.rtherm4 4 3 = 6.4e-1
rtherm.rtherm5 3 2 = 7.7e-1
rtherm.rtherm6 2 tl = 1.0
}
RTHERM4
RTHERM6
RTHERM5
RTHERM3
RTHERM2
RTHERM1
CTHERM4
CTHERM6
CTHERM5
CTHERM3
CTHERM2
CTHERM1
tl
2
3
4
5
6
th JUNCTION
CASE
HUF75307P3, HUF75307D3, HUF75307D3S
