M1A3PE3000-1FG484I - Microsemi - Datasheet.Directory

August 2009 I

ProASIC3E Flash Family FPGAs

with Optional Soft ARM® Support

Features and Benefits

High Capacity

• 600 k to 3 Million System Gates

• 108 to 504 kbits of True Dual-Port SRAM

• Up to 620 User I/Os

Reprogrammable Flash Technology

• 130-nm, 7-Layer Metal (6 Copper), Flash-Based CMOS Process

• Live at Power-Up (LAPU) Level 0 Support

• Single-Chip Solution

• Retains Programmed Design when Powered Off

On-Chip User Nonvolatile Memory

• 1 kbit of FlashROM with Synchronous Interfacing

High Performance

• 350 MHz System Performance

• 3.3 V, 66 MHz 64-Bit PCI

In-System Programming (ISP) and Security

• Secure ISP Using On-Chip 128-Bit Advanced Encryption

Standard (AES) Decryption via JTAG (IEEE 1532–compliant)

•FlashLock

® to Secure FPGA Contents

Low Power

• Core Voltage for Low Power

• Support for 1.5-V-Only Systems

• Low-Impedance Flash Switches

High-Performance Routing Hierarchy

• Segmented, Hierarchical Routing and Clock Structure

• Ultra-Fast Local and Long-Line Network

• Enhanced High-Speed, Very-Long-Line Network

• High-Performance, Low-Skew Global Network

• Architecture Supports Ultra-High Utilization

Pro (Professional) I/O

• 700 Mbps DDR, LVDS-Capable I/Os

• 1.5 V, 1.8 V, 2.5 V, and 3.3 V Mixed-Voltage Operation

• Bank-Selectable I/O Voltages—up to 8 Banks per Chip

• Single-Ended I/O Standards: LVTTL, LVCMOS 3.3 V /

2.5 V / 1.8 V / 1.5 V, 3.3 V PCI / 3.3 V PCI-X, and LVCMOS

2.5 V / 5.0 V Input

• Differential I/O Standards: LVPECL, LVDS, B-LVDS, and

M-LVDS

• Voltage-Referenced I/O Standards: GTL+ 2.5 V / 3.3 V, GTL

2.5 V / 3.3 V, HSTL Class I and II, SSTL2 Class I and II, SSTL3

Class I and II

• I/O Registers on Input, Output, and Enable Paths

• Hot-Swappable and Cold Sparing I/Os

• Programmable Output Slew Rate and Drive Strength

• Programmable Input Delay

• Schmitt Trigger Option on Single-Ended Inputs

• Weak Pull-Up/-Down

• IEEE 1149.1 (JTAG) Boundary Scan Test

• Pin-Compatible Packages across the ProASIC®3E Family

Clock Conditioning Circuit (CCC) and PLL

• Six CCC Blocks, Each with an Integrated PLL

• Configurable Phase-Shift, Multiply/Divide, Delay

Capabilities and External Feedback

• Wide Input Frequency Range (1.5 MHz to 200 MHz)

SRAMs and FIFOs

• Variable-Aspect-Ratio 4,608-Bit RAM Blocks (×1, ×2, ×4, ×9,

and ×18 organizations available)

• True Dual-Port SRAM (except ×18)

• 24 SRAM and FIFO Configurations with Synchronous

Operation up to 350 MHz

ARM Processor Support in ProASIC3E FPGAs

• M1 ProASIC3E Devices—Cortex-M1 Soft Processor Available

with or without Debug

Table 1-1 • ProASIC3E Product Family

ProASIC3E Devices A3PE600 A3PE1500 A3PE3000

Cortex-M1 Devices 1M1A3PE1500 M1A3PE3000

System Gates 600 k 1.5 M 3 M

VersaTiles (D-flip-flops) 13,824 38,400 75,264

RAM kbits (1,024 bits) 108 270 504

4,608-Bit Blocks 24 60 112

FlashROM Bits 1 k 1 k 1 k

Secure (AES) ISP Yes Yes Yes

CCCs with Integrated PLLs266 6

VersaNet Globals318 18 18

I/O Banks 88 8

Maximum User I/Os 270 444 620

Package Pins

PQFP

FBGA

PQ208

FG256, FG484

PQ208

FG484, FG676

PQ208

FG324, FG484, FG896

Notes:

1. Refer to the Cortex-M1 product brief for more information.

2. The PQ208 package supports six CCCs and two PLLs.

3. Six chip (main) and three quadrant global networks are available.

4. For devices supporting lower densities, refer to the ProASIC3 Flash Family FPGAs handbook.

v1.2

II v1.2

I/Os Per Package1

ProASIC3E Devices A3PE600 A3PE1500 3A3PE3000 3

Cortex-M1 Devices 2M1A3PE1500 M1A3PE3000

Package

I/O Types

Single-Ended I/O1

Differential I/O Pairs

Single-Ended I/O1

Differential I/O Pairs

Single-Ended I/O1

Differential I/O Pairs

PQ208 147 65 147 65 147 65

FG256 16579––––

FG324 – – – – 221 110

FG484 270 135 280 139 341 168

FG676 – – 444 222 – –

FG896 – – – – 620 310

Notes:

1. When considering migrating your design to a lower- or higher-density device, refer to the ProASIC3E Flash Family FPGAs

handbook to ensure compliance with design and board migration requirements.

2. Each used differential I/O pair reduces the number of single-ended I/Os available by two.

3. For A3PE1500 and A3PE3000 devices, the usage of certain I/O standards is limited as follows:

– SSTL3(I) and (II): up to 40 I/Os per north or south bank

– LVPECL / GTL+ 3.3 V / GTL 3.3 V: up to 48 I/Os per north or south bank

– SSTL2(I) and (II) / GTL+ 2.5 V/ GTL 2.5 V: up to 72 I/Os per north or south bank

4. FG256 and FG484 are footprint-compatible packages.

5. When using voltage-referenced I/O standards, one I/O pin should be assigned as a voltage-referenced pin (VREF) per

minibank (group of I/Os).

6. "G" indicates RoHS-compliant packages. Refer to the "ProASIC3E Ordering Information" on page III for the location of

the "G" in the part number.

Table 1-2 • ProASIC3E FPGAs Package Sizes Dimensions

Package PQ208 FG256 FG324 FG484 FG676 FG896

Length × Width

(mm\mm)

28 × 28 17 × 17 19 × 19 23 × 23 27 × 27 31 × 31

Nominal Area

(mm2)

784 289 361 529 729 961

Pitch (mm) 0.5 1.0 1.0 1.0 1.0 1.0

Height (mm) 3.40 1.60 1.63 2.23 2.23 2.23

ProASIC3E Flash Family FPGAs

v1.2 III

ProASIC3E Ordering Information

A3PE3000 FG

Part Number

Speed Grade

1 = 15% Faster than Standard

2 = 25% Faster than Standard

Package Type

PQ =Plastic Quad Flat Pack (0.5 mm pitch)

FG =Fine Pitch Ball Grid Array (1.0 mm pitch)

896 I

Package Lead Count

Application (Temperature Range)

Blank = Commercial (0°C to +70°C Ambient Temperature)

I = Industrial (–40°C to +85°C Ambient Temperature)

PP = Pre-Production

ES = Engineering Sample (Room Temperature Only)

600,000 System Gates

A3PE600 =

1,500,000 System Gates

A3PE1500 =

3,000,000 System Gates

A3PE3000 =

1,500,000 System Gates

M1A3PE1500 =

3,000,000 System Gates

M1A3PE3000 =

Lead-Free Packaging

Blank = Standard Packaging

G = RoHS-Compliant (Green) Packaging

ProASIC3E Devices

ProASIC3E Devices with Cortex-M1

IV v1.2

Temperature Grade Offerings

Speed Grade and Temperature Grade Matrix

References made to ProASIC3E devices also apply to ARM-enabled ProASIC3E devices. The ARM-enabled part numbers start

with M1 (Cortex-M1).

Contact your local Actel representative for device availability:

http://www.actel.com/contact/default.aspx.

Package A3PE600 A3PE1500 A3PE3000

Cortex-M1 Devices M1A3PE1500 M1A3PE3000

PQ208 C, I C, I C, I

FG256 C, I – –

FG324 – – C, I

FG484 C, I C, I C, I

FG676 – C, I –

FG896 – – C, I

Note: C = Commercial temperature range: 0°C to 70°C ambient temperature

I = Industrial temperature range: –40°C to 85°C ambient temperature

Temperature Grade Std. –1 –2

C1✓✓✓

I2✓✓✓

Notes:

1. C = Commercial temperature range: 0°C to 70°C ambient temperature

2. I = Industrial temperature range: –40°C to 85°C ambient temperature

v1.2 1-1

1 – ProASIC3E Device Family Overview

General Description

ProASIC3E, the third-generation family of Actel flash FPGAs, offers performance, density, and

features beyond those of the ProASICPLUS® family. Nonvolatile flash technology gives ProASIC3E

devices the advantage of being a secure, low-power, single-chip solution that is live at power-up

(LAPU). ProASIC3E is reprogrammable and offers time-to-market benefits at an ASIC-level unit cost.

These features enable designers to create high-density systems using existing ASIC or FPGA design

flows and tools.

ProASIC3E devices offer 1 kbit of on-chip, programmable, nonvolatile FlashROM storage as well as

clock conditioning circuitry based on six integrated phase-locked loops (PLLs). ProASIC3E devices

have up to three million system gates, supported with up to 504 kbits of true dual-port SRAM and

up to 620 user I/Os.

Several ProASIC3E devices support the Cortex-M1 soft IP cores, and the ARM-Enabled devices have

Actel ordering numbers that begin with M1A3PE.

Flash Advantages

Reduced Cost of Ownership

Advantages to the designer extend beyond low unit cost, performance, and ease of use. Unlike

SRAM-based FPGAs, flash-based ProASIC3E devices allow all functionality to be live at power-up; no

external boot PROM is required. On-board security mechanisms prevent access to all the

programming information and enable secure remote updates of the FPGA logic. Designers can

perform secure remote in-system reprogramming to support future design iterations and field

upgrades with confidence that valuable intellectual property (IP) cannot be compromised or

copied. Secure ISP can be performed using the industry-standard AES algorithm. The ProASIC3E

family device architecture mitigates the need for ASIC migration at higher user volumes. This

makes the ProASIC3E family a cost-effective ASIC replacement solution, especially for applications

in the consumer, networking/ communications, computing, and avionics markets.

Security

The nonvolatile, flash-based ProASIC3E devices do not require a boot PROM, so there is no

vulnerable external bitstream that can be easily copied. ProASIC3E devices incorporate FlashLock,

which provides a unique combination of reprogrammability and design security without external

overhead, advantages that only an FPGA with nonvolatile flash programming can offer.

ProASIC3E devices utilize a 128-bit flash-based lock and a separate AES key to secure programmed

intellectual property and configuration data. In addition, all FlashROM data in ProASIC3E devices

can be encrypted prior to loading, using the industry-leading AES-128 (FIPS192) bit block cipher

encryption standard. The AES standard was adopted by the National Institute of Standards and

Technology (NIST) in 2000 and replaces the 1977 DES standard. ProASIC3E devices have a built-in

AES decryption engine and a flash-based AES key that make them the most comprehensive

programmable logic device security solution available today. ProASIC3E devices with AES-based

security allow for secure, remote field updates over public networks such as the Internet, and

ensure that valuable IP remains out of the hands of system overbuilders, system cloners, and IP

thieves. The contents of a programmed ProASIC3E device cannot be read back, although secure

design verification is possible.

Security, built into the FPGA fabric, is an inherent component of the ProASIC3E family. The flash

cells are located beneath seven metal layers, and many device design and layout techniques have

been used to make invasive attacks extremely difficult. The ProASIC3E family, with FlashLock and

AES security, is unique in being highly resistant to both invasive and noninvasive attacks. Your

ProASIC3E Device Family Overview

1-2 v1.2

valuable IP is protected and secure, making remote ISP possible. A ProASIC3E device provides the

most impenetrable security for programmable logic designs.

Single Chip

Flash-based FPGAs store their configuration information in on-chip flash cells. Once programmed,

the configuration data is an inherent part of the FPGA structure, and no external configuration

data needs to be loaded at system power-up (unlike SRAM-based FPGAs). Therefore, flash-based

ProASIC3E FPGAs do not require system configuration components such as EEPROMs or

microcontrollers to load device configuration data. This reduces bill-of-materials costs and PCB

area, and increases security and system reliability.

Live at Power-Up

The Actel flash-based ProASIC3E devices support Level 0 of the LAPU classification standard. This

feature helps in system component initialization, execution of critical tasks before the processor

wakes up, setup and configuration of memory blocks, clock generation, and bus activity

management. The LAPU feature of flash-based ProASIC3E devices greatly simplifies total system

design and reduces total system cost, often eliminating the need for CPLDs and clock generation

PLLs that are used for these purposes in a system. In addition, glitches and brownouts in system

power will not corrupt the ProASIC3E device's flash configuration, and unlike SRAM-based FPGAs,

the device will not have to be reloaded when system power is restored. This enables the reduction

or complete removal of the configuration PROM, expensive voltage monitor, brownout detection,

and clock generator devices from the PCB design. Flash-based ProASIC3E devices simplify total

system design and reduce cost and design risk while increasing system reliability and improving

system initialization time.

Firm Errors

Firm errors occur most commonly when high-energy neutrons, generated in the upper atmosphere,

strike a configuration cell of an SRAM FPGA. The energy of the collision can change the state of the

configuration cell and thus change the logic, routing, or I/O behavior in an unpredictable way.

These errors are impossible to prevent in SRAM FPGAs. The consequence of this type of error can be

a complete system failure. Firm errors do not exist in the configuration memory of ProASIC3E flash-

based FPGAs. Once it is programmed, the flash cell configuration element of ProASIC3E FPGAs

cannot be altered by high-energy neutrons and is therefore immune to them. Recoverable (or soft)

errors occur in the user data SRAM of all FPGA devices. These can easily be mitigated by using error

detection and correction (EDAC) circuitry built into the FPGA fabric.

Low Power

Flash-based ProASIC3E devices exhibit power characteristics similar to an ASIC, making them an

ideal choice for power-sensitive applications. ProASIC3E devices have only a very limited power-on

current surge and no high-current transition period, both of which occur on many FPGAs.

ProASIC3E devices also have low dynamic power consumption to further maximize power savings.

Advanced Flash Technology

The ProASIC3E family offers many benefits, including nonvolatility and reprogrammability through

an advanced flash-based, 130-nm LVCMOS process with seven layers of metal. Standard CMOS

design techniques are used to implement logic and control functions. The combination of fine

granularity, enhanced flexible routing resources, and abundant flash switches allows for very high

logic utilization without compromising device routability or performance. Logic functions within

the device are interconnected through a four-level routing hierarchy.

ProASIC3E Flash Family FPGAs

v1.2 1-3

Advanced Architecture

The proprietary ProASIC3E architecture provides granularity comparable to standard-cell ASICs. The

ProASIC3E device consists of five distinct and programmable architectural features (Figure 1-1 on

page 3):

• FPGA VersaTiles

• Dedicated FlashROM

• Dedicated SRAM/FIFO memory

• Extensive CCCs and PLLs

• Pro I/O structure

The FPGA core consists of a sea of VersaTiles. Each VersaTile can be configured as a three-input

logic function, a D-flip-flop (with or without enable), or a latch by programming the appropriate

flash switch interconnections. The versatility of the ProASIC3E core tile as either a three-input

lookup table (LUT) equivalent or as a D-flip-flop/latch with enable allows for efficient use of the

FPGA fabric. The VersaTile capability is unique to the Actel ProASIC family of third-generation

architecture Flash FPGAs. VersaTiles are connected with any of the four levels of routing hierarchy.

Flash switches are distributed throughout the device to provide nonvolatile, reconfigurable

interconnect programming. Maximum core utilization is possible for virtually any design.

In addition, extensive on-chip programming circuitry allows for rapid, single-voltage (3.3 V)

programming of ProASIC3E devices via an IEEE 1532 JTAG interface.

Figure 1-1 • ProASIC3E Device Architecture Overview

4,608-Bit Dual-Port SRAM

or FIFO Block

VersaTile

RAM Block

CCC

Pro I/Os

ISP AES Decryption User Nonvolatile

FlashROM Charge Pumps

4,608-Bit Dual-Port SRAM

or FIFO Block

RAM Block

ProASIC3E Device Family Overview

1-4 v1.2

VersaTiles

The ProASIC3E core consists of VersaTiles, which have been enhanced beyond the ProASICPLUS®

core tiles. The ProASIC3E VersaTile supports the following:

• All 3-input logic functions—LUT-3 equivalent

• Latch with clear or set

• D-flip-flop with clear or set

• Enable D-flip-flop with clear or set

Refer to Figure 1-2 for VersaTile configurations.

User Nonvolatile FlashROM

Actel ProASIC3E devices have 1 kbit of on-chip, user-accessible, nonvolatile FlashROM. The

FlashROM can be used in diverse system applications:

• Internet protocol addressing (wireless or fixed)

• System calibration settings

• Device serialization and/or inventory control

• Subscription-based business models (for example, set-top boxes)

• Secure key storage for secure communications algorithms

• Asset management/tracking

• Date stamping

• Version management

The FlashROM is written using the standard ProASIC3E IEEE 1532 JTAG programming interface. The

core can be individually programmed (erased and written), and on-chip AES decryption can be used

selectively to securely load data over public networks, as in security keys stored in the FlashROM for

a user design.

The FlashROM can be programmed via the JTAG programming interface, and its contents can be

read back either through the JTAG programming interface or via direct FPGA core addressing. Note

that the FlashROM can only be programmed from the JTAG interface and cannot be programmed

from the internal logic array.

The FlashROM is programmed as 8 banks of 128 bits; however, reading is performed on a byte-by-

byte basis using a synchronous interface. A 7-bit address from the FPGA core defines which of the 8

banks and which of the 16 bytes within that bank are being read. The three most significant bits

(MSBs) of the FlashROM address determine the bank, and the four least significant bits (LSBs) of

the FlashROM address define the byte.

The Actel ProASIC3E development software solutions, Libero® Integrated Design Environment (IDE)

and Designer, have extensive support for the FlashROM. One such feature is auto-generation of

sequential programming files for applications requiring a unique serial number in each part.

Another feature allows the inclusion of static data for system version control. Data for the

FlashROM can be generated quickly and easily using Actel Libero IDE and Designer software tools.

Comprehensive programming file support is also included to allow for easy programming of large

numbers of parts with differing FlashROM contents.

Figure 1-2 • VersaTile Configurations

LUT-3

Data Y

CLK

Enable

CLR

D-FF

Data Y

CLK

CLR

D-FF

LUT-3 Equivalent D-Flip-Flop with Clear or Set Enable D-Flip-Flop with Clear or Set

ProASIC3E Flash Family FPGAs

v1.2 1-5

SRAM and FIFO

ProASIC3E devices have embedded SRAM blocks along their north and south sides. Each variable-

aspect-ratio SRAM block is 4,608 bits in size. Available memory configurations are 256×18, 512×9,

1k×4, 2k×2, and 4k×1 bits. The individual blocks have independent read and write ports that can be

configured with different bit widths on each port. For example, data can be sent through a 4-bit

port and read as a single bitstream. The embedded SRAM blocks can be initialized via the device

JTAG port (ROM emulation mode) using the UJTAG macro.

In addition, every SRAM block has an embedded FIFO control unit. The control unit allows the

SRAM block to be configured as a synchronous FIFO without using additional core VersaTiles. The

FIFO width and depth are programmable. The FIFO also features programmable Almost Empty

(AEMPTY) and Almost Full (AFULL) flags in addition to the normal Empty and Full flags. The

embedded FIFO control unit contains the counters necessary for generation of the read and write

address pointers. The embedded SRAM/FIFO blocks can be cascaded to create larger configurations.

PLL and CCC

ProASIC3E devices provide designers with very flexible clock conditioning capabilities. Each

member of the ProASIC3E family contains six CCCs, each with an integrated PLL.

The six CCC blocks are located at the four corners and the centers of the east and west sides.

To maximize user I/Os, only the center east and west PLLs are available in devices using the PQ208

package. However, all six CCC blocks are still usable; the four corner CCCs allow simple clock delay

operations as well as clock spine access.

The inputs of the six CCC blocks are accessible from the FPGA core or from one of several inputs

located near the CCC that have dedicated connections to the CCC block.

The CCC block has these key features:

• Wide input frequency range (fIN_CCC) = 1.5 MHz to 350 MHz

• Output frequency range (fOUT_CCC) = 0.75 MHz to 350 MHz

• Clock delay adjustment via programmable and fixed delays from –7.56 ns to +11.12 ns

• 2 programmable delay types for clock skew minimization

• Clock frequency synthesis

Additional CCC specifications:

• Internal phase shift = 0°, 90°, 180°, and 270°. Output phase shift depends on the output

divider configuration.

• Output duty cycle = 50% ± 1.5% or better

• Low output jitter: worst case < 2.5% × clock period peak-to-peak period jitter when single

global network used

• Maximum acquisition time = 300 µs

• Low power consumption of 5 mW

• Exceptional tolerance to input period jitter— allowable input jitter is up to 1.5 ns

• Four precise phases; maximum misalignment between adjacent phases of 40 ps × (350 MHz /

fOUT_CCC)

Global Clocking

ProASIC3E devices have extensive support for multiple clocking domains. In addition to the CCC

and PLL support described above, there is a comprehensive global clock distribution network.

Each VersaTile input and output port has access to nine VersaNets: six chip (main) and three

quadrant global networks. The VersaNets can be driven by the CCC or directly accessed from the

core via multiplexers (MUXes). The VersaNets can be used to distribute low-skew clock signals or for

rapid distribution of high fanout nets.

ProASIC3E Device Family Overview

1-6 v1.2

Pro I/Os with Advanced I/O Standards

The ProASIC3E family of FPGAs features a flexible I/O structure, supporting a range of voltages

(1.5 V, 1.8 V, 2.5 V, and 3.3 V). ProASIC3E FPGAs support 19 different I/O standards, including single-

ended, differential, and voltage-referenced. The I/Os are organized into banks, with eight banks

per device (two per side). The configuration of these banks determines the I/O standards

supported. Each I/O bank is subdivided into VREF minibanks, which are used by voltage-referenced

I/Os. VREF minibanks contain 8 to 18 I/Os. All the I/Os in a given minibank share a common VREF line.

Therefore, if any I/O in a given VREF minibank is configured as a VREF pin, the remaining I/Os in that

minibank will be able to use that reference voltage.

Each I/O module contains several input, output, and enable registers. These registers allow the

implementation of the following:

• Single-Data-Rate applications (e.g., PCI 66 MHz, bidirectional SSTL 2 and 3, Class I and II)

• Double-Data-Rate applications (e.g., DDR LVDS, B-LVDS, and M-LVDS I/Os for point-to-point

communications, and DDR 200 MHz SRAM using bidirectional HSTL Class II)

ProASIC3E banks support M-LVDS with 20 multi-drop points.

Hot-swap (also called hot-plug, or hot-insertion) is the operation of hot-insertion or hot-removal of

a card in a powered-up system.

Cold-sparing (also called cold-swap) refers to the ability of a device to leave system data

undisturbed when the system is powered up, while the component itself is powered down, or

when power supplies are floating.

ProASIC3E Flash Family FPGAs

v1.2 1-7

Part Number and Revision Date

Part Number 51700098-001-3

Revised August 2009

List of Changes

The following table lists critical changes that were made in the current version of the document.

Previous Version Changes in Current Version (v1.2) Page

v1.1

(February 2009)

All references to speed grade –F have been removed from this document. N/A

The "Pro I/Os with Advanced I/O Standards" section was revised to add

definitions of hot-swap and cold-sparing.

v1.0

(March 2008)

Table 1-2 · ProASIC3E FPGAs Package Sizes Dimensions is new. 1-6

51700098-001-1 This document was divided into two sections and given a version number,

starting at v1.0. The first section of the document includes features, benefits,

ordering information, and temperature and speed grade offerings. The second

section is a device family overview.

N/A

51700098-001-0

(January 2008)

The FG324 package was added to the "ProASIC3E Product Family" table, the

"I/Os Per Package1" table, and the "Temperature Grade Offerings" table for

A3PE3000.

I, II, IV

v2.1

(July 2007)

This document was previously in datasheet v2.1. As a result of moving to the

handbook format, Actel has restarted the version numbers. The new version

number is 51700098-001-0.

N/A

v2.0

(April 2007)

CoreMP7 information was removed from the "Features and Benefits" section. i

The M1 device part numbers have been updated in Table 4 • ProASIC3E

Product Family, "Packaging Tables", "Temperature Grade Offerings", "Speed

Grade and Temperature Grade Matrix", and "Speed Grade and Temperature

Grade Matrix".

ii, iii,

iv, iv

The words "ambient temperature" were added to the temperature range in

the "Temperature Grade Offerings", "Speed Grade and Temperature Grade

Matrix", and "Speed Grade and Temperature Grade Matrix" sections.

iii, iv, iv

The "Clock Conditioning Circuit (CCC) and PLL" section was updated. i

Advance v0.6

(January 2007)

In the "Temperature Grade Offerings" section, Ambient was deleted. iii

Ambient was deleted from "Temperature Grade Offerings". iii

Ambient was deleted from the "Speed Grade and Temperature Grade Matrix". iv

Advance v0.5

(April 2006)

In the "Packaging Tables" table, the number of I/Os for the A3PE1500 was

changed for the FG484 and FG676 packages.

Advance v0.4

(October 2005)

B-LVDS and M-LDVS are new I/O standards added to the datasheet. N/A

The term flow-through was changed to pass-through. N/A

Advance v0.2 The "Packaging Tables" table was updated. ii

ProASIC3E Device Family Overview

1-8 v1.2

Datasheet Categories