K7N403209B K7N403609B K7N401809B Preliminary 128Kx36 & 128Kx32 & 256Kx18 Pipelined NtRAMTM Document Title 128Kx36 & 128Kx32 & 256Kx18-Bit Pipelined NtRAMTM Revision History Rev. No. History Draft Date Remark 0.0 1. Initial document. May. 15. 2001 Preliminary 0.1 1. Changed DC parameters Icc ; from 470mA to 400mA at -25, from 440mA to 360mA at -22, from 400mA to 330mA at -20, from 370mA to 310mA at -18, June. 12. 2001 Preliminary Aug. 11. 2001 Preliminary ISB ; from 180mA from 170mA from 160mA from 150mA 0.2 to to to to 160mA at -25, 155mA at -22, 150mA at -20, 140mA at -18, ISB1 ; from 100mA to 80mA 1. Add x32 org. and industrial temperature The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this device. If you have any questions, please contact the SAMSUNG branch office near your office, call or contact Headquarters. -1- Aug 2001 Rev 0.2 K7N403209B K7N403609B K7N401809B Preliminary 128Kx36 & 128Kx32 & 256Kx18 Pipelined NtRAMTM 4Mb NtRAM(Flow Through / Pipelined) Ordering Information Org. Part Number K7M401825B-QC(I)65/75/80 256Kx18 K7N401801B-QC(I)16/13 Mode VDD Speed FT ; Access Time(ns) Pipelined ; Cycle Time(MHz) FlowThrough 3.3 6.5/7.5/8.0 ns Pipelined 3.3 167/133 MHz K7N401809B-QC(I)25/22/20 Pipelined 3.3 250/225/200 MHz K7M403225B-QC(I)65/75/80 FlowThrough 3.3 6.5/7.5/8.0 ns Pipelined 3.3 167/133 MHz K7N403209B-QC(I)25/22/20 Pipelined 3.3 250/225/200 MHz K7M403625B-QC(I)65/75/80 FlowThrough 3.3 6.5/7.5/8.0 ns Pipelined 3.3 167/133 MHz Pipelined 3.3 250/225/200 MHz 128Kx32 K7N403201B-QC(I)16/13 128Kx36 K7N403601B-QC(I)16/13 K7N403609B-QC(I)25/22/20 -2- PKG Q :100TQFP Temp C (Commercial Temperature Range) I: (Industrial Temperature Range) Aug 2001 Rev 0.2 K7N403209B K7N403609B K7N401809B Preliminary 128Kx36 & 128Kx32 & 256Kx18 Pipelined NtRAMTM 128Kx36 & 128Kx32 & 256Kx18-Bit Pipelined NtRAMTM FEATURES GENERAL DESCRIPTION * V DD=3.3V+0.165V/-0.165V Power Supply. * V DDQ Supply Voltage 3.3V+0.165V/-0.165V for 3.3V I/O The K7N403609B, K7N403209B and K7N401809B are 4,718,592 bits Synchronous Static SRAMs. The NtRAM TM , or No Turnaround Random Access Memory utilizes all the bandwidth in any combination of operating cycles. Address, data inputs, and all control signals except output enable and linear burst order are synchronized to input clock. Burst order control must be tied "High or Low". Asynchronous inputs include the sleep mode enable(ZZ). Output Enable controls the outputs at any given time. Write cycles are internally self-timed and initiated by the rising edge of the clock input. This feature eliminates complex offchip write pulse generation and provides increased timing flexibility for incomming signals. For read cycles, pipelined SRAM output data is temporarily stored by an edge trigered output register and then released to the output bufferes at the next rising edge of clock. The K7N403609B, K7N403209B and K7N401809B are implemented with SAMSUNG s high performance CMOS technology and is available in 100pin TQFP packages. Multiple power and ground pins minimize ground bounce. or 2.5V+0.4V/-0.125V for 2.5V I/O. * Byte Writable Function. * Enable clock and suspend operation. * Single READ/WRITE control pin. * Self-Timed Write Cycle. * Three Chip Enable for simple depth expansion with no datacontention. * interleaved burst or a linear burst mode. * Asynchronous output enable control. * Power Down mode. * TTL-Level Three-State Outputs. * 100-TQFP-1420A Package. * Operating in commeical and industrial temperature range. FAST ACCESS TIMES PARAMETER Symbol -25 -22 -20 Unit Cycle Time tCYC 4.0 4.4 5.0 ns Clock Access Time tCD 2.4 2.6 2.8 ns Output Enable Access Time tOE 2.4 2.6 2.8 ns LOGIC BLOCK DIAGRAM LBO A [0:16]or A [0:17] CKE ADDRESS REGISTER A 2~A 16 or A 2~A 17 CONTROL LO GIC CLK A 0~A 1 ADV WE BW x (x=a,b,c,d or a,b) K CO NTRO L REG ISTER CS 1 CS 2 CS 2 WRITE ADDRESS REGISTER BURST ADDRESS COUNTER A 0 ~A 1 WRITE ADDRESS REGISTER 128Kx36/32 , 256Kx18 MEMORY ARRAY K DATA-IN REGISTER K DATA-IN REGISTER CONTROL LOGIC K OUTPUT REGISTER BUFFER OE ZZ 36/32 or 18 DQa 0 ~ DQd7 or DQa 0 ~ DQb8 DQPa ~ DQPd NtRAM TM and No Turnaround Random Access Memory are trademarks of Samsung, -3- Aug 2001 Rev 0.2 K7N403209B K7N403609B K7N401809B Preliminary 128Kx36 & 128Kx32 & 256Kx18 Pipelined NtRAMTM A6 A7 CS 1 CS 2 BWd BWc BWb BWa CS 2 V DD V SS CLK WE CK E OE ADV N.C. N.C. A8 A9 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 100 Pin TQFP (20mm x 14mm) 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 A4 A3 A2 A1 A0 N.C. N.C. V SS V DD N.C. N.C. A 10 A 11 A 12 A 13 A 14 A 15 A 16 K7N403609B(128Kx36) /K7N403209B(128Kx32) A5 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 LBO DQPc/NC DQc0 DQc1 V DDQ V SSQ DQc2 DQc3 DQc4 DQc5 V SSQ V DDQ DQc6 DQc7 V DD V DD V DD V SS DQd 0 DQd 1 V DDQ V SSQ DQd 2 DQd 3 DQd 4 DQd 5 V SSQ V DDQ DQd 6 DQd 7 DQPd/NC 100 PIN CONFIGURATION(TOP VIEW) 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 DQPb/NC DQb 7 DQb 6 V DDQ V SSQ DQb 5 DQb 4 DQb 3 DQb 2 V SSQ V DDQ DQb 1 DQb 0 V SS V DD V DD ZZ DQa 7 DQa 6 V DDQ V SSQ DQa 5 DQa 4 DQa 3 DQa 2 V SSQ V DDQ DQa 1 DQa 0 DQPa/NC PIN NAME SYMBOL PIN NAME A 0 - A 16 Address Inputs ADV WE CLK CKE CS 1 CS 2 CS 2 B Wx(x=a,b,c,d) OE ZZ LBO Address Advance/Load Read/Write Control Input Clock Clock Enable Chip Select Chip Select Chip Select Byte Write Inputs Output Enable Power Sleep Mode Burst Mode Control TQFP PIN NO. 32,33,34,35,36,37 44,45,46,47,48,49 50,81,82,99,100 85 88 89 87 98 97 92 93,94,95,96 86 64 31 SYMBOL PIN NAME TQFP PIN NO. V DD V SS N.C. Power Supply(+3.3V) Ground No Connect 14,15,16,41,65,66,91 17,40,67,90 38,39,42,43,83,84 DQa 0~a7 DQb 0~b7 DQc 0~c 7 DQd 0~d7 DQPa~Pd /NC V DDQ Data Inputs/Outputs 52,53,56,57,58,59,62,63 68,69,72,73,74,75,78,79 2,3,6,7,8,9,12,13 18,19,22,23,24,25,28,29 51,80,1,30 Output Power Supply (2.5V or 3.3V) Output Ground 4,11,20,27,54,61,70,77 V SSQ 5,10,21,26,55,60,71,76 Notes : 1. The pin 83 is reserved for address bit for the 8Mb NtRAM. 2. A0 and A 1 are the two least significant bits(LSB) of the address field and set the internal burst counter if burst is desired. 3. DQPa~Pd pins are NC for K7N403209B -4- Aug 2001 Rev 0.2 K7N403209B K7N403609B K7N401809B Preliminary 128Kx36 & 128Kx32 & 256Kx18 Pipelined NtRAMTM A7 CS 1 CS 2 N.C. N.C. BWb BWa CS 2 V DD V SS CLK WE CK E OE ADV N.C. N.C. A8 A9 98 97 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 96 A6 99 100 Pin TQFP (20mm x 14mm) 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 A4 A3 A2 A1 A0 N.C. N.C. V SS V DD N.C. N.C. A 11 A 12 A 13 A 14 A 15 A 16 A 17 K7N401809B(256Kx18) A5 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 LBO N.C. N.C. N.C. V DDQ V SSQ N.C. N.C. DQb 8 DQb 7 V SSQ V DDQ DQb 6 DQb 5 V DD V DD V DD V SS DQb 4 DQb 3 V DDQ V SSQ DQb 2 DQb 1 DQb 0 N.C. V SSQ V DDQ N.C. N.C. N.C. 100 PIN CONFIGURATION(TOP VIEW) 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 A 10 N.C. N.C. V DDQ V SSQ N.C. DQa 0 DQa 1 DQa 2 V SSQ V DDQ DQa 3 DQa 4 V SS V DD V DD ZZ DQa 5 DQa 6 V DDQ V SSQ DQa 7 DQa 8 N.C. N.C. V SSQ V DDQ N.C. N.C. N.C. PIN NAME SYMBOL PIN NAME A 0 - A 17 Address Inputs ADV WE CLK CKE CS 1 CS 2 CS 2 BWx(x=a,b) OE ZZ LBO Address Advance/Load Read/Write Control Input Clock Clock Enable Chip Select Chip Select Chip Select Byte Write Inputs Output Enable Power Sleep Mode Burst Mode Control TQFP PIN NO. 32,33,34,35,36,37, 44,45,46,47,48,49 50,80,81,82,99,100 85 88 89 87 98 97 92 93,94 86 64 31 SYMBOL PIN NAME TQFP PIN NO. V DD V SS N.C. Power Supply(+3.3V) 14,15,16,41,65,66,91 Ground 17,40,67,90 No Connect 1,2,3,6,7,25,28,29,30, 38,39,42,43,51,52,53, 56,57,75,78,79,83,84 95,96 DQa0~a8 DQb0~b8 Data Inputs/Outputs V DDQ Output Power Supply 4,11,20,27,54,61,70,77 (2.5V or 3.3V) Output Ground 5,10,21,26,55,60,71,76 V SSQ 58,59,62,63,68,69,72,73,74 8,9,12,13,18,19,22,23,24 Notes : 1. The pin 83 is reserved for address bit for the 8Mb NtRAM. 2. A0 and A1 are the two least significant bits(LSB) of the address field and set the internal burst counter if burst is desired. -5- Aug 2001 Rev 0.2 K7N403209B K7N403609B K7N401809B Preliminary 128Kx36 & 128Kx32 & 256Kx18 Pipelined NtRAMTM FUNCTION DESCRIPTION The K7N4036/3209B and K7N401809B are NtRAM TM designed to sustain 100% bus bandwidth by eliminating turnaround cycle when there is transition from Read to Write, or vice versa. All inputs (with the exception of O E, LBO and ZZ) are synchronized to rising clock edges. All read, write and deselect cycles are initiated by the ADV input. Subsequent burst addresses can be internally generated by the burst advance pin (ADV). ADV should be driven to Low once the device has been deselected in order to load a new address for next operation. Clock Enable(CKE) pin allows the operation of the chip to be suspended as long as necessary. When CKE is high, all synchronous inputs are ignored and the internal device registers will hold their previous values. NtRAM TM latches external address and initiates a cycle, when CKE, ADV are driven to low and all three chip enables( CS 1, CS 2, CS 2) are active . Output Enable(OE ) can be used to disable the output at any given time. Read operation is initiated when at the rising edge of the clock, the address presented to the address inputs are latched in the address register, CKE is driven low, all three chip enables( CS 1, CS 2 , CS 2) are active, the write enable input signals WE are driven high, and ADV driven low.The internal array is read between the first rising edge and the second rising edge of the clock and the data is latched in the output register. At the second clock edge the data is driven out of the SRAM. Also during read operation OE must be driven low for the device to drive out the requested data. Write operation occurs when WE is driven low at the rising edge of the clock. B W[d:a] can be used for byte write operation. The pipelined NtRAMTM uses a late-late write cycle to utilize 100% of the bandwidth. At the first rising edge of the clock, W E and address are registered, and the data associated with that address is required two cycle later. Subsequent addresses are generated by ADV High for the burst access as shown below. The starting point of the burst seguence is provided by the external address. The burst address counter wraps around to its initial state upon completion. The burst sequence is determined by the state of the LBO pin. When this pin is low, linear burst sequence is selected. And when this pin is high, Interleaved burst sequence is selected. During normal operation, ZZ must be driven low. When ZZ is driven high, the SRAM will enter a Power Sleep Mode after 2 cycles. At this time, internal state of the SRAM is preserved. When ZZ returns to low, the SRAM normally operates after 2 cycles of wake up time. BURST SEQUENCE TABLE LBO PIN HIGH First Address Fourth Address (Interleaved Burst, LBO=High) Case 1 A1 0 0 1 1 Case 2 A0 0 1 0 1 A1 0 0 1 1 Case 3 A0 1 0 1 0 A1 1 1 0 0 Case 4 A0 0 1 0 1 A1 1 1 0 0 A0 1 0 1 0 Note : 1. LBO pin must be tied to High or Low, and Floating State must not be allowed . BQ TABLE LBO PIN (Linear Burst, LBO =Low) LOW First Address Fourth Address Case 1 A1 0 0 1 1 Case 2 A0 0 1 0 1 A1 0 1 1 0 Case 3 A0 1 0 1 0 A1 1 1 0 0 Case 4 A0 0 1 0 1 A1 1 0 0 1 A0 1 0 1 0 Note : 1. LBO pin must be tied to High or Low, and Floating State must not be allowed . -6- Aug 2001 Rev 0.2 K7N403209B K7N403609B K7N401809B Preliminary 128Kx36 & 128Kx32 & 256Kx18 Pipelined NtRAMTM STATE DIAGRAM FOR N tRAMTM WRITE READ READ BEGIN READ BEGIN WRITE DS RE AD W DS AD W R IT E ST BUR TE E R BURST DS BURST READ BURST WRITE COMMAND DS WRI DESELECT DS BURST TE BUR ST D R EA DS RI WRITE BURST ACTION DESELECT READ BEGIN READ WRITE BEGIN WRITE BURST BEGIN READ BEGIN WRITE CONTINUE DESELECT Notes : 1. An IGNORE CLOCK EDGE cycle is not shown is the above diagram. This is because CKE HIGH only blocks the clock(CLK) input and does not change the state of the device. 2. States change on the rising edge of the clock(CLK) -7- Aug 2001 Rev 0.2 K7N403209B K7N403609B K7N401809B Preliminary 128Kx36 & 128Kx32 & 256Kx18 Pipelined NtRAMTM TRUTH TABLES SYNCHRONOUS TRUTH TABLE CS 1 CS 2 CS 2 ADV WE BWx OE CKE CLK ADDRESS ACCESSED OPERATION H X X L X X X L N/A Not Selected X L X L X X X L N/A Not Selected X X H L X X X L N/A Not Selected X X X H X X X L N/A Not Selected Continue L H L L H X L L External Address Begin Burst Read Cycle X X X H X X L L Next Address Continue Burst Read Cycle L H L L H X H L External Address NOP/Dummy Read X X X H X X H L Next Address Dummy Read L H L L L L X L External Address Begin Burst Write Cycle X X X H X L X L Next Address Continue Burst Write Cycle L H L L L H X L N/A NOP/Write Abort X X X H X H X L Next Address Write Abort X X X X X X X H Current Address Ignore Clock Notes : 1. X means "Don t Care". 2. The rising edge of clock is symbolized by (). 3. A continue deselect cycle can only be enterd if a deselect cycle is executed first. 4. WRITE = L means Write operation in WRITE TRUTH TABLE. WRITE = H means Read operation in WRITE TRUTH TABLE. 5. Operation finally depends on status of asynchronous input pins(ZZ and OE). WRITE TRUTH TABLE(x36/32) WE BWa BWb BW c BW d OPERATION H X X X X READ L L H H H WRITE BYTE a L H L H H WRITE BYTE b L H H L H WRITE BYTE c L H H H L WRITE BYTE d L L L L L WRITE ALL BYTEs L H H H H WRITE ABORT/NOP Notes : 1. X means "Dont Care". 2. All inputs in this table must meet setup and hold time around the rising edge of CLK(). WRITE TRUTH TABLE(x18) WE BWa BWb OPERATION H X X READ L L H WRITE BYTE a L H L WRITE BYTE b L L L WRITE ALL BYTEs L H H WRITE ABORT/NOP Notes : 1. X means "Dont Care". 2. All inputs in this table must meet setup and hold time around the rising edge of CLK() . -8- Aug 2001 Rev 0.2 K7N403209B K7N403609B K7N401809B Preliminary 128Kx36 & 128Kx32 & 256Kx18 Pipelined NtRAMTM ASYNCHRONOUS TRUTH TABLE OPERATION ZZ OE I/O STATUS Sleep Mode H X High-Z L L DQ L H High-Z Write L X Din, High-Z Deselected L X High-Z Read Notes 1. X means "Don t Care". 2. Sleep Mode means power Sleep Mode of which stand-by current does not depend on cycle time. 3. Deselected means power Sleep Mode of which stand-by current depends on cycle time. ABSOLUTE MAXIMUM RATINGS* PARAMETER SYMBOL RATING UNIT V DD -0.3 to 4.6 V Voltage on V DD Supply Relative to V SS Voltage on V DDQ Supply Relative to V SS V DDQ V DD V Voltage on Input Pin Relative to VSS V IN -0.3 to V DD+0.3 V Voltage on I/O Pin Relative to VSS V IO -0.3 to V DDQ+0.3 V Power Dissipation PD 1.4 W T STG -65 to 150 C TOPR 0 to 70 C TOPR -40 to 85 C T BIAS -10 to 85 C Storage Temperature Commercial Operating Temperature Industrial Storage Temperature Range Under Bias *Note : Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. OPERATING CONDITIONS at 3.3V I/O(0C TA 70C) PARAMETER Supply Voltage Ground SYMBOL MIN Typ. MAX UNIT V DD 3.135 3.3 3.465 V V DDQ 3.135 3.3 3.465 V V SS 0 0 0 V OPERATING CONDITIONS at 2.5V I/O(0C TA 70C) PARAMETER Supply Voltage Ground SYMBOL MIN Typ. MAX UNIT V DD 3.135 3.3 3.465 V V DDQ 2.375 2.5 2.9 V V SS 0 0 0 V CAPACITANCE*(TA =25C, f=1MHz) PARAMETER Input Capacitance Output Capacitance SYMBOL TEST CONDITION MIN MAX UNIT C IN V IN=0V - 5 pF COUT V OUT=0V - 7 pF *Note : Sampled not 100% tested. -9- Aug 2001 Rev 0.2 K7N403209B K7N403609B K7N401809B Preliminary 128Kx36 & 128Kx32 & 256Kx18 Pipelined NtRAMTM DC ELECTRICAL CHARACTERISTICS (VDD =3.3V+0.165V/-0.165V, TA =0C to +70C) PARAMETER SYMBOL Input Leakage Current(except ZZ) IIL V DD=Max ; V IN=V SS to V DD Output Leakage Current IOL Output Disabled, ICC Operating Current ISB Standby Current TEST CONDITIONS V DD=Max IOUT=0mA Cycle Time tCYC Min Device deselected, I OUT=0mA, ZZV IL , f=Max, All Inputs0.2V or V DD-0.2V MIN MAX UNIT -2 +2 A A -2 +2 -25 - 400 -22 - 360 -20 - 330 -25 - 160 -22 - 155 -20 - 150 mA NOTES 1,2 mA ISB1 Device deselected, I OUT=0mA, ZZ0.2V, f=0, All Inputs=fixed (V DD-0.2V or 0.2V) - 80 mA ISB2 Device deselected, I OUT=0mA, ZZV DD-0.2V, f=Max, All InputsV IL or V IH - 50 mA Output Low Voltage(3.3V I/O) V OL IOL =8.0mA - 0.4 V Output High Voltage(3.3V I/O) V OH IOH=-4.0mA 2.4 - V Output Low Voltage(2.5V I/O) V OL IOL =1.0mA - 0.4 V Output High Voltage(2.5V I/O) V OH IOH=-1.0mA 2.0 - V Input Low Voltage(3.3V I/O) V IL -0.3* 0.8 V Input High Voltage(3.3V I/O) V IH 2.0 V DD+0.3** V Input Low Voltage(2.5V I/O) V IL -0.3* 0.7 V Input High Voltage(2.5V I/O) V IH 1.7 V DD+0.3** V 3 3 Notes : 1. Reference AC Operating Conditions and Characteristics for input and timing. 2. Data states are all zero. 3. In Case of I/O Pins, the Max. VIH =V DDQ+0.3V VIH VSS VS S -1.0V 20% t CYC (MIN) TEST CONDITIONS (VDD=3.3V+0.165V/-0.165V,VDDQ=3.3V+0.165/-0.165V or VDD=3.3V+0.165V/-0.165V,VDDQ=2.5V+0.4V/-0.125V, TA=0to70C) PARAMETER VALUE Input Pulse Level(for 3.3V I/O) 0 to 3.0V Input Pulse Level(for 2.5V I/O) 0 to 2.5V Input Rise and Fall Time(Measured at 20% to 80% for 3.3V I/O) 1.0V/ns Input Rise and Fall Time(Measured at 20% to 80% for 2.5V I/O) 1.0V/ns Input and Output Timing Reference Levels for 3.3V I/O 1.5V Input and Output Timing Reference Levels for 2.5V I/O V DDQ /2 Output Load See Fig. 1 - 10 - Aug 2001 Rev 0.2 K7N403209B K7N403609B K7N401809B Preliminary 128Kx36 & 128Kx32 & 256Kx18 Pipelined NtRAMTM Output Load(A) Output Load(B), (for tLZC, tLZOE , tHZOE & tHZC) +3.3V for 3.3V I/O /+2.5V for 2.5V I/O RL=50 Dout Zo=50 30pF* VL=1.5V for 3.3V I/O V DDQ /2 for 2.5V I/O 319 / 1667 Dout 353 / 1538 5pF* * Including Scope and Jig Capacitance Fig. 1 AC TIMING CHARACTERISTICS (VDD=3.3V+0.165V/-0.165V, T A=0C to +70C) -25 PARAMETER Cycle Time Symbol Min -22 Max Min -20 Max Min Max UNIT tCYC 4.0 - 4.4 - 5.0 - ns Clock Access Time tCD - 2.4 - 2.6 - 2.8 ns Output Enable to Data Valid tOE - 2.4 - 2.6 - 2.8 ns Clock High to Output Low-Z tLZC 0.8 - 1.0 - 1.0 - ns Output Hold from Clock High tOH 0.8 - 1.0 - 1.0 - ns Output Enable Low to Output Low-Z tLZOE 0 - 0 - 0 - ns Output Enable High to Output High-Z tHZOE - 2.4 - 2.6 - 2.8 ns Clock High to Output High-Z tHZC - 2.4 - 2.6 - 2.8 ns Clock High Pulse Width tCH 1.7 - 2.0 - 2.0 - ns Clock Low Pulse Width tCL 1.7 - 2.0 - 2.0 - ns Address Setup to Clock High tAS 0.8 - 1.2 - 1.2 - ns CKE Setup to Clock High tCES 0.8 - 1.2 - 1.2 - ns Data Setup to Clock High tDS 0.8 - 1.2 - 1.2 - ns Write Setup to Clock High (WE, BWX) tWS 0.8 - 1.2 - 1.2 - ns Address Advance Setup to Clock High tADVS 0.8 - 1.2 - 1.2 - ns tCSS 0.8 - 1.2 - 1.2 - ns Chip Select Setup to Clock High Address Hold from Clock High tAH 0.3 - 0.4 - 0.4 - ns CKE Hold from Clock High tCEH 0.3 - 0.4 - 0.4 - ns Data Hold from Clock High tDH 0.3 - 0.4 - 0.4 - ns Write Hold from Clock High (WE , BWE X) tWH 0.3 - 0.4 - 0.4 - ns Address Advance Hold from Clock High tADVH 0.3 - 0.4 - 0.4 - ns Chip Select Hold from Clock High tCSH 0.3 - 0.4 - 0.4 - ns ZZ High to Power Down tPDS 2 - 2 - 2 - cycle ZZ Low to Power Up tPUS 2 - 2 - 2 - cycle Notes : 1. All address inputs must meet the specified setup and hold times for all rising clock(CLK) edges when ADV is sampled low and CS is sampled low. All other synchronous inputs must meet the specified setup and hold times whenever this device is chip selected. 2. Chip selects must be valid at each rising edge of CLK(when ADV is Low) to remain enabled. 3. A write cycle is defined by WE low having been registered into the device at ADV Low, A Read cycle is defined by WE High with ADV Low, Both cases must meet setup and hold times. 4. To avoid bus contention, At a given voltage and temperature tLZC is more than tHZC. The specs as shown do not imply bus contention because tLZC is a Min. parameter that is worst case at totally different test conditions (0C,3.465V) than tH Z C, which is a Max. parameter(worst case at 70C,3.135V) It is not possible for two SRAMs on the same board to be at such different voltage and temperature. - 11 - Aug 2001 Rev 0.2 K7N403209B K7N403609B K7N401809B Preliminary 128Kx36 & 128Kx32 & 256Kx18 Pipelined NtRAMTM SLEEP MODE SLEEP MODE is a low current, power-down mode in which the device is deselected and current is reduced to I SB2. The duration of SLEEP MODE is dictated by the length of time the ZZ is in a High state. After entering SLEEP MODE, all inputs except ZZ become disabled and all outputs go to High-Z The ZZ pin is an asynchronous, active high input that causes the device to enter SLEEP MODE. When the ZZ pin becomes a logic High, ISB2 is guaranteed after the time t ZZI is met. Any operation pending when entering SLEEP MODE is not guaranteed to successful complete. Therefore, SLEEP MODE (READ or WRITE) must not be initiated until valid pending operations are completed. similarly, when exiting SLEEP MODE during t PUS, only a DESELECT or READ cycle should be given while the SRAM is transitioning out of SLEEP MODE. SLEEP MODE ELECTRICAL CHARACTERISTICS DESCRIPTION Current during SLEEP MODE CONDITIONS SYMBOL ZZ V IH ISB2 MIN MAX 10 UNITS mA ZZ active to input ignored tPDS 2 cycle ZZ inactive to input sampled tPUS 2 cycle ZZ active to SLEEP current tZZI ZZ inactive to exit SLEEP current tRZZI 2 cycle 0 SLEEP MODE WAVEFORM K t PDS ZZ setup cycle tPUS ZZ recovery cycle ZZ t ZZI Isupply ISB2 tRZZI All inputs (except ZZ) Deselect or Read Only Deselect or Read Only Normal operation cycle Outputs (Q) High-Z DON T CARE - 12 - Aug 2001 Rev 0.2 - 13 - Data Out OE ADV CS WRITE Address CKE Clock A1 tADVH tCSH tWH tAH tLZOE tOE Q 1-1 A2 tHZOE tCEH Q 2-1 tCD tOH tCYC Q2-2 tCL NO TE S : WRITE = L me ans WE = L, an d B Wx = L CS = L mean s CS1 = L, CS2 = H and CS2 = L CS = H means CS1 = H, or CS1 = L and CS 2 = H, or CS 1 = L, and CS 2 = L tADVS tCSS tWS tAS tCES tCH Q 2-3 A3 TIMING WAVEFORM OF READ CYCLE Q2-4 Q 3-1 Q 3-2 Q3-3 Un defined Do nt Care Q3-4 tHZC K7N403209B K7N403609B K7N401809B Preliminary 128Kx36 & 128Kx32 & 256Kx18 Pipelined NtRAMTM Aug 2001 Rev 0.2 - 14 - Data Out Data In OE ADV CS WRITE Address CKE Clock Q 0-4 tHZOE D1-1 A2 tCYC tCL D2-1 D2-2 NOTES : WRITE = L means WE = L, a nd BWx = L CS = L me ans CS1 = L, CS2 = H a nd CS 2 = L CS = H mean s CS1 = H, or CS1 = L and CS2 = H, or CS1 = L, and CS2 = L Q0-3 A1 tCES tCEH tCH D2-3 A3 TIMING WAVEFORM OF WRTE CYCLE D2-4 D3-1 tDS D3-2 tDH D3-3 Undefined Dont Ca re D3-4 K7N403209B K7N403609B K7N401809B Preliminary 128Kx36 & 128Kx32 & 256Kx18 Pipelined NtRAMTM Aug 2001 Rev 0.2 - 15 - Data In Data Out OE ADV CS WRITE Address CKE Clock tOE tLZOE A2 Q1 A3 tDS D2 tDH Q3 A4 NOTES : WRITE = L means WE = L, a nd BWx = L CS = L me ans CS1 = L, CS2 = H a nd CS 2 = L CS = H mean s CS1 = H, or CS1 = L and CS2 = H, or CS1 = L, and CS2 = L A1 tCES tCEH A5 Q4 A6 D5 A7 TIMING WAVEFORM OF SINGLE READ/WRITE tCH Q6 tCYC tCL A8 Q7 A9 Undefined Dont Car e K7N403209B K7N403609B K7N401809B Preliminary 128Kx36 & 128Kx32 & 256Kx18 Pipelined NtRAMTM Aug 2001 Rev 0.2 - 16 - Data In A1 tCES tCEH tCD tLZC A2 Q1 tHZC A3 NO TE S : WRITE = L me ans WE = L, an d B Wx = L CS = L mean s CS1 = L, CS2 = H and CS2 = L CS = H means CS1 = H, or CS1 = L and CS 2 = H, or CS 1 = L, and CS 2 = L Data Out OE ADV CS WRITE Address CKE Clock tDS D2 A4 TIMING WAVEFORM OF CKE OPERATION tDH tCH Q3 tCYC tCL A5 Q4 A6 Undefined Dont Care K7N403209B K7N403609B K7N401809B Preliminary 128Kx36 & 128Kx32 & 256Kx18 Pipelined NtRAMTM Aug 2001 Rev 0.2 - 17 - Data In Data Out OE ADV CS WRITE Address CKE Clock A1 tCEH tOE tLZOE A2 Q1 Q2 tHZC A3 NO TE S : WRITE = L me ans WE = L, an d B Wx = L CS = L mean s CS1 = L, CS2 = H and CS2 = L CS = H means CS1 = H, or CS1 = L and CS 2 = H, or CS 1 = L, and CS 2 = L tCES D3 tDS tDH A4 tCD tLZC TIMING WAVEFORM OF CS OPERATION Q4 A5 tCH tCYC tCL D5 Undefined Dont Care K7N403209B K7N403609B K7N401809B Preliminary 128Kx36 & 128Kx32 & 256Kx18 Pipelined NtRAMTM Aug 2001 Rev 0.2 K7N403209B K7N403609B K7N401809B Preliminary 128Kx36 & 128Kx32 & 256Kx18 Pipelined NtRAMTM PACKAGE DIMENSIONS 100-TQFP-1420A Units ; millimeters/Inches 22.00 0.30 20.00 0.20 0~8 0.10 0.127 +- 0.05 16.00 0.30 14.00 0.20 0.10 MAX (0.83) 0.50 #1 0.65 0.10 (0.58) 0.30 0.10 0.10 MAX 1.40 0.10 1.60 MAX 0.50 0.10 - 18 - 0.05 MIN Aug 2001 Rev 0.2