DM74S373N - Fairchild Semiconductor

August 1986

Revised May 2000

DM74S373 • DM74S374 3-STATE Octal D-Type Transparent Latches and Edge-Triggered Flip-Flops

DM74S373 • DM74S374

3-STATE Octal D-Type Transparent Latches

and Edge-Triggered Flip-Flops

General Description

These 8-bit registers feature totem-pole 3-STATE outputs

designed specifically for driving highly-capacitive or rela-

tively low- impe dan ce l oa ds. Th e high-imped ance state and

increased high-logic-level drive provide these registers with

the capability of being connected directly to a nd driving the

bus line s i n a bu s-or ga nized system wi th ou t n eed fo r i nte r-

face or pull- up components. They are particularly attractive

for implementing buffer registers, I/O ports, bidirectional

bus drivers, and working registers.

The eigh t latch es o f the D M 74 S373 are tran spa ren t D -ty pe

latches meaning that while the enable (G) is HIGH the Q

output s will follow the da ta (D) inputs. When the enable i s

taken LOW the output will be latched at the level of the

data that was set up.

The eight flip-flops of the DM74S374 are edge-triggered D-

type flip-flo ps. On the po sitive tr ansiti on of the clock , the Q

outputs will be set to the logic states that were set up at the

D inputs.

Schmitt-trigger buffered inputs at the enable/clock lines

simplify system design as ac and dc noise rejection is

improved by typically 400 mV due to the input hysteresis. A

buffered output control input can be used to place the eight

outputs in either a no rmal logic state (HIGH or LOW logic

levels) or a high-impedance state. In the high-impedance

state the outputs neither load nor drive the bus lines signifi-

cantly.

The outpu t control do es not affect the intern al opera tion of

the latches or flip-flops. That is, the old data can be

retained or new data can be entered even while the outputs

are OFF.

Features

■Choice of 8 latches or 8 D-type flip-flops in a single

package

■3-STATE bus-driving outputs

■Full parallel-access for loading

■Buffered control input s

■P-N-P input reduce D-C loading on data lines

Ordering Code:

Devices also available in Tape and Reel. Spe ci fy by append ing the suffix let t er “X” to the o rdering code.

Connection Diagrams

DM74S373N DM74S374N

Order Number Package Number Package Description

DM74S373WM M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide

DM74S373N N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

DM74S374WM M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide

DM74S374N N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

www.fairchildsemi.com 2

DM74S373 • DM74S374

Truth Tables

DM74S373

H = HIGH Level (St eady St ate)

L = LOW Lev el (Steady St at e)

X = Don’t Care

Z = High Impeda nc e State

↑ = Transition f rom LOW-to-HIGH lev el,

Q0 = The level of the output before steady-state input conditions were

established.

DM74S374

Logic Diagrams

74S373

Transpar en t Lat ch es 74S374

Positive-Edge-T riggered Flip-Flops

Output Enable D Output

Control G

LHHH

LHLL

LLXQ

HXXZ

Output Clock D Output

Control

L↑HH

L↑LL

LLXQ

HXXZ

3 www.fairchildsemi.com

DM74S373 • DM74S374

Absolute Maximum Ratings(Note 1) Note 1: The “A bsolute Maximum Ratings” are thos e values bey ond which

the saf ety of the device cannot be gu aranteed. Th e device shou ld not be

operated at these limits. The parametric values defined in the Electrical

Char ac teristi c s tables a re not guar anteed at t he absolute m ax imum r atings.

The “R ecomm ended Ope rating Co ndition s” table will define the condit ions

for actu al device operation.

DM74S373 Recommended Operating Conditions

Note 2: CL = 15 pF, RL = 280Ω, TA = 25 °C and VCC = 5V.

Note 3: CL = 50 pF and RL = 280Ω, TA = 25°C and VCC = 5V.

Note 4: The symbol (↓) indicates the falling edge of the clock pulse is used for reference.

Note 5: TA = 25°C an d VCC = 5V.

DM74S373 Electrical Characteristics

over recommended operating free air temperature (unless otherwise noted)

Note 6: All typ icals are at VCC = 5V, TA = 25°C.

Note 7: Not more than one out put shou ld be shorte d at a t im e, and the duration sh ould not ex c eed one s ec ond.

Supply Voltage 7V

Input Voltage 5.5V

Operating Free Air Temperature Range 0°C to +70°C

Storage Temperature Range −65°C to +150°C

Symbol Parameter Min Nom Max Units

VCC Supply Voltage 4.75 5 5.25 V

VIH HIGH Level Input Voltage 2 V

VIL LOW Level Input Voltage 0.8 V

IOH HIGH Level Output Current −6.5 mA

IOL LOW Level Output Current 20 mA

tWPulse Width (Note 2) Enable HIGH 6 ns

Enable LOW 7.3

tWPulse Width (Note 3) Enable HIGH 15 ns

Enable LOW 15 ns

tSU Data Setup Time (Note 4)(Note 5) 0↓ns

tHData Hold Time (Note 4)(Note 5) 10↓ns

TAFree Air Operating Temperature 0 70 °C

Symbol Parameter Conditions Min Typ Max Units

(Note 6)

VIInput Clamp Voltage VCC = Min, II = −18 mA −1.2 V

VOH HIGH Level VCC = Min, IOH = Max 2.4 3.2 V

Output Voltage VIL = Max, VIH = Min

VOL LOW Level VCC = Min, IOL = Max 0.5 V

Output Voltage VIH = Min, VIL = Max

IIInput Current @ Max Input Voltage VCC = Max, VI = 5.5V 1 mA

IIH HIGH Level Input Current VCC = Max, VI = 2.7V 50 µA

IIL LOW Level Input Current VCC = Max, VI = 0.5V −250 µA

IOZH Off-State Output Current with VCC = Max, VO = 2.4V 50 µA

HIGH Level Output Voltage Applied VIH = Min, VIL = Max

IOZL Off-State Output Current with VCC = Max, VO = 0.5V −50 µA

LOW Level Output Voltage Applied VIH = Min, VIL = Max

IOS Short Circuit Output Current VCC = Max (Note 7) −40 −100 mA

ICC Supply Current VCC = Max Outputs HIGH or LOW 105 160 mA

Outputs Disabled 190

www.fairchildsemi.com 4

DM74S373 • DM74S374

DM74S373 Switching Characteristics

at VCC = 5V and TA = 25°C

Note 8: CL = 5 pF

DM74S374 Recommended Operating Conditions

Note 9: CL = 15 pF, R L = 280Ω, TA = 25°C and VCC = 5V.

Note 10: CL = 50 pF, RL = 280Ω, TA = 25°C and VCC = 5V.

Note 11: The sy m bol (↑) indicates the rising edge of the clock pulse is used for reference.

Note 12: TA = 25°C and VCC = 5V.

RL = 280Ω

Symbol Parameter From (Input) CL = 15 pF CL = 50 pF Units

To (Output) Min Max Min Max

tPLH Propagati on Delay T ime Data to Any Q 12 14 ns

LOW-to-HIGH Level Output

tPHL Propagation Del ay Ti me Data to Any Q 12 16 ns

HIGH-to-LOW Level Output

tPLH Propagati on Delay T ime Enable to Any Q 14 14 ns

LOW-to-HIGH Level Output

tPHL Propagation Del ay Ti me Enable to Any Q 18 21 ns

HIGH-to-LOW Level Output

tPZH Enable Time to Output Control to Any Q 15 17 ns

HIGH Level Output

tPZL Output Enable Time to Output Control to Any Q 18 23 ns

LOW Level Output

tPHZ Output Disable Time to Output Control to Any Q 9 ns

HIGH Level Output (Note 8)

tPLZ Output Disable Time to Output Control to Any Q 12 ns

LOW Level Output (Note 8)

Symbol Parameter Min Nom Max Units

VCC Supply Voltag e 4.75 5 5. 25 V

VIH HIGH Level Input Voltage V

VIL LOW Level Input Voltage 0.8 V

IOH HIGH Level Output Current −6.5 mA

IOL LOW Level Output Current 20 mA

fCLK Clock Frequency (Note 9) 0 75 MHz

fCLK Clock Frequency (Note 10) 0 75 MHz

tWPulse Width Clock HIGH 6

(Note 9) Clock LOW 7.3 ns

Pulse Width Clock HIGH 15

(Note 10) Clock LOW 15

tSU Data Setup Time (Note 11)(Note 12) 5↑ns

tHData Hold Time (Note 11)(Note 12) 2↑ns

TAFree Air Operating Temperature 0 70 °C

5 www.fairchildsemi.com

DM74S373 • DM74S374

DM74S374 Electrical Characteristics

over recommended operating free air temperature (unless otherwise noted)

Note 13: All typic als are at VCC = 5V, TA = 25°C.

Note 14: Not more than one output should be shorted at a time, and the duration should not exceed one second.

DM74S374 Switching Characteristics

at VCC = 5V and TA = 25°C

Note 15: CL = 5 pF

Symbol Parameter Conditions Min Typ Max Units

(Note 13)

VIInput Clamp Voltage VCC = Min, II = −18 mA −1.2 V

VOH HIGH Level VCC = Min, IOH = Max 2.4 3.2 V

Output Voltage VIL = Max, VIH = Min

VOL LOW Level VCC = Min, IOL = Max 0.5 V

Output Voltage VIH = Min, VIL = Max

IIInput Current @ Max Input Voltage VCC = Max, VI = 5.5V 1 mA

IHHIGH Level Input Current VCC = Max, VI = 2.7V 50 µA

IIL LOW Level Input Current VCC = Max, VI = 0.5V −250 µA

IOZH Off-State Output Current with VCC = Max, VO = 2.4V 50 µA

HIGH Level Output Voltage Applied VIH = Min, VIL = Max

IOZL Off-State Output Current with VCC = Max, VO = 0.5V −50 µA

LOW Level Output Voltage Applied VIH = Min, VIL = Max

IOS Short Circuit Output Current VCC = Max (Note 14) −40 −100 mA

ICC Supply Current VCC = Max Outputs HIGH 110 mAOutputs LOW 90 140

Outputs Disabled 160

RL = 280Ω

Symbol Parameter From (Input) CL = 15 pF CL = 50 pF Units

To (Ou tput) Min Max M in Ma x

fMAX Maximum Clock Frequency 75 75 MHz

tPLH Propagation Delay Time Clock to Any Q 15 15 ns

LOW-to-HIGH Level Output

tPHL Propagation Delay Time Clock to Any Q 17 20 ns

HIGH-to-LOW Level Output

tPZH Output Enable Time to Output Control to Any Q 15 17 ns

HIGH Level Output

tPZL Output Enable Time to Output Control to Any Q 18 23 ns

LOW Level Output

tPHZ Output Disable Time from Output Control to Any Q 9 ns

HIGH Level Output (Note 15)

tPLZ Output Disable Time from Output Control to Any Q 12 ns

LOW Level Output (Note 15)

www.fairchildsemi.com 6

DM74S373 • DM74S374

Physical Dimensions inches (millimeters) unless otherwise noted

20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide

Package Number M20B

7 www.fairchildsemi.com

DM74S373 • DM74S374 3-STATE Octal D-Type Transparent Latches and Edge-Triggered Flip-Flops

Physical Dim ensions inches (millimeters) unless otherwise noted (Continued)

20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

Package Number N20A

Fairchild does not assume an y responsibility for u se of any circuitry d escribed, no circu it patent licenses are implied and

Fairchild reserves the right at any time without notice to change said circuitry and specifications.

LIFE SUPPORT POLICY

FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT

DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD

SEMICONDUCTOR CORPORATION. As used herein:

1. Life suppor t de vices o r syst ems are dev ic es or syste ms

which, (a) are intended for surgical implant into the

body, or (b) support or sustain life, and (c) whose failure

to perform when properly used in accordance with

instruct ions fo r use pr ovi de d in the l abe ling, can be rea-

sonably expected to result in a significant injury to the

user.

2. A crit ical componen t in any com ponen t of a life s uppor t

device or system whose failure to perform can be rea-

sonabl y e xpec ted to cause th e fa i lure of the l ife s upport

device or system, or to affect its safety or effectiveness.