1
PBL 402 15
January 2001
Preliminary
RF Transceiver circuit for the Digital
Enhanced Cordless Telecommunications
(DECT) system
PBL 402 15
Description.
The PBL 402 15 is a complete RF transceiver to be used in the Digital Enhanced
Cordless Telecommunications ( DECT ) system. It is designed to interface to various
base-band controllers.
The circuit contains transmit and receive functions that share integrated high stability
VCO´s and a phase locked loop function ( PLL ). All functionality is controlled through a
3-wire bus interface with optional hard wire lines.
The receive section comprises of a low noise image reject down conversion to the
first intermediate frequency, an external channel filter, a second down convertion to a
second intermediate frequency, an integrated channel pass filter, a high gain limiting
amplifier, a received signal strenght indicator with DC compensation loop, a self aligned
frequency discriminator and a preamble based data slicer.
The transmit section comprises of a signal gate and a pre-power amplifier. Data
transmission is achieved by direct open loop modulation of the Tx VCO.
Key features.
• High Tx output power to +7dBm
• Integrated PLL and high stability
VCO´s
• 3-line serial interface bus
• Minimum 2.7 V supply voltage
• Low current consumption
• Differential Rx input and Tx output
• Flexible interface to various base-
band controllers
• Exellent performance with Ericsson´s
power amplifier PBL403 09
• Low cost
Applications:
• DECT Handset and base station
• Wireless local area network ( WLAN )
• Wireless local loop ( WLL )
Figure 1. Block diagram. Figure 2. Package outlook.
PBL 402 15
2
PBL 402 15
PBL402 15
1
2
3
4
5
6
7
8
9
10
11
1213 14 15 16 17 18 19 20 21 22 23 24
48 47 46 45 44 43 42 41 40 39 38 37
36
35
34
33
32
31
30
29
28
27
26
25
EN
REF
VccPLL
GND
VccCP
NC
NC
680 pF
C1
C0
6.8nF
R0
3.9k
C2
100nF
VccVCO
Regulated supply Vcc
GND
DTx MOD SHold
2nF
C3
DRx DSL
RSSI
VccFM Vcc
GND
C18 22nF
L1
140nH *
C7 68pF *
C6 68pF *
GND
VccIF
MS lines 2
MS lines 3
MS lines 1
LD
IF - SAW filter
+
+
_
_
in
out
L0
180nH *
C4 11pF *
C5 11pF *
GND
GND C10 8pF C8 1pF
C11 8pF
C9
L4
8.2nH
L3
5.6nH
L2 5.6nF
RxEN TxEN ST CK D GATE
GND
GND GND
L6 4.7nH
L5 4.7nH
C13 1pF
C12 1pF
+in
-in
+out
-out
Vcc
Gate
C16
10nF C17
33pF
C14
2.2nF C15
8pF
PA - Vcc
Consult PBL40309 for PA
output matching requirements
RF in to Rx
Feed from antenna switch.
( 50 ohms )
CP
V
TUNE
PA Gate
Can also be a balun type of solution
GND 1pF
* These components for matching are not needed if Murata filter is used
Figure 3. DECT application.
Figure 4. The European DECT band .
EUROPEAN DECT Band 1880 - 1900 MHz
Channel 0
1
2
3
4
5
6
7
8
9
10 channels
Channel spacing
1.728 MHz
TDMA ( time division multiple access )
Frequency and time division.
Frame =10 ms
24 time slots
1 slot = 416.67µseach slot contains, a synchronisation field,
control info, data package and error control.
Frequency
Time
12345678910
11 12 13 14 15 16 17 18 19 20 22 2321
Base to Mobile Mobile to Base
0
Frequency MHz
1881.792
1883.520
1885.248
1886.976
1888.704
1890.432
1892.160
1893.888
1895.616
1897.344
A-word
CNT_A
1
2
3
4
5
6
7
8
9
10
3
PBL 402 15
1
2
3
4
5
6
7
8
9
10
11
12
13
14
36
35
34
33
32
31
30
29
28
27
26
25
REF
VccPLL
GndPLL
VccCP
CP
GndCP
VTUNE
GndVCO
NC
NC
VccVCO
EN GndRF
RX+
RX-
GndRF
PA Gate
IFOUT+
IFOUT-
LD
VccIF
GndIF
IFIN+
IFIN-
GndFM
DTX
MOD
SHOLD
DRX
DSL
VccFM
RSSI
VccRSSI
CAP+
CAP-
GndRSSI
RXEN
DIE
TXEN
ST
CK
D
GATE
VccRF
GndRF
TX+
TX-
GndRF
15 16 17 18 19 20 21 22 23 24
48 47 46 45 44 43 42 41 40 39 38 37
Figure 5. Pinning configuration.
Pin Descriptions:
Refer to pin configuration.
Pin number Name Function Schematic in/output of the pin
1 EN Enable 3-wire interface and synthesiser.
2 REF PLL reference clock input
3VCCPLL Voltage supply to the frequency synthesiser.
4 GndPLL Ground connection to the frequency synthesiser.
5 GndCP Ground connection to the charge pump.
6 CP Charge pump output.
7VCCCP Voltage supply to the charge pump.
VCCPLL
EN
GndPLL
165 k
V
CC
PLL
REF
GndPLL
Clamp to GndPLL
A diode to GndCP and GndRF
A diode to GndPLL and GndVCO
V
CC
CP
CP
GndCP
Clamp to GndCP
4
PBL 402 15
Pin Descriptions (cont.):
Pin number Name Function Schematic in/output of the pin
8 Not connected
9 Not connected
10 VCCVCO Voltage supply to the VCO
11 VTUNE Tuning voltage input for the VCO
12 GndVCO Ground connection to the VCO
13 GndFM Ground connection to the FM discriminator section.
14 DTX Tx data input for either analog or logic signal.
15 MOD Apply modulation. The PLL is set into open loop
condition and modulation is applied to the VCO.
16 SHOLD Slice level hold logic input. (In Tx mode this input
may also act as the MOD pin).
17 DRX Rx data output of FM discriminator for either analog
or logic signal.(In standby mode outputs lock detect)
18 DSL Data slice level output.
19 VCCFM Voltage supply to the FM discriminator section.
20 RSSI RSSI output of limiting strip detector chain.
N/C
Clamp to GndVCO
V
CC
VCO
VTUNE
GndVCO
A diode to GndCP and GndFM
VCCFM
DTX
GndFM
V
CC
FM
MOD
GndFM
Bias
V
CC
FM
SHOLD
GndFM
Bias
V
CC
FM
DRX
GndFM
V
CC
FM
DSL
GndFM
Clamp to GndFM
21 VCCRSSI Voltage supply to the RSSI section.
22 CAP+ External stabilising capacitors for limiting strip
DC input offset correction loop.
23 CAP-
V
CC
RSSI
RSSI
GndRSSI
Clamp to GndRSSI
V
CC
RSSI
CAP+/CAP-
Both inputs alike
GndRSSI
5
PBL 402 15
Pin Descriptions (cont.):
Pin number Name Function Schematic in/output of the pin
24 GndRSSI Ground connection to the RSSI.
25 PA Gate Output control signal for external PA power on/off.
26 IFIN- Rx IF inputs to internal channel filtering, limiting
amplifiers,RSSI and FM discriminator. Internally
27 IFIN+ matched to 300 Ω.
28 GndIF Ground connection to the down IF convertor and
channel filter sections.
29 VCCIF Voltage supply to the down IF convertor and
channel filter sections.
30 LD Lock detect.
31 IFOUT- Rx IF outputs to external adjacent channel filter.
Internally matched to 300Ω.
32 IFOUT+
33, 36 GndRF Ground connection to the RF sections.
37, 40
34 RX- RF inputs to LNA and image reject mixer.
35 RX+ Internally matched to 100Ω.
38 TX- Tx outputs to external PA. Internally matched to
39 TX+ 100 Ω. Each output requires an externalchoke
to VCC.
41 VCCRF Voltage supply to the RF sections.
42 GATE Input to gate the Tx output power.
43 D Serial interface, Data .
A diode to GndFM and GndIF
V
CC
RF
PA - Gate
GndRF
V
CC
IF
IFIN-/IFIN+
both inputs alike
GndIF
A diode to GndFM and GndIF
Clamp to GndIF
V
CC
RF
LD
GndRF
V
CC
RF
IFOUT-/IFOUT+
both outputs alike
GndRF
A diode to GndIF and GndPLL
V
CC
RF
RX-/RX+
both inputs alike
GndRF
V
CC
RF
TX-/TX+
Both inputs alike
GndRF
Clamp to GndRF
V
CC
PLL
GATE
GndPLL
Bias
V
CC
PLL
D
GndPLL
Bias
6
PBL 402 15
Pin Descriptions (cont.):
Pin number Name Function Schematic in/output of the pin
44 CK Serial interface, Clock .
45 ST Serial interface, Strobe .
46 TXEN Transmitter enable.
47 DIE Gnd. pin used for internal shielding. Connected
to DIE substrate.
48 RXEN Receiver enable
V
CC
PLL
CK
GndPLL
Bias
V
CC
PLL
ST
GndPLL
165 k
V
CC
PLL
TXEN
GndPLL
Bias
VCCPLL
RXEN
GndPLL
Bias
7
PBL 402 15
÷2
-π/4
π/4
TXEN
RXEN
EN
ST
CK
D
Control
Slice
control
IFOUT IFIN
IR RX
TXOUT
RXIN
PIN switch
×2
ƒ-φ
DTX
RSSI
FM Demod
IF Filt
CAP
PLL
TX
Modulator
GATE
CP
VTUNE REF
MOD
IR IF
RSSI
DSL DRX
SHOLD
+
+
PA-GATE
LD
LD
Slave PLL
÷2
÷R
IF2
+
π/4
-π/4
÷2
π/4
-π/4
÷2
Figure 6. Block diagram.
Maximum Ratings
Parameter Condition Symbol Min. Typ. Max. Unit
Supply voltage Vcc 5.5 V
Voltage applied between two different Vccdiff 0.6 V
supply pins, except VccRF (a)
Voltage applied between two Grounds are clamped together Gnddiff 0.6 V
different ground pins (a) by diodes
Maximum input power LNA input Pmax 10 dBm
Maximum power dissipation PD250 mW
IC storage temperature TS-65 150 °C
Lead temperature solder, 10 sec. TLEAD 300 °C
(a). Under continous operation and during power-up sequences.
Handling
Every pin withstands the ESD test in accordance with MIL-STD-883 (method 3050) and IEC 68-2.
8
PBL 402 15
Parameter Condition Symbol Min. Typ. Max. Unit
Temperature range Fully compliant TAMB -20 70 °C
Operational -40 85
Supply voltage range Vcc 2.7 4.5 V
Shutdown supply current IOFF 2µA
Supply current One slot duplex communication IACTIVE 6 mA
Stand-by turn on time (a) τON 3µs
Receive turn on time (b) τRXON 3µs
Transmit turn on time (b) τTXON 3µs
a. Time may depend upon settling time of the limiting strip DC correction feedback.
b. Time for the receive or transmit gain to be within 1 dB of its final value.
Digital I/O Parameters
The digital output PA_GATE is served of the VCCRF/GndRF supply. All other digital signals are served of the VCCPLL/GndPLL
supply. The digital signals are EN, RXEN,TXEN, ST, D, CK, GATE, LD, MOD and SHOLD.
Parameter Condition Symbol Min. Typ. Max. Unit
Input voltage high VIH 2.1 V
Input voltage low VIL 0.6 V
Output voltage high VOH VCC-0.4 VCC-0.2 V
Output voltage low VOL 0.6 V
Digital input capacitance CDI 2pF
Digital input resistance RDI 100 kΩ
Digital load capacitance CDL 4pF
Digital load resistance RDL 30 kΩ
Operating conditions:
10 slots
17mA
57mA
19mA
51mA
t
Transmit, 1 slot
Receive, 1 slot
Setup to transmit, (blind slot) Setup to receive, (blind slot)
Typical current consumption
Tx Rx
Figure 7. Typical current consumtion.
9
PBL 402 15
The 3-Wire Control Bus Interface.
The 3-wire serial bus interface controls the various IC parameters and consists of 3 lines, strobe, data and clock ( ST, D, CK ).
Alternatively, selected power control modes may be controlled by 3 hard-wire control lines ( EN, RXEN, TXEN ).
The 3-wire bus is active when either EN or ST, or both are active. The strobe signal is used to enable the clock and latch the
data frame. Each frame consists of 24 bits, built from a word field and a data field. The word address is the last bit to be sent
( LSB ), with the data field being the proceeding 23 bits. Data on D is shifted into the frame register by clock CK.
The 3-wire interface allows setting of word A and word B. These control the IC configuration.
F0 W0
F1 D0
F2 D1
F3 D2
F4 D3
F5 D4
F6 D5
F7 D6
F8 D7
F9 D8
F10 D9
F11 D10
F12 D11
F13 D12
F14 D13
F15 D14
F16 D15
F17 D16
F18 D17
F19 D18
F20 D19
F21 D20
F22 D21
F23 D22
LSB
Last in
Word
Address
Data
MSB
First in
Frame:
Description
tag:
Frame definition:
ST Digital input The control section is powered up when ST is low. Data is latched on the rising edge.
ST has an internal 160kΩ pull up resistor to VCC PLL.
CK Digital input 3-wire interface clock. May be running continuously, but to minimise the risk of VCO spurious it is
recommended that the clock only runs when required.
D Digital input 3-wire interface data. Data latched by rising edge of CK.
EN Digital input IC enable control. Active low. The control section is powered when EN is active.
EN has an internal 160 kΩ pull up resistor to VCC PLL.
RXEN Digital input Receiver enable. Active low.
TXEN Digital input Transmitter enable. Active low.
Pin Spec. Description
Digital Interface:
Digital Interface:
Parameter Condition Symbol Min. Typ. Max. Unit
Serial clock frequency fCK 13.9 MHz
Delay strobe to first rising clock tSCK 288 ns
Data setup time: D to CK tDS 18 ns
Data hold time tDH 18 ns
Clock pulse widh high tCKW 18 ns
Strobe hold time high tSW 144 ns
10
PBL 402 15
t
DS
ST
D
CK
t
CKW
t
SCK
t
DS
t
SW
t
DH
Clock enabled
Clock disabled
LSBMSB
Figure 8. 3-wire timing diagram.
Word A.
Description.
Word A has the address W0 = 0. It permits IC operation and defines the synthesiser frequency.
IC operation is controlled by the EN pin and the CE flag. If EN is not active then CE must be enabled for the IC to become
and remain operational. If CE is disabled then the IC shuts down completely with only the status of ST and EN determining if the
control section takes power. All configurations are erased and must be re-programmed if the chip has been disabled.
CL determines if the internal flags or the hard wire control lines are used to control section power. The internal flags provide
more flexibility.
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PBL 402 15
Data address Name Default Description
D0 CE 0 0 = Chip disable
1 = Chip enable
Active low on the external EN pin will also enable the chip
D1 CL 0 0 = Internal control flags
1 = External control lines
D2 CNT_A0 0
D3 CNT_A1 0
D4 CNT_A2 0
D5 CNT_A3 0
D6 CNT_A4 0
D7 CNT_M 0 Synthesiser frequency counter M
0 → M = 32 (used for receive)
1 → M = 34 (used for transmit)
D8 CNT_R 0 Synthesiser reference counter R
0 → R = 6 used if REF = 10.368 MHz
1 → R = 8 used if REF = 13.824 MHz
D9 (a) 0
D10 (a) 0
D11 RXVCO_EN 0 (1)
D12 (a) 0
D13 (a) 0
D14 TXVCO_EN 0 (1)
D15 Reserved 0 (a)
D16 DRX_T 0 1 = Analog signal output at DRX pin.
0 = Digital data output at DRX pin.
D17 TX_P0 0
D18 TX_P1 0
D19 RX_G 0
D20 IFT0 1
D21 IFT1 1
D22 IFT2 0
Receiver VCO enable . 000 = VCO disabled.
Any other setting activates the VCO. (default 100)
Transmit power trim bits 00 = -1.3 dB Min.
0 (LSB) to 1 (MSB) 01 = Nominal power
10 = +1.3 dB
11 = +1.9 dB Max.
Synthesiser frequency counter A bit 0 (LSB) to 4 (MSB)
IRRX gain.
0 = +0dB extra
1 = +9dB extra
Demodulation IF frequency trim bits 0 (LSB) to 2 (MSB).
This should be programmed to the default settings.
a. Use ´0´ only.
b. Recommended at all times.
Word A Table.
Transmit VCO enable . 000 = VCO disabled.
Any other setting activates the VCO. (default 100)
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PBL 402 15
Word B.
Description.
Word B has address W0 =1. It controls modes, functionality and configuration. Word B signals are only active when CE is enabled
or EN is active.
Data address Name Default Description
D0 SYN_EN 0 1 = Synthesiser power on.
0 = Synthesiser power off.
D1 IF_EN 0 1 = IF receiver enabled. IF mixer + RSSI + Demodulator + Slave PLL
0 = IF receiver disabled.
D2 RX_EN 0 1 = Receiver power on. LNA + front end mixer
0 = Receiver power off.
D3 TX_EN 0 1 = Transmit power on.
0 = Transmit power off.
D4 SHOLD_P 0 1 = Slice hold pin SHOLD, active high.
0 = Slice hold pin SHOLD, active low.
D5 SHOLD_EN 0 1 = Slice hold enable.
0 = Slice hold disable.
Active level on the external SHOLD pin determined by SHOLD_P will
also enable slice hold.
D6 MOD_P 0 1 = Modulation pin MOD, active high.
0 = Modulation pin MOD, active low.
D7 MOD_EN 0 1 = Enable modulation.
0 = Disable modulation.
Active level on the external MOD pin determined by MOD_P will
also enable modulation.
D8 MOD_SW 0 1 = Modulation controlled by the SHOLD pin.
0 = Modulation controlled by the MOD pin.
The effect is to multiplex between the MOD & SHOLD pins.
D9 GATE_P 0 1 = TX gating pin, GATE active high.
0 = TX gating pin, GATE active low.
D10 CPC0 0 Charge pump operation control.
D11 CPC1 0 00 = Normal 01 = Force CP voltage down ( =VCO frequency up )
11 = Tri-state 10 = Force CP voltage up ( =VCO frequency down )
D12 to D23 Reserved. These bits need not to be programmed.
Word B Table.
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PBL 402 15
24 bit shift register
23 bit A-word latch
12 bit B-word latch
CE CL
EN
RXEN
TXEN
SYN_EN
IF_EN
RX_EN
TX_EN
ST
Data
CK
Synth. power on
IF power on
RX power on
TX power on
Synth. Nc
TXVCO power on
RXVCO power on
IF trim.
RX gain
TX power
DRX control
SYN_EN
IF_EN
RX_EN
TX_EN SHOLD_P
SHOLD_EN
MOD_P
MOD_EN
MOD_SW GATE_P
Charge pump control
RF enable
PA_GATE
GATE
PA-timing
control
MOD
Tristate CP
"hold" SLICE level
SHOLD
a).
b).
a). See figure PA_GATE timing diagram.
b). See figure SLICE control.
0
1
0
0
0
0
0
0
0
1
1
1
1
1
1
1
Digital interface power on
165k
165k
Figure 9. Control logic.
14
PBL 402 15
Hard Wire Control Lines.
The 3 hardwire control lines EN, RXEN and TXEN allow control of the IC by a controller with limited interface access or capabili-
ties. Typically, controllers with only one access per slot or no access between slots.
For correct operation the 3 hard wire lines require appropriate programming of the CE and CL flags.
The hardwire lines directly force the state of the appropriate word B flags as detailed below.
×2
ƒ-φ
PLL
Modulator
÷R
÷2
IF
LO and Modulation Section.
The LO section consists of a TX VCO with a frequency doubler, a RX VCO and a charge pump PLL.
The VCO´s are fully integrated and are phase/frequency locked to an external reference frequency applied to the REF pin. The
frequency is programmed by the 3-wire interface. Lock detect is available on the LD pin. When neither TX_EN or RX_EN are active,
lock detect is also available at the DRX output.
The RX VCO runs at twice the frequency. The frequency of the RX VCO is divided by 2 for the PLL. The TX VCO runs at half the
TX frequency to improve pulling immunity to TX harmonics. A frequency doubler generates the TX LO for the PLL.
The TX VCO is modulated by an external signal applied to the DTX pin. The DTX input is permanently connected to the TXVCO.
An active MOD_EN signal disables the PLL charge pump output which allows modulation to be applied. A hardware modulation
enable signal may be applied to either the MOD pin or SHOLD pin depending upon setting of the MOD_SW flag.
Hard wire line Description
EN Powers the serial bus interface.
Upon the rising edge of ST and provided CL is set to 1, the effect is as SYN_EN.
RXEN Provided EN is active and CL is set to 1, the effect is as IF_EN and RX_EN.
TXEN Provided EN is active and CL is set to 1, the effect is as TX_EN.
15
PBL 402 15
TX VCO.
A fully integrated balanced VCO. The VCO frequency is controlled by the voltage applied to the VTUNE pin, and the applied
modulation voltage. Both have a negative sensitivity, i.e., as the voltage increases, the VCO frequency decreases. The base-band
must invert the transit modulation data to allow for this. The tuning voltage is referenced to VCCVCO.
The VCO is buffered to provide isolation against frequency pulling and reverse injection.
TX VCO Table.
Typical TX VCO analog modulation voltage table.
Parameter Condition Symbol Min. Typ. Max. Unit
Carrier frequency range 0.4≤VT≤VCC-0.4 ƒC940 967 MHz
Tuning voltage VT0.4 VCC-0.4 V
Frequency tuning sensitivity ƒSEN ~-40 ~-72 ~-140 MHz/V
Frequency pulling stand-by ↔RX ƒPULL kHz
stand-by ↔TX
Frequency pushing against VCC, CPC = 2 ƒPUSH 1.5 MHz/V
Frequency drift per slot of 417 µsƒ
DRIFT 7.5 kHz
Modulation pushing modulation deviation against VCC ƒMPUSH kHz/V
Modulation tuning sensitivity modulation deviation against VTƒMSEN kHz/V
Analog modulation voltage (a) ± 144 kHz see table below VMOD ± 375 mVpk
(a). The input analog signal is expected to vary between 0V and 0.75V
Pre-modulation and post-modulation, it is expected to have a level of 0.375.
Channel No Supply voltage Condition Symbol -20°C20°C70°C Unit
0 VCC = 2.7 For ± 144 kHz VMOD27 239 ± 222 211 mVpk
31 223 ± 208 200
0V
CC = 3.3 For ± 144 kHz VMOD33 370 ± 339 320 mVpk
31 344 ± 315 299
0V
CC = 3.6 For ± 144 kHz VMOD36 460 ± 419 395 mVpk
31 426 ± 390 369
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PBL 402 15
RX VCO Table.
The PLL.
N/N+1
ƒ-φ
R
M
A
Store
REF
LO
CP
÷2
÷2
LD LD &
DRX
864kHz
The frequency synthesiser is based on a charge pump PLL ( Phase Locked Loop ).
Counter R divides the reference clock, REF. The division ratio, R, is determined by the value of CNT_R. Counters N, A and M form a
modulus pulse swallow counter which divides the LO clock by M∗N+A . The value of M is determined by CNT_M. The value of A is
taken from the CNT_A.
A combined 3 state frequency-phase detector compares the divided REF and LO signals and controls the charge pump.The
frequency-phase comparator outputs are controlled by the CPC1-0 bits and MOD_EN. The action of the CPC bits are unsynchronised.
The action of MOD_EN is synchronised to the charge pump states, holding the charge pump in tri-state mode when MOD becomes
active.
An active high lock detect signal is provided when frequency lock has been achieved for 148 µs. The signal is available on the LD
pin and on the DRX pin when SYN_EN is active and neither of RX_EN or TX_EN are active.
The PLL is designed to work with two different reference frequencies, 10.368 MHz ( = 9 x the DECT bitrate of 1.152 MHz ) or
13.824 MHz ( = 12 x the DECT bitrate of 1.152 MHz )
RX VCO.
A fully integrated balanced VCO. The VCO frequency is controlled by the voltage applied to the VTUNE pin, and has a
negative sensitivity, i.e., as the voltage increases, the VCO frequency decreases. The tuning voltage is referenced to VCCVCO.
The VCO is buffered to provide isolation against frequency pulling and reverse injection.
A divider by 2 stage, reduces the VCO frequency by 2 for the PLL.
Parameter Condition Symbol Min. Typ. Max. Unit
Carrier frequency range 0.4≤VT≤VCC-0.4 ƒC3.53 3.65 GHz
Tuning voltage VT0.4 VCC-0.4 V
Frequency sensitivity ƒSEN ~-100 ~-280 ~-460 MHz/V
Frequency pulling stand-by ↔RX ƒPULL kHz
stand-by ↔TX
Frequency pushing against VCC , CPC = 2 ƒPUSH 1,0 MHz/V
Noise floor nominal output power NFLR -140 dBc/Hz
17
PBL 402 15
The synthesiser frequency is given by, fRF = (fREF / R) (M * N+A)
where: fRF = RF frequency
fREF = either 10.368 MHz or 13.824 MHz
R = 6 or 8 (see CNT_R)
M = 32 or 34 (see CNT_M)
N = 32
A = 0, 1, ......,31
PLL Table.
Transmit section.
TX
GATE
Description.
The transmitter consists of a band-pass filter, a gated amplifier and a pre-power amplifier. The band-pass filter cleans the
output signal of the LO modulator prior to amplification.
The gated amplifier is controlled by the GATE pin, with signal polarity determined by the GATE_P flag. The attenuation of the
gating amplifier should be used in addition to the external PA to meet the transmit power ramp requirements. An active GATE
signal causes the output power to ramp up to its required power level. An inactive GATE signal causes the output power to ramp
down to a leakage level. Spectral spreading requirements are best met if the external PA turns on before the power ramp up, and
turn off after the power ramp down. Should the external PA be controlled by the same GATE signal, a delayed copy of the GATE
signal is provided at the PA _GATE output.
The TX output is balanced with an impedance of ~100 Ω and requires external inductors to VCCRF. The transmit power may be
trimmed by the TX_P 0-1 bits.
The TX is designed for easy interfacing to the PBL 403 09 DECT PA circuit, which is enabled with an active low signal. See
application diagram for details.
Parameter Condition Symbol Min. Typ. Max. Unit
Carrier frequency range 0.4≤VT≤VCC-0.4 ƒC1769 1934 MHz
Lock time (1) tLOCK 320 µs
Charge pump current ICP 400 µA
Charge pump leakage tri-state ILEAK 100 pA
Reference frequency CNT_R=0 ƒREF 10.368 MHz
CNT_R=1 13.824
Reference input voltage VREF 50 mVpk
(1). Depends upon charge pump loop components.
18
PBL 402 15
Transmit section Table.
t
PAOFF
PA_GATE (active low)
t
PAON
GATE (active low)
2µs2µs
RF signal at TX
∼
∼
Parameter Condition Symbol Min. Typ. Max. Unit
Frequency range at output ƒ 1800 2000 MHz
Nominal output power Gate enable PNOM 5 dBm
Output power Gate disable POFF -22 dBc
Power of 2xLO spurious P2LO -35 -20 dBc
Power of 3xLO spurious P3LO -35 -20 dBc
TX_P1, 0=0, 0 PTRIM -1.3 dB
Output power trim about nominal TX_P1, 0=0, 1 0
TX_P1, 0=1, 0 +1.3
TX_P1, 0=1, 1 +1.9
POFF to PNOM time tON 25µs
PNOM to POFF time tOFF 25µs
Gate active to PA_GATE active tPAON 100 200 ns
Gate inactive to PA_GATE inactive tPAOFF 36µs
Noise floor nominal output power NFLR -135 dBm/Hz
Noise at channel M±1ƒ±1.728 MHz NM1 -93 dBc
Noise at channel M±2ƒ±3.456 MHz NM2 -115 dBc
Noise at channel M±3ƒ±5.184 MHz NM3 -129 dBc
Noise at channel M±4ƒ±6.912 MHz NM4 -132 dBc
Output impedance ZOUT 100 Ω
Output VSWR VSWRO1.5:1 -
Figure 10. GATE / PA_GATE timing diagram, GATE_P = 0.
19
PBL 402 15
Image Reject Front End Table.
The IF outputs are self biasing and define a balanced output impedance of 300 Ω. The output should be matched to an
external adjacent channel filter.
The gain is switchable to cater for the insertion loss of different external filters.
Image Reject Front End.
÷2
-π/4π/4
IR RX
The image reject front end consists of an LNA (Low Noise Amplifier) with dual outputs, 2 mixers, quadrature LO generation, 2
low pass filters, a +π/4 and a -π/4 all-pass filters and a summing output stage.
The receiver input is a 1.9 GHz LNA with a characteristic balanced input impedance. The inputs are self biassing and require
external matching to the source, with DC blocking capacitors if the source passes DC.
The high side image rejection mixer, down converts from RF to an IF frequency of 110.6 MHz.
Parameter Condition Symbol Min. Typ. Max. Unit
Input frequency range ƒIN 1800 1890 2000 MHz
Output frequency range ƒOUT 100 110.6 120 MHz
Gain 1 RX_G = 0 G1 18 20 22 dB
Gain 2 RX_G = 1 G2 23 25 27 dB
Input IP3 RX_G = 0 IP3 -21 -17 dBm
RX_G = 1 -23
Input 1 dB compression RX_G = 0 CPI1 -24 dBm
RX_G = 1 -31
Output 1 dB compression CPO1 -7 dBm
Output saturation -1.5 dBm
Lower image suppression Tested at ƒIN -2•110.6 MHz SSB 29 35 dB
Noise figure NF 3.6 4.1 dB
Input impedance ZIN 100 Ω
Output impedance ZOUT 300 Ω
Input VSWR VSWRI1.5:1 -
Output VSWR VSWRO1.5:1 -
20
PBL 402 15
IF ReceiverTable.
IF Receiver.
The IF receiver consists of an upper sideband image reject down converter, a channel blocking filter, a limiting amplifier and
RSSI, an FM discriminator, a post detection filter and a data slicer.
The IF inputs are self biasing and have a balanced input impedance of 300 Ω. Matching to the external filter is required.
A band-pass filter provides additional channel selection and noise filtering prior to the limiting chain.
The quadrature based FM discriminator and post detection filter are self tuned to the required frequency by a slave PLL.
The FSK data is recovered by a threshold based data slicer. The slice level is determined up to the end of the 16 bit packet
preamble, where it should be held by an active SHOLD signal provided from the base-band controller. The slice controller determines
a more accurate level from this signal. An external capacitor is required on the DSL pin.
Parameter Condition Symbol Min. Typ. Max. Unit
Frequency range ƒIF 110.6 MHz
Input IP3 IP3 -13 dBm
Input 1dB compression CP1 -15 -13 dBm
Lower image suppression Tested at ƒIF -23.5 MHz SSB 29 dB
Noise figure Referenced to 300 ΩNF 14 dB
Sensitivity BER = 10-3 SENS -79 dBm
Input impedance ZIN 300 Ω
Input VSWR VSWRI1.5:1 -
Attenuation of channel M±1>ƒC ± 1.152 MHz ATT1
Attenuation of channel M±2>ƒC ± 2.88 MHz ATT2
Attenuation of channel M±3>ƒC ± 4.608 MHz ATT3
Attenuation of channel M±4>ƒC ± 6.336 MHz ATT4
Group delay deviation ƒC ± 576 kHz GDD 0.3 µs
Slice hold capacitor On DSL pin to Gnd CDSL 2nF
DSL
R
+
-
R = 2k R = 4k R = 200k
SHOLD activated
12 x bit time @ (∼10.4µs)
When the IF section is powered off, the DSL pin is tri-stated.
PLL
0
1
DRX
0
1
Demodulator
Synth. power on
Tx power on
Rx power on
LD
C
DSL
DRX_T
Figure 11. Slice control.
21
PBL 402 15
Limiting Amplifier and RSSI ( Received Signal Strength Indicator ).
The stage consists of a limiting amplifier chain with an RSSI detector. The inputs are internally coupled from the channel
selection filter which limits the noise bandwidth. A balanced DC offset correction loop, provides maximum sensitivity, and
ensures a short settling time upon power up.
An RSSI output provides a voltage proportional to the logarithm of the rectified input level. The rise time response of the
RSSI output and the peak hold is dependent upon the external circuit.
Limiting Amplifier strip and RSSI, Table.
Parameter Condition Symbol Min. Typ. Max. Unit
Frequency range ƒ 11.7 MHz
Limiter 1 dB bandwidth ƒ1dB 22 MHz
Voltage gain G 74 dB
RSSI range RR74 dB
RSSI minimum detection level measured at IFIN RDMIN -83 dBm
RSSI maximum detection level measured at IFIN RDMAX -9 dBm
RSSI slope RSLOPE 15.2 mV/dB
Zero scale RSSI output voltage VRZERO 375 mVpk
Full scale RSSI output voltage VRFULL 1500 mVpk
RSSI relative error best fit to straight line (a) RERR ±2.5 dB
RSSI rise time 20 pF load tRISE 2µs
Feedback capacitance CCAP 18 nF
a. The RSSI relative accuracy is the deviation of the RSSI value from a best fit straight line fitted to several calibration points.
These points are determined for each part.
22
PBL 402 15
Specifications subject to change without
notice.
1522-PBL 402 15 Uen Rev.A
© Ericsson Microelectronics AB
January 2001
Information given in this data sheet is believed to be accurate and reliable. However no responsibility is assumed
for the consequences of its use nor for any infringement of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Ericsson
Microelectronics AB. These products are sold only according to Ericsson Microelectronics AB's general conditions
of sale, unless otherwise confirmed in writing.
Ericsson Microelectronics AB
S-164 81 Kista-Stockholm, Sweden
Telephone: (08) 757 50 00
www.ericsson.se/microe
DIM. mm inch
MIN. TYP. MAX. MIN. TYP. MAX.
A 1.60 0.063
A1 0.05 0.15 0.002 0.006
A2 1.35 1.40 1.45 0.053 0.055 0.057
B 0.17 0.22 0.27 0.006 0.008 0.010
C 0.09 0.20 0.004 0.008
D 9.00 0.354
D1 7.00 0.276
D3 5.50 0.217
e 0.50 0.020
E 9.00 0.354
E1 7.00 0.276
E3 5.50 0.217
L 0.45 0.60 0.75 0.018 0.024 0.030
L1 1.00 0.039
K0∞(min.), 3.5°(typ.), 7∞(max.)
TQFP 48 Pin Package
