K6T4008V2C-ZF70 - Samsung - Datasheet.Directory

K6T4008V2C, K6T4008U2C Family CMOS SRAM

Revision 1.0

April 1999

Document Title

512Kx8 bit Low Power and Low Voltage CMOS Static RAM

Revision History

Revision No.

0.0

1.0

Remark

Preliminary

Final

History

Initial Draft

Finalize

Draft Data

December 3, 1998

April 28, 1999

The attached datasheets are provided by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications.

SAMSUNG Electronics will answer to your questions about device. If you have any questions, please contact the SAMSUNG branch office.

K6T4008V2C, K6T4008U2C Family CMOS SRAM

Revision 1.0

April 1999

512K×8 bit Low Power and Low Voltage CMOS Static RAM

GENERAL DESCRIPTION

The K6T4008V2C and K6T4008U2C families are fabricated by

SAMSUNG′s advanced CMOS process technology. The fami-

lies support industrial operating temperature range and have

chip scale package type for user flexibility of system design.

The families also support low data retention voltage for battery

back-up operation with low data retention current.

FEATURES

• Process Technology: TFT

• Organization: 512K×8

• Power Supply Voltage

K6T4008V2C Family: 3.0~3.6V

K6T4008U2C Family: 2.7~3.3V

• Low Data Retention Voltage: 2V(Min)

• Three state output and TTL Compatible

• Package Type: 48(36)-uBGA-6.10x8.90

PIN DESCRIPTION

PRODUCT FAMILY

1. The paramerter is measured with 30pF test load.

Product Family Operating Temperature Vcc Range Speed Power Dissipation PKG Type

Standby

(ISB1, Max) Operating

(ICC2, Max)

K6T4008V2C-F Industrial(-40~85°C) 3.0~3.6V 701)/85ns 20µA30mA 48(36)-uBGA

K6T4008U2C-F 2.7~3.3V 701)/85/100ns

FUNCTIONAL BLOCK DIAGRAM

SAMSUNG ELECTRONICS CO., LTD. reserves the right to change products and specifications without notice.

Precharge circuit.

Memory array

1024 rows

512×8 columns

I/O Circuit

Column select

Clk gen.

Row

select

I/O1Data

cont

Data

cont

I/O8

Control

logic

Name Function Name Function

CS1, CS2 Chip Select Inputs I/O1~I/O8Data Inputs/Outputs

WE Write Enable Input Vcc Power

OE Output Enable Input Vss Ground

A0~A18 Address Inputs NC No Connection

CS1

A0 A1 CS2 A3 A6 A8

I/O5 A2 WE A4 A7 I/O1

I/O6 NC A5 I/O2

Vss Vcc

Vcc Vss

I/O7 A18 A17 I/O3

I/O8 OE CS1A16 A15 I/O4

A9 A10 A11 A12 A13 A14

1 23456

48(36)-uBGA

CS2

Top View (Ball Down)

K6T4008V2C, K6T4008U2C Family CMOS SRAM

Revision 1.0

April 1999

PRODUCT LIST

Industrial Temp Products(-40~85°C)

Part Name Function

K6T4008V2C-ZF70

K6T4008V2C-ZF85

K6T4008U2C-ZF70

K6T4008U2C-ZF85

K6T4008U2C-ZF10

48-uBGA, 70ns, 3.3V, LL

48-uBGA, 85ns, 3.3V, LL

48-uBGA, 70ns, 3.0V, LL

48-uBGA, 85ns, 3.0V, LL

48-uBGA, 100ns, 3.0V, LL

FUNCTIONAL DESCRIPTION

1. X means don′t care (Must be in low or high state)

CS1CS2OE WE I/O Mode Power

HX1) X1) X1) High-Z Deselected Standby

X1) LX1) X1) High-Z Deselected Standby

LHHHHigh-Z Output Disabled Active

LHLHDout Read Active

LHX1) LDin Write Active

ABSOLUTE MAXIMUM RATINGS1)

1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Functional operation should be

restricted to recommended operating condition. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

Item Symbol Ratings Unit Remark

Voltage on any pin relative to Vss VIN,VOUT -0.5 to VCC+0.5 V-

Voltage on Vcc supply relative to Vss VCC -0.3 to 4.6 V-

Power Dissipation PD1.0 W-

Storage temperature TSTG -65 to 150 °C-

Operating Temperature TA-40 to 85 °CK6T4008V2C-P, K6T4008U2C-P

K6T4008V2C, K6T4008U2C Family CMOS SRAM

Revision 1.0

April 1999

RECOMMENDED DC OPERATING CONDITIONS1)

Note:

1. Industrial Product: TA=-40 to 85°C, otherwise specified

2. Overshoot: VCC+2.0V in case of pulse width ≤ 30ns

3. Undershoot: -2.0V in case of pulse width ≤ 30ns

4. Overshoot and undershoot are sampled, not 100% tested.

Item Symbol Product Min Typ Max Unit

Supply voltage Vcc K6T4008V2C Family

K6T4008U2C Family 3.0

2.7 3.3

3.0 3.6

3.3 V

Ground Vss All Family 0 0 0 V

Input high voltage VIH K6T4008V2C, K6T4008U2C Family 2.2 -Vcc+0.32) V

Input low voltage VIL K6T4008V2C, K6T4008U2C Family -0.33) -0.6 V

CAPACITANCE1) (f=1MHz, TA=25°C)

1. Capacitance is sampled, not 100% tested

Item Symbol Test Condition Min Max Unit

Input capacitance CIN VIN=0V -8pF

Input/Output capacitance CIO VIO=0V -10 pF

DC AND OPERATING CHARACTERISTICS

Item Symbol Test Conditions Min Typ Max Unit

Input leakage current ILI VIN=Vss to Vcc -1 -1µA

Output leakage current ILO CS1=VIH or CS2=VIL or OE=VIH or WE=VIL VIO=Vss to Vcc -1 -1µA

Operating power supply current ICC IIO=0mA, CS1=VIL, CS2=VIH, WE=VIH, VIN=VIL or VIH - - 4mA

Average operating current ICC1 Cycle time=1µs, 100% duty, IIO=0mA

CS1≤0.2V, CS2≥Vcc-0.2V, VIN≤0.2V or VIN≥Vcc-0.2V - - 4mA

ICC2 Cycle time=Min, 100% duty, IIO=0mA, CS1=VIL, CS2=VIH, VIN=VIH or VIL - - 30 mA

Output low voltage VOL IOL=2.1mA - - 0.4 V

Output high voltage VOH IOH=-1.0mA 2.2 - - V

Standby Current(TTL) ISB CS1=VIH, CS2=VIL, Other inputs = VIL or VIH - - 0.3 mA

Standby Current (CMOS) ISB1 CS1≥Vcc-0.2V, CS2≥Vcc-0.2V or CS2≤0.2V, Other inputs=0~Vcc - - 20 µA

K6T4008V2C, K6T4008U2C Family CMOS SRAM

Revision 1.0

April 1999

AC CHARACTERISTICS (TA=-40 to 85°C, K6T4008V2C Family: 3.0~3.6V, K6T4008U2C Family: 2.7~3.3V)

Parameter List Symbol

Speed Bins

Units

70ns 85ns 100ns

Min Max Min Max Min Max

Read

Read cycle time tRC 70 -85 -100 -ns

Address access time tAA -70 -85 -100 ns

Chip select to output tCO1, tCO2 -70 -85 -100 ns

Output enable to valid output tOE -35 -40 -50 ns

Chip select to low-Z output tLZ 10 -10 -10 -ns

Output enable to low-Z output tOLZ 5-5-5-ns

Chip disable to high-Z output tHZ 025 025 030 ns

Output disable to high-Z output tOHZ 025 025 030 ns

Output hold from address change tOH 10 -10 -15 -ns

Write

Write cycle time tWC 70 -85 -100 -ns

Chip select to end of write tCW 60 -70 -80 -ns

Address set-up time tAS 0-0-0-ns

Address valid to end of write tAW 60 -70 -80 -ns

Write pulse width tWP 55 -55 -70 -ns

Write recovery time tWR 0-0-0-ns

Write to output high-Z tWHZ 025 025 030 ns

Data to write time overlap tDW 30 -35 -40 -ns

Data hold from write time tDH 0-0-0-ns

End write to output low-Z tOW 5-5-5-ns

CL1)

1. Including scope and jig capacitance

AC OPERATING CONDITIONS

TEST CONDITIONS(Test Load and Input/Output Reference)

Input pulse level : 0.4 to 2.2V

Input rising and falling time : 5ns

Input and output reference voltage :1.5V

Output load(see right) : CL=100pF+1TTL

CL1)=30pF+1TTL

1. 70ns products

DATA RETENTION CHARACTERISTICS

1. CS1≥Vcc-0.2V, CS2≥Vcc-0.2V(CS1 controlled) or CS2≤0.2V(CS2 controlled)

Item Symbol Test Condition Min Typ Max Unit

Vcc for data retention VDR CS1≥Vcc-0.2V1) 2.0 -3.6 V

Data retention current IDR Vcc=3.0V, CS1≥Vcc-0.2V1) -0.5 20 µA

Data retention set-up time tSDR See data retention waveform 0- - ms

Recovery time tRDR 5- -

K6T4008V2C, K6T4008U2C Family CMOS SRAM

Revision 1.0

April 1999

Address

Data Out Previous Data Valid Data Valid

TIMMING DIAGRAMS

TIMING WAVEFORM OF READ CYCLE(1) (Address Controlled, CS1=OE=VIL, CS2=WE=VIH)

tAA

tRC

tOH

TIMING WAVEFORM OF READ CYCLE(2) (WE=VIH)

Data Valid

High-Z

CS1

Address

Data out

NOTES (READ CYCLE)

1. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage

levels.

2. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device to device

interconnection.

CS2

tOH

tAA

tOLZ

tLZ tOHZ

tHZ(1,2)

tRC

tCO2tOE

tCO1

K6T4008V2C, K6T4008U2C Family CMOS SRAM

Revision 1.0

April 1999

TIMING WAVEFORM OF WRITE CYCLE(1) (WE Controlled)

Address

CS1

tCW(2) tWR(4)

TIMING WAVEFORM OF WRITE CYCLE(2) (CS1 Controlled)

Address

CS1

tWC

tWR(4)

tAS(3)

CS2tCW(2)

tWP(1)

tDW tDH

tOW

tWHZ

Data Undefined

Data Valid

Data in

Data out

tDW tDH

Data Valid

Data in

Data out High-Z High-Z

CS2

tWC

tAW

tAS(3)

tCW(2)

tWP(1)

tAW

K6T4008V2C, K6T4008U2C Family CMOS SRAM

Revision 1.0

April 1999

DATA RETENTION WAVE FORM

CS1 controlled

VCC

3.0/2.7V

2.2V

VDR

CS1

GND

Data Retention Mode

CS1≥VCC - 0.2V

tSDR tRDR

TIMING WAVEFORM OF WRITE CYCLE(3) (CS2 Controlled)

Address

CS1

tAW

NOTES (WRITE CYCLE)

1. A write occurs during the overlap of a low CS1, a high CS2 and a low WE. A write begins at the latest transition among CS1 goes low,

CS2 going high and WE going low : A write end at the earliest transition among CS1 going high, CS2 going low and WE going high,

tWP is measured from the begining of write to the end of write.

2. tCW is measured from the CS1 going low or CS2 going high to the end of write.

3. tAS is measured from the address valid to the beginning of write.

4. tWR is measured from the end of write to the address change. tWR1 applied in case a write ends as CS1 or WE going high tWR2 applied

in case a write ends as CS2 going to low.

CS2

tCW(2)

Data in Data Valid

Data out High-Z High-Z

tCW(2) tWR(4)

tWP(1)

tDW tDH

tAS(3)

tWC

CS2 controlled

VCC

3.0/2.7V

0.4V

VDR

CS2

GND

Data Retention Mode

tSDR tRDR

CS2≤0.2V

K6T4008V2C, K6T4008U2C Family CMOS SRAM

Revision 1.0

April 1999

654321

C/2

B/2

Ball #A1

B/2

Elastomer

SRAM Die

Ball #A1

C/2

Bottom ViewTop View

Detail A

Side View

0.68/Typ.

0.45/Typ. 0.25/Typ.

Elastomer

0.3/Typ.

Die

Detail A

Notes.

1. Bump counts : 48(8row x 6column)

2. Bump pitch : (x,y)=(0.75 x 0.75)(typ.)

3. All tolerence are +/-0.050 unless

otherwise specified.

4. Typ : Typical

5. Y is coplanarity: 0.08(Max)

Min Typ Max

A-0.75 -

B6.00 6.10 6.20

B1 -3.75 -

C8.80 8.90 9.00

C1 -5.25 -

D0.30 0.35 0.40

E-0.93 0.94

E1 -0.68 -

E2 -0.25 -

Y- - 0.08

PACKAGE DIMENSIONS Units: millimeters

48 BALL MICRO BALL GRID ARRAY- 0.75mm ball pitch