1
FEATURES APPLICATIONS
24
23
22
21
20
19
18
17
16
15
14
13
1
2
3
4
5
6
7
8
9
10
11
12
TPS2223A, TPS2224A
DB OR PWP PACKAGE
(TOP VIEW)
5V
5V
DATA
CLOCK
LATCH
NC
12V†
AVPP
AVCC
AVCC
GND
RESET
5V
NC
NC
SHDN
12V†
BVPP
BVCC
BVCC
NC
OC
3.3V
3.3V
NC − No internal connection
†Pin 7 and 20 are NC for TPS2223A.
DESCRIPTION
TPS2220A , TPS2223ATPS2224A , TPS2226A
SLVS428E – MAY 2002 – REVISED MSRCH 2008www.ti.com
CARDBUS POWER-INTERFACE SWITCHESFOR SERIAL PCMCIA CONTROLLERS
•Notebook and Desktop Computers234
•Provides S-CARD and M-CARD PowerManagement for CableCARD™ Applications
•Bar Code Scanners•Digital Cameras•Single-Slot Switch: TPS2220ADual-Slot Switches: TPS2223A, TPS2224A,
•Set-Top BoxesTPS2226A
•PDAs•Fast Current Limit Response Time•Fully Integrated VCC and VPP Switching for3.3 V, 5 V, and 12 V (no 12 V on TPS2223A)•Meets Current PC Card™ Standards•V
pp
Output Selection Independent of V
CC•12-V and 5-V Supplies Can Be Disabled•TTL-Logic Compatible Inputs•Short-Circuit and Thermal Protection•24-Pin HTSSOP, 24- or 30-Pin SSOP•140- µA (Typical) Quiescent Current from3.3-V Input•Break-Before-Make Switching•Power-On Reset•– 40 °C to 85 °C Operating Ambient TemperatureRange
The TPS2223A, TPS2224A, and TPS2226A CardBus™ power-interface switches provide an integratedpower-management solution for two PC Card sockets. The TPS2220A is a single-slot option for this family ofdevices. These devices allow the controlled distribution of 3.3 V, 5 V, and 12 V to each card slot. Thecurrent-limiting and thermal-protection features eliminate the need for fuses. Current-limit reporting helps the userisolate a system fault. The switch r
DS(on)
and current-limit values have been set for the peak and average currentrequirements stated in the PC Card specification, and optimized for cost. A faster maximum current limitresponse time is the only difference between the TPS2223A, TPS2224A, and TPS2226A and the TPS2223,TPS2224, and TPS2226.
Like the TPS2214 and TPS2214A and the TPS2216 and TPS2216A, this family of devices supports independentVPP/VCC switching; however, the standby and interface-mode pins are not supported. Shutdown mode is nowsupported independently on SHDN as well as in the serial interface. Optimized for lower power implementation,the TPS2223A does not support 12-V switching to VPP. For the most current package and ordering information,see the Package Option Addendum at the end of this document, or see the TI website at www.ti.com .
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications ofTexas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2CableCARD is a trademark of Cable Tevelision Laboratories, Inc..3PC Card, CardBus are trademarks of PCMCIA (Personal Computer Memory Card International Association).4All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Copyright © 2002 – 2008, Texas Instruments IncorporatedProducts conform to specifications per the terms of the TexasInstruments standard warranty. Production processing does notnecessarily include testing of all parameters.
www.ti.com
ABSOLUTE MAXIMUM RATINGS
DISSIPATION RATING TABLE
RECOMMENDED OPERATING CONDITIONS
TPS2220A , TPS2223ATPS2224A , TPS2226A
SLVS428E – MAY 2002 – REVISED MSRCH 2008
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foamduring storage or handling to prevent electrostatic damage to the MOS gates.
over operating free-air temperature range (unless otherwise noted)
(1)
TPA222xA UNIT
V
I(3.3V)
– 0.3 to 5.5 VV
I
Input voltage range for card power V
I(5V)
– 0.3 to 5.5 VV
I(12V)
(2)
– 0.3 to 14 VLogic input/output voltage – 0.3 to 6 VV
O(xVCC)
– 0.3 to 6 VV
O
Output voltage
V
O(xVPP)
– 0.3 to 14 VContinuous total power dissipation See Dissipation Rating TableI
O(xVCC)
Internally LimitedI
O
Output current
I
O(xVPP)
Internally LimitedT
J
Operating virtual junction temperature range – 40 to 100 °CT
stg
Storage temperature range – 55 to 150 °COC sink current 10 mA
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratingsonly, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operatingconditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.(2) Not applicable for TPS2223A
T
A
≤25 °C DERATING FACTOR T
A
= 70 °C T
A
= 85 °CPACKAGE
(1)
POWER RATING ABOVE T
A
= 25 °C POWER RATING POWER RATING
24 890 mW 8.9 mW/ °C 489 mW 356 mWDB
30 1095 mW 10.95 mW/ °C 602 mW 438 mWPWP 24 3322 mW 33.22 mW/ °C 1827 mW 1329 mW
(1) These devices are mounted on an JEDEC low-k board (2-oz. traces on surface).
MIN MAX UNIT
V
I(3.3V)
(1)
3 3.6Input voltage, V
I(3.3V)
is required for all circuitoperations. 5V and 12V are only required for V
I(5V)
3 5.5 Vtheir respective functions.
V
I(12V)
(2)
7 13.5I
O(xVCC)
at T
J
= 100 °C 1 AI
O
Output current
I
O(xVPP)
at T
J
= 100 °C 100 mAf
(clock)
Clock frequency 2.5 MHzData 200Latch 250t
w
Pulse duration nsClock 100Reset 100t
h
Data-to-clock hold time (see Figure 2 ) 100 nst
su
Data-to-clock setup time (see Figure 2 ) 100 nst
d(latch)
Latch delay time (see Figure 2 ) 100 nst
d(clock)
Clock delay time (see Figure 2 ) 250 ns
(1) It is understood that for V
I(3.3V)
< 3 V, voltages within the absolute maximum ratings applied to pin 5V or pin 12V do not damage the IC.(2) Not applicable for TPS2223A
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Product Folder Link(s): TPS2220A TPS2223A TPS2224A TPS2226A
www.ti.com
ELECTRICAL CHARACTERISTICS
TPS2220A , TPS2223ATPS2224A , TPS2226A
SLVS428E – MAY 2002 – REVISED MSRCH 2008
RECOMMENDED OPERATING CONDITIONS (continued)
MIN MAX UNIT
Operating virtual junction temperature (maximum to be calculated at worst case P
D
at 85 °CT
J
– 40 100 °Cambient)
T
J
= 25 °C, V
I(5V)
= 5 V, V
I(3.3V)
= 3.3 V, V
I(12V)
= 12 V (not applicable for TPS2223A), all outputs unloaded (unless otherwisenoted)
PARAMETER TEST CONDITIONS
(1)
MIN TYP MAX UNIT
POWER SWITCH
I
O
= 750 mA each 85 1103.3V to xVCC
(2)
I
O
= 750 mA each, T
J
= 100 °C 110 140
mΩI
O
= 500 mA each 95 1305V to xVCC
(2)
I
O
= 500 mA each, T
J
= 100 °C 120 160Static drain-sourcer
DS(on)
on-state resistance
I
O
= 50 mA each 0.8 13.3V or 5V to xVPP
(2)
I
O
= 50 mA each, T
J
= 100 °C 1 1.3
ΩI
O
= 50 mA each 2 2.512V to xVPP
(2)
I
O
= 50 mA each, T
J
= 100 °C 2.5 3.4
Discharge at xVCC I
O(disc)
= 1 mA 0.5 0.7 1Output discharge
kΩresistance
Discharge at xVPP I
O(disc)
= 1 mA 0.2 0.4 0.5
I
OS(xVCC)
1 1.4 2 ALimit (steady-state value), outputpowered into a short circuit
I
OS(xVPP)
120 200 300 mAI
OS
Short-circuit output current
Limit (steady-state value), output I
OS(xVCC)
1 1.4 2 Apowered into a short circuit,
I
OS(xVPP)
120 200 300 mAT
J
= 100 °C
Thermal trip point Rising temperature 135Thermal shutdownT
J
°Ctemperature
(2)
Hysteresis 10
5V to xVCC = 5 V, with 100-m Ωshort to GND 10Current-limit response time
(3) (4)
µs5V to xVPP = 5 V, with 100-m Ωshort to GND 3
I
I(3.3V)
140 200Normal V
O
(xVCC) = V
O
(xVPP) = 3.3 V andI
I(5V)
8 12operation also for RESET = 0 VI
I(12V)
100 180I
I
Input current, quiescent µAI
I(3.3V)
0.3 2
Shutdown mode I
I(5V)
V
O
(xVCC) = V
O
(xVPP) = Hi-z 0.1 2
I
I(12V)
0.3 2
10V
O(xVCC)
= 5 V, V
I(5V)
= V
I(12V)
= 0 V
T
J
= 100 °C 50Leakage current,I
lkg
Shutdown mode µAoutput off state
10V
O(xVPP)
= 12 V, V
I(5V)
= V
I(12V)
= 0 V
T
J
= 100 °C 50
(1) Pulse-testing techniques maintain junction temperature close to ambient temperature; thermal effects must be taken into accountseparately.
(2) TPS2223A, TPS2224A, TPS2226A: two switches on. TPS2220A: one switch on.(3) Specified by design; not tested in production.(4) From application of short to 110% of final current limit.
Copyright © 2002 – 2008, Texas Instruments Incorporated Submit Documentation Feedback 3
Product Folder Link(s): TPS2220A TPS2223A TPS2224A TPS2226A
www.ti.com
TPS2220A , TPS2223ATPS2224A , TPS2226A
SLVS428E – MAY 2002 – REVISED MSRCH 2008
ELECTRICAL CHARACTERISTICS (continued)T
J
= 25 °C, V
I(5V)
= 5 V, V
I(3.3V)
= 3.3 V, V
I(12V)
= 12 V (not applicable for TPS2223A), all outputs unloaded (unless otherwisenoted)
PARAMETER TEST CONDITIONS
(1)
MIN TYP MAX UNIT
LOGIC SECTION (CLOCK, DATA, LATCH, RESET, SHDN, OC)
RESET = 5.5 V -1 1I
I(/RESET)
(5)
RESET = 0 V -30 -20 -10
SHDN = 5.5 V -1 1I
I(/SHDN)
(5)I
I
Input current, logic SHDN = 0 V -50 -3 µA
LATCH = 5.5 V 50I
I(LATCH)
(5)
LATCH = 0 V -1 1
I
I(CLOCK, DATA)
0 V to 5.5 V -1 1
V
IH
High-level input voltage, logic 2 V
V
IL
Low-level input voltage, logic 0.8 V
V
O(sat)
Output saturation voltage at OC I
O
= 2 mA 0.14 0.4 V
I
lkg
Leakage current at OC V
O(/OC)
= 5.5 V 0 1 µA
UVLO AND POR (POWER-ON RESET)
V
I(3.3V)
Input voltage at 3.3V pin, UVLO 3.3-V level below which all switches are Hi-Z 2.4 2.7 2.9 V
V
hys(3.3V)
UVLO hysteresis voltage at VA
(6)
100 mV
V
I(5V)
Input voltage at 5V pin, UVLO 5-V level below which only 5V switches are Hi-Z 2.3 2.5 2.8 V
Delay from voltage hit (step from 3 V to 2.3 V) toV
hys(5V)
UVLO hysteresis voltage at 5V
(6)
100 mVHi-Z control (90% V
G
to GND)
t
df
Delay time for falling response, UVLO
(6)
4µs
3.3-V voltage below which POR is asserted causing aV
I(POR)
Input voltage, power-on reset
(6)
RESET internally with all line switches open and all 1.7 Vdischarge switches closed.
(5) LATCH has low-current pulldown. RESET and SHDN have low-current pullup.(6) Specified by design; not tested in production.
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Product Folder Link(s): TPS2220A TPS2223A TPS2224A TPS2226A
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SWITCHING CHARACTERISTICS
TPS2220A , TPS2223ATPS2224A , TPS2226A
SLVS428E – MAY 2002 – REVISED MSRCH 2008
V
CC
= 5 V, T
A
= 25 °C, V
I(3.3V)
= 3.3 V, V
I(5V)
= 5 V, V
I(12)
= 12 V (not applicable for TPS2223A) all outputs unloaded (unlessotherwise noted)
PARAMETER
(1)
LOAD CONDITION TEST CONDITIONS
(2)
MIN TYP MAX UNIT
V
O(xVCC)
= 5 V 0.9C
L(xVCC)
= 0.1 µF, C
L(xVPP)
= 0.1 µF,I
O(xVCC)
= 0 A, I
O(xVPP)
= 0 A
V
O(xVPP)
= 12 V 0.26t
r
Output rise times
(3)
msV
O(xVCC)
= 5 V 1.1C
L(xVCC)
= 150 µF, C
L(xVPP)
= 10 µF,I
O(xVCC)
= 0.75 A, I
O(xVPP)
= 50 mA
V
O(xVPP)
= 12 V 0.6V
O(xVCC)
= 5 V,
0.5Discharge switches ONC
L(xVCC)
= 0.1 µF, C
L(xVPP)
= 0.1 µF,I
O(xVCC)
= 0 A, I
O(xVPP)
= 0 A
V
O(xVPP)
= 12 V,
0.2t
f
Output fall times
(3)
msDischarge switches ONV
O(xVCC)
= 5 V 2.35C
L(xVCC)
= 150 µF, C
L(xVPP)
= 10 µF,I
O(xVCC)
= 0.75 A, I
O(xVPP)
= 50 mA
V
O(xVPP)
= 12 V 3.9t
pdon
2Latch ↑to xVPP (12V)
(4)
t
pdoff
0.62t
pdon
0.77Latch ↑to xVPP (5V)
t
pdoff
0.51t
pdon
0.75C
L(xVCC)
= 0.1 µF, C
L(xVPP)
= 0.1 µF,
Latch ↑to xVPP (3.3V) msI
O(xVCC)
= 0 A, I
O(xVPP)
= 0 A
t
pdoff
0.52t
pdon
0.3Latch ↑to xVCC (5V)
t
pdoff
2.5t
pdon
0.3Latch ↑to xVCC (3.3V)
t
pdoff
2.8Propagation delayt
pd
times
(3)
t
pdon
2.2Latch ↑to xVPP (12V)
(4)
t
pdoff
0.8t
pdon
0.8Latch ↑to xVPP (5V)
t
pdoff
0.6t
pdon
0.8C
L(xVCC)
= 150 µF, C
L(xVPP)
= 10 µF,
Latch ↑to xVPP (3.3V) msI
O(xVCC)
= 0.75 A, I
O(xVPP)
= 50 mA
t
pdoff
0.6t
pdon
0.6Latch ↑to xVCC (5V)
t
pdoff
2.5t
pdon
0.5Latch ↑to xVCC (3.3V)
t
pdoff
2.6
(1) Refer to Parameter Measurement Information in Figure 1 .(2) No card inserted, assumes a 0.1- µF output capacitor (see Figure 1 ).(3) Specified by design; not tested in production.(4) Not applicable for TPS2223A
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Product Folder Link(s): TPS2220A TPS2223A TPS2224A TPS2226A
www.ti.com
CS
CS
S1
S4
CS
S7
CS
S11
Control Logic
SHDN
RESET
DATA
CLOCK
LATCH
OC
GND
UVLO
POR
Current Limit
Thermal Limit
S2
S5
S3
S6
S8
S9
S10
S12
S13
S14
Discharge
Element
13
14
3.3 V
3.3 V
Power
Inputs
3.3V
1
2
24
5 V
5 V
5 V
Power
Inputs
5V
7
12 V
Power
Inputs
12V
20
12 V
21
12
3
4
5
15
9
10
AVCC
AVCC
17
18
BVCC
BVCC
8AVPP
19 BVPP
11
Power Outputs
NOTES:A. Diagram shown for 24-pin DB package.
B. Current sense
C. The two 12-V pins must be externally connected.
D. No connections for TPS2223A.
See Note B
See Note B
See Note B
See Note B
See Note C
See Note C
See Note C
See Note D
TPS2220A , TPS2223ATPS2224A , TPS2226A
SLVS428E – MAY 2002 – REVISED MSRCH 2008
FUNCTIONAL BLOCK DIAGRAM OF TPS2223A, TPS2224A and TPS2226A (see Note A)
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See Note A
See Note A
CS
S1
CS
S7
Control Logic
SHDN
RESET
DATA
CLOCK
LATCH
OC
GND
UVLO
POR
Current Limit
Thermal Limit
S2
S3
S4
S5
S6
3.3 V
5 V
5 V
12 V
AVCC
AVCC
AVPP
See Note B
NOTES:A. Current sense
B. The two 12-V pins must be externally connected.
12 V
See Note B
PIN ASSIGNMENTS
24
23
22
21
20
19
18
17
16
15
14
13
1
2
3
4
5
6
7
8
9
10
11
12
TPS2220A
DB OR PWP PACKAGE
(TOP VIEW)
5V
5V
DATA
CLOCK
LATCH
NC
12V
AVPP
AVCC
AVCC
GND
RESET
NC
NC
NC
SHDN
12V
NC
NC
NC
NC
OC
NC
3.3V
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
TPS2226A
DB PACKAGE
(TOP VIEW)
5V
5V
DATA
CLOCK
LATCH
NC
12V
AVPP
AVCC
AVCC
AVCC
GND
NC
RESET
3.3V
5V
NC
NC
NC
NC
SHDN
12V
BVPP
BVCC
BVCC
BVCC
NC
OC
3.3V
3.3V
NC - No internal connection
TPS2220A , TPS2223ATPS2224A , TPS2226A
SLVS428E – MAY 2002 – REVISED MSRCH 2008
FUNCTIONAL BLOCK DIAGRAM OF TPS2220A
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Product Folder Link(s): TPS2220A TPS2223A TPS2224A TPS2226A
www.ti.com
TPS2220A , TPS2223ATPS2224A , TPS2226A
SLVS428E – MAY 2002 – REVISED MSRCH 2008
Terminal Functions
TERMINAL
NO. I/O DESCRIPTIONNAME
TPS2220A TPS2223A TPS2224A TPS2226A
3.3V 13 13, 14 13, 14 15, 16, 17 I 3.3-V input for card power and chip power5V 1, 2 1, 2, 24 1, 2, 24 1, 2, 30 I 5-V input for card power12-V input for card power (xVPP). The two 12-V pins must be12V 7, 20 NA 7, 20 7, 24 I
externally connected.
Switched output that delivers 3.3 V, 5 V, ground or high impedance toAVCC 9, 10 9, 10 9, 10 9, 10, 11 O
card
Switched output that delivers 3.3 V, 5 V, 12 V, ground or highAVPP 8 8 8 8 O
impedance to card (12 V not applicable to TPS2223A)Switched output that delivers 3.3 V, 5 V, ground or high impedance toBVCC – 17, 18 17, 18 20, 21, 22 O
card
Switched output that delivers 3.3 V, 5 V, 12 V, ground or highBVPP – 19 19 23 O
impedance to card (12 V not applicable for TPS2223A)GND 11 11 11 12 Ground
Open-drain overcurrent reporting output that goes low when anOC 15 15 15 18 O
overcurrent condition exists. An external pullup is required.Hi-Z (open) all switches. Identical function to serial D8. AsynchronousSHDN 21 21 21 25 I
active-low command, internal pullupLogic-level RESET input active low. Asynchronous active-lowRESET 12 12 12 14 I
command, internal pullupCLOCK 4 4 4 4 I Logic-level clock for serial data wordDATA 3 3 3 3 I Logic-level serial data wordLATCH 5 5 5 5 I Logic-level latch for serial data word, internal pulldown6, 14, 16, 6, 13, 19,6, 7, 16, 6, 16, 22,NC 17, 18, 19, 26, 27, 28, No internal connection20, 22, 23 2322, 23, 24 29
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Product Folder Link(s): TPS2220A TPS2223A TPS2224A TPS2226A
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PARAMETER MEASUREMENT INFORMATION
50%
LATCH VDD
GND
10%
90%
tpd(on)
GND
VO(xVPP)
Propagation Delay (xVPP)
50%
LATCH VDD
GND
10%
90%
tpd(on)
GND
VO(xVCC)
Propagation Delay (xVCC)
10%
90%
tr
GND
VO(xVPP)
Rise/Fall Time (xVPP)
tf
10%
90%
tr
GND
VO(xVCC)
Rise/Fall Time (xVCC)
tf
50% VDD
GND
10%
90%
ton
GND
VO(xVCC)
Turnon/off Time (xVCC)
xVPP
VOLTAGE WAVEFORMS
LOAD CIRCUIT (xVPP)
IO(xVPP)
xVCC
50%
LATCH VDD
GND
10%
90%
ton
GND
VO(xVPP)
Turnon/off Time (xVPP)
IO(xVCC)
tpd(off)
tpd(off)
toff toff
LOAD CIRCUIT (xVCC)
VI(12V/5V/3.3V) VI(5V/3.3V)
VI(12V/5V/3.3V) VI(5V/3.3V)
VI(12V/5V/3.3V) VI(5V/3.3V)
LATCH
D10 D9 D8 D7 D6 D5 D4 D3 D2
DATA
LATCH
CLOCK
D1 D0
Data Setup Time Data Hold Time Latch Delay Time
Clock Delay Time
TPS2220A , TPS2223ATPS2224A , TPS2226A
SLVS428E – MAY 2002 – REVISED MSRCH 2008
Figure 1. Test Circuits and Voltage Waveforms
NOTE: Data is clocked in on the positive edge of the clock. The positive edge of the latch signal should occur before the nextpositive edge of the clock. For definition of D0 to D10, see the control logic table.
Figure 2. Serial-Interface Timing for TPS2226A
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Product Folder Link(s): TPS2220A TPS2223A TPS2224A TPS2226A
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Table of Graphs
1 2 3 4 5
t − Time − ms
0
VO(/OC)
2 V/div
IO(xVPP)
2 A/div
TPS2220A , TPS2223ATPS2224A , TPS2226A
SLVS428E – MAY 2002 – REVISED MSRCH 2008
PARAMETER MEASUREMENT INFORMATION (continued)
FIGURE
Short-circuit response, short applied to powered-on 5-V xVCC-switch output vs Time 3Short-circuit response, short applied to powered-on 12-V xVPP-switch output vs Time 4OC response with ramped overcurrent-limit load on 5-V xVCC-switch output vs Time 5OC response with ramped overcurrent-limit load on 12-V xVPP-switch output vs Time 6xVCC Turnon propagation delay time
L
= 150 µF) vs Junction temperature 7xVCC Turnoff propagation delay time
L
= 150 µF) vs Junction temperature 8xVPP Turnon propagation delay time
L
= 10 µF) vs Junction temperature 9xVPP Turnoff propagation delay time
L
= 10 µF) vs Junction temperature 10xVCC Turnon propagation delay time (T
J
= 25 °C) vs Load capacitance 11xVCC Turnoff propagation delay time (T
J
= 25 °C) vs Load capacitance 12xVPP Turnon propagation delay time (T
J
= 25 °C) vs Load capacitance 13xVPP Turnoff propagation delay time (T
J
= 25 °C) vs Load capacitance 14xVCC Rise time
L
= 150 µF) vs Junction temperature 15xVCC Fall time
L
= 150 µF) vs Junction temperature 16xVPP Rise time
L
= 10 µF) vs Junction temperature 17xVPP Fall time
L
= 10 µF) vs Junction temperature 18xVCC Rise time (T
J
= 25 °C) vs Load capacitance 19xVCC Fall time (T
J
= 25 °C) vs Load capacitance 20xVPP Rise time (T
J
= 25 °C) vs Load capacitance 21xVPP Fall time (T
J
= 25 °C) vs Load capacitance 22
SHORT-CIRCUIT RESPONSE, SHORT-CIRCUIT RESPONSE,SHORT APPLIED TO POWERED-ON 5-V SHORT APPLIED TO POWERED-ON 12-VxVCC-SWITCH OUTPUT xVPP-SWITCH OUTPUT
Figure 3. Figure 4.
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10 20 30 40 50
t − Time − ms
0
VO(/OC)
5 V/div
IO(xVCC)
1 A/div
2 4 6 8 10
t − Time − ms
0
VO(/OC)
5 V/div
IO(xVPP)
100 mA/div
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
−50 −20 10 40 70 100
xVCC = 5 V
IO = 0.75 A
CL = 150 µF
− Turnon Propagation Delay Time, xVCC − ms
tpd(on)
TJ − Junction Temperature − °C
2.25
2.3
2.35
2.4
2.45
2.5
2.55
2.6
−50 −20 10 40 70 100
xVCC = 5 V
IO = 0.75 A
CL = 150 µF
tpd(off)
TJ − Junction Temperature − °C
− Turnoff Propagation Delay Time, xVCC − ms
TPS2220A , TPS2223ATPS2224A , TPS2226A
SLVS428E – MAY 2002 – REVISED MSRCH 2008
OC RESPONSE WITH RAMPED OC RESPONSE WITH RAMPEDOVERCURRENT-LIMIT LOAD ON 5-V OVERCURRENT-LIMIT LOAD ON 12-VxVCC-SWITCH OUTPUT xVPP-SWITCH OUTPUT
Figure 5. Figure 6.
TURNON PROPAGATION DELAY TIME, xVCC TURNOFF PROPAGATION DELAY TIME, xVCCvs vsJUNCTION TEMPERATURE JUNCTION TEMPERATURE
Figure 7. Figure 8.
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0
0.5
1
1.5
2
2.5
3
−50 −20 10 40 70 100
tpd(on)
TJ − Junction Temperature − °C
xVPP = 12 V
IO = 0.05 A
CL = 10 µF
− Turnon Propagation Delay Time, xVPP − ms
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
−50 −20 10 40 70 100
− Turnoff Propagation Delay Time, xVCC − ms
tpd(off)
TJ − Junction Temperature − °C
xVCC = 12 V
IO = 0.05 A
CL = 10 µF
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.1 1 10 100 1000
− Turnon Propagation Delay Time, xVCC − ms
tpd(on)
xVCC = 5 V
IO = 0.75 A
TJ = 25°C
CL − Load Capacitance − µF
2.25
2.3
2.35
2.4
2.45
2.5
2.55
0.1 1 10 100 1000
xVCC = 5 V
IO = 0.75 A
TJ = 25°C
CL − Load Capacitance − µF
tpd(off) − Turnoff Propagation Delay Time, xVCC − ms
TPS2220A , TPS2223ATPS2224A , TPS2226A
SLVS428E – MAY 2002 – REVISED MSRCH 2008
TURNON PROPAGATION DELAY TIME, xVPP TURNON PROPAGATION DELAY TIME, xVPPvs vsJUNCTION TEMPERATURE JUNCTION TEMPERATURE
Figure 9. Figure 10.
TURNON PROPAGATION DELAY TIME, xVCC TURNON PROPAGATION DELAY TIME, xVCCvs vsLOAD CAPACITANCE LOAD CAPACITANCE
Figure 11. Figure 12.
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1.95
2
2.05
2.1
2.15
2.2
2.25
0.1 1 10
− Turnon Propagation Delay Time, xVPP − ms
tpd(on)
xVPP = 12 V
IO = 0.05 A
TJ = 25°C
CL − Load Capacitance − µF
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
0.1 1 10
− Turnoff Propagation Delay Time, xVPP − ms
tpd(off)
xVPP = 12 V
IO = 0.05 A
TJ = 25°C
CL − Load Capacitance − µF
2.34
2.35
2.36
2.37
2.38
2.39
2.4
2.41
−50 −20 10 40 70 100
− Fall Time xVCC − ms
tf
TJ − Junction Temperature − °C
xVCC = 5 V
IO = 0.75 A
CL = 150 µF
1.04
1.06
1.08
1.1
1.12
1.14
1.16
1.18
1.2
1.22
−50 −20 10 40 70 100
− Rise Time, xVCC − ms
tr
TJ − Junction Temperature − °C
xVCC = 5 V
IO = 0.75 A
CL = 150 µF
TPS2220A , TPS2223ATPS2224A , TPS2226A
SLVS428E – MAY 2002 – REVISED MSRCH 2008
TURNON PROPAGATION DELAY TIME, xVPP TURNON PROPAGATION DELAY TIME, xVPPvs vsLOAD CAPACITANCE LOAD CAPACITANCE
Figure 13. Figure 14.
RISE TIME, xVCC FALL TIME, xVCCvs vsJUNCTION TEMPERATURE JUNCTION TEMPERATURE
Figure 15. Figure 16.
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0.575
0.58
0.585
0.59
0.595
0.6
0.605
−50 −20 10 40 70 100
− Rise Time xVPP − ms
tr
TJ − Junction Temperature − °C
xVPP = 12 V
IO = 0.05 A
CL = 10 µF
3.85
3.9
3.95
4
4.05
4.1
4.15
−50 −20 10 40 70 100
− Fall Time, xVPP − ms
tf
TJ − Junction Temperature − °C
xVPP = 12 V
IO = 0.05 A
CL = 10 µF
0
0.5
1
1.5
2
2.5
0.1 1 10 100 1000
− Fall Time xVCC − ms
tf
xVCC = 5 V
IO = 0.75 A
TJ = 25°C
CL − Load Capacitance − µF
0
0.2
0.4
0.6
0.8
1
1.2
0.1 1 10 100 1000
− Rise Time, xVCC − ms
tr
xVCC = 5 V
IO = 0.75 A
TJ = 25°C
CL − Load Capacitance − µF
TPS2220A , TPS2223ATPS2224A , TPS2226A
SLVS428E – MAY 2002 – REVISED MSRCH 2008
RISE TIME, xVPP FALL TIME, xVPPvs vsJUNCTION TEMPERATURE JUNCTION TEMPERATURE
Figure 17. Figure 18.
RISE TIME, xVCC FALL TIME, xVCCvs vsLOAD CAPACITANCE LOAD CAPACITANCE
Figure 19. Figure 20.
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0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
0.1 1 10
− Fall Time, xVPP − ms
tf
xVPP = 12 V
IO = 0.05 A
TJ = 25°C
CL − Load Capacitance − µF
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.1 1 10
− Rise Time, xVPP − ms
tr
xVPP = 12 V
IO = 0.05 A
TJ = 25°C
CL − Load Capacitance − µF
TYPICAL CHARACTERISTICS
Table of Graphs
TPS2220A , TPS2223ATPS2224A , TPS2226A
SLVS428E – MAY 2002 – REVISED MSRCH 2008
RISE TIME, xVPP FALL TIME, xVPPvs vsLOAD CAPACITANCE LOAD CAPACITANCE
Figure 21. Figure 22.
FIGURE
Input current, xVCC = 3.3 V 23I
I
Input current, xVCC = 5 V vs Junction temperature 24Input current, xVPP = 12 V 25Static drain-source on-state resistance, 3.3 V to xVCC switch 26r
DS(on)
Static drain-source on-state resistance, 5 V to xVCC switch vs Junction temperature 27Static drain-source on-state resistance, 12 V to xVPP switch 28xVCC switch voltage drop, 3.3-V input 29V
O
xVCC switch voltage drop, 5-V input vs Load current 30xVPP switch voltage drop, 12-V input 31Short-circuit current limit, 3.3 V to xVCC 32I
OS
Short-circuit current limit, 5 V to xVCC vs Junction temperature 33Short-circuit current limit, 12 V to xVPP 34
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0
20
40
60
80
100
120
140
160
180
−50 −20 10 40 70 100
TJ − Junction Temperature − °C
II− Input Current, xVCC = 3.3 V − Aµ
0
2
4
6
8
10
12
14
−50 −20 10 40 70 100
TJ − Junction Temperature − °C
II− Input Current, xVCC = 5 V − Aµ
0
0.02
0.04
0.06
0.08
0.1
0.12
−50 −20 10 40 70 100
TJ − Junction Temperature − °C
Ω
rDS(on) − Static Drain-Source On-State Resistance,
3.3 V to xVCC Switch −
0
20
40
60
80
100
120
−50 −20 10 40 70 100
TJ − Junction Temperature − °C
II− Input Current, xVPP = 12 V − Aµ
TPS2220A , TPS2223ATPS2224A , TPS2226A
SLVS428E – MAY 2002 – REVISED MSRCH 2008
INPUT CURRENT, xVCC = 3.3 V INPUT CURRENT, xVCC = 5 Vvs vsJUNCTION TEMPERATURE JUNCTION TEMPERATURE
Figure 23. Figure 24.
STATIC DRAIN-SOURCE ON-STATE RESISTANCE,INPUT CURRENT, xVPP = 12 V 3.3 V TO xVCC SWITCHvs vsJUNCTION TEMPERATURE JUNCTION TEMPERATURE
Figure 25. Figure 26.
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0
0.02
0.04
0.06
0.08
0.1
0.12
0.14
−50 −20 10 40 70 100
TJ − Junction Temperature − °C
Ω
rDS(on) − Static Drain-Source On-State Resistance,
5 V to xVCC Switch −
0
0.5
1
1.5
2
2.5
3
−50 −20 10 40 70 100
TJ − Junction Temperature − °C
Ω
rDS(on) − Static Drain-Source On-State Resistance,
12 V to xVPP Switch −
0
0.02
0.04
0.06
0.08
0.1
0.12
0 0.2 0.4 0.6 0.8 1
TJ = −40°C
TJ = 85°C
TJ = 100°C
IL − Load Current − A
− xVCC Switch Voltage Drop, 3.3-V Input − VVO
TJ = 25°C
TJ = 0°C
0
0.02
0.04
0.06
0.08
0.1
0.12
0.14
0 0.2 0.4 0.6 0.8 1
IL − Load Current − A
− xVCC Switch Voltage Drop, 5-V Input − VVO
TJ = −40°C
TJ = 85°C
TJ = 100°C
TJ = 25°C
TJ = 0°C
TPS2220A , TPS2223ATPS2224A , TPS2226A
SLVS428E – MAY 2002 – REVISED MSRCH 2008
STATIC DRAIN-SOURCE ON-STATE RESISTANCE, STATIC DRAIN-SOURCE ON-STATE RESISTANCE,5 V TO xVCC SWITCH 12 V TO xVPP SWITCHvs vsJUNCTION TEMPERATURE JUNCTION TEMPERATURE
Figure 27. Figure 28.
xVCC SWITCH VOLTAGE DROP, 3.3-V INPUT xVCC SWITCH VOLTAGE DROP, 5-V INPUTvs vsLOAD CURRENT LOAD CURRENT
Figure 29. Figure 30.
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0
0.02
0.04
0.06
0.08
0.1
0.12
0.14
0 0.01 0.02 0.03 0.04 0.05
IL − Load Current − A
− xVPP Switch Voltage Drop, 12-V Input − VVO
TJ = −40°C
TJ = 85°C
TJ = 100°C
TJ = 25°C
TJ = 0°C
1.355
1.36
1.365
1.37
1.375
1.38
1.385
1.39
1.395
−50 −20 10 40 70 100
TJ − Junction Temperature − °C
IOS− Short-Circuit Current Limit, 3.3 V to xVCC − A
1.385
1.39
1.395
1.4
1.405
1.41
1.415
1.42
1.425
1.43
1.435
−50 −20 10 40 70 100
TJ − Junction Temperature − °C
IOS− Short-Circuit Current Limit, 5 V to xVCC − A
0.19
0.192
0.194
0.196
0.198
0.2
0.202
0.204
0.206
0.208
−50 −20 10 40 70 100
xVPP = 12 V
TJ − Junction Temperature − °C
IOS− Short-Circuit Current Limit, 12 V to xVPP − A
TPS2220A , TPS2223ATPS2224A , TPS2226A
SLVS428E – MAY 2002 – REVISED MSRCH 2008
xVPP SWITCH VOLTAGE DROP, 12-V INPUT SHORT-CIRCUIT CURRENT LIMIT, 3.3 V TO xVCCvs vsLOAD CURRENT JUNCTION TEMPERATURE
Figure 31. Figure 32.
SHORT-CIRCUIT CURRENT LIMIT, 5 V TO xVCC SHORT-CIRCUIT CURRENT LIMIT, 12 V TO xVPPvs vsJUNCTION TEMPERATURE JUNCTION TEMPERATURE
Figure 33. Figure 34.
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APPLICATION INFORMATION
OVERVIEW
PC CARD POWER SPECIFICATION
DESIGNING FOR VOLTAGE REGULATION
VDS +VO(reg)–VPS(reg)–VPCB
IOmax +
VDS
rDS(on)
OVERCURRENT AND OVERTEMPERATURE PROTECTION
TPS2220A , TPS2223ATPS2224A , TPS2226A
SLVS428E – MAY 2002 – REVISED MSRCH 2008
PC Cards were initially introduced as a means to add flash memory to portable computers. The idea of add-incards quickly took hold, and modems, wireless LANs, global positioning satellite system (GPS), multimedia, andhard-disk versions were soon available. As the number of PC Card applications grew, the engineeringcommunity quickly recognized the need for a standard to ensure compatibility across platforms. Therefore, thePCMCIA (Personal Computer Memory Card International Association) was established, comprising membersfrom leading computer, software, PC Card, and semiconductor manufacturers. One key goal was to realize theplug-and-play concept, so that cards and hosts from different vendors would be transparently compatible.
System compatibility also means power compatibility. The most current set of specifications (PC Card Standard)set forth by the PCMCIA committee states that power is to be transferred between the host and the card througheight of the 68 terminals of the PC Card connector. This power interface consists of two V
CC
, two V
pp
, and fourground terminals. Multiple V
CC
and ground terminals minimize connector-terminal and line resistance. The twoV
pp
terminals were originally specified as separate signals, but are normally tied together in the host to form asingle node to minimize voltage losses. Card primary power is supplied through the V
CC
terminals; flash-memoryprogramming and erase voltage is supplied through the V
pp
terminals. Cardbus cards of today typically do notuse 12 V, which is now more of an optional requirement in the host.
The current PCMCIA specification for output voltage regulation, V
O(reg)
, of the 5-V output is 5% (250 mV). In atypical PC power-system design, the power supply has an output-voltage regulation, V
PS(reg)
, of 2% (100 mV).Also, a voltage drop from the power supply to the PC Card results from resistive losses, V
PCB
, in the PCB tracesand the PCMCIA connector. A typical design would limit the total of these resistive losses to less than 1% (50mV) of the output voltage. Therefore, the allowable voltage drop, V
DS
, for the TPS2220A, TPS2223A, TPS2224A,and TPS2226A would be the PCMCIA voltage regulation less the power supply regulation and less the PCB andconnector resistive drops:
Typically, this would leave 100 mV for the allowable voltage drop across the 5-V switch. The specification foroutput voltage regulation of the 3.3-V output is 300 mV; therefore, using the same equation by deducting thevoltage drop percentages (2%) for power-supply regulation and PCB resistive loss (1%), the allowable voltagedrop for the 3.3-V switch is 200 mV. The voltage drop is the output current multiplied by the switch resistance ofthe device. Therefore, the maximum output current, I
O
max, that can be delivered to the PC Card in regulation isthe allowable voltage drop across the IC, divided by the output-switch resistance.
The xVCC outputs have been designed to deliver the peak and average currents defined by the PC Cardspecification within regulation over the operating temperature range. The xVPP outputs of the device have beendesigned to deliver 100 mA continuously.
PC Cards are inherently subject to damage that can result from mishandling. Host systems require protectionagainst short-circuited cards that can lead to power-supply or PCB trace damage. Even extremely robustsystems can undergo rapid battery discharge into a damaged PC Card, resulting in the sudden and unacceptableloss of system power. In comparison, the reliability of fused systems is poor because blown fuses requiretroubleshooting and repair, usually by the manufacturer.
The TPS2220A, TPS2223A, TPS2224A, and TPS2226A take a two-pronged approach to overcurrent protection,which is designed to activate if an output is shorted or when an overcurrent condition is present when switchesare powered up. First, instead of fuses, sense FETs monitor each of the xVCC and xVPP power outputs. Unlike
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12-V SUPPLY NOT REQUIRED
VOLTAGE-TRANSITIONING REQUIREMENT
SHUTDOWN MODE
POWER-SUPPLY CONSIDERATIONS
TPS2220A , TPS2223ATPS2224A , TPS2226A
SLVS428E – MAY 2002 – REVISED MSRCH 2008
sense resistors or polyfuses, these FETs do not add to the series resistance of the switch; therefore, voltage andpower losses are reduced. Overcurrent sensing is applied to each output separately. Excessive currentgenerates an error signal that limits the output current of only the affected output, preventing damage to the host.Each xVCC output overcurrent limits from 1 A to 2.0 A, typically around 1.6 A; the xVPP outputs limit from 100mA to 250 mA, typically around 200 mA.
Second, when an overcurrent condition is detected, the TPS2220A, TPS2223A, TPS2224A, and TPS2226Aassert an active low OC signal that can be monitored by the microprocessor or controller to initiate diagnosticsand/or send the user a warning message. If an overcurrent condition persists, causing the IC to exceed itsmaximum junction temperature, thermal-protection circuitry activates, shutting down all power outputs until thedevice cools to within a safe operating region, which is ensured by a thermal shutdown hysteresis. Thermallimiting prevents destruction of the IC from overheating beyond the package power-dissipation ratings.
During power up, the devices control the rise times of the xVCC and xVPP outputs and limit the inrush currentinto a large load capacitance, faulty card, or connector.
Some PC Card switches use the externally supplied 12 V to power gate drive and other chip functions, whichrequires that power be present at all times. The TPS2220A, TPS2224A and TPS2226A offer considerable powersavings by using an internal charge pump to generate the required higher gate drive voltages from the 3.3-Vinput. Therefore, the external 12-V supply can be disabled except when needed by the PC Card in the slot,thereby extending battery lifetime. A special feature in the 12-V circuitry actually helps to reduce the supplycurrent demanded from the 3.3-V input. When 12 V is supplied and requested at the VPP output, a voltageselection circuit draws the charge-pump drive current for the 12-V FETs from the 12-V input. This selection isautomatic and effectively reduces demand fluctuations on the normal 3.3-V VCC rail. For proper operation of thisfeature, a minimum 3.3-V input capacitance of 4.7 µF is recommended, and a minimum 12-V input ramp-up rateof 12 V/50 ms (240 V/s) is required. Additional power savings are realized during a software shutdown in whichquiescent current drops to a maximum of 1 µA.
PC Cards, like portables, are migrating from 5 V to 3.3 V to minimize power consumption, optimize board space,and increase logic speeds. The TPS2220A, TPS2223A, TPS2224A, and TPS2226A meet all combinations ofpower delivery as currently defined in the PCMCIA standard. The latest protocol accommodates mixed 3.3-V/5-Vsystems by first powering the card with 5 V, then polling it to determine its 3.3-V compatibility. The PCMCIAspecification requires that the capacitors on 3.3-V-compatible cards be discharged to below 0.8 V beforeapplying 3.3-V power. This action ensures that sensitive 3.3-V circuitry is not subjected to any residual 5-Vcharge and functions as a power reset. PC Card specification requires that V
CC
be discharged within 100 ms. PCCard resistance cannot be relied on to provide a discharge path for voltages stored on PC Card capacitancebecause of possible high-impedance isolation by power-management schemes. The devices include dischargetransistors on all xVCC and xVPP outputs to meet the specification requirement.
In the shutdown mode, which can be controlled by SHDN or bit D8 of the input serial DATA word, each of thexVCC and xVPP outputs is forced to a high-impedance state. In this mode, the chip quiescent current is reducedto 1 µA or less to conserve battery power.
These switches have multiple pins for each 3.3-V (except for TPS2220A) and 5-V power input and for theswitched xVCC outputs. Any individual pin can conduct the rated input or output current. Unless all pins areconnected in parallel, the series resistance is higher than that specified, resulting in increased voltage drops andpower loss. It is recommended that all input and output power pins be paralleled for optimum operation.
To increase the noise immunity of the TPS2220A, TPS2223A, TPS2224A, and TPS2226A, the power-supplyinputs should be bypassed with at least a 4.7- µF electrolytic or tantalum capacitor paralleled by a 0.047- µF to
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RESET INPUT
CALCULATING JUNCTION TEMPERATURE
PD+rDS(on) I2
TJ+ǒȍPD RqJAǓ)TA
where:RθJA is the inverse of the derating factor given in the dissipation rating table.
LOGIC INPUTS AND OUTPUTS
TPS2220A , TPS2223ATPS2224A , TPS2226A
SLVS428E – MAY 2002 – REVISED MSRCH 2008
0.1- µF ceramic capacitor. It is strongly recommended that the switched outputs be bypassed with a 0.1- µF (orlarger) ceramic capacitor; doing so improves the immunity of the IC to electrostatic discharge (ESD). Care shouldbe taken to minimize the inductance of PCB traces between the devices and the load. High switching currentscan produce large negative voltage transients, which forward biases substrate diodes, resulting in unpredictableperformance. Similarly, no pin should be taken below -0.3 V.
To ensure that cards are in a known state after power brownouts or system initialization, the PC Cards should bereset at the same time as the host by applying low-impedance paths from xVCC and xVPP terminals to ground.A low-impedance output state allows discharging of residual voltage remaining on PC Card filter capacitance,permitting the system (host and PC Cards) to be powered up concurrently. The active low RESET input closesinternal ground switches S1, S4, S7, and S11 with all other switches left open. The TPS2220A, TPS2223A,TPS2224A, and TPS2226A remain in the low-impedance output state until the signal is de-asserted and furtherdata is clocked in and latched. The input serial data cannot be latched during reset mode. RESET is provided fordirect compatibility with systems that use an active-low reset voltage supervisor. The RESET pin has an internal150-k Ωpullup resistor.
The switch resistance, r
DS(on)
, is dependent on the junction temperature, T
J
, of the die. The junction temperatureis dependent on both r
DS(on)
and the current through the switch. To calculate T
J
, first find r
DS(on)
from Figure 26through Figure 28 , using an initial temperature estimate about 30 °C above ambient. Then, calculate the powerdissipation for each switch, using the formula:
Next, sum the power dissipation of all switches and calculate the junction temperature:
Compare the calculated junction temperature with the initial temperature estimate. If the temperatures are notwithin a few degrees of each other, recalculate using the calculated temperature as the initial estimate.
The serial interface consists of the DATA, CLOCK, and LATCH leads. The data is clocked in on the positiveedge of the clock (see Figure 2 ). The 11-bit (D0-D10) serial data word is loaded during the positive edge of thelatch signal. The positive edge of the latch signal should occur before the next positive edge of the clock occurs.
The serial interface of the device is compatible with serial-interface PCMCIA controllers.
An overcurrent output ( OC) is provided to indicate an overcurrent or overtemperature condition in any of thexVCC and xVPP outputs as previously discussed.
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PACKAGE OPTION ADDENDUM
www.ti.com 30-Jul-2011
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
TPS2220ADBR ACTIVE SSOP DB 24 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS2220ADBRG4 ACTIVE SSOP DB 24 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS2220APWP ACTIVE HTSSOP PWP 24 60 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS2220APWPG4 ACTIVE HTSSOP PWP 24 60 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS2220APWPR ACTIVE HTSSOP PWP 24 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS2220APWPRG4 ACTIVE HTSSOP PWP 24 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS2223ADB ACTIVE SSOP DB 24 60 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS2223ADBG4 ACTIVE SSOP DB 24 60 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS2223ADBR ACTIVE SSOP DB 24 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS2223ADBRG4 ACTIVE SSOP DB 24 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS2223APWP ACTIVE HTSSOP PWP 24 60 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS2223APWPG4 ACTIVE HTSSOP PWP 24 60 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS2223APWPR ACTIVE HTSSOP PWP 24 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS2223APWPRG4 ACTIVE HTSSOP PWP 24 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS2224ADB ACTIVE SSOP DB 24 60 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS2224ADBG4 ACTIVE SSOP DB 24 60 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS2224ADBR ACTIVE SSOP DB 24 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
PACKAGE OPTION ADDENDUM
www.ti.com 30-Jul-2011
Addendum-Page 2
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
TPS2224ADBRG4 ACTIVE SSOP DB 24 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS2224APWP ACTIVE HTSSOP PWP 24 60 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS2224APWPG4 ACTIVE HTSSOP PWP 24 60 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS2224APWPR ACTIVE HTSSOP PWP 24 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS2224APWPRG4 ACTIVE HTSSOP PWP 24 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS2226ADB ACTIVE SSOP DB 30 50 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS2226ADBG4 ACTIVE SSOP DB 30 50 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS2226ADBR ACTIVE SSOP DB 30 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS2226ADBRG4 ACTIVE SSOP DB 30 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
PACKAGE OPTION ADDENDUM
www.ti.com 30-Jul-2011
Addendum-Page 3
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
TPS2220ADBR SSOP DB 24 2000 330.0 16.4 8.2 8.8 2.5 12.0 16.0 Q1
TPS2220APWPR HTSSOP PWP 24 2000 330.0 16.4 6.95 8.3 1.6 8.0 16.0 Q1
TPS2223ADBR SSOP DB 24 2000 330.0 16.4 8.2 8.8 2.5 12.0 16.0 Q1
TPS2223APWPR HTSSOP PWP 24 2000 330.0 16.4 6.95 8.3 1.6 8.0 16.0 Q1
TPS2224ADBR SSOP DB 24 2000 330.0 16.4 8.2 8.8 2.5 12.0 16.0 Q1
TPS2224APWPR HTSSOP PWP 24 2000 330.0 16.4 6.95 8.3 1.6 8.0 16.0 Q1
TPS2226ADBR SSOP DB 30 2000 330.0 16.4 8.2 10.5 2.5 12.0 16.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TPS2220ADBR SSOP DB 24 2000 367.0 367.0 38.0
TPS2220APWPR HTSSOP PWP 24 2000 367.0 367.0 38.0
TPS2223ADBR SSOP DB 24 2000 367.0 367.0 38.0
TPS2223APWPR HTSSOP PWP 24 2000 367.0 367.0 38.0
TPS2224ADBR SSOP DB 24 2000 367.0 367.0 38.0
TPS2224APWPR HTSSOP PWP 24 2000 367.0 367.0 38.0
TPS2226ADBR SSOP DB 30 2000 367.0 367.0 38.0
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 2
MECHANICAL DATA
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE
4040065 /E 12/01
28 PINS SHOWN
Gage Plane
8,20
7,40
0,55
0,95
0,25
38
12,90
12,30
28
10,50
24
8,50
Seating Plane
9,907,90
30
10,50
9,90
0,38
5,60
5,00
15
0,22
14
A
28
1
2016
6,50
6,50
14
0,05 MIN
5,905,90
DIM
A MAX
A MIN
PINS **
2,00 MAX
6,90
7,50
0,65 M
0,15
0°–ā8°
0,10
0,09
0,25
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-150
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