TPS2220A, TPS2223A TPS2224A, TPS2226A www.ti.com SLVS428E - MAY 2002 - REVISED MSRCH 2008 CARDBUS POWER-INTERFACE SWITCHES FOR SERIAL PCMCIA CONTROLLERS FEATURES APPLICATIONS * Provides S-CARD and M-CARD Power Management for CableCARDTM Applications * Single-Slot Switch: TPS2220A Dual-Slot Switches: TPS2223A, TPS2224A, TPS2226A * Fast Current Limit Response Time * Fully Integrated VCC and VPP Switching for 3.3 V, 5 V, and 12 V (no 12 V on TPS2223A) * Meets Current PC CardTM Standards * Vpp Output Selection Independent of VCC * 12-V and 5-V Supplies Can Be Disabled * TTL-Logic Compatible Inputs * Short-Circuit and Thermal Protection * 24-Pin HTSSOP, 24- or 30-Pin SSOP * 140-A (Typical) Quiescent Current from 3.3-V Input * Break-Before-Make Switching * Power-On Reset * -40C to 85C Operating Ambient Temperature Range * * * * * 1 234 Notebook and Desktop Computers Bar Code Scanners Digital Cameras Set-Top Boxes PDAs TPS2223A, TPS2224A DB OR PWP PACKAGE (TOP VIEW) 5V 5V DATA CLOCK LATCH NC 12V AVPP AVCC AVCC GND RESET 1 2 3 4 5 6 7 8 9 10 11 12 NC - No internal connection Pin 7 and 20 are NC for 24 23 22 21 20 19 18 17 16 15 14 13 5V NC NC SHDN 12V BVPP BVCC BVCC NC OC 3.3V 3.3V TPS2223A. DESCRIPTION The TPS2223A, TPS2224A, and TPS2226A CardBusTM power-interface switches provide an integrated power-management solution for two PC Card sockets. The TPS2220A is a single-slot option for this family of devices. These devices allow the controlled distribution of 3.3 V, 5 V, and 12 V to each card slot. The current-limiting and thermal-protection features eliminate the need for fuses. Current-limit reporting helps the user isolate a system fault. The switch rDS(on) and current-limit values have been set for the peak and average current requirements stated in the PC Card specification, and optimized for cost. A faster maximum current limit response time is the only difference between the TPS2223A, TPS2224A, and TPS2226A and the TPS2223, TPS2224, and TPS2226. Like the TPS2214 and TPS2214A and the TPS2216 and TPS2216A, this family of devices supports independent VPP/VCC switching; however, the standby and interface-mode pins are not supported. Shutdown mode is now supported independently on SHDN as well as in the serial interface. Optimized for lower power implementation, the TPS2223A does not support 12-V switching to VPP. For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI website at www.ti.com. 1 2 3 4 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. CableCARD is a trademark of Cable Tevelision Laboratories, Inc.. PC Card, CardBus are trademarks of PCMCIA (Personal Computer Memory Card International Association). All other trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright (c) 2002-2008, Texas Instruments Incorporated TPS2220A, TPS2223A TPS2224A, TPS2226A www.ti.com SLVS428E - MAY 2002 - REVISED MSRCH 2008 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range (unless otherwise noted) (1) VI Input voltage range for card power TPA222xA UNIT VI(3.3V) -0.3 to 5.5 V VI(5V) -0.3 to 5.5 V VI(12V) (2) -0.3 to 14 V -0.3 to 6 V VO(xVCC) -0.3 to 6 V VO(xVPP) -0.3 to 14 V Logic input/output voltage VO Output voltage Continuous total power dissipation See Dissipation Rating Table IO(xVCC) Internally Limited IO Output current TJ Operating virtual junction temperature range -40 to 100 C Tstg Storage temperature range -55 to 150 C 10 mA IO(xVPP) Internally Limited OC sink current (1) (2) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. Not applicable for TPS2223A DISSIPATION RATING TABLE PACKAGE (1) DB PWP (1) TA 25C POWER RATING DERATING FACTOR ABOVE TA = 25C TA = 70C POWER RATING TA = 85C POWER RATING 356 mW 24 890 mW 8.9 mW/C 489 mW 30 1095 mW 10.95 mW/C 602 mW 438 mW 24 3322 mW 33.22 mW/C 1827 mW 1329 mW These devices are mounted on an JEDEC low-k board (2-oz. traces on surface). RECOMMENDED OPERATING CONDITIONS VI(3.3V) (1) Input voltage, VI(3.3V) is required for all circuit operations. 5V and 12V are only required for VI(5V) their respective functions. VI(12V) (2) IO Output current f(clock) Clock frequency MIN MAX 3 3.6 3 5.5 7 13.5 UNIT V IO(xVCC) at TJ = 100C 1 IO(xVPP) at TJ = 100C 100 mA 2.5 MHz Data 200 Latch 250 Clock 100 Reset 100 A tw Pulse duration th Data-to-clock hold time (see Figure 2) 100 ns tsu Data-to-clock setup time (see Figure 2) 100 ns td(latch) Latch delay time (see Figure 2) 100 ns td(clock) Clock delay time (see Figure 2) 250 ns (1) (2) 2 ns It is understood that for VI(3.3V) < 3 V, voltages within the absolute maximum ratings applied to pin 5V or pin 12V do not damage the IC. Not applicable for TPS2223A Submit Documentation Feedback Copyright (c) 2002-2008, Texas Instruments Incorporated Product Folder Link(s): TPS2220A TPS2223A TPS2224A TPS2226A TPS2220A, TPS2223A TPS2224A, TPS2226A www.ti.com SLVS428E - MAY 2002 - REVISED MSRCH 2008 RECOMMENDED OPERATING CONDITIONS (continued) Operating virtual junction temperature (maximum to be calculated at worst case PD at 85C ambient) TJ MIN MAX UNIT -40 100 C ELECTRICAL CHARACTERISTICS TJ = 25C, VI(5V) = 5 V, VI(3.3V) = 3.3 V, VI(12V) = 12 V (not applicable for TPS2223A), all outputs unloaded (unless otherwise noted) TEST CONDITIONS (1) PARAMETER MIN TYP MAX UNIT POWER SWITCH IO = 750 mA each 3.3V to xVCC (2) Static drain-source on-state resistance 3.3V or 5V to xVPP (2) 12V to xVPP (2) Output discharge resistance IOS TJ 140 95 130 IO = 500 mA each, TJ = 100C 120 160 IO = 50 mA each 0.8 1 IO = 50 mA each, TJ = 100C 1 1.3 IO = 50 mA each 2 2.5 2.5 3.4 IO = 50 mA each, TJ = 100C Discharge at xVCC IO(disc) = 1 mA 0.5 0.7 1 Discharge at xVPP IO(disc) = 1 mA 0.2 0.4 0.5 Short-circuit output current Thermal shutdown temperature (2) 110 IO = 500 mA each 5V to xVCC (2) rDS(on) 85 110 IO = 750 mA each, TJ = 100C Thermal trip point Limit (steady-state value), output powered into a short circuit IOS(xVCC) 1 1.4 2 IOS(xVPP) 120 200 300 Limit (steady-state value), output powered into a short circuit, TJ = 100C IOS(xVCC) 1 1.4 2 IOS(xVPP) 120 200 300 Rising temperature 135 Hysteresis 5V to xVCC = 5 V, with 100-m short to GND 10 5V to xVPP = 5 V, with 100-m short to GND 3 II(3.3V) Normal operation II Input current, quiescent Shutdown mode II(5V) 140 VO(xVCC) = VO(xVPP) = 3.3 V and also for RESET = 0 V 8 12 180 II(3.3V) 0.3 2 0.1 2 VO(xVCC) = VO(xVPP) = Hi-z 0.3 VO(xVCC) = 5 V, VI(5V) = VI(12V) = 0 V Ilkg Leakage current, output off state Shutdown mode VO(xVPP) = 12 V, VI(5V) = VI(12V) = 0 V (1) (2) (3) (4) A mA A mA 200 100 II(12V) k s II(12V) II(5V) C 10 Current-limit response time (3) (4) m A 2 10 TJ = 100C 50 10 TJ = 100C A 50 Pulse-testing techniques maintain junction temperature close to ambient temperature; thermal effects must be taken into account separately. TPS2223A, TPS2224A, TPS2226A: two switches on. TPS2220A: one switch on. Specified by design; not tested in production. From application of short to 110% of final current limit. Copyright (c) 2002-2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPS2220A TPS2223A TPS2224A TPS2226A 3 TPS2220A, TPS2223A TPS2224A, TPS2226A www.ti.com SLVS428E - MAY 2002 - REVISED MSRCH 2008 ELECTRICAL CHARACTERISTICS (continued) TJ = 25C, VI(5V) = 5 V, VI(3.3V) = 3.3 V, VI(12V) = 12 V (not applicable for TPS2223A), all outputs unloaded (unless otherwise noted) TEST CONDITIONS (1) PARAMETER MIN TYP MAX -20 -10 UNIT LOGIC SECTION (CLOCK, DATA, LATCH, RESET, SHDN, OC) (5) II(/RESET) II Input current, logic -1 RESET = 0 V II(/SHDN) (5) II(LATCH) (5) II(CLOCK, RESET = 5.5 V DATA) -30 SHDN = 5.5 V SHDN = 0 V 1 -1 1 -50 -3 LATCH = 5.5 V LATCH = 0 V -1 1 0 V to 5.5 V -1 1 VIH High-level input voltage, logic VIL Low-level input voltage, logic VO(sat) Output saturation voltage at OC IO = 2 mA Ilkg Leakage current at OC VO(/OC) = 5.5 V A 50 2 V 0.8 V 0.14 0.4 V 0 1 A 2.7 2.9 UVLO AND POR (POWER-ON RESET) VI(3.3V) Input voltage at 3.3V pin, UVLO Vhys(3.3V) UVLO hysteresis voltage at VA (6) VI(5V) Input voltage at 5V pin, UVLO Vhys(5V) tdf 4 5-V level below which only 5V switches are Hi-Z Input voltage, power-on reset (6) 2.4 100 Delay from voltage hit (step from 3 V to 2.3 V) to Hi-Z control (90% VG to GND) (6) Delay time for falling response, UVLO VI(POR) (5) (6) UVLO hysteresis voltage at 5V 3.3-V level below which all switches are Hi-Z (6) 3.3-V voltage below which POR is asserted causing a RESET internally with all line switches open and all discharge switches closed. 2.3 2.5 V mV 2.8 V 100 mV 4 s 1.7 V LATCH has low-current pulldown. RESET and SHDN have low-current pullup. Specified by design; not tested in production. Submit Documentation Feedback Copyright (c) 2002-2008, Texas Instruments Incorporated Product Folder Link(s): TPS2220A TPS2223A TPS2224A TPS2226A TPS2220A, TPS2223A TPS2224A, TPS2226A www.ti.com SLVS428E - MAY 2002 - REVISED MSRCH 2008 SWITCHING CHARACTERISTICS VCC = 5 V, TA = 25C, VI(3.3V) = 3.3 V, VI(5V) = 5 V, VI(12) = 12 V (not applicable for TPS2223A) all outputs unloaded (unless otherwise noted) PARAMETER (1) tr tf LOAD CONDITION Output rise times (3) Output fall times (3) TEST CONDITIONS (2) 0.9 VO(xVPP) = 12 V 0.26 CL(xVCC) = 150 F, CL(xVPP) = 10 F, IO(xVCC) = 0.75 A, IO(xVPP) = 50 mA VO(xVCC) = 5 V 1.1 VO(xVPP) = 12 V 0.6 VO(xVCC) = 5 V, Discharge switches ON 0.5 VO(xVPP) = 12 V, Discharge switches ON 0.2 CL(xVCC) = 0.1 F, CL(xVPP) = 0.1 F, IO(xVCC) = 0 A, IO(xVPP) = 0 A VO(xVCC) = 5 V 2.35 VO(xVPP) = 12 V 3.9 Latch to xVPP (12V) (4) Latch to xVPP (5V) CL(xVCC) = 0.1 F, CL(xVPP) = 0.1 F, IO(xVCC) = 0 A, IO(xVPP) = 0 A Latch to xVPP (3.3V) Latch to xVCC (5V) Latch to xVCC (3.3V) Propagation delay times (3) Latch to xVPP (12V) (4) Latch to xVPP (5V) CL(xVCC) = 150 F, CL(xVPP) = 10 F, IO(xVCC) = 0.75 A, IO(xVPP) = 50 mA Latch to xVPP (3.3V) Latch to xVCC (5V) Latch to xVCC (3.3V) (1) (2) (3) (4) TYP MAX VO(xVCC) = 5 V CL(xVCC) = 150 F, CL(xVPP) = 10 F, IO(xVCC) = 0.75 A, IO(xVPP) = 50 mA tpd MIN CL(xVCC) = 0.1 F, CL(xVPP) = 0.1 F, IO(xVCC) = 0 A, IO(xVPP) = 0 A tpdon 2 tpdoff 0.62 tpdon 0.77 tpdoff 0.51 tpdon 0.75 tpdoff 0.52 tpdon 0.3 tpdoff 2.5 tpdon 0.3 tpdoff 2.8 tpdon 2.2 tpdoff 0.8 tpdon 0.8 tpdoff 0.6 tpdon 0.8 tpdoff 0.6 tpdon 0.6 tpdoff 2.5 tpdon 0.5 tpdoff 2.6 UNIT ms ms ms ms Refer to Parameter Measurement Information in Figure 1. No card inserted, assumes a 0.1-F output capacitor (see Figure 1). Specified by design; not tested in production. Not applicable for TPS2223A Copyright (c) 2002-2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPS2220A TPS2223A TPS2224A TPS2226A 5 TPS2220A, TPS2223A TPS2224A, TPS2226A www.ti.com SLVS428E - MAY 2002 - REVISED MSRCH 2008 FUNCTIONAL BLOCK DIAGRAM OF TPS2223A, TPS2224A and TPS2226A (see Note A) 13 S2 14 S5 1 5V 2 5V 5 V 24 S3 3.3 V 3.3 V Power Inputs 5V 10 S1 S6 17 CS See Note B See Note C 12 V 9 CS See Note B S4 See Note B S8 7 18 8 CS AVCC AVCC BVCC BVCC AVPP Power Outputs Power Inputs 3.3V S9 S7 Power Inputs 12V S10 See Note D See Note B CS S12 12 V 20 See Note C 19 S13 S11 S14 Control Logic 21 12 SHDN 3 4 DATA 5 15 NOTES: A. B. C. D. 6 BVPP Discharge Element See Note C Current Limit RESET Thermal Limit CLOCK LATCH 11 GND UVLO OC POR Diagram shown for 24-pin DB package. Current sense The two 12-V pins must be externally connected. No connections for TPS2223A. Submit Documentation Feedback Copyright (c) 2002-2008, Texas Instruments Incorporated Product Folder Link(s): TPS2220A TPS2223A TPS2224A TPS2226A TPS2220A, TPS2223A TPS2224A, TPS2226A www.ti.com SLVS428E - MAY 2002 - REVISED MSRCH 2008 FUNCTIONAL BLOCK DIAGRAM OF TPS2220A See Note A S2 3.3 V CS AVCC AVCC S1 S3 5V S4 See Note A CS AVPP S5 S7 5V 12 V See Note B S6 12 V See Note B Control Logic Current Limit SHDN RESET Thermal Limit DATA CLOCK GND LATCH UVLO OC POR NOTES: A. Current sense B. The two 12-V pins must be externally connected. PIN ASSIGNMENTS TPS2226A DB PACKAGE (TOP VIEW) 5V 5V DATA CLOCK LATCH NC 12V AVPP AVCC AVCC AVCC GND NC RESET 3.3V 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 TPS2220A DB OR PWP PACKAGE (TOP VIEW) 5V NC NC NC NC SHDN 12V BVPP BVCC BVCC BVCC NC OC 3.3V 3.3V 5V 5V DATA CLOCK LATCH NC 12V AVPP AVCC AVCC GND RESET 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 NC NC NC SHDN 12V NC NC NC NC OC NC 3.3V NC - No internal connection Copyright (c) 2002-2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPS2220A TPS2223A TPS2224A TPS2226A 7 TPS2220A, TPS2223A TPS2224A, TPS2226A www.ti.com SLVS428E - MAY 2002 - REVISED MSRCH 2008 Terminal Functions TERMINAL NAME NO. I/O DESCRIPTION TPS2220A TPS2223A TPS2224A TPS2226A 3.3V 13 13, 14 13, 14 15, 16, 17 I 3.3-V input for card power and chip power 5V 1, 2 1, 2, 24 1, 2, 24 1, 2, 30 I 5-V input for card power 12V 7, 20 NA 7, 20 7, 24 I 12-V input for card power (xVPP). The two 12-V pins must be externally connected. AVCC 9, 10 9, 10 9, 10 9, 10, 11 O Switched output that delivers 3.3 V, 5 V, ground or high impedance to card AVPP 8 8 8 8 O Switched output that delivers 3.3 V, 5 V, 12 V, ground or high impedance to card (12 V not applicable to TPS2223A) BVCC - 17, 18 17, 18 20, 21, 22 O Switched output that delivers 3.3 V, 5 V, ground or high impedance to card BVPP - 19 19 23 O Switched output that delivers 3.3 V, 5 V, 12 V, ground or high impedance to card (12 V not applicable for TPS2223A) GND 11 11 11 12 OC 15 15 15 18 O Open-drain overcurrent reporting output that goes low when an overcurrent condition exists. An external pullup is required. SHDN 21 21 21 25 I Hi-Z (open) all switches. Identical function to serial D8. Asynchronous active-low command, internal pullup RESET 12 12 12 14 I Logic-level RESET input active low. Asynchronous active-low command, internal pullup CLOCK 4 4 4 4 I Logic-level clock for serial data word DATA 3 3 3 3 I Logic-level serial data word LATCH 5 5 5 5 I Logic-level latch for serial data word, internal pulldown 6, 16, 22, 23 6, 13, 19, 26, 27, 28, 29 NC 8 6, 14, 16, 17, 18, 19, 22, 23, 24 6, 7, 16, 20, 22, 23 Submit Documentation Feedback Ground No internal connection Copyright (c) 2002-2008, Texas Instruments Incorporated Product Folder Link(s): TPS2220A TPS2223A TPS2224A TPS2226A TPS2220A, TPS2223A TPS2224A, TPS2226A www.ti.com SLVS428E - MAY 2002 - REVISED MSRCH 2008 PARAMETER MEASUREMENT INFORMATION xVPP xVCC IO(xVPP) IO(xVCC) LOAD CIRCUIT (xVCC) LOAD CIRCUIT (xVPP) VDD LATCH VDD LATCH 50% 50% GND GND tpd(off) tpd(on) VI(12V/5V/3.3V) VI(5V/3.3V) 90% VO(xVPP) VO(xVCC) Propagation Delay (xVCC) tf tf tr VI(12V/5V/3.3V) VI(5V/3.3V) VO(xVCC) 90% GND 10% GND 10% Propagation Delay (xVPP) VO(xVPP) 90% GND 10% tr tpd(off) tpd(on) 90% GND 10% Rise/Fall Time (xVCC) Rise/Fall Time (xVPP) VDD LATCH VDD 50% 50% LATCH GND GND toff ton VI(5V/3.3V) VI(12V/5V/3.3V) VO(xVPP) toff ton VO(xVCC) 90% 90% GND 10% 10% Turnon/off Time (xVPP) GND Turnon/off Time (xVCC) VOLTAGE WAVEFORMS Figure 1. Test Circuits and Voltage Waveforms DATA D10 D9 D8 D7 Data Setup Time D6 D5 Data Hold Time D4 D3 D2 D1 D0 Latch Delay Time LATCH Clock Delay Time CLOCK NOTE: Data is clocked in on the positive edge of the clock. The positive edge of the latch signal should occur before the next positive edge of the clock. For definition of D0 to D10, see the control logic table. Figure 2. Serial-Interface Timing for TPS2226A Copyright (c) 2002-2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPS2220A TPS2223A TPS2224A TPS2226A 9 TPS2220A, TPS2223A TPS2224A, TPS2226A www.ti.com SLVS428E - MAY 2002 - REVISED MSRCH 2008 PARAMETER MEASUREMENT INFORMATION (continued) Table of Graphs FIGURE Short-circuit response, short applied to powered-on 5-V xVCC-switch output vs Time 3 Short-circuit response, short applied to powered-on 12-V xVPP-switch output vs Time 4 OC response with ramped overcurrent-limit load on 5-V xVCC-switch output vs Time 5 OC response with ramped overcurrent-limit load on 12-V xVPP-switch output vs Time 6 xVCC Turnon propagation delay time L = 150 F) vs Junction temperature 7 xVCC Turnoff propagation delay time L = 150 F) vs Junction temperature 8 xVPP Turnon propagation delay time L = 10 F) vs Junction temperature 9 xVPP Turnoff propagation delay time L = 10 F) vs Junction temperature 10 xVCC Turnon propagation delay time (TJ = 25C) vs Load capacitance 11 xVCC Turnoff propagation delay time (TJ = 25C) vs Load capacitance 12 xVPP Turnon propagation delay time (TJ = 25C) vs Load capacitance 13 xVPP Turnoff propagation delay time (TJ = 25C) vs Load capacitance 14 xVCC Rise time = 150 F) vs Junction temperature 15 xVCC Fall time L = 150 F) vs Junction temperature 16 xVPP Rise time L = 10 F) vs Junction temperature 17 xVPP Fall time L = 10 F) vs Junction temperature 18 xVCC Rise time (TJ = 25C) vs Load capacitance 19 xVCC Fall time (TJ = 25C) vs Load capacitance 20 xVPP Rise time (TJ = 25C) vs Load capacitance 21 xVPP Fall time (TJ = 25C) vs Load capacitance 22 L SHORT-CIRCUIT RESPONSE, SHORT APPLIED TO POWERED-ON 5-V xVCC-SWITCH OUTPUT SHORT-CIRCUIT RESPONSE, SHORT APPLIED TO POWERED-ON 12-V xVPP-SWITCH OUTPUT VO(/OC) 5 V/div VO(/OC) 2 V/div VIN(5V) 2 V/div IO(xVPP) 2 A/div IO(VCC) 5 A/div 0 100 200 300 t - Time - s Figure 3. 10 Submit Documentation Feedback 400 500 0 1 2 3 4 5 t - Time - ms Figure 4. Copyright (c) 2002-2008, Texas Instruments Incorporated Product Folder Link(s): TPS2220A TPS2223A TPS2224A TPS2226A TPS2220A, TPS2223A TPS2224A, TPS2226A www.ti.com SLVS428E - MAY 2002 - REVISED MSRCH 2008 OC RESPONSE WITH RAMPED OVERCURRENT-LIMIT LOAD ON 5-V xVCC-SWITCH OUTPUT OC RESPONSE WITH RAMPED OVERCURRENT-LIMIT LOAD ON 12-V xVPP-SWITCH OUTPUT VO(/OC) 5 V/div VO(/OC) 5 V/div IO(xVCC) 1 A/div IO(xVPP) 100 mA/div 0 10 20 30 40 50 0 t - Time - ms Figure 5. xVCC = 5 V IO = 0.75 A CL = 150 F 0.6 0.5 0.4 0.3 0.2 0.1 -20 10 40 70 TJ - Junction Temperature - C Figure 7. Copyright (c) 2002-2008, Texas Instruments Incorporated 100 t pd(off) - Turnoff Propagation Delay Time, xVCC - ms t pd(on) - Turnon Propagation Delay Time, xVCC - ms 6 8 10 TURNOFF PROPAGATION DELAY TIME, xVCC vs JUNCTION TEMPERATURE 0.8 0 -50 4 t - Time - ms Figure 6. TURNON PROPAGATION DELAY TIME, xVCC vs JUNCTION TEMPERATURE 0.7 2 2.6 xVCC = 5 V IO = 0.75 A CL = 150 F 2.55 2.5 2.45 2.4 2.35 2.3 2.25 -50 -20 10 40 70 TJ - Junction Temperature - C Figure 8. Submit Documentation Feedback Product Folder Link(s): TPS2220A TPS2223A TPS2224A TPS2226A 100 11 TPS2220A, TPS2223A TPS2224A, TPS2226A www.ti.com SLVS428E - MAY 2002 - REVISED MSRCH 2008 xVPP = 12 V IO = 0.05 A CL = 10 F 2.5 2 1.5 1 0.5 0 -50 -20 10 40 70 TJ - Junction Temperature - C 100 0.9 0.8 0.7 0.6 0.5 0.4 0.3 xVCC = 12 V IO = 0.05 A CL = 10 F 0.2 0.1 0 -50 -20 10 40 70 TJ - Junction Temperature - C Figure 9. Figure 10. TURNON PROPAGATION DELAY TIME, xVCC vs LOAD CAPACITANCE TURNON PROPAGATION DELAY TIME, xVCC vs LOAD CAPACITANCE 0.7 xVCC = 5 V IO = 0.75 A TJ = 25C 0.6 0.5 0.4 0.3 0.2 0.1 0 t pd(off) - Turnoff Propagation Delay Time, xVCC - ms 3 0.1 1 10 100 CL - Load Capacitance - F Figure 11. 12 TURNON PROPAGATION DELAY TIME, xVPP vs JUNCTION TEMPERATURE Submit Documentation Feedback 1000 t pd(off) - Turnoff Propagation Delay Time, xVCC - ms t pd(on) - Turnon Propagation Delay Time, xVCC - ms t pd(on) - Turnon Propagation Delay Time, xVPP - ms TURNON PROPAGATION DELAY TIME, xVPP vs JUNCTION TEMPERATURE 100 2.55 2.5 xVCC = 5 V IO = 0.75 A TJ = 25C 2.45 2.4 2.35 2.3 2.25 0.1 1 10 100 CL - Load Capacitance - F 1000 Figure 12. Copyright (c) 2002-2008, Texas Instruments Incorporated Product Folder Link(s): TPS2220A TPS2223A TPS2224A TPS2226A TPS2220A, TPS2223A TPS2224A, TPS2226A www.ti.com SLVS428E - MAY 2002 - REVISED MSRCH 2008 TURNON PROPAGATION DELAY TIME, xVPP vs LOAD CAPACITANCE 2.25 2.2 xVPP = 12 V IO = 0.05 A TJ = 25C 2.15 2.1 2.05 2 1.95 0.1 1 CL - Load Capacitance - F 10 t pd(off) - Turnoff Propagation Delay Time, xVPP - ms t pd(on) - Turnon Propagation Delay Time, xVPP - ms TURNON PROPAGATION DELAY TIME, xVPP vs LOAD CAPACITANCE 0.8 xVPP = 12 V IO = 0.05 A TJ = 25C 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 0.1 1 CL - Load Capacitance - F Figure 13. Figure 14. RISE TIME, xVCC vs JUNCTION TEMPERATURE FALL TIME, xVCC vs JUNCTION TEMPERATURE 1.22 10 2.41 xVCC = 5 V IO = 0.75 A CL = 150 F 1.18 2.4 t f - Fall Time xVCC - ms 1.2 t r - Rise Time, xVCC - ms 0.9 1.16 1.14 1.12 1.1 xVCC = 5 V IO = 0.75 A CL = 150 F 2.39 2.38 2.37 2.36 1.08 2.35 1.06 1.04 -50 -20 10 40 70 TJ - Junction Temperature - C Figure 15. Copyright (c) 2002-2008, Texas Instruments Incorporated 100 2.34 -50 -20 10 40 70 TJ - Junction Temperature - C 100 Figure 16. Submit Documentation Feedback Product Folder Link(s): TPS2220A TPS2223A TPS2224A TPS2226A 13 TPS2220A, TPS2223A TPS2224A, TPS2226A www.ti.com SLVS428E - MAY 2002 - REVISED MSRCH 2008 RISE TIME, xVPP vs JUNCTION TEMPERATURE FALL TIME, xVPP vs JUNCTION TEMPERATURE 4.15 0.605 xVPP = 12 V IO = 0.05 A CL = 10 F 4.1 t f - Fall Time, xVPP - ms t r - Rise Time xVPP - ms 0.6 0.595 0.59 0.585 0.58 -20 10 40 70 TJ - Junction Temperature - C 4 3.95 3.85 -50 100 Figure 18. RISE TIME, xVCC vs LOAD CAPACITANCE FALL TIME, xVCC vs LOAD CAPACITANCE 1.2 2.5 1 2 0.8 0.6 0.4 0 0.1 -20 10 40 70 TJ - Junction Temperature - C Figure 17. xVCC = 5 V IO = 0.75 A TJ = 25C 0.2 1 10 100 CL - Load Capacitance - F Figure 19. 14 4.05 3.9 t f - Fall Time xVCC - ms t r - Rise Time, xVCC - ms 0.575 -50 xVPP = 12 V IO = 0.05 A CL = 10 F Submit Documentation Feedback 100 xVCC = 5 V IO = 0.75 A TJ = 25C 1.5 1 0.5 1000 0 0.1 1 10 100 CL - Load Capacitance - F 1000 Figure 20. Copyright (c) 2002-2008, Texas Instruments Incorporated Product Folder Link(s): TPS2220A TPS2223A TPS2224A TPS2226A TPS2220A, TPS2223A TPS2224A, TPS2226A www.ti.com SLVS428E - MAY 2002 - REVISED MSRCH 2008 RISE TIME, xVPP vs LOAD CAPACITANCE FALL TIME, xVPP vs LOAD CAPACITANCE 0.7 4 t f - Fall Time, xVPP - ms t r - Rise Time, xVPP - ms 0.6 4.5 xVPP = 12 V IO = 0.05 A TJ = 25C 0.5 0.4 0.3 0.2 xVPP = 12 V IO = 0.05 A TJ = 25C 3.5 3 2.5 2 1.5 1 0.1 0 0.1 0.5 1 CL - Load Capacitance - F 10 0 0.1 1 CL - Load Capacitance - F Figure 21. 10 Figure 22. TYPICAL CHARACTERISTICS Table of Graphs FIGURE Input current, xVCC = 3.3 V II Input current, xVCC = 5 V 23 vs Junction temperature Input current, xVPP = 12 V 25 Static drain-source on-state resistance, 3.3 V to xVCC switch rDS(on) Static drain-source on-state resistance, 5 V to xVCC switch 26 vs Junction temperature Static drain-source on-state resistance, 12 V to xVPP switch xVCC switch voltage drop, 5-V input 29 vs Load current 30 xVPP switch voltage drop, 12-V input 31 Short-circuit current limit, 3.3 V to xVCC IOS Short-circuit current limit, 5 V to xVCC 32 vs Junction temperature Short-circuit current limit, 12 V to xVPP Copyright (c) 2002-2008, Texas Instruments Incorporated 27 28 xVCC switch voltage drop, 3.3-V input VO 24 33 34 Submit Documentation Feedback Product Folder Link(s): TPS2220A TPS2223A TPS2224A TPS2226A 15 TPS2220A, TPS2223A TPS2224A, TPS2226A www.ti.com SLVS428E - MAY 2002 - REVISED MSRCH 2008 INPUT CURRENT, xVCC = 3.3 V vs JUNCTION TEMPERATURE INPUT CURRENT, xVCC = 5 V vs JUNCTION TEMPERATURE 180 14 I I - Input Current, xVCC = 5 V - A I I - Input Current, xVCC = 3.3 V - A 160 140 120 100 80 60 40 12 10 8 6 4 2 20 0 -50 -20 10 40 70 TJ - Junction Temperature - C 0 -50 100 Figure 23. rDS(on) - Static Drain-Source On-State Resistance, 3.3 V to xVCC Switch - I I - Input Current, xVPP = 12 V - A 120 100 80 60 40 20 -20 10 40 70 TJ - Junction Temperature - C Figure 25. 16 Submit Documentation Feedback 100 Figure 24. INPUT CURRENT, xVPP = 12 V vs JUNCTION TEMPERATURE 0 -50 -20 10 40 70 TJ - Junction Temperature - C 100 STATIC DRAIN-SOURCE ON-STATE RESISTANCE, 3.3 V TO xVCC SWITCH vs JUNCTION TEMPERATURE 0.12 0.1 0.08 0.06 0.04 0.02 0 -50 -20 10 40 70 TJ - Junction Temperature - C 100 Figure 26. Copyright (c) 2002-2008, Texas Instruments Incorporated Product Folder Link(s): TPS2220A TPS2223A TPS2224A TPS2226A TPS2220A, TPS2223A TPS2224A, TPS2226A SLVS428E - MAY 2002 - REVISED MSRCH 2008 STATIC DRAIN-SOURCE ON-STATE RESISTANCE, 5 V TO xVCC SWITCH vs JUNCTION TEMPERATURE 0.14 rDS(on) - Static Drain-Source On-State Resistance, 12 V to xVPP Switch - rDS(on) - Static Drain-Source On-State Resistance, 5 V to xVCC Switch - www.ti.com 0.12 0.1 0.08 0.06 0.04 0.02 0 -50 -20 10 40 70 TJ - Junction Temperature - C 100 STATIC DRAIN-SOURCE ON-STATE RESISTANCE, 12 V TO xVPP SWITCH vs JUNCTION TEMPERATURE 3 2.5 2 1.5 1 0.5 0 -50 Figure 27. xVCC SWITCH VOLTAGE DROP, 3.3-V INPUT vs LOAD CURRENT 0.14 0.1 VO - xVCC Switch Voltage Drop, 5-V Input - V VO - xVCC Switch Voltage Drop, 3.3-V Input - V 100 xVCC SWITCH VOLTAGE DROP, 5-V INPUT vs LOAD CURRENT 0.12 TJ = 100C 0.08 TJ = 0C TJ = 25C 0.06 TJ = -40C 0.04 TJ = 85C 0.02 0 -20 10 40 70 TJ - Junction Temperature - C Figure 28. 0 0.2 0.4 0.6 IL - Load Current - A Figure 29. Copyright (c) 2002-2008, Texas Instruments Incorporated 0.8 1 0.12 TJ = 100C 0.1 TJ = 0C 0.08 TJ = 25C 0.06 TJ = -40C 0.04 TJ = 85C 0.02 0 0 0.2 0.4 0.6 IL - Load Current - A Figure 30. 0.8 Submit Documentation Feedback Product Folder Link(s): TPS2220A TPS2223A TPS2224A TPS2226A 1 17 TPS2220A, TPS2223A TPS2224A, TPS2226A www.ti.com SLVS428E - MAY 2002 - REVISED MSRCH 2008 xVPP SWITCH VOLTAGE DROP, 12-V INPUT vs LOAD CURRENT SHORT-CIRCUIT CURRENT LIMIT, 3.3 V TO xVCC vs JUNCTION TEMPERATURE I OS - Short-Circuit Current Limit, 3.3 V to xVCC - A VO - xVPP Switch Voltage Drop, 12-V Input - V 0.14 0.12 0.1 TJ = 100C 0.08 TJ = 0C TJ = 25C 0.06 0.04 TJ = -40C 0.02 0 TJ = 85C 0 0.01 0.02 0.03 IL - Load Current - A 0.04 0.05 1.385 1.38 1.375 1.37 1.365 1.36 1.355 -50 -20 10 40 70 TJ - Junction Temperature - C 100 Figure 32. SHORT-CIRCUIT CURRENT LIMIT, 5 V TO xVCC vs JUNCTION TEMPERATURE SHORT-CIRCUIT CURRENT LIMIT, 12 V TO xVPP vs JUNCTION TEMPERATURE I OS - Short-Circuit Current Limit, 12 V to xVPP - A I OS - Short-Circuit Current Limit, 5 V to xVCC - A 1.39 Figure 31. 1.435 1.43 1.425 1.42 1.415 1.41 1.405 1.4 1.395 1.39 1.385 -50 -20 10 40 70 TJ - Junction Temperature - C Figure 33. 18 1.395 Submit Documentation Feedback 100 0.208 0.206 0.204 0.202 xVPP = 12 V 0.2 0.198 0.196 0.194 0.192 0.19 -50 -20 10 40 70 100 TJ - Junction Temperature - C Figure 34. Copyright (c) 2002-2008, Texas Instruments Incorporated Product Folder Link(s): TPS2220A TPS2223A TPS2224A TPS2226A TPS2220A, TPS2223A TPS2224A, TPS2226A www.ti.com SLVS428E - MAY 2002 - REVISED MSRCH 2008 APPLICATION INFORMATION OVERVIEW PC Cards were initially introduced as a means to add flash memory to portable computers. The idea of add-in cards quickly took hold, and modems, wireless LANs, global positioning satellite system (GPS), multimedia, and hard-disk versions were soon available. As the number of PC Card applications grew, the engineering community quickly recognized the need for a standard to ensure compatibility across platforms. Therefore, the PCMCIA (Personal Computer Memory Card International Association) was established, comprising members from leading computer, software, PC Card, and semiconductor manufacturers. One key goal was to realize the plug-and-play concept, so that cards and hosts from different vendors would be transparently compatible. PC CARD POWER SPECIFICATION System compatibility also means power compatibility. The most current set of specifications (PC Card Standard) set forth by the PCMCIA committee states that power is to be transferred between the host and the card through eight of the 68 terminals of the PC Card connector. This power interface consists of two VCC, two Vpp, and four ground terminals. Multiple VCC and ground terminals minimize connector-terminal and line resistance. The two Vpp terminals were originally specified as separate signals, but are normally tied together in the host to form a single node to minimize voltage losses. Card primary power is supplied through the VCC terminals; flash-memory programming and erase voltage is supplied through the Vpp terminals. Cardbus cards of today typically do not use 12 V, which is now more of an optional requirement in the host. DESIGNING FOR VOLTAGE REGULATION The current PCMCIA specification for output voltage regulation, VO(reg), of the 5-V output is 5% (250 mV). In a typical PC power-system design, the power supply has an output-voltage regulation, VPS(reg), of 2% (100 mV). Also, a voltage drop from the power supply to the PC Card results from resistive losses, VPCB, in the PCB traces and the PCMCIA connector. A typical design would limit the total of these resistive losses to less than 1% (50 mV) of the output voltage. Therefore, the allowable voltage drop, VDS, for the TPS2220A, TPS2223A, TPS2224A, and TPS2226A would be the PCMCIA voltage regulation less the power supply regulation and less the PCB and connector resistive drops: V +V -V -V DS O(reg) PS(reg) PCB Typically, this would leave 100 mV for the allowable voltage drop across the 5-V switch. The specification for output voltage regulation of the 3.3-V output is 300 mV; therefore, using the same equation by deducting the voltage drop percentages (2%) for power-supply regulation and PCB resistive loss (1%), the allowable voltage drop for the 3.3-V switch is 200 mV. The voltage drop is the output current multiplied by the switch resistance of the device. Therefore, the maximum output current, IO max, that can be delivered to the PC Card in regulation is the allowable voltage drop across the IC, divided by the output-switch resistance. V I max + r DS O DS(on) The xVCC outputs have been designed to deliver the peak and average currents defined by the PC Card specification within regulation over the operating temperature range. The xVPP outputs of the device have been designed to deliver 100 mA continuously. OVERCURRENT AND OVERTEMPERATURE PROTECTION PC Cards are inherently subject to damage that can result from mishandling. Host systems require protection against short-circuited cards that can lead to power-supply or PCB trace damage. Even extremely robust systems can undergo rapid battery discharge into a damaged PC Card, resulting in the sudden and unacceptable loss of system power. In comparison, the reliability of fused systems is poor because blown fuses require troubleshooting and repair, usually by the manufacturer. The TPS2220A, TPS2223A, TPS2224A, and TPS2226A take a two-pronged approach to overcurrent protection, which is designed to activate if an output is shorted or when an overcurrent condition is present when switches are powered up. First, instead of fuses, sense FETs monitor each of the xVCC and xVPP power outputs. Unlike Copyright (c) 2002-2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPS2220A TPS2223A TPS2224A TPS2226A 19 TPS2220A, TPS2223A TPS2224A, TPS2226A www.ti.com SLVS428E - MAY 2002 - REVISED MSRCH 2008 sense resistors or polyfuses, these FETs do not add to the series resistance of the switch; therefore, voltage and power losses are reduced. Overcurrent sensing is applied to each output separately. Excessive current generates an error signal that limits the output current of only the affected output, preventing damage to the host. Each xVCC output overcurrent limits from 1 A to 2.0 A, typically around 1.6 A; the xVPP outputs limit from 100 mA to 250 mA, typically around 200 mA. Second, when an overcurrent condition is detected, the TPS2220A, TPS2223A, TPS2224A, and TPS2226A assert an active low OC signal that can be monitored by the microprocessor or controller to initiate diagnostics and/or send the user a warning message. If an overcurrent condition persists, causing the IC to exceed its maximum junction temperature, thermal-protection circuitry activates, shutting down all power outputs until the device cools to within a safe operating region, which is ensured by a thermal shutdown hysteresis. Thermal limiting prevents destruction of the IC from overheating beyond the package power-dissipation ratings. During power up, the devices control the rise times of the xVCC and xVPP outputs and limit the inrush current into a large load capacitance, faulty card, or connector. 12-V SUPPLY NOT REQUIRED Some PC Card switches use the externally supplied 12 V to power gate drive and other chip functions, which requires that power be present at all times. The TPS2220A, TPS2224A and TPS2226A offer considerable power savings by using an internal charge pump to generate the required higher gate drive voltages from the 3.3-V input. Therefore, the external 12-V supply can be disabled except when needed by the PC Card in the slot, thereby extending battery lifetime. A special feature in the 12-V circuitry actually helps to reduce the supply current demanded from the 3.3-V input. When 12 V is supplied and requested at the VPP output, a voltage selection circuit draws the charge-pump drive current for the 12-V FETs from the 12-V input. This selection is automatic and effectively reduces demand fluctuations on the normal 3.3-V VCC rail. For proper operation of this feature, a minimum 3.3-V input capacitance of 4.7 F is recommended, and a minimum 12-V input ramp-up rate of 12 V/50 ms (240 V/s) is required. Additional power savings are realized during a software shutdown in which quiescent current drops to a maximum of 1 A. VOLTAGE-TRANSITIONING REQUIREMENT PC Cards, like portables, are migrating from 5 V to 3.3 V to minimize power consumption, optimize board space, and increase logic speeds. The TPS2220A, TPS2223A, TPS2224A, and TPS2226A meet all combinations of power delivery as currently defined in the PCMCIA standard. The latest protocol accommodates mixed 3.3-V/5-V systems by first powering the card with 5 V, then polling it to determine its 3.3-V compatibility. The PCMCIA specification requires that the capacitors on 3.3-V-compatible cards be discharged to below 0.8 V before applying 3.3-V power. This action ensures that sensitive 3.3-V circuitry is not subjected to any residual 5-V charge and functions as a power reset. PC Card specification requires that VCC be discharged within 100 ms. PC Card resistance cannot be relied on to provide a discharge path for voltages stored on PC Card capacitance because of possible high-impedance isolation by power-management schemes. The devices include discharge transistors on all xVCC and xVPP outputs to meet the specification requirement. SHUTDOWN MODE In the shutdown mode, which can be controlled by SHDN or bit D8 of the input serial DATA word, each of the xVCC and xVPP outputs is forced to a high-impedance state. In this mode, the chip quiescent current is reduced to 1 A or less to conserve battery power. POWER-SUPPLY CONSIDERATIONS These switches have multiple pins for each 3.3-V (except for TPS2220A) and 5-V power input and for the switched xVCC outputs. Any individual pin can conduct the rated input or output current. Unless all pins are connected in parallel, the series resistance is higher than that specified, resulting in increased voltage drops and power loss. It is recommended that all input and output power pins be paralleled for optimum operation. To increase the noise immunity of the TPS2220A, TPS2223A, TPS2224A, and TPS2226A, the power-supply inputs should be bypassed with at least a 4.7-F electrolytic or tantalum capacitor paralleled by a 0.047-F to 20 Submit Documentation Feedback Copyright (c) 2002-2008, Texas Instruments Incorporated Product Folder Link(s): TPS2220A TPS2223A TPS2224A TPS2226A TPS2220A, TPS2223A TPS2224A, TPS2226A www.ti.com SLVS428E - MAY 2002 - REVISED MSRCH 2008 0.1-F ceramic capacitor. It is strongly recommended that the switched outputs be bypassed with a 0.1-F (or larger) ceramic capacitor; doing so improves the immunity of the IC to electrostatic discharge (ESD). Care should be taken to minimize the inductance of PCB traces between the devices and the load. High switching currents can produce large negative voltage transients, which forward biases substrate diodes, resulting in unpredictable performance. Similarly, no pin should be taken below -0.3 V. RESET INPUT To ensure that cards are in a known state after power brownouts or system initialization, the PC Cards should be reset at the same time as the host by applying low-impedance paths from xVCC and xVPP terminals to ground. A low-impedance output state allows discharging of residual voltage remaining on PC Card filter capacitance, permitting the system (host and PC Cards) to be powered up concurrently. The active low RESET input closes internal ground switches S1, S4, S7, and S11 with all other switches left open. The TPS2220A, TPS2223A, TPS2224A, and TPS2226A remain in the low-impedance output state until the signal is de-asserted and further data is clocked in and latched. The input serial data cannot be latched during reset mode. RESET is provided for direct compatibility with systems that use an active-low reset voltage supervisor. The RESET pin has an internal 150-k pullup resistor. CALCULATING JUNCTION TEMPERATURE The switch resistance, rDS(on), is dependent on the junction temperature, TJ, of the die. The junction temperature is dependent on both rDS(on) and the current through the switch. To calculate TJ, first find rDS(on) from Figure 26 through Figure 28, using an initial temperature estimate about 30C above ambient. Then, calculate the power dissipation for each switch, using the formula: P +r I2 D DS(on) Next, sum the power dissipation of all switches and calculate the junction temperature: T + P R )T J D qJA A where: RJA is the inverse of the derating factor given in the dissipation rating table. Compare the calculated junction temperature with the initial temperature estimate. If the temperatures are not within a few degrees of each other, recalculate using the calculated temperature as the initial estimate. LOGIC INPUTS AND OUTPUTS The serial interface consists of the DATA, CLOCK, and LATCH leads. The data is clocked in on the positive edge of the clock (see Figure 2). The 11-bit (D0-D10) serial data word is loaded during the positive edge of the latch signal. The positive edge of the latch signal should occur before the next positive edge of the clock occurs. The serial interface of the device is compatible with serial-interface PCMCIA controllers. An overcurrent output (OC) is provided to indicate an overcurrent or overtemperature condition in any of the xVCC and xVPP outputs as previously discussed. Copyright (c) 2002-2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPS2220A TPS2223A TPS2224A TPS2226A 21 PACKAGE OPTION ADDENDUM www.ti.com 30-Jul-2011 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp (3) TPS2220ADBR ACTIVE SSOP DB 24 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS2220ADBRG4 ACTIVE SSOP DB 24 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS2220APWP ACTIVE HTSSOP PWP 24 60 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TPS2220APWPG4 ACTIVE HTSSOP PWP 24 60 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TPS2220APWPR ACTIVE HTSSOP PWP 24 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TPS2220APWPRG4 ACTIVE HTSSOP PWP 24 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TPS2223ADB ACTIVE SSOP DB 24 60 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS2223ADBG4 ACTIVE SSOP DB 24 60 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS2223ADBR ACTIVE SSOP DB 24 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS2223ADBRG4 ACTIVE SSOP DB 24 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS2223APWP ACTIVE HTSSOP PWP 24 60 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TPS2223APWPG4 ACTIVE HTSSOP PWP 24 60 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TPS2223APWPR ACTIVE HTSSOP PWP 24 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TPS2223APWPRG4 ACTIVE HTSSOP PWP 24 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TPS2224ADB ACTIVE SSOP DB 24 60 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS2224ADBG4 ACTIVE SSOP DB 24 60 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS2224ADBR ACTIVE SSOP DB 24 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Addendum-Page 1 Samples (Requires Login) PACKAGE OPTION ADDENDUM www.ti.com Orderable Device 30-Jul-2011 Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp (3) TPS2224ADBRG4 ACTIVE SSOP DB 24 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS2224APWP ACTIVE HTSSOP PWP 24 60 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TPS2224APWPG4 ACTIVE HTSSOP PWP 24 60 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TPS2224APWPR ACTIVE HTSSOP PWP 24 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TPS2224APWPRG4 ACTIVE HTSSOP PWP 24 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TPS2226ADB ACTIVE SSOP DB 30 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS2226ADBG4 ACTIVE SSOP DB 30 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS2226ADBR ACTIVE SSOP DB 30 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS2226ADBRG4 ACTIVE SSOP DB 30 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Samples (Requires Login) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Addendum-Page 2 PACKAGE OPTION ADDENDUM www.ti.com 30-Jul-2011 Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 3 PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 12.0 16.0 Q1 TPS2220ADBR SSOP DB 24 2000 330.0 16.4 8.2 8.8 2.5 TPS2220APWPR HTSSOP PWP 24 2000 330.0 16.4 6.95 8.3 1.6 8.0 16.0 Q1 TPS2223ADBR SSOP DB 24 2000 330.0 16.4 8.2 8.8 2.5 12.0 16.0 Q1 TPS2223APWPR HTSSOP PWP 24 2000 330.0 16.4 6.95 8.3 1.6 8.0 16.0 Q1 TPS2224ADBR SSOP DB 24 2000 330.0 16.4 8.2 8.8 2.5 12.0 16.0 Q1 TPS2224APWPR HTSSOP PWP 24 2000 330.0 16.4 6.95 8.3 1.6 8.0 16.0 Q1 TPS2226ADBR SSOP DB 30 2000 330.0 16.4 8.2 10.5 2.5 12.0 16.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS2220ADBR SSOP DB 24 2000 367.0 367.0 38.0 TPS2220APWPR HTSSOP PWP 24 2000 367.0 367.0 38.0 TPS2223ADBR SSOP DB 24 2000 367.0 367.0 38.0 TPS2223APWPR HTSSOP PWP 24 2000 367.0 367.0 38.0 TPS2224ADBR SSOP DB 24 2000 367.0 367.0 38.0 TPS2224APWPR HTSSOP PWP 24 2000 367.0 367.0 38.0 TPS2226ADBR SSOP DB 30 2000 367.0 367.0 38.0 Pack Materials-Page 2 MECHANICAL DATA MSSO002E - JANUARY 1995 - REVISED DECEMBER 2001 DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE 28 PINS SHOWN 0,38 0,22 0,65 28 0,15 M 15 0,25 0,09 8,20 7,40 5,60 5,00 Gage Plane 1 14 0,25 A 0-8 0,95 0,55 Seating Plane 2,00 MAX 0,10 0,05 MIN PINS ** 14 16 20 24 28 30 38 A MAX 6,50 6,50 7,50 8,50 10,50 10,50 12,90 A MIN 5,90 5,90 6,90 7,90 9,90 9,90 12,30 DIM 4040065 /E 12/01 NOTES: A. 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