SN54ALVTH16373, SN74ALVTH16373 2.5-V/3.3-V 16-BIT TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS SCES067F - JUNE 1996 - REVISED JANUARY 1999 D D D D D D D D D D D D D State-of-the-Art Advanced BiCMOS Technology (ABT) Widebus Design for 2.5-V and 3.3-V Operation and Low Static Power Dissipation Support Mixed-Mode Signal Operation (5-V Input and Output Voltages With 2.3-V to 3.6-V VCC ) Typical VOLP (Output Ground Bounce) < 0.8 V at VCC = 3.3 V, TA = 25C High Drive (-24/24 mA at 2.5-V and -32/64 mA at 3.3-V VCC) Power Off Disables Outputs, Permitting Live Insertion High-Impedance State During Power Up and Power Down Prevents Driver Conflict Uses Bus Hold on Data Inputs in Place of External Pullup/Pulldown Resistors to Prevent the Bus From Floating Auto3-State Eliminates Bus Current Loading When Output Exceeds VCC + 0.5 V Latch-Up Performance Exceeds 250 mA Per JESD 17 ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model; and Exceeds 1000 V Using Charged-Device Model, Robotic Method Flow-Through Architecture Facilitates Printed Circuit Board Layout Distributed VCC and GND Pin Configuration Minimizes High-Speed Switching Noise Package Options Include Plastic Shrink Small-Outline (DL), Thin Shrink Small-Outline (DGG), Thin Very Small-Outline (DGV) Packages, and 380-mil Fine-Pitch Ceramic Flat (WD) Package SN54ALVTH16373 . . . WD PACKAGE SN74ALVTH16373 . . . DGG, DGV, OR DL PACKAGE (TOP VIEW) 1OE 1Q1 1Q2 GND 1Q3 1Q4 VCC 1Q5 1Q6 GND 1Q7 1Q8 2Q1 2Q2 GND 2Q3 2Q4 VCC 2Q5 2Q6 GND 2Q7 2Q8 2OE 1 48 2 47 3 46 4 45 5 44 6 43 7 42 8 41 9 40 10 39 11 38 12 37 13 36 14 35 15 34 16 33 17 32 18 31 19 30 20 29 21 28 22 27 23 26 24 25 1LE 1D1 1D2 GND 1D3 1D4 VCC 1D5 1D6 GND 1D7 1D8 2D1 2D2 GND 2D3 2D4 VCC 2D5 2D6 GND 2D7 2D8 2LE description The 'ALVTH16373 devices are 16-bit transparent D-type latches with 3-state outputs designed for 2.5-V or 3.3-V VCC operation, but with the capability to provide a TTL interface to a 5-V system environment. These devices are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. These devices can be used as two 8-bit latches or one 16-bit latch. When the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs are latched at the levels set up at the D inputs. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Widebus is a trademark of Texas Instruments Incorporated. Copyright 1999, Texas Instruments Incorporated UNLESS OTHERWISE NOTED this document contains PRODUCTION DATA information current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 1 SN54ALVTH16373, SN74ALVTH16373 2.5-V/3.3-V 16-BIT TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS SCES067F - JUNE 1996 - REVISED JANUARY 1999 description (continued) A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and the increased drive provide the capability to drive bus lines without interface or pullup components. OE does not affect internal operations of the latch. Old data can be retained or new data can be entered while the outputs are in the high-impedance state. Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level. When VCC is between 0 and 1.2 V, the device is in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 1.2 V, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. The SN54ALVTH16373 is characterized for operation over the full military temperature range of -55C to 125C. The SN74ALVTH16373 is characterized for operation from -40C to 85C. FUNCTION TABLE (each 8-bit section) INPUTS 2 OE LE D OUTPUT Q L H H H L H L L L L X Q0 H X X Z POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 SN54ALVTH16373, SN74ALVTH16373 2.5-V/3.3-V 16-BIT TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS SCES067F - JUNE 1996 - REVISED JANUARY 1999 logic diagram (positive logic) 1OE 1LE 1D1 1 2OE 48 2LE C1 47 2 1D 1Q1 24 25 C1 2D1 36 13 1D 2Q1 To Seven Other Channels To Seven Other Channels absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 4.6 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 7 V Voltage range applied to any output in the high-impedance or power-off state, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 7 V Voltage range applied to any output in the high state, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . -0.5 V to 7 V Output current in the low state, IO: SN54ALVTH16373 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 mA SN74ALVTH16373 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA Output current in the high state, IO: SN54ALVTH16373 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -48 mA SN74ALVTH16373 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -64 mA Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -50 mA Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -50 mA Package thermal impedance, JA (see Note 2): DGG package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89C/W DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93C/W DL package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65C to 150C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 51. recommended operating conditions, VCC = 2.5 V 0.2 V (see Note 3) SN54ALVTH16373 SN74ALVTH16373 MIN MAX MIN 2.7 2.3 VCC VIH Supply voltage 2.3 High-level input voltage 1.7 VIL VI Low-level input voltage IOH High-level output current Low-level output current IOL TYP TYP 2.7 1.7 0 Low-level output current; current duty cycle 50%; f 1 kHz t/v Input transition rise or fall rate t/VCC TA Power-up ramp rate 200 Operating free-air temperature -55 Outputs enabled VCC UNIT V V 0.7 Input voltage MAX 0.7 V 5.5 V -6 -8 mA 6 8 18 24 5.5 0 10 VCC 10 -40 ns/V s/V 200 125 mA 85 C NOTE 3: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 3 SN54ALVTH16373, SN74ALVTH16373 2.5-V/3.3-V 16-BIT TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS SCES067F - JUNE 1996 - REVISED JANUARY 1999 recommended operating conditions, VCC = 3.3 V 0.3 V (see Note 3) SN54ALVTH16373 SN74ALVTH16373 MIN MAX MIN 3.6 3 VCC VIH Supply voltage 3 High-level input voltage 2 VIL VI Low-level input voltage IOH High-level output current IOL t/v TYP TYP 3.6 2 0 5.5 0.8 0 V VCC V 5.5 V -24 -32 mA Low-level output current 24 32 Low-level output current; current duty cycle 50%; f 1 kHz 48 64 Input transition rise or fall rate 10 10 Outputs enabled VCC UNIT V 0.8 Input voltage MAX mA ns/V t/VCC Power-up ramp rate 200 200 s/V TA Operating free-air temperature -55 125 -40 85 C NOTE 3: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. 4 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 SN54ALVTH16373, SN74ALVTH16373 2.5-V/3.3-V 16-BIT TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS SCES067F - JUNE 1996 - REVISED JANUARY 1999 electrical characteristics over recommended operating free-air temperature range, VCC = 2.5 V 0.2 V (unless otherwise noted) PARAMETER VIK VOH VCC = 2.3 V, VCC = 2.3 V to 2.7 V, II = -18 mA IOH = -100 A 3V VCC = 2 2.3 IOH = -6 mA IOH = -8 mA VCC = 2.3 V to 2.7 V, VOL VCC = 2 2.3 3V Control inputs VCC = 2.7 V, VCC = 0 or 2.7 V, II Data inputs Ioff IBHL IBHH SN54ALVTH16373 MIN TYP MAX TEST CONDITIONS VCC = 2.7 V SN74ALVTH16373 MIN TYP MAX -1.2 VCC-0.2 1.8 -1.2 V 1.8 IOL = 100 A IOL = 6 mA 0.2 0.2 0.4 IOL = 8 mA IOL = 18 mA 0.4 IOL = 24 mA VI = VCC or GND 0.5 VI = 5.5 V VI = 5.5 V VI = VCC VI = 0 1 1 10 10 10 10 1 1 -5 -5 100 VCC = 2.3 V, VCC = 2.7 V, VI = 1.7 V VI = 0 to VCC IEX|| VCC = 2.7 V, VCC = 2.3 V, VI = 0 to VCC VO = 5.5 V IOZ(PU/PD)k VCC 1.2 V, VO = 0.5 V to VCC, VI = GND or VCC, OE = don't care IOZH VCC = 2 2.7 7V IOZL 7V VCC = 2 2.7 Outputs high ICC VCC = 2.7 V, IO = 0, VI = VCC or GND Outputs disabled VCC = 2.5 V, VCC = 2.5 V, VI = 2.5 V or 0 VO = 2.5 V or 0 3.5 3.5 6 6 Co V 0.5 VI or VO = 0 to 4.5 V VI = 0.7 V Ci V VCC-0.2 VCC = 0, VCC = 2.3 V, IBHLO IBHHO# UNIT A A 115 115 A -10 -10 A 300 300 A -300 -300 A 125 125 A 100 100 A VO = 2.3 V, VI = 0.7 V or 1.7 V 5 5 A VO = 0.5 V, VI = 0.7 V or 1.7 V 5 -5 5 -5 A Outputs low 0.04 0.1 0.04 0.1 2.3 0.04 4.5 2.3 4.5 0.1 0.04 0.1 mA pF pF All typical values are at VCC = 2.5 V, TA = 25C. The bus-hold circuit can sink at least the minimum low sustaining current at VIL max. IBHL should be measured after lowering VIN to GND and then raising it to VIL max. The bus-hold circuit can source at least the minimum high sustaining current at VIH min. IBHH should be measured after raising VIN to VCC and then lowering it to VIH min. An external driver must source at least IBHLO to switch this node from low to high. # An external driver must sink at least IBHHO to switch this node from high to low. || Current into an output in the high state when VO > VCC k High-impedance state during power up or power down PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 5 SN54ALVTH16373, SN74ALVTH16373 2.5-V/3.3-V 16-BIT TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS SCES067F - JUNE 1996 - REVISED JANUARY 1999 electrical characteristics over recommended operating free-air temperature range, VCC = 3.3 V 0.3 V (unless otherwise noted) PARAMETER VIK VOH VCC = 3 V, VCC = 3 V to 3.6 V, II = -18 mA IOH = -100 A VCC = 3 V IOH = -24 mA IOH = -32 mA VCC = 3 V to 3.6 V, VOL VCC = 3 V Control inputs Ioff IBHL IBHH IBHLO IBHHO# IEX|| 2 IOL = 100 A IOL = 16 mA 0.2 IOL = 24 mA IOL = 32 mA 0.5 IOL = 48 mA IOL = 64 mA 0.55 0.2 0.4 0.5 V 0.55 1 1 10 10 10 10 1 1 VCC = 3.6 V VI = 0 VI or VO = 0 to 4.5 V -5 VCC = 3.6 V, VCC = 3 V, V V VI = 5.5 V VI = VCC VCC = 3 V, VCC = 3.6 V, -1.2 UNIT VCC-0.2 VI = VCC or GND VI = 5.5 V VCC = 0, VCC = 3 V, SN74ALVTH16373 MIN TYP MAX -1.2 VCC-0.2 2 VCC = 3.6 V, VCC = 0 or 3.6 V, II Data inputs SN54ALVTH16373 MIN TYP MAX TEST CONDITIONS VI = 0.8 V VI = 2 V VI = 0 to VCC VI = 0 to VCC A -5 100 A 75 75 A -75 -75 A 500 500 A -500 A -500 125 125 A 100 100 A IOZ(PU/PD)k VO = 5.5 V VCC 1.2 V, VO = 0.5 V to VCC, VI = GND or VCC, OE = don't care IOZH VCC = 3 3.6 6V VO = 3 V, VI = 0.8 V or 2 V 5 5 A IOZL VCC = 3 3.6 6V VO = 0.5 V, VI = 0.8 V or 2 V -5 5 -5 5 A ICC VCC = 3.6 V, IO = 0, VI = VCC or GND Outputs high 0.07 0.1 0.07 Outputs low 3.2 5.5 3.2 5 0.07 0.1 0.07 0.1 Outputs disabled ICCh VCC = 3 V to 3.6 V, One input at VCC - 0.6 V, Other inputs at VCC or GND Ci VCC = 3.3 V, VCC = 3.3 V, Co VI = 3.3 V or 0 VO = 3.3 V or 0 0.4 0.1 0.4 3.5 3.5 6 6 mA mA pF pF All typical values are at VCC = 3.3 V, TA = 25C. The bus-hold circuit can sink at least the minimum low sustaining current at VIL max. IBHL should be measured after lowering VIN to GND and then raising it to VIL max. The bus-hold circuit can source at least the minimum high sustaining current at VIH min. IBHH should be measured after raising VIN to VCC and then lowering it to VIH min. An external driver must source at least IBHLO to switch this node from low to high. # An external driver must sink at least IBHHO to switch this node from high to low. || Current into an output in the high state when VO > VCC k High-impedance state during power up or power down h This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND. PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. 6 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 SN54ALVTH16373, SN74ALVTH16373 2.5-V/3.3-V 16-BIT TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS SCES067F - JUNE 1996 - REVISED JANUARY 1999 timing requirements over recommended operating free-air temperature range, VCC = 2.5 V 0.2 V (unless otherwise noted) (see Figure 1) SN54ALVTH16373 MIN tw Pulse duration, LE high tsu Setup time, time data before LE th Hold time, time data after LE MAX SN74ALVTH16373 MIN 1.5 1.5 Data high 1.1 1 Data low 1.6 1.5 1 0.9 1.6 1.5 Data high Data low MAX UNIT ns ns ns timing requirements over recommended operating free-air temperature range, VCC = 3.3 V 0.3 V (unless otherwise noted) (see Figure 2) SN54ALVTH16373 MIN tw Pulse duration, LE high Data high tsu Setup time, time data before LE th Hold time, time data after LE Data low Data high Data low MAX SN74ALVTH16373 MIN 1.5 1.5 1.5 1.4 1 0.9 1 0.9 1.5 1.4 MAX UNIT ns ns ns switching characteristics over recommended operating free-air temperature range, CL = 30 pF, VCC = 2.5 V 0.2 V (unless otherwise noted) (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) tPLH tPHL D Q tPLH tPHL LE Q tPZH tPZL OE Q OE Q tPHZ tPLZ SN54ALVTH16373 SN74ALVTH16373 MIN MAX MIN MAX 1 3.4 1 3.3 1 4.3 1 4.2 1.4 3.9 1.5 3.8 1.4 4.6 1.5 4.5 1.7 4.4 1.8 4.3 1.4 4.1 1.5 4 1.4 4.7 1.5 4.6 1 3.7 1 3.6 UNIT ns ns ns ns switching characteristics over recommended operating free-air temperature range, CL = 50 pF, VCC = 3.3 V 0.3 V (unless otherwise noted) (see Figure 2) PARAMETER FROM (INPUT) TO (OUTPUT) tPLH tPHL D Q tPLH tPHL LE Q tPZH tPZL OE Q OE Q tPHZ tPLZ SN54ALVTH16373 SN74ALVTH16373 MIN MAX MIN MAX 1 3.2 1 3.1 1 3.4 1 3.3 1 3.4 1 3.3 1 3.6 1 3.5 1.3 4.1 1.4 4 1 3.5 1 3.4 1.4 5 1.5 4.9 1.4 4.6 1.5 4.5 UNIT ns ns ns ns PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 7 SN54ALVTH16373, SN74ALVTH16373 2.5-V/3.3-V 16-BIT TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS SCES067F - JUNE 1996 - REVISED JANUARY 1999 PARAMETER MEASUREMENT INFORMATION VCC = 2.5 V 0.2 V 2 x VCC S1 500 From Output Under Test Open GND CL = 30 pF (see Note A) 500 TEST S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open 2 x VCC GND LOAD CIRCUIT tw VCC Timing Input VCC/2 VCC/2 VCC/2 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VCC/2 VCC/2 0V tPLH Output Control (low-level enabling) tPLZ VCC VCC/2 VCC/2 VOL Output Waveform 2 S1 at GND (see Note B) VOL + 0.15 V VOL tPHZ tPZH VOH VCC/2 0V Output Waveform 1 S1 at 2 x VCC (see Note B) tPHL VCC/2 VCC VCC/2 tPZL VCC Input VOLTAGE WAVEFORMS PULSE DURATION th VCC Data Input VCC/2 0V 0V tsu Output VCC VCC/2 Input VCC/2 VOH VOH - 0.15 V 0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50 , tr 2 ns, tf 2 ns. D. The outputs are measured one at a time with one transition per measurement. Figure 1. Load Circuit and Voltage Waveforms 8 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 SN54ALVTH16373, SN74ALVTH16373 2.5-V/3.3-V 16-BIT TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS SCES067F - JUNE 1996 - REVISED JANUARY 1999 PARAMETER MEASUREMENT INFORMATION VCC = 3.3 V 0.3 V 6V 500 From Output Under Test S1 Open GND CL = 50 pF (see Note A) 500 TEST S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open 6V GND LOAD CIRCUIT tw 3V 3V Timing Input 1.5 V VOLTAGE WAVEFORMS PULSE DURATION th 3V 1.5 V 3V 1.5 V 0V 0V Output Output Waveform 1 S1 at 6 V (see Note B) 3V 1.5 V 1.5 V VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS Output Waveform 2 S1 at GND (see Note B) VOL + 0.3 V VOL tPHZ tPZH tPHL VOH 1.5 V tPLZ tPZL 1.5 V tPLH 1.5 V 0V 3V 1.5 V 1.5 V Output Control VOLTAGE WAVEFORMS SETUP AND HOLD TIMES Input 1.5 V 0V 0V tsu Data Input 1.5 V Input 1.5 V VOH VOH - 0.3 V 0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform22 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50 , tr 2.5 ns, tf 2.5 ns. D. The outputs are measured one at a time with one transition per measurement. Figure 2. Load Circuit and Voltage Waveforms POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 9 PACKAGE OPTION ADDENDUM www.ti.com 3-May-2012 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp ACTIVE SSOP DL 48 25 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 74ALVTH16373DLRG4 ACTIVE SSOP DL 48 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 74ALVTH16373GRE4 ACTIVE TSSOP DGG 48 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 74ALVTH16373GRG4 ACTIVE TSSOP DGG 48 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 74ALVTH16373VRE4 ACTIVE TVSOP DGV 48 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 74ALVTH16373VRG4 ACTIVE TVSOP DGV 48 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 74ALVTH16373ZQLR ACTIVE BGA MICROSTAR JUNIOR ZQL 56 1000 Green (RoHS & no Sb/Br) SN74ALVTH16373DL ACTIVE SSOP DL 48 25 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74ALVTH16373DLR ACTIVE SSOP DL 48 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74ALVTH16373GR ACTIVE TSSOP DGG 48 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74ALVTH16373KR LIFEBUY BGA MICROSTAR JUNIOR GQL 56 1000 TBD SN74ALVTH16373VR ACTIVE TVSOP DGV 48 2000 Green (RoHS & no Sb/Br) (1) SNPB Level-1-260C-UNLIM Level-1-240C-UNLIM CU NIPDAU Level-1-260C-UNLIM The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. Addendum-Page 1 Samples (Requires Login) 74ALVTH16373DLG4 SNAGCU (3) PACKAGE OPTION ADDENDUM www.ti.com 3-May-2012 (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. 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Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device 74ALVTH16373ZQLR Package Package Pins Type Drawing Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant ZQL 56 1000 330.0 16.4 4.8 7.3 1.5 8.0 16.0 Q1 SSOP DL 48 1000 330.0 32.4 11.35 16.2 3.1 16.0 32.0 Q1 SN74ALVTH16373GR TSSOP DGG 48 2000 330.0 24.4 8.6 15.8 1.8 12.0 24.0 Q1 SN74ALVTH16373KR BGA MI CROSTA R JUNI OR GQL 56 1000 330.0 16.4 4.8 7.3 1.45 8.0 16.0 Q1 SN74ALVTH16373VR TVSOP DGV 48 2000 330.0 16.4 7.1 10.2 1.6 12.0 16.0 Q1 SN74ALVTH16373DLR BGA MI CROSTA R JUNI OR SPQ Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) 74ALVTH16373ZQLR BGA MICROSTAR JUNIOR ZQL 56 1000 333.2 345.9 28.6 SN74ALVTH16373DLR SSOP DL 48 1000 367.0 367.0 55.0 SN74ALVTH16373GR TSSOP DGG 48 2000 367.0 367.0 45.0 SN74ALVTH16373KR BGA MICROSTAR JUNIOR GQL 56 1000 333.2 345.9 28.6 SN74ALVTH16373VR TVSOP DGV 48 2000 367.0 367.0 38.0 Pack Materials-Page 2 MECHANICAL DATA MPDS006C - FEBRUARY 1996 - REVISED AUGUST 2000 DGV (R-PDSO-G**) PLASTIC SMALL-OUTLINE 24 PINS SHOWN 0,40 0,23 0,13 24 13 0,07 M 0,16 NOM 4,50 4,30 6,60 6,20 Gage Plane 0,25 0-8 1 0,75 0,50 12 A Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,08 14 16 20 24 38 48 56 A MAX 3,70 3,70 5,10 5,10 7,90 9,80 11,40 A MIN 3,50 3,50 4,90 4,90 7,70 9,60 11,20 DIM 4073251/E 08/00 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side. Falls within JEDEC: 24/48 Pins - MO-153 14/16/20/56 Pins - MO-194 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 MECHANICAL DATA MSSO001C - JANUARY 1995 - REVISED DECEMBER 2001 DL (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 48 PINS SHOWN 0.025 (0,635) 0.0135 (0,343) 0.008 (0,203) 48 0.005 (0,13) M 25 0.010 (0,25) 0.005 (0,13) 0.299 (7,59) 0.291 (7,39) 0.420 (10,67) 0.395 (10,03) Gage Plane 0.010 (0,25) 1 0-8 24 0.040 (1,02) A 0.020 (0,51) Seating Plane 0.110 (2,79) MAX 0.004 (0,10) 0.008 (0,20) MIN PINS ** 28 48 56 A MAX 0.380 (9,65) 0.630 (16,00) 0.730 (18,54) A MIN 0.370 (9,40) 0.620 (15,75) 0.720 (18,29) DIM 4040048 / E 12/01 NOTES: A. B. C. D. All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15). Falls within JEDEC MO-118 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 MECHANICAL DATA MTSS003D - JANUARY 1995 - REVISED JANUARY 1998 DGG (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 48 PINS SHOWN 0,27 0,17 0,50 48 0,08 M 25 6,20 6,00 8,30 7,90 0,15 NOM Gage Plane 1 0,25 24 0- 8 A 0,75 0,50 Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,10 48 56 64 A MAX 12,60 14,10 17,10 A MIN 12,40 13,90 16,90 DIM 4040078 / F 12/97 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold protrusion not to exceed 0,15. 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