M48T201Y-70MH6TR - STMicroelectronics, Inc.

1/32March 2003

Rev. 3.0

M48T201Y

M48T201V

5.0 or 3.3V TIMEKEEPER® SUPERVISOR

FEATURES SUMMARY

■CONVERTS LOW POWER SRAM INTO

NVRAMs

■YEAR 2000 COMPLIA NT

■BATTERY LOW FLAG

■INTEGRATED REAL TIME CLOCK, POWER-

FAIL CONTROL CIRCUIT, BATT ERY and

CRYSTAL

■WATCHDOG T IME R

■CHOICE OF WRITE PROTECT VOLTAGES

(VPFD = Power-fail Deselect Voltage):

– M48T 201Y : VCC = 4.5 to 5.5V

4.1V ≤ VPFD ≤ 4.5V

– M48T 201V : VCC = 3.0 to 3.6V

2.7V ≤ VPFD ≤ 3.0V

■MI CR OPRO C ESSOR POWER- O N RES ET

(Valid even during battery back-up mode)

■PR O GRAMM A BLE A L A R M O U TPUT ACTIVE

IN THE BATTERY BACKED-UP MODE

■PACKAGING INCLUDES A 44-LEAD SOIC and

SNAPHAT® TOP (to be ordered separately)

■SOIC PAC KAG E PR OV IDES D IR ECT

CON NEC TION FOR A SNAPHAT® TOP

WHICH CONTAINS THE BATTERY and

CRYSTAL

Figu re 1. 44- pi n S OI C Package

SOH44 (MH)

SNAPHAT (SH)

Crystal/Battery

M48T201Y, M48T201V
2/32
TABLE OF CONT ENTS
DESCRIPTION  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Figure 2. Logic D iagram  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Table  1. Signal Names  .  . . . . . . . . . . . .  . . .  . . . . . . . . . .  . . .  . . . . . . . . . .  . . .  . . . . . . . . . .  . . . . . . . 4
Figure 3. SOIC Connect ions  . . . . . . . . . . . . . . . . . . . . . .  . . . . . .  . . . . . . . . . . . . .  . . .  . . . .  . . . . . . . 5
Figure 4. Hard ware Hookup  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
MAXIMU M RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Table 2. Absolute Maxim um Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Table  3. DC an d AC Measureme nt Conditions . . . . . . . .  . . .  . . . .  . . . . . .  . . .  . . . .  . . . . . .  . . . . . .  . 8
Figure 5. AC Testing Load  Circuit . . . . . .  . . . . . .  . . . . . .  . . . . . .  . . .  . . . .  . . . . . .  . . .  . . . .  . . . . . . . 8
Table  4. Capacitance. . . . .  . . . . .  . . . . . .  . . . . . . . . . . . .  . . .  . . . . . . . . . .  . . .  . . . . . . . . . .  . . . . . . . 8
Table 5. DC Chara cteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
OPERATION  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
A ddress Decod ing. . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . .  . . . . . . . . . . . . . 10
Table  6. Operating Modes. . . . .  . . . . . . . . . . . . . . . . . . . . . . . . .  . . .  . . . . . . . . . .  . . .  . . . . . . . . . . 10
READ Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 6. GCON Timing When  Switching Bet ween RTC and External  SRAM . . . . .  . . . . . .  . . . . . . 11
Figure 7. READ Cycle Timing: RTC and External RAM  Control Signals. . .  . . . . . .  . . . . . .  . . . . . . 12
Table 7. READ Mode AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
WRITE Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 8. WRITE  Cycle Timing: RTC & External RAM Control Signals. . .  . . . . . .  . . . . . . . . . . . . . 14
Table  8. WRIT E  Mode AC Characteristics  . . . . .  . . . . . .  . . . . . .  . . .  . . . .  . . . . . .  . . .  . . . .  . . . . . . 15
Data Re tention Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 6
Figure 9. Power Down/Up Mode AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table  9. Power Down/Up Mode AC Characteristics . . . .  . . . . . . . . . . . . . .  . . . . . . . . . . . . . .  . . . . 17
CLOCK OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
TIMEKEEPER® Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Reading  the Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Setting  the  Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Stopping a nd Starting the Oscillator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 10. TIMEKEEPER® Registe r Map  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Setting  the  Alarm Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 10. Alarm Interrupt Reset Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table  11. Alarm Repeat Modes. . .  . . . . .  . . . . . .  . . . . . . . . . . . .  . . .  . . . . . . . . . .  . . .  . . . . . . . . . . 19
Figure 11. Back-up Mode Alarm Waveform s. . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . 20

3/32
M48T201Y, M 48T201V
Watchdog Time r  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 0
Sq uare  Wave Outp ut . . . . . . . . . . . . . .  . . . . . . .  . . . . . . . . .  . . . . .  . . . . .  . . .  . . . . .  . . . . . . . . . . . 2 1
Table  12. Square Wave Output  Frequency.  . . . .  . . . . . . . . . . . .  . . .  . . . . . . . . . .  . . .  . . . . . . . . . . 21
Po wer-o n Reset .  . . . . . .  . . . . .  . . . . . .  . . .  . . . . . . . . . .  . . .  . . . . . . . . . .  . . .  . . . . . . . . . .  . . . . . . 22
R eset Inputs (RSTIN1 & RSTIN2) . . . . . . . . . . .  . . . . . . . . . . . . . .  . . . . . . . . . . . . . .  . . . .  . . . . . . 22
Figure 12. RSTIN1 and RST IN2 Timing Waveform s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 13. Reset AC Characteristics  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Calibratin g the Clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . 23
Battery Low Warning. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 4
Initial Power-on Defaults . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . 2 4
Table 14. Defa ult Values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 13. Crystal Accuracy Across Temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 14. Calibration  Waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 5
VCC Noise And Negative Going Transie nts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 15. Supply Voltage Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
PACKAGE MECHANICAL INFORMAT ION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 19. SNAPHAT® Battery Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

M48T201Y, M48T201V

4/32

DESCRIPTION

The M48T201Y/V are self-contai ned devices that

include a real time clock (RTC), programmable

alarms, a watchdog timer, and a square wave out-

put which provides contr ol of up to 512K x 8 of ex-

ternal low-power static RAM. Access to all RTC

functions and the external RAM is the same as

conventional bytewide SRAM. The 16 TIME-

KEEPER® registers offer year, month, date, day,

hour, minute, second, calibration, alarm, century,

watchdog, and square wave output data. External -

ly attached static RAMs are controlled by the

M48T201 Y/V via the GCON and ECON signals.

The 44-pin, 330mil SOIC provides sockets with

gold plated contacts at both ends for direct con-

nection to a separate SNAPHAT® housing con-

taining the battery and crystal. The unique design

allows the SNAPHAT battery package to be

mounted on top of the SOIC package after the

completion of the surface mount process.

Insertion of the SNAPHAT housing after reflow

prevents potential battery damage due to the high

temperatures required for device surface-mount-

ing. The SNAPHAT housing is keyed to prevent

reverse insertion. The SOIC and battery packages

are shipped separately in plastic anti-static tubes

or in Tape & Reel form. For the 44-lead SOIC, the

battery/crystal package (e.g., SNAPHAT) part

number is “M4Txx-BR12SH” (see Table 19 , page

30).

Caution: Do not place the SNAPHAT batter y/crys-

tal top in conductive foam as t his will dr ain the l i th-

ium but ton-cell battery.

Figure 2. Logic Diagram Tabl e 1. Signal Names

AI02240

A0-A18

WDI

DQ0-DQ7

VCC

M48T201Y

M48T201V

VSS

ECON

GCON

RSTIN2

RSTIN1

RST

IRQ/FT

VOUT

SQW

A0-A18 Address Inputs

DQ0-DQ7 Data Inputs / Outpu ts

RSTIN1 Reset 1 Input

RSTIN2 Reset 2 Input

RST Reset Output (Open Drain)

WDI Watchdog Input

EChip Enable Input

GOutput Enable Input

WWRITE Enable Input

ECON RAM Chip Enable Output

GCON RAM Enable Output

IRQ/FT Interrupt / Frequency Test Output

(Open Drain)

SQW Square Wave Output

VOUT Supply Voltage Output

VCC Supply Voltage

VSS Ground

NC Not Connected Internally

5/32

M48T201Y, M 48T201V

Figure 3. SOIC Connections

RST

WDI

A10

A11

DQ7

A17

IRQ/FT

DQ6

DQ1 DQ3

VSS

DQ4

A13

VOUT

A12

A14

VCC

AI02241

M48T201Y

M48T201V

2322

GCON

DQ0

A18

A16

SQW

A15

DQ2 21

DQ5

RSTIN2

RSTIN1

ECON

M48T201Y, M48T201V

6/32

Figure 4. Hardware Hookup

Note: 1. If the se cond chip enable pi n (E2) is unused, it shoul d be tied to V OUT.

AI00604

32,768 Hz

CRYSTAL

LITHIUM

CELL

A0-A18

DQ0-DQ7

VCC

WDI

RSTIN1

RSTIN2

VSS

E2(1)

VCC

VSS

A0-Axx

DQ0-DQ7

0.1µF

ECON

GCON

RST

IRQ/FT

SQW

M48T201Y/V

CMOS

SRAM

VOUT

7/32

M48T201Y, M 48T201V

MAX I MUM R A TI N G

Stressing the device ab ove t he rati ng l isted in t he

“Absolute Maximum Ratings” table may cause

permanent damage to the device. These are

stress ratings only and operation of the device at

these or any other conditions above those indicat-

ed in the Oper ating sections of this specification is

not impl ied. Exposure to Absol ute Max imum Ra t-

ing conditions for extended periods may affect de-

vice reliability. Refer also to the

STMicroelectronics SURE P rogram and oth er rel-

evant quality documents.

Table 2. Absolute Maximum Ratings

No te : 1. Reflow at pea k t emperature o f 2 15°C to 225°C f or < 60 seconds (to ta l thermal budget not to exce ed 1 80°C for between 90 t o 120

seconds).

CAUTION: Negati ve undershoots below –0.3V are n ot allowed on any pi n while in th e Batte ry Back-up mod e.

CAUTION: Do NOT wave solder SOI C to avoid d am aging SNAPHAT sock ets.

Symbol Parameter Value Unit

TAAmbient Operating Temperature Grade 1 0 to 70 °C

Grade 6 –40 to 85 °C

TSTG Storage Temperature SNAPHAT®–40 to 85 °C

SOIC –55 to 125 °C

TSLD(1) Lead Solder Temperature for 10 seconds 260 °C

VIO Input or Output Voltage –0.3 to VCC + 0.3 V

VCC Supply Voltage M48T201Y –0.3 to 7.0 V

M48T201V –0.3 to 4.6 V

IO(2) Output Current 20 mA

PDPower Dissipation 1 W

M48T201Y, M48T201V

8/32

DC AND AC PARAMETERS

This section summarizes the operating and mea-

surement conditions, as well as the DC and AC

characteristics of the device. The parameters in

the following DC and AC Characteristic tables are

derived from tests pe rformed unde r t he Measure-

ment Conditions listed i n the relevant tables. De-

signers should check that the operating conditions

in their projects match the measurement condi-

tions when using the quoted parameters.

Table 3. DC and AC Measurement Conditions

No te : O utput High Z is define d as the poi nt where data is no long er driv en.

Figure 5. AC Testing Load Circuit

Notes:Excluding open-drain out put pin; 50pF for M48T201V.

Table 4. Capacitance

No te : 1. Ef fectiv e capacitance m easured with powe r suppl y at 5V ; s a m pl ed only , not 100% tested.

2. At 25°C; f = 1 M Hz.

3. Outputs desele ct ed.

Parameter M48T201Y M48T201V Unit

VCC Supply Voltage 4.5 to 5.5 3.0 to 3.6 V

Ambient Operating Temperature Grade 1 0 to 70 0 to 70 °C

Grade 6 –40 to 85 –40 to 85 °C

Load Capacitance (CL)100 50 pF

Input Rise and Fall Times ≤ 5 ≤ 5ns

Input Pulse Voltages 0 to 3 0 to 3 V

Input and Output Timing Ref. Voltages 1.5 1.5 V

AI04764

CL = 100pF

CL includes JIG capacitance

645Ω

DEVICE

UNDER

TEST

1.75V

Symbol Parameter(1,2) Min Max Unit

CIN Input Capacitance 10 pF

COUT(3) Input/Output Capacitance 10 pF

9/32

M48T201Y, M 48T201V

Table 5. DC Characteristics

No te : 1. Valid fo r Ambien t Operatin g T em perature: TA = 0 to 70°C or –40 to 85° C; VCC = 4.5 t o 5. 5V or 3. 0 to 3.6V (except where noted).

2. RSTIN1 and RSTIN2 internally pulled-up to VCC through 100KΩ resistor. WDI int ernally pulled-down to VSS through 100KΩ resistor.

3. Outputs desele ct ed.

4. IBAT (OSC ON) = Industrial Temperature Range - Grade 6 devic e.

5. F or IRQ/FT & RST pins (Open Drain).

6. Conditioned outputs (ECON - GCON) can only sustain CMOS leakage currents in the battery back-up mode. Higher leakage currents

will reduce battery life.

7. External SRAM must matc h TIMEKEEPER SUPERVISOR chip VCC specification.

Sym Parameter Test Condition(1)

M48T201Y M48T201V

Unit–70 –85

Min Typ Max Min Typ Max

ILI(2) Input Leakage Current 0V ≤ VIN ≤ VCC ±1 ±1 µA

ILO(3) Output Leakage Current 0V ≤ VOUT ≤ VCC ±1 ±1 µA

ICC Supply Current Outputs open 8 15 4 10 mA

ICC1 Supply Current (S tandby)

TTL E = VIH 53mA

CC2 Supply Current (S tandby)

CMOS E = VCC –0.2 32mA

BAT

Battery Current OSC ON

VCC = 0V

575 800 575 800 nA

Battery Current OSC

ON(4) 950 1250 950 1250 nA

Battery Current OSC

OFF 100 100 nA

VIL Input Low Voltage –0.3 0.8 –0.3 0.8 V

VIH Input High Voltage 2.2 VCC +

0.3 2.0 VCC +

0.3 V

VOL

Output Low Voltage IOL = 2.1mA 0.4 0.4 V

Output Low Voltage

(open drain)(5) IOL = 10mA 0.4 0.4 V

VOH Output High Voltage IOH = –1.0mA 2.4 2.4 V

VOHB(6) VOH Battery Back-up IOUT2 = –1.0µA 2.0 3.6 2.0 3.6 V

IOUT1(7) VOUT Current (Active) VOUT1 > VCC –0.3 100 70 mA

IOUT2 VOUT Current (Battery

Back-up) VOUT2 > VBAT –0.3 100 100 µA

VPFD Power-fail Deselect

Voltage 4.1 4.35 4.5 2.7 2.9 3.0 V

VSO Battery Back-up

Switchover Voltage 3.0 VPFD –

100mV V

VBAT Battery Voltage 3.0 3.0 V

M48T201Y, M48T201V

10/32

OPERATION

Automatic backup and write protection for an ex-

ternal SRAM is provided through VOUT, ECON, and

GCON pins. (Users are urged to insure that voltage

specifications, for both the SUPERVISOR chip

and external SRAM chosen, are similar.) The

SNAPHAT® containing the lithium energy source

is used to retain the RTC and RAM data in the ab-

sence of VCC power through the VOUT pin. The

chip enable output to RAM (ECON) an d the output

enable output to RAM (GCON) are con trolled dur-

ing power transients to prevent data corruption.

The date is automatically adjuste d for months with

less than 31 days and corrects for leap years (valid

until 2100). The internal watchdog timer provides

programma ble alarm windows.

The nine clock bytes (7FFFFh-7FFF9h and

7FFF1h) are not the actual clock counters, they

are memory locations consisting of BiPORT™

READ/WRITE memory c ells wi thi n the static RAM

array. Clock c ircuitry updat es t he c lock byt es with

current information once per second. The informa-

tion can be accessed by the user in the same man-

ner as any other location in the static memory

array. Byte 7FFF8h is the clock control register.

This byte controls user access to the clock infor-

mation and also stores the clock calibration set-

ting.

Byte 7FFF7h contains the watchdog t imer setting.

The watchdog timer can generate either a reset or

an interrupt, depending on the state of the Watch-

dog Steering Bit (WDS). Bytes 7FFF6h-7FFF2h

include bits that, when programmed, provide for

clock alarm functionality. Alarms are activated

when the register content matches the month,

date, hours, minutes, and seconds of the clock

registers. Byte 7FFF1h contains century informa-

tion. Byte 7FFF0h contains additional flag informa-

tion pertaining to the watchdog timer, the alarm

condition, the battery status and square wave out-

put operat ion. 4 bi ts are included within this regis-

ter (RS0-RS3) that are used to program the

Square Wave Output Frequency (see Table 12,

page 21). The M 48T201Y/V also has its own Pow-

er-Fail Detect circuit. This control circuitry con-

stantly monitors the supply voltage for an out of

tolerance condition. When VCC is out of tolerance,

t he ci rcui t wr it e pro tect s t he TIMEKE EPER® regis-

ter data and exte rnal SR AM, prov id ing data s ecu-

rit y in the midst of unpredictable system operation.

As VCC falls below the Battery Back-up Switchover

Voltage (VSO), the control circuitry automatically

switches to t he battery, maintaining data and clock

operation until valid power is rest ored.

Address Decoding

The M48T201Y/V accommodates 19 address

lines (A0-A18) which allow direct connection of up

to 512K bytes of static RA M. Regardless of SRAM

density used, tim ekeeping , watchdog, alarm , cen-

tury, flag, and control registers are located in the

upper RAM lo cations. All TIMEKEEPER registers

reside in the upper R AM l ocations without conflict

by inhibiting t he GCON (output enable RA M) signal

duri ng c lock access. The RAM's physi cal locations

are transparent to the user an d the memory map

looks continuous from the first clock address to the

upper most attached RAM addresses.

Table 6. Operating Modes

No te: X = VIH or VIL; VSO = Battery Back-up Switchover V olta ge

1. See Tabl e 9, page 17 for deta i l s.

Mode VCC E G W DQ7-DQ0 Power

Deselect

4.5V to 5.5V

3.0V to 3.6V

VIH X X High-Z Standby

WRITE VIL XVIL DIN Active

READ VIL VIL VIH DOUT Active

READ VIL VIH VIH High-Z Active

Deselect VSO to VPFD (min)(1) X X X High-Z CMOS Standby

Deselect ≤ VSO(1) X X X High-Z Battery Back-Up

11/32

M48T201Y, M 48T201V

READ Mode

The M48T201Y /V executes a RE AD Cycle when-

ever W (WRITE Enable) is high and E (Chip En-

able) is lo w. The unique address specified by the

address in puts (A0-A18) defines which one of the

on-chip TIMEKEEPER® registers or external

SRAM lo cations is to be ac cessed. Whe n the ad-

dress presented to the M48T201Y/V is in the

range of 7FFFFh-7FFF0h, one of the on-board

TIMEKEEPER registers is accessed and valid

data will be available to the eight data output driv-

ers within tAVQV after the address input signal is

stable, providing that the E and G access times

are also satisfi ed. If they are not , then data access

must be measured f rom the latt er occurring si gnal

(E or G) and the limiting pa rameter is e ither tELQV

for E or tGLQV for G rather than the address ac cess

time. When one of t he on-chip TIMEKEEPER re g -

isters is selected for READ, the GCON signal will

remain inactive throughout the READ Cycle.

When the address value presented to the

M48T201Y/V is outside the range of TIMEKEEP-

ER registers, an external SRAM location will be

selected. In this case the G signal will be passed

to the GCON p in, with the specified delay times of

tAOEL or tOERL.

Figure 6. GCON Timing When Switching Between RTC and External SRA M

AI02333

GCON

tAOEL

ADDRESS

00000h - 7FFEFh 7FFF0h - 7FFFFh 00000h - 7FFEFh7FFF0h - 7FFFFh

tAOEH tOERL tRO

External SRAM

RTC External SRAM

RTC

M48T201Y, M48T201V

12/32

Figure 7. READ Cycl e Timing: RTC and External RAM Contr ol Signals

AI02334

GCON

DQ0-DQ7

ECON

DATA OUT

VALID

ADDRESS

tAVAV

tELQV

tAVAV tAVAV

READ READ WRITE

DATA IN

VALID

DATA OUT

VALID

tAVQV tWHAXtAVWL

tELQX

tGLQV

tEPD

tRO

tGHQZ

tWLWH

tAXQXtGLQX

13/32

M48T201Y, M 48T201V

Table 7. RE AD Mode AC Characteristics

No te : 1. Valid fo r Ambien t Operatin g T em perature: TA = 0 to 70°C or –40 to 85° C; VCC = 4.5 t o 5. 5V or 3. 0 to 3.6V (except where noted).

2. CL = 5pF.

Symbol Parameter(1)

M48T201Y M48T201V

Unit–70 –85

Min Max Min Max

tAVAV READ Cycle Time 70 85 ns

tAVQV Address Valid to Output Valid 70 85 ns

tELQV Chip Enable Low to Output Valid 70 85 ns

tGLQV Output Enable Low to Output Valid 25 35 ns

tELQX(2) Chip Enable Low to Output Transition 5 5 ns

tGLQX(2) Output Enable Low to Output Transition 0 0 ns

tEHQZ(2) Chip Enable High to Output Hi-Z 20 25 ns

tGHQZ(2) Output Enable High to Output Hi-Z 20 25 ns

tAXQX Address Transition to Output Transition 5 5 ns

tAOEL External SRAM Address to GCON Low 20 30 ns

tAOEH SUPERVISOR SRAM Address to GCON High 20 30 ns

tEPD E to ECON Low or High 10 15 ns

tOERL G Low to GCON Low 15 20 ns

tRO G High to GCON High 10 15 ns

M48T201Y, M48T201V

14/32

WRITE Mod e

The M48T201Y/V is in the WRITE Mode whenever

W (WRITE Enable) and E (Chip Enable) are low

state after the address input s are stable. The start

of a WRI TE is ref erenced from the latter occurring

falling edge of W or E. A WRITE is term inated by

the earlier rising edge of W or E. The addresses

must be held valid throughout the cycle. E or W

must return high f or a minimum of tEHAX from Chip

Enable or tWHAX from W RITE Enable prior to the

initiation of another READ or WRITE Cycle. Data-

in m ust be valid tDVWH prior to the end of WRITE

and remain valid for tWHDX af terward. G should be

kept high during WRITE Cycles to avoi d bus con-

tention; although, if the output bu s has be en acti-

vated by a low on E and G a low on W will disable

the outputs tWLQZ after W falls.

When the address value presented to the

M48T201 Y/V during the WRITE is in the range of

7FFFFh-7FFF0h, one of the on-board TIME-

KEEPER® registers will be selected and data will

be written into t he device. When the address value

presented to M48T2 01Y/V is outside the range of

TIMEKEEPER registers, an external SRAM loca-

tion is sele cte d .

Figure 8. WRITE Cycle Ti min g: RTC & Exter nal RAM Con tr ol Signals

AI02336

GCON

DQ0-DQ7

ECON

DATA IN

VALID

ADDRESS

tAVAV

tAVEH

tAVAV tAVAV

WRITE WRITE READ

DATA OUT

VALID

DATA OUT

VALID

tAVWH

tAVQV

tWLWH

tWHDX

tWHAX

tWHQX

tEPD

tRO

tWLQZ

tDVWH

tGLQV

tEHQZ tDVEH

DATA IN

VALID

tELEH tEHAX

tAVEL

tEHDX

tAVWL

15/32

M48T201Y, M 48T201V

Table 8. WRITE Mode AC Characteristics

No te : 1. Valid fo r Ambien t Operatin g T em perature: TA = 0 to 70°C or –40 to 85° C; VCC = 4.5 t o 5. 5V or 3. 0 to 3.6V (except where noted).

2. CL = 5pF

3. If E goes low simultaneously with W goin g l ow, the outputs rem ai n in the hi gh i m pedance state.

Symbol Parameter(1)

M48T201Y M48T201V

Unit–70 –85

Min Max Min Max

tAVAV WRITE Cycle Time 70 85 ns

tAVWL Address Valid to WRITE Enable Low 0 0 ns

tAVEL Address Valid to Chip Enable Low 0 0 ns

tWLWH WRITE Enable Pulse Width 45 55 ns

tELEH Chip Enable Low to Chip Enable High 50 60 ns

tWHAX WRITE Enable High to Address Transition 0 0 ns

tEHAX Chip Enable High to Address Transition 0 0 ns

tDVWH Input Valid to WRITE Enable High 25 30 ns

tDVEH Input Valid to Chip Enable High 25 30 ns

tWHDX WRITE Enable High to Input Transition 0 0 ns

tEHDX Chip Enable High to Input Transition 0 0 ns

tWLQZ(2,3) WRITE Enable Low to Output High-Z 20 25 ns

tAVWH Address Valid to WRITE Enable High 55 65 ns

tAVEH Address Valid to Chip Enable High 55 65 ns

tWHQX(2,3) WRITE Enable High to Output Transition 5 5 ns

M48T201Y, M48T201V

16/32

Data Retention Mode

With valid VCC applied, the M48T201Y/V can be

accessed as described above with READ or

WRITE cycles. Should the supply voltage decay,

the M48T201Y/ V will autom atically deselect, write

protecting itself (and any external SRAM) when

VCC falls between VPFD (max) and VPFD (min).

This is accomplished by internally inhibiting ac-

cess to the clock registers via the E signal. A t this

time, the Reset pin (RST) is driven act ive an d wi ll

remain active until VCC returns to nominal levels.

External RAM access is inhibited in a si milar man-

ner by forcing ECON to a high level. This level is

within 0.2V of the VBAT. ECON will remain at this

level as long as VCC remains at an out-of-toler-

ance condition. When V CC falls bel ow the level of

the battery (VBAT), power input is switched from

the VCC pin to the SNAPHAT® battery and the

clock registers are maintained from the attached

battery supply. External RAM is also powered by

the SNAPHAT battery. All outputs except GCON,

ECON, RST, IRQ/FT and VOUT, become high im-

pedance. The VOUT pin is capable of supplying

100µA of current to the attac hed mem or y with less

than 0.3V drop under this conditi on. On power up,

when VCC returns to a nominal value, write protec-

tion continues for 200ms (max) by inhibiting ECON.

The RST signal also remains active during this

time (see Figure 9).

Note: Most low power SRAMs on the market to-

day can be used with the M48T201Y/V TIME-

KEEPER® SUPERVISOR. There are, however

some criteria which should be used in making the

final choice of an SRAM to use.

The SRAM must be designed in a way where the

chip enable input disables all other inputs to the

SRAM. This allows inputs t o the M48T201Y/V and

SRAMs to be “Don't care” once VCC falls below

VPFD (min). The SRAM should also guarantee

data retention down to VCC = 2.0V. The chip en-

able access time must be sufficient to meet the

system needs with the chip enable (and output en-

able) output propagation delays include d.

Figure 9. Power Down/Up Mode AC Waveforms

AI03519

VCC

INPUTS

RST

OUTPUTS

DON'T CARE

HIGH-Z

tFB

tRECtRB

VALID VALID

VPFD (max)

VPFD (min)

VSO

VALID VALID

17/32

M48T201Y, M 48T201V

Table 9. Power Down/Up M ode AC Characteristics

No te : 1. Valid fo r Ambien t Operatin g T em perature: TA = 0 to 70°C or –40 to 85° C; VCC = 4.5 t o 5. 5V or 3. 0 to 3.6V (except where noted).

2. VPFD (max) to VPFD (min) fall time o f less th an tF may result in deselection/write prot ection not occurring until 200µs aft er VCC pass-

es VPFD (min).

3. VPFD (min) to VSS fall time of less than tFB may cause corruption of RAM data.

4. tREC (min) = 20ms for industrial temperature Grade 6 device.

CLOCK OPERATION

TIMEKEEPER® Registers

The M48T201Y/V offers 16 internal registers

which conta in TIMEKEEPER®, Alarm, Watchdog,

Flag, and Control data (see Table 10, page 18).

These registers are m emory locations which con-

tain ext e rnal (user accessible) and internal copies

of the data (usually referred to as BiPORT™

TIMEKEEPER cells). The external copies are in-

dependent of internal functions except that they

are updated periodically by the simultaneous

transfer of the incremented internal copy. TIME-

KEEPER and Alarm Regi sters st ore da ta in BCD.

Control, Watchdog and Flags (Bits D0 to D3) Reg-

isters store data in Binary Format.

Reading the Clock

Updates to the TIMEKEEPER registers should be

halted bef ore clock data is read to prevent reading

data in transition. The BiPORT TIMEKEEPER

cells in the RAM array are only data registers and

not the actual clock counters , so updating the reg-

isters can be halt ed without disturbing the cl ock it-

self.

Updating is halted when a '1' is written to the

READ Bit, D6 in t he Control Register (7FFF8h). As

long as a '1' remains in that position, updating is

halted. After a halt is i ssu ed, the registers reflect

the count; that is, the day, dat e, and time that were

current at the moment the halt command was is-

sued.

All of the TIMEKEEPER registe rs are update d si-

multaneously. A halt will not interrupt an update in

progress. Updating occurs approximately 1 sec-

ond after the READ Bit is reset to a '0.'

S etting the C l ock

Bit D7 of the Control Register (7FFF8h) is the

WRITE Bit. Setting the WRIT E Bit to a '1,' like the

READ Bit, halts updates to the TIMEKEEPER reg-

isters. The user can then load them with the cor-

rect day, date, and time data in 24-hour BCD

format (see Table 10, page 18).

Resetting the WRITE Bit to a '0' t h en tran sfers the

values of all time registers (7FFFFh-7FFF9h,

7FFF1h) to the actual TIMEKEEPER counters and

allows normal operation to resume. After the

WRITE Bit is reset, the next clock update will occur

approximately one second later.

Note: Upon power-up following a power failure,

both the WRITE Bit and the READ Bit will be res et

to '0.'

Stopping and Starting the Oscillato r

The oscillator may be stopped at any time. If the

device is going to spend a significant amount of

time on the shelf, the oscillat or can be turned off to

minimize current drain on the battery. The STOP

Bit is located at Bit D7 within the Seconds Register

(7FFF9h). Setting it to a '1' stops the oscillator.

When reset to a '0,' the M48T201Y/V oscillator

starts within one second.

Note: It is not necessary to set the WRITE Bit

when setting or resetting the FREQUE NCY TES T

Bit (FT) or the STOP Bit (ST).

Symbol Parameter(1) Min Max Unit

tF(2) VPFD (max) to VPFD (min) VCC Fall Time 300 µs

tFB(3) VPFD (min) to VSS VCC Fall Time M48T201Y 10 µs

M48T201V 150 µs

tRVPFD (min) to VPFD (max) VCC Rise Time 10 µs

tREC(4) VPFD (max) to RST High 40 200 ms

tRB VSS to VPFD (min) VCC Rise Time 5µs

M48T201Y, M48T201V

18/32

Table 10. TIMEKEEPER® Register Map

Keys: S = Si gn Bit

FT = Frequency Test Bit

R = READ Bit

W = WRITE Bit

ST = Sto p Bit

0 = Must be set to '0'

WDS = Watchd og Steeri ng Bit

AF = Alarm Flag

BL = Battery Low Flag

SQWE = Square Wave Enable Bit

BMB0-BMB4 = Watchdog Multiplier Bits

RB0-RB1 = Watchd og Resolution Bits

AFE = Ala rm Flag Enable Flag

ABE = Alarm in Bat te ry Back-Up Mode Enable Bit

RPT1-RP T 5 = A l arm Repeat Mode Bits

WDF = Watchdog Flag

RS0-RS3 = SQW Frequency

Address Data Function/Range

BCD Format

D7 D6 D5 D4 D3 D2 D1 D0

7FFFFh 10 Years Year Ye ar 00-99

7FFFEh 0 0 0 10 M Month Month 01-12

7FFFDh 0 0 10 Date Date: Day of Month Date 01-31

7FFFCh 0 FT 0 0 0 Day Day 01-07

7FFFBh 0 0 10 Hours Hours (24 Hour Format) Hours 00-23

7FFFAh 0 10 Minutes Minutes Minutes 00-59

7FFF9h ST 10 Seco nds Seco nds Secon ds 00 -59

7FFF8h W R S Calibration Control

7FFF7h WDS BMB4 BMB3 BMB2 BMB1 BMB0 RB1 RB0 Watchdog

7FFF6h AFE SQWE ABE Al.10M Alarm Month Al. Month 01-12

7FFF5h RPT4 RPT5 Al. 10 Da te A larm Date Al. Date 01-31

7FFF4h RPT3 0 Al. 10 Hours Alarm Hours Al. Hours 00-23

7FFF3h RPT2 Alarm 10 Minutes Alarm Minutes Al. Minutes 00-59

7FFF2h RPT1 Alarm 10 Seconds Alarm Seconds Al. Seconds 00-59

7FFF1h 1000 Years 100 Years Century 00-99

7FFF0h WDF AF 0 BL RS3 RS2 RS1 RS0 Flags

19/32

M48T201Y, M 48T201V

Setting the Al arm Cl ock

Registers 7F FF6h-7FFF2 h contain t he alarm set-

tings. The alarm can be configured to go off at a

prescribed time on a specific month, day of mont h,

hour, minute, or second or repeat every month,

day of month, hour, minute, or second.

It can also be programmed to go off while the

M48T201 Y/V is in the batt ery bac k-up to serve as

a system wake-up call.

Bits RPT5-RPT1 put the alarm in the repeat mode

of operation. Tabl e 11 shows the po ssible config-

urations. Codes not listed in the table default to the

once per secon d m ode t o qu ick ly alert the us er of

an incorrect alarm setting.

Note: User must transition address (or toggle c hip

enable) to see Fl ag Bit change.

When the clock information matches the alarm

clock settings based on the match cr iteria d efined

by RPT5-RPT1, the AF (Alarm Flag) is set. If AFE

(Alarm Flag Enable) is also set, the alarm condi-

tion activates the IRQ/FT pin. To disable alarm,

write ’0’ to the Alarm-Date register and RPT1-5.

The IRQ/FT output is cleared by a READ to the

Flags Register as shown in Figure 10. A subse-

quent READ of the F lags Regi st er is necessary to

see that the value of the Alarm Fl ag has been re-

set to '0.'

The IRQ/FT pin can also be activated in the bat-

tery back-up mode. The IRQ/FT will go low if an

alarm occurs and both ABE (Alarm in Battery

Back-up Mode Enable) and AFE are set. The ABE

and AFE Bits are reset during power-up, therefore

an alarm generate d during power-up will only set

AF. The user can read t he Flag Register at syst em

boot-up to determine if an alarm was generated

while the M48T20 1Y/V was in t he desel ect m ode

during power-up. Figure 11, page 20 illustrates the

back-up mode alarm timing.

Figure 10. Alarm Interrupt Reset Waveforms

Table 11. Alarm Repeat Modes

RPT5 RPT4 RPT3 RPT2 RPT1 Alarm Setting

11111 Once per Second

11110 Once per Minute

11100 Once per Hour

11000 Once per Day

10000 Once per Month

00000 Once per Year

AI02331

A0-A18

ACTIVE FLAG BIT

ADDRESS 7FFF0h

IRQ/FT

15ns Min

HIGH-Z

M48T201Y, M48T201V

20/32

Figure 11. Back-up M ode Alarm Waveform s

Watchdog Timer

The watchdog timer can be used to detect an ou t-

of-control microprocessor. The us er program s the

watchdog timer by setting the desired amount of

time-out into the Watchdog Register, address

7FFF7h. Bits BMB4-BMB0 store a binary multiplier

and the two lower order bits RB1-RB0 select the

resolution, where 00 = 1/16 second, 01 = 1/4 sec-

ond, 10 = 1 second, and 11 = 4 seconds. The

amount of time-out is then determined to be the

multiplication of the five-bit multiplier value with the

resolution. (For example: writing 00001110 in the

Watchdog Register = 3*1 or 3 s econds).

Note: Accuracy of timer is within ± the selected

resolution.

If the processor does not reset the timer within the

specified period, the M48T201Y/V sets the WDF

(Watchdog Flag) and generates a watchdog i nter-

rupt or a microprocessor reset. WDF is reset by

reading the Flag Register (Addres s 7FFF0h).

The most significa nt bit of the Watchdog Regi ster

is the Watc hdog Steering Bit (WDS). When set to

a '0', the watchdog will activate the IRQ/FT pin

when timed-out. When WDS is set to a '1,' the

watchdog will output a negative pul se on the RS T

pin for tREC. The Watchdog register and the AFE,

SQWE, ABE, and FT Bits will reset to a '0' at the

end of a Watc hdog time-out when t he WDS Bit is

set to a '1.'

The watchdog timer can be reset by two methods:

1. a transition (high-to-low or low-to-high) can be

applied to the Watchdog Input pin (WDI) or

2. the m icroproc essor can perform a WRITE of the

Watchdog Regi ster.

The time-out period then starts over. The WDI pin

should be tied to VSS if not used. The watchdog

will be reset on each transition (edge) seen by the

WDI pin.

In order to perform a software reset of the watch-

dog timer, the original time-out period can be writ-

ten into the Watchdog Register, effectively

res tar ti n g the count- do wn cycle .

Should the wat chdog t imer time-out, and the WDS

Bit is programmed to output an interrupt, a value of

00h needs to be written to the Watchdog Register

in order to clear the IRQ/FT pin. This will also dis-

able the watchdog function until it is again pro-

grammed c orrectly. A READ of the Flags Regis ter

will reset the Watchdog Flag (Bit D7; Register

7FFF0h).

The watchdog function is automatically disabled

upon power-down and the Watchdog Register is

cleared. If the watchdog function i s set t o output to

the IRQ /FT pin and the frequency test function is

activated, the watchdog or alarm function prevails

and the frequency test function is denied.

Note: The user must transition the address (or

toggle chip enable) to see the Flag Bit change.

AI03520

VCC

IRQ/FT

HIGH-Z

VPFD (max)

VPFD (min)

AFE bit/ABE bit

AF bit in Flags Register

HIGH-Z

VSO

tREC

21/32

M48T201Y, M 48T201V

Square Wave Output

The M48T201Y/V offers the user a programm able

square wave function which is output on the SQW

pin. RS3-RS0 Bits located in 7FFF0h establ ish the

square wave output f requency. These frequenci es

are listed in Table 12. Once the selection of the

SQW frequency has been completed, the SQW

pin can be turned on and o ff under s oftware con-

trol with the Square W ave Enabl e Bit (SQWE ) lo-

cated in Register 7FFF6h.

Table 12. Square Wave Outp ut Frequen cy

Square Wave Bits Square Wave

RS3 RS2 RS1 RS0 Frequency Units

0 0 0 0 Hi-Z -

0 0 0 1 32.768 kHz

0 0 1 0 8.192 kHz

0 0 1 1 4.096 kHz

0 1 0 0 2.048 kHz

0 1 0 1 1.024 kHz

0 1 1 0 512 Hz

0 1 1 1 256 Hz

1 0 0 0 128 Hz

100164Hz

101032Hz

101116Hz

11008Hz

11014Hz

11102Hz

11111Hz

M48T201Y, M48T201V

22/32

Power -on Reset

The M48T201Y/V continuously monitors VCC.

When VCC falls to the power fail detect trip point,

the RST pulls low ( open drai n) and remains low on

power-up for tREC after VCC passes VPFD (max).

The RST pin is an open drain output and an appro-

priate pull-up resist or to VCC should be chosen to

control rise time.

Reset Inputs (RSTIN1 & RSTIN2)

The M48T201Y/V provides two independent in-

puts which can generate an output reset. The du-

ration and function of these resets is identical to a

reset generated by a pow er cycle. Figure 12 and

Table 13 illustrate the AC reset characteristics of

this function. Pulses shorter than tR1 and tR2 will

not generate a reset condition. RSTIN1 and

RSTIN2 are each internally pulled up to VCC

through a 100KΩ resistor.

Figure 12. RSTIN1 and RSTIN2 Tim i ng W aveforms

Table 13. Reset AC Characteristics

No te : 1. Valid fo r Ambien t Operatin g T em perature: TA = 0 to 70°C or –40 to 85° C; VCC = 4.5 t o 5. 5V or 3. 0 to 3.6V (except where noted).

2. CL = 5pF (see Figure 5).

3. tR1HRZ or tR2HRZ = 20ms f or i ndust ri al tempe rat ure Grade 6 device.

Symbol Parameter(1) Min Max Unit

tR1 RSTIN1 Low to RST Low 50 200 ns

tR2 RSTIN2 Low to RST Low 20 100 ms

tR1HRZ(2,3) RSTIN1 High to RST Hi-Z 40 200 ms

tR2HRZ(2,3) RSTIN2 High to RST Hi-Z 40 200 ms

AI01679

RSTIN1

RST

RSTIN2

tR1 tR1HRZ

Hi-Z

tR2

tR2HRZ

Hi-Z

23/32

M48T201Y, M 48T201V

Ca librat ing th e C lock

The M48T201Y/V is driven by a q uartz con trolled

oscillator with a nominal frequency of 32,768Hz.

The devices are factory calibrated at 25°C and

tested for accuracy. Clock accuracy will not ex-

ceed ±35 PPM (parts per million) oscillator fre-

quency error at 25°C, which equates to about

±1.53 minutes per month. When the Calibration

circuit i s properly employed, accuracy improves to

better than +1/–2 PPM at 25°C.

The oscillation rate of crystals changes with tem-

perature (see Figure 13, page 25). The

M48T201Y/V design employs periodic counter

correction. The calibr ation circuit adds or subtracts

counts from the oscillator divider circuit at the di-

vide by 256 stage, as shown in Figure 14, page 25.

The number of times pulses which are blanked

(subtracted, negative calibration) or split (added,

positive calibration) depends upon the v alue load-

ed into the five Calibration bits found in the Control

tracting counts slows the clock down.

The Calibration bits occupy the five lower order

bits (D4-D0) in the Control Register 7FFF8h.

These bits can be set to re present any value be-

tween 0 and 31 in bi nary f orm. Bit D5 i s a Sign Bit ;

'1' indicates positive cal ibration, '0' indi cates nega-

tive calibration. Calibration occurs within a 64

minute cycle. The first 62 minutes in the cycle

may, once per minute, have one second either

shortened by 12 8 o r lengthened by 256 oscillator

cycles. If a binary '1' is loaded into the register,

only the first 2 minutes in th e 64 minute cycle wi ll

be modified; if a binary 6 i s loaded, the fi rst 12 will

be affected, and so on.

Therefore, e ach calibration step ha s the effect of

adding 512 or subtracting 256 osc illator cycles for

every 125,829,120 actual oscillator cycles, that is

+4.068 or –2.034 PPM of adjustment p er ca libra-

tion step i n t he cal ibrat ion registe r. Ass um ing that

the oscilla tor is running at exactly 32,7 68Hz , each

of the 31 increm ents in the Calibration byte wou ld

represent +10.7 or –5.35 seconds per month

which corresponds to a total range of +5. 5 or –2.75

minutes per month.

Two methods are available for ascertaining how

much calibration a given M48T201Y/V may re-

quire. The first involves se tting the clock, letting it

run for a month and compari ng i t to a known accu-

rate reference and recording deviation over a fixed

period of time. Calibration values, including the

number of seconds los t or gained in a given peri-

od, can be found in the STM icroelectronics Appli-

cation Note AN934, “TIMEKEEPER®

CALIBRATION.” This allows the designer to give

the end user the ability to calibrate the clock as the

environment requires, even if the final product is

packaged in a non-user serviceable enclosure.

The designer c ould pr ov ide a simple utility that ac-

cesses the Calibration byte.

The second approach is better suited to a manu-

facturing envi ronment, and involves the use of the

IRQ/FT pin. The pin wil l toggle at 512Hz, when the

Stop Bit (ST , D7 of 7F FF9h) is '0, ' the Frequency

Test Bit (FT, D6 of 7FFFCh ) is '1,' the Alarm Flag

Enable Bit (AFE, D7 of 7FFF6h) is '0,' and the

Watchdog Steering Bit (WDS, D7 of 7FFF7h) is '1'

or the Watchdog Register (7FFF7h=0 ) is reset.

Note: A 4-second settling time must be allowed

before reading the 512Hz output.

Any deviation from 512Hz indicates the degree

and direction of oscillator frequency shift at the test

temperature. For example, a reading of

512.010124 Hz would indicate a + 20 PPM o scilla-

tor frequency error, requiring a –10 (WR001010)

to be loaded into the Calibration Byte for correc-

tion. Note that setting or cha nging the Calibrat ion

Byte does not affect the Frequency Test output

frequency.

The IRQ/FT pin is an open d rain out put which re-

quires a pull-up resistor to VCC for proper opera-

tion. A 500-10kΩ resistor is recommended in order

to control the rise time. The FT Bit is cleared on

power-down.

M48T201Y, M48T201V

24/32

Batt ery Lo w W arn in g

The M48T201Y/V automatically performs battery

voltage monitoring upo n power-up and at factory-

programmed time intervals of approximately 24

hours. The Battery Low (BL) Bit, Bit D4 of Flags

voltage is found to be less than approximately

2.5V. The BL Bit will remain asserted until comple-

tion of battery replacement and subsequent bat-

tery low monitoring tests, either during the next

power-up sequence or the next scheduled 24-hour

interval.

If a battery low is generated during a power-up se-

quence, this indicates that the battery is below ap-

proximately 2.5V and ma y not be able to maintain

data integrity in the SRAM. Data should be consid-

ered suspect and verified as correct. A fresh bat-

tery should be installed .

If a battery low indication is generated during the

24-hour interval check, this indicates that the bat-

tery is n ear end of life. However, data is not com-

promised due to the fact that a nominal VCC is

supplied. In order to insure data integrity during

subsequent pe riods of bat tery back- up mode, the

battery should be replaced. The SNAPHAT® top

may be replaced while VCC is applied to the de-

vice.

Note: This will cause the clock to lose time during

the interval the battery/crystal is removed.

The M48T201Y/V only monitors the batte ry when

a nominal VCC is applied to the device. Thus appli-

cations which require extensive durations in the

battery back- up mode should be powered-up peri-

odically (at least once every few mont hs) in order

for this technique to be beneficial. Additionally, i f a

battery low is indicated, data integrity should be

verified upon power-up via a checksum or other

technique.

Initial Power-on Defaults

Upon application of power to the device, the fol-

lowing register bits are set to a '0' state: WDS;

BMB0-BMB4; RB0-RB1; AFE; ABE; SQWE; W; R;

FT (see Table 14).

Table 14. Default Values

No te: 1. WDS, BM B0-BMB4, RB0, RB1 .

2. St at e of othe r contro l b its undefi ned.

3. St at e of othe r contro l b its rem ains unchanged.

4. As suming these bi ts set to '1' prior to power-down.

Condition W R FT AFE ABE SQWE WATCH DOG

Initial Power-up

(Battery Attach for SNAPHAT)(2) 000000 0

RESET(3) 000000 0

Power-down(4) 000111 0

25/32

M48T201Y, M 48T201V

Figure 13. Crysta l Accuracy Acro ss Temp eratur e

Figu re 14. Ca l ibr ati on W aveform

AI00999

–160

0 10203040506070

Frequency (ppm)

Temperature °C

80–10–20–30–40

–100

–120

–140

–40

–60

–80

–20

∆F= -0.038 (T - T

)

± 10%

Fppm

= 25 °C

AI00594B

NORMAL

POSITIVE

CALIBRATION

NEGATIVE

CALIBRATION

M48T201Y, M48T201V

26/32

VCC Noise And Negative Go ing Transients

ICC tr ansients, includi ng t hose produced by output

switching, can produce voltage fluctuations, re-

sulting in spi kes on the VCC bus. These transien ts

can be reduced if capacitors are used to store en-

ergy which stabilizes the VCC bus. The energy

stored in the bypass c apaci tors will be released as

low going spikes are generated or energy will be

absorbed when overshoots occur. A ceramic by-

pass capacitor val ue of 0.1µF (as shown in Figure

15) is recomm ended in order to provide the need-

ed filterin g.

In addition to transients that are caused by normal

SRAM operation, power cy cling can generate neg-

ative voltage spikes on VCC that drive it to values

below VSS by as much as one volt. These negative

spikes can cause data corruption in the SRAM

while in battery backup mode. To protect from

these voltage spikes, STMicroelectronics recom-

mends connecting a schottky diode from VCC to

VSS (cathode connected to VCC, anode to VSS).

Schottky diode 1N5817 is recommended for

through hole and MBRS120T3 is recommended

for surface mount .

Figure 15. Supply Voltage Protection

AI00605

VCC

0.1µF DEVICE

VCC

VSS

27/32

M48T201Y, M 48T201V

PACKAGE MECHANICAL INF O RMATION

Figure 16. SOH44 – 44-lead Plastic Small Outline, SNAPHAT, Pac kage Outline

Not e: Drawing is not to scale.

Table 15. SOH44 – 44-lead Plastic Small Outline, SNAPHAT , Package Mec han ical Data

Symb mm inches

Typ Min Max Typ Min Max

A 3.05 0.120

A1 0.05 0.36 0.002 0.014

A2 2.34 2.69 0.092 0.106

B 0.36 0.46 0.014 0.018

C 0.15 0.32 0.006 0.012

D 17.71 18.49 0.697 0.728

E 8.23 8.89 0.324 0.350

e 0.81 – – 0.032 – –

eB 3.20 3.61 0.126 0.142

H 11.51 12.70 0.453 0.500

L 0.41 1.27 0.016 0.050

α0° 8° 0° 8°

N44 44

CP 0.10 0.004

SOH-A

LA1 α

M48T201Y, M48T201V

28/32

Figure 17. SH – 4-pin SNAPHAT Housing for 48mAh B attery & Cry stal, Package Outline

Not e: Drawing is not to scale.

Table 16. SH – 4-pin S NAPHAT Housing for 48mA h Bat tery & Crystal, Package Mechanic al Data

Symb mm inches

Typ Min Max Typ Min Max

A 9.78 0.385

A1 6.73 7.24 0.265 0.285

A2 6.48 6.99 0.255 0.275

A3 0.38 0.015

B 0.46 0.56 0.018 0.022

D 21.21 21.84 0.835 0.860

E 14.22 14.99 0.560 0.590

eA 15.55 15.95 0.612 0.628

eB 3.20 3.61 0.126 0.142

L 2.03 2.29 0.080 0.090

SHTK-A

A1 A

29/32

M48T201Y, M 48T201V

Figure 18. SH – 4-pin SNAPHAT Housing for 120mAh Battery & Crystal, Package Outline

Not e: Drawing is not to scale.

Table 17. SH – 4-pin SNAPHAT Housing for 120mAh Battery & Crystal , Package Mechanical Data

Symb mm inches

Typ Min Max Typ Min Max

A 10.54 0.415

A1 8.00 8.51 0.315 .0335

A2 7.24 8.00 0.285 0.315

A3 0.38 0.015

B 0.46 0.56 0.018 0.022

D 21.21 21.84 0.835 0.860

E 17.27 18.03 0.680 .0710

eA 15.55 15.95 0.612 0.628

eB 3.20 3.61 0.126 0.142

L 2.03 2.29 0.080 0.090

SHTK-A

A1 A

M48T201Y, M48T201V

30/32

PART NUMBERING

Table 18. Ordering Information Example

Note: 1. The SOIC package (SOH44) requires the battery package (SNAPHAT®) which is ordered separately under the part number

“M4Txx-BR12SH” in plastic tube or “M4Txx-BR12SHTR” in Tape & Reel form.

Caution: Do not place the SNAPHAT battery p ackage “M4 Txx-BR12SH” in con ductive foa m as it will d rain the lithium bu tton-cell

battery.

For a list of available options (e.g., Speed, Package) or for furt her information on any aspect of this device,

please contact the ST Sales Office nearest to you.

Table 19. SNAPHAT® B at t ery Table

Example: M48T 201Y –70 MH 1 TR

Device Type

M48T

Supply and Write Protect Voltage

201Y = VCC = 4.5 to 5.5V; VPFD = 4.1V to 4.5V

201V = VCC = 3.0 to 3.6V; VPFD = 2.7V to 3.0V

Speed

–70 = 70ns (for M48T201Y)

–85 = 85ns (for M48T201V)

Package

MH(1) = SOH44

Tem pera ture Rang e

1 = 0 to 70°C

6 = –40 to 85°C

Shipping Method for SOIC

blank = Tubes

TR = Tape & Reel

Part Number Descr iption Pa ckag e

M4T28-BR12SH Lithium Battery (48mAh) SNAPHAT SH

M4T32 -BR1 2SH Lithiu m Battery (120m Ah) SNAP HAT SH

31/32
M48T201Y, M 48T201V
RE VISION HISTORY
Table 20. Document Revisio n History
Date Rev. # Revision Details
November 1999 1.0 First Issue
10-May-01 2.0 Reformatted; added Industrial temperature (Table 2, 5, 7, 8, 9)
14-May-01 2.1 Corrected table footnote (Table 9)
30-May-01 2.2 Change “Controller” references to “SUPERVISOR”
01-Aug-01 2.3 Formatting changes from recent document review findings; E2 added to Hookup (Figure 
4)
08-Aug-01 2.4 Improve text in “Setting the Alarm Clock” section
18-Dec-01 2.5 Added IBAT values for Industrial Temperature device (Table 5)
13-May-02 2.6 Modify reflow time and temperature footnote (Table 2)
16-Jul-02 2.7 Update DC Characteristics, footnotes (Table 5)
27-Mar-03 3.0 v2.2 template applied; update test condition (Table 5)

M48T201Y, M48T201V

32/32

M48T20 1 , M48T201Y, M48T201V, 48T201, 48T201Y, 48T 201V, T2 01, T201Y, T201V, SUPERVISOR, SUPERVISOR, SUPERVISOR, SUPERVISOR, SUPERVISOR, SUPERVISOR, SUPERVI SOR, SUPER-

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processor, Microprocessor, Microprocessor, Microprocesso r, Microprocessor, Microproce ssor, Microprocessor, Microprocess or, Microprocessor, Microprocesso r, Microprocessor, Microproce ssor, Microproces-

sor, Microprocessor, Microprocessor, Microprocessor, Microp rocessor, Microprocesso r, Microprocessor, Microproce ssor, Microprocessor, Low, Low, Low, Low, Low, Low, Low, Low, Low, Lo w, Low, Low, Low,

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Low , Low, Low, Low, Low, Low, Low, Low, Low, Lo w , Low, Low, Low, L ow , Low, Low, Low , Low, Low, Alar m , Al arm, Ala r m , Al ar m , A larm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm,

Alarm, Alarm, Alarm , Alarm, Alarm , Alarm, Alarm, Alarm, Ala rm, Alarm, Alarm, Alarm, Alarm , Alarm, Alarm , Alarm, Alarm, Alarm, Alarm, Alarm , A larm, Alarm, Ala rm, A larm, Alarm , A larm, Alarm, Ala rm, A larm,

Alarm, Alar m, Alarm, Alarm, Al arm, Alarm, Alarm, Alarm, Al arm, Alarm, Alarm, Alarm, Alarm, Al arm, Alarm, Alarm, Alarm, Alarm, Alarm, Al arm, Alarm, Alarm, Alarm, Al arm, A larm, Alarm, Alarm, Watc hdog, Watch-

dog, Wat c hdog, Watchdog , W at c hdog, Watchdog, Watchdog , Wa t chdog, Watch dog, Wat c hdog, Wa t ch dog, Watchdog, Watchdog, Watch dog, Wat c hdog, Wa t c hdog, Watchdog, Watchdog, Watch dog, Wat chdog ,

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Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, W atchdog, W atchdog, Watchdog, Watchdog, Watchdog, W atchdog, PFI, PFI, PFI, PFI, PFI, PFI, PFI, PFI, PFI, PFI, PFI, PFI, P FI, PFI, PFI,

PFI, PFI, PFI, PFI, PFI, PFI, PFI, PFI, PFI, PFI, PFI, PFI, PFI, PFI, PFI, PFI, PFI, PFI, PFI, PFI, PFO, PFO, PFO, PFO, PFO, PFO, P F O, PFO, PFO, PF O, P FO, PFO, PF O, PF O, PFO, PFO, P FO, P FO , PFO,

PFO, Reset, Reset, Reset, Reset, Re set, R e set, Reset, Reset, Reset, R e set, Re set, Reset, Reset, Rese t, R e set, Re set, Re set, Reset, R eset, Reset, Re set, Re set, Reset, R eset, Reset, Re set, Re set, R eset,

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Battery, Battery, Battery, Battery, Ba ttery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Batt ery, Battery , Battery, Batt ery, Batt ery, Batt ery, Battery , Battery, Batt ery, Batt ery,

Battery, B attery, Battery, B attery, Battery, Battery, Battery, Ba ttery, Battery, Battery, Switchover, Sw itchover, Switchover, Switchover, Switchover, Switchover, Switchover, Switc hover, Switchov er, Switchover,

Power-f ail , Power-f ail, Power -fail, Po wer-fa il, Power-f ail , Power-fai l, Power- fail, Po wer-fa il, Power-f ail, Power-fai l, Comparat o r , Comparator , C o m par ator , C omparat or , Co mp ar a t or , Comparat or , Compa r ator, Com-

parator, Comparator, Comparator, Comparator, Comparator, Comparator, Comparator, Comparator, Comparator, Comparator, Comparator, Comparator, Comparator, Comparator, Comparator, Comparator,

Comparator, Comparator, Comparator, Comparator, Comparator, Comparator, Comparator, Comparator, Comparator, Comparator, Comparator, Comparator, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT,

SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT,

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5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5 V , 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 3.3V, 3.3V, 3.3V, 3.3V, 3.3V, 3.3V, 3.3V, 3.3V, 3.3V, 3.3V

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