HI3-0508A-5Z - RENESAS TECHNOLOGY

FN3143 Rev.6.00 Page 1 of 20

October 30, 2007

FN3143

Rev.6.00

October 30, 2007

HI-506A, HI-507A, HI-508A, HI-509A

16-Channel, 8-Channel, Differential 8-Channel and Differential 4-Channel,

CMOS Analog MUXs with Active Overvoltage Protection

DATASHEET

The HI-506A, HI-507A, HI-508A and HI-509A are analog

multiplexers with active overvoltage protection. Analog input

levels may greatly exceed either power supply without

damaging the device or disturbing the signal path of other

channels. Active protection circuitry assures that signal

fidelity is maintained even under fault conditions that would

destroy other multiplexers. Analog inputs can withstand

constant 70VP-P levels with 15V supplies. Digital inputs will

also sustain continuous faults up to 4V greater than either

supply. In addition, signal sources are protected from short

circuiting should multiplexer supply loss occur. Each input

presents 1k of resistance under this condition. These

features make the HI-506A, HI-507A, HI-508A and HI-509A

ideal for use in systems where the analog inputs originate

from external equipment, or separately powered circuitry. All

devices are fabricated with 44V dielectrically isolated CMOS

technology. The HI-506A is a single 16-channel multiplexer,

the HI-507A is an 8-channel differential multiplexer, the

HI-508A is a single 8-channel multiplexer and the HI-509A is

a differential 4-channel multiplexer. If input overvoltage

protection is not needed the HI-506/507/508/509

multiplexers are recommended. For further information see

Application Note AN520.

Features

• Analog Overvoltage . . . . . . . . . . . . . . . . . . . . . . . . 70VP-P

• No Channel Interaction During Overvoltage

• Maximum Power Supply . . . . . . . . . . . . . . . . . . . . . . 44V

• Fail Safe with Power Loss (No Latch-Up)

• Break-Before-Make Switching

• Analog Signal Range . . . . . . . . . . . . . . . . . . . . . . . . 15V

• Access Time. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns

• Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . 7.5mW

• Pb-Free Available (RoHS Compliant)

Applications

• Data Acquisition Systems

• Industrial Controls

• Telemetry

HI-506A, HI-507A, HI-508A, HI-509A

FN3143 Rev.6.00 Page 2 of 20

October 30, 2007

Ordering Information

PART

NUMBER PART MARKING TEMP. RANGE (°C) PACKAGE PKG. DWG. #

HI1-0506A-2 HI1-506A-2 -55 to +125 28 Ld CERDIP F28.6

HI1-0506A-5 HI1-506A-5 0 to +75 28 Ld CERDIP F28.6

HI1-0506A-8 HI1-506A-8 -55 to +125

+ 160 Hour Burn-In

28 Ld CERDIP F28.6

HI3-0506A-5 HI3-506A-5 0 to +75 28 Ld PDIP E28.6

HI3-0506A-5Z (Note 1) HI3-506A-5Z 0 to +75 28 Ld PDIP (Note 2) (Pb-free) E28.6

HI3-0507A-5 HI3-507A-5 0 to +75 28 Ld PDIP E28.6

HI3-0507A-5Z (Note 1) HI3-507A-5Z 0 to +75 28 Ld PDIP (Note 2) (Pb-free) E28.6

HI1-0508A-8 HI1-508A-8 -55 to +125

+ 160 Hour Burn-In

16 Ld CERDIP F16.3

HI3-0508A-5 HI3-508A-5 0 to +75 16 Ld PDIP E16.3

HI3-0508A-5Z (Note 1) HI3-508A-5Z 0 to +75 16 Ld PDIP (Note 2) (Pb-free) E16.3

HI1-0509A-2 HI1-509A-2 -55 to +125 16 Ld CERDIP F16.3

HI1-0509A-5 HI1-509A-5 0 to +75 16 Ld CERDIP F16.3

HI1-0509A-8 HI1-509A-8 -55 to +125

+ 160 Hour Burn-In

16 Ld CERDIP F16.3

HI3-0509A-5 HI3-509A-5 0 to +75 16 Ld PDIP E16.3

HI3-0509A-5Z (Note 1) HI3-509A-5Z 0 to +75 16 Ld PDIP (Note 2) (Pb-free) E16.3

NOTES:

1. These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte

tin plate PLUS ANNEAL - e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations.

Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC

J STD-020.

2. Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications.

HI-506A, HI-507A, HI-508A, HI-509A

FN3143 Rev.6.00 Page 3 of 20

October 30, 2007

Pinouts

HI-506A (CERDIP, PDIP)

TOP VIEW

HI-507A (PDIP)

TOP VIEW

HI-508A (CERDIP, PDIP)

TOP VIEW

HI-509A (CERDIP, PDIP)

TOP VIEW

+VSUPPLY

IN 16

IN 15

IN 14

IN 13

IN 12

IN 11

IN 10

IN 9

GND

VREF

ADDRESS A3

OUT

IN 8

IN 7

IN 6

IN 5

IN 3

IN 1

ENABLE

ADDRESS A0

ADDRESS A1

ADDRESS A2

-VSUPPLY

IN 4

IN 2

+VSUPPLY

OUT B

IN 8B

IN 7B

IN 6B

IN 5B

IN 4B

IN 3B

IN 2B

IN 1B

GND

VREF

OUT A

IN 8A

IN 7A

IN 6A

IN 5A

IN 3A

IN 1A

ENABLE

ADDRESS A0

ADDRESS A1

ADDRESS A2

-VSUPPLY

IN 4A

IN 2A

ENABLE

-VSUPPLY

IN 1

IN 2

IN 3

OUT

IN 4

GND

+VSUPPLY

IN 5

IN 6

IN 7

IN 8

ENABLE

-VSUPPLY

IN 1A

IN 2A

IN 3A

OUT A

IN 4A

+VSUPPLY

IN 1B

IN 2B

IN 3B

IN 4B

OUT B

GND

HI-506A, HI-507A, HI-508A, HI-509A

FN3143 Rev.6.00 Page 4 of 20

October 30, 2007

Truth Tables

HI-506A

A3A2A1A0EN “ON” CHANNEL

XXXXL None

LLLLH 1

LLLHH 2

LLHLH 3

L LHHH 4

LHLLH 5

LHLHH 6

LHHLH 7

LHHHH 8

HLLLH 9

HLLHH 10

HLHLH 11

HLHHH 12

HHL LH 13

HHLHH 14

HHHLH 15

HHHHH 16

HI-507A

A2A1A0EN “ON” CHANNEL PAIR

XXXL None

LLLH 1

LLHH 2

LHLH 3

LHHH 4

HLLH 5

HLHH 6

HHLH 7

HHHH 8

HI-508A

A2A1A0EN “ON” CHANNEL

XXXL None

LLLH 1

LLHH 2

LHLH 3

LHHH 4

HLLH 5

HLHH 6

HHLH 7

HHHH 8

HI-509A

A1A0EN “ON” CHANNEL PAIR

X X L None

LLH 1

LHH 2

HLH 3

HHH 4

HI-506A, HI-507A, HI-508A, HI-509A

FN3143 Rev.6.00 Page 5 of 20

October 30, 2007

Functional Diagrams

HI-506A HI-507A

HI-508A HI-509A

DECODER/

DRIVER

† † † †

OUT

IN 1

IN 2

IN 16

PROTECTION A0A1A2A3

†

† DIGITAL INPUT

LEVEL

SHIFT

REF

VREF

OVERVOLTAGE

CLAMP AND

SIGNAL

ISOLATION

DECODER/

DRIVER

† † †

OUT

IN 1A

IN 8A

IN 1B

PROTECTION A0A1A2

†

† DIGITAL INPUT

LEVEL

SHIFT

REF

VREF

OVERVOLTAGE

CLAMP AND

SIGNAL

ISOLATION

IN 8B

OUT

DECODER/

DRIVER

† † †

OUT

IN 1

IN 2

IN 8

PROTECTION A0A1A2

†

† DIGITAL INPUT

LEVEL

SHIFT

REF

OVERVOLTAGE

CLAMP AND

SIGNAL

ISOLATION

DECODER/

DRIVER

† †

OUT

IN 1A

IN 4A

IN 1B

PROTECTION A0A1

†

† DIGITAL INPUT

LEVEL

SHIFT

REF

OVERVOLTAGE

CLAMP AND

SIGNAL

ISOLATION

IN 4B

OUT

HI-506A, HI-507A, HI-508A, HI-509A

FN3143 Rev.6.00 Page 6 of 20

October 30, 2007

Schematic Diagrams

ADDRESS INPUT BUFFER AND LEVEL SHIFTER

ADDRESS DECODER

LEVEL SHIFTER

VREF

ADD

P P

LEVEL

SHIFTED

ADDRESS

TTL REFERENCE

CIRCUIT

V+

R10

GND

OVERVOLTAGE

PROTECTION

200

V-



V+

GND

V+

V-

DECODE

R5 R7

A0 OR A0

TO N-CHANNEL

DEVICE OF

THE SWITCH

A1 OR A1

A2 OR A2

A3 OR A3

ENABLE

PP PP P P

V+

V-

TO P-CHANNEL

DEVICE OF

THE SWITCH

DELETE A3 OR A3 INPUT

FOR HI-507A, HI-508A, HI-509A

DELETE A2 OR A2 INPUT FOR HI-509A

HI-506A, HI-507A, HI-508A, HI-509A

FN3143 Rev.6.00 Page 7 of 20

October 30, 2007

MULTIPLEX SWITCH

Schematic Diagrams (Continued)

FROM DECODE

V+

OUT

FROM DECODE

OVERVOLTAGE PROTECTION

R11

V-

D7 D4 D5

HI-506A, HI-507A, HI-508A, HI-509A

FN3143 Rev.6.00 Page 8 of 20

October 30, 2007

Absolute Maximum Ratings Thermal Information

V+ to V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+44V

V+ to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+22V

V- to GND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -25V

Digital Input Voltage (VEN, VA) . . . . . . . . . . . . . (V-) -4V to (V+) +4V

or 20mA, Whichever Occurs First

Analog Signal (VIN, VOUT) . . . . . . . . . . . . . . (V-) -20V to (V+) +20V

Continuous Current, IN or OUT . . . . . . . . . . . . . . . . . . . . . . . . 20mA

Peak Current, IN or OUT, Pulsed 1ms, 10% Duty Cycle (Max) . . 40mA

Operating Conditions

Temperature Ranges

HI-506A/507A/508A/509A-2, -8 . . . . . . . . . . . . . .-55°C to +125°C

HI-506A/507A/508A/509A-5. . . . . . . . . . . . . . . . . . . 0°C to +75°C

Thermal Resistance (Typical, Note 3) JA (°C/W) JC (°C/W)

28 Ld CERDIP Package. . . . . . . . . . . . 55 18

16 Ld CERDIP Package. . . . . . . . . . . . 75 22

28 Ld PDIP Package . . . . . . . . . . . . . . 60 N/A

16 Ld PDIP Package . . . . . . . . . . . . . . 90 N/A

Maximum Junction Temperature

CERDIP Packages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175°C

PDIP Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +150°C

Maximum Storage Temperature Range . . . . . . . . . .-65°C to +150°C

Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below

http://www.intersil.com/pbfree/Pb-FreeReflow.asp

CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product relia bility and

result in failures not covered by warranty.

NOTE:

3. JA is measured with the component mounted on an evaluation PC board in free air.

Electrical Specifications Supplies = +15V, -15V; VREF Pin = Open; VAH (Logic Level High) = 4V; VAL (Logic Level Low) = 0.8V,

Unless Otherwise Specified. For Test Conditions, Consult Test Circuits Section.

PARAMETER

TEST

CONDITIONS

TEMP

(°C)

-2, -8 -5

UNITS

MIN

(Note 12) TYP

MAX

(Note 12)

MIN

(Note 12) TYP

MAX

(Note 12)

DYNAMIC CHARACTERISTICS

Access Time, tANote 4 25 - 0.5 - - 0.5 - s

Full - - 1.0 - - 1.0 s

Break-Before-Make Delay, tOPEN Note 4 25 25 80 - 25 80 - ns

Enable Delay (ON), tON(EN) Note 4 25 - 300 500 - 300 - ns

Full - - 1000 - - 1000 ns

Enable Delay (OFF), tOFF(EN) Note 4 25 - 300 500 - 300 - ns

Full - - 1000 - - 1000 ns

Settling Time, tS

HI-506A and HI-507A To 0.1% 25 - 1.2 - - 1.2 - s

To 0.01% 25 - 3.5 - - 3.5 - s

HI-508A and HI-509A To 0.1% 25 - 1.2 - - 1.2 - s

To 0.01% 25 - 3.5 - - 3.5 - s

Off Isolation Note 9 25 - 68 - - 68 - dB

Channel Input Capacitance, CS(OFF) 25 -10- -10- pF

Channel Output Capacitance, CD(OFF)

HI-506A 25 - 52 - - 52 - pF

HI-507A 25 - 30 - - 30 - pF

HI-508A 25 - 25 - - 25 - pF

HI-509A 25 - 12 - - 12 - pF

Digital Input Capacitance, CA25 -10- -10- pF

Input to Output Capacitance, CDS(OFF) 25 - 0.1 - - 0.1 - pF

DIGITAL INPUT CHARACTERISTICS

Input Low Threshold, TTL Drive, VAL Note 4 Full - - 0.8 - - 0.8 V

Input High Threshold, VAH (Note 11) Note 4 Full 4.0 - - 4.0 - - V

HI-506A, HI-507A, HI-508A, HI-509A

FN3143 Rev.6.00 Page 9 of 20

October 30, 2007

Input Leakage Current (High or Low), IANotes 4, 8 Full - - 1.0 - - 1.0 A

MOS Drive, VAL, HI-506A/HI-507A VREF = +10V 25 - - 0.8 - - 0.8 V

MOS Drive, VAH, HI-506A/HI-507A VREF = +10V 25 6.0 - - 6.0 - - V

ANALOG CHANNEL CHARACTERISTICS

Analog Signal Range, VIN Note 4 Full -15 - +15 -15 - +15 V

On Resistance, rON Notes 4, 5 25 - 1.2 1.5 - 1.5 1.8 k

Full - 1.5 1.8 - 1.8 2.0 k

Off Input Leakage Current, IS(OFF) Notes 4, 6 25 - 0.03 - - 0.03 - nA

Full - - 50 - - 50 nA

Off Output Leakage Current, ID(OFF) Notes 4, 6 25 - 0.1 - - 0.1 - nA

HI-506A Full - - 300 - - 300 nA

HI-507A Full - - 200 - - 200 nA

HI-508A Full - - 200 - - 200 nA

HI-509A Full - - 100 - - 100 nA

ID(OFF) With Input Overvoltage Applied Note 7 25 - 4.0 - - 4.0 - nA

Full - - 2.0 - - - A

On Channel Leakage Current, ID(ON) Notes 4, 6 25 - 0.1 - - 0.1 - nA

HI-506A Full - - 300 - - 300 nA

HI-507A Full - - 200 - - 200 nA

HI-508A Full - - 200 - - 200 nA

HI-509A Full - - 100 - - 100 nA

Differential Off Output Leakage Current, IDIFF,

(HI-507A, HI-509A Only)

Full - - 50 - - 50 nA

POWER SUPPLY CHARACTERISTICS

Current, I+ Notes 4, 10 Full - 0.5 2.0 - 0.5 2.0 mA

Current, I- Notes 4, 10 Full - 0.02 1.0 - 0.02 1.0 mA

Power Dissipation, PDFull - 7.5 - - 7.5 - mW

NOTES:

4. 100% tested for Dash 8. Leakage currents not tested at -55°C.

5. VOUT = 10V, IOUT = +100A.

6. 10nA is the practical lower limit for high speed measurement in the production test environment.

7. Analog Overvoltage = 33V.

8. Digital input leakage is primarily due to the clamp diodes (see Schematic). Typical leakage is less than 1nA at +25°C.

9. VEN = 0.8V, RL = 1k, CL = 15pF, VS = 7VRMS, f = 100kHz.

10. VEN, VA = 0V or 4V.

11. To drive from DTL/TTL Circuits, 1k pull-up resistors to +5V supply are recommended.

12. Parts are 100% tested at +25°C. Over-temperature limits established by characterization and are not production tested.

Electrical Specifications Supplies = +15V, -15V; VREF Pin = Open; VAH (Logic Level High) = 4V; VAL (Logic Level Low) = 0.8V,

Unless Otherwise Specified. For Test Conditions, Consult Test Circuits Section. (Continued)

PARAMETER

TEST

CONDITIONS

TEMP

(°C)

-2, -8 -5

UNITS

MIN

(Note 12) TYP

MAX

(Note 12)

MIN

(Note 12) TYP

MAX

(Note 12)

HI-506A, HI-507A, HI-508A, HI-509A

FN3143 Rev.6.00 Page 10 of 20

October 30, 2007

Test Circuits and Waveforms TA = +25°C, VSUPPLY = 15V, VAH = 4V, VAL = 0.8V, VREF = Open,

Unless Otherwise Specified

FIGURE 1A. TEST CIRCUIT

FIGURE 1B. ON RESISTANCE vs ANALOG INPUT VOLTAGE FIGURE 1C. NORMALIZED ON RESISTANCE vs SUPPLY

VOLTAGE

FIGURE 1. ON RESISTANCE

FIGURE 2A. LEAKAGE CURRENT vs TEMPERATURE FIGURE 2B. ID(OFF) TEST CIRCUIT (NOTE 13)

100A

OUTIN

VIN rON =

100A

-10

ANALOG INPUT (V)

ON RESISTANCE (k)

-8 246810-6 -4 -2 0

1.4

1.3

1.2

1.1

1.0

0.9

0.8

+125°C

+25°C

-55°C

0.7

0.6

1.5

1.4

1.3

1.2

1.1

1.0

0.9

0.8

NORMALIZED RESISTANCE

(REFERRED TO VALUE AT15V)

7 8 9 101112131415

SUPPLY VOLTAGE (V)

-55°C TO +125°C

VIN = +5V

100nA

10nA

1nA

100pA

10pA

LEAKAGE CURRENT

25 50 75 100 125

TEMPERATURE (°C)

OFF OUTPUT

CURRENT

ID(OFF)

OFF INPUT

LEAKAGE CURRENT

IS(OFF)

ON LEAKAGE

CURRENT

ID(ON)

ID(OFF)

±10V

+0.8V

OUT

10V

HI-506A, HI-507A, HI-508A, HI-509A

FN3143 Rev.6.00 Page 11 of 20

October 30, 2007

FIGURE 2C. IS(OFF) TEST CIRCUIT (NOTE 13) FIGURE 2D. ID(On) TEST CIRCUIT (NOTE 13)

NOTE:

13. Two measurements per channel: ±10V and +10V. (Two measurements per device for ID(OFF) ±10V and +10V.)

FIGURE 2. LEAKAGE CURRENTS

FIGURE 3A. ANALOG INPUT OVERVOLTAGE

CHARACTERISTICS

FIGURE 3B. TEST CIRCUIT

FIGURE 3. ANALOG INPUT OVERVOLTAGE CHARACTERISTICS

FIGURE 4A. ON CHANNEL CURRENT vs VOLTAGE FIGURE 4B. TEST CIRCUIT

FIGURE 4. ON CHANNEL CURRENT

Test Circuits and Waveforms TA = +25°C, VSUPPLY = 15V, VAH = 4V, VAL = 0.8V, VREF = Open,

Unless Otherwise Specified (Continued)

±10V

10V

+0.8V

OUT

IS(OFF)

OUT

ID(ON)

±10V

A0A1

10V

15 18 21 24 27 30 33 36

ANALOG INPUT OVERVOLTAGE (±V)

ANALOG INPUT CURRENT (mA)

OUTPUT OFF LEAKAGE CURRENT (nA)

ANALOG INPUT

CURRENT (IIN)

OUTPUT OFF LEAKAGE

CURRENT ID(OFF)

VIN

AIIN ID(OFF)

024 68101214

±14

±12

±10

±8

±6

±4

±2

VOLTAGE ACROSS SWITCH (V)

SWITCH CURRENT (mA)

-55°C

+25°C

+125°C

VIN

HI-506A, HI-507A, HI-508A, HI-509A

FN3143 Rev.6.00 Page 12 of 20

October 30, 2007

FIGURE 5A. SUPPLY CURRENT vs TOGGLE FREQUENCY †Similar connection for HI-507A/HI-508A/HI-509A

FIGURE 5B. TEST CIRCUIT

FIGURE 5. DYNAMIC SUPPLY CURRENT

FIGURE 6A. ACCESS TIME vs LOGIC LEVEL (HIGH) †Similar connection for HI-507A/HI-580A/HI-509A

FIGURE 6B. TEST CIRCUIT

FIGURE 6C. MEASUREMENT POINTS FIGURE 6D. WAVEFORMS

FIGURE 6. ACCESS TIME

Test Circuits and Waveforms TA = +25°C, VSUPPLY = 15V, VAH = 4V, VAL = 0.8V, VREF = Open,

Unless Otherwise Specified (Continued)

TOGGLE FREQUENCY (Hz)

SUPPLY CURRENT (mA)

10k 100k 1M 10M

VSUPPLY = ±10V

VSUPPLY = ±15V

+15V/+10V

V+

V-

IN 1

IN 2

IN 8/IN 16

OUT

10 14

MpF

50

+4V

GND

-15V/-10V

A-ISUPPLY

+ISUPPLY

±10V/±5V

THRU

IN 7/IN 15

HI-506A†

10V/



900

700

500

300

ACCESS TIME (ns)

LOGIC LEVEL (HIGH) (V)

579 151311

800

600

400

4 6 8 10 12 14

VREF = OPEN FOR LOGIC HIGH LEVEL  6V

VREF = LOGIC HIGH FOR LOGIC HIGH LEVELS > 6V

10V

+15V

V+

V-

IN 1

IN 2 THRU

IN 16

OUT

10 50

kpF

50

+4V

GND

-15V

10V

IN 7/IN 15

HI-506A†



VREF

1/2 VAH

VAH = 4.0V

10%

+10V

OUTPUT

-10V

ADDRESS

DRIVE (VA)

200ns/DIV.

VA INPUT

2V/DIV.

OUTPUT

5V/DIV.

S1 ON

S16 ON

HI-506A, HI-507A, HI-508A, HI-509A

FN3143 Rev.6.00 Page 13 of 20

October 30, 2007

FIGURE 7A. TEST CIRCUIT FIGURE 7B. MEASUREMENT POINTS

FIGURE 7C. WAVEFORMS

FIGURE 7. BREAK-BEFORE-MAKE DELAY

Test Circuits and Waveforms TA = +25°C, VSUPPLY = 15V, VAH = 4V, VAL = 0.8V, VREF = Open,

Unless Otherwise Specified (Continued)

IN 1

IN 2 THRU

IN 8/IN 16

OUT

50pF

1k

VOUT

50

+4.0V

GND

IN 7/IN 15

HI-506A†

†Similar connection for HI-507A/HI-508A/HI-509A

+5V

50% 50%

VAH = 4.0V

OUTPUT

ADDRESS

DRIVE (VA)

tOPEN

S1 ON S16 ON

VA INPUT

2V/DIV.

OUTPUT

0.5V/DIV.

100ns/DIV.

HI-506A, HI-507A, HI-508A, HI-509A

FN3143 Rev.6.00 Page 14 of 20

October 30, 2007

FIGURE 8A. TEST CIRCUIT FIGURE 8B. MEASUREMENT POINTS

FIGURE 8C. WAVEFORMS

FIGURE 8. ENABLE DELAYS

Test Circuits and Waveforms TA = +25°C, VSUPPLY = 15V, VAH = 4V, VAL = 0.8V, VREF = Open,

Unless Otherwise Specified (Continued)

IN 1

IN 2 THRU

IN 8 /IN 16

OUT

50pF

VAGND 1k

+10V

IN 7/IN 15

HI-506A†

†Similar connection for HI-507A//HI-508A/HI-509A

50

VOUT

VAH = 4.0V

OUTPUT

tOFF(EN)

tON(EN)

10%

50%

90%

ENABLE DRIVE

(VA)

DISABLED

OUTPUT

2V/DIV.

100ns/DIV.

ENABLE DRIVE

2V/DIV.

ENABLED

(S1 ON)

HI-506A, HI-507A, HI-508A, HI-509A

FN3143 Rev.6.00 Page 15 of 20

October 30, 2007

Die Characteristics

DIE DIMENSIONS:

159 mils x 83.9 mils

METALLIZATION:

Type: CuAl

Thickness: 16kÅ 2kÅ

SUBSTRATE POTENTIAL (NOTE):

-VSUPPLY

PASSIVATION:

Silox: 12kÅ 2kÅ

Nitride: 3.5kÅ 1kÅ

WORST CASE CURRENT DENSITY:

1.4 x 105 A/cm2

TRANSISTOR COUNT:

485

PROCESS:

CMOS-DI

NOTE: The substrate appears resistive to the -VSUPPLY terminal, therefore it may be left floating (Insulating Die Mount) or it may be mounted on a

conductor at -VSUPPLY potential.

Metallization Mask Layouts

HI-506A HI-507A

IN 9

IN 10

IN 11

IN 12

IN 13

IN 14

IN 15

IN 16

V- (27) +V (1) NC (2)

IN 1

IN 2

IN 3

IN 4

IN 5

IN 6

IN 7

IN 8

EN A0A1A2VREF GND

(18) (17) (16) (15) (13) (12)

(19)

(20)

(21)

(22)

(23)

(24)

(25)

(26) (4)

(5)

(6)

(7)

(8)

(9)

(10)

(11)

OUT (28)

(14)

IN 1B

IN 2B

IN 3B

IN 4B

IN 5B

IN 6B

IN 7B

IN 8B

V- (27) +V (1) OUT B(2)

IN 1A

IN 2A

IN 3A

IN 4A

IN 5A

IN 6A

IN 7A

IN 8A

EN A0A1A2NC VREF GND

(18) (17) (16) (15) (14) (13) (12)

(19)

(20)

(21)

(22)

(23)

(24)

(25)

(26) (4)

(5)

(6)

(7)

(8)

(9)

(10)

(11)

OUT A (28)

HI-506A, HI-507A, HI-508A, HI-509A

FN3143 Rev.6.00 Page 16 of 20

October 30, 2007

Die Characteristics

DIE DIMENSIONS:

108 mils x 83 mils

METALLIZATION:

Type: CuAl

Thickness: 16kÅ 2kÅ

SUBSTRATE POTENTIAL (NOTE):

-VSUPPLY

PASSIVATION:

Silox: 12kÅ 2kÅ

Nitride: 3.5kÅ 1kÅ

WORST CASE CURRENT DENSITY:

1.4 x 105 A/cm2

TRANSISTOR COUNT:

253

PROCESS:

CMOS-DI

NOTE: The substrate appears resistive to the -VSUPPLY terminal, therefore it may be left floating (Insulating Die Mount) or it may be mounted on a

conductor at -VSUPPLY potential.

Metallization Mask Layouts

HI-508A HI-509A

IN 6 IN 7 IN 8 OUT IN 4 IN 3

IN 1

IN 2

-V

A2EN

IN 5

GND

(11) (10) (9) (8) (7) (6)

(12)

(13)

(14)

(5)

(4)

(3)

(15) (16) (1) (2)

IN 3B IN 4B OUT B OUT A IN 4A IN 3A

IN 1A

IN 2A

-V

GND EN

IN 2B

IN 1B

(11) (10) (9) (8) (7) (6)

(12)

(13)

(14)

(5)

(4)

(3)

(15) (16) (1) (2)

HI-506A, HI-507A, HI-508A, HI-509A

FN3143 Rev.6.00 Page 17 of 20

October 30, 2007

Ceramic Dual-In-Line Frit Seal Packages (CERDIP)

NOTES:

1. Index area: A notch or a pin one identification mark shall be locat-

ed adjacent to pin one and shall be located within the shaded

area shown. The manufacturer’s identification shall not be used

as a pin one identification mark.

2. The maximum limits of lead dimensions b and c or M shall be

measured at the centroid of the finished lead surfaces, when

solder dip or tin plate lead finish is applied.

3. Dimensions b1 and c1 apply to lead base metal only. Dimension

M applies to lead plating and finish thickness.

4. Corner leads (1, N, N/2, and N/2+1) may be configured with a

partial lead paddle. For this configuration dimension b3 replaces

dimension b2.

5. This dimension allows for off-center lid, meniscus, and glass

overrun.

6. Dimension Q shall be measured from the seating plane to the

base plane.

7. Measure dimension S1 at all four corners.

8. N is the maximum number of terminal positions.

9. Dimensioning and tolerancing per ANSI Y14.5M - 1982.

10. Controlling dimension: INCH.

bbb C A - B

SEATING

BASE

PLANE

-D-

-A-

-C-

-B-



(c)

(b)

SECTION A-A

BASE

LEAD FINISH

METAL

eA/2

ccc C A - B

SSaaa CA - B

F28.6 MIL-STD-1835 GDIP1-T28 (D-10, CONFIGURATION A)

28 LEAD CERAMIC DUAL-IN-LINE FRIT SEAL PACKAGE

SYMBOL

INCHES MILLIMETERS

NOTESMIN MAX MIN MAX

A - 0.232 - 5.92 -

b 0.014 0.026 0.36 0.66 2

b1 0.014 0.023 0.36 0.58 3

b2 0.045 0.065 1.14 1.65 -

b3 0.023 0.045 0.58 1.14 4

c 0.008 0.018 0.20 0.46 2

c1 0.008 0.015 0.20 0.38 3

D - 1.490 - 37.85 5

E 0.500 0.610 12.70 15.49 5

e 0.100 BSC 2.54 BSC -

eA 0.600 BSC 15.24 BSC -

eA/2 0.300 BSC 7.62 BSC -

L 0.125 0.200 3.18 5.08 -

Q 0.015 0.060 0.38 1.52 6

S1 0.005 - 0.13 - 7

90o105o90o105o-

aaa - 0.015 - 0.38 -

bbb - 0.030 - 0.76 -

ccc - 0.010 - 0.25 -

M - 0.0015 - 0.038 2, 3

N28 288

Rev. 0 4/94

HI-506A, HI-507A, HI-508A, HI-509A

FN3143 Rev.6.00 Page 18 of 20

October 30, 2007

Dual-In-Line Plastic Packages (PDIP)

NOTES:

1. Controlling Dimensions: INCH. In case of conflict between English and

Metric dimensions, the inch dimensions control.

2. Dimensioning and tolerancing per ANSI Y14.5M-1982.

3. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of

Publication No. 95.

4. Dimensions A, A1 and L are measured with the package seated in

JEDEC seating plane gauge GS-3.

5. D, D1, and E1 dimensions do not include mold flash or protrusions.

Mold flash or protrusions shall not exceed 0.010 inch (0.25mm).

6. E and are measured with the leads constrained to be perpendic-

ular to datum .

7. eB and eC are measured at the lead tips with the leads unconstrained.

eC must be zero or greater.

8. B1 maximum dimensions do not include dambar protrusions. Dambar

protrusions shall not exceed 0.010 inch (0.25mm).

9. N is the maximum number of terminal positions.

10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3,

E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm).

-C-

-B-

INDEX 12 3 N/2

AREA

SEATING

BASE

PLANE

-C-

-A-

0.010 (0.25) C AMBS

E28.6 (JEDEC MS-011-AB ISSUE B)

28 LEAD DUAL-IN-LINE PLASTIC PACKAGE

SYMBOL

INCHES MILLIMETERS

NOTESMIN MAX MIN MAX

A - 0.250 - 6.35 4

A1 0.015 - 0.39 - 4

A2 0.125 0.195 3.18 4.95 -

B 0.014 0.022 0.356 0.558 -

B1 0.030 0.070 0.77 1.77 8

C 0.008 0.015 0.204 0.381 -

D 1.380 1.565 35.1 39.7 5

D1 0.005 - 0.13 - 5

E 0.600 0.625 15.24 15.87 6

E1 0.485 0.580 12.32 14.73 5

e 0.100 BSC 2.54 BSC -

eA0.600 BSC 15.24 BSC 6

eB- 0.700 - 17.78 7

L 0.115 0.200 2.93 5.08 4

N28 289

Rev. 1 12/00

HI-506A, HI-507A, HI-508A, HI-509A

FN3143 Rev.6.00 Page 19 of 20

October 30, 2007

Ceramic Dual-In-Line Frit Seal Packages (CERDIP)

NOTES:

1. Index area: A notch or a pin one identification mark shall be locat-

ed adjacent to pin one and shall be located within the shaded

area shown. The manufacturer’s identification shall not be used

as a pin one identification mark.

2. The maximum limits of lead dimensions b and c or M shall be

measured at the centroid of the finished lead surfaces, when

solder dip or tin plate lead finish is applied.

3. Dimensions b1 and c1 apply to lead base metal only. Dimension

M applies to lead plating and finish thickness.

4. Corner leads (1, N, N/2, and N/2+1) may be configured with a

partial lead paddle. For this configuration dimension b3 replaces

dimension b2.

5. This dimension allows for off-center lid, meniscus, and glass

overrun.

6. Dimension Q shall be measured from the seating plane to the

base plane.

7. Measure dimension S1 at all four corners.

8. N is the maximum number of terminal positions.

9. Dimensioning and tolerancing per ANSI Y14.5M - 1982.

10. Controlling dimension: INCH.

bbb C A - B

SEATING

BASE

PLANE

-D-

-A-

-C-

-B-



(c)

(b)

SECTION A-A

BASE

LEAD FINISH

METAL

eA/2

ccc C A - B

SSaaa CA - B

F16.3 MIL-STD-1835 GDIP1-T16 (D-2, CONFIGURATION A)

16 LEAD CERAMIC DUAL-IN-LINE FRIT SEAL PACKAGE

SYMBOL

INCHES MILLIMETERS

NOTESMIN MAX MIN MAX

A - 0.200 - 5.08 -

b 0.014 0.026 0.36 0.66 2

b1 0.014 0.023 0.36 0.58 3

b2 0.045 0.065 1.14 1.65 -

b3 0.023 0.045 0.58 1.14 4

c 0.008 0.018 0.20 0.46 2

c1 0.008 0.015 0.20 0.38 3

D - 0.840 - 21.34 5

E 0.220 0.310 5.59 7.87 5

e 0.100 BSC 2.54 BSC -

eA 0.300 BSC 7.62 BSC -

eA/2 0.150 BSC 3.81 BSC -

L 0.125 0.200 3.18 5.08 -

Q 0.015 0.060 0.38 1.52 6

S1 0.005 - 0.13 - 7

90o105o90o105o-

aaa - 0.015 - 0.38 -

bbb - 0.030 - 0.76 -

ccc - 0.010 - 0.25 -

M - 0.0015 - 0.038 2, 3

N16 168

Rev. 0 4/94

FN3143 Rev.6.00 Page 20 of 20

October 30, 2007

HI-506A, HI-507A, HI-508A, HI-509A

Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted

in the quality certifications found at www.intersil.com/en/support/qualandreliability.html

Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such

modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are

current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its

subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or

otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see www.intersil.com

For additional products, see www.intersil.com/en/products.html

All trademarks and registered trademarks are the property of their respective owners.

Dual-In-Line Plastic Packages (PDIP)

NOTES:

1. Controlling Dimensions: INCH. In case of conflict between English and

Metric dimensions, the inch dimensions control.

2. Dimensioning and tolerancing per ANSI Y14.5M-1982.

3. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of

Publication No. 95.

4. Dimensions A, A1 and L are measured with the package seated in JE-

DEC seating plane gauge GS-3.

5. D, D1, and E1 dimensions do not include mold flash or protrusions.

Mold flash or protrusions shall not exceed 0.010 inch (0.25mm).

6. E and are measured with the leads constrained to be perpendic-

ular to datum .

7. eB and eC are measured at the lead tips with the leads unconstrained.

eC must be zero or greater.

8. B1 maximum dimensions do not include dambar protrusions. Dambar

protrusions shall not exceed 0.010 inch (0.25mm).

9. N is the maximum number of terminal positions.

10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3,

E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm).

-C-

-B-

INDEX 12 3 N/2

AREA

SEATING

BASE

PLANE

-C-

-A-

0.010 (0.25) C AMBS

E16.3 (JEDEC MS-001-BB ISSUE D)

16 LEAD DUAL-IN-LINE PLASTIC PACKAGE

SYMBOL

INCHES MILLIMETERS

NOTESMIN MAX MIN MAX

A - 0.210 - 5.33 4

A1 0.015 - 0.39 - 4

A2 0.115 0.195 2.93 4.95 -

B 0.014 0.022 0.356 0.558 -

B1 0.045 0.070 1.15 1.77 8, 10

C 0.008 0.014 0.204 0.355 -

D 0.735 0.775 18.66 19.68 5

D1 0.005 - 0.13 - 5

E 0.300 0.325 7.62 8.25 6

E1 0.240 0.280 6.10 7.11 5

e 0.100 BSC 2.54 BSC -

eA0.300 BSC 7.62 BSC 6

eB- 0.430 - 10.92 7

L 0.115 0.150 2.93 3.81 4

N16 169

Rev. 0 12/93