PIC18F26/45/46Q10 28/40-Pin, Low-Power, High-Performance Microcontrollers Description PIC18F26/45/46Q10 microcontrollers feature analog, core independent, and communication peripherals for a wide range of general purpose and low-power applications. These 28/40/44-pin devices are equipped with a 10-bit ADC with Computation (ADC2) automating Capacitive Voltage Divider (CVD) techniques for advanced touch sensing, averaging, filtering, oversampling and performing automatic threshold comparisons. They also offer a set of core independent peripherals such as Complementary Waveform Generator (CWG), Windowed Watchdog Timer (WWDT), Cyclic Redundancy Check (CRC)/ Memory Scan, Zero-Cross Detect (ZCD), Configurable Logic Cell (CLC), and Peripheral Pin Select (PPS), providing increased design flexibility and lower system cost. Core Features * C Compiler Optimized RISC Architecture * Operating Speed: - DC - 64 MHz clock input over the full VDD range - 62.5 ns minimum instruction cycle * Programmable 2-Level Interrupt Priority * 31-Level Deep Hardware Stack * Three 8-Bit Timers (TMR2/4/6) with Hardware Limit Timer (HLT) * Four 16-Bit Timers (TMR0/1/3/5) * Low-Current Power-on Reset (POR) * Power-up Timer (PWRT) * Brown-out Reset (BOR) * Low-Power BOR (LPBOR) Option * Windowed Watchdog Timer (WWDT): - Watchdog Reset on too long or too short interval between watchdog clear events - Variable prescaler selection - Variable window size selection - All sources configurable in hardware or software Memory * * * * Up to 64K Bytes Program Flash Memory Up to 3615 Bytes Data SRAM Memory Up to 1024 Bytes Data EEPROM Programmable Code Protection (c) 2019 Microchip Technology Inc. Preliminary Datasheet DS40001996C-page 1 PIC18F26/45/46Q10 * Direct, Indirect and Relative Addressing modes Operating Characteristics * Operating Voltage Range: - 1.8V to 5.5V * Temperature Range: - Industrial: -40C to 85C - Extended: -40C to 125C Power-Saving Operation Modes * * * * Doze: CPU and Peripherals Running at Different Cycle Rates (typically CPU is lower) Idle: CPU Halted While Peripherals Operate Sleep: Lowest Power Consumption Peripheral Module Disable (PMD): - Ability to selectively disable hardware module to minimize active power consumption of unused peripherals * Extreme Low-Power mode (XLP) - Sleep: 500 nA typical @ 1.8V - Sleep and Watchdog Timer: 900 nA typical @ 1.8V Digital Peripherals * Configurable Logic Cell (CLC): - Integrated combinational and sequential logic * Complementary Waveform Generator (CWG): - Rising and falling edge dead-band control - Full-bridge, half-bridge, 1-channel drive - Multiple signal sources * Capture/Compare/PWM (CCP) modules: - Two CCPs - 16-bit resolution for Capture/Compare modes - 10-bit resolution for PWM mode * 10-Bit Pulse-Width Modulators (PWM): - Two 10-bit PWMs * Serial Communications: - Two Enhanced USART (EUSART) with Auto-Baud Detect, Auto-wake-up on Start. RS-232, RS-485, LIN compatible - SPI - I2C, SMBus and PMBusTM compatible * Up to 35 I/O Pins and One Input Pin: - Individually programmable pull-ups - Slew rate control (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 2 PIC18F26/45/46Q10 * * * * - Interrupt-on-change on all pins - Input level selection control Programmable CRC with Memory Scan: - Reliable data/program memory monitoring for Fail-Safe operation (e.g., Class B) - Calculate CRC over any portion of Flash or EEPROM - High-speed or background operation Hardware Limit Timer (TMR2/4/6+HLT): - Hardware monitoring and Fault detection Peripheral Pin Select (PPS): - Enables pin mapping of digital I/O Data Signal Modulator (DSM) Analog Peripherals * 10-Bit Analog-to-Digital Converter with Computation (ADC2): - 35 external channels - Conversion available during Sleep - Four internal analog channels - Internal and external trigger options - Automated math functions on input signals: * Averaging, filter calculations, oversampling and threshold comparison - 8-bit hardware acquisition timer * Hardware Capacitive Voltage Divider (CVD) Support: - 8-bit precharge timer - Adjustable Sample-and-Hold capacitor array - Guard ring digital output drive * Zero-Cross Detect (ZCD): - Detect when AC signal on pin crosses ground * 5-Bit Digital-to-Analog Converter (DAC): - Output available externally - Programmable 5-bit voltage (% of VDD,[VREF+ - VREF-], FVR) - Internal connections to comparators and ADC * Two Comparators (CMP): - Four external inputs - External output via PPS * Fixed Voltage Reference (FVR) Module: - 1.024V, 2.048V and 4.096V output levels - Two buffered outputs: One for DAC/CMP and one for ADC Clocking Structure * High-Precision Internal Oscillator Block (HFINTOSC): - Selectable frequencies up to 64 MHz - 1% at calibration (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 3 PIC18F26/45/46Q10 * 32 kHz Low-Power Internal Oscillator (LFINTOSC) * External 32 kHz Crystal Oscillator (SOSC) * External High-frequency Oscillator Block: - Three crystal/resonator modes - Digital Clock Input mode - 4x PLL with external sources * Fail-Safe Clock Monitor: - Allows for safe shutdown if external clock stops * Oscillator Start-up Timer (OST) Programming/Debug Features * In-Circuit Serial ProgrammingTM (ICSPTM) via Two Pins * In-Circuit Debug (ICD) with Three Breakpoints via Two Pins * Debug Integrated On-Chip PIC18F26/45/46Q10 Family Types CLC Low Voltage Detect (LVD) 8-bit TMR with HLT CRC with Memory Scan EUSART I2C/SPI PPS Peripheral Module Disable Temperature Indicator Debug(1) 24 1 1 2/2 1 8 1 3 Y Y 2 2 Y Y Y I PIC18F45Q10 32k 2304 256 36 4 2 35 1 1 2/2 1 8 1 3 Y Y 2 2 Y Y Y I PIC18F46Q10 64k 3615 1024 36 4 2 35 1 1 2/2 1 8 1 3 Y Y 2 2 Y Y Y I Timer CWG 2 Windowed Watchdog Zero-Cross Detect 4 CCP/10-bit PWM 5-bit DAC 25 Computation (ch) Comparators 1024 10-bit ADC2 with 16-bit Timers 3615 Data EEPROM (bytes) 64k Device Data SRAM (bytes)(2) PIC18F26Q10 Program Memory Flash (bytes) I/O Pins Table 1. Devices included in this data sheet Note: 1. Debugging Methods: (I) - Integrated on-chip. 2. SRAM includes 256 bytes of SECTOR space which is not included in the data size displayed by MPLAB X. CWG CLC Low Voltage Detect (LVD) 8-bit TMR with HLT CRC with Memory Scan EUSART I2C/SPI PPS Peripheral Module Disable Temperature Indicator Debug(1) 2 24 1 1 2/2 1 0 1 3 Y Y 1 1 Y Y Y I PIC18F25Q10 32k 2304 256 25 4 2 24 1 1 2/2 1 0 1 3 Y Y 1 1 Y Y Y I PIC18F27Q10 128k 3615 1024 25 4 2 24 1 1 2/2 1 8 1 3 Y Y 2 2 Y Y Y I (c) 2019 Microchip Technology Inc. Datasheet Preliminary Timer Zero-Cross Detect 4 Windowed Watchdog 5-bit DAC 25 CCP/10-bit PWM Comparators 256 Computation (ch) 16-bit Timers 1280 10-bit ADC2 with I/O Pins 16k Device Data SRAM (bytes)(2) PIC18F24Q10 Program Memory Flash (bytes) Data EEPROM (bytes) Table 2. Devices not included in this data sheet DS40001996C-page 4 PIC18F26/45/46Q10 PPS Peripheral Module Disable Temperature Indicator Debug(1) Y I2C/SPI 3 EUSART 1 CRC with Memory Scan 8-bit TMR with HLT 8 Timer Low Voltage Detect (LVD) 1 2/2 Windowed Watchdog CLC 1 CCP/10-bit PWM 1 CWG 35 Zero-Cross Detect 2 Computation (ch) 4 10-bit ADC2 with 36 5-bit DAC 1024 Comparators 3615 16-bit Timers 128k I/O Pins PIC18F47Q10 Data EEPROM (bytes) Device Data SRAM (bytes)(2) Program Memory Flash (bytes) ...........continued Y 2 2 Y Y Y I Note: 1. Debugging Methods: (I) - Integrated on-chip. 2. SRAM includes 256 bytes of SECTOR space which is not included in the data size displayed by MPLAB X. Data Sheet Index: 1. 2. DS40001945 Data Sheet, 28-Pin, 8-bit Flash Microcontrollers DS40002043 Data Sheet, 28/40-Pin, 8-bit Flash Microcontrollers Packages Important: For other small form-factor package availability and marking information, visit http://www.microchip.com/packaging or contact your local Microchip sales office. TQFP (PT) PDIP (P) QFN (MP) (5x5x0.9) PIC18F45Q10 PIC18F46Q10 Packages PIC18F26Q10 SPDIP (SP) SOIC (SO) SSOP (SS) QFN (ML) (6x6x0.9) VQFN (STX) (4x4x1) Important: Pin details are subject to change. (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 5 Filename: Title: Last Edit: First Used: Notes: PIC18F26/45/46Q10 00-000028A.vsd 28-pin DIP 10/3/2018 N/A Generic 28-pin dual in-line diagram Pin Diagrams Figure 1. 28-pin SPDIP, SSOP, SOIC Rev. 00-000028A 10/3/2018 MCLR/VPP/RE3 RA0 RA1 RA2 RA3 RA4 RA5 VSS RA7 RA6 RC0 RC1 RC2 RC3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 RB7/ICSPDAT RB6/ICSPCLK RB5 RB4 RB3 RB2 RB1 RB0 VDD VSS RC7 RC6 RC5 RC4 RA1 RA0 RE3/MCLR/VPP RB7/ICSPDAT RB6/ICSPCLK RB5 RB4 Figure 2. 28-pin QFN VQFN Rev. 00-000028B 6/23/2017 28 27 26 25 24 23 22 RA2 1 RA3 RA4 RA5 VSS RA7 RA6 21 RB3 20 RB2 2 3 19 RB1 18 RB0 4 5 17 VDD 16 VSS 6 7 15 RC7 RC0 RC1 RC2 RC3 RC4 RC5 RC6 8 9 10 11 12 13 14 Note: It is recommended that the exposed bottom pad be connected to VSS, however it must not be the only VSS connection to the device. (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 6 Filename: Title: Last Edit: First Used: Notes: 00-000040A.vsd 40-pin DIP 10/3/2018 N/A Generic 40-pin dual in-line diagram PIC18F26/45/46Q10 Figure 3. 40-pin PDIP Rev. 00-000040A 10/3/2018 Filename: Title: Last Edit: First Used: Notes: MCLR/VPP/RE3 RA0 RA1 RA2 RA3 RA4 RA5 RE0 RE1 RE2 VDD VSS RA7 RA6 RC0 RC1 00-000040B.vsd RC2 40-pin QFN RC3 11/6/2017 N/A RD0 Generic 40-pin QFN diagram RD1 40 39 38 37 36 35 34 33 32 31 30 29 28 27 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 26 25 24 23 22 21 RB7/ICSPDAT RB6/ICSPCLK RB5 RB4 RB3 RB2 RB1 RB0 VDD VSS RD7 RD6 RD5 RD4 RC7 RC6 RC5 RC4 RD3 RD2 Figure 4. 40-pin QFN RC6 RC5 RC4 RD3 RD2 RD1 RD0 RC3 RC2 RC1 Rev. 00-000040B 11/6/2017 40 39 38 37 36 35 34 33 32 31 RC7 RD4 RD5 RD6 RD7 VSS VDD RB0 RB1 RB2 1 2 3 4 5 6 7 8 9 10 30 29 28 27 26 25 24 23 22 21 RC0 RA6 RA7 VSS VDD RE2 RE1 RE0 RA5 RA4 RB3 RB4 RB5 ICSPCLK/RB6 ICSPDAT/RB7 VPP/MCLR/RE3 RA0 RA1 RA2 RA3 11 12 13 14 15 16 17 18 19 20 Note: It is recommended that the exposed bottom pad be connected to VSS, however it must not be the only VSS connection to the device. (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 7 Filename: Title: Last Edit: First Used: Notes: 00-000044A.vsd 44-pin TQFP 11/6/2017 N/A Generic 44-pin TQFP diagram PIC18F26/45/46Q10 RC6 RC5 RC4 RD3 RD2 RD1 RD0 RC3 RC2 RC1 NC Figure 5. 44-pin TQFP Rev. 00-000044A 11/6/2017 44 43 42 41 40 39 38 37 36 35 34 RC7 RD4 RD5 RD6 RD7 VSS VDD RB0 RB1 RB2 RB3 1 2 3 4 5 6 7 8 9 10 11 NC RC0 RA6 RA7 VSS VDD RE2 RE1 RE0 RA5 RA4 33 32 31 30 29 28 27 26 25 24 23 NC NC RB4 RB5 ICSPCLK/RB6 ICSPDAT/RB7 VPP/MCLR/RE3 RA0 RA1 RA2 RA3 12 13 14 15 16 17 18 19 20 21 22 Pin Allocation Tables Table 3. 28-Pin Allocation Table I/O(2) RA0 28-Pin SPDIP, SOIC, SSOP 28-Pin (V)QFN A/D Reference 2 27 ANA0 -- Comparator Timers DSM MSSP Pullup Basic -- -- -- Y -- IOCA1 -- -- -- Y -- -- IOCA2 -- -- -- Y -- -- -- IOCA3 -- MDCARL(1) -- Y -- CCP CWG -- -- -- -- IOCA0 -- -- -- -- -- -- -- C1IN1+ -- -- C1IN0- ZCD Interrupt EUSART C2IN0RA1 3 28 ANA1 -- C1IN1C2IN1- RA2 4 1 ANA2 DAC1OUT1 C1IN0+ VREF- (DAC) C2IN0+ VREF- (ADC) RA3 5 2 ANA3 VREF+ (DAC) VREF+ (ADC) RA4 6 3 ANA4 -- -- T0CKI(1) -- -- -- IOCA4 -- MDCARH(1) -- Y -- RA5 7 4 ANA5 -- -- -- -- -- -- IOCA5 -- MDSRC(1) SS1(1) Y -- RA6 10 7 ANA6 -- -- -- -- -- -- IOCA6 -- -- -- Y CLKOUT OSC2 RA7 9 6 ANA7 -- -- -- -- -- -- IOCA7 -- -- -- Y OSC1 CLKIN RB0 21 18 ANB0 -- C2IN1+ -- -- CWG1(1) ZCDIN IOCB0 -- -- SS2(1) Y -- -- -- SCK2(1) Y -- INT0(1) RB1 22 19 ANB1 -- (c) 2019 Microchip Technology Inc. C1IN3C2IN3- -- -- -- -- IOCB1 INT1(1) Datasheet Preliminary SCL2(3,4) DS40001996C-page 8 PIC18F26/45/46Q10 ...........continued I/O(2) RB2 28-Pin SPDIP, SOIC, SSOP 28-Pin (V)QFN A/D Reference 23 20 ANB2 -- Comparator Timers -- -- CCP CWG -- -- ZCD Interrupt EUSART -- IOCB2 INT2(1) -- DSM MSSP Pullup Basic -- SDI2(1) Y -- SDA2(3,4) RB3 24 21 ANB3 -- C1IN2C2IN2- -- -- -- -- IOCB3 -- -- -- Y -- RB4 25 22 ANB4 -- -- -- -- -- IOCB4 -- -- -- Y -- RB5 26 23 ANB5 -- -- T5G(1) T1G(1) -- -- -- IOCB5 -- -- -- Y -- RB6 27 24 ANB6 -- -- -- -- -- -- IOCB6 -- -- -- Y ICSPCLK RB7 28 25 ANB7 DAC1OUT2 -- T6IN(1) -- -- -- IOCB7 -- -- -- Y ICSPDAT -- T1CKI(1) T3CKI(1) -- -- -- IOCC0 -- -- -- Y SOSCO CCP2(1) -- -- IOCC1 -- -- -- Y SOSCIN SOSCI T5CKI(1) CCP1(1) T2IN(1) -- -- -- IOCC2 -- -- -- Y -- -- -- IOCC3 -- -- SCK1(1) SCL1(3,4) Y -- -- -- SDI1(1) SDA1(3,4) Y -- RC0 11 8 ANC0 -- T3G(1) RC1 12 9 ANC1 -- -- -- RC2 13 10 ANC2 -- -- RC3 14 11 ANC3 -- -- RC4 15 12 ANC4 -- -- -- -- -- -- IOCC4 RC5 16 13 ANC5 -- -- T4IN(1) -- -- -- IOCC5 -- -- -- Y -- RC6 17 14 ANC6 -- -- -- -- -- -- IOCC6 CK1(1,3) -- -- Y -- RC7 18 15 ANC7 -- -- -- -- -- -- IOCC7 RX1/ DT1(1,3) -- -- Y -- RE3 1 26 -- -- -- -- -- -- -- IOCE3 -- -- -- Y Vpp/MCLR VSS 19 16 -- -- -- -- -- -- -- -- -- -- -- -- VDD(5) 20 17 -- -- -- -- -- -- -- -- -- -- -- -- VSS VDD VSS 8 5 -- -- -- -- -- -- -- -- -- -- -- -- VSS OUT(2) -- -- ADGRDA ADGRDB -- C1OUT C2OUT TMR0 CCP1 CCP2 CWG1A CWG1B -- -- DSM SDO1 SCK1 -- -- PWM3 CWG1C TX1/ CK1(3) DT1(3) PWM4 CWG1D Note: 1. This is a PPS remappable input signal. The input function may be moved from the default location shown to one of several other PORTx pins. Refer to the peripheral input selection table for details on which port pins may be used for this signal. 2. All output signals shown in this row are PPS remappable. These signals may be mapped to output onto one of several PORTx pin options as described in the peripheral output selection table. 3. 4. This is a bidirectional signal. For normal module operation, the firmware should map this signal to the same pin in both the PPS input and PPS output registers. These pins are configured for I2C logic levels; The SCLx/SDAx signals may be assigned to any of these pins. PPS assignments to the other pins (e.g., RB1) will operate, but input logic levels will be standard TTL/ST as selected by the INLVL register, instead of the I2C specific or SMBus input buffer thresholds. 5. A 0.1 uF bypass capacitor to VSS is required on the VDD pin. Table 4. 40/44-Pin Allocation Table I/O(2) 40-Pin PDIP 4044-Pin Pin TQFP QFN A/D Reference Comparator Timers CCP CWG ZCD Interrupt EUSART DSM MSSP Pullup Basic RA0 2 17 19 ANA0 -- C1INOC2IN0- -- -- -- -- IOCA0 -- -- -- Y -- RA1 3 18 20 ANA1 -- C1IN1- -- -- -- -- IOCA1 -- -- -- Y -- C2IN1- (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 9 PIC18F26/45/46Q10 ...........continued I/O(2) RA2 40-Pin PDIP 4 4044-Pin Pin TQFP QFN 19 21 A/D ANA2 Reference Comparator Timers DSM MSSP Pullup Basic -- -- -- Y -- IOCA3 -- MDCARL(1) -- Y -- IOCA4 -- MDCARH(1) -- Y -- SS1(1) CCP CWG -- -- -- -- IOCA2 C1IN1+ -- -- -- -- -- T0CKI(1) -- -- -- DAC1OUT1 C1IN0+ VREF(DAC5) C2IN0+ ZCD Interrupt EUSART VREF(ADC) RA3 5 20 22 ANA3 VREF+ (DAC5) VREF+ (ADC) RA4 6 21 23 ANA4 -- RA5 7 22 24 ANA5 -- -- -- -- -- -- IOCA5 -- MDSRC(1) Y -- RA6 14 29 31 ANA6 -- -- -- -- -- -- IOCA6 -- -- -- Y CLKOUT RA7 13 28 30 ANA7 -- -- -- -- -- -- IOCA7 -- -- -- Y RB0 33 8 8 ANB0 -- C2IN1+ -- -- CWG1(1) ZCDIN IOCB0 -- -- SS2(1) Y -- -- -- SCK2(1) Y -- Y -- OSC2 OSC1 CLKIN INT0(1) RB1 34 9 9 ANB1 -- C1IN3- -- -- -- -- INT1(1) C2IN3RB2 35 10 10 ANB2 -- -- IOCB1 -- -- -- -- IOCB2 SCL2(3,4) -- -- INT2(1) RB3 36 11 11 ANB3 -- RB4 37 12 14 ANB4 -- RB5 38 13 15 ANB5 -- C1IN2- SDI2(1) SDA2(3,4) -- -- -- -- IOCB3 -- -- -- Y -- -- T5G(1) -- -- -- IOCB4 -- -- -- Y -- -- T1G(1) -- -- -- IOCB5 -- -- -- Y -- -- -- Y ICSPCLK C2IN2- RB6 39 14 16 ANB6 -- -- -- -- -- -- IOCB6 CK2(1,3) -- -- -- IOCB7 RX2/ DT2(1,3) -- -- Y ICSPDAT -- -- -- IOCC0 -- -- -- Y SOSCO CCP2(1) -- -- IOCC1 -- -- -- Y SOSCIN RB7 40 15 17 ANB7 DAC1OUT2 -- T6IN(1) RC0 15 30 32 ANC0 -- -- T1CKI(1) T3CKI(1) T3G(1) RC1 16 31 35 ANC1 -- -- -- SOSCI RC2 RC3 17 18 32 33 36 37 ANC2 ANC3 -- -- -- -- T5CKI(1) CCP1(1) T2IN(1) -- -- -- -- -- IOCC2 IOCC3 -- -- -- -- Y -- -- SCK1(1) Y -- -- -- SCL1(3,4) RC4 23 38 42 ANC4 -- -- -- -- -- -- IOCC4 -- -- SDI1(1) SDA1(3,4) RC5 24 39 43 ANC5 -- -- T4IN(1) -- -- -- IOCC5 -- -- -- Y -- RC6 25 40 44 ANC6 -- -- -- -- -- -- IOCC6 CK1(1,3) -- -- Y -- RC7 26 1 1 ANC7 -- -- -- -- -- -- IOCC7 RX1/ DT1(1,3) -- -- Y -- RD0 19 34 38 AND0 -- -- -- -- -- -- -- -- -- -- Y -- RD1 20 35 39 AND1 -- -- -- -- -- -- -- -- -- -- Y -- (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 10 PIC18F26/45/46Q10 ...........continued 4044-Pin Pin TQFP QFN I/O(2) 40-Pin PDIP DSM MSSP Pullup Basic RD2 21 36 40 AND2 -- -- -- -- -- Y -- RD3 22 37 41 AND3 -- -- -- -- -- Y -- RD4 27 2 2 AND4 RD5 28 3 3 AND5 -- -- -- -- -- Y -- -- -- -- -- -- Y -- RD6 29 4 4 -- -- -- -- -- -- Y -- RD7 30 5 -- -- -- -- -- -- -- Y -- RE0 8 RE1 9 -- -- -- -- -- -- -- -- Y -- -- -- -- -- -- -- -- -- Y -- RE2 -- -- -- -- -- -- -- -- -- Y -- -- -- -- -- -- -- IOCE3 -- -- -- Y Vpp/MCLR -- -- -- -- -- -- -- -- -- -- -- VSS -- -- -- -- -- -- -- -- -- -- -- -- VDD 28 -- -- -- -- -- -- -- -- -- -- -- -- VSS 29 -- -- -- -- -- -- -- -- -- -- -- -- VSS -- ADGRDA -- C1OUT TMR0 CCP1 CCP2 CWG1A -- -- TX1/ CK1(3) DSM SDO1 SCK1 -- -- A/D Reference Comparator Timers CCP CWG -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- AND6 -- -- -- -- 5 AND7 -- -- -- 23 25 ANE0 -- -- 24 26 ANE1 -- -- 10 25 27 ANE2 -- RE3 1 16 18 -- VSS 12 6 6 -- VDD(5) 11 7 7 VDD(5) 32 26 VSS 31 27 OUT(2) -- -- ADGRDB C2OUT PWM3 PWM4 ZCD Interrupt EUSART CWG1B CWG1C CWG1D DT1(3) SDO2 TX2/ CK2(3) SCK2 DT2(3) Note: 1. This is a PPS remappable input signal. The input function may be moved from the default location shown to one of several other PORTx pins. Refer to the peripheral input selection table for details on which port pins may be used for this signal. 2. All output signals shown in this row are PPS remappable. These signals may be mapped to output onto one of several PORTx pin options as described in the peripheral output selection table. 3. This is a bidirectional signal. For normal module operation, the firmware should map this signal to the same pin in both the PPS input and PPS output registers. 4. These pins are configured for I2C logic levels; The SCLx/SDAx signals may be assigned to any of these pins. PPS assignments to the other pins (e.g., RB1) will operate, but input logic levels will be standard TTL/ST as selected by the INLVL register, instead of the I2C specific or SMBus input buffer thresholds. 5. A 0.1 uF bypass capacitor to VSS is required on all VDD pins. (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 11 PIC18F26/45/46Q10 Table of Contents Description.......................................................................................................................1 Core Features..................................................................................................................1 Memory............................................................................................................................1 Operating Characteristics................................................................................................ 2 Power-Saving Operation Modes......................................................................................2 Digital Peripherals........................................................................................................... 2 Analog Peripherals.......................................................................................................... 3 Clocking Structure........................................................................................................... 3 Programming/Debug Features........................................................................................ 4 PIC18F26/45/46Q10 Family Types................................................................................. 4 Packages.........................................................................................................................5 Pin Diagrams................................................................................................................... 6 Pin Allocation Tables....................................................................................................... 8 1. Device Overview......................................................................................................15 2. Guidelines for Getting Started with PIC18F26/45/46Q10 Microcontrollers............. 23 3. Device Configuration............................................................................................... 28 4. Oscillator Module (with Fail-Safe Clock Monitor).....................................................44 5. Reference Clock Output Module............................................................................. 66 6. Power-Saving Operation Modes..............................................................................72 7. (PMD) Peripheral Module Disable........................................................................... 81 8. Resets..................................................................................................................... 90 9. (WWDT) Windowed Watchdog Timer....................................................................104 10. Memory Organization............................................................................................ 116 11. (NVM) Nonvolatile Memory Control.......................................................................151 (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 12 PIC18F26/45/46Q10 12. 8x8 Hardware Multiplier.........................................................................................180 13. (CRC) Cyclic Redundancy Check Module with Memory Scanner.........................185 14. Interrupts............................................................................................................... 206 15. I/O Ports................................................................................................................ 237 16. Interrupt-on-Change.............................................................................................. 285 17. (PPS) Peripheral Pin Select Module......................................................................301 18. Timer0 Module.......................................................................................................312 19. Timer1 Module with Gate Control.......................................................................... 321 20. Timer2 Module.......................................................................................................341 21. Capture/Compare/PWM Module........................................................................... 368 22. (PWM) Pulse-Width Modulation............................................................................ 384 23. (ZCD) Zero-Cross Detection Module.....................................................................393 24. (CWG) Complementary Waveform Generator Module..........................................401 25. (CLC) Configurable Logic Cell...............................................................................431 26. (DSM) Data Signal Modulator Module...................................................................454 27. (MSSP) Master Synchronous Serial Port Module................................................. 469 28. (EUSART) Enhanced Universal Synchronous Asynchronous Receiver Transmitter ...............................................................................................................................533 29. (FVR) Fixed Voltage Reference.............................................................................568 30. Temperature Indicator Module...............................................................................573 31. (DAC) 5-Bit Digital-to-Analog Converter Module................................................... 576 32. (ADC2) Analog-to-Digital Converter with Computation Module............................. 582 33. (CMP) Comparator Module................................................................................... 630 34. (HLVD) High/Low-Voltage Detect.......................................................................... 643 35. Register Summary.................................................................................................651 36. In-Circuit Serial ProgrammingTM (ICSPTM) .............................................................662 37. Instruction Set Summary....................................................................................... 665 (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 13 PIC18F26/45/46Q10 38. Development Support............................................................................................764 39. Electrical Specifications.........................................................................................769 40. DC and AC Characteristics Graphs and Tables.................................................... 801 41. Packaging Information...........................................................................................802 42. Revision History.....................................................................................................824 The Microchip Web Site.............................................................................................. 825 Customer Change Notification Service........................................................................825 Customer Support....................................................................................................... 825 Product Identification System...................................................................................... 826 Microchip Devices Code Protection Feature............................................................... 826 Legal Notice.................................................................................................................827 Trademarks................................................................................................................. 827 Quality Management System Certified by DNV...........................................................828 Worldwide Sales and Service......................................................................................829 (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 14 PIC18F26/45/46Q10 Device Overview 1. Device Overview This document contains device specific information for the following devices: * PIC18F26Q10 * PIC18F45Q10 * PIC18F46Q10 This family offers the advantages of all PIC18 microcontrollers - namely, high computational performance at an economical price - with the addition of high-endurance Program Flash Memory. In addition to these features, the PIC18F26/45/46Q10 family introduces design enhancements that make these microcontrollers a logical choice for many high-performance, power sensitive applications. 1.1 New Core Features 1.1.1 Low-Power Technology All of the devices in the PIC18F26/45/46Q10 family incorporate a range of features that can significantly reduce power consumption during operation. Key items include: * Alternate Run modes: By clocking the microcontroller from the secondary oscillator or the internal oscillator block, power consumption during code execution can be reduced by as much as 90%. * Multiple Idle modes: The controller can also run with its CPU core disabled but the peripherals are still active. In these states, power consumption can be reduced even further, to as little as 4% of normal operation requirements. * On-the-fly mode switching: The Power-Managed modes are invoked by user code during operation, allowing the user to incorporate power-saving ideas into their application's software design. * Peripheral Module Disable: Modules that are not being used in the code can be selectively disabled using the PMD module. This further reduces the power consumption. 1.1.2 Multiple Oscillator Options and Features All of the devices in the PIC18F26/45/46Q10family offer several different oscillator options. The PIC18F26/45/46Q10 family can be clocked from several different sources: * HFINTOSC - 1-64 MHz precision digitally controlled internal oscillator * LFINTOSC - 31 kHz internal oscillator * EXTOSC - External clock (EC) - Low-power oscillator (LP) - Medium power oscillator (XT) - High power oscillator (HS) * SOSC - Secondary oscillator circuit optimized for 31 kHz clock crystals * A Phase Lock Loop (PLL) frequency multiplier (4x) is available to the External Oscillator modes enabling clock speeds of up to 64 MHz (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 15 PIC18F26/45/46Q10 Device Overview * Fail-Safe Clock Monitor: This option constantly monitors the main clock source against a reference signal provided by the LFINTOSC. If a clock failure occurs, the controller is switched to the internal oscillator block, allowing for continued operation or a safe application shutdown. 1.2 Other Special Features * Memory Endurance: The Flash cells for both program memory and data EEPROM are rated to last for many thousands of erase/write cycles - up to 10K for program memory and 100K for EEPROM. Data retention without refresh is conservatively estimated to be greater than 40 years. * Self-programmability: These devices can write to their own program memory spaces under internal software control. By using a boot loader routine located in the protected Boot Block at the top of program memory, it becomes possible to create an application that can update itself in the field. * Extended Instruction Set: The PIC18F26/45/46Q10 family includes an optional extension to the PIC18 instruction set, which adds eight new instructions and an Indexed Addressing mode. This extension, enabled as a device configuration option, has been specifically designed to optimize reentrant application code originally developed in high-level languages, such as C. * Enhanced Peripheral Pin Select: The Peripheral Pin Select (PPS) module connects peripheral inputs and outputs to the device I/O pins. Only digital signals are included in the selections. All analog inputs and outputs remain fixed to their assigned pins. * Enhanced Addressable EUSART: This serial communication module is capable of standard RS-232 operation and provides support for the LIN bus protocol. Other enhancements include automatic baud rate detection and a 16-bit Baud Rate Generator for improved resolution. When the microcontroller is using the internal oscillator block, the EUSART provides stable operation for applications that talk to the outside world without using an external crystal (or its accompanying power requirement). * 10-bit A/D Converter with Computation: This module incorporates programmable acquisition time, allowing for a channel to be selected and a conversion to be initiated without waiting for a sampling period and thus, reduce code overhead. It has a new module called ADC2 with computation features, which provides a digital filter and threshold interrupt functions. * Windowed Watchdog Timer (WWDT): - Timer monitoring of overflow and underflow events - Variable prescaler selection - Variable window size selection - All sources configurable in hardware or software 1.3 Details on Individual Family Members Devices in the PIC18F26/45/46Q10 family are available in 28-pin and 40/44-pin packages. The block diagram for this device is shown in Figure 1-1. The devices have the following differences: 1. 2. 3. 4. 5. 6. Program Flash Memory Data Memory SRAM Data Memory EEPROM A/D channels I/O ports Enhanced USART (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 16 PIC18F26/45/46Q10 Device Overview 7. Input Voltage Range/Power Consumption All other features for devices in this family are identical. These are summarized in the following Device Features table. The pinouts for all devices are listed in the pin summary tables. Table 1-1. Device Features Features PIC18F26Q10 PIC18F45Q10 PIC18F46Q10 Program Memory (Bytes) 65536 32768 65536 Program Memory (Instructions) 32768 16384 32768 Data Memory (Bytes) 3615 2048 3615 Data EEPROM Memory (Bytes) 1024 256 1024 A,B,C,E(1) A,B,C,D,E A,B,C,D,E Capture/Compare/PWM Modules (CCP) 2 2 2 10-Bit Pulse-Width Modulator (PWM) 2 2 2 4 internal 24 external 4 internal 35 external 4 internal 35 external 28-pin SPDIP 28-pin SOIC 28-pin SSOP 28-pin VQFN 28-pin QFN 40-pin PDIP 40-pin QFN 44-pin TQFP 40-pin PDIP 40-pin QFN 44-pin TQFP 4/3 4/3 4/3 2 MSSP, 2 EUSART 2 MSSP, 2 EUSART 2 MSSP, 2 EUSART Enhanced Complementary Waveform Generator (ECWG) 1 1 1 Zero-Cross Detect (ZCD) 1 1 1 Data Signal Modulator (DSM) 1 1 1 Configurable Logic Cell (CLC) 8 8 8 Yes Yes Yes I/O Ports 10-Bit Analog-to-Digital Module (ADC2) with Computation Accelerator Packages Timers (16-/8-bit) Serial Communications Peripheral Pin Select (PPS) (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 17 PIC18F26/45/46Q10 Device Overview ...........continued Features PIC18F26Q10 PIC18F45Q10 PIC18F46Q10 Peripheral Module Disable (PMD) Yes Yes Yes 16-bit CRC with NVMSCAN Yes Yes Yes Programmable High/LowVoltage Detect (HLVD) Yes Yes Yes Programmable Brown-out Reset (BOR) Yes Yes Yes POR, BOR, RESET Instruction, POR, BOR, RESET Instruction, POR, BOR, RESET Instruction, Stack Overflow, Stack Overflow, Stack Overflow, Stack Underflow Stack Underflow Stack Underflow (PWRT, OST), (PWRT, OST), (PWRT, OST), MCLR, WDT MCLR, WDT MCLR, WDT 75 Instructions; 83 with Extended Instruction Set enabled 75 Instructions; 83 with Extended Instruction Set enabled 75 Instructions; 83 with Extended Instruction Set enabled DC - 64 MHz DC - 64 MHz DC - 64 MHz Resets (and Delays) Instruction Set Operating Frequency Note 1: PORTE contains the single RE3 read-only bit. (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 18 PIC18F26/45/46Q10 Device Overview Figure 1-1. PIC18F26/45/46Q10 Family Block Diagram Rev. 30-000131B 6/14/2017 Data Bus<8> Table Pointer<21> Data Latch 8 8 inc/dec logic Data Memory PCLATU PCLATH 21 PORTA Address Latch 20 PCU PCH PCL Program Counter RA<7:0> 12 Data Address<12> 31-Level Stack 4 BSR Address Latch Program Memory (8/16/32/64 Kbytes) STKPTR 12 Data Latch 8 PORTB 12 RB<7:0> inc/dec logic Table Latch Instruction Bus <16> 4 Access Bank FSR0 FSR1 FSR2 Address Decode ROM Latch PORTC RC<7:0> IR 8 State machine control signals Instruction Decode and Control PRODH PRODL 3 8 W BITOP 8 Internal Oscillator Block Power-up Timer SOSCI LFINTOSC Oscillator SOSCO 64 MHz Oscillator Oscillator Start-up Timer Power-on Reset OSC1(2) OSC2(2) Single-Supply Programming In-Circuit Debugger MCLR(1) BOR HLVD FVR DAC Note Comparators C1/C2 Brown-out Reset Fail-Safe Clock Monitor NVM Timer0 Controller CCP1 CCP2 PWM3 PWM4 Timer1 Timer3 Timer5 8 Timer2 Timer4 Timer6 RE3 is only available when MCLR functionality is disabled. 2: 3: PORTD and PORTE<2:0> not implemented on 28-pin devices. PORTE RE<2:0>(3) RE3(1) 8 Precision Band Gap Reference MSSP1 EUSART1 ECWG MSSP2 EUSART2 1: 8 ALU<8> ZCD RD<7:0> 8 8 Watchdog Timer PORTD(3) 8x8 Multiply FVR CRC-Scan DSM DAC PMD ADC 10-bit FVR FVR OSC1/CLKIN and OSC2/CLKOUT are only available in select oscillator modes. (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 19 PIC18F26/45/46Q10 Device Overview 1.4 Register and Bit Naming Conventions 1.4.1 Register Names When there are multiple instances of the same peripheral in a device, the Peripheral Control registers will be depicted as the concatenation of a peripheral identifier, peripheral instance, and control identifier. The control registers section will show just one instance of all the register names with an `x' in the place of the peripheral instance number. This naming convention may also be applied to peripherals when there is only one instance of that peripheral in the device to maintain compatibility with other devices in the family that contain more than one. 1.4.2 Bit Names There are two variants for bit names: * Short name: Bit function abbreviation * Long name: Peripheral abbreviation + short name 1.4.2.1 Short Bit Names Short bit names are an abbreviation for the bit function. For example, some peripherals are enabled with the EN bit. The bit names shown in the registers are the short name variant. Short bit names are useful when accessing bits in C programs. The general format for accessing bits by the short name is RegisterNamebits.ShortName. For example, the enable bit, EN, in the CM1CON0 register can be set in C programs with the instruction CM1CON0bits.EN = 1. Short names are generally not useful in assembly programs because the same name may be used by different peripherals in different bit positions. When this occurs, during the include file generation, all instances of that short bit name are appended with an underscore plus the name of the register in which the bit resides to avoid naming contentions. 1.4.2.2 Long Bit Names Long bit names are constructed by adding a peripheral abbreviation prefix to the short name. The prefix is unique to the peripheral, thereby making every long bit name unique. The long bit name for the COG1 enable bit is the COG1 prefix, G1, appended with the enable bit short name, EN, resulting in the unique bit name G1EN. Important: The COG1 peripheral is used as an example. Not all devices have the COG peripheral. Long bit names are useful in both C and assembly programs. For example, in C the COG1CON0 enable bit can be set with the G1EN = 1 instruction. In assembly, this bit can be set with the BSF COG1CON0,G1EN instruction. 1.4.2.3 Bit Fields Bit fields are two or more adjacent bits in the same register. Bit fields adhere only to the short bit naming convention. For example, the three Least Significant bits of the COG1CON0 register contain the Mode Control bits. The short name for this field is MD. There is no long bit name variant. Bit field access is only possible in C programs. The following example demonstrates a C program instruction for setting the COG1 to the Push-Pull mode: COG1CON0bits.MD = 0x5; (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 20 PIC18F26/45/46Q10 Device Overview Individual bits in a bit field can also be accessed with long and short bit names. Each bit is the field name appended with the number of the bit position within the field. For example, the Most Significant mode bit has the short bit name MD2 and the long bit name is G1MD2. The following two examples demonstrate assembly program sequences for setting the COG1 to Push-Pull mode: Example 1: MOVLW ANDWF MOVLW IORWF ~(1<<G1MD1) COG1CON0,F 1<<G1MD2 | 1<<G1MD0 COG1CON0,F Example 2: BSF BCF BSF COG1CON0,G1MD2 COG1CON0,G1MD1 COG1CON0,G1MD0 1.4.3 Register and Bit Naming Exceptions 1.4.3.1 Status, Interrupt, and Mirror Bits Status, interrupt enables, Interrupt flags, and Mirror bits are contained in registers that span more than one peripheral. In these cases, the bit name shown is unique so there is no prefix or short name variant. 1.4.3.2 Legacy Peripherals There are some peripherals that do not strictly adhere to these naming conventions. Peripherals that have existed for many years and are present in almost every device are the exceptions. These exceptions were necessary to limit the adverse impact of the new conventions on legacy code. Peripherals that do adhere to the new convention will include a table in the registers section indicating the long name prefix for each peripheral instance. Peripherals that fall into the exception category will not have this table. These peripherals include, but are not limited to the following: * EUSART * MSSP 1.5 Register Legend The table below describes the conventions for bit types and bit Reset values used in the current data sheet. Table 1-2. Register Legend Value Description RO Read-only bit W Writable bit U Unimplemented bit, read as `0' P Programmable bit `1' Bit is set `0' Bit is cleared x Bit is unknown (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 21 PIC18F26/45/46Q10 Device Overview ...........continued Value Description u Bit is unchanged -n/n Value at POR and BOR/Value at all other Resets q Reset Value is determined by hardware f Reset Value is determined by fuse setting g Reset Value at POR for PPS re-mappable signals (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 22 PIC18F26/45/46Q10 Guidelines for Getting Started with PIC18F26/45/46... 2. Guidelines for Getting Started with PIC18F26/45/46Q10 Microcontrollers 2.1 Basic Connection Requirements Getting started with the PIC18F26/45/46Q10 family of 8-bit microcontrollers requires attention to a minimal set of device pin connections before proceeding with development. The following pins must always be connected: * All VDD and VSS pins (see 2.2 Power Supply Pins) * All VDD pins must have a 0.1 uF bypass capacitor to VSS. These pins must also be connected if they are being used in the end application: TM TM * ICSPCLK/ICSPDAT pins used for In-Circuit Serial Programming (ICSP ) and debugging purposes (see 2.4 In-Circuit Serial ProgrammingTM (ICSPTM) Pins) * OSCI and OSCO pins when an external oscillator source is used (see 2.5 External Oscillator Pins) 10-000249C.vsd * MCLR pin (see 2.3 MasterFilename: Clear (MCLR) Pin) when external master clear configuration is selected. Title: Getting Started on PIC18 Additionally, the following pins Last mayEdit: be required:5/1/2018 First Used: PIC18FxxQ10 Generic figure showingfor theanalog MCLR, VDD and VSS pin connections. * VREF+/VREF- pins are usedNote: when external voltage reference modules is implemented The minimum mandatory connections are shown in the figure below. Figure 2-1. Recommended Minimum Connections Rev. 10-000249C 5/1/2018 VDD VDD R1 R2 Vss C2 MCLR C1 PIC MCU Vss Key: C1: 0.1 F, 20V ceramic (recommended) R1: 10 k (recommended) R2: 100 to 470 (recommended) C2: 0.1 F, 20V ceramic (required) 2.2 Power Supply Pins 2.2.1 Decoupling Capacitors The use of decoupling capacitors on every pair of power supply pins (VDD and VSS) is required. Consider the following criteria when using decoupling capacitors: (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 23 PIC18F26/45/46Q10 Guidelines for Getting Started with PIC18F26/45/46... * Value and type of capacitor: A 0.1 F (100 nF), 10-20V capacitor is required. The capacitor should be a low-ESR device, with a resonance frequency in the range of 200 MHz and higher. Ceramic capacitors are recommended. * Placement on the printed circuit board: The decoupling capacitors should be placed as close to the pins as possible. It is recommended to place the capacitors on the same side of the board as the device. If space is constricted, the capacitor can be placed on another layer on the PCB using a via; however, ensure that the trace length from the pin to the capacitor is no greater than 0.25 inch (6 mm). * Handling high-frequency noise: If the board is experiencing high-frequency noise (upward of tens of MHz), add a second ceramic type capacitor in parallel to the above described decoupling capacitor. The value of the second capacitor can be in the range of 0.01 F to 0.001 F. Place this second capacitor next to each primary decoupling capacitor. In high-speed circuit designs, consider implementing a decade pair of capacitances as close to the power and ground pins as possible (e.g., 0.1 F in parallel with 0.001 F). * Maximizing performance: On the board layout from the power supply circuit, run the power and return traces to the decoupling capacitors first, and then to the device pins. This ensures that the decoupling capacitors are first in the power chain. Equally important is to keep the trace length between the capacitor and the power pins to a minimum, thereby reducing PCB trace inductance. 2.2.2 Tank Capacitors On boards with power traces running longer than six inches in length, it is suggested to use a tank capacitor for integrated circuits, including microcontrollers, to supply a local power source. The value of the tank capacitor should be determined based on the trace resistance that connects the power supply source to the device, and the maximum current drawn by the device in the application. In other words, select the tank capacitor that meets the acceptable voltage sag at the device. Typical values range from 4.7 F to 47 F. 2.3 Master Clear (MCLR) Pin The MCLR pin provides two specific device functions: Device Reset, and Device Programming and Debugging. If programming and debugging are not required in the end application, a direct connection to VDD may be all that is required. The addition of other components, to help increase the application's resistance to spurious Resets from voltage sags, may be beneficial. A typical configuration is shown in Figure 2-1. Other circuit designs may be implemented, depending on the application's requirements. During programming and debugging, the resistance and capacitance that can be added to the pin must be considered. Device programmers and debuggers drive the MCLR pin. Consequently, specific voltage levels (VIH and VIL) and fast signal transitions must not be adversely affected. Therefore, specific values of R1 and C1 will need to be adjusted based on the application and PCB requirements. For example, it is recommended that the capacitor, C1, be isolated from the MCLR pin during programming and debugging operations by using a jumper as shown in the following figure. The jumper is replaced for normal run-time operations. Any components associated with the MCLR pin should be placed within 0.25 inch (6 mm) of the pin. (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 24 PIC18F26/45/46Q10 Guidelines for Getting Started with PIC18F26/45/46... Figure 2-2. Example of MCLR Pin Connections Rev. 30-000058A 6/23/2017 VDD R1 R2 MCLR JP C1 Note: Note 1: AR1 10 k is recommendedPA 1. R1 10 k is recommended. suggested starting value suggested is 10 k. Ensure that the MCLR pin VIH starting value is 10 k P Ensure that the and VIL specifications are met. MCLR pin VIH and VIL specifications are metP 2. R2 470 will limit any current flowing MCLR from the extended capacitor, C1, in the event of 2: R2 470 into will limit any current flowing into MCLR from the Discharge external capacitorO C1Oor in the MCLR pin breakdown, due to Electrostatic (ESD) Electrical Overstress (EOS). Ensure event of MCLR pin breakdownO due to that the MCLR pin VIH and VIL specifications are met. Electrostatic Discharge DESD( or Electrical Overstress DEOS(PEnsure that the MCLR pin VIH and VIL specifications are metP 2.4 In-Circuit Serial ProgrammingTM (ICSPTM) Pins The ICSPCLK and ICSPDAT pins are used for ICSP and debugging purposes. It is recommended to keep the trace length between the ICSP connector and the ICSP pins on the device as short as possible. If the ICSP connector is expected to experience an ESD event, a series resistor is recommended, with the value in the range of a few tens of ohms, not to exceed 100. Pull-up resistors, series diodes and capacitors on the ICSPCLK and ICSPDAT pins are not recommended as they can interfere with the programmer/debugger communications to the device. If such discrete components are an application requirement, they should be removed from the circuit during programming and debugging. Alternatively, refer to the AC/DC characteristics and timing requirements information in the respective device Flash programming specification for information on capacitive loading limits, and pin input voltage high (VIH) and input low (VIL) requirements. For device emulation, ensure that the "Communication Channel Select" (i.e., ICSPCLK/ICSPDAT pins), programmed into the device, matches the physical connections for the ICSP to the Microchip debugger/ emulator tool. For more information on available Microchip development tools connection requirements, refer to the "Development Support" section. Related Links 38. Development Support 2.5 External Oscillator Pins Many microcontrollers have options for at least two oscillators: a high-frequency primary oscillator and a low-frequency secondary oscillator. The oscillator circuit should be placed on the same side of the board as the device. Place the oscillator circuit close to the respective oscillator pins with no more than 0.5 inch (12 mm) between the circuit components and the pins. The load capacitors should be placed next to the oscillator itself, on the same side of the board. Use a grounded copper pour around the oscillator circuit to isolate it from surrounding circuits. The grounded copper pour should be routed directly to the MCU ground. Do not run any signal traces or (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 25 PIC18F26/45/46Q10 Guidelines for Getting Started with PIC18F26/45/46... power traces inside the ground pour. Also, if using a two-sided board, avoid any traces on the other side of the board where the crystal is placed. Layout suggestions are shown in the following figure. In-line packages may be handled with a singlesided layout that completely encompasses the oscillator pins. With fine-pitch packages, it is not always possible to completely surround the pins and components. A suitable solution is to tie the broken guard sections to a mirrored ground layer. In all cases, the guard trace(s) must be returned to ground. Figure 2-3. Suggested Placement of the Oscillator Circuit Rev. 30-000059A 4/6/2017 Single-Sided and In-Line Layouts: Copper Pour (tied to ground) Primary Oscillator Crystal DEVICE PINS Primary Oscillator OSC1 C1 OSC2 GND C2 SOSCO SOSCI Secondary Oscillator (SOSC) Crystal SOSC: C1 SOSC: C2 Fine-Pitch (Dual-Sided) Layouts: Top Layer Copper Pour (tied to ground) Bottom Layer Copper Pour (tied to ground) OSCO C2 Oscillator Crystal GND C1 OSCI DEVICE PINS In planning the application's routing and I/O assignments, ensure that adjacent port pins, and other signals in close proximity to the oscillator, are benign (i.e., free of high frequencies, short rise and fall times, and other similar noise). For additional information and design guidance on oscillator circuits, refer to these Microchip Application Notes, available at the corporate website (www.microchip.com): (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 26 PIC18F26/45/46Q10 Guidelines for Getting Started with PIC18F26/45/46... * * * * (R) AN826, "Crystal Oscillator Basics and Crystal Selection for rfPICTM and PICmicro Devices" (R) AN849, "Basic PICmicro Oscillator Design" (R) AN943, "Practical PICmicro Oscillator Analysis and Design" AN949, "Making Your Oscillator Work" Related Links 4. Oscillator Module (with Fail-Safe Clock Monitor) 2.6 Unused I/Os Unused I/O pins should be configured as outputs and driven to a logic low state. Alternatively, connect a 1 k to 10 k resistor to VSS on unused pins to drive the output to logic low. (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 27 PIC18F26/45/46Q10 Device Configuration 3. Device Configuration Device configuration consists of Configuration Words, Code Protection, Device ID and Rev ID. 3.1 Configuration Words There are six Configuration Words that allow the user to select the device oscillator, reset, and memory protection options. These are implemented as Configuration Word 1 through Configuration Word 6 at 300000h through 30000Bh. Important: The DEBUG bit in Configuration Words is managed automatically by device development tools including debuggers and programmers. For normal device operation, this bit should be maintained as a `1'. 3.2 Code Protection Code protection allows the device to be protected from unauthorized access. Program memory protection and data memory protection are controlled independently. Internal access to the program memory is unaffected by any code protection setting. 3.2.1 Program Memory Protection The entire program memory space is protected from external reads and writes by the CP bit. When CP = 0, external reads and writes of program memory are inhibited and a read will return all `0's. The CPU can continue to read program memory, regardless of the protection bit settings. Self-writing the program memory is dependent upon the write protection setting. 3.2.2 Data Memory Protection The entire data EEPROM memory space is protected from external reads and writes by the CPD bit. When CPD = 0, external reads and writes of data EEPROM memory are inhibited and a read will return all `0's. The CPU can continue to read data EEPROM memory regardless of the protection bit settings. 3.3 Write Protection Write protection allows the device to be protected from unintended self-writes. Applications, such as boot loader software, can be protected while allowing other regions of the program memory to be modified. The WRT bits define the size of the program memory block that is protected. 3.4 User ID 256 bytes in the memory space (200000h-20000FFh) are designated as ID locations where the user can store checksum or other code identification numbers. These locations are readable and writable during normal execution. See the "User ID, Device ID and Configuration Word Access" section for more information on accessing these memory locations. For more information on checksum calculation, see the "PIC18F26/45/46Q10 Memory Programming Specification", (DS40001874). (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 28 PIC18F26/45/46Q10 Device Configuration 3.5 Device ID and Revision ID The 16-bit Device ID word is located at 0x3FFFFE and the 16-bit revision ID is located at 0x3FFFFC. These locations are read-only and cannot be erased or modified. Development tools, such as device programmers and debuggers, may be used to read the Device ID, Revision ID and Configuration Words. Refer to the "Nonvolatile Memory (NVM) Control" section for more information on accessing these locations. Related Links 11. (NVM) Nonvolatile Memory Control (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 29 PIC18F26/45/46Q10 Device Configuration 3.6 Register Summary - Configuration Words Address Name 0x300000 CONFIG1 0x300002 CONFIG2 0x300004 CONFIG3 0x300006 CONFIG4 0x300008 CONFIG5 0x30000A CONFIG6 3.7 Bit Pos. 7:0 RSTOSC[2:0] 15:8 FCMEN 7:0 15:8 FEXTOSC[2:0] BOREN[1:0] XINST 7:0 CSWEN PWRTE DEBUG STVREN PPS1WAY WDTE[1:0] 15:8 ZCD MCLRE BORV[1:0] WDTCPS[4:0] WDTCCS[2:0] 7:0 15:8 CLKOUTEN LPBOREN WDTCWS[2:0] WRT3 LVP SCANE WRT2 WRT1 WRT0 WRTD WRTB WRTC CPD CP EBTR1 EBTR0 7:0 15:8 7:0 EBTR3 15:8 EBTR2 EBTRB Register Definitions: Configuration Words (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 30 PIC18F26/45/46Q10 Device Configuration 3.7.1 CONFIG1 Name: Address: CONFIG1 0x300000 Configuration Word 1 Oscillators Bit 15 14 Access Reset Bit 7 6 13 12 11 10 Reset 8 FCMEN CSWEN CLKOUTEN R/W R/W R/W 1 1 1 5 4 3 2 RSTOSC[2:0] Access 9 1 0 FEXTOSC[2:0] R/W R/W R/W R/W R/W R/W 1 1 1 1 1 1 Bit 13 - FCMEN Fail-Safe Clock Monitor Enable bit Value Description 1 Fail-Safe Clock Monitor enabled 0 Fail-Safe Clock Monitor disabled Bit 11 - CSWEN Clock Switch Enable bit Value Description 1 Writing to NOSC and NDIV is allowed 0 The NOSC and NDIV bits cannot be changed by user software Bit 8 - CLKOUTEN Clock Out Enable bit If FEXTOSC = HS, XT, LP, then this bit is ignored. Otherwise: Value Description 1 CLKOUT function is disabled; I/O function on OSC2 0 CLKOUT function is enabled; FOSC/4 clock appears at OSC2 Bits 6:4 - RSTOSC[2:0] Power-up Default Value for COSC bits This value is the Reset default value for COSC and selects the oscillator first used by user software. Refer to COSC operation. Value Description 111 EXTOSC operating per FEXTOSC bits (device manufacturing default) 110 HFINTOSC with HFFRQ = 4 MHz and CDIV = 4:1 101 LFINTOSC 100 SOSC 011 Reserved 010 EXTOSC with 4x PLL, with EXTOSC operating per FEXTOSC bits 001 Reserved 000 HFINTOSC with HFFRQ = 64 MHz and CDIV = 1:1. Resets COSC/NOSC to b'110'. Bits 2:0 - FEXTOSC[2:0] FEXTOSC External Oscillator Mode Selection bits (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 31 PIC18F26/45/46Q10 Device Configuration Value 111 110 101 100 011 010 001 000 Description ECH (external clock) above 16 MHz ECM (external clock) for 500 kHz to 16 MHz ECL (external clock) below 500 kHz Oscillator not enabled Reserved (do not use) HS (crystal oscillator) above 4 MHz XT (crystal oscillator) above 500 kHz, below 4 MHz LP (crystal oscillator) optimized for 32.768 kHz Related Links 4.6.5 OSCFRQ 4.6.2 OSCCON2 (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 32 PIC18F26/45/46Q10 Device Configuration 3.7.2 CONFIG2 Name: Address: CONFIG2 0x300002 Configuration Word 2 Supervisor Bit 15 Access 13 12 11 10 XINST 14 DEBUG STVREN PPS1WAY ZCD 9 8 BORV[1:0] R/W R/W R/W R/W R/W R/W R/W Reset 1 1 1 1 1 1 1 Bit 7 5 4 3 2 6 BOREN[1:0] Access Reset 1 0 LPBOREN PWRTE MCLRE R/W R/W R/W R/W R/W 0 1 1 1 1 Bit 15 - XINST Extended Instruction Set Enable bit Value Description 1 Extended Instruction Set and Indexed Addressing mode disabled (Legacy mode) 0 Extended Instruction Set and Indexed Addressing mode enabled Bit 13 - DEBUG Debugger Enable bit Value Description 1 Background debugger disabled 0 Background debugger enabled Bit 12 - STVREN Stack Overflow/Underflow Reset Enable bit Value Description 1 Stack Overflow or Underflow will cause a Reset 0 Stack Overflow or Underflow will not cause a Reset Bit 11 - PPS1WAY PPSLOCKED bit One-Way Set Enable bit Value Description 1 The PPSLOCKED bit can only be set once after an unlocking sequence is executed; once PPSLOCK is set, all future changes to PPS registers are prevented 0 The PPSLOCKED bit can be set and cleared as needed (provided an unlocking sequence is executed) Bit 10 - ZCD ZCD Disable bit Value Description 1 ZCD disabled. ZCD can be enabled by setting the ZCDSEN bit of ZCDCON 0 ZCD always enabled, PMDx[ZCDMD] bit is ignored Bits 9:8 - BORV[1:0] Brown-out Reset Voltage Selection bit Value Description 11 Brown-out Reset Voltage (VBOR) set to 1.90V (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 33 PIC18F26/45/46Q10 Device Configuration ...........continued Value Description 10 Brown-out Reset Voltage (VBOR) set to 2.45V 01 Brown-out Reset Voltage (VBOR) set to 2.7V 00 Brown-out Reset Voltage (VBOR) set to 2.85V Bits 7:6 - BOREN[1:0] Brown-out Reset Enable bits When enabled, Brown-out Reset Voltage (VBOR) is set by BORV bit Value Description 11 Brown-out Reset enabled, SBOREN bit is ignored 10 Brown-out Reset enabled while running, disabled in Sleep; SBOREN is ignored 01 Brown-out Reset enabled according to SBOREN 00 Brown-out Reset disabled Bit 5 - LPBOREN Low-Power BOR Enable bit Value Description 1 Low-Power Brown-out Reset is disabled 0 Low-Power Brown-out Reset is enabled Bit 1 - PWRTE Power-up Timer Enable bit Value Description 1 PWRT disabled 0 PWRT enabled Bit 0 - MCLRE Master Clear (MCLR) Enable bit Value Condition Description x If LVP = 1 RE3 pin function is MCLR 1 If LVP = 0 MCLR pin is MCLR 0 If LVP = 0 MCLR pin function is port defined function Note: BORV - The higher voltage setting is recommended for operation at or above 16 MHz. Related Links 7.4.3 PMD2 (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 34 PIC18F26/45/46Q10 Device Configuration 3.7.3 CONFIG3 Name: Address: CONFIG3 0x300004 Configuration Word 3 Windowed Watchdog Timer Bit 15 14 13 12 11 10 WDTCCS[2:0] Access 7 WDTCWS[2:0] R/W R/W R/W R/W R/W 1 1 1 1 1 1 5 4 3 2 1 0 6 WDTE[1:0] Access 8 R/W Reset Bit 9 WDTCPS[4:0] R/W R/W R/W R/W R/W R/W R/W 1 1 1 1 1 1 1 Reset Bits 13:11 - WDTCCS[2:0] WDT Input Clock Selector bits Value Condition Description x WDTE=00 These bits have no effect 111 WDTE00 Software Control 110 to WDTE00 Reserved (Default to LFINTOSC) 010 001 WDTE00 WDT reference clock is the 31.25 kHz MFINTOSC 000 WDTE00 WDT reference clock is the 31.0 kHz LFINTOSC (default value) Bits 10:8 - WDTCWS[2:0] WDT Window Select bits WDTCON1[WINDOW] at POR WDTCWS Value Window delay Percent of time Window opening Percent of time 111 111 n/a 100 110 110 n/a 100 101 101 25 75 100 100 37.5 62.5 011 011 50 50 010 010 62.5 37.5 001 001 75 25 000 000 87.5 12.5 Software control of WINDOW Keyed access required? Yes No No Yes Bits 6:5 - WDTE[1:0] WDT Operating Mode bits Value Description 11 WDT enabled regardless of Sleep; SEN bit in WDTCON0 is ignored 10 WDT enabled while Sleep = 0, suspended when Sleep = 1; SEN bit in WDTCON0 is ignored (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 35 PIC18F26/45/46Q10 Device Configuration Value 01 00 Description WDT enabled/disabled by SEN bit in WDTCON0 WDT disabled, SEN bit in WDTCON0 is ignored Bits 4:0 - WDTCPS[4:0] WDT Period Select bits WDTCON0[WDTPS] at POR WDTCPS Typical Time-Out (FIN = 31 kHz) Software Control of WDTPS? 216 2s Yes 1:32 25 1 ms No 10010 1:8388608 223 256s 10001 10001 1:4194304 222 128s 10000 10000 1:2097152 221 64s 01111 01111 1:1048576 220 32s 01110 01110 1:524299 219 16s 01101 01101 1:262144 218 8s 01100 01100 1:131072 217 4s 01011 01011 1:65536 216 2s 01010 01010 1:32768 215 1s 01001 01001 1:16384 214 512 ms 01000 01000 1:8192 213 256 ms 00111 00111 1:4096 212 128 ms 00110 00110 1:2048 211 64 ms 00101 00101 1:1024 210 32 ms 00100 00100 1:512 29 16 ms 00011 00011 1:256 28 8 ms 00010 00010 1:128 27 4 ms 00001 00001 1:64 26 2 ms 00000 00000 1:32 25 1 ms Value Divider Ratio 11111 01011 1:65536 11110 ... 10011 11110 ... 10011 10010 (c) 2019 Microchip Technology Inc. Datasheet Preliminary No DS40001996C-page 36 PIC18F26/45/46Q10 Device Configuration 3.7.4 CONFIG4 Name: Address: CONFIG4 0x300006 Configuration Word 4 Memory Write Protection Bit 15 14 Access Reset Bit 7 6 13 12 11 10 9 8 LVP SCANE WRTD WRTB WRTC R/W R/W R/W R/W R/W 1 1 1 1 1 5 4 3 2 1 0 WRT3 WRT2 WRT1 WRT0 R/W R/W R/W R/W 1 1 1 1 Access Reset Bit 13 - LVP Low-Voltage Programming Enable bit The LVP bit cannot be written (to zero) while operating from the LVP programming interface. The purpose of this rule is to prevent the user from dropping out of LVP mode while programming from LVP mode, or accidentally eliminating LVP mode from the Configuration state. Value Description 1 Low-voltage programming enabled. MCLR/VPP pin function is MCLR. MCLRE Configuration bit is ignored. 0 HV on MCLR/VPP must be used for programming Bit 12 - SCANE Scanner Enable bit Value Description 1 Scanner module is available for use, PMD0[SCANMD] bit enables the module 0 Scanner module is NOT available for use, PMD0[SCANMD] bit is ignored Bit 10 - WRTD Data EEPROM Write Protection bit Value Description 1 Data EEPROM NOT write-protected 0 Data EEPROM write-protected Bit 9 - WRTB Boot Block Write Protection bit Value Description 1 Boot Block NOT write-protected 0 Boot Block write-protected Bit 8 - WRTC Configuration Register Write Protection bit Value Description 1 Configuration Registers NOT write-protected 0 Configuration Registers write-protected Bits 0, 1, 2, 3 - WRTn User NVM Self-Write Protection bits Value Description 1 Corresponding Memory Block NOT write-protected (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 37 PIC18F26/45/46Q10 Device Configuration Value 0 Description Corresponding Memory Block write-protected Related Links 10.1 Program Memory Organization 11.3.4 Operation During Code-Protect and Write-Protect (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 38 PIC18F26/45/46Q10 Device Configuration 3.7.5 CONFIG5 Name: Address: CONFIG5 0x300008 Configuration Word 5 Code Protection Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Access Reset Bit Access Reset CPD CP RO RO 1 1 Bit 1 - CPD Data NVM (DFM) Memory Code Protection bit Value Description 1 Data NVM code protection disabled 0 Data NVM code protection enabled Bit 0 - CP Value 1 0 User NVM Program Memory Code Protection bit Description User NVM code protection disabled User NVM code protection enabled (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 39 PIC18F26/45/46Q10 Device Configuration 3.7.6 CONFIG6 Name: Address: CONFIG6 0x30000A Configuration Word 6 Memory Read Protection Bit 15 14 13 12 11 10 9 8 EBTRB Access R/W Reset Bit 1 7 6 5 Access Reset 4 3 2 1 0 EBTR3 EBTR2 EBTR1 EBTR0 R/W R/W R/W R/W 1 1 1 1 Bit 9 - EBTRB Table Read Protection bit Value Description 1 Memory Boot Block NOT protected from table reads executed in other blocks 0 Memory Boot Block protected from table reads executed in other blocks Bits 0, 1, 2, 3 - EBTRn Table Read Protection bits Value Description 1 Corresponding Memory Block NOT protected from table reads executed in other blocks 0 Corresponding Memory Block protected from table reads executed in other blocks Related Links 10.1 Program Memory Organization (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 40 PIC18F26/45/46Q10 Device Configuration 3.8 Register Summary - Device and Revision Address Name 0x3FFFFC REVISION ID 0x3FFFFE 3.9 DEVICE ID Bit Pos. 7:0 15:8 MJRREV[1:0] MNRREV[5:0] 1010[3:0] MJRREV[5:2] 7:0 DEV[7:0] 15:8 DEV[15:8] Register Definitions: Device and Revision (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 41 PIC18F26/45/46Q10 Device Configuration 3.9.1 DEVICE ID Name: Address: DEVICE ID 0x3FFFFE Device ID Register Bit 15 14 13 12 11 10 9 8 DEV[15:8] Access RO RO RO RO RO RO RO RO Reset q q q q q q q q Bit 7 6 5 4 3 2 1 0 RO RO RO RO RO RO RO RO q q q q q q q q DEV[7:0] Access Reset Bits 15:0 - DEV[15:0] Device ID bits Device Device ID PIC18F26Q10 7180h PIC18F45Q10 7140h PIC18F46Q10 7120h (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 42 PIC18F26/45/46Q10 Device Configuration 3.9.2 REVISION ID Name: Address: REVISION ID 0x3FFFFC Revision ID Register Bit 15 14 13 12 11 10 1010[3:0] Access 9 8 MJRREV[5:2] RO RO RO RO RO RO RO RO Reset 1 0 1 0 q q q q Bit 7 6 5 4 3 2 1 0 RO RO RO RO RO RO RO RO q q q q q q q q MJRREV[1:0] Access Reset MNRREV[5:0] Bits 15:12 - 1010[3:0] Read as `1010' These bits are fixed with value `1010' for all devices in this family. Bits 11:6 - MJRREV[5:0] Major Revision ID bits These bits are used to identify a major revision. A major revision is indicated by an all-layer revision (A0, B0, C0, etc.). Revision A = b'00 0000' Bits 5:0 - MNRREV[5:0] Minor Revision ID bits These bits are used to identify a minor revision. (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 43 PIC18F26/45/46Q10 Oscillator Module (with Fail-Safe Clock Monitor) 4. Oscillator Module (with Fail-Safe Clock Monitor) 4.1 Overview The oscillator module has multiple clock sources and selection features that allow it to be used in a wide range of applications while maximizing performance and minimizing power consumption. Figure 4-1 illustrates a block diagram of the oscillator module. Clock sources can be supplied from external oscillators, quartz-crystal resonators and ceramic resonators. In addition, the system clock source can be supplied from one of two internal oscillators and PLL circuits, with a choice of speeds selectable via software. Additional clock features include: * Selectable system clock source between external or internal sources via software. * Fail-Safe Clock Monitor (FSCM) designed to detect a failure of the external clock source (LP, XT, HS, ECH, ECM, ECL) and switch automatically to the internal oscillator. * Oscillator Start-up Timer (OST) ensures stability of crystal oscillator sources. The RSTOSC bits of Configuration Word 1 determine the type of oscillator that will be used when the device runs after Reset, including when it is first powered up. If an external clock source is selected, the FEXTOSC bits of Configuration Word 1 must be used in conjunction with the RSTOSC bits to select the External Clock mode. The external oscillator module can be configured in one of the following clock modes, by setting the FEXTOSC<2:0> bits of Configuration Word 1: * ECL - External Clock Low-Power mode (below 100 kHz) * ECM - External Clock Medium Power mode (100 kHz to 16 MHz) * ECH - External Clock High-Power mode (above 16 MHz) * LP - 32 kHz Low-Power Crystal mode * XT - Medium Gain Crystal or Ceramic Resonator Oscillator mode (between 500 kHz and 4 MHz) * HS - High Gain Crystal or Ceramic Resonator mode (above 4 MHz) The ECH, ECM, and ECL Clock modes rely on an external logic level signal as the device clock source. The LP, XT, and HS Clock modes require an external crystal or resonator to be connected to the device. Each mode is optimized for a different frequency range. The internal oscillator block produces low and high-frequency clock sources, designated LFINTOSC and HFINTOSC. Multiple device clock frequencies may be derived from these clock sources. (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 44 Filename: Title: Last Edit: First Used: Notes: 10-000208D.vsd Simplified Clock Source Block Diagram for PIC18(L)F2x/4x/6xK40 5/10/2016 PIC18(L)F2x/4x/6xK40 (MVAE,MVAF,MVAB,MVAC,MVAK) PIC18F26/45/46Q10 Oscillator Module (with Fail-Safe Clock Monitor) (R) Figure 4-1. Simplified PIC MCU Clock Source Block Diagram Rev. 10-000208D 5/10/2016 CLKIN/OSC1 External Oscillator (EXTOSC) CLKOUT/OSC2 CDIV<4:0> 4x PLL COSC<2:0> Secondary Oscillator (SOSC) SOSCO LFINTOSC 31 kHz Oscillator HFINTOSC 512 1001 111 256 1000 010 128 0111 100 64 0110 32 0101 16 0100 8 0011 Post-Divider SOSCIN/SOSCI 101 110 011 Reserved 001 4 0010 000 2 Sleep Reserved 0001 1 Idle 0000 LFINTOSC is used to monitor system clock System Clock SYSCMD Reserved FRQ<3:0> 1,2,4,8,12,16,32,48,64 MHz Oscillator Sleep Peripheral Clock FSCM MFINTOSC To Peripherals 31.25 kHz and 500 kHz Oscillator To Peripherals To Peripherals To Peripherals Related Links 3.7.1 CONFIG1 4.2 Clock Source Types Clock sources can be classified as external or internal. External clock sources rely on external circuitry for the clock source to function. Examples are: oscillator modules (ECH, ECM, ECL mode), quartz crystal resonators or ceramic resonators (LP, XT and HS modes). Internal clock sources are contained within the oscillator module. The internal oscillator block has two internal oscillators that are used to generate internal system clock sources. The High-Frequency Internal Oscillator (HFINTOSC) can produce 1, 2, 4, 8, 12, 16, 32, 48 and 64 MHz clock. The frequency can be controlled through the OSCFRQ register. The Low-Frequency Internal Oscillator (LFINTOSC) generates a fixed 31 kHz frequency. A 4x PLL is provided that can be used in conjunction with the external clock. The system clock can be selected between external or internal clock sources via the NOSC bits. The system clock can be made available on the OSC2/CLKOUT pin for any of the modes that do not use the OSC2 pin. The clock out functionality is governed by the CLKOUTEN bit in the CONFIG1H register. If enabled, the clock out signal is always at a frequency of FOSC/4. Related Links 4.6.5 OSCFRQ 4.2.1.4 4x PLL (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 45 PIC18F26/45/46Q10 Oscillator Module (with Fail-Safe Clock Monitor) 4.3 Clock Switching 4.2.1 External Clock Sources An external clock source can be used as the device system clock by performing one of the following actions: * Program the RSTOSC<2:0> and FEXTOSC<2:0> bits in the Configuration Words to select an external clock source that will be used as the default system clock upon a device Reset. * Write the NOSC<2:0> and NDIV<3:0> bits to switch the system clock source. Related Links 4.3 Clock Switching 4.2.1.1 EC Mode The External Clock (EC) mode allows an externally generated logic level signal to be the system clock source. When operating in this mode, an external clock source is connected to the OSC1 input. OSC2/ CLKOUT is available for general purpose I/O or CLKOUT. The following figure shows the pin connections for EC mode. EC mode has three power modes to select from through Configuration Words: * ECH - High power, above 16 MHz * ECM - Medium power, 100 kHz-16 MHz * ECL - Low power, below 100 kHz The Oscillator Start-up Timer (OST) is disabled when EC mode is selected. Therefore, there is no delay (R) in operation after a Power-on Reset (POR) or wake-up from Sleep. Because the PIC MCU design is fully static, stopping the external clock input will have the effect of halting the device while leaving all data intact. Upon restarting the external clock, the device will resume operation as if no time had elapsed. Figure 4-2. External Clock (EC) Mode Operation Rev. 30-000060A 4/6/2017 OSC1/CLKIN Clock from Ext. System PIC(R) MCU FOSC/4 or I/O(1) OSC2/CLKOUT Note: 1. Output depends upon CLKOUTEN bit of the Configuration Words (CONFIG1H). 4.2.1.2 LP, XT, HS Modes The LP, XT and HS modes support the use of quartz crystal resonators or ceramic resonators connected to OSC1 and OSC2 (Figure 4-3). The three modes select a low, medium or high gain setting of the internal inverter-amplifier to support various resonator types and speed. LP Oscillator mode selects the lowest gain setting of the internal inverter-amplifier. LP mode current consumption is the least of the three modes. This mode is designed to drive only 32.768 kHz tuning-fork type crystals (watch crystals). XT Oscillator mode selects the intermediate gain setting of the internal inverter-amplifier. XT mode current consumption is the medium of the three modes. This mode is best suited to drive resonators with a medium drive level specification (between 100 kHz - 4 MHz). (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 46 PIC18F26/45/46Q10 Oscillator Module (with Fail-Safe Clock Monitor) HS Oscillator mode selects the highest gain setting of the internal inverter-amplifier. HS mode current consumption is the highest of the three modes. This mode is best suited for resonators that require a high drive setting (above 4 MHz). Figure 4-3 and Figure 4-4 show typical circuits for quartz crystal and ceramic resonators, respectively. Figure 4-3. Quartz Crystal Operation (LP, XT or HS Mode) Rev. 30-000061A 4/6/2017 PIC(R) MCU OSC1/CLKIN C1 To Internal Logic Quartz Crystal C2 RS(1) RF(2) Sleep OSC2/CLKOUT Note: 1. A series resistor (RS) may be required for quartz crystals with low drive level. 2. The value of RF varies with the Oscillator mode selected (typically between 2 M to 10 M). Figure 4-4. Ceramic Resonator Operation (XT or HS Mode) Rev. 30-000062A 4/6/2017 PIC(R) MCU OSC1/CLKIN C1 To Internal Logic RP(3) C2 Ceramic RS(1) Resonator RF(2) Sleep OSC2/CLKOUT Note: 1. A series resistor (RS) may be required for ceramic resonators with low drive level. 2. The value of RF varies with the Oscillator mode selected (typically between 2 M to 10 M). 3. An additional parallel feedback resistor (RP) may be required for proper ceramic resonator operation. 4.2.1.3 Oscillator Start-up Timer (OST) If the oscillator module is configured for LP, XT or HS modes, the Oscillator Start-up Timer (OST) counts 1024 oscillations from OSC1. This occurs following a Power-on Reset (POR), or a wake-up from Sleep. The OST ensures that the oscillator circuit, using a quartz crystal resonator or ceramic resonator, has started and is providing a stable system clock to the oscillator module. 4.2.1.4 4x PLL The oscillator module contains a 4x PLL that can be used with the external clock sources to provide a system clock source. The input frequency for the PLL must fall within specifications. (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 47 PIC18F26/45/46Q10 Oscillator Module (with Fail-Safe Clock Monitor) The PLL can be enabled for use by one of two methods: 1. Program the RSTOSC bits in the Configuration Word 1 to `010' (enable EXTOSC with 4x PLL). 2. Write the NOSC bits to `010' (enable EXTOSC with 4x PLL). Related Links 39.4.3 PLL Specifications 4.2.1.5 Secondary Oscillator The secondary oscillator is a separate oscillator block that can be used as an alternate system clock source. The secondary oscillator is optimized for 32.768 kHz, and can be used with an external crystal oscillator connected to the SOSCI and SOSCO device pins, or an external clock source connected to the SOSCIN pin. The secondary oscillator can be selected during run-time using clock switching. Figure 4-5. Quartz Crystal Operation (Secondary Oscillator) Rev. 30-000063A 4/6/2017 PIC(R) MCU SOSCI C1 To Internal Logic 32.768 kHz Quartz Crystal C2 SOSCO Note: 1. Quartz crystal characteristics vary according to type, package and manufacturer. The user should consult the manufacturer data sheets for specifications and recommended application. 2. Always verify oscillator performance over the VDD and temperature range that is expected for the application. 3. For oscillator design assistance, reference the following Microchip Application Notes: (R) (R) - AN826, "Crystal Oscillator Basics and Crystal Selection for PIC and PIC Devices" (DS00826) (R) - AN849, "Basic PIC Oscillator Design" (DS00849) (R) - AN943, "Practical PIC Oscillator Analysis and Design" (DS00943) - AN949, "Making Your Oscillator Work" (DS00949) - TB097, "Interfacing a Micro Crystal MS1V-T1K 32.768 kHz Tuning Fork Crystal to a PIC16F690/SS" (DS91097) - AN1288, "Design Practices for Low-Power External Oscillators" (DS01288) Related Links 4.3 Clock Switching 4.2.2 Internal Clock Sources The device may be configured to use the internal oscillator block as the system clock by performing one of the following actions: * Program the RSTOSC<2:0> bits in Configuration Words to select the INTOSC clock as the default system clock upon a device Reset. (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 48 PIC18F26/45/46Q10 Oscillator Module (with Fail-Safe Clock Monitor) * Write the NOSC<2:0> bits to switch the system clock source to the internal oscillator during run-time. In INTOSC mode, OSC1/CLKIN is available for general purpose I/O. OSC2/CLKOUT is available for general purpose I/O or CLKOUT. The function of the OSC2/CLKOUT pin is determined by the CLKOUTEN bit in Configuration Words. The internal oscillator block has two independent oscillators that can produce two internal system clock sources. 1. 2. The HFINTOSC (High-Frequency Internal Oscillator) is factory-calibrated and operates from 1 to 64 MHz. The frequency of HFINTOSC can be selected through the OSCFRQ Frequency Selection register, and fine-tuning can be done via the OSCTUNE register. The LFINTOSC (Low-Frequency Internal Oscillator) is factory-calibrated and operates at 31 kHz. Related Links 4.3 Clock Switching 4.6.5 OSCFRQ 4.6.6 OSCTUNE 4.2.2.1 HFINTOSC The High-Frequency Internal Oscillator (HFINTOSC) is a precision digitally-controlled internal clock source that produces a stable clock up to 64 MHz. The HFINTOSC can be enabled through one of the following methods: * Programming the RSTOSC<2:0> bits in Configuration Word 1 to `110' (FOSC = 1 MHz) or `000' (FOSC = 64 MHz) to set the oscillator upon device Power-up or Reset. * Write to the NOSC<2:0> bits during run-time. The HFINTOSC frequency can be selected by setting the HFFRQ<3:0> bits. The NDIV<3:0> bits allow for division of the HFINTOSC output from a range between 1:1 and 1:512. Related Links 4.3 Clock Switching 4.2.2.2 MFINTOSC The module provides two (500 kHz and 31.25 kHz) constant clock outputs. These clocks are digital divisors of the HFINTOSC clock. Dynamic divider logic is used to provide constant MFINTOSC clock rates for all settings of HFINTOSC. The MFINTOSC cannot be used to drive the system but it is used to clock certain modules such as the Timers and WWDT. 4.2.2.3 LFINTOSC The Low-Frequency Internal Oscillator (LFINTOSC) is a factory-calibrated 31 kHz internal clock source. The LFINTOSC is the frequency for the Power-up Timer (PWRT), Windowed Watchdog Timer (WWDT) and Fail-Safe Clock Monitor (FSCM). The LFINTOSC is enabled through one of the following methods: * Programming the RSTOSC<2:0> bits of Configuration Word 1 to enable LFINTOSC. * Write to the NOSC<2:0> bits during run-time. Related Links 4.3 Clock Switching (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 49 PIC18F26/45/46Q10 Oscillator Module (with Fail-Safe Clock Monitor) 4.2.2.4 ADCRC (also referred to as FRC) The ADCRC is an oscillator dedicated to the ADC2 module. The ADCRC oscillator can be manually enabled using the ADOEN bit. The ADCRC runs at a fixed frequency of 600 kHz. ADCRC is automatically enabled if it is selected as the clock source for the ADC2 module. 4.2.3 Oscillator Status and Adjustments 4.2.3.1 Internal Oscillator Frequency Adjustment The internal oscillator is factory-calibrated. This internal oscillator can be adjusted in software by writing to the OSCTUNE register. The default value of the OSCTUNE register is 00h. The value is a 6-bit two's complement number. A value of 1Fh will provide an adjustment to the maximum frequency. A value of 20h will provide an adjustment to the minimum frequency. When the OSCTUNE register is modified, the oscillator frequency will begin shifting to the new frequency. Code execution continues during this shift. There is no indication that the shift has occurred. OSCTUNE does not affect the LFINTOSC frequency. Operation of features that depend on the LFINTOSC clock source frequency, such as the Power-up Timer (PWRT), WWDT, Fail-Safe Clock Monitor (FSCM) and peripherals, are not affected by the change in frequency. Related Links 4.6.6 OSCTUNE 4.2.3.2 Oscillator Status and Manual Enable The Ready status of each oscillator (including the ADCRC oscillator) is displayed in OSCSTAT. The oscillators (but not the PLL) may be explicitly enabled through OSCEN. Related Links 4.6.4 OSCSTAT 4.6.7 OSCEN 4.2.3.3 HFOR and MFOR Bits The HFOR and MFOR bits indicate that the HFINTOSC and MFINTOSC is ready. These clocks are always valid for use at all times, but only accurate after they are ready. When a new value is loaded into the OSCFRQ register, the HFOR and MFOR bits will clear, and set again when the oscillator is ready. During pending OSCFRQ changes the MFINTOSC clock will stall at a high or a low state, until the HFINTOSC resumes operation. 4.3 Clock Switching The system clock source can be switched between external and internal clock sources via software using the New Oscillator Source (NOSC) bits. The following clock sources can be selected using the following: * External oscillator * Internal Oscillator Block (INTOSC) (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 50 PIC18F26/45/46Q10 Oscillator Module (with Fail-Safe Clock Monitor) Important: The Clock Switch Enable bit in Configuration Word 1 can be used to enable or disable the clock switching capability. When cleared, the NOSC and NDIV bits cannot be changed by user software. When set, writing to NOSC and NDIV is allowed and would switch the clock frequency. 4.3.1 New Oscillator Source (NOSC) and New Divider Selection Request (NDIV) Bits The New Oscillator Source (NOSC) and New Divider Selection Request (NDIV) bits select the system clock source and frequency that are used for the CPU and peripherals. When new values of NOSC and NDIV are written to OSCCON1, the current oscillator selection will continue to operate while waiting for the new clock source to indicate that it is stable and ready. In some cases, the newly requested source may already be in use, and is ready immediately. In the case of a divider-only change, the new and old sources are the same, so the source will be ready immediately. The device may enter Sleep while waiting for the switch. When the new oscillator is ready, the New Oscillator Ready (NOSCR) bit is set and also the Clock Switch Interrupt Flag (CSWIF) bit of PIR1 sets. If Clock Switch Interrupts are enabled (CSWIE = 1), an interrupt will be generated at that time. The Oscillator Ready (ORDY) bit can also be polled to determine when the oscillator is ready in lieu of an interrupt. Important: The CSWIF interrupt will not wake the system from Sleep. If the Clock Switch Hold (CSWHOLD) bit is clear, the oscillator switch will occur when the New Oscillator is Ready bit (NOSCR) is set, and the interrupt (if enabled) will be serviced at the new oscillator setting. If CSWHOLD is set, the oscillator switch is suspended, while execution continues using the current (old) clock source. When the NOSCR bit is set, software should: * Set CSWHOLD = 0 so the switch can complete, or * Copy COSC into NOSC to abandon the switch. If DOZE is in effect, the switch occurs on the next clock cycle, whether or not the CPU is operating during that cycle. Changing the clock post-divider without changing the clock source (i.e., changing FOSC from 1 MHz to 2 MHz) is handled in the same manner as a clock source change, as described previously. The clock source will already be active, so the switch is relatively quick. CSWHOLD must be clear (CSWHOLD = 0) for the switch to complete. The current COSC and CDIV are indicated in the OSCCON2 register up to the moment when the switch actually occurs, at which time OSCCON2 is updated and ORDY is set. NOSCR is cleared by hardware to indicate that the switch is complete. Related Links 4.3.3 Clock Switch and Sleep 4.3.2 PLL Input Switch Switching between the PLL and any non-PLL source is managed as described above. The input to the PLL is established when NOSC selects the PLL, and maintained by the COSC setting. (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 51 PIC18F26/45/46Q10 Oscillator Module (with Fail-Safe Clock Monitor) When NOSC and COSC select the PLL with different input sources, the system continues to run using the COSC setting, and the new source is enabled per NOSC. When the new oscillator is ready (and CSWHOLD = 0), system operation is suspended while the PLL input is switched and the PLL acquires lock. This provides a truly glitch-free clock switch operation. Important: If the PLL fails to lock, the FSCM will trigger. 4.3.3 Clock Switch and Sleep If OSCCON1 is written with a new value and the device is put to Sleep before the switch completes, the switch will not take place and the device will enter Sleep mode. When the device wakes from Sleep and the CSWHOLD bit is clear, the device will wake with the `new' clock active, and the Clock Switch Interrupt Flag bit (CSWIF) will be set. When the device wakes from Sleep and the CSWHOLD bit is set, the device will wake with the `old' clock active and the new clock will be requested again. Figure 4-6. Clock Switch (CSWHOLD = 0) Rev. 30-000064A 4/7/2016 OSCCON1 WRITTEN OSC #2 OSC #1 ORDY NOTE 2 NOSCR NOTE 1 CSWIF CSWHOLD USER CLEAR Note 1: CSWIF is asserted coincident with NOSCR; interrupt is serviced at OSC#2 speed. Note: 2: The assertion of NOSCR is hidden from the user because it appears only for the duration of the switch. 1. CSWIF is asserted coincident with NOSCR; interrupt is serviced at OSC#2 speed. 2. The assertion of NOSCR is hidden from the user because it appears only for the duration of the switch. (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 52 PIC18F26/45/46Q10 Oscillator Module (with Fail-Safe Clock Monitor) Figure 4-7. Clock Switch (CSWHOLD = 1) Rev. 30-000065A 4/6/2017 OSCCON1 WRITTEN OSC #1 OSC #2 ORDY NOSCR NOTE 1 CSWIF USER CLEAR CSWHOLD Note 1: CSWIF is asserted coincident with NOSCR, and may be cleared before or after clearing CSWHOLD = 0. Note: 1. CSWIF is asserted coincident with NOSCR, and may be cleared before or after clearing CSWHOLD = 0. Figure 4-8. Clock Switch Abandoned Rev. 30-000066A 4/6/2017 OSCCON1 WRITTEN OSCCON1 WRITTEN OSC #1 ORDY NOTE 2 NOSCR CSWIF NOTE 1 CSWHOLD Note: 1. CSWIF may be cleared before or after rewriting OSCCON1; CSWIF is not automatically cleared. 2. ORDY = 0 if OSCCON1 does not match OSCCON2; a new switch will begin. 4.4 Fail-Safe Clock Monitor The Fail-Safe Clock Monitor (FSCM) allows the device to continue operating should the external oscillator fail. The FSCM is enabled by setting the FCMEN bit in the Configuration Words. The FSCM is applicable to all external Oscillator modes (LP, XT, HS, ECL/M/H and Secondary Oscillator). (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 53 PIC18F26/45/46Q10 Oscillator Module (with Fail-Safe Clock Monitor) Figure 4-9. FSCM Block Diagram Clock Monitor Latch External Clock LFINTOSC Oscillator / 64 31 kHz D~32 usd 488 Hz D~2 msd S Q R Q Sample Clock Rev. 30-000067A 4/6/2017 Clock Failure Detected 4.4.1 Fail-Safe Detection The FSCM module detects a failed oscillator by comparing the external oscillator to the FSCM sample clock. The sample clock is generated by dividing the LFINTOSC by 64. See Figure 4-9. Inside the fail detector block is a latch. The external clock sets the latch on each falling edge of the external clock. The sample clock clears the latch on each rising edge of the sample clock. A failure is detected when an entire half-cycle of the sample clock elapses before the external clock goes low. 4.4.2 Fail-Safe Operation When the external clock fails, the FSCM overwrites the COSC bits to select HFINTOSC (3'b110). The frequency of HFINTOSC would be determined by the previous state of the HFFRQ bits and the NDIV/ CDIV bits. The bit flag OSCFIF of the PIR1 register is set. Setting this flag will generate an interrupt if the OSCFIE bit of the PIE1 register is also set. The device firmware can then take steps to mitigate the problems that may arise from a failed clock. The system clock will continue to be sourced from the internal clock source until the device firmware successfully restarts the external oscillator and switches back to external operation, by writing to the NOSC and NDIV bits. 4.4.3 Fail-Safe Condition Clearing The Fail-Safe condition is cleared after a Reset, executing a SLEEP instruction or changing the NOSC and NDIV bits. When switching to the external oscillator or PLL, the OST is restarted. While the OST is running, the device continues to operate from the INTOSC selected in OSCCON1. When the OST times out, the Fail-Safe condition is cleared after successfully switching to the external clock source. The OSCFIF bit should be cleared prior to switching to the external clock source. If the Fail-Safe condition still exists, the OSCFIF flag will again become set by hardware. 4.4.4 Reset or Wake-up from Sleep The FSCM is designed to detect an oscillator failure after the Oscillator Start-up Timer (OST) has expired. The OST is used after waking up from Sleep and after any type of Reset. The OST is not used with the EC Clock modes so that the FSCM will be active as soon as the Reset or wake-up has completed. (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 54 PIC18F26/45/46Q10 Oscillator Module (with Fail-Safe Clock Monitor) Figure 4-10. FSCM Timing Diagram Rev. 30-000068A 4/6/2017 Sample Clock Oscillator Failure System Clock Output Clock Monitor Output (Q) Failure Detected OSCFIF Test Test Test Note: The system clock is normally at a much higher frequency than the sample clock. The relative frequencies in this example have been chosen for clarity. (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 55 PIC18F26/45/46Q10 Oscillator Module (with Fail-Safe Clock Monitor) 4.5 Register Summary - OSC Address Name Bit Pos. 0x0ED3 OSCCON1 7:0 0x0ED4 OSCCON2 7:0 0x0ED5 OSCCON3 7:0 NOSC[2:0] NDIV[3:0] COSC[2:0] CSWHOLD SOSCPWR CDIV[3:0] ORDY NOSCR 0x0ED6 OSCSTAT 7:0 EXTOR HFOR MFOR LFOR SOR ADOR 0x0ED7 OSCEN 7:0 EXTOEN HFOEN MFOEN LFOEN SOSCEN ADOEN 0x0ED8 OSCTUNE 7:0 0x0ED9 OSCFRQ 7:0 4.6 PLLR HFTUN[5:0] HFFRQ[3:0] Register Definitions: Oscillator Control (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 56 PIC18F26/45/46Q10 Oscillator Module (with Fail-Safe Clock Monitor) 4.6.1 OSCCON1 Name: Address: OSCCON1 0xED3 Oscillator Control Register1 Bit 7 6 5 4 3 2 NOSC[2:0] Access Reset 1 0 NDIV[3:0] R/W R/W R/W R/W R/W R/W R/W f f f f f f f Bits 6:4 - NOSC[2:0] New Oscillator Source Request bits(1,2,3) The setting requests a source oscillator and PLL combination per Table 4-2. Table 4-1. Default Oscillator Settings CONFIG1[RSTOSC] SFR Reset Values (fff ffff) NOSC/COSC NDIV/CDIV 111 111 0000 110 110 0010 101 101 0000 100 100 0000 011 Initial FOSC Frequency OSCFRQ EXTOSC per FEXTOSC 4 MHz FOSC = 1 MHz (4 MHz/4) LFINTOSC SOSC Reserved 010 010 0000 001 4 MHz EXTOSC + 4xPLL(4) Reserved 000 110 0000 64 MHz FOSC = 64 MHz Table 4-2. NOSC Bit Settings NOSC<2:0> Clock Source 111 EXTOSC(5) 110 HFINTOSC(6) 101 LFINTOSC 100 SOSC 011 Reserved 010 EXTOSC + 4x PLL(7) 001 Reserved 000 Reserved Bits 3:0 - NDIV[3:0] New Divider Selection Request bits(2,3) The setting determines the new postscaler division ratio per Table 4-3. (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 57 PIC18F26/45/46Q10 Oscillator Module (with Fail-Safe Clock Monitor) Table 4-3. NDIV Bit Settings NDIV<3:0> Clock Divider 1111-1010 Reserved 1001 512 1000 256 0111 128 0110 64 0101 32 0100 16 0011 8 0010 4 0001 2 0000 1 Note: 1. The default value (f/f) is determined by the CONFIG1[RSTOSC] Configuration bits. See Table 4-1. 2. If NOSC is written with a reserved value (Table 4-2), the operation is ignored and NOSC is not written. 3. When CONFIG1[CSWEN] = 0, this register is read-only and cannot be changed from the POR value. 4. EXTOSC must meet the PLL specifications. 5. EXTOSC configured by CONFIG1[FEXTOSC]. 6. HFINTOSC frequency is set with the HFFRQ bits. 7. EXTOSC must meet the PLL specifications. Related Links 3.7.1 CONFIG1 39.4.3 PLL Specifications (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 58 PIC18F26/45/46Q10 Oscillator Module (with Fail-Safe Clock Monitor) 4.6.2 OSCCON2 Name: Address: OSCCON2 0xED4 Oscillator Control Register 2 Bit 7 6 5 4 3 2 COSC[2:0] 1 0 CDIV[3:0] Access R R R R R R R Reset q q q q q q q Bits 6:4 - COSC[2:0] Current Oscillator Source Select bits (read-only)(1,2) Indicates the current source oscillator and PLL combination as shown in the following table. Table 4-4. COSC Bit Settings COSC/NOSC Clock Source 111 EXTOSC(3) 110 HFINTOSC(4) 101 LFINTOSC 100 SOSC 011 Reserved 010 EXTOSC + 4x PLL(5) 001 Reserved 000 Reserved Bits 3:0 - CDIV[3:0] Current Divider Select bits (read-only)(1,2) Indicates the current postscaler division ratio as shown in the follwing table. Table 4-5. CDIV Bit Settings CDIV/NDIV Clock Divider 1111-1010 Reserved 1001 512 1000 256 0111 128 0110 64 0101 32 0100 16 0011 8 0010 4 0001 2 (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 59 PIC18F26/45/46Q10 Oscillator Module (with Fail-Safe Clock Monitor) ...........continued CDIV/NDIV Clock Divider 0000 1 Note: 1. The POR value is the value present when user code execution begins. 2. The Reset value (q/q) is the same as the NOSC/NDIV bits. 3. EXTOSC configured by the CONFIG1[FEXTOSC] bits. 4. HFINTOSC frequency is set with the HFFRQ bits. 5. EXTOSC must meet the PLL specifications. Related Links 3.7.1 CONFIG1 39.4.3 PLL Specifications (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 60 PIC18F26/45/46Q10 Oscillator Module (with Fail-Safe Clock Monitor) 4.6.3 OSCCON3 Name: Address: OSCCON3 0xED5 Oscillator Control Register 3 Bit Access Reset 7 6 4 3 CSWHOLD SOSCPWR 5 ORDY NOSCR R/W/HC R/W RO RO 0 0 0 0 2 1 0 Bit 7 - CSWHOLD Clock Switch Hold bit Value Description 1 Clock switch will hold (with interrupt) when the oscillator selected by NOSC is ready 0 Clock switch may proceed when the oscillator selected by NOSC is ready; when NOSCR becomes `1', the switch will occur Bit 6 - SOSCPWR Secondary Oscillator Power Mode Select bit Value Description 1 Secondary oscillator operating in High-Power mode 0 Secondary oscillator operating in Low-Power mode Bit 4 - ORDY Oscillator Ready bit (read-only) Value Description 1 OSCCON1 = OSCCON2; the current system clock is the clock specified by NOSC 0 A clock switch is in progress Bit 3 - NOSCR New Oscillator is Ready bit (read-only)(1) Value Description 1 A clock switch is in progress and the oscillator selected by NOSC indicates a ready condition 0 A clock switch is not in progress, or the NOSC-selected oscillator is not yet ready Note: 1. If CSWHOLD = 0, the user may not see this bit set because the bit is set for less than one instruction cycle. (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 61 PIC18F26/45/46Q10 Oscillator Module (with Fail-Safe Clock Monitor) 4.6.4 OSCSTAT Name: Address: OSCSTAT 0xED6 Oscillator Status Register 1 Bit Access Reset 7 6 5 4 3 2 EXTOR HFOR MFOR LFOR SOR ADOR 1 PLLR 0 RO RO RO RO RO RO RO q q q q q q q Bit 7 - EXTOR EXTOSC (external) Oscillator Ready bit Value Description 1 The oscillator is ready to be used 0 The oscillator is not enabled, or is not yet ready to be used Bit 6 - HFOR HFINTOSC Oscillator Ready bit Value Description 1 The oscillator is ready to be used 0 The oscillator is not enabled, or is not yet ready to be used Bit 5 - MFOR MFINTOSC Oscillator Ready bit Value Description 1 The oscillator is ready to be used 0 The oscillator is not enabled, or is not yet ready to be used Bit 4 - LFOR LFINTOSC Oscillator Ready bit Value Description 1 The oscillator is ready to be used 0 The oscillator is not enabled, or is not yet ready to be used Bit 3 - SOR Secondary (Timer1) Oscillator Ready bit Value Description 1 The oscillator is ready to be used 0 The oscillator is not enabled, or is not yet ready to be used Bit 2 - ADOR ADC Oscillator Ready bit Value Description 1 The oscillator is ready to be used 0 The oscillator is not enabled, or is not yet ready to be used Bit 0 - PLLR PLL Ready bit Value Description 1 The PLL is ready to be used 0 The PLL is not enabled, the required input source is not ready, or the PLL is not locked. (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 62 PIC18F26/45/46Q10 Oscillator Module (with Fail-Safe Clock Monitor) 4.6.5 OSCFRQ Name: Address: OSCFRQ 0xED9 HFINTOSC Frequency Selection Register Bit 7 6 5 4 3 2 1 0 HFFRQ[3:0] Access Reset R/W R/W R/W R/W q q q q Bits 3:0 - HFFRQ[3:0] HFINTOSC Frequency Selection bits HFFRQ Nominal Freq (MHz) 1001 1010 1111 1110 Reserved 1101 1100 1011 1000(1) 64 0111 48 0110 32 0101 16 0100 12 0011 8 0010(1) 4 0001 2 0000 1 Note: 1. Refer to Table 4-1 for more information. (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 63 PIC18F26/45/46Q10 Oscillator Module (with Fail-Safe Clock Monitor) 4.6.6 OSCTUNE Name: Address: OSCTUNE 0xED8 HFINTOSC Tuning Register Bit 7 6 5 4 3 2 1 0 HFTUN[5:0] Access Reset R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 Bits 5:0 - HFTUN[5:0] HFINTOSC Frequency Tuning bits Value Description 01 1111 Maximum frequency 00 0000 Center frequency. Oscillator module is running at the calibrated frequency (default value). 10 0000 Minimum frequency (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 64 PIC18F26/45/46Q10 Oscillator Module (with Fail-Safe Clock Monitor) 4.6.7 OSCEN Name: Address: OSCEN 0xED7 Oscillator Manual Enable Register Bit Access Reset 7 6 5 4 3 2 EXTOEN HFOEN MFOEN LFOEN SOSCEN ADOEN R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 1 0 Bit 7 - EXTOEN External Oscillator Manual Request Enable bit Value Description 1 EXTOSC is explicitly enabled, operating as specified by CONFIG1[FEXTOSC] 0 EXTOSC is only enabled if requested by a peripheral Bit 6 - HFOEN HFINTOSC Oscillator Manual Request Enable bit Value Description 1 HFINTOSC is explicitly enabled, operating as specified by OSCFRQ 0 HFINTOSC is only enabled if requested by a peripheral Bit 5 - MFOEN MFINTOSC (500 kHz/31.25 kHz) Oscillator Manual Request Enable bit (Derived from HFINTOSC) Value Description 1 MFINTOSC is explicitly enabled 0 MFINTOSC is only enabled if requested by a peripheral Bit 4 - LFOEN LFINTOSC (31 kHz) Oscillator Manual Request Enable bit Value Description 1 LFINTOSC is explicitly enabled 0 LFINTOSC is only enabled if requested by a peripheral Bit 3 - SOSCEN Secondary Oscillator Manual Request Enable bit Value Description 1 Secondary Oscillator is explicitly enabled, operating as specified by SOSCPWR 0 Secondary Oscillator is only enabled if requested by a peripheral Bit 2 - ADOEN ADC Oscillator Manual Request Enable bit Value Description 1 ADC oscillator is explicitly enabled 0 ADC oscillator is only enabled if requested by a peripheral (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 65 PIC18F26/45/46Q10 Reference Clock Output Module Reference Clock Output Module The reference clock output module provides the ability to send a clock signal to the clock reference output pin (CLKR). The reference clock output can also be routed internally as a signal for other peripherals, such as the Data Signal Modulator (DSM), memory scanner, and timer module. The reference clock output module has the following features: Filename: 10-000261B.vsd Clock SourceBlock Using the CLKRCLK Register Title:* SelectableClock Reference Diagram With Selectable Clock Source Last Edit: 5/11/2016 * Programmable Clock Divider First Used: PIC18(L)F2x/4x/6xK40 (MVAF,MVAE,MVAB,MVAC,MVAK) * Selectable Duty Cycle Notes: Figure 5-1. Clock Reference Block Diagram Rev. 10-000261B 5/11/2016 DIV EN See CLKRCLK Register Filename: Title: Last Edit: First Used: Notes: Counter Reset Reference Clock Divider 5. 128 111 64 110 32 101 16 100 8 011 10-000264B.vsd 4 010 Clock Reference Timing 5/25/2016 2 001 PIC18(L)F2x/4x/6xK40 (MVAF,MVAE,MVAB,MVAC,MVAK) CLK RxyPPS DC CLKR Duty Cycle PPS To Peripherals 000 EN Figure 5-2. Clock Reference Timing P1 Rev. 10-000264B 5/25/2016 P2 CLKRCLK CLKREN CLKR Output CLKRDIV<2:0> = 001 CLKRDC<1:0> = 10 CLKR Output CLKRDIV<2:0> = 001 CLKRDC<1:0> = 01 (c) 2019 Microchip Technology Inc. Duty Cycle (50%) CLKRCLK/2 Duty Cycle (25%) Datasheet Preliminary DS40001996C-page 66 PIC18F26/45/46Q10 Reference Clock Output Module 5.1 Clock Source The clock source of the reference clock peripheral is selected with the CLK bits. The available clock sources are listed in the following table: Table 5-1. CLKR Clock Sources 5.1.1 CLK Clock Source 1111 LC8_out 1110 LC7_out 1101 LC6_out 1100 LC5_out 1011 LC4_out 1010 LC3_out 1001 LC2_out 1000 LC1_out 0111-0101 0101 0100 SOSC 0011 MFINTOSC (500 kHz) 0010 LFINTOSC (31 kHz) 0001 HFINTOSC 0000 FOSC Clock Synchronization The CLKR output signal is ensured to be glitch-free when the EN bit is set to start the module and enable the CLKR output. When the reference clock output is disabled, the output signal will be disabled immediately. Clock dividers and clock duty cycles can be changed while the module is enabled but doing so may cause glitches to occur on the output. To avoid possible glitches, clock dividers and clock duty cycles should be changed only when the EN bit is clear. 5.2 Programmable Clock Divider The module takes the clock input and divides it based on the value of the DIV bits. The following configurations are available: * * * * * Base FOSC value FOSC divided by 2 FOSC divided by 4 FOSC divided by 8 FOSC divided by 16 (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 67 PIC18F26/45/46Q10 Reference Clock Output Module * FOSC divided by 32 * FOSC divided by 64 * FOSC divided by 128 The clock divider values can be changed while the module is enabled. However, in order to prevent glitches on the output, the DIV bits should only be changed when the module is disabled (EN = 0). 5.3 Selectable Duty Cycle The DC bits are used to modify the duty cycle of the output clock. A duty cycle of 0%, 25%, 50%, or 75% can be selected for all clock rates when the DIV value is not 0b000. When DIV=0b000 then the duty cycle defaults to 50% for all values of DC except 0b00 in which case the duty cycle is 0% (constant low output). The duty cycle can be changed while the module is enabled. However, in order to prevent glitches on the output, the DC bits should only be changed when the module is disabled (EN = 0). Important: The DC value at reset is 10. This makes the default duty cycle 50% and not 0%. 5.4 Operation in Sleep Mode The reference clock module continues to operate and provide a signal output in Sleep for all clock source selections except FOSC (CLK=0). (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 68 PIC18F26/45/46Q10 Reference Clock Output Module 5.5 Register Summary: Reference CLK Address Name Bit Pos. 0x0F39 CLKRCON 7:0 0x0F3A CLKRCLK 7:0 5.6 EN DC[1:0] DIV[2:0] CLK[3:0] Register Definitions: Reference Clock Long bit name prefixes for the Reference Clock peripherals are shown in the following table. Refer to the "Long Bit Names" section for more information. Table 5-2. TABLE 5-1: Peripheral Bit Name Prefix CLKR CLKR Related Links 1.4.2.2 Long Bit Names (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 69 PIC18F26/45/46Q10 Reference Clock Output Module 5.6.1 CLKRCON Name: Address: CLKRCON 0xF39 Reference Clock Control Register Bit 7 6 5 4 EN Access Reset 3 2 DC[1:0] 1 0 DIV[2:0] R/W R/W R/W R/W R/W R/W 0 1 0 0 0 0 Bit 7 - EN Reference Clock Module Enable bit Value Description 1 Reference clock module enabled 0 Reference clock module is disabled Bits 4:3 - DC[1:0] Reference Clock Duty Cycle bits(1) Value Description 11 Clock outputs duty cycle of 75% 10 Clock outputs duty cycle of 50% 01 Clock outputs duty cycle of 25% 00 Clock outputs duty cycle of 0% Bits 2:0 - DIV[2:0] Reference Clock Divider bits Value Description 111 Base clock value divided by 128 110 Base clock value divided by 64 101 Base clock value divided by 32 100 Base clock value divided by 16 011 Base clock value divided by 8 010 Base clock value divided by 4 001 Base clock value divided by 2 000 Base clock value Note: 1. Bits are valid for reference clock divider values of two or larger, the base clock cannot be further divided. (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 70 PIC18F26/45/46Q10 Reference Clock Output Module 5.6.2 CLKRCLK Name: Address: CLKRCLK 0xF3A Clock Reference Clock Selection MUX Bit 7 6 5 4 3 2 1 0 CLK[3:0] Access Reset R/W R/W R/W R/W 0 0 0 0 Bits 3:0 - CLK[3:0] CLKR Clock Selection bits See the Clock Sources table. (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 71 PIC18F26/45/46Q10 Power-Saving Operation Modes 6. Power-Saving Operation Modes The purpose of the Power-Down modes is to reduce power consumption. There are three Power-Down modes: * Doze mode * Sleep mode * Idle mode 6.1 Doze Mode Doze mode allows for power-saving by reducing CPU operation and program memory (PFM) access, without affecting peripheral operation. Doze mode differs from Sleep mode because the band gap and system oscillators continue to operate, while only the CPU and PFM are affected. The reduced execution saves power by eliminating unnecessary operations within the CPU and memory. When the Doze Enable bit is set (DOZEN = 1), the CPU executes only one instruction cycle out of every N cycles as defined by the DOZE bits. For example, if DOZE = 001, the instruction cycle ratio is 1:4. The CPU and memory execute for one instruction cycle and then lay idle for three instruction cycles. During the unused cycles, the peripherals continue to operate at the system clock speed. 6.1.1 Doze Operation The Doze operation is illustrated in Figure 6-1 . For this example: * Doze enabled (DOZEN = 1) * DOZE = 001 (1:4) ratio * Recover-on-Interrupt enabled (ROI = 1) As with normal operation, the PFM fetches for the next instruction cycle. The Q-clocks to the peripherals continue throughout. Figure 6-1. DOZE MODE OPERATION EXAMPLE (DOZE<2:0> = 001, 1:4) Rev. 3000089A 4/11/2017 6.1.2 Interrupts During Doze If an interrupt occurs and the Recover-On-Interrupt bit is clear (ROI = 0) at the time of the interrupt, the Interrupt Service Routine (ISR) continues to execute at the rate selected by DOZE<2:0>. Interrupt latency is extended by the DOZE<2:0> ratio. If an interrupt occurs and the ROI bit is set (ROI = 1) at the time of the interrupt, the DOZEN bit is cleared and the CPU executes at full speed. The prefetched instruction is executed and then the interrupt vector (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 72 PIC18F26/45/46Q10 Power-Saving Operation Modes sequence is executed. In Figure 6-1, the interrupt occurs during the 2nd instruction cycle of the Doze period, and immediately brings the CPU out of Doze. If the Doze-On-Exit (DOE) bit is set (DOE = 1) when the RETFIE operation is executed, DOZEN is set, and the CPU executes at the reduced rate based on the DOZE<2:0> ratio. Figure 6-2. Doze Software Example //Mainline operation bool somethingToDo = FALSE: void main() { initializeSystem(); // DOZE = 64:1 (for example) // ROI = 1; GIE = 1; // enable interrupts while (1) { // If ADC completed, process data if (somethingToDo) { doSomething(); DOZEN = 1; // resume low-power } } } // Data interrupt handler void interrupt() { // DOZEN = 0 because ROI = 1 if (ADIF) { somethingToDo = TRUE; DOE = 0; // make main() go fast ADIF = 0; } // else check other interrupts... if (TMR0IF) { timerTick++; DOE = 1; // make main() go slow TMR0IF = 0; } } 6.2 Sleep Mode Sleep mode is entered by executing the SLEEP instruction, while the Idle Enable (IDLEN) bit of the CPUDOZE register is clear (IDLEN = 0). Upon entering Sleep mode, the following conditions exist: 1. 2. 3. 4. 5. 6. 7. WDT will be cleared but keeps running if enabled for operation during Sleep The PD bit of the STATUS register is cleared The TO bit of the STATUS register is set The CPU clock is disabled LFINTOSC, SOSC, HFINTOSC and ADCRC are unaffected and peripherals using them may continue operation in Sleep. I/O ports maintain the status they had before Sleep was executed (driving high, low, or highimpedance) Resets other than WDT are not affected by Sleep mode Refer to individual chapters for more details on peripheral operation during Sleep. (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 73 PIC18F26/45/46Q10 Power-Saving Operation Modes To minimize current consumption, the following conditions should be considered: * * * * * I/O pins should not be floating External circuitry sinking current from I/O pins Internal circuitry sourcing current from I/O pins Current draw from pins with internal weak pull-ups Modules using any oscillator I/O pins that are high-impedance inputs should be pulled to VDD or VSS externally to avoid switching currents caused by floating inputs. Examples of internal circuitry that might be sourcing current include modules such as the DAC and FVR modules. Related Links 31. (DAC) 5-Bit Digital-to-Analog Converter Module 29. (FVR) Fixed Voltage Reference 6.2.1 Wake-up from Sleep The device can wake-up from Sleep through one of the following events: 1. External Reset input on MCLR pin, if enabled 2. 3. 4. 5. 6. BOR Reset, if enabled Low-Power Brown-Out Reset (LPBOR), if enabled POR Reset Windowed Watchdog Timer, if enabled All interrupt sources except clock switch interrupt can wake-up the part. The first five events will cause a device Reset. The last one event is considered a continuation of program execution. To determine whether a device Reset or wake-up event occurred, refer to the "Determining the Cause of a Reset" section. When the SLEEP instruction is being executed, the next instruction (PC + 2) is prefetched. For the device to wake-up through an interrupt event, the corresponding Interrupt Enable bit must be enabled, as well as the Peripheral Interrupt Enable bit (PEIE = 1), for every interrupt not in PIR0. Wake-up will occur regardless of the state of the GIE bit. If the GIE bit is disabled, the device continues execution at the instruction after the SLEEP instruction. If the GIE bit is enabled, the device executes the instruction after the SLEEP instruction, the device will then call the Interrupt Service Routine. In cases where the execution of the instruction following SLEEP is not desirable, the user should have a NOP after the SLEEP instruction. The WDT is cleared when the device wakes-up from Sleep, regardless of the source of wake-up. Upon a wake from a Sleep event, the core will wait for a combination of three conditions before beginning execution. The conditions are: * PFM Ready * COSC-Selected Oscillator Ready * BOR Ready (unless BOR is disabled) Related Links 8.11 Determining the Cause of a Reset (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 74 PIC18F26/45/46Q10 Power-Saving Operation Modes 6.2.2 Wake-up Using Interrupts When global interrupts are disabled (GIE cleared) and any interrupt source, with the exception of the clock switch interrupt, has both its interrupt enable bit and interrupt flag bit set, one of the following will occur: * If the interrupt occurs before the execution of a SLEEP instruction - SLEEP instruction will execute as a NOP - WDT and WDT prescaler will not be cleared - TO bit of the STATUS register will not be set - PD bit of the STATUS register will not be cleared * If the interrupt occurs during or after the execution of a SLEEP instruction - SLEEP instruction will be completely executed - - - - Device will immediately wake-up from Sleep WDT and WDT prescaler will be cleared TO bit of the STATUS register will be set PD bit of the STATUS register will be cleared Even if the flag bits were checked before executing a SLEEP instruction, it may be possible for flag bits to become set before the SLEEP instruction completes. To determine whether a SLEEP instruction executed, test the PD bit. If the PD bit is set, the SLEEP instruction was executed as a NOP. Figure 6-3. WAKE-UP FROM SLEEP THROUGH INTERRUPT Rev. 3000090A 4/12/2017 CLKIN(1) TOST(3) CLKOUT(2) Interrupt Latency (4) Interrupt flag GIE bit (INTCON reg.) Instruction Flow PC Instruction Fetched Instruction Executed Processor in Sleep PC Inst(PC) = Sleep Inst(PC - 1) PC + 1 PC + 2 PC + 2 PC + 2 Inst(PC + 1) Inst(PC + 2) Sleep Inst(PC + 1) Forced NOP 0004h 0005h Inst(0004h) Inst(0005h) Forced NOP Inst(0004h) Note: 1. External clock. High, Medium, Low mode assumed. 2. CLKOUT is shown here for timing reference. 3. TOST = 1024 TOSC. This delay does not apply to EC and INTOSC Oscillator modes. 4. GIE = 1 assumed. In this case after wake-up, the processor calls the ISR at 0004h. If GIE = 0, execution will continue in-line. 6.2.3 Low-Power Sleep Mode The PIC18F26/45/465Q10 device family contains an internal Low Dropout (LDO) voltage regulator, which allows the device I/O pins to operate at voltages up to 5.5V while the internal device logic operates at a lower voltage. The LDO and its associated reference circuitry must remain active when the device is in Sleep mode. (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 75 PIC18F26/45/46Q10 Power-Saving Operation Modes The PIC18F26/45/465Q10devices allows the user to optimize the operating current in Sleep, depending on the application requirements. Low-Power Sleep mode can be selected by setting the VREGPM bit of the VREGCON register. 6.2.3.1 Sleep Current vs. Wake-up Time In the default operating mode, the LDO and reference circuitry remain in the normal configuration while in Sleep. The device is able to exit Sleep mode quickly since all circuits remain active. In Low-Power Sleep mode, when waking-up from Sleep, an extra delay time is required for these circuits to return to the normal configuration and stabilize. The Low-Power Sleep mode is beneficial for applications that stay in Sleep mode for long periods of time. The Normal mode is beneficial for applications that need to wake from Sleep quickly and frequently. 6.2.3.2 Peripheral Usage in Sleep Some peripherals that can operate in Sleep mode will not operate properly with the Low-Power Sleep mode selected. The Low-Power Sleep mode is intended for use with these peripherals: * * * * Brown-out Reset (BOR) Windowed Watchdog Timer (WWDT) External interrupt pin/Interrupt-On-Change pins Peripherals that run off external secondary clock source It is the responsibility of the end user to determine what is acceptable for their application when setting the VREGPM settings in order to ensure operation in Sleep. 6.3 Idle Mode When IDLEN is set (IDLEN = 1), the SLEEP instruction will put the device into Idle mode. In Idle mode, the CPU and memory operations are halted, but the peripheral clocks continue to run. This mode is similar to Doze mode, except that in IDLE both the CPU and PFM are shut off. Important: If CLKOUTEN is enabled (CLKOUTEN = 0, Configuration Word 1H), the output will continue operating while in Idle. 6.3.1 Idle and Interrupts IDLE mode ends when an interrupt occurs (even if GIE = 0), but IDLEN is not changed. The device can re-enter IDLE by executing the SLEEP instruction. If Recover-on-Interrupt is enabled (ROI = 1), the interrupt that brings the device out of Idle also restores full-speed CPU execution when doze is also enabled. 6.3.2 Idle and WWDT When in Idle, the WWDT Reset is blocked and will instead wake the device. The WWDT wake-up is not an interrupt, therefore ROI does not apply. Important: The WWDT can bring the device out of Idle, in the same way it brings the device out of Sleep. The DOZEN bit is not affected. (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 76 PIC18F26/45/46Q10 Power-Saving Operation Modes 6.4 Peripheral Operation in Power-Saving Modes All selected clock sources and the peripherals running off them are active in both IDLE and DOZE mode. Only in Sleep mode, both the FOSC and FOSC/4 clocks are unavailable. All the other clock sources are active, if enabled manually or through peripheral clock selection before the part enters Sleep. (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 77 PIC18F26/45/46Q10 Power-Saving Operation Modes 6.5 Register Summary - Power Savings Control Address Name Bit Pos. 0x0ED2 CPUDOZE 7:0 IDLEN DOZEN ROI DOE DOZE[2:0] 0x0ED3 ... Reserved 0x0ED9 0x0EDA 6.6 VREGCON 7:0 PMSYS[1:0] VREGPM[1:0] Register Definitions: Power Savings Control (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 78 PIC18F26/45/46Q10 Power-Saving Operation Modes 6.6.1 VREGCON Name: Address: VREGCON 0xEDA Note: 1. System and peripheral inputs should not exceed 500 kHz in ULP mode. Voltage Regulator Control Register Bit 7 6 5 4 3 2 1 PMSYS[1:0] Access Reset 0 VREGPM[1:0] RO RO R/W R/W g g 1 0 Bits 5:4 - PMSYS[1:0] System Power Mode Status bits Value Description 11 Reserved 10 ULP regulator is active 01 Main regulator in LP mode is active 00 Main regulator in HP mode is active Bits 1:0 - VREGPM[1:0] Voltage Regulator Power Mode Selection bit Value Description 11 Reserved. Do not use. 10 ULP regulator(1) 01 Main regulator in LP mode 00 Main regulator in HP mode (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 79 PIC18F26/45/46Q10 Power-Saving Operation Modes 6.6.2 CPUDOZE Name: Address: CPUDOZE 0xED2 Doze and Idle Register Bit Access Reset 7 6 5 4 IDLEN DOZEN ROI DOE 3 2 1 0 R/W R/W/HC/HS R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 DOZE[2:0] Bit 7 - IDLEN Idle Enable bit Reset States: POR/BOR = 0 All Other Resets = u Value Description 1 A SLEEP instruction inhibits the CPU clock, but not the peripheral clock(s) 0 A SLEEP instruction places the device into full Sleep mode Bit 6 - DOZEN Doze Enable bit(1) Value Description 1 The CPU executes instruction cycles according to DOZE setting 0 The CPU executes all instruction cycles (fastest, highest power operation) Bit 5 - ROI Recover-On-Interrupt bit Value Description 1 Entering the Interrupt Service Routine (ISR) makes DOZEN = 0, bringing the CPU to fullspeed operation 0 Interrupt entry does not change DOZEN Bit 4 - DOE Doze-On-Exit bit Value Description 1 Executing RETFIE makes DOZEN = 1, bringing the CPU to reduced speed operation 0 RETFIE does not change DOZEN Bits 2:0 - DOZE[2:0] Ratio of CPU Instruction Cycles to Peripheral Instruction Cycles Value Description 111 1:256 110 1:128 101 1:64 100 1:32 011 1:16 010 1:8 001 1:4 000 1:2 Note: 1. When ROI = 1 or DOE = 1, DOZEN is changed by hardware interrupt entry and/or exit. (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 80 PIC18F26/45/46Q10 (PMD) Peripheral Module Disable 7. (PMD) Peripheral Module Disable This module provides the ability to selectively enable or disable a peripheral. Disabling a peripheral places it in its lowest possible power state. The user can disable unused modules to reduce the overall power consumption. The PIC18F26/45/46Q10 devices address this requirement by allowing peripheral modules to be selectively enabled or disabled. Disabling a peripheral places it in the lowest possible power mode. Important: All modules are ON by default following any system Reset. 7.1 Disabling a Module A peripheral can be disabled by setting the corresponding peripheral disable bit in the PMDx register. Disabling a module has the following effects: * The module is held in Reset and does not function. * All the SFRs pertaining to that peripheral become "unimplemented" - Writing is disabled - Reading returns 0x00 * Module outputs are disabled Related Links 15.1 I/O Priorities 7.2 Enabling a Module Clearing the corresponding module disable bit in the PMDx register, re-enables the module and the SFRs will reflect the Power-on Reset values. Important: There should be no reads/writes to the module SFRs for at least two instruction cycles after it has been re-enabled. (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 81 PIC18F26/45/46Q10 (PMD) Peripheral Module Disable 7.3 Register Summary - PMD Address Name Bit Pos. 0x0EDC PMD0 7:0 0x0EDD PMD1 0x0EDE PMD2 0x0EDF PMD3 7:0 CLC8MD CLC7MD CLC6MD CLC5MD 0x0EE0 PMD4 7:0 UART2MD UART1MD MSSP2MD MSSP1MD CWG1MD 0x0EE1 PMD5 7:0 CLC4MD CLC3MD CLC2MD CLC1MD DSMMD 7.4 SYSCMD FVRMD HLVDMD CRCMD SCANMD 7:0 TMR6MD TMR5MD TMR4MD TMR3MD 7:0 DACMD ADCMD PWM4MD NVMMD CLKRMD IOCMD TMR2MD TMR1MD TMR0MD CMP2MD CMP1MD ZCDMD PWM3MD CCP2MD CCP1MD Register Definitions: Peripheral Module Disable (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 82 PIC18F26/45/46Q10 (PMD) Peripheral Module Disable 7.4.1 PMD0 Name: Address: PMD0 0xEDC PMD Control Register 0 Bit Access Reset 7 6 5 4 3 2 1 0 SYSCMD FVRMD HLVDMD CRCMD SCANMD NVMMD CLKRMD IOCMD R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Bit 7 - SYSCMD Disable Peripheral System Clock Network bit Disables the System clock network(1) Value Description 1 System clock network disabled (FOSC) 0 System clock network enabled Bit 6 - FVRMD Disable Fixed Voltage Reference bit Value Description 1 FVR module disabled 0 FVR module enabled Bit 5 - HLVDMD Disable High-Low-Voltage Detect bit Value Description 1 HLVD module disabled 0 HLVD module enabled Bit 4 - CRCMD Disable CRC Engine bit Value Description 1 CRC module disabled 0 CRC module enabled Bit 3 - SCANMD Disable NVM Memory Scanner bit Disables the Scanner module(2) Value Description 1 NVM Memory Scan module disabled 0 NVM Memory Scan module enabled Bit 2 - NVMMD NVM Module Disable bit Disables the NVM module(3) Value Description 1 All Memory reading and writing is disabled; NVMCON registers cannot be written 0 NVM module enabled Bit 1 - CLKRMD Disable Clock Reference bit Value Description 1 CLKR module disabled 0 CLKR module enabled (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 83 PIC18F26/45/46Q10 (PMD) Peripheral Module Disable Bit 0 - IOCMD Disable Interrupt-on-Change bit, All Ports Value Description 1 IOC module(s) disabled 0 IOC module(s) enabled Note: 1. Clearing the SYSCMD bit disables the system clock (FOSC) to peripherals, however peripherals clocked by FOSC/4 are not affected. 2. Subject to SCANE bit in Configuration Word 4. 3. When enabling NVM, a delay of up to 1 s is required before accessing data. Related Links 3.7.4 CONFIG4 (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 84 PIC18F26/45/46Q10 (PMD) Peripheral Module Disable 7.4.2 PMD1 Name: Address: PMD1 0xEDD PMD Control Register 1 Bit Access Reset 7 6 5 4 3 2 1 0 TMR6MD TMR5MD TMR4MD TMR3MD TMR2MD TMR1MD TMR0MD R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 Bits 0, 1, 2, 3, 4, 5, 6 - TMRnMD Disable Timer n bit Value Description 1 TMRn module disabled 0 TMRn module enabled (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 85 PIC18F26/45/46Q10 (PMD) Peripheral Module Disable 7.4.3 PMD2 Name: Address: PMD2 0xEDE PMD Control Register 2 Bit 7 Access Reset 6 5 2 1 0 DACMD ADCMD 4 3 CMP2MD CMP1MD ZCDMD R/W R/W R/W R/W R/W 0 0 0 0 0 Bit 6 - DACMD Disable DAC bit Value Description 1 DAC module disabled 0 DAC module enabled Bit 5 - ADCMD Disable ADC bit Value Description 1 ADC module disabled 0 ADC module enabled Bits 1, 2 - CMPnMD Disable Comparator CMPn bit Value Description 1 CMPn module disabled 0 CMPn module enabled Bit 0 - ZCDMD Disable Zero-Cross Detect module bit(1) Value Description 1 ZCD module disabled 0 ZCD module enabled Note: 1. Subject to ZCD bit in Configuration Word 2. Related Links 3.7.2 CONFIG2 (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 86 PIC18F26/45/46Q10 (PMD) Peripheral Module Disable 7.4.4 PMD3 Name: Address: PMD3 0xEDF PMD Control Register 3 Bit Access Reset 7 6 5 4 3 2 1 0 CLC8MD CLC7MD CLC6MD CLC5MD PWM4MD PWM3MD CCP2MD CCP1MD R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Bits 4, 5, 6, 7 - CLCnMD Disable CLCn bit Value Description 1 CLCn module disabled 0 CLCn module enabled Bits 2, 3 - PWMnMD Disable PWMn bit Value Description 1 PWMn module disabled 0 PWMn module enabled Bits 0, 1 - CCPnMD Disable Capture/Compare/PWMn bit Value Description 1 CCPn module disabled 0 CCPn module enabled (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 87 PIC18F26/45/46Q10 (PMD) Peripheral Module Disable 7.4.5 PMD4 Name: Address: PMD4 0xEE0 PMD Control Register 4 Bit Access Reset 7 6 5 4 UART2MD UART1MD MSSP2MD MSSP1MD 3 2 1 CWG1MD 0 R/W R/W R/W R/W R/W 0 0 0 0 0 Bits 6, 7 - UARTnMD Disable EUSARTn bit Value Description 1 EUSARTn module disabled 0 EUSARTn module enabled Bits 4, 5 - MSSPnMD Disable MSSPn bit Value Description 1 MSSPn module disabled 0 MSSPn module enabled Bit 0 - CWG1MD Disable CWG1 Module bit Value Description 1 CWG1 module disabled 0 CWG1 module enabled (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 88 PIC18F26/45/46Q10 (PMD) Peripheral Module Disable 7.4.6 PMD5 Name: Address: PMD5 0xEE1 PMD Control Register 5 Bit Access Reset 7 6 5 4 CLC4MD CLC3MD CLC2MD CLC1MD 3 2 1 DSMMD 0 R/W R/W R/W R/W R/W 0 0 0 0 0 Bits 4, 5, 6, 7 - CLCnMD Disable CLCn bit Value Description 1 CLCn module disabled 0 CLCn module enabled Bit 0 - DSMMD Disable DSM bit Value Description 1 DSM module disabled 0 DSM module enabled (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 89 PIC18F26/45/46Q10 Resets 8. Resets There are multiple ways to reset this device: * * * * Power-on Reset (POR) Brown-out Reset (BOR) Low-Power Brown-out Reset (LPBOR) MCLR Reset * WDT Reset * RESET instruction * Stack Overflow * Stack Underflow * Programming mode exit To allow VDD to stabilize, an optional Power-up Timer can be enabled to extend the Reset time after a BORFilename: or POR event. 10-000006E.vsd Title: Simplified block diagram for RESET module First Used: PIC18(L)F2x/4x/6xK40 (MVAF,MVAE,MVAB,MVAC,MVAK) A simplified of the On-Chip Reset Circuit is shown in the block diagram below. Last Edit: block diagram 5/11/2016 Figure 8-1. Simplified Block Diagram of On-Chip Note: 1. See Table 8-1 for BOR active conditions Reset Circuit Rev. 10-000006E 5/11/2016 ICSPTM Programming Mode Exit RESET Instruction Stack Underflow Stack Overflow VPP/MCLR MCLRE WWDT Time-out/ Window voilation Device Reset Power-on Reset VDD Brown-out Reset(1) R LFINTOSC LPBOR Reset Power-up Timer PWRTE Note: See "BOR Operating Conditions" table for BOR active conditions. 8.1 Power-on Reset (POR) The POR circuit holds the device in Reset until VDD has reached an acceptable level for minimum operation. Slow rising VDD, fast operating speeds or analog performance may require greater than minimum VDD. The PWRT, BOR or MCLR features can be used to extend the start-up period until all device operation conditions have been met. (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 90 PIC18F26/45/46Q10 Resets 8.2 Brown-out Reset (BOR) The BOR circuit holds the device in Reset when VDD reaches a selectable minimum level. Between the POR and BOR, complete voltage range coverage for execution protection can be implemented. The Brown-out Reset module has four operating modes controlled by the BOREN<1:0> bits in Configuration Words. The four operating modes are: * BOR is always on * BOR is off when in Sleep * BOR is controlled by software * BOR is always off Refer to "BOR Operating Conditions" table for more information. The Brown-out Reset voltage level is selectable by configuring the BORV<1:0> bits in Configuration Words. A VDD noise rejection filter prevents the BOR from triggering on small events. If VDD falls below VBOR for a duration greater than parameter TBORDC, the device will reset. Related Links 3.7.2 CONFIG2 39.4.5 Reset, WDT, Oscillator Start-up Timer, Power-up Timer, Brown-Out Reset and Low-Power BrownOut Reset Specifications 8.2.1 BOR is Always On When the BOREN bits of Configuration Words are programmed to `11', the BOR is always on. The device start-up will be delayed until the BOR is ready and VDD is higher than the BOR threshold. BOR protection is active during Sleep. The BOR does not delay wake-up from Sleep. 8.2.2 BOR is OFF in Sleep When the BOREN bits of Configuration Words are programmed to `10', the BOR is on, except in Sleep. The device start-up will be delayed until the BOR is ready and VDD is higher than the BOR threshold. BOR protection is not active during Sleep. The device wake-up will be delayed until the BOR is ready. 8.2.3 BOR Controlled by Software When the BOREN bits of Configuration Words are programmed to `01', the BOR is controlled by the SBOREN bit. The device start-up is not delayed by the BOR ready condition or the VDD level. BOR protection begins as soon as the BOR circuit is ready. The status of the BOR circuit is reflected in the BORRDY bit. BOR protection is unchanged by Sleep. Table 8-1. BOR Operating Modes BOREN<1:0> SBOREN 11 X (c) 2019 Microchip Technology Inc. Device Mode BOR Mode X Active Instruction Execution upon: Release of POR Wake-up from Sleep Wait for release of BOR (BORRDY = 1) Begins immediately Datasheet Preliminary DS40001996C-page 91 PIC18F26/45/46Q10 Resets ...........continued BOREN<1:0> SBOREN 10 01 00 Device Mode BOR Mode Awake Instruction Execution upon: Release of POR Wake-up from Sleep Active Wait for release of BOR (BORRDY = 1) N/A Sleep Hibernate N/A Wait for release of BOR (BORRDY = 1) 1 X Active 0 X Hibernate Wait for release of BOR (BORRDY = 1) Begins immediately X X Disabled X Begins immediately Note: 1. In this specific case, "Release of POR" and "Wake-up from Sleep", there is no delay in start-up. The BOR ready flag, (BORRDY = 1), will be set before the CPU is ready to execute instructions because the BOR circuit is forced on by the BOREN<1:0> bits Figure 8-2. Brown-out Situations Rev. 30-000092A 4/12/2017 VDD Internal Reset VBOR TPWRT(1) VDD Internal Reset VBOR < TPWRT TPWRT(1) VDD VBOR Internal Reset TPWRT(1) Note: TPWRT delay only if PWRTE bit is programmed to `0'. 8.2.4 BOR and Bulk Erase BOR is forced ON during PFM Bulk Erase operations to make sure that the system code protection cannot be compromised by reducing VDD. During Bulk Erase, the BOR is enabled at 1.9V, even if it is configured to some other value. If VDD falls, the erase cycle will be aborted, but the device will not be reset. (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 92 PIC18F26/45/46Q10 Resets 8.3 Low-Power Brown-out Reset (LPBOR) The Low-Power Brown-out Reset (LPBOR) provides an additional BOR circuit for low-power operation. Refer to the figure below to see how the BOR interacts with other modules. The LPBOR is used to monitor the external VDD pin. When too low of a voltage is detected, the device is held in Reset. Figure 8-3. LPBOR, BOR, POR Relationship Rev. 30-000091B 6/21/2017 Any Reset BOR BOR Event REARM POR Event To PCON indicator bit POR LPBOR POR Event LPBOR Event Reset logic 8.3.1 Enabling LPBOR The LPBOR is controlled by the LPBOREN bit of Configuration Word 2. When the device is erased, the LPBOR module defaults to disabled. Related Links 3.7.2 CONFIG2 8.3.1.1 LPBOR Module Output The output of the LPBOR module is a signal indicating whether or not a Reset is to be asserted. This signal is OR'd together with the Reset signal of the BOR module to provide the generic BOR signal, which goes to the PCON0 register and to the power control block. 8.4 MCLR Reset The MCLR is an optional external input that can reset the device. The MCLR function is controlled by the MCLRE bit of Configuration Words and the LVP bit of Configuration Words (see table below). The RMCLR bit in the PCON0 register will be set to `0' if a MCLR has occurred. Table 8-2. MCLR Configuration MCLRE LVP MCLR x 1 Enabled (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 93 PIC18F26/45/46Q10 Resets ...........continued 8.4.1 MCLRE LVP MCLR 1 0 Enabled 0 0 Disabled MCLR Enabled When MCLR is enabled and the pin is held low, the device is held in Reset. The MCLR pin is connected to VDD through an internal weak pull-up. The device has a noise filter in the MCLR Reset path. The filter will detect and ignore small pulses. Important: An internal Reset event (RESET instruction, BOR, WWDT, POR, STKOVF, STKUNF) does not drive the MCLR pin low. 8.4.2 MCLR Disabled When MCLR is disabled, the MCLR becomes input-only and pin functions such as internal weak pull-ups are under software control. Related Links 15.1 I/O Priorities 8.5 Windowed Watchdog Timer (WWDT) Reset The Windowed Watchdog Timer generates a Reset if the firmware does not issue a CLRWDT instruction within the time-out period or window set. The TO and PD bits in the STATUS register and the RWDT bit are changed to indicate a WDT Reset. The WDTWV bit indicates if the WDT Reset has occurred due to a time-out or a window violation. Related Links 10.8.5 STATUS 9. (WWDT) Windowed Watchdog Timer 8.6 RESET Instruction A RESET instruction will cause a device Reset. The RI bit will be set to `0'. See Table 8-3 for default conditions after a RESET instruction has occurred. 8.7 Stack Overflow/Underflow Reset The device can reset when the Stack Overflows or Underflows. The STKOVF or STKUNF bits register indicate the Reset condition. These Resets are enabled by setting the STVREN bit in Configuration Words. Related Links 3.7.2 CONFIG2 10.1.2.3 Stack Overflow and Underflow Resets (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 94 PIC18F26/45/46Q10 Resets 8.8 Programming Mode Exit Upon exit of Programming mode, the device will behave as if a POR had just occurred. 8.9 Power-up Timer (PWRT) The Power-up Timer provides a nominal 66 ms (2048 cycles of LFINTOSC) time-out on POR or Brownout Reset. The device is held in Reset as long as PWRT is active. The PWRT delay allows additional time for the VDD to rise to an acceptable level. The Power-up Timer is enabled by clearing the PWRTE bit in Configuration Words. The Power-up Timer starts after the release of the POR and BOR. For additional information, refer to Application Note AN607, "Power-up Trouble Shooting" (DS00000607). 8.10 Start-up Sequence Upon the release of a POR or BOR, the following must occur before the device will begin executing: 1. 2. 3. Power-up Timer runs to completion (if enabled). Oscillator Start-up Timer runs to completion (if required for selected oscillator source). MCLR must be released (if enabled). The total time-out will vary based on oscillator configuration and Power-up Timer configuration. The Power-up Timer and Oscillator Start-up Timer run independently of MCLR Reset. If MCLR is kept low long enough, the Power-up Timer and Oscillator Start-up Timer will expire. Upon bringing MCLR high, the device will begin execution after 10 FOSC cycles (see figure below). This is useful for testing purposes or to synchronize more than one device operating in parallel. (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 95 PIC18F26/45/46Q10 Resets Figure 8-4. Reset Start-up Sequence Rev. 30-000093A 4/12/2017 VDD Internal POR TPWRT Power-up Timer MCLR TMCLR Internal RESET Oscillator Modes External Crystal TOST Oscillator Start-up Timer Oscillator FOSC Internal Oscillator Oscillator FOSC External Clock (EC) CLKIN FOSC Related Links 4. Oscillator Module (with Fail-Safe Clock Monitor) 8.11 Determining the Cause of a Reset Upon any Reset, multiple bits in the STATUS and PCON0 registers are updated to indicate the cause of the Reset. The following table shows the Reset conditions of these registers. Table 8-3. Reset Condition for Special Registers Program Counter STATUS Register(2,3) PCON0 Register PCON1 Register Power-on Reset 0 -110 0000 0011 110x ---- -1-1 Brown-out Reset 0 -110 0000 0011 11u0 ---- -u-u MCLR Reset during normal operation 0 -uuu uuuu uuuu 0uuu uuuu-u-u MCLR Reset during Sleep 0 -10u uuuu uuuu 0uuu uuuu-u-u Condition (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 96 PIC18F26/45/46Q10 Resets ...........continued Program Counter STATUS Register(2,3) PCON0 Register PCON1 Register WDT Time-out Reset 0 -0uu uuuu uuu0 uuuu uuuu-u-u WDT Wake-up from Sleep PC + 2 -00u uuuu uuuu uuuu uuuu-u-u WWDT Window Violation Reset 0 -uuu uuuu uu0u uuuu uuuu-u-u Interrupt Wake-up from Sleep PC + 2(1) -10u 0uuu uuuu uuuu uuuu-u-u RESET Instruction Executed 0 -uuu uuuu uuuu u0uu uuuu-u-u Stack Overflow Reset (STVREN = 1) 0 -uuu uuuu 1uuu uuuu uuuu-u-u Stack Underflow Reset (STVREN = 1) 0 -uuu uuuu u1uu uuuu uuuu-u-u Data Protection (Fuse Fault) 0 ---u uuuu uuuu uuuu ---- -u-0 VREG or ULP Ready Fault 0 ---1 1000 0011 001u ---- -0-1 Condition Legend: u = unchanged, x = unknown, -- = unimplemented bit, reads as `0'. Note: 1. When the wake-up is due to an interrupt and Global Interrupt Enable bit (GIE) is set, the return address is pushed on the stack and PC is loaded with the corresponding interrupt vector (depending on source, high or low priority) after execution of PC + 2. 2. If a Status bit is not implemented, that bit will be read as `0'. 3. Status bits Z, C, DC are reset by POR/BOR. Related Links 10.8.5 STATUS 8.12 Power Control (PCON0) Register The Power Control (PCON0) register contains flag bits to differentiate between a: * * * * Brown-out Reset (BOR) Power-on Reset (POR) Reset Instruction Reset (RI) MCLR Reset (RMCLR) (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 97 PIC18F26/45/46Q10 Resets * * * * Watchdog Timer Reset (RWDT) Watchdog Window Violation (WDTWV) Stack Underflow Reset (STKUNF) Stack Overflow Reset (STKOVF) The Power Control register bits are shown in 8.14.2 PCON0. Hardware will change the corresponding register bit during the Reset process; if the Reset was not caused by the condition, the bit remains unchanged (Table 8-3). Software should reset the bit to the Inactive state after restart (hardware will not reset the bit). Software may also set any PCON0 bit to the Active state, so that user code may be tested, but no Reset action will be generated. (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 98 PIC18F26/45/46Q10 Resets 8.13 Register Summary - BOR Control and Power Control Address Name Bit Pos. 0x0EDB BORCON 7:0 SBOREN BORRDY 0x0EDC ... Reserved 0x0FD5 0x0FD6 PCON1 7:0 0x0FD7 PCON0 7:0 8.14 RVREG STKOVF STKUNF WDTWV RWDT RMCLR RI RCM POR BOR Register Definitions: Power Control (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 99 PIC18F26/45/46Q10 Resets 8.14.1 BORCON Name: Address: BORCON 0xEDB Brown-out Reset Control Register Bit Access Reset 7 6 5 4 3 2 1 0 SBOREN BORRDY R/W R 1 q Bit 7 - SBOREN Software Brown-out Reset Enable bit Reset States: POR/BOR = 1 All Other Resets = u Value Condition Description -- If BOREN 01 SBOREN is read/write, but has no effect on the BOR. 1 If BOREN= 01 BOR Enabled 0 If BOREN= 01 BOR Disabled Bit 0 - BORRDY Brown-out Reset Circuit Ready Status bit Reset States: POR/BOR = q All Other Resets = u Value Description 1 The Brown-out Reset Circuit is active and armed 0 The Brown-out Reset Circuit is disabled or is warming up Related Links 3.7.2 CONFIG2 (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 100 PIC18F26/45/46Q10 Resets 8.14.2 PCON0 Name: Address: PCON0 0xFD7 Power Control Register 0 Bit Access Reset 7 6 5 4 3 2 1 0 STKOVF STKUNF WDTWV RWDT RMCLR RI POR BOR R/W/HS R/W/HS R/W/HC R/W/HC R/W/HC R/W/HC R/W/HC R/W/HC 0 0 1 1 1 1 0 q Bit 7 - STKOVF Stack Overflow Flag bit Reset States: POR/BOR = 0 All Other Resets = q Value Description 1 A Stack Overflow occurred (more CALLs than fit on the stack) 0 A Stack Overflow has not occurred or set to `0' by firmware Bit 6 - STKUNF Stack Underflow Flag bit Reset States: POR/BOR = 0 All Other Resets = q Value Description 1 A Stack Underflow occurred (more RETURNs than CALLs) 0 A Stack Underflow has not occurred or set to `0' by firmware Bit 5 - WDTWV Watchdog Window Violation Flag bit Reset States: POR/BOR = 1 All Other Resets = q Value Description 1 A WDT window violation has not occurred or set to `1' by firmware 0 A CLRWDT instruction was issued when the WDT Reset window was closed (set to `0' in hardware when a WDT window violation Reset occurs) Bit 4 - RWDT WDT Reset Flag bit Reset States: POR/BOR = 1 All Other Resets = q Value Description 1 A WDT overflow/time-out Reset has not occurred or set to `1' by firmware 0 A WDT overflow/time-out Reset has occurred (set to `0' in hardware when a WDT Reset occurs) Bit 3 - RMCLR MCLR Reset Flag bit Reset States: POR/BOR = 1 All Other Resets = q Value Description 1 A MCLR Reset has not occurred or set to `1' by firmware 0 A MCLR Reset has occurred (set to `0' in hardware when a MCLR Reset occurs) (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 101 PIC18F26/45/46Q10 Resets Bit 2 - RI RESET Instruction Flag bit Reset States: POR/BOR = 1 All Other Resets = q Value Description 1 A RESET instruction has not been executed or set to `1' by firmware 0 A RESET instruction has been executed (set to `0' in hardware upon executing a RESET instruction) Bit 1 - POR Power-on Reset Status bit Reset States: POR/BOR = 0 All Other Resets = u Value Description 1 No Power-on Reset occurred or set to `1' by firmware 0 A Power-on Reset occurred (set to `0' in hardware when a Power-on Reset occurs) Bit 0 - BOR Brown-out Reset Status bit Reset States: POR/BOR = q All Other Resets = u Value Description 1 No Brown-out Reset occurred or set to `1' by firmware 0 A Brown-out Reset occurred (set to `0' in hardware when a Brown-out Reset occurs) (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 102 PIC18F26/45/46Q10 Resets 8.14.3 PCON1 Name: Address: PCON1 0xFD6 Power Control Register 1 Bit 7 6 5 4 3 Access Reset 2 1 0 RVREG RCM R/W/HC R/W/HC 1 1 Bit 2 - RVREG Main LDO Voltage Regulator Reset Flag bit Reset States: POR/BOR = 1 All Other Resets = q Value Description 1 No LDO or ULP "ready" Reset has occured; or set to `1' by firmware 0 LDO or ULP "ready" Reset has occurred (VDDCORE reached its minimum spec) Bit 0 - RCM Configuration Memory Reset Flag bit Reset States: POR/BOR = 1 All Other Resets = q Value Description 1 A Reset occurred due to corruption of the configuration and/or calibration data latches 0 The configuration and calibration latches have not been corrupted (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 103 PIC18F26/45/46Q10 (WWDT) Windowed Watchdog Timer 9. (WWDT) Windowed Watchdog Timer The Watchdog Timer (WDT) is a system timer that generates a Reset if the firmware does not issue a CLRWDT instruction within the time-out period. The Watchdog Timer is typically used to recover the system from unexpected events. The Windowed Watchdog Timer (WWDT) differs in that CLRWDT instructions are only accepted when they are performed within a specific window during the time-out period. The WWDT has the following features: * Selectable clock source * Multiple operating modes - WWDT is always on - WWDT is off when in Sleep - WWDT is controlled by software - WWDT is always off * Configurable time-out period is from 1 ms to 256s (nominal) * Configurable window size from 12.5% to 100% of the time-out period * Multiple Reset conditions (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 104 Filename: Title: Last Edit: First Used: Notes: 10-000162A.vsd Windowed Watchdog Timer Timer Block Diagram 1/2/2014 PIC16(L)F1613 (LECQ) PIC18F26/45/46Q10 (WWDT) Windowed Watchdog Timer Figure 9-1. Windowed Watchdog Timer Block Diagram Rev. 10-000 162A 1/2/201 4 WWDT Armed WDT Window Violation Window Closed Window Sizes CLRWDT Comparator WINDOW RESET Reserved 111 Reserved 110 Reserved 101 Reserved 100 Reserved 011 SOSC 010 MFINTOSC/16 001 LFINTOSC 000 R 18-bit Prescale Counter E CS PS R 5-bit WDT Counter Overflow Latch WDT Time-out WDTE<1:0> = 01 SEN WDTE<1:0> = 11 WDTE<1:0> = 10 Sleep 9.1 Independent Clock Source The WWDT can derive its time base from either the 31 kHz LFINTOSC or 31.25 kHz MFINTOSC internal oscillators, depending on the value of WDTE Configuration bits. If WDTE = 'b1x, then the clock source will be enabled depending on the WDTCCS Configuration bits. If WDTE = 'b01, the SEN bit should be set by software to enable WWDT, and the clock source is enabled by the WDTCS bits. Time intervals in this chapter are based on a minimum nominal interval of 1 ms. See "Electrical Specifications" for LFINTOSC and MFINTOSC tolerances. (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 105 PIC18F26/45/46Q10 (WWDT) Windowed Watchdog Timer Related Links 3.7.3 CONFIG3 39.4.2 Internal Oscillator Parameters(1) 9.2 WWDT Operating Modes The Windowed Watchdog Timer module has four operating modes controlled by the WDTE bits in Configuration Words. See Table 9-1. 9.2.1 WWDT Is Always On When the WDTE bits of Configuration Words are set to `11', the WWDT is always on. WWDT protection is active during Sleep. 9.2.2 WWDT Is Off in Sleep When the WDTE bits of Configuration Words are set to `10', the WWDT is on, except in Sleep. WWDT protection is not active during Sleep. 9.2.3 WWDT Controlled by Software When the WDTE bits of Configuration Words are set to `01', the WWDT is controlled by the SEN bit. WWDT protection is unchanged by Sleep. See the following table for more details. Table 9-1. WWDT Operating Modes WDTE<1:0> SEN Device Mode WWDT Mode 11 X X Active 10 X Awake Active Sleep Disabled 1 X Active 0 X Disabled X X Disabled 01 00 9.3 Time-out Period If the WDTCPS Configuration bits default to 0'b11111, then the WDTPS bits set the time-out period from 1 ms to 256 seconds (nominal). If any value other than the default value is assigned to WDTCPS Configuration bits, then the timer period will be based on the WDTCPS bits in the CONFIG3 register. After a Reset, the default time-out period is 2s. Related Links 3.7.3 CONFIG3 9.4 Watchdog Window The Windowed Watchdog Timer has an optional Windowed mode that is controlled by the WDTCWS Configuration bits and WINDOW bits. In the Windowed mode, the CLRWDT instruction must occur within (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 106 PIC18F26/45/46Q10 (WWDT) Windowed Watchdog Timer the allowed window of the WDT period. Any CLRWDT instruction that occurs outside of this window will trigger a window violation and will cause a WWDT Reset, similar to a WWDT time-out. See Figure 9-2 for an example. The window size is controlled by the WINDOW Configuration bits, or the WINDOW bits, if WDTCWS = 111. The five Most Significant bits of the WDTTMR register are used to determine whether the window is open, as defined by the WINDOW bits. In the event of a window violation, a Reset will be generated and the WDTWV bit of the PCON0 register will be cleared. This bit is set by a POR or can be set in firmware. Related Links 8.14.2 PCON0 9.5 Clearing the WWDT The WWDT is cleared when any of the following conditions occur: * Any Reset * Valid CLRWDT instruction is executed * * * * * 9.5.1 Device enters Sleep Exit Sleep by Interrupt WWDT is disabled Oscillator Start-up Timer (OST) is running Any write to the WDTCON0 or 9.8.2 WDTCON1 registers CLRWDT Considerations (Windowed Mode) When in Windowed mode, the WWDT must be armed before a CLRWDT instruction will clear the timer. This is performed by reading the WDTCON0 register. Executing a CLRWDT instruction without performing such an arming action will trigger a window violation regardless of whether the window is open or not. See Table 9-2 for more information. 9.6 Operation During Sleep When the device enters Sleep, the WWDT is cleared. If the WWDT is enabled during Sleep, the WWDT resumes counting. When the device exits Sleep, the WWDT is cleared again. The WWDT remains clear until the Oscillator Start-up Timer (OST) completes, if enabled. When a WWDT time-out occurs while the device is in Sleep, no Reset is generated. Instead, the device wakes up and resumes operation. The TO and PD bits in the STATUS register are changed to indicate the event. The RWDT bit in the PCON0 register can also be used. (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 107 PIC18F26/45/46Q10 (WWDT) Windowed Watchdog Timer Table 9-2. WWDT Clearing Conditions Conditions WWDT WDTE = 00 WDTE = 01 and SEN = 0 WDTE = 10 and enter Sleep Cleared CLRWDT Command Oscillator Fail Detected 10-000163A.vsd ExitFilename: Sleep + System Clock = SOSC, EXTRC, INTOSC, EXTCLK Title: WDT WINDOW PERIOD AND DELAY Edit: + System 8/15/2016 ExitLast Sleep Clock = XT, HS, LP First Used: Notes: Change INTOSC Cleared until the end of OST PIC16(L)F1613 (LECQ) divider (IRCF bits) Unaffected Figure 9-2. Window Period and Delay Rev. 10-000163A 8/15/2016 CLRWDT Instruction (or other WDT Reset) Window Period Window Closed Window Open Window Delay (window violation can occur) Time-out Event Related Links 4.2.1.3 Oscillator Start-up Timer (OST) 10.8.5 STATUS 8.14.2 PCON0 10. Memory Organization (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 108 PIC18F26/45/46Q10 (WWDT) Windowed Watchdog Timer 9.7 Register Summary - WDT Control Address Name Bit Pos. 0x0ECD WDTCON0 7:0 0x0ECE WDTCON1 7:0 0x0ECF WDTPSL 7:0 0x0ED0 WDTPSH 7:0 0x0ED1 WDTTMR 7:0 9.8 WDTPS[4:0] SEN WDTCS[2:0] WINDOW[2:0] PSCNTL[7:0] PSCNTH[7:0] WDTTMR[4:0] STATE PSCNT[1:0] Register Definitions: Windowed Watchdog Timer Control (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 109 PIC18F26/45/46Q10 (WWDT) Windowed Watchdog Timer 9.8.1 WDTCON0 Name: Address: WDTCON0 0xECD Watchdog Timer Control Register 0 Bit 7 6 5 4 3 2 1 WDTPS[4:0] Access Reset 0 SEN R/W R/W R/W R/W R/W R/W q q q q q 0 Bits 5:1 - WDTPS[4:0] Watchdog Timer Prescale Select bits(1) Bit Value = Prescale Rate Value Description 11111 Reserved. Results in minimum interval (1 ms) to 10011 10010 1:8388608 (223) (Interval 256s nominal) 10001 1:4194304 (222) (Interval 128s nominal) 10000 1:2097152 (221) (Interval 64s nominal) 01111 1:1048576 (220) (Interval 32s nominal) 01110 1:524288 (219) (Interval 16s nominal) 01101 1:262144 (218) (Interval 8s nominal) 01100 1:131072 (217) (Interval 4s nominal) 01011 1:65536 (Interval 2s nominal) (Reset value) 01010 1:32768 (Interval 1s nominal) 01001 1:16384 (Interval 512 ms nominal) 01000 1:8192 (Interval 256 ms nominal) 00111 1:4096 (Interval 128 ms nominal) 00110 1:2048 (Interval 64 ms nominal) 00101 1:1024 (Interval 32 ms nominal) 00100 1:512 (Interval 16 ms nominal) 00011 1:256 (Interval 8 ms nominal) 00010 1:128 (Interval 4 ms nominal) 00001 1:64 (Interval 2 ms nominal) 00000 1:32 (Interval 1 ms nominal) Bit 0 - SEN Software Enable/Disable for Watchdog Timer bit Value Condition Description -- If WDTE = 1x This bit is ignored 1 If WDTE = 01 WDT is turned on 0 If WDTE = 01 WDT is turned off -- If WDTE = 00 This bit is ignored (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 110 PIC18F26/45/46Q10 (WWDT) Windowed Watchdog Timer Note: 1. Times are approximate. WDT time is based on 31 kHz LFINTOSC. 2. When WDTCPS in CONFIG3 = 11111, the Reset value (q) of WDTPS is `01011'. Otherwise, the Reset value of WDTPS is equal to WDTCPS in CONFIG3. 3. When WDTCPS in CONFIG3L 11111, these bits are read-only. (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 111 PIC18F26/45/46Q10 (WWDT) Windowed Watchdog Timer 9.8.2 WDTCON1 Name: Address: WDTCON1 0xECE Watchdog Timer Control Register 1 Bit 7 6 5 4 3 2 WDTCS[2:0] Access Reset 1 0 WINDOW[2:0] R/W R/W R/W R/W R/W R/W q q q q q q Bits 6:4 - WDTCS[2:0] Watchdog Timer Clock Select bits Value Description 111 to Reserved 010 001 MFINTOSC 31.25 kHz 000 LFINTOSC 31 kHz Bits 2:0 - WINDOW[2:0] Watchdog Timer Window Select bits WINDOW Window delay Percent of time Window opening Percent of time 111 N/A 100 110 12.5 87.5 101 25 75 100 37.5 62.5 011 50 50 010 62.5 37.5 001 75 25 000 87.5 12.5 Note: 1. If WDTCCS in CONFIG3 = 111, the Reset value of WDTCS is `000'. 2. 3. The Reset value (q) of WINDOW is determined by the value of WDTCWS in the CONFIG3 register. If WDTCCS in CONFIG3 111, these bits are read-only. 4. If WDTCWS in CONFIG3 111, these bits are read-only. (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 112 PIC18F26/45/46Q10 (WWDT) Windowed Watchdog Timer 9.8.3 WDTPSH Name: Address: WDTPSH 0xED0 WWDT Prescale Select High Register (Read-Only) Bit 7 6 5 4 3 2 1 0 PSCNTH[7:0] Access Reset RO RO RO RO RO RO RO RO 0 0 0 0 0 0 0 0 Bits 7:0 - PSCNTH[7:0] Prescale Select High Byte bits(1) Note: 1. The 18-bit WDT prescale value, PSCNT<17:0> includes the WDTPSL, WDTPSH and the lower bits of the WDTTMR registers. PSCNT<17:0> is intended for debug operations and should be read during normal operation. (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 113 PIC18F26/45/46Q10 (WWDT) Windowed Watchdog Timer 9.8.4 WDTPSL Name: Address: WDTPSL 0xECF WWDT Prescale Select Low Register (Read-Only) Bit 7 6 5 4 3 2 1 0 PSCNTL[7:0] Access Reset RO RO RO RO RO RO RO RO 0 0 0 0 0 0 0 0 Bits 7:0 - PSCNTL[7:0] Prescale Select Low Byte bits(1) Note: 1. The 18-bit WDT prescale value, PSCNT<17:0> includes the WDTPSL, WDTPSH and the lower bits of the WDTTMR registers. PSCNT<17:0> is intended for debug operations and should be read during normal operation. (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 114 PIC18F26/45/46Q10 (WWDT) Windowed Watchdog Timer 9.8.5 WDTTMR Name: Address: WDTTMR 0xED1 WDT Timer Register (Read-Only) Bit 7 6 5 4 3 2 WDTTMR[4:0] Access Reset 1 STATE 0 PSCNT[1:0] RO RO RO RO RO RO RO RO 0 0 0 0 0 0 0 0 Bits 7:3 - WDTTMR[4:0] Watchdog Window Value bits WINDOW WDT Window State Open Percent Closed Open 111 N/A 00000-11111 100 110 00000-00011 00100-11111 87.5 101 00000-00111 01000-11111 75 100 00000-01011 01100-11111 62.5 011 00000-01111 10000-11111 50 010 00000-10011 10100-11111 37.5 001 00000-10111 11000-11111 25 000 00000-11011 11100-11111 12.5 Bit 2 - STATE WDT Armed Status bit Value Description 1 WDT is armed 0 WDT is not armed Bits 1:0 - PSCNT[1:0] Prescale Select Upper Byte bits(1) Note: 1. The 18-bit WDT prescale value, PSCNT<17:0> includes the WDTPSL, WDTPSH and the lower bits of the WDTTMR registers. PSCNT<17:0> is intended for debug operations and should be read during normal operation. (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 115 PIC18F26/45/46Q10 Memory Organization 10. Memory Organization There are three types of memory in PIC18 enhanced microcontroller devices: * Program Memory * Data RAM * Data EEPROM In Harvard architecture devices, the data and program memories use separate buses that allows for concurrent access of the two memory spaces. The data EEPROM, for practical purposes, can be regarded as a peripheral device, since it is addressed and accessed through a set of control registers. Additional detailed information on the operation of the Program Flash Memory and data EEPROM memory is provided in the Nonvolatile Memory (NVM) control section. 10.1 Program Memory Organization PIC18 microcontrollers implement a 21-bit Program Counter, which is capable of addressing a 2 Mbyte program memory space. Accessing a location between the upper boundary of the physically implemented memory and the 2 Mbyte address will return all `0's (a NOP instruction). Refer to the following tables for device memory maps and code protection Configuration bits associated with the various sections of PFM. PIC18 devices have two interrupt vectors. The Reset vector address is at 0000h and the interrupt vector addresses are at 0008h and 0018h. (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 116 PIC18F26/45/46Q10 Memory Organization Figure 10-1. Program and Data Memory Map Rev. 40-000101C 6/16/2017 Device Address PIC18F26Q10 PIC18F46Q10 PIC18F45Q10 Note 1 Stack (31 Levels) 00 0000h Reset Vector ... ... 00 0008h Interrupt Vector High ... ... 00 0018h Interrupt Vector Low ... ... 00 001Ah 00 7FFFh Program Flash Memory (16 KW) 00 8000h 00 FFFFh 01 0000h 01 FFFFh 02 0000h Program Flash Memory (32 KW) Not Present(2) Not Present(2) 1F FFFFh 20 0000h User IDs (256 Words)(3) 20 00FFh 20 0100h Reserved 2F FFFFh 30 0000h Configuration Words (6 Words)(3) 30 000Bh 30 000Ch Reserved 30 02FFh 30 0300h Unimplemented 30 FFFBh 31 0000h Data EEPROM (256 Bytes) Data EEPROM 31 00FFh (1 k Bytes) 31 0100h 31 03FFh Unimplemented 31 0400h Unimplemented 3F FFFBh 3F FFFCh Revision ID (1 Word)(4) 3F FFFDh 3F FFFEh Device ID (1 Word)(4) 3F FFFFh Note 1: The stack is a separate SRAM panel, apart from all user memory panels. 2: The addresses do not roll over. The region is read as `0'. 3: Not code-protected. 4: Device/Revision IDs are hard-coded in silicon. (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 117 PIC18F26/45/46Q10 Memory Organization Figure 10-2. Memory Map and Code Protection Control Rev. 40-000100C 12/19/2017 Device Region Address 00 0000h to 00 07FFh 00 0800h to 00 1FFFh 00 2000h to 00 3FFFh 00 4000h to 00 5FFFh 00 6000h to 00 7FFFh PFM PIC18F45Q10 Boot Block 1 KW CP, WRTB, EBTRB Block 0 3 KW CP, WRT0, EBTR0 Block 1 4 KW CP, WRT1, EBTR1 Block 2 4 KW CP, WRT2, EBTR2 Block 3 4 KW CP, WRT3, EBTR3 PIC18F26Q10 PIC18F46Q10 Boot Block 1 KW CP, WRTB, EBTRB Block 0 7 KW CP, WRT0, EBTR0 Block 1 8 KW CP, WRT1, EBTR1 00 8000h to 00 BFFFh Block 2 8 KW CP, WRT2, EBTR2 00 C000h to 00 FFFFh Block 3 8 KW CP, WRT3, EBTR3 01 0000h to 01 3FFFh 01 4000h to 01 7FFFh Not Present Not Present 01 8000h to 01 BFFFh 01 C000h to 01 FFFFh CONFIG Data EEPROM (c) 2019 Microchip Technology Inc. 30 0000h to 30 000Bh 31 0000h to 31 00FFh Configuration Words WRTC 256 Words CPD, WRTD 31 0100h to 31 01FFh Datasheet Preliminary 1 KW CPD, WRTD DS40001996C-page 118 PIC18F26/45/46Q10 Memory Organization 10.1.1 Program Counter The Program Counter (PC) specifies the address of the instruction to fetch for execution. The PC is 21 bits wide and is contained in three separate 8-bit registers. The low byte, known as the PCL register, is both readable and writable. The high byte, or PCH register, contains the PC<15:8> bits; it is not directly readable or writable. Updates to the PCH register are performed through the PCLATH register. The upper byte is called PCU. This register contains the PC<20:16> bits; it is also not directly readable or writable. Updates to the PCU register are performed through the PCLATU register. The contents of PCLATH and PCLATU are transferred to the Program Counter by any operation that writes PCL. Similarly, the upper two bytes of the Program Counter are transferred to PCLATH and PCLATU by an operation that reads PCL. This is useful for computed offsets to the PC (see 10.1.3.1 Computed GOTO). The PC addresses bytes in the program memory. To prevent the PC from becoming misaligned with word instructions, the Least Significant bit of PCL is fixed to a value of `0'. The PC increments by two to address sequential instructions in the program memory. The CALL, RCALL, GOTO and program branch instructions write to the Program Counter directly. For these instructions, the contents of PCLATH and PCLATU are not transferred to the Program Counter. 10.1.2 Return Address Stack The return address stack allows any combination of up to 31 program calls and interrupts to occur. The PC is pushed onto the stack when a CALL or RCALL instruction is executed or an interrupt is Acknowledged. The PC value is pulled off the stack on a RETURN, RETLW or a RETFIE instruction. PCLATU and PCLATH are not affected by any of the RETURN or CALL instructions. The stack operates as a 31-word by 21-bit RAM and a 5-bit Stack Pointer, or as a 35-word by 21-bit RAM with a 6-bit Stack Pointer in ICD mode. The stack space is not part of either program or data space. The Stack Pointer is readable and writable and the address on the top of the stack is readable and writable through the Top-of-Stack (TOS) Special File registers. Data can also be pushed to, or popped from the stack, using these registers. A CALL type instruction causes a push onto the stack; the Stack Pointer is first incremented and the location pointed to by the Stack Pointer is written with the contents of the PC (already pointing to the instruction following the CALL). A RETURN type instruction causes a pop from the stack; the contents of the location pointed to by the STKPTR are transferred to the PC and then the Stack Pointer is decremented. The Stack Pointer is initialized to `0b00000' after all Resets. There is no RAM associated with the location corresponding to a Stack Pointer value of `0b00000'; this is only a Reset value. Status bits in the PCON0 register indicate if the stack is full or has overflowed or has under-flowed. 10.1.2.1 Top-of-Stack Access Only the top of the return address stack (TOS) is readable and writable. A set of three registers, TOSU:TOSH:TOSL, hold the contents of the stack location pointed to by the STKPTR register (see Figure 10-3). This allows users to implement a software stack if necessary. After a CALL, RCALL or interrupt, the software can read the pushed value by reading the TOSU:TOSH:TOSL registers. These values can be placed on a user defined software stack. At return time, the software can return these values to TOSU:TOSH:TOSL and do a return. The user must disable the Global Interrupt Enable (GIE) bits while accessing the stack to prevent inadvertent stack corruption. (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 119 PIC18F26/45/46Q10 Memory Organization Figure 10-3. Return Address Stack and Associated Registers Rev. 30-00094A 4/12/2017 Return Address Stack <20:0> 11111 11110 11101 Top-of-Stack Registers TOSU 00h TOSH 1Ah Stack Pointer STKPTR<4:0> 00010 TOSL 34h Top-of-Stack 001A34h 000D58h 00011 00010 00001 00000 10.1.2.2 Return Stack Pointer The 10.8.4 STKPTR register contains the Stack Pointer value. The STKOVF (Stack Overflow) Status bit and the STKUNF (Stack Underflow) Status bit can be accessed using the PCON0 register. The value of the Stack Pointer can be 0 through 31. On Reset, the Stack Pointer value will be zero. The user may read and write the Stack Pointer value. This feature can be used by a Real-Time Operating System (RTOS) for stack maintenance. After the PC is pushed onto the stack 32 times (without popping any values off the stack), the STKOVF bit is set. The STKOVF bit is cleared by software or by a POR. The action that takes place when the stack becomes full depends on the state of the STVREN (Stack Overflow Reset Enable) Configuration bit. If STVREN is set (default), a Reset will be generated and a Stack Overflow will be indicated by the STKOVF bit when the 32nd push is initiated. This includes CALL and CALLW instructions, as well as stacking the return address during an interrupt response. The STKOVF bit will remain set and the Stack Pointer will be set to zero. If STVREN is cleared, the STKOVF bit will be set on the 32nd push and the Stack Pointer will remain at 31 but no Reset will occur. Any additional pushes will overwrite the 31st push but the STKPTR will remain at 31. Setting STKOVF = 1 in software will change the bit, but will not generate a Reset. The STKUNF bit is set when a stack pop returns a value of zero. The STKUNF bit is cleared by software or by POR. The action that takes place when the stack becomes full depends on the state of the STVREN (Stack Overflow Reset Enable) Configuration bit. If STVREN is set (default) and the stack has been popped enough times to unload the stack, the next pop will return a value of zero to the PC, it will set the STKUNF bit and a Reset will be generated. This condition can be generated by the RETURN, RETLW and RETFIE instructions. If STVREN is cleared, the STKUNF bit will be set, but no Reset will occur. Important: Returning a value of zero to the PC on an underflow has the effect of vectoring the program to the Reset vector, where the stack conditions can be verified and appropriate actions can be taken. This is not the same as a Reset, as the contents of the SFRs are not affected. Related Links 3.7.2 CONFIG2 (c)2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 120 PIC18F26/45/46Q10 Memory Organization 10.1.2.3 Stack Overflow and Underflow Resets Device Resets on Stack Overflow and Stack Underflow conditions are enabled by setting the STVREN Configuration bit in Configuration. When STVREN is set, a Full or Underflow condition will set the respective STKOVF or STKUNF bit and then cause a device Reset. When STVREN is cleared, a Full or Underflow condition will set the respective STKOVF or STKUNF bit but not cause a device Reset. The STKOVF or STKUNF bits are cleared by the user software or a Power-on Reset. 10.1.2.4 PUSH and POP Instructions Since the Top-of-Stack is readable and writable, the ability to push values onto the stack and pull values off the stack without disturbing normal program execution is a desirable feature. The PIC18 instruction set includes two instructions, PUSH and POP, that permit the TOS to be manipulated under software control. TOSU, TOSH and TOSL can be modified to place data or a return address on the stack. The PUSH instruction places the current PC value onto the stack. This increments the Stack Pointer and loads the current PC value onto the stack. The POP instruction discards the current TOS by decrementing the Stack Pointer. The previous value pushed onto the stack then becomes the TOS value. 10.1.2.5 Fast Register Stack A Fast Register Stack is provided for the STATUS, WREG and BSR registers, to provide a "fast return" option for interrupts. The Stack for each register is only one level deep and is neither readable nor writable. It is loaded with the current value of the corresponding register when the processor vectors for an interrupt. All interrupt sources will push values into the Fast Register Stack. The values in the registers are then loaded back into their associated registers if the RETFIE, FAST instruction is used to return from the interrupt. Important: The TO and PD bits of the STATUS register are not copied over in this operation. If both low and high-priority interrupts are enabled, the Stack registers cannot be used reliably to return from low-priority interrupts. If a high-priority interrupt occurs while servicing a low-priority interrupt, the Stack register values stored by the low-priority interrupt will be overwritten. In these cases, users must save the key registers by software during a low-priority interrupt. If interrupt priority is not used, all interrupts may use the Fast Register Stack for returns from interrupt. If no interrupts are used, the Fast Register Stack can be used to restore the STATUS, WREG and BSR registers at the end of a subroutine call. To use the Fast Register Stack for a subroutine call, a CALL label, FAST instruction must be executed to save the STATUS, WREG and BSR registers to the Fast Register Stack. A RETURN, FAST instruction is then executed to restore these registers from the Fast Register Stack. The following example shows a source code example that uses the Fast Register Stack during a subroutine call and return. Example 10-1. Fast Register Stack Code Example CALL SUB1, FAST * * SUB1: * (c) 2019 Microchip Technology Inc. ;STATUS, WREG, BSR SAVED IN FAST REGISTER STACK Datasheet Preliminary DS40001996C-page 121 PIC18F26/45/46Q10 Memory Organization * RETURN, FAST 10.1.3 ;RESTORE VALUES SAVED IN FAST REGISTER STACK Look-up Tables in Program Memory There may be programming situations that require the creation of data structures, or look-up tables, in program memory. For PIC18 devices, look-up tables can be implemented in two ways: * Computed GOTO * Table Reads 10.1.3.1 Computed GOTO A computed GOTO is accomplished by adding an offset to the Program Counter. An example is shown in the following code example. A look-up table can be formed with an ADDWF PCL instruction and a group of RETLW nn instructions. The W register is loaded with an offset into the table before executing a call to that table. The first instruction of the called routine is the ADDWF PCL instruction. The next instruction executed will be one of the RETLW nn instructions that returns the value `nn' to the calling function. The offset value (in WREG) specifies the number of bytes that the Program Counter should advance and must be multiples of two (LSb = 0). In this method, only one data byte may be stored in each instruction location and room on the return address stack is required. Example 10-2. Computed GOTO Using an Offset Value RLNCF CALL ORG TABLE: ADDWF RETLW RETLW RETLW . . . OFFSET, W TABLE ; W must be an even number, Max OFFSET = 127 nn00h ; 00 in LSByte ensures no addition overflow PCL A B C ; ; ; ; Add OFFSET to program counter Value @ OFFSET=0 Value @ OFFSET=1 Value @ OFFSET=2 10.1.3.2 Table Reads and Table Writes A more compact method of storing data in program memory allows two bytes of data to be stored in each instruction location. Look-up table data may be stored two bytes per program word by using table reads and writes. The Table Pointer (TBLPTR) register specifies the byte address and the Table Latch (TABLAT) register contains the data that is read from or written to program memory. Data is transferred to or from program memory one byte at a time. Table read and table write operations are discussed further in the Table Reads and Table Writes section. (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 122 PIC18F26/45/46Q10 Memory Organization 10.2 PIC18 Instruction Cycle 10.2.1 Clocking Scheme The microcontroller clock input, whether from an internal or external source, is internally divided by four to generate four non-overlapping quadrature clocks (Q1, Q2, Q3 and Q4). Internally, the Program Counter is incremented on every Q1; the instruction is fetched from the program memory and latched into the instruction register during Q4. The instruction is decoded and executed during the following Q1 through Q4. The clocks and instruction execution flow are shown in the following figure. Figure 10-4. CLOCK/INSTRUCTION CYCLE Rev. 30-000095A 4/13/2017 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 OSC1 Q1 Q2 Internal Phase Clock Q3 Q4 PC PC PC + 2 PC + 4 OSC2/CLKOUT (RC mode) Execute INST (PC - 2) Fetch INST (PC) 10.2.2 Execute INST (PC) Fetch INST (PC + 2) Execute INST (PC + 2) Fetch INST (PC + 4) Instruction Flow/Pipelining An "Instruction Cycle" consists of four Q cycles: Q1 through Q4. The instruction fetch and execute are pipelined in such a manner that a fetch takes one instruction cycle, while the decode and execute take another instruction cycle. However, due to the pipelining, each instruction effectively executes in one cycle. If an instruction causes the Program Counter to change (e.g., GOTO), then two cycles are required to complete the instruction as shown in the figure below. A fetch cycle begins with the Program Counter (PC) incrementing in Q1. In the execution cycle, the fetched instruction is latched into the Instruction Register (IR) in cycle Q1. This instruction is then decoded and executed during the Q2, Q3 and Q4 cycles. Data memory is read during Q2 (operand read) and written during Q4 (destination write). Figure 10-5. Instruction Pipeline Flow Rev. 10-000337A 9/27/2017 1. MOVLW 55h 2. MOVWF PORTB TCY0 TCY1 Fetch 1 Execute 1 3. BRA Sub_1 4. BSF PORTA, BITS (Forced NOP) Fetch 2 TCY2 TCY3 TCY4 TCY5 Execute 2 Fetch 3 Execute 3 Fetch 4 5. Instruction @ address Sub_1 Flush (NOP) Fetch Sub_1 Execute Sub_1 All instructions are single cycle except for any program branches. These take two cycles since the fetch instruction is "flushed" from the pipeline while the new instruction is being fetched and then executed. (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 123 PIC18F26/45/46Q10 Memory Organization 10.2.3 Instructions in Program Memory The program memory is addressed in bytes. Instructions are stored as either two bytes or four bytes in program memory. The Least Significant Byte of an instruction word is always stored in a program memory location with an even address (LSb = 0). To maintain alignment with instruction boundaries, the PC increments in steps of two and the LSb will always read `0' (see 10.1.1 Program Counter). The Instructions in Program Memory figure below shows how instruction words are stored in the program memory. The CALL and GOTO instructions have the absolute program memory address embedded into the instruction. Since instructions are always stored on word boundaries, the data contained in the instruction is a word address. The word address is written to PC<20:1>, which accesses the desired byte address in program memory. Instruction #2 in the example shows how the instruction GOTO 0006h is encoded in the program memory. Program branch instructions, which encode a relative address offset, operate in the same manner. The offset value stored in a branch instruction represents the number of single-word instructions that the PC will be offset by. The Instruction Set Summary provides further details of the instruction set. Figure 10-6. Instructions in Program Memory LSB = 1 LSB = 0 0Fh EFh F0h C1h F4h 55h 03h 00h 23h 56h Program Memory Byte Locations Instruction 1: Instruction 2: MOVLW GOTO 055h 0006h Instruction 3: MOVFF 123h, 456h Word Address 000000h 000002h 000004h 000006h 000008h 00000Ah 00000Ch 00000Eh 000010h 000012h 000014h Rev. 30-000112A4/19/2017 Related Links 37. Instruction Set Summary 10.2.4 Two-Word Instructions The standard PIC18 instruction set has four two-word instructions: CALL, MOVFF, GOTO and LFSR. In all cases, the second word of the instruction always has `1111' as its four Most Significant bits; the other 12 bits are literal data, usually a data memory address. The use of `1111' in the 4 MSbs of an instruction specifies a special form of NOP. If the instruction is executed in proper sequence - immediately after the first word - the data in the second word is accessed and used by the instruction sequence. If the first word is skipped for some reason and the second word is executed by itself, a NOP is executed instead. This is necessary for cases when the two-word instruction is preceded by a conditional instruction that changes the PC. The Two-Word Instructions figure below shows how this works. Important: See the 10.6 PIC18 Instruction Execution and the Extended Instruction Set section for information on two-word instructions in the extended instruction set. (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 124 PIC18F26/45/46Q10 Memory Organization Figure 10-7. Two-Word Instructions Rev. 30-000113A 4/19/2017 CASE 1: Object Code 0110 0110 0000 1100 0001 0010 1111 0100 0101 0010 0100 0000 0000 0011 0110 0000 Source Code TSTFSZ REG1 ; is RAM location 0? MOVFF REG1, REG2 ; No, skip this word ; Execute this word as a NOP ADDWF REG3 ; continue code 0000 0011 0110 0000 Source Code TSTFSZ REG1 ; is RAM location 0? MOVFF REG1, REG2 ; Yes, execute this word ; 2nd word of instruction ADDWF REG3 ; continue code CASE 2: Object Code 0110 0110 0000 1100 0001 0010 1111 0100 0101 0010 0100 0000 10.3 Data Memory Organization Important: The operation of some aspects of data memory are changed when the PIC18 extended instruction set is enabled. See 10.6 PIC18 Instruction Execution and the Extended Instruction Set for more information. The data memory in PIC18 devices is implemented as static RAM. Each register in the data memory has a 12-bit address, allowing up to 4096 bytes of data memory. The memory space is divided into as many as 16 banks that contain 256 bytes each. The figure below shows the data memory organization for all devices in the device family. The data memory contains Special Function Registers (SFRs) and General Purpose Registers (GPRs). The SFRs are used for control and status of the controller and peripheral functions, while GPRs are used for data storage and scratchpad operations in the user's application. Any read of an unimplemented location will read as `0's. The instruction set and architecture allow operations across all banks. The entire data memory may be accessed by Direct, Indirect or Indexed Addressing modes. Addressing modes are discussed later in this subsection. To ensure that commonly used registers (SFRs and select GPRs) can be accessed in a single cycle, PIC18 devices implement an Access Bank. This is a 256-byte memory space that provides fast access to SFRs and the lower portion of GPR Bank 0 without using the Bank Select Register (BSR). The 10.3.2 Access Bank section provides a detailed description of the Access RAM. (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 125 PIC18F26/45/46Q10 Memory Organization Figure 10-8. Data Memory Map Rev. 40-000102C 6/16/2017 BanK BSR<3:0> addr<11:8> addr<7:0> PIC18F 45Q10 26Q10 46Q10 00h-5Fh 0 0h 1 1h 00h-FFh 2 2h 00h-FFh 3 3h 00h-FFh 4 4h 00h-FFh 5 5h 00h-FFh 6 6h 00h-FFh 60h-FFh 7 7h 00h-FFh 8 8h 00h-FFh Virtual Access Bank 9 9h 00h-FFh 00h-5Fh 10 Ah 00h-FFh 60h-FFh 11 Bh 00h-FFh 12 Ch 00h-FFh 13 Dh 00h-FFh 00h-1Eh 14 Eh 1Fh-9Ah 9Bh-FFh 15 Fh 00h-5Fh 60h-FFh GPR SFR Sector RAM Unimplemented 10.3.1 Bank Select Register Large areas of data memory require an efficient addressing scheme to make rapid access to any address possible. Ideally, this means that an entire address does not need to be provided for each read or write operation. For PIC18 devices, this is accomplished with a RAM banking scheme. This divides the memory space into 16 contiguous banks of 256 bytes. Depending on the instruction, each location can be addressed directly by its full 12-bit address, or an 8-bit low-order address and a 4-bit Bank Pointer. Most instructions in the PIC18 instruction set make use of the Bank Pointer, known as the Bank Select Register (10.8.13 BSR). This SFR holds the four Most Significant bits of a location's address; the instruction itself includes the eight Least Significant bits. Only the four lower bits of the BSR are implemented (BSR<3:0>). The upper four bits are unused; they will always read `0' and cannot be written to. The BSR can be loaded directly by using the MOVLB instruction. The value of the BSR indicates the bank in data memory; the eight bits in the instruction show the location in the bank and can be thought of as an offset from the bank's lower boundary. The relationship between the BSR's value and the bank division in data memory is shown in the figure below. (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 126 PIC18F26/45/46Q10 Memory Organization Since up to 16 registers may share the same low-order address, the user must always be careful to ensure that the proper bank is selected before performing a data read or write. For example, writing what should be program data to an 8-bit address of F9h while the BSR is 0Fh will end up resetting the Program Counter. While any bank can be selected, only those banks that are actually implemented can be read or written to. Writes to unimplemented banks are ignored, while reads from unimplemented banks will return `0's. Even so, the STATUS register will still be affected as if the operation was successful. The data memory maps in the following figure indicate which banks are implemented. In the core PIC18 instruction set, only the MOVFF instruction fully specifies the 12-bit address of the source and target registers. This instruction ignores the BSR completely when it executes. All other instructions include only the low-order address as an operand and must use either the BSR or the Access Bank to locate their target registers. Figure 10-9. Use of the Bank Select Register (Direct Addressing) 0 Data Memory BSR(1) 7 0 0 0 0 Rev. 30-000108A 09/07/2017 0 0 1 000h 0 100h Bank Select(2) 200h Bank 0 Bank 1 Bank 2 300h 00h FFh 00h From Opcode(2) 7 1 1 1 1 1 1 0 1 1 FFh 00h FFh Bank 3 through Bank 13 E00h F00h FFFh Note 1: 2: 10.3.2 Bank 14 Bank 15 00h FFh 00h FFh The Access RAM bit of the instruction can be used to force an override of the selected bank (BSR<3:0>) to the registers of the Access Bank. The MOVFF instruction embeds the entire 12-bit address in the instruction. Access Bank While the use of the BSR with an embedded 8-bit address allows users to address the entire range of data memory, it also means that the user must always ensure that the correct bank is selected. Otherwise, data may be read from or written to the wrong location. This can be disastrous if a GPR is the intended target of an operation, but an SFR is written to instead. Verifying and/or changing the BSR for each read or write to data memory can become very inefficient. To streamline access for the most commonly used data memory locations, the data memory is configured with an Access Bank, which allows users to access a mapped block of memory without specifying a BSR. The Access Bank consists of the first 96 bytes of memory (00h-5Fh) in Bank 0 and the last 160 bytes of memory (60h-FFh) in Block 15. The lower half is known as the "Access RAM" and is composed of GPRs. This upper half is also where the device's SFRs are mapped. These two areas are mapped contiguously (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 127 PIC18F26/45/46Q10 Memory Organization in the Access Bank and can be addressed in a linear fashion by an 8-bit address (see Data Memory Map). The Access Bank is used by core PIC18 instructions that include the Access RAM bit (the `a' parameter in the instruction). When `a' is equal to `1', the instruction uses the BSR and the 8-bit address included in the opcode for the data memory address. When `a' is `0', however, the instruction is forced to use the Access Bank address map; the current value of the BSR is ignored entirely. Using this "forced" addressing allows the instruction to operate on a data address in a single cycle, without updating the BSR first. For 8-bit addresses of 60h and above, this means that users can evaluate and operate on SFRs more efficiently. The Access RAM below 60h is a good place for data values that the user might need to access rapidly, such as immediate computational results or common program variables. Access RAM also allows for faster and more code efficient context saving and switching of variables. The mapping of the Access Bank is slightly different when the extended instruction set is enabled (XINST Configuration bit = 1). This is discussed in more detail in the 10.5.3 Mapping the Access Bank in Indexed Literal Offset Mode section. 10.3.3 General Purpose Register File PIC18 devices may have banked memory in the GPR area. This is data RAM, which is available for use by all instructions. GPRs start at the bottom of Bank 0 (address 000h) and grow upwards towards the bottom of the SFR area. GPRs are not initialized by a Power-on Reset and are unchanged on all other Resets. 10.3.4 Special Function Registers The Special Function Registers (SFRs) are registers used by the CPU and peripheral modules for controlling the desired operation of the device. These registers are implemented as static RAM. SFRs start at the top of data memory (FFFh) and extend downward. A list of these registers is given in the register summary table. The SFRs can be classified into two sets: those associated with the "core" device functionality (ALU, Resets and interrupts) and those related to the peripheral functions. The Reset and Interrupt registers are described in their respective chapters, while the ALU's STATUS register is described later in this section. Registers related to the operation of a peripheral feature are described in the chapter for that peripheral. The SFRs are typically distributed among the peripherals whose functions they control. Unused SFR locations are unimplemented and read as `0's. Related Links 35. Register Summary 10.3.5 Status Register The 10.8.5 STATUS register contains the arithmetic status of the ALU. As with any other SFR, it can be the operand for any instruction. If the STATUS register is the destination for an instruction that affects the Z, DC, C, OV or N bits, the results of the instruction are not written; instead, the STATUS register is updated according to the instruction performed. Therefore, the result of an instruction with the STATUS register as its destination may be different than intended. As an example, CLRF STATUS will set the Z bit and leave the remaining Status bits unchanged (`000u u1uu'). (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 128 PIC18F26/45/46Q10 Memory Organization It is recommended that only BCF, BSF, SWAPF, MOVFF and MOVWF instructions are used to alter the STATUS register, because these instructions do not affect the Z, C, DC, OV or N bits in the STATUS register. For other instructions that do not affect Status bits, see the instruction set summaries. Important: The C and DC bits operate as the borrow and digit borrow bits, respectively, in subtraction. Related Links 37. Instruction Set Summary 10.4 Data Addressing Modes Important: The execution of some instructions in the core PIC18 instruction set are changed when the PIC18 extended instruction set is enabled. See 10.5 Data Memory and the Extended Instruction Set for more information. Information in the data memory space can be addressed in several ways. For most instructions, the Addressing mode is fixed. Other instructions may use up to three modes, depending on which operands are used and whether or not the extended instruction set is enabled. The Addressing modes are: * * * * Inherent Literal Direct Indirect An additional Addressing mode, Indexed Literal Offset, is available when the extended instruction set is enabled (XINST Configuration bit = 1). Its operation is discussed in greater detail in 10.5.1 Indexed Addressing with Literal Offset. 10.4.1 Inherent and Literal Addressing Many PIC18 control instructions do not need any argument at all; they either perform an operation that globally affects the device or they operate implicitly on one register. This Addressing mode is known as Inherent Addressing. Examples include SLEEP, RESET and DAW. Other instructions work in a similar way but require an additional explicit argument in the opcode. This is known as Literal Addressing mode because they require some literal value as an argument. Examples include ADDLW and MOVLW, which respectively, add or move a literal value to the W register. Other examples include CALL and GOTO, which include a 20-bit program memory address. 10.4.2 Direct Addressing Direct Addressing specifies all or part of the source and/or destination address of the operation within the opcode itself. The options are specified by the arguments accompanying the instruction. In the core PIC18 instruction set, bit-oriented and byte-oriented instructions use some version of Direct Addressing by default. All of these instructions include some 8-bit literal address as their Least Significant (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 129 PIC18F26/45/46Q10 Memory Organization Byte. This address specifies either a register address in one of the banks of data RAM (see 10.3.3 General Purpose Register File) or a location in the Access Bank (see 10.3.2 Access Bank) as the data source for the instruction. The Access RAM bit `a' determines how the address is interpreted. When `a' is `1', the contents of the BSR (see 10.3.1 Bank Select Register) are used with the address to determine the complete 12-bit address of the register. When `a' is `0', the address is interpreted as being a register in the Access Bank. Addressing that uses the Access RAM is sometimes also known as Direct Forced Addressing mode. A few instructions, such as MOVFF, include the entire 12-bit address (either source or destination) in their opcodes. In these cases, the BSR is ignored entirely. The destination of the operation's results is determined by the destination bit `d'. When `d' is `1', the results are stored back in the source register, overwriting its original contents. When `d' is `0', the results are stored in the W register. Instructions without the `d' argument have a destination that is implicit in the instruction; their destination is either the target register being operated on or the W register. 10.4.3 Indirect Addressing Indirect Addressing allows the user to access a location in data memory without giving a fixed address in the instruction. This is done by using File Select Registers (FSRs) as pointers to the locations which are to be read or written. Since the FSRs are themselves located in RAM as Special File Registers, they can also be directly manipulated under program control. This makes FSRs very useful in implementing data structures, such as tables and arrays in data memory. The registers for Indirect Addressing are also implemented with Indirect File Operands (INDFs) that permit automatic manipulation of the pointer value with auto-incrementing, auto-decrementing or offsetting with another value. This allows for efficient code, using loops, such as the following example of clearing an entire RAM bank. Example 10-3. How to Clear RAM (Bank 1) Using Indirect Addressing LFSR FSR0,100h ; Set FSR0 to beginning of Bank1 CLRF POSTINC0 ; Clear location in Bank1 then increment FSR0 BTFSS BRA FSR0H,1 NEXT ; Has high FSR0 byte incremented to next bank? ; NO, clear next byte in Bank1 NEXT: CONTINUE: ; YES, continue 10.4.3.1 FSR Registers and the INDF Operand At the core of Indirect Addressing are three sets of registers: FSR0, FSR1 and FSR2. Each represents a pair of 8-bit registers, FSRnH and FSRnL. Each FSR pair holds a 12-bit value, therefore, the four upper bits of the FSRnH register are not used. The 12-bit FSR value can address the entire range of the data memory in a linear fashion. The FSR register pairs, then, serve as pointers to data memory locations. Indirect Addressing is accomplished with a set of Indirect File Operands, INDF0 through INDF2. These can be thought of as "virtual" registers; they are mapped in the SFR space but are not physically implemented. Reading or writing to a particular INDF register actually accesses its corresponding FSR register pair. A read from INDF1, for example, reads the data at the address indicated by FSR1H:FSR1L. Instructions that use the INDF registers as operands actually use the contents of their corresponding FSR as a pointer to the instruction's target. The INDF operand is just a convenient way of using the pointer. Because Indirect Addressing uses a full 12-bit address, the FSR value can target any location in any bank regardless of the BSR value. However, the Access RAM bit must be cleared to 0 to ensure that the (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 130 PIC18F26/45/46Q10 Memory Organization INDF register in Access space is the object of the operation instead of a register in one of the other banks. The assembler default value for the Access RAM bit is zero when targeting any of the indirect operands. 10.4.3.2 FSR Registers and POSTINC, POSTDEC, PREINC and PLUSW In addition to the INDF operand, each FSR register pair also has four additional indirect operands. Like INDF, these are "virtual" registers that cannot be directly read or written. Accessing these registers actually accesses the location to which the associated FSR register pair points, and also performs a specific action on the FSR value. They are: * POSTDEC: accesses the location to which the FSR points, then automatically decrements the FSR by 1 afterwards * POSTINC: accesses the location to which the FSR points, then automatically increments the FSR by 1 afterwards * PREINC: automatically increments the FSR by one, then uses the location to which the FSR points in the operation * PLUSW: adds the signed value of the W register (range of -127 to 128) to that of the FSR and uses the location to which the result points in the operation. In this context, accessing an INDF register uses the value in the associated FSR register without changing it. Similarly, accessing a PLUSW register gives the FSR value an offset by that in the W register; however, neither W nor the FSR is actually changed in the operation. Accessing the other virtual registers changes the value of the FSR register. Figure 10-10. Indirect Addressing Rev. 30-000109A 4/18/2017 000h Using an instruction with one of the Indirect Addressing registers as the operand.... ADDWF, INDF1, 0 100h Bank 0 Bank 1 200h ...uses the 12-bit address stored in the FSR pair associated with that register.... 300h FSR1H:FSR1L 7 0 x x x x 1 1 1 0 7 0 Bank 2 Bank 3 through Bank 13 1 1 0 0 1 1 0 0 ...to determine the data memory location to be used in that operation. E00h In this case, the FSR1 pair contains ECCh. This means the contents of location ECCh will be added to that of the W register and stored back in ECCh. F00h FFFh Bank 14 Bank 15 Data Memory Operations on the FSRs with POSTDEC, POSTINC and PREINC affect the entire register pair; that is, rollovers of the FSRnL register from FFh to 00h carry over to the FSRnH register. On the other hand, results of these operations do not change the value of any flags in the STATUS register (e.g., Z, N, OV, etc.). (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 131 PIC18F26/45/46Q10 Memory Organization The PLUSW register can be used to implement a form of Indexed Addressing in the data memory space. By manipulating the value in the W register, users can reach addresses that are fixed offsets from pointer addresses. In some applications, this can be used to implement some powerful program control structure, such as software stacks, inside of data memory. 10.4.3.3 Operations by FSRs on FSRs Indirect Addressing operations that target other FSRs or virtual registers represent special cases. For example, using an FSR to point to one of the virtual registers will not result in successful operations. As a specific case, assume that FSR0H:FSR0L contains the address of INDF1. Attempts to read the value of the INDF1 using INDF0 as an operand will return 00h. Attempts to write to INDF1 using INDF0 as the operand will result in a NOP. On the other hand, using the virtual registers to write to an FSR pair may not occur as planned. In these cases, the value will be written to the FSR pair but without any incrementing or decrementing. Thus, writing to either the INDF2 or POSTDEC2 register will write the same value to the FSR2H:FSR2L. Since the FSRs are physical registers mapped in the SFR space, they can be manipulated through all direct operations. Users should proceed cautiously when working on these registers, particularly if their code uses Indirect Addressing. Similarly, operations by Indirect Addressing are generally permitted on all other SFRs. Users should exercise the appropriate caution that they do not inadvertently change settings that might affect the operation of the device. 10.5 Data Memory and the Extended Instruction Set Enabling the PIC18 extended instruction set (XINST Configuration bit = 1) significantly changes certain aspects of data memory and its addressing. Specifically, the use of the Access Bank for many of the core PIC18 instructions is different; this is due to the introduction of a new Addressing mode for the data memory space. What does not change is just as important. The size of the data memory space is unchanged, as well as its linear addressing. The SFR map remains the same. Core PIC18 instructions can still operate in both Direct and Indirect Addressing mode; inherent and literal instructions do not change at all. Indirect addressing with FSR0 and FSR1 also remain unchanged. 10.5.1 Indexed Addressing with Literal Offset Enabling the PIC18 extended instruction set changes the behavior of Indirect Addressing using the FSR2 register pair within Access RAM. Under the proper conditions, instructions that use the Access Bank - that is, most bit-oriented and byte-oriented instructions - can invoke a form of Indexed Addressing using an offset specified in the instruction. This special Addressing mode is known as Indexed Addressing with Literal Offset, or Indexed Literal Offset mode. When using the extended instruction set, this Addressing mode requires the following: * The use of the Access Bank is forced (`a' = 0) and * The file address argument is less than or equal to 5Fh. Under these conditions, the file address of the instruction is not interpreted as the lower byte of an address (used with the BSR in Direct Addressing), or as an 8-bit address in the Access Bank. Instead, the value is interpreted as an offset value to an Address Pointer, specified by FSR2. The offset and the contents of FSR2 are added to obtain the target address of the operation. (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 132 PIC18F26/45/46Q10 Memory Organization 10.5.2 Instructions Affected by Indexed Literal Offset Mode Any of the core PIC18 instructions that can use Direct Addressing are potentially affected by the Indexed Literal Offset Addressing mode. This includes all byte-oriented and bit-oriented instructions, or almost one-half of the standard PIC18 instruction set. Instructions that only use Inherent or Literal Addressing modes are unaffected. Additionally, byte-oriented and bit-oriented instructions are not affected if they do not use the Access Bank (Access RAM bit is `1'), or include a file address of 60h or above. Instructions meeting these criteria will continue to execute as before. A comparison of the different possible Addressing modes when the extended instruction set is enabled is shown in the following figure. Those who desire to use byte-oriented or bit-oriented instructions in the Indexed Literal Offset mode should note the changes to assembler syntax for this mode. This is described in more detail in the Extended Instruction Syntax section. (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 133 PIC18F26/45/46Q10 Memory Organization Figure 10-11. Comparing Addressing Options for Bit-Oriented and Byte-Oriented Instructions (Extended Instruction Set Enabled) Rev. 30-000110A 4/18/2017 EXAMPLE INSTRUCTION: ADDWF, f, d, a (Opcode: 0010 01da ffff ffff) When `a' = 0 and f 60h: The instruction executes in Direct Forced mode. `f' is interpreted as a location in the Access RAM between 060h and 0FFh. This is the same as locations F60h to FFFh (Bank 15) of data memory. Locations below 60h are not available in this addressing mode. 000h 060h Bank 0 100h Note that in this mode, the correct syntax is now: ADDWF [k], d where `k' is the same as `f'. When `a' = 1 (all values of f): The instruction executes in Direct mode (also known as Direct Long mode). `f' is interpreted as a location in one of the 16 banks of the data memory space. The bank is designated by the Bank Select Register (BSR). The address can be in any implemented bank in the data memory space. 60h Valid range for `f' Access RAM F00h FFh Bank 15 F60h FFFh When `a' = 0 and f 5Fh: The instruction executes in Indexed Literal Offset mode. `f' is interpreted as an offset to the address value in FSR2. The two are added together to obtain the address of the target register for the instruction. The address can be anywhere in the data memory space. 00h Bank 1 through Bank 14 SFRs Data Memory 000h 060h Bank 0 100h 001001da ffffffff Bank 1 through Bank 14 FSR2H FSR2L F00h Bank 15 F60h SFRs FFFh Data Memory BSR 00000000 000h 060h Bank 0 100h Bank 1 through Bank 14 001001da ffffffff F00h Bank 15 F60h SFRs FFFh (c) 2019 Microchip Technology Inc. Data Memory Datasheet Preliminary DS40001996C-page 134 PIC18F26/45/46Q10 Memory Organization Related Links 37.2.1 Extended Instruction Syntax 10.5.3 Mapping the Access Bank in Indexed Literal Offset Mode The use of Indexed Literal Offset Addressing mode effectively changes how the first 96 locations of Access RAM (00h to 5Fh) are mapped. Rather than containing just the contents of the bottom section of Bank 0, this mode maps the contents from a user defined "window" that can be located anywhere in the data memory space. The value of FSR2 establishes the lower boundary of the addresses mapped into the window, while the upper boundary is defined by FSR2 plus 95 (5Fh). Addresses in the Access RAM above 5Fh are mapped as previously described (see 10.3.2 Access Bank). An example of Access Bank remapping in this Addressing mode is shown in the following figure. Figure 10-12. Remapping the Access Bank with Indexed Literal Offset Addressing Rev. 30-000111A 4/18/2017 Example Situation: ADDWF f, d, a FSR2H:FSR2L = 120h Locations in the region from the FSR2 pointer (120h) to the pointer plus 05Fh (17Fh) are mapped to the bottom of the Access RAM (000h-05Fh). 000h Bank 0 100h 120h 17Fh 200h Bank 1 Window Bank 1 00h Bank 1 "Window" 5Fh 60h Special File Registers at F60h through FFFh are mapped to 60h through FFh, as usual. Bank 2 through Bank 14 Bank 0 addresses below 5Fh can still be addressed by using the BSR. SFRs FFh Access Bank F00h Bank 15 F60h FFFh SFRs Data Memory Remapping of the Access Bank applies only to operations using the Indexed Literal Offset mode. Operations that use the BSR (Access RAM bit is `1') will continue to use Direct Addressing as before. 10.6 PIC18 Instruction Execution and the Extended Instruction Set Enabling the extended instruction set adds eight additional commands to the existing PIC18 instruction set. These instructions are executed as described in the Extended Instruction Set section. Related Links 37.2.1 Extended Instruction Syntax (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 135 PIC18F26/45/46Q10 Memory Organization 10.7 Register Summary: Memory and Status Address Name Bit Pos. 0x0FD8 STATUS 7:0 0x0FD9 FSR2 TO PD 7:0 N OV Z DC C FSRL[7:0] 15:8 FSRH[3:0] 0x0FDB PLUSW2 7:0 PLUSW[7:0] 0x0FDC PREINC2 7:0 PREINC[7:0] 0x0FDD POSTDEC2 7:0 POSTDEC[7:0] 0x0FDE POSTINC2 7:0 POSTINC[7:0] 0x0FDF INDF2 7:0 INDF[7:0] 0x0FE0 BSR 7:0 0x0FE1 FSR1 BSR[3:0] 7:0 FSRL[7:0] 15:8 FSRH[3:0] 0x0FE3 PLUSW1 7:0 PLUSW[7:0] 0x0FE4 PREINC1 7:0 PREINC[7:0] 0x0FE5 POSTDEC1 7:0 POSTDEC[7:0] 0x0FE6 POSTINC1 7:0 POSTINC[7:0] 0x0FE7 INDF1 7:0 INDF[7:0] 0x0FE8 WREG 7:0 WREG[7:0] 0x0FE9 FSR0 7:0 FSRL[7:0] 15:8 FSRH[3:0] 0x0FEB PLUSW0 7:0 PLUSW[7:0] 0x0FEC PREINC0 7:0 PREINC[7:0] 0x0FED POSTDEC0 7:0 POSTDEC[7:0] 0x0FEE POSTINC0 7:0 POSTINC[7:0] 0x0FEF INDF0 7:0 INDF[7:0] 7:0 PCL[7:0] 7:0 PCLATH[7:0] 0x0FF0 ... Reserved 0x0FF8 0x0FF9 PCL 0x0FFA PCLAT 0x0FFC 0x0FFD 15:8 PCLATU[4:0] STKPTR 7:0 STKPTR[4:0] 7:0 TOSL[7:0] TOS 15:8 TOSH[7:0] 23:16 10.8 TOSU[4:0] Register Definitions: Memory and Status (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 136 PIC18F26/45/46Q10 Memory Organization 10.8.1 PCL Name: Address: PCL 0xFF9 Low byte of the Program Counter Bit 7 6 5 4 3 2 1 0 PCL[7:0] Access Reset R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Bits 7:0 - PCL[7:0] Provides direct read and write access to the Program Counter (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 137 PIC18F26/45/46Q10 Memory Organization 10.8.2 PCLAT Name: Address: PCLAT 0xFFA Program Counter Latches. Holding register for bits <21:9> of the Program Counter (PC). Reads of the PCL register transfer the upper PC bits to the PCLAT register. Writes to PCL register transfer the PCLAT value to the PC. Bit 15 14 13 12 11 10 9 8 PCLATU[4:0] Access Reset Bit 7 6 5 R/W R/W R/W R/W R/W 0 0 0 0 0 3 2 1 0 4 PCLATH[7:0] Access Reset R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Bits 12:8 - PCLATU[4:0] Upper PC Latch register Holding register for Program Counter bits <21:17> Bits 7:0 - PCLATH[7:0] High PC Latch register Holding register for Program Counter bits <16:8> (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 138 PIC18F26/45/46Q10 Memory Organization 10.8.3 TOS Name: Address: TOS 0xFFD Top-Of-Stack Registers. Contents of the stack pointed to by the 10.8.4 STKPTR register. This is the value that will be loaded into the Program Counter upon a RETURN or RETFIE instruction. Bit 23 22 21 20 19 18 17 16 TOSU[4:0] Access Reset Bit 15 14 13 R/W R/W R/W R/W R/W 0 0 0 0 0 11 10 9 8 12 TOSH[7:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 TOSL[7:0] Access Reset Bits 20:16 - TOSU[4:0] Upper byte of TOS register Bits <21:17> of the TOS Bits 15:8 - TOSH[7:0] High Byte of the TOS Register Bits <16:8> of the TOS Bits 7:0 - TOSL[7:0] Low Byte TOS Register Bits <7:0> of the TOS (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 139 PIC18F26/45/46Q10 Memory Organization 10.8.4 STKPTR Name: Address: STKPTR 0xFFC Stack Pointer Register Bit 7 6 5 4 3 2 1 0 STKPTR[4:0] Access Reset R/W R/W R/W R/W R/W 0 0 0 0 0 Bits 4:0 - STKPTR[4:0] Stack Pointer Location bits (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 140 PIC18F26/45/46Q10 Memory Organization 10.8.5 STATUS Name: Address: STATUS 0xFD8 Status Register Bit 7 6 5 4 3 2 1 0 TO PD N OV Z DC C Access R R R/W R/W R/W R/W R/W Reset 1 1 0 0 0 0 0 Bit 6 - TO Time-Out bit Reset States: POR/BOR = 1 All Other Resets = q Value Description 1 Set at power-up or by execution of CLRWDT or SLEEP instruction 0 A WDT time-out occurred Bit 5 - PD Power-Down bit Reset States: POR/BOR = 1 All Other Resets = q Value Description 1 Set at power-up or by execution of CLRWDT instruction 0 Cleared by execution of the SLEEP instruction Bit 4 - N Negative bit Used for signed arithmetic (2's complement); indicates if the result is negative, (ALU MSb = 1). Reset States: POR/BOR = 0 All Other Resets = u Value Description 1 The result is negative 0 The result is positive Bit 3 - OV Overflow bit Used for signed arithmetic (2's complement); indicates an overflow of the 7-bit magnitude, which causes the sign bit (bit 7) to change state. Reset States: POR/BOR = 0 All Other Resets = u Value Description 1 Overflow occurred for current signed arithmetic operation 0 No overflow occurred Bit 2 - Z Zero bit Reset States: POR/BOR = 0 All Other Resets = u Value Description 1 The result of an arithmetic or logic operation is zero (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 141 PIC18F26/45/46Q10 Memory Organization Value 0 Description The result of an arithmetic or logic operation is not zero Bit 1 - DC Digit Carry/Borrow bit ADDWF, ADDLW, SUBLW, SUBWF instructions(1) Reset States: POR/BOR = 0 All Other Resets = u Value Description 1 A carry-out from the 4th low-order bit of the result occurred 0 No carry-out from the 4th low-order bit of the result Bit 0 - C Carry/Borrow bit ADDWF, ADDLW, SUBLW, SUBWF instructions(1,2) Reset States: POR/BOR = 0 All Other Resets = u Value Description 1 A carry-out from the Most Significant bit of the result occurred 0 No carry-out from the Most Significant bit of the result occurred Note: 1. For Borrow, the polarity is reversed. A subtraction is executed by adding the two's complement of the second operand. 2. For Rotate (RRCF, RLCF) instructions, this bit is loaded with either the high or low-order bit of the Source register. (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 142 PIC18F26/45/46Q10 Memory Organization 10.8.6 WREG Name: Address: WREG 0xFE8 Shadow of Working Data Register Bit 7 6 5 4 3 2 1 0 WREG[7:0] Access Reset R/W R/W R/W R/W R/W R/W R/W R/W x x x x x x x x Bits 7:0 - WREG[7:0] (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 143 PIC18F26/45/46Q10 Memory Organization 10.8.7 INDF Name: Address: INDFx 0xFEF,0xFE7,0xFDF Indirect Data Register. This is a virtual register. The GPR/SFR register addressed by the FSRx register is the target for all operations involving the INDFx register. Bit 7 6 5 4 3 2 1 0 R/W R/W R/W R/W 0 0 0 R/W R/W R/W R/W 0 0 0 0 0 INDF[7:0] Access Reset Bits 7:0 - INDF[7:0] Indirect data pointed to by the FSRx register (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 144 PIC18F26/45/46Q10 Memory Organization 10.8.8 POSTDEC Name: Address: POSTDECx 0xFED,0xFE5,0xFDD Indirect Data Register with post decrement. This is a virtual register. The GPR/SFR register addressed by the FSRx register is the target for all operations involving the POSTDECx register. FSRx is decrememted after the read or write operation. Bit 7 6 5 4 3 2 1 0 POSTDEC[7:0] Access Reset R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Bits 7:0 - POSTDEC[7:0] (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 145 PIC18F26/45/46Q10 Memory Organization 10.8.9 POSTINC Name: Address: POSTINCx 0xFEE,0xFE6,0xFDE Indirect Data Register with post increment. This is a virtual register. The GPR/SFR register addressed by the FSRx register is the target for all operations involving the POSTINCx register. FSRx is incremented after the read or write operation. Bit 7 6 5 4 3 2 1 0 POSTINC[7:0] Access Reset R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Bits 7:0 - POSTINC[7:0] (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 146 PIC18F26/45/46Q10 Memory Organization 10.8.10 PREINC Name: Address: PREINCx 0xFEC,0xFE4,0xFDC Indirect Data Register with pre-increment. This is a virtual register. The GPR/SFR register addressed by the FSRx register plus 1 is the target for all operations involving the PREINCx register. FSRx is incremented before the read or write operation. Bit 7 6 5 4 3 2 1 0 PREINC[7:0] Access Reset R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Bits 7:0 - PREINC[7:0] (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 147 PIC18F26/45/46Q10 Memory Organization 10.8.11 PLUSW Name: Address: PLUSWx 0xFEB,0xFE3,0xFDB Indirect Data Register with WREG offset. This is a virtual register. The GPR/SFR register addressed by the sum of the FSRx register plus the signed value of the W register is the target for all operations involving the PLUSWx register. Bit 7 6 5 4 3 2 1 0 PLUSW[7:0] Access Reset R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Bits 7:0 - PLUSW[7:0] (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 148 PIC18F26/45/46Q10 Memory Organization 10.8.12 FSR Name: Address: FSRx 0xFE9,0xFE1,0xFD9 Indirect Address Register. The FSR value is the address of the data to which the INDF register points. Bit 15 14 13 12 11 10 9 8 FSRH[3:0] Access Reset Bit R/W R/W R/W R/W 0 0 0 0 3 2 1 0 7 6 5 4 R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 FSRL[7:0] Access Reset Bits 11:8 - FSRH[3:0] Most Significant address of INDF data Bits 7:0 - FSRL[7:0] Least Significant address of INDF data (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 149 PIC18F26/45/46Q10 Memory Organization 10.8.13 BSR Name: Address: BSR 0xFE0 Bank Select Register The BSR indicates the data memory bank which is bits 11:8 of the GPR address. Bit 7 6 5 4 3 2 1 0 R/W R/W 0 R/W R/W 0 0 0 BSR[3:0] Access Reset Bits 3:0 - BSR[3:0] Four Most Significant bits of the data memory address (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 150 PIC18F26/45/46Q10 (NVM) Nonvolatile Memory Control 11. (NVM) Nonvolatile Memory Control Nonvolatile memory is separated into three categories: Program Flash Memory (PFM) including User IDs, Configuration Words, and Data Flash Memory (DFM). DFM is also referred to as EEPROM because it is written one byte at a time and the erase before write is automatic. Although User IDs are above the PFM section they are included in the PFM category because the read and write access is identical for both. The write and erase times are controlled by an on-chip timer. The write and erase voltages are generated by an on-chip charge pump rated to function over the operating voltage range of the device. PFM and DFM can be protected in two ways: code protection and write protection. Code protection (Configuration bits CP for PFM and CPD for DFM) disables read and write access through an external device programmer. Code protection does not affect the self-write and erase functionality whereas write protection does. Code protection write protection can only be reset by a Bulk Erase performed by an external device programmer. A PFM Bulk Erase clears the program space, Configuration bits, and User IDs. A Bulk Erase only clears DFM if the CPD = 0. When CPD = 1 then bulk erasing DFM requires setting the Program Counter to the DFM area before the Bulk Erase command is issued, and then only the DFM area is cleared. See the programming specification for more details. Write protection prevents writes to NVM areas tagged for protection by the WRTn Configuration bits. Attempts to write a protected location will set the NVMERR bit. PFM and Configuration Words can be accessed by either the Table Pointer or NVM controls. DFM can be accessed only by the NVM controls. The PFM access is by single byte, single word, or full sector. A sector is 256 bytes (128 PFM words). The sector memory occupies one full bank of RAM space located in the RAM bank following the last occupied GPR bank. Sector memory is also referred to elsewhere in this document as the write block holding registers. The Table Pointer accesses memory by bytes. The NVM control accesses the DFM section by bytes and the other sections by words and sectors. The NVM controls include five independent access functions with five corresponding control bits. The controls are as follows: * * * * * RD - Single byte/word read WR - single byte/word write SECRD - Sector read SECWR - Sector write SECER - Sector erase The NVMADR registers determine the address of the memory region being accessed by the NVM control. The TBLPTR registers determine the address of the memory being accessed by the Table Pointer functions. The following table indicates which controls operate in each region. Table 11-1. NVM Organization Table Region Address Range Table Pointer TBLRD RD WR SECRD SECWR SECER PFM 00 0000h 01 FFFFh User IDs 20 0000h 20 00FFh (c) 2019 Microchip Technology Inc. NVMCON1 Datasheet Preliminary DS40001996C-page 151 PIC18F26/45/46Q10 (NVM) Nonvolatile Memory Control ...........continued 11.1 Region Address Range Table Pointer TBLRD NVMCON1 RD CONFIG 30 0000h 30 000Bh DFM 31 0000h 31 00FFh WR SECRD SECWR SECER Program Flash Memory The Program Flash Memory is readable, writable, and erasable during normal operation over the entire VDD range. A read from program memory is executed one byte at a time. A program memory erase is executed on blocks of n bytes at a time, also referred to as sectors. Refer to the following table for write and erase block sizes. A Bulk Erase operation cannot be issued from user code. A write to program memory can be executed by sectors or single words. Table 11-2. Flash Memory Organization by Device Device Sector Erase Size (Words) Holding Registers (Bytes) TBLPTR LSbs (Holding Address) 128 256 8 PIC18F26Q10 PIC18F46Q10 PIC18F45Q10 Program Flash Memory (Words) Data Flash Memory (Bytes) 32768 1024 16384 256 Writing or erasing program memory will cease instruction fetches until the operation is complete. The program memory cannot be accessed during the write or erase, therefore, code cannot execute. An internal programming timer terminates program memory writes and erases. A value written to program memory does not need to be a valid instruction. Executing a program memory location that forms an invalid instruction results in a NOP. It is important to understand the PFM memory structure for erase and programming operations. Program memory word size is 16 bits wide. PFM is arranged in sectors. A sector is the minimum size that can be erased by user software. After a sector has been erased, all or a portion of this sector can be programmed. Data can be written directly into PFM one 16-bit word at a time using the NVMADR and NVMCON1 controls or as a full sector from sector RAM, which is also referred to as the holding registers. These 8-bit registers are located in the RAM bank following the last GPR RAM bank. The holding registers are directly accessible as any other SFR/GPR register and also may be loaded via sequential writes using the TABLAT and 11.5.7 TBLPTR registers. (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 152 PIC18F26/45/46Q10 (NVM) Nonvolatile Memory Control Important: To modify only a portion of a previously programmed sector the contents of the entire sector must be read and saved in RAM prior to the sector erase. The SECRD operation is the easiest way to do this. Then, the new data can be written into the holding registers to reprogram the sector of PFM. However, any unprogrammed locations can be written using the single word write operation without first erasing the sector. 11.1.1 Table Pointer Operations In order to read and write program memory, there are two operations that allow the processor to move bytes between the program memory space and the data RAM: * Table Read (TBLRD*) * Table Write (TBLWT*) The SFR registers associated with these operations include: * TABLAT register * TBLPTR registers The program memory space is 16 bits wide, while the data RAM space is eight bits wide. The TBLPTR registers determine the address of one byte of the NVM memory. Table reads move one byte of data from NVM space to the TABLAT register and table writes move the TABLAT data to a holding register ready for a subsequent write to NVM space with the NVM controls. 11.1.1.1 Table Pointer Register The Table Pointer (TBLPTR) register addresses a byte within the program memory. The TBLPTR comprises three SFR registers: Table Pointer Upper Byte, Table Pointer High Byte and Table Pointer Low Byte (TBLPTRU:TBLPTRH:TBLPTRL). These three registers join to form a 22-bit wide pointer (bits 0 through 21). The bits 0 through 20 allow the device to address up to 2 Mbytes of program memory space. Bit 21 allows access to the Device ID, the User ID and the Configuration bits. The Table Pointer register, TBLPTR, is used by the TBLRD and TBLWT instructions. These instructions can increment and decrement the TBLPTR depending on specific appended characters as shown in the following table. The increment and decrement operations on the TBLPTR affect only bits 0 through 20. Table 11-3. Table Pointer Operations with TBLRD and TBLWT Instructions Example Operation on Table Pointer TBLRD* TBLWT* TBLPTR is not modified TBLRD*+ TBLWT*+ TBLPTR is incremented after the read/write TBLRD*TBLWT*- TBLPTR is decremented after the read/write TBLRD+* TBLWT+* TBLPTR is incremented before the read/write (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 153 PIC18F26/45/46Q10 (NVM) Nonvolatile Memory Control 11.1.1.2 Table Latch Register The Table Latch (TABLAT) is an 8-bit register mapped into the SFR space. The Table Latch register receives one byte of NVM data resulting from a TBLRD* instruction and is the source of the 8-bit data sent to the holding register space as a result of a TBLWT* instruction. 11.1.1.3 Table Read Operations The table read operation retrieves one byte of data directly from program memory pointed to by the TBLPTR registers and places it into the TABLAT register. Figure 11-1 shows the operation of a table read. Figure 11-1. Table Read Operation Rev. 30-000002A Instruction: TBLRD* Program Memory Table Pointer(1) TBLPTRH TBLPTRU 3/22/2017 Table Latch (8-bit) TBLPTRL TABLAT Program Memory (TBLPTR) Note 1: Table Pointer register points to a byte in program memory. 11.1.1.4 Table Write Operations The table write operation stores one byte of data from the TABLAT register into a sector RAM holding register. The following figure shows the operation of a table write from the TABLAT register to the holding register space. The procedure to write the contents of the holding registers into program memory is detailed in the "Writing to Program Flash Memory" section. Figure 11-2. Table Write Operation Rev. 30-000003B6/23/2017 Instruction: TBLWT* Program Memory Table TBLPTRU Pointer(1) TBLPTRH Sector RAM Table Latch (8-bit) TBLPTRL TABLAT Program Memory (TBLPTR<MSbs>) Note 1: During table writes the Table Pointer points to two areas. The LSbs of TBLPRTL point to an address within the sector RAM space. The MSbs of the Table Pointer determine where the sector will eventually be written. (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 154 PIC18F26/45/46Q10 (NVM) Nonvolatile Memory Control Table operations work with byte entities. Tables containing data, rather than program instructions, are not required to be word-aligned. Therefore, a table can start and end at any byte address. If a table write is being used to write executable code into program memory, program instructions will need to be wordaligned. Related Links 11.1.4 Writing to Program Flash Memory 11.1.1.5 Table Pointer Boundaries TBLPTR is used in reads, writes and erases of the Program Flash Memory. When a TBLRD is executed, all 22 bits of the TBLPTR determine which byte is read from program memory directly into the TABLAT register. When a TBLWT is executed the byte in the TABLAT register is written, not to Flash memory, but to a holding register in preparation for a program memory write. The holding registers constitute a write block, which may vary depending on the device (see the "Flash Memory Organization by Device" table in the "Program Flash Memory" section). The LSbs of the TBLPTRL register determine which specific address within the holding register block is written to. The size of the write block determines the number of LSbs. The MSbs of the Table Pointer have no effect during TBLWT operations. When a PFM sector write is executed the entire holding register block is written to the Flash memory sector at the address determined by the MSbs of the NVMADR. The LSbs are ignored during sector writes. For more detail, see the 11.1.4 Writing to Program Flash Memory section. The following figure illustrates the relevant boundaries of TBLPTR and NVMADR based on NVM control operations. Figure 11-3. Table Pointer Boundaries Based on Operation Rev. 30-000004B 5/11/2017 21 TBLPTRU 16 NVMADRU 15 TBLPTRH 8 7 NVMADRH SECTOR ERASE/WRITE NVMADR<21:n+1>(1) TBLPTRL 0 TBLPTRL TABLE WRITE TBLPTR<n:0>(1) TABLE READ - TBLPTR<21:0> Note: 1. See the "Flash Memory Organization by Device" table in the "Program Flash Memory" section for the write holding registers block size. Related Links 11.1 Program Flash Memory (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 155 PIC18F26/45/46Q10 (NVM) Nonvolatile Memory Control 11.1.1.6 Reading the Program Flash Memory The TBLRD instruction retrieves data from program memory at the TBLPTR location and places it into the TABLAT SFR register. Table reads from program memory are performed one byte at a time. In addition, TBLPTR can be modified automatically for the next table read operation. The CPU operation is suspended during the read, and it resumes immediately after. From the user point of view, TABLAT is valid in the next instruction cycle. The internal program memory is typically organized by words. The Least Significant bit of the address selects between the high and low bytes of the word. Figure 11-4 shows the interface between the internal program memory and the TABLAT. Figure 11-4. Reads from Program Flash Memory Rev. 30-000006A 3/22/2017 Program Memory (Even Byte Address) (Odd Byte Address) TBLPTR = xxxxx1 Instruction Register (IR) (c) 2019 Microchip Technology Inc. FETCH TBLRD Datasheet Preliminary TBLPTR = xxxxx0 TABLAT Read Register DS40001996C-page 156 Filename: Title: Last Edit: First Used: Note: 10-000046B.vsd FLASH PROGRAM MEMORY READ FLOWCHART 8/10/2016 PIC16F1508/9 PIC18F26/45/46Q10 (NVM) Nonvolatile Memory Control Figure 11-5. Program Flash Memory Read Flowchart Rev. 10-000 046B 8/10/201 6 Start Read Operation Select Word Address (TBLPTR registers) Initiate Read operation (TBLRD) Data read now in TABLAT register End Read Operation Example 11-1. Reading a Program Flash Memory Word MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF READ_WORD: TBLRD*+ MOVF MOVWF TBLRD*+ MOVFW MOVF 11.1.2 CODE_ADDR_UPPER TBLPTRU CODE_ADDR_HIGH TBLPTRH CODE_ADDR_LOW TBLPTRL TABLAT, W WORD_EVEN TABLAT, W WORD_ODD ; Load TBLPTR with the base ; address of the word ; read into TABLAT and increment ; get data ; read into TABLAT and increment ; get data NVM Unlock Sequence The unlock sequence is a mechanism that protects the NVM from unintended self-write programming, sector reads, and erasing. The sequence must be executed and completed without interruption to successfully complete any of the following operations: * * * * * * PFM sector erase PFM sector write from holding registers PFM sector read into write block holding registers PFM word write directly to NVM DFM byte write directly to NVM Write to Configuration Words Each of these operations correspond to one of four unlock code sequences as shown in the following table: (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 157 PIC18F26/45/46Q10 (NVM) Nonvolatile Memory Control Table 11-4. NVM Unlock Codes First Unlock Byte Second Unlock Byte NVMCON1 Operation Bit Word/Byte write 55h AAh WR Sector write DDh 22h SECWR Sector erase CCh 33h SECER Sector read BBh 44h SECRD Operation The general unlock sequence consists of the following steps and must be completed in order: * Write first unlock byte to NVMCON2 * Write second unlock byte to NMVCON2 * Set the operation control bit of NVMCON1 For PFM and Configuration Word operations, once the control bit is set the processor will stall internal operations until the operation is complete and then resume with the next instruction. DFM operations do not stall the CPU. Since the unlock sequence must not be interrupted, global interrupts should be disabled prior to the unlock sequence and re-enabled after the unlock sequence is completed. Figure 11-6. NVM Unlock Sequence Flowchart Rev. 30-000005B 4/27/2017 Start Unlock Sequence Write first unlock byte to NVMCON2 Write second unlock byte to NVMCON2 Set NVMCON1 control bit to Initiate write or erase operation End Unlock Operation Example 11-2. NVM Unlock Sequence for PFM word write BCF MOVF MOVWF INTCON,GIE UpperAddr,W NVMADRU (c) 2019 Microchip Technology Inc. ; Recommended so sequence is not interrupted ; set the target address Datasheet Preliminary DS40001996C-page 158 PIC18F26/45/46Q10 (NVM) Nonvolatile Memory Control MOVF HighAddr,W MOVWF NVMADRH MOVF LowAddr,W MOVWF NVMADRL MOVF HighByte,W ; high byte of word to be written MOVWF NVMDATH ; store in high byte transfer register MOVF LowByte,W ; low byte of word to be written MOVWF NVMDATL ; store in low byte transfer register BSF NVMCON0,NVMEN ; Enable NVM operation MOVLW 55h ; Load first unlock byte ; ------------------- Required Sequence -----------------------------MOVWF NVMCON2 ; Step 1: Load first byte into NVMCON2 MOVLW AAh ; Step 2: Load W with second unlock byte MOVWF NVMCON2 ; Step 3: Load second byte into NVMCON2 BSF NVMCON1,WR ; Step 4: Set WR bit to begin write ; -------------------------------------------------------------------BSF INTCON,GIE ; Re-enable interrupts Important: 1. Sequence begins when NVMCON2 is written; steps 1-4 must occur in the cycle-accurate order shown. If the timing of the steps 1 to 4 is corrupted by an interrupt or a debugger halt, the action will not take place. 2. Opcodes shown are illustrative; any instruction that has the indicated effect may be used. 11.1.3 Erasing Program Flash Memory (PFM) The minimum erase block is always one sector. Only through the use of an external programmer, or through ICSPTM control, can larger blocks of program memory be Bulk Erased. Word erase in the Flash array is not supported. For example, when initiating an erase sequence from a microcontroller with sector erase size of 128 words, a block of 128 words (256 bytes) of program memory is erased. The NVMADR<21:8> bits point to the block being erased. The NVMADR<7:0> bits are ignored. The NVMCON0 and NVMCON1 registers command the erase operation. The NVMEN bit must be set to enable write operations. The SECER bit is set to initiate the erase operation. The NVM unlock sequence described in the 11.1.2 NVM Unlock Sequence section must be used, which guards against accidental writes. This is sometimes referred to as a long write. A long write is necessary for erasing the internal Flash. Instruction execution is halted during the long write cycle. The long write is terminated by the internal programming timer. 11.1.3.1 PFM Erase Sequence The sequence of events for erasing a block of internal program memory is: 1. 2. 3. 4. Set NVMADR to an address within the intended sector. Set the NVMEN bit to enable NVM Perform the unlock sequence as described the 11.1.2 NVM Unlock Sequence section Set the SECER bit If the PFM address is write-protected, the SECER bit will be cleared and the erase operation will not take place, NVMERR is signaled in this scenario. The operation erases the sector indicated by masking the LSbs of the current NVMADR. (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 159 PIC18F26/45/46Q10 (NVM) Nonvolatile Memory Control While erasing PFM, CPU operation is suspended and it resumes when the operation is complete. Upon completion the SECER bit is cleared in hardware, the NVMIF is set and an interrupt will occur if the NVMIE bit is also set. The holding register data are not affected by erase operations and NVMEN will remain unchanged. Figure 11-7. PFM Sector Erase Flowchart Rev/ 30-000007B 5/1/2017 Start Erase Operation Load NVMADR registers with address of the block being erased Disable Interrupts (GIE = 1) Enable Write/Erase Operation (NVMEN =1) Sector Erase Unlock Sequence Select Erase Operation (SECER = 1) CPU stalls while Erase operation completes (10 ms typical) Enable Interrupts (GIE = 1) Disable Write/Erase Operation (NVMEN = 0) End Erase Operation Example 11-3. Erasing a Program Flash Memory block ; This sample sector erase routine assumes that the target address ; specified by CODE_ADDR_UPPER and CODE_ADDR_HIGH contain a value within ; the PFM address range of the device. MOVLW MOVWF MOVLW MOVWF ERASE_BLOCK: BSF BCF Required MOVLW (c) 2019 Microchip Technology Inc. CODE_ADDR_UPPER NVMADRU CODE_ADDR_HIGH NVMADRH ; load NVMADR with the base ; address of the memory block NVMCON0, NVMEN INTCON, GIE CCh ; enable Program Flash Memory ; disable interrupts ; first unlock byte for erase Datasheet Preliminary DS40001996C-page 160 PIC18F26/45/46Q10 (NVM) Nonvolatile Memory Control Sequence MOVWF MOVLW MOVWF BSF BSF BCF NVMCON2 33h NVMCON2 NVMCON1, SECER INTCON, GIE NVMCON0, NVMEN ; ; ; ; ; ; write CCh second unlock byte for erase write 33h start erase (CPU stalls) re-enable interrupts disable writes to memory Important: 1. If a write or erase operation is terminated by an unexpected event, NVMERR bit will be set which the user can check to decide whether a rewrite of the location(s) is needed. 2. NVMERR is set if SECER is written to `1' while NVMADR points to a write-protected address. 3. NVMERR is set if SECER is written to `1' while NVMADR points to an invalid address location ( Refer to the device memory map and NVM Organization Table). Related Links 11. (NVM) Nonvolatile Memory Control 11.1.4 Writing to Program Flash Memory Program memory can be written either one word at a time or a sector at a time. A single word is written by setting the NVMADR to the target address and loading NVMDAT with the desired word. The word is then transferred to Flash memory with the WR unlock and write sequence. A sector is written by first loading a block of holding registers and then executing a sector write sequence. The programming write block size is specified as the holding registers, also referred to as sector RAM, in the Flash memory organization by device table. Table writes are used to write the holding register bytes that are then transferred to Flash memory with the SECWR unlock and write sequence. There are only as many holding registers as there are bytes in a write block. Since the table latch (11.5.6 TABLAT) is only a single byte, the TBLWT instruction needs to be executed multiple times for each sector programming operation. The write protection state is ignored for table writes. All of the table write operations will essentially be short writes because only the holding registers are written. NVMIF is not affected while writing to the holding registers. After all the holding registers have been written, the programming operation of that sector of memory is started by setting NVMADR to an address within the target sector and executing a sector write unlock sequence followed immediately by setting the SECWR bit. If the PFM address in the NVMADR is write-protected, or if NVMADR points to an invalid location, the SECWR bit is cleared without any effect and the NVMERR is set. CPU operation is suspended during a long write cycle and resumes when the operation is complete. The long write operation completes in one extended instruction cycle. When complete, the SECWR or WR bit is cleared by hardware and NVMIF is set. An interrupt will occur if NVMIE is also set. The holding registers are unchanged. NVMEN is not changed. The internal programming timer controls the write time. The write/erase voltages are generated by an onchip charge pump, rated to operate over the voltage range of the device. (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 161 PIC18F26/45/46Q10 (NVM) Nonvolatile Memory Control Important: The holding registers are undefined on device Resets and unchanged after write operations. Individual bytes of program memory may be modified, provided that the modification does not attempt to change any bit from a `0' to a `1'. When modifying individual bytes with a sector write operation, it is necessary to load all holding registers with either FFh or the existing contents of memory before executing a long write operation. The fastest way to do this is by performing a sector read operation. Figure 11-8. Table Writes to Program Flash Memory Rev. 30-000008A 3/22/2017 TABLAT Write Register 8 8 TBLPTR = xxxx00 TBLPTR = xxxx01 Holding Register 8 TBLPTR = xxxx02 Holding Register Holding Register 8 TBLPTR = xxxxYY(1) Holding Register Program Memory Note: Refer to Flash memory organization by device table for number of holding registers (e.g. YY = FFh for 256 holding registers). Related Links 11.1 Program Flash Memory 11.1.4.1 PFM Sector Write Sequence The sequence of events for programming a block of internal program memory location should be: 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. Set NVMADR with the target sector address. Read the PFM sector into RAM with the SECRD operation. Execute the sector erase procedure (see 11.1.3.1 PFM Erase Sequence). SECER is set as the last step in the erase sequence. The CPU will stall for the duration of the erase (about 10 ms using internal timer). Load TBLPTR with address of first byte being updated. Write the n-byte block into the holding registers with auto-increment. Refer to the Flash memory organization by device table for the number of holding registers. Disable interrupts. Execute the sector write unlock sequence (see 11.1.2 NVM Unlock Sequence). SECWR bit is set as last step in the unlock sequence. The CPU will stall for the duration of the write (about 10 ms using internal timer). Re-enable interrupts. Verify the memory (table read). This procedure will require about 20 ms to update each block of memory. See the "Memory Programming Specifications" for more detail. An example of the required code is given below. (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 162 PIC18F26/45/46Q10 (NVM) Nonvolatile Memory Control Important: Before setting the SECWR bit, the NVMADR value needs to be within the intended address range of the target PFM sector. Figure 11-9. Program Flash Memory (PFM) Write Flowchart Rev. 10-000 049D 12/15/201 7 Start Write O peration Determine number of byte s to be writte n in to PFM. The number of byte s cannot exceed the numbe r of bytes per sector (byte_cnt) Loa d TAB LAT with the value to write Disa ble In terr upts (GIE = 0) Update the byte cou nte r (byte_cnt--) Per form SECWR ope ration Write b yte to sector RAM with TBLWT*+ CPU stalls while Write ope rati on comple tes (10 ms typi cal) Set NV MA DR to add ress with in targ et sector Per form SECRD ope ration No delay whe n writing to PFM La tches Disa ble NV M (NVMEN = 0) Era se target P FM se ctor with SE CE R ope ratio n CPU stalls while Era se ope rati on comple tes (10 ms typi cal) Last byte written? Yes Re-ena ble Interru pts (GIE = 1) No End Write O peration Set TB LPTR to P FM add ress of first byte Example 11-4. Writing a Sector of Program Flash Memory ; Code sequence to modify one word in a programmed sector of PFM ; Calling routine should check WREG for the following errors: ; ; 00h = Successful modification ; 01h = Read error ; 02h = Erase error ; 03h = Write error ; READ_BLOCK: MOVLW CODE_ADDR_UPPER ; load NVMADR with the base MOVWF NVMADRU ; address of the memory sector MOVLW CODE_ADDR_HIGH (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 163 PIC18F26/45/46Q10 (NVM) Nonvolatile Memory Control MOVWF NVMADRH MOVLW CODE_ADDR_LOW MOVWF NVMADRL BCF INTCON, GIE BSF NVMCON0, NVMEN ; ----- Required Sequence ----MOVLW 0BBh MOVWF NVMCON2 MOVLW 44h MOVWF NVMCON2 BSF NVMCON1, SECRD ; -----------------------------BTFSC NVMCON0, NVMERR BRA NVM_RDERR ERASE_BLOCK: block ; ----- Required Sequence ----MOVLW 0CCh MOVWF NVMCON2 MOVLW 33h MOVWF NVMCON2 BSF NVMCON1, SECER ; -----------------------------BTFSC NVMCON0, NVMERR BRA NVM_ERERR MODIFY_WORD: MOVLW TARGET_ADDR_UPPER MOVWF TBLPTRU MOVLW TARGET_ADDR_HIGH MOVWF TBLPTRH MOVLW TARGET_ADDR_LOW MOVWF TBLPTRL MOVLW NEW_DATA_LOW MOVWF TABLAT TBLWT*+ MOVLW NEW_DATA_HIGH MOVWF TABLAT TBLWT*+ PROGRAM_MEMORY: block ; ----- Required Sequence ----MOVLW 0DDh MOVWF NVMCON2 MOVLW 22h MOVWF NVMCON2 BSF NVMCON1, SECWR ; -----------------------------BTFSC NVMCON0, NVMERR BRA NVM_WRERR CLRF WREG,F BRA NVM_EXIT NVM_RDERR: MOVLW 01h BRA NVM_EXIT NVM_ERERR: MOVLW 02h BRA NVM_EXIT NVM_WRERR: MOVLW 03h NVM_EXIT: BCF NVMCON0, NVMEN BSF INTCON, GIE RETURN ; disable interrupts ; enable NVM ; first unlock byte = 0BBh ; second unlock byte = 44h ; start sector read (CPU stall) ; Verify no error occurred during read ; return read error code ; NVMADR is already pointing to target ; first unlock byte = 0CCh ; second unlock byte = 33h ; start sector erase (CPU stall) ; Verify no error occurred during erase ; return erase error code ; load TBLPTR with the target address ; of the LSByte ; update holding register ; NVMADR is already pointing to target ; first unlock byte = 0DDh ; second unlock byte = 22h ; start sector programming (CPU stall) ; Verify no error occurred during write ; return sector write error code ; return with no error ; disable NVM ; re-enable interrupts Related Links 39.3.5 Memory Programming Specifications 11.1.4.2 PFM Word Write Sequence The sequence of events for programming an erased single word of internal program memory location should be: 1. Set NVMADR with the target word address. (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 164 PIC18F26/45/46Q10 (NVM) Nonvolatile Memory Control 2. 3. 4. 5. 6. 7. 8. Load NVMDAT with desired word. Disable interrupts. Execute the word/byte write unlock sequence (see 11.1.2 NVM Unlock Sequence). WR bit is set as last step in the unlock sequence. The CPU will stall for the duration of the write (about 50 s using internal timer). Re-enable interrupts. Verify the memory (word read). Example 11-5. Writing a Word of Program Flash Memory ; Code sequence to program one erased word of PFM ; Target address is in WORD_ADDR_UPPER:WORD_ADDR_HIGH:WORD_ADDR_LOW ; Target data is in WORD_HIGH_BYTE:WORD_LOW_BYTE ; Calling routine should check WREG for the following errors: ; ; 00h = Successful modification ; 03h = Write error ; WORD_WRITE: MOVF WORD_ADDR_UPPER, W ; load NVMADR with the target MOVWF NVMADRU ; address of the word MOVF WORD_ADDR_HIGH, W MOVWF NVMADRH MOVF WORD_ADDR_LOW, W MOVWF NVMADRL MOVF WORD_HIGH_BYTE, W ; load NVMDAT with desired MOVWF NVMDATH ; word MOVF WORD_LOW_BYTE, W MOVWF NVMDATL BCF INTCON, GIE ; disable interrupts BSF NVMCON0, NVMEN ; enable NVM PROGRAM_WORD: ; ----- Required Sequence ----MOVLW 055h MOVWF NVMCON2 ; first unlock byte = 055h MOVLW 0AAh MOVWF NVMCON2 ; second unlock byte = 0AAh BSF NVMCON1, WR ; start word programming (CPU stall) ; -----------------------------BTFSC NVMCON0, NVMERR ; Verify no error occurred during write BRA NVM_WRERR ; return sector write error code VERIFY_WORD: BSF NVMCON0, RD ; Retrieve word from PFM MOVF WORD_HIGH_BYTE, W ; Verify high byte CPFSEQ NVMDATH BRA NVM_RDERR ; not equal - return error code MOVF WORD_LOW_BYTE, W ; Verify low byte CPFSEQ NVMDATL BRA NVM_RDERR ; not equal - return error code CLRF WREG,F BRA NVM_EXIT NVM_RDERR: MOVLW 01h BRA NVM_EXIT NVM_WRERR: MOVLW 03h NVM_EXIT: BCF NVMCON0, NVMEN BSF INTCON, GIE RETURN ; return with no error ; disable NVM ; re-enable interrupts 11.1.4.3 Write Verify Depending on the application, good programming practice may dictate that the value written to the memory should be verified against the original value. This should be used in applications where excessive writes can stress bits near the specification limit. Since program memory is stored as a full (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 165 PIC18F26/45/46Q10 Filename: Title: Last Edit: First Used: memory Note: contents page, the stored program after the last write is complete. 10-000051B.vsd FLASH PROGRAM MEMORY VERIFY FLOWCHART 12/4/2015 PIC18(L)F2x/4xK40 are compared intended data stored in sector 1: Refer to Figurewith 11-5,the Program Flash Memory Read Flowchart (NVM) Nonvolatile Memory Control RAM Figure 11-10. Program Flash Memory Verify Flowchart Rev. 10-000051B 12/4/2015 Start Verify Operation This routine assumes that the last row of data written was from an image saved on RAM. This image will be used to verify the data currently stored in PFM Read Operation(1) NVMDAT = RAM image ? Yes No No Fail Verify Operation Last word ? Yes End Verify Operation 11.1.4.4 Unexpected Termination of Write Operation If a write is terminated by an unplanned event, such as loss of power or an unexpected Reset, the memory location just programmed should be verified and reprogrammed if needed. If the write operation is interrupted by a MCLR Reset or a WDT Time-out Reset during normal operation, the NVMERR bit will be set which the user can check to decide whether a rewrite of the location(s) is needed. 11.1.4.5 Protection Against Spurious Writes A write sequence is valid only when both the following conditions are met. This prevents spurious writes that might lead to data corruption. 1. 2. The WR, RD, SECWR, SECRD, and SECER bits are gated through the NVMEN bit. It is suggested to have the NVMEN bit cleared at all times except during memory writes and reads. This prevents memory operations if any of the control bits are set accidentally. The NVM unlock sequence must be performed each time before all but the RD operation. (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 166 PIC18F26/45/46Q10 (NVM) Nonvolatile Memory Control 11.2 User ID, Device ID and Configuration Word Access The NVMADR value determines which NVM address space is accessed. The User IDs and Configuration Words areas allow read and write whereas Device and Revision IDs allow read-only (see NVM organization table). Reading and writing User ID space is identical to writing to PFM space as described in the preceding paragraphs. Writing to the Configuration space can only be done with the SECWR operation. A sector erase operation on Configuration space cannot be performed with the SECER operation. When a SECWR operation is performed on the Configuration space a sector erase is performed automatically before the sector write. Any code protection settings that are not enabled will remain not enabled after the sector write operation unless the new values enable them. However, any code protection settings that are enabled cannot be disabled by a self-write of the Configuration space. The user can modify the Configuration space by the following steps: 1. Read Configuration space with the unlock and SECRD sequence. 2. Modify the desired Configuration Word holding registers using TBLPTR address, TABLAT data, and TBLWT* instruction. 3. Write the holding registers to Configuration space with the unlock and SECWR sequence. Related Links 11. (NVM) Nonvolatile Memory Control 11.3 Data Flash Memory (DFM) The data Flash memory is a nonvolatile memory array, also referred to as EEPROM. The DFM is separate from the Program Flash Memory, which is used for long-term storage of program data. The DFM is mapped above program memory space and is indirectly addressed through the NVM Special Function Registers (SFRs). The DFM is readable and writable during normal operation over the entire VDD range. Five SFRs are used to read and write to the data DFM. They are: * * * * * NVMCON0 NVMCON1 NVMCON2 NVMDAT NVMADR The DFM can only be read and written one byte at a time. When interfacing to the data memory block, NVMDATL holds the 8-bit data for read/write and the 11.5.5 NVMADR register holds the address of the DFM location being accessed. The DFM is rated for high erase/write cycle endurance. A byte write automatically erases the location and writes the new data (erase-before-write). The write time is controlled by an internal programming timer; it will vary with voltage and temperature as well as from chip-to-chip. Refer to the data EEPROM memory parameters in the electrical specifications section for the limits. Related Links 39.3.5 Memory Programming Specifications (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 167 PIC18F26/45/46Q10 (NVM) Nonvolatile Memory Control 11.3.1 Reading the DFM To read a DFM location, the user must write the address to the NVMADR register, enable NVM control by setting the NVMEN bit, and then set the RD control bit. The data is available on the very next instruction cycle; therefore, the NVMDAT register can be read by the next instruction. NVMDAT will hold this value until another read operation, or until it is written to by the user (during a write operation). The basic process is shown in the following flowchart. Figure 11-11. DFM Read Flowchart Rev. 30-000009B 5/10/2017 Start Read Operation Select Word Address (NVMADRU:NVMADRH:NVMADRL) Initiate Read Operation (RD = 1) Data read now in NVMDAT End Read Operation Example 11-6. DFM Read ; Data Flash Memory Address to read BSF NVMCON0, NVMEN MOVF DFM_ADDRL, W MOVWF NVMADRL MOVF DFM_ADDRH, W MOVWF NVMADRH MOVF DFM_ADDRU, W MOVWF NVMADRU BSF NVMCON1, RD MOVF NVMDAT, W BCF NVMCON0, NVMEN ; ; ; ; ; ; ; ; ; ; Enable NVM Setup Address low byte Setup Address high byte Setup Address upper byte Issue EE Read W = EE_DATA Disable NVM Only byte reads are supported for DFM. Reading a block of DFM with a SECRD operation is not supported. 11.3.2 Writing to DFM To write a DFM location, the address must first be written to the NVMADR register and the data written to the NVMDATL register. The sequence shown in 11.1.2 NVM Unlock Sequence must be followed to initiate the write cycle. Block writes, also referred to as sector writes, are not supported for the DFM. The write will not begin if NVM Unlock sequence is not exactly followed for each byte. It is strongly recommended that interrupts be disabled during this code segment. Additionally, the NVMEN bit must be set to enable NVM control. This mechanism prevents accidental writes to DFM due to unexpected code execution (i.e., runaway programs). The NVMEN bit should be kept clear at all times, except when updating the DFM. The NVMEN bit is not cleared by hardware. (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 168 PIC18F26/45/46Q10 (NVM) Nonvolatile Memory Control After a write sequence has been initiated, NVMCON1, NVMADR and NVMDAT cannot be modified. The WR bit will be inhibited from being set unless the NVMEN bit is set. After a write sequence has been initiated, clearing the NVMEN bit will not affect this write cycle. A single DFM byte is written and the operation includes an implicit erase cycle for that word. CPU execution continues in parallel and at the completion of the write cycle, the WR bit is cleared in hardware and the NVM Interrupt Flag bit (NVMIF) is set. The user can either enable this interrupt or poll this bit. NVMIF must be cleared by software. Example 11-7. DFM Write ; Data Flash Memory Address to write MOVF DFM_ADDRL, W ; MOVWF NVMADRL ; Setup Address MOVF DFM_ADDRH, W ; MOVWF NVMADRH ; Setup Address MOVF DFM_ADDRU, W ; MOVWF NVMADRU ; Setup Address ; Data Memory Value to write MOVF DMF_DATA, W ; MOVWF NVMDATL ; ; Enable writes BSF NVMCON0, NVMEN ; Enable NVM ; Disable interrupts BCF INTCON, GIE ; ; -------- Required Sequence --------MOVLW 55h ; MOVWF NVMCON2 ; MOVLW AAh ; MOVWF NVMCON2 ; BSF NVMCON1, WR ; Set WR bit to ; ------------------------------------; Wait for write to complete BTFSC NVMCON1, WR ; DFM writes do BRA $-2 ; Enable INT BSF INTCON, GIE ; ; Disable writes BCF NVMCON0, NVMEN ; 11.3.3 low byte high byte upper byte begin write not stall the CPU DFM Write Verify Depending on the application, good programming practice may dictate that the value written to the memory should be verified against the original value. This should be used in applications where excessive writes can stress bits near the specification limit. 11.3.4 Operation During Code-Protect and Write-Protect DFM has its own code-protect bits in the Configuration Words. In-Circuit Serial Programming read and write operations are disabled when code protection is enabled. However, internal reads operate normally. Internal writes operate normally provided that write protection is not enabled. If the DFM is write-protected or if NVMADR points at an invalid address location, the WR bit is cleared without any effect. NVMERR is signaled in this scenario. 11.3.5 Protection Against Spurious Write There are conditions when the user may not want to write to the DFM. To protect against spurious DFM writes, various mechanisms have been implemented. On any Reset, the NVMEN bit is cleared. In addition, writes to the DFM are blocked during the Power-up Timer period (TPWRT). The unlock sequence and the NVMEN bit together help prevent an accidental write during brown-out, power glitch or software malfunction. (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 169 PIC18F26/45/46Q10 (NVM) Nonvolatile Memory Control 11.3.6 Erasing the DFM DFM can be erased by writing 0xFF to all locations in the memory that need to be erased. Example 11-8. DFM Erase Routine Loop: CLRF CLRF MOVLW MOVWF SETF BCF BSF MOVLW MOVWF MOVLW MOVWF BSF BTFSC BRA INCFSZ BRA ; The following INCF MOVLW CPFSGT register BRA BCF BSF (c) 2019 Microchip Technology Inc. NVMADRL NVMADRH 31h NVMADRU NVMDAT INTCON, GIE NVMCON0, NVMEN ; ; ; ; ; ; ; ; ; ; ; ; ; ; Clear address low byte Clear address high byte EEPROM upper address Set address upper byte Load 0xFF to data register Disable interrupts Enable NVM Loop to refresh array Initiate unlock sequence ; ; ; ; Skip if greater than working register Else go back to erase loop Disable NVM Enable interrupts 0x55 NVMCON2 0xAA NVMCON2 NVMCON1, WR Set WR bit to begin write NVMCON1, WR Wait for write to complete $-2 NVMADRL, F ; Increment address low byte Loop ; Not zero, do it again 4 lines of code are not needed if EEPROM is 256 bytes or less NVMADRH, F ; Decrement address high byte 0x03 ; Move 0x03 to working register NVMADRH ; Compare address high byte with working Loop NVMCON0, NVMEN INTCON, GIE Datasheet Preliminary DS40001996C-page 170 PIC18F26/45/46Q10 (NVM) Nonvolatile Memory Control 11.4 Address 0x0F79 Register Summary: NVM Control Name NVMADR Bit Pos. 7:0 NVMADRL[7:0] 15:8 NVMADRH[7:0] 23:16 NVMADRU[5:0] 7:0 NVMDATL[7:0] 15:8 NVMDATH[7:0] 0x0F7C NVMDAT 0x0F7E Reserved 0x0F7F NVMCON0 7:0 0x0F80 NVMCON1 7:0 0x0F81 NVMCON2 7:0 NVMEN NVMERR SECER SECWR Reserved WR SECRD RD NVMCON2[7:0] 0x0F82 ... Reserved 0x0FF4 0x0FF5 0x0FF6 TABLAT TBLPTR 7:0 TABLAT[7:0] 7:0 TBLPTRL[7:0] 15:8 TBLPTRH[7:0] 23:16 11.5 TBLPTR21 TBLPTRU[4:0] Register Definitions: Nonvolatile Memory (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 171 PIC18F26/45/46Q10 (NVM) Nonvolatile Memory Control 11.5.1 NVMCON0 Name: Address: NVMCON0 0xF7F Nonvolatile Memory Control 0 Register Bit Access Reset 4 3 NVMEN 7 6 5 NVMERR Reserved R/W R/W/HS R/W 0 x 0 2 1 0 Bit 7 - NVMEN NVM Enable bit Value Description 1 NVM is enabled for all operations 0 NVM is disabled for all operations except single byte or word read. Bit 4 - NVMERR NVM Error Flag bit Value Description 1 An attempted NVM write or sector read did not complete successfully. Must be cleared by software. 0 All NVM operations have completed successfully. Bit 3 - Reserved Reserved - Do not use. This bit must be maintained as `0'. (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 172 PIC18F26/45/46Q10 (NVM) Nonvolatile Memory Control 11.5.2 NVMCON1 Name: Address: NVMCON1 0xF80 Nonvolatile Memory Control 1 Register Bit 7 Access Reset 6 5 4 1 0 SECER SECWR WR 3 2 SECRD RD R/S/HC R/S/HC R/S/HC R/S/HC R/S/HC 0 0 0 0 0 Bit 6 - SECER NVM Sector Erase Enable Control bit Value Condition Description 1 NVMADR points to PFM Immediately following the sector erase unlock sequence, perform a sector erase operation. Stays set until operation is complete. Cannot be cleared by software. 0 NVMADR points to PFM NVM sector erase operation is complete and inactive. Bit 5 - SECWR NVM Sector Write Enable Control bit Value Condition 1 NVMADR points to PFM or CONFIG 0 NVMADR points to PFM or CONFIG Bit 4 - WR NVM Write Control bit Value Condition 1 NVMADR points to DFM 1 NVMADR points to PFM 0 NVMADR points to PFM or DFM Description Immediately following the sector write unlock sequence, initiates the PFM sector write operation. Stays set until the write is complete. Cannot be cleared by software. NVM sector write operation is complete and inactive. Description Immediately following the DFM write unlock sequence, initiates a DFM byte erase/write sequence using data in the NVMDATL register. Stays set until the operation is complete. Cannot be cleared by software. Immediately following the PFM write unlock sequence, initiates an NVM word write sequence using data in the NVMDATH:L register pair. Stays set until the operation is complete. Cannot be cleared by software. NVM byte/word write operation is complete and inactive. Bit 1 - SECRD PFM Sector Read Enable Control bit Value Condition Description 1 NVMADR points to PFM or Immediately following the sector read unlock sequence, initiates CONFIG a read of one full sector from PFM into sector RAM. Stays set until the read is complete. Cannot be cleared by software. (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 173 PIC18F26/45/46Q10 (NVM) Nonvolatile Memory Control Value 0 Condition Description NVMADR points to PFM or PFM sector read operation is complete and inactive. CONFIG Bit 0 - RD NVM Read Enable Control bit Value Condition Description 1 NVMADR points to DFM Initiates a read of one byte from DFM into the NVMDATL register. Stays set until the read is complete. Cannot be cleared by software. 1 NVMADR points to PFM Initiates a read of one word from PFM into the NVMDATH:L registers. Stays set until the read is complete. Cannot be cleared by software. 0 NVMADR points to PFM NVM read operation is complete and inactive. or DFM (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 174 PIC18F26/45/46Q10 (NVM) Nonvolatile Memory Control 11.5.3 NVMCON2 Name: Address: NVMCON2 0xF81 Nonvolatile Memory Control 2 Register Note: This register always reads zeros, regardless of data written. Refer to the NVM Unlock Sequence section Bit 7 6 5 4 3 2 1 0 NVMCON2[7:0] Access Reset WO WO WO WO WO WO WO WO 0 0 0 0 0 0 0 0 Bits 7:0 - NVMCON2[7:0] (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 175 PIC18F26/45/46Q10 (NVM) Nonvolatile Memory Control 11.5.4 NVMDAT Name: Address: NVMDAT 0xF7C NVM Data Register Bit 15 14 13 12 11 10 9 8 NVMDATH[7:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 NVMDATL[7:0] Access Reset Bits 15:8 - NVMDATH[7:0] NVMDAT Most Significant Byte of data written to and read from PFM. Bits 7:0 - NVMDATL[7:0] NVMDAT Least Significant Byte of data written to and read from PFM or DFM. (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 176 PIC18F26/45/46Q10 (NVM) Nonvolatile Memory Control 11.5.5 NVMADR Name: Address: NVMADR 0xF79 NVM Address Register Bit 23 22 21 20 19 18 17 16 NVMADRU[5:0] Access Reset Bit R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 11 10 9 8 15 14 13 12 R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 NVMADRH[7:0] Access NVMADRL[7:0] Access Reset R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Bits 21:16 - NVMADRU[5:0] NVM address bits <21:16> . Bits 15:8 - NVMADRH[7:0] High byte of NVM address. Bits 7:0 - NVMADRL[7:0] Low byte of NVM address. (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 177 PIC18F26/45/46Q10 (NVM) Nonvolatile Memory Control 11.5.6 TABLAT Name: Address: TABLAT 0xFF5 Program, Configuration, Device ID, and User ID Memory Data Bit 7 6 5 4 3 2 1 0 TABLAT[7:0] Access Reset R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Bits 7:0 - TABLAT[7:0] The value of the NVM memory byte returned from the address contained in TBLPTR after a TBLRD command, or the data written to the latch by a TBLWT command. (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 178 PIC18F26/45/46Q10 (NVM) Nonvolatile Memory Control 11.5.7 TBLPTR Name: Address: TBLPTR 0xFF6 Program, Configuration, Device ID and User ID Memory Address Bit 23 22 21 20 19 TBLPTR21 Access Reset Bit 18 17 16 TBLPTRU[4:0] R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 11 10 9 8 15 14 13 12 R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 TBLPTRH[7:0] Access TBLPTRL[7:0] Access Reset R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Bit 21 - TBLPTR21 NVM Most Significant Address bit Value Description 1 Access Configuration, User ID, Device ID, and Revision ID spaces 0 Access Program Flash Memory space Bits 20:16 - TBLPTRU[4:0] NVM Upper Address bits Bits 15:8 - TBLPTRH[7:0] High Byte of NVM Address bits Bits 7:0 - TBLPTRL[7:0] Low Byte of NVM Address bits (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 179 PIC18F26/45/46Q10 8x8 Hardware Multiplier 12. 12.1 8x8 Hardware Multiplier Introduction All PIC18 devices include an 8x8 hardware multiplier as part of the ALU. The multiplier performs an unsigned operation and yields a 16-bit result that is stored in the product register pair, PRODH:PRODL. The multiplier's operation does not affect any flags in the STATUS register. Making multiplication a hardware operation allows it to be completed in a single instruction cycle. This has the advantages of higher computational throughput and reduced code size for multiplication algorithms and allows the PIC18 devices to be used in many applications previously reserved for digital signal processors. A comparison of various hardware and software multiply operations, along with the savings in memory and execution time, is shown in Table 12-1. 12.2 Operation Example 12-1 shows the instruction sequence for an 8x8 unsigned multiplication. Only one instruction is required when one of the arguments is already loaded in the WREG register. Example 12-2 shows the sequence to do an 8x8 signed multiplication. To account for the sign bits of the arguments, each argument's Most Significant bit (MSb) is tested and the appropriate subtractions are done. Example 12-1. 8x8 Unsigned Multiply Routine MOVF ARG1, W ; MULWF ARG2 ; ARG1 * ARG2 -> PRODH:PRODL Example 12-2. 8x8 Signed Multiply Routine MOVF MULWF BTFSC SUBWF MOVF BTFSC SUBWF ARG1, W ARG2 ARG2, SB PRODH, F ARG2, W ARG1, SB PRODH, F ; ARG1 * ARG2 -> PRODH:PRODL ; Test Sign Bit ; PRODH = PRODH - ARG1 ; Test Sign Bit ; PRODH = PRODH - ARG2 Table 12-1. Performance Comparison for Various Multiply Operations Routine 8x8 unsigned Multiply Method Program Time Cycles Memory (Max) @ 64 MHz @ 40 MHz @ 10 MHz @ 4 MHz (Words) Without hardware multiply 13 69 4.3 s 6.9 s 27.6 s 69 s Hardware multiply 1 1 62.5 ns 100 ns 400 ns 1 s (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 180 PIC18F26/45/46Q10 8x8 Hardware Multiplier ...........continued Routine Multiply Method Program Time Cycles Memory (Max) @ 64 MHz @ 40 MHz @ 10 MHz @ 4 MHz (Words) Without hardware multiply 33 91 5.7 s 9.1 s 36.4 s 91 s Hardware multiply 6 6 375 ns 600 ns 2.4 s 6 s Without hardware 16x16 unsigned multiply 21 242 15.1 s 24.2 s 96.8 s 242 s Hardware multiply 28 28 1.8 s 2.8 s 11.2 s 28 s Without hardware multiply 52 254 15.9 s 25.4 s 102.6 s 254 s Hardware multiply 35 40 2.5 s 4.0 s 16.0 s 40 s 8x8 signed 16x16 signed Example 12-3 shows the sequence to do a 16 x 16 unsigned multiplication. The equation below shows the algorithm that is used. The 32-bit result is stored in four registers (RES<3:0>). 16 x 16 Unsigned Multiplication Algorithm 3: 0 = 1: 1 * 2: 2 = 1 * 2 * 216 + 1 * 2 * 28 + 1 * 2 * 28 + 1 * 2 Example 12-3. 16 x 16 Unsigned Multiply Routine ; ; ; MOVF MULWF MOVFF MOVFF ARG1L, W ARG2L PRODH, RES1 PRODL, RES0 ; ARG1L * ARG2L PRODH:PRODL ; ; MOVF MULWF MOVFF MOVFF ARG1H, W ARG2H PRODH, RES3 PRODL, RES2 ; ; ARG1H * ARG2H PRODH:PRODL ; ; MOVF MULWF MOVF ADDWF MOVF ADDWFC CLRF ADDWFC ARG1L, W ARG2H PRODL, W RES1, F PRODH, W RES2, F WREG RES3, F ; ARG1L * ARG2H PRODH:PRODL ; ; Add cross products ; ; ; ; MOVF MULWF MOVF ADDWF MOVF ADDWFC CLRF ADDWFC ARG1H, W ARG2L PRODL, W RES1, F PRODH, W RES2, F WREG RES3, F ; ; ARG1H * ARG2L PRODH:PRODL ; ; Add cross products ; ; ; ; Example 12-4 shows the sequence to do a 16 x 16 signed multiply. The equation below shows the algorithm used. The 32-bit result is stored in four registers (RES<3:0>). To account for the sign bits of the arguments, the MSb for each argument pair is tested and the appropriate subtractions are done. (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 181 PIC18F26/45/46Q10 8x8 Hardware Multiplier 16 x 16 Signed Multiplication Algorithm 3: 0 = 1: 1 * 2: 2 = 1 * 2 * 216 + 1 * 2 * 28 + 1 * 2 * 28 + 1 * 2 + - 1 * 2 < 7 > * 1: 1 * 216 + - 1 * 1 < 7 > * 2: 2 * 216 Example 12-4. 16 x 16 Signed Multiply Routine ; ; ; ; ; MOVF MULW MOVF MOVFF ARG1L, W ARG2L PRODH, RES1 PRODL, RES0 ; ARG1L * ARG2L PRODH:PRODL ; ; MOVF MULWF MOVFF MOVFF ARG1H, W ARG2H PRODH, RES3 PRODL, RES2 ; ARG1H * ARG2H PRODH:PRODL ; ; MOVF MULWF MOVF ADDWF MOVF ADDWFC CLRF ADDWFC ARG1L, W ARG2H PRODL, W RES1, F PRODH, W RES2, F WREG RES3, F ; ARG1L * ARG2H PRODH:PRODL ; ; Add cross products ; ; ; ; MOVF MULWF MOVF ADDWF MOVF ADDWFC CLRF ADDWFC ARG1H, W ARG2L PRODL, W RES1, F PRODH, W RES2, F WREG RES3, F ; ; ARG1H * ARG2L PRODH:PRODL ; ; Add cross products ; ; ; ; BTFSS BRA MOVF SUBWF MOVF SUBWFB ARG2H, 7 SIGN_ARG1 ARG1L, W RES2 ARG1H, W RES3 ; ARG2H:ARG2L neg? ; no, check ARG1 ; ; ; ARG1H, 7 CONT_CODE ARG2L, W RES2 ARG2H, W RES3 ; ARG1H:ARG1L neg? ; no, done ; ; ; SIGN_ARG1: BTFSS BRA MOVF SUBWF MOVF SUBWFB ; CONT_CODE: : (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 182 PIC18F26/45/46Q10 8x8 Hardware Multiplier 12.3 Register Summary - 8x8 Hardware Multiplier Address Name 0x0FF3 PROD 12.4 Bit Pos. 7:0 PRODL[7:0] 15:8 PRODH[7:0] Register Definitions: 8x8 Hardware Multiplier (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 183 PIC18F26/45/46Q10 8x8 Hardware Multiplier 12.4.1 PROD Name: Address: PROD 0xFF3 Product Register Pair The PROD register stores the 16-bit result yielded by the unsigned operation performed by the 8x8 hardware multiplier. Bit 15 14 13 12 11 10 9 8 PRODH[7:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset x x x x x x x x Bit 7 6 5 4 3 2 1 0 R/W R/W R/W R/W R/W R/W R/W R/W x x x x x x x x PRODL[7:0] Access Reset Bits 15:8 - PRODH[7:0] PROD Most Significant bits Bits 7:0 - PRODL[7:0] PROD Least Significant bits (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 184 PIC18F26/45/46Q10 (CRC) Cyclic Redundancy Check Module with Me... 13. (CRC) Cyclic Redundancy Check Module with Memory Scanner The Cyclic Redundancy Check (CRC) module provides a software-configurable hardware-implemented CRC checksum generator. This module includes the following features: * * * * * * * 13.1 Any standard CRC up to 16 bits can be used Configurable Polynomial Any seed value up to 16 bits can be used Standard and reversed bit order available Augmented zeros can be added automatically or by the user Memory scanner for fast CRC calculations on program memory user data Software loadable data registers for communication CRC's CRC Module Overview The CRC module provides a means for calculating a check value of program memory. The CRC module is coupled with a memory scanner for faster CRC calculations. The memory scanner can automatically provide data to the CRC module. The CRC module can also be operated by directly writing data to SFRs, without using a scanner. 13.2 CRC Functional Overview The CRC module can be used to detect bit errors in the Flash memory using the built-in memory scanner or through user input RAM memory. The CRC module can accept up to a 16-bit polynomial with up to a 16-bit seed value. A CRC calculated check value (or checksum) will then be generated into the 13.12.4 CRCACC registers for user storage. The CRC module uses an XOR shift register implementation to perform the polynomial division required for the CRC calculation. (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 185 Filename: Title: Last Edit: First Used: Notes: 10-000206A.vsd CRC EXAMPLE 1/8/2014 PIC16(L)F1613 PIC18F26/45/46Q10 (CRC) Cyclic Redundancy Check Module with Me... Figure 13-1. CRC Example Rev. 10-000206A 1/8/2014 CRC-16-ANSI x16 + x15 + x2 + 1 (17 bits) Standard 16-bit representation = 0x8005 CRCXORH = 0b10000000 CRCXORL = 0b0000010- (1) Data Sequence: 0x55, 0x66, 0x77, 0x88 DLEN = 0b0111 PLEN = 0b1111 Data entered into the CRC: SHIFTM = 0: 01010101 01100110 01110111 10001000 SHIFTM = 1: 10101010 01100110 11101110 00010001 Check Value (ACCM = 1): SHIFTM = 0: 0x32D6 CRCACCH = 0b00110010 CRCACCL = 0b11010110 SHIFTM = 1: 0x6BA2 CRCACCH = 0b01101011 CRCACCL = 0b10100010 Note 1: Bit 0 is unimplemented. The LSb of any CRC polynomial is always `1' and will always be treated as a `1' by the CRC for calculating the CRC check value. This bit will be read in software as a `0'. 13.3 CRC Polynomial Implementation Any polynomial can be used. The polynomial and accumulator sizes are determined by the PLEN bits. For an n-bit accumulator, PLEN = n-1 and the corresponding polynomial is n+1 bits. Therefore, the accumulator can be any size up to 16 bits with a corresponding polynomial up to 17 bits. The MSb and LSb of the polynomial are always `1' which is forced by hardware. However, the LSb of the CRCXORL register is unimplemented and always reads as '0'. All polynomial bits between the MSb and LSb are specified by the 13.12.6 CRCXOR registers. For example, when using CRC16-ANSI, the polynomial is defined as X16+X15+X2+1. The X16 and X0 = 1 terms are the MSb and LSb controlled by hardware. The X15 and X2 terms are specified by setting the corresponding CRCXOR<15:0> bits with the value of 0x8004. The actual value is 0x8005 because the hardware sets the LSb to 1. Refer to Figure 13-1. (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 186 Filename: Title: Last Edit: First Used: Notes: 10-000207A.vsd CRC LFSR EXAMPLE 5/27/2014 PIC16F1613 LECQ PIC18F26/45/46Q10 (CRC) Cyclic Redundancy Check Module with Me... Figure 13-2. CRC LFSR Example Rev. 10-000207A 5/27/2014 Linear Feedback Shift Register for CRC-16-ANSI x16 + x15 + x2 + 1 Data in Augmentation Mode ON b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 Data in Augmentation Mode OFF b15 13.4 b14 b13 b12 b11 b10 b9 b8 b7 b6 b0 b5 b4 b3 b2 b1 b0 CRC Data Sources Data can be input to the CRC module in two ways: * User data using the 13.12.3 CRCDAT registers * From Flash memory using the program memory scanner Up to 16 bits of data per word are specified with the DLEN bits. Only the number of data bits in the CRCDATA registers specified by DLEN will be used, other data bits in CRCDATA registers will be ignored. Data is moved into the 13.12.5 CRCSHIFT as an intermediate to calculate the check value located in the 13.12.4 CRCACC registers. The SHIFTM bit is used to determine the bit order of the data being shifted into the accumulator. If SHIFTM is not set, the data will be shifted in MSb first (Big Endian). The value of DLEN will determine the MSb. If SHIFTM bit is set, the data will be shifted into the accumulator in reversed order, LSb first (Little Endian). The CRC module can be seeded with an initial value by setting the CRCACC registers to the appropriate value before beginning the CRC. 13.4.1 CRC from User Data To use the CRC module on data input from the user, the user must write the data to the CRCDAT registers. The data from the CRCDAT registers will be latched into the shift registers on any write to the CRCDATL register. 13.4.2 CRC from Flash To use the CRC module on data located in Flash memory, the user can initialize the program memory scanner as defined in the 13.8 Program Memory Scan Configuration section. 13.5 CRC Check Value The CRC check value will be located in the CRCACC registers after the CRC calculation has finished. The check value will depend on the ACCM and SHIFTM mode settings. (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 187 PIC18F26/45/46Q10 (CRC) Cyclic Redundancy Check Module with Me... When the ACCM bit is set, the CRC module augments the data with a number of zeros equal to the length of the polynomial to align the final check value. When the ACCM bit is not set, the CRC will stop at the end of the data. A number of zeros equal to the length of the polynomial can then be entered into CRCDAT to find the same check value as augmented mode. Alternatively, the expected check value can be entered at this point to make the final result equal 0. When the CRC check value is computed with the SHIFTM bit set, selecting LSb first, and the ACCM bit is set then the final value in the CRCACC registers will be reversed such that the LSb will be in the MSb position and vice versa. This is the expected check value in bit reversed form. When creating a check value to be appended to a data stream, then a bit reversal must be performed on the final value to achieve the correct checksum. CRC can be used to do this reversal by following the steps below: 1. 2. 3. 4. Save CRCACC value in user RAM space Clear the CRCACC registers Clear the CRCXOR registers Write the saved CRCACC value to the CRCDAT input The properly oriented check value will be in the CRCACC registers as the result. 13.6 CRC Interrupt The CRC will generate an interrupt when the BUSY bit transitions from 1 to 0. The CRCIF Interrupt Flag bit of the PIRx register is set every time the BUSY bit transitions, regardless of whether or not the CRC interrupt is enabled. The CRCIF bit can only be cleared in software. The CRC interrupt enable is the CRCIE bit of the PIEx register. 13.7 Configuring the CRC The following steps illustrate how to properly configure the CRC. 1. Determine if the automatic program memory scan will be used with the scanner or manual calculation through the SFR interface and perform the actions specified in 13.4 CRC Data Sources, depending on which decision was made. 2. If desired, seed a starting CRC value into the 13.12.4 CRCACC registers. 3. Program the 13.12.6 CRCXOR registers with the desired generator polynomial. 4. Program the DLENbits with the length of the data word - 1 (refer to Figure 13-1). This determines how many times the shifter will shift into the accumulator for each data word. 5. Program the PLEN bits with the length of the polynomial -2 (refer to Figure 13-1). 6. Determine whether shifting in trailing zeros is desired and set the ACCM bit accordingly. 7. Likewise, determine whether the MSb or LSb should be shifted first and write the SHIFTM bit accordingly. 8. Set the GO bit to begin the shifting process. 9. If manual SFR entry is used, monitor the FULL bit. When FULL = 0, another word of data can be written to the 13.12.3 CRCDAT registers, keeping in mind that Most Significant Byte, CRCDATH, should be written first if the data has more than eight bits, as the shifter will begin upon the CRCDATL register being written. 10. If the scanner is used, the scanner will automatically stuff words into the CRCDAT registers as needed, as long as the SCANGO bit is set. (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 188 PIC18F26/45/46Q10 (CRC) Cyclic Redundancy Check Module with Me... 11. If using the Flash memory scanner, monitor the PIRx SCANIF bit (or the SCANGO bit) for the scanner to finish pushing information into the CRCDATA registers. After the scanner is completed, monitor the BUSY bit to determine that the CRC has been completed and the check value can be read from the CRCACC registers. If both the interrupt flags are set (or both BUSY and SCANGO bits are cleared), the completed CRC calculation can be read from the CRCACC registers. 12. If manual entry is used, monitor the BUSY bit to determine when the CRCACC registers hold the valid check value. 13.8 Program Memory Scan Configuration The program memory scan module may be used in conjunction with the CRC module to perform a CRC calculation over a range of program memory addresses. In order to setup the scanner to work with the CRC the following steps need to performed: 1. 2. 3. 4. 5. 13.9 Set both the EN and SCANEN bits. If they get disabled, all internal states of the scanner and the CRC are reset. However, the CRC SFR registers are unaffected. Choose which memory access mode is to be used (see 13.10 Scanning Modes) and set the MODE bits accordingly. Based on the memory access mode, set the INTM bits to the appropriate Interrupt mode (see 13.10.5 Interrupt Interaction) Set the 13.12.8 SCANLADR and 13.12.9 SCANHADR registers with the respective beginning and ending locations in memory that are to be scanned. The GO bit must be set before setting the SCANGO bit. Setting the SCANGO bit starts the scan. Both the EN and GO bits must be enabled to use the scanner. When either of these bits are disabled, the scan aborts and the INVALID bit is set. The scanner will wait for the signal from the CRC that it is ready for the first Flash memory location, then begin loading data into the CRC. It will continue to do so until it either hits the configured end address or an address that is unimplemented on the device, at which point the SCANGO bit will clear, Scanner functions will cease, and the SCANIF interrupt will be triggered. Alternately, the SCANGO bit can be cleared in software to terminate the scan early if desired. Scanner Interrupt The scanner will trigger an interrupt when the SCANGO bit transitions from `1' to `0'. The SCANIF interrupt flag of PIRx is set when the last memory location is reached and the data is entered into the CRCDATA registers. The SCANIF bit can only be cleared in software. The SCAN interrupt enable is the SCANIE bit of the PIEx register. 13.10 Scanning Modes The memory scanner can scan in four modes: Burst, Peek, Concurrent, and Triggered. These modes are controlled by the MODE bits. The four modes are summarized in Table 13-1. 13.10.1 Burst Mode When MODE = 01, the scanner is in Burst mode. In Burst mode, CPU operation is stalled beginning with the operation after the one that sets the SCANGO bit, and the scan begins, using the instruction clock to execute. The CPU is held in its current state until the scan stops. Note that because the CPU is not executing instructions, the SCANGO bit cannot be cleared in software, so the CPU will remain stalled (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 189 PIC18F26/45/46Q10 (CRC) Cyclic Redundancy Check Module with Me... until one of the hardware end-conditions occurs. Burst mode has the highest throughput for the scanner, but has the cost of stalling other execution while it occurs. 13.10.2 Concurrent Mode When MODE = 00, the scanner is in Concurrent mode. Concurrent mode, like Burst mode, stalls the CPU while performing accesses of memory. However, while Burst mode stalls until all accesses are complete, Concurrent mode allows the CPU to execute in between access cycles. 13.10.3 Triggered mode When MODE = 11, the scanner is in Triggered mode. Triggered mode behaves identically to Concurrent mode, except instead of beginning the scan immediately upon the SCANGO bit being set, it waits for a rising edge from a separate trigger source which is determined by the 13.12.10 SCANTRIG register. 13.10.4 Peek Mode When MODE = 10, the scanner is in Peek mode. Peek mode waits for an instruction cycle in which the CPU does not need to access the NVM (such as a branch instruction) and uses that cycle to do its own NVM access. This results in the lowest throughput for the NVM access (and can take a much longer time to complete a scan than the other modes), but does so without any impact on execution times, unlike the other modes. Table 13-1. Summary of Scanner Modes Description MODE<1:0> 11 Triggered 10 Peek First Scan Access CPU Operation As soon as possible following a trigger Stalled during NVM access CPU resumes execution following each access At the first dead cycle Timing is unaffected CPU continues execution following each access 01 Burst Stalled during NVM access As soon as possible 00 Concurrent CPU suspended until scan completes CPU resumes execution following each access 13.10.5 Interrupt Interaction The INTM bit controls the scanner's response to interrupts depending on which mode the NVM scanner is in, as described in the following table. Table 13-2. Scan Interrupt Modes MODE<1:0> INTM 1 MODE == Burst Interrupt overrides SCANGO (to zero) to pause the burst and the interrupt handler executes at full speed; Scanner Burst resumes when interrupt completes. (c) 2019 Microchip Technology Inc. MODE == CONCURENT or TRIGGERED MODE ==PEEK Scanner suspended during interrupt response (SCANGO = 0); interrupt executes at full speed and scan resumes when the interrupt is complete. This bit is ignored Datasheet Preliminary DS40001996C-page 190 PIC18F26/45/46Q10 (CRC) Cyclic Redundancy Check Module with Me... ...........continued MODE<1:0> INTM 0 MODE == CONCURENT or TRIGGERED MODE == Burst Interrupts do not override SCANGO, and the scan (burst) operation will continue; interrupt response will be delayed until scan completes (latency will be increased). Scanner accesses NVM during interrupt response. MODE ==PEEK This bit is ignored In general, if INTM = 0, the scanner will take precedence over the interrupt, resulting in decreased interrupt processing speed and/or increased interrupt response latency. If INTM = 1, the interrupt will take precedence and have a better speed, delaying the memory scan. 13.10.6 WWDT interaction Operation of the WWDT is not affected by scanner activity. Hence, it is possible that long scans, particularly in Burst mode, may exceed the WWDT time-out period and result in an undesired device Reset. This should be considered when performing memory scans with an application that also utilizes WWDT. 13.10.7 In-Circuit Debug (ICD) Interaction The scanner freezes when an ICD halt occurs, and remains frozen until user-mode operation resumes. The debugger may inspect the SCANCON0 and SCANLADR registers to determine the state of the scan. The ICD interaction with each operating mode is summarized in the following table. (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 191 PIC18F26/45/46Q10 (CRC) Cyclic Redundancy Check Module with Me... Table 13-3. ICD and Scanner Interactions Scanner Operating Mode ICD Halt Peek External Halt PC Breakpoint Data Breakpoint Concurrent Triggered If external halt is asserted during a scan cycle, the instruction (delayed by scan) may or may not execute before ICD entry, depending on external halt timing. If external halt is asserted during the BSF(SCANCON.GO), ICD entry occurs, and the burst is delayed until ICD exit. Otherwise, the current NVM-access cycle will complete, and then the scanner will be interrupted for ICD entry. If external halt is asserted during the cycle immediately prior to the scan cycle, both scan and instruction execution happen after the ICD exits. If external halt is asserted during the burst, the burst is suspended and will resume with ICD exit. Scan cycle occurs before ICD entry and If scanner would peek instruction execution an instruction that is happens after the ICD not executed (because exits. of ICD entry), the peek The instruction with the will occur after ICD dataBP executes and exit, when the ICD entry occurs instruction executes. immediately after. If scan is requested during that cycle, the scan cycle is postponed until the ICD exits. Single Step If a scan cycle is ready after the debug instruction is executed, the scan will read PFM and then the ICD is reentered. SWBP and ICDINST If scan would stall a SWBP, the scan cycle occurs and the ICD is entered. (c) 2019 Microchip Technology Inc. Burst If PCPB (or single step) is on BSF(SCANCON.GO), the ICD is entered before execution; execution of the burst will occur at ICD exit, and the burst will run to completion. Note that the burst can be interrupted by an external halt. If SWBP replaces BSF(SCANCON.GO), the ICD will be entered; instruction execution will occur at ICD exit (from ICDINSTR register), and the burst will run to completion. Datasheet Preliminary DS40001996C-page 192 PIC18F26/45/46Q10 (CRC) Cyclic Redundancy Check Module with Me... 13.10.8 Peripheral Module Disable Both the CRC and scanner module can be disabled individually by setting the CRCMD and SCANMD bits of the PMD0 register. The SCANMD can be used to enable or disable to the scanner module only if the SCANE bit of Configuration Word 4 is set. If the SCANE bit is cleared, then the scanner module is not available for use and the SCANMD bit is ignored. (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 193 PIC18F26/45/46Q10 (CRC) Cyclic Redundancy Check Module with Me... 13.11 Address 0x0F44 Register Summary - CRC Name SCANLADR Bit Pos. 7:0 SCANLADRL[7:0] 15:8 SCANLADRH[7:0] 23:16 0x0F47 SCANHADR SCANLADRU[5:0] 7:0 SCANHADRL[7:0] 15:8 SCANHADRH[7:0] 23:16 0x0F4A SCANCON0 7:0 0x0F4B SCANTRIG 7:0 SCANHADRU[5:0] SCANEN SCANGO BUSY INVALID INTM MODE[1:0] TSEL[4:0] 0x0F4C ... Reserved 0x0F6E 0x0F6F CRCDAT 7:0 15:8 CRCDATH[7:0] 7:0 CRCACCL[7:0] 15:8 CRCACCH[7:0] 0x0F71 CRCACC 0x0F73 CRCSHIFT 0x0F75 CRCXOR 0x0F77 CRCCON0 7:0 0x0F78 CRCCON1 7:0 13.12 CRCDATL[7:0] 7:0 CRCSHIFTL[7:0] 15:8 CRCSHIFTH[7:0] 7:0 CRCXORL[6:0] 15:8 CRCXORL0 CRCXORH[7:0] EN GO BUSY ACCM SHIFTM DLEN[3:0] FULL PLEN[3:0] Register Definitions: CRC and Scanner Control Long bit name prefixes for the CRC are shown in the table below. Refer to the "Long Bit Names Section" for more information. Table 13-4. CRC Long Bit Name Prefixes Peripheral Bit Name Prefix CRC CRC Related Links 1.4.2.2 Long Bit Names (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 194 PIC18F26/45/46Q10 (CRC) Cyclic Redundancy Check Module with Me... 13.12.1 CRCCON0 Name: Address: Reset: CRCCON0 0xF77 0 CRC Control Register 0 Bit Access Reset 7 6 5 4 3 2 1 0 EN GO BUSY ACCM SHIFTM FULL R/W R/W RO R/W R/W RO 0 0 0 0 0 0 Bit 7 - EN Value 1 0 CRC Enable bit Description CRC module is released from Reset CRC is disabled and consumes no operating current Bit 6 - GO Value 1 0 CRC Start bit Description Start CRC serial shifter CRC serial shifter turned off Bit 5 - BUSY CRC Busy bit Value Description 1 Shifting in progress or pending 0 All valid bits in shifter have been shifted into accumulator and EMPTY = 1 Bit 4 - ACCM Accumulator Mode bit Value Description 1 Data is augmented with zeros 0 Data is not augmented with zeros Bit 1 - SHIFTM Shift Mode bit Value Description 1 Shift right (LSb) 0 Shift left (MSb) Bit 0 - FULL Data Path Full Indicator bit Value Description 1 CRCDATH/L registers are full 0 CRCDATH/L registers have shifted their data into the shifter (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 195 PIC18F26/45/46Q10 (CRC) Cyclic Redundancy Check Module with Me... 13.12.2 CRCCON1 Name: Address: Reset: CRCCON1 0xF78 0 CRC Control Register 1 Bit 7 6 5 4 3 2 R/W 0 1 0 R/W R/W R/W R/W R/W 0 0 0 0 R/W R/W 0 0 0 DLEN[3:0] Access Reset PLEN[3:0] Bits 7:4 - DLEN[3:0] Data Length bits Denotes the length of the data word -1 (See Figure 13-1) Bits 3:0 - PLEN[3:0] Polynomial Length bits Denotes the length of the polynomial -1 (See Figure 13-1) (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 196 PIC18F26/45/46Q10 (CRC) Cyclic Redundancy Check Module with Me... 13.12.3 CRCDAT Name: Address: CRCDAT 0xF6F CRC Data Register Bit 15 14 13 12 11 10 9 8 CRCDATH[7:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset x x x x x x x x Bit 7 6 5 4 3 2 1 0 R/W R/W R/W R/W R/W R/W R/W R/W x x x x x x x x CRCDATL[7:0] Access Reset Bits 15:8 - CRCDATH[7:0] CRC Input/Output Data Most Significant Byte Bits 7:0 - CRCDATL[7:0] CRC Input/Output Data Least Significant Byte (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 197 PIC18F26/45/46Q10 (CRC) Cyclic Redundancy Check Module with Me... 13.12.4 CRCACC Name: Address: Reset: CRCACC 0xF71 0 CRC Accumulator Register Bit 15 14 13 12 R/W R/W R/W R/W Reset 0 0 0 0 Bit 7 6 5 4 11 10 9 8 R/W R/W R/W R/W 0 0 0 0 3 2 1 0 CRCACCH[7:0] Access CRCACCL[7:0] Access Reset R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Bits 15:8 - CRCACCH[7:0] CRC Accumulator Register most significant byte Writing to this register writes the Most Significant Byte of the CRC accumulator register. Reading from this register reads the Most Significant Byte of the CRC accumulator. Bits 7:0 - CRCACCL[7:0] CRC Accumulator Register least significant byte Writing to this register writes the Least Significant Byte of the CRC accumulator register. Reading from this register reads the Least Significant Byte of the CRC accumulator. (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 198 PIC18F26/45/46Q10 (CRC) Cyclic Redundancy Check Module with Me... 13.12.5 CRCSHIFT Name: Address: Reset: CRCSHIFT 0xF73 0 CRC Shift Register Bit 15 14 13 12 Access RO RO RO RO Reset 0 0 0 0 Bit 7 6 5 4 11 10 9 8 RO RO RO RO 0 0 0 0 3 2 1 0 CRCSHIFTH[7:0] CRCSHIFTL[7:0] Access Reset RO RO RO RO RO RO RO RO 0 0 0 0 0 0 0 0 Bits 15:8 - CRCSHIFTH[7:0] CRC Shifter Register Most Significant Byte Reading from this register reads the Most Significant Byte of the CRC Shifter. Bits 7:0 - CRCSHIFTL[7:0] CRC Shifter Register Least Significant Byte Reading from this register reads the Least Significant Byte of the CRC Shifter. (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 199 PIC18F26/45/46Q10 (CRC) Cyclic Redundancy Check Module with Me... 13.12.6 CRCXOR Name: Address: CRCXOR 0xF75 CRC XOR Register Bit 15 14 13 12 11 10 9 8 CRCXORH[7:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset x x x x x x x x Bit 7 6 5 4 3 2 1 0 R/W R/W R/W R/W R/W R/W R/W U x x x x x x x 1 CRCXORL[6:0] Access Reset CRCXORL0 Bits 15:8 - CRCXORH[7:0] XOR of Polynomial Term XN Enable Most Significant Byte Bits 7:1 - CRCXORL[6:0] XOR of Polynomial Term XN Enable Least Significant Byte Bit 0 - CRCXORL0 LSbit is unimplemented. Read as 1 (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 200 PIC18F26/45/46Q10 (CRC) Cyclic Redundancy Check Module with Me... 13.12.7 SCANCON0 Name: Address: SCANCON0 0xF4A Scanner Access Control Register 0 Bit Access Reset 7 6 5 4 3 SCANEN SCANGO BUSY INVALID INTM 2 1 0 R/W R/W/HC R R R/W R/W R/W 0 0 0 1 0 0 0 MODE[1:0] Bit 7 - SCANEN Scanner Enable bit(1) Value Description 1 Scanner is enabled 0 Scanner is disabled, internal states are reset Bit 6 - SCANGO Scanner GO bit(2, 3) Value Description 1 When the CRC sends a ready signal, NVM will be accessed according to MDx and data passed to the client peripheral. 0 Scanner operations will not occur Bit 5 - BUSY Scanner Busy Indicator bit(4) Value Description 1 Scanner cycle is in process 0 Scanner cycle is complete (or never started) Bit 4 - INVALID Scanner Abort Signal bit Value Description 1 SCANLADRL/H/U has incremented to an invalid address(6) or the scanner was not setup correctly(7) 0 SCANLADRL/H/U points to a valid address Bit 3 - INTM NVM Scanner Interrupt Management Mode Select bit Value Condition Description X MODE = 10 This bit is ignored 1 MODE = 01 CPU is stalled until all data is transferred. SCANGO is overridden (to zero) during interrupt operation; scanner resumes after returning from interrupt 0 MODE = 01 CPU is stalled until all data is transferred. SCANGO is not affected by interrupts, the interrupt response will be affected 1 MODE = 00 OR 11 SCANGO is overridden (to zero) during interrupt operation; scan operations resume after returning from interrupt 0 MODE = 00 OR 11 Interrupts do not prevent NVM access Bits 1:0 - MODE[1:0] Memory Access Mode bits(5) Value Description 11 Triggered mode (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 201 PIC18F26/45/46Q10 (CRC) Cyclic Redundancy Check Module with Me... Value 10 01 00 Description Peek mode Burst mode Concurrent mode Note: 1. Setting SCANEN = 0 (SCANCON0 register) does not affect any other register content. 2. This bit is cleared when LADR > HADR (and a data cycle is not occurring). 3. If INTM = 1, this bit is overridden (to zero, but not cleared) during an interrupt response. 4. BUSY = 1 when the NVM is being accessed, or when the CRC sends a ready signal. 5. See Table 13-1 for more detailed information. 6. An invalid address can occur when the entire range of PFM is scanned and the value of LADR rolls over. An invalid address can also occur if the value in the Scan Low address registers points to a location that is not mapped in the memory map of the device. 7. CRCEN and CRCGO bits must be set before setting SCANGO bit. Refer to 13.8 Program Memory Scan Configuration. (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 202 PIC18F26/45/46Q10 (CRC) Cyclic Redundancy Check Module with Me... 13.12.8 SCANLADR Name: Address: Reset: SCANLADR 0xF44 0 Scan Low Address Register Bit 23 22 21 20 19 R/W R/W R/W 0 0 0 13 12 11 18 17 16 R/W R/W R/W 0 0 0 10 9 8 SCANLADRU[5:0] Access Reset Bit 15 14 SCANLADRH[7:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 SCANLADRL[7:0] Access Reset R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Bits 21:16 - SCANLADRU[5:0] Scan Start/Current Address upper byte Upper bits of the current address to be fetched from, value increments on each fetch of memory. Bits 15:8 - SCANLADRH[7:0] Scan Start/Current Address high byte High byte of the current address to be fetched from, value increments on each fetch of memory. Bits 7:0 - SCANLADRL[7:0] Scan Start/Current Address low byte Low byte of the current address to be fetched from, value increments on each fetch of memory. Note: 1. Registers SCANLADRU/H/L form a 22-bit value, but are not guarded for atomic or asynchronous access; registers should only be read or written while SCANGO = 0. 2. While SCANGO = 1, writing to this register is ignored. (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 203 PIC18F26/45/46Q10 (CRC) Cyclic Redundancy Check Module with Me... 13.12.9 SCANHADR Name: Address: Reset: SCANHADR 0xF47 0 Scan High Address Register Bit 23 22 21 20 19 R/W R/W R/W 1 1 1 13 12 11 18 17 16 R/W R/W R/W 1 1 1 10 9 8 SCANHADRU[5:0] Access Reset Bit 15 14 SCANHADRH[7:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 1 1 1 1 1 1 1 1 Bit 7 6 5 4 3 2 1 0 SCANHADRL[7:0] Access Reset R/W R/W R/W R/W R/W R/W R/W R/W 1 1 1 1 1 1 1 1 Bits 21:16 - SCANHADRU[5:0] Scan End Address bits Upper bits of the address at the end of the designated scan Bits 15:8 - SCANHADRH[7:0] Scan End Address bits High byte of the address at the end of the designated scan Bits 7:0 - SCANHADRL[7:0] Scan End Address bits Low byte of the address at the end of the designated scan Note: 1. Registers SCANHADRU/H/L form a 22-bit value but are not guarded for atomic or asynchronous access; registers should only be read or written while SCANGO = 0. 2. While SCANGO = 1, writing to this register is ignored. (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 204 PIC18F26/45/46Q10 (CRC) Cyclic Redundancy Check Module with Me... 13.12.10 SCANTRIG Name: Address: Reset: SCANTRIG 0xF4B 0 SCAN Trigger Selection Register Bit 7 6 5 4 3 R/W R/W 0 0 2 1 0 R/W R/W R/W 0 0 0 TSEL[4:0] Access Reset Bits 4:0 - TSEL[4:0] Scanner Data Trigger Input Selection bits Table 13-5. SCAN Trigger Sources TSEL Trigger Source 11000 - 11111 Reserved 10111 CLC8_out 10110 CLC7_out 10101 CLC6_out 10100 CLC5_out 10011 CLC4_out 10010 CLC3_out 10001 CLC2_out 10000 CLC1_out 01001 - 01111 Reserved 01000 TMR6_postscaled 00111 TMR5_output 00110 TMR4_postscaled 00101 TMR3_output 00100 TMR2_postscaled 00011 TMR1_output 00010 TMR0_output 00001 CLKREF_output 00000 LFINTOSC (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 205 PIC18F26/45/46Q10 Interrupts 14. Interrupts The PIC18F26/45/46Q10 devices have multiple interrupt sources and an interrupt priority feature that allows most interrupt sources to be assigned a high or low-priority level. The high-priority interrupt vector is at 0008h and the low-priority interrupt vector is at 0018h. A high-priority interrupt event will interrupt a low-priority interrupt that may be in progress. The registers for controlling interrupt operation are: * * * * INTCON PIRx (Interrupt flags) PIEx (Interrupt enables) IPRx (High/Low interrupt priority) (R) It is recommended that the Microchip header files supplied with MPLAB IDE be used for the symbolic bit names in these registers. This allows the assembler/compiler to automatically take care of the placement of these bits within the specified register. In general, interrupt sources have three bits to control their operation. They are: * Flag bit to indicate that an interrupt event occurred * Enable bit that allows program execution to branch to the interrupt vector address when the flag bit is set * Priority bit to select high priority or low priority 14.1 Midrange Compatibility When the IPEN bit is cleared (default state), the interrupt priority feature is disabled and interrupts are (R) compatible with PIC microcontroller midrange devices. In Compatibility mode, the interrupt priority bits of the IPRx registers have no effect. The PEIE/GIEL bit is the global interrupt enable for the peripherals. The PEIE/GIEL bit disables only the peripheral interrupt sources and enables the peripheral interrupt sources when the GIE/GIEH bit is also set. The GIE/GIEH bit is the global interrupt enable which enables all nonperipheral interrupt sources and disables all interrupt sources, including the peripherals. All interrupts branch to address 0008h in Compatibility mode. 14.2 Interrupt Priority The interrupt priority feature is enabled by setting the IPEN bit. When interrupt priority is enabled the GIE/ GIEH and PEIE/GIEL Global Interrupt Enable bits of Compatibility mode are replaced by the GIEH high priority, and GIEL low priority, global interrupt enables. When the IPEN bit is set, the GIEH bit enables all interrupts which have their associated bit in the IPRx register set. When the GIEH bit is cleared, then all interrupt sources including those selected as low priority in the IPRx register are disabled. When both GIEH and GIEL bits are set, all interrupts selected as low priority sources are enabled. A high-priority interrupt will vector immediately to address 00 0008h and a low-priority interrupt will vector to address 00 0018h. 14.3 Interrupt Response When an interrupt is responded to, the Global Interrupt Enable bit is cleared to disable further interrupts. The GIE/GIEH bit is the Global Interrupt Enable when the IPEN bit is cleared. When the IPEN bit is set, (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 206 PIC18F26/45/46Q10 Interrupts enabling interrupt priority levels, the GIEH bit is the high priority Global Interrupt Enable and the GIEL bit is the low priority Global Interrupt Enable. High-priority interrupt sources can interrupt a low-priority interrupt. Low-priority interrupts are not processed while high-priority interrupts are in progress. The return address is pushed onto the stack and the PC is loaded with the interrupt vector address (0008h or 0018h). Once in the Interrupt Service Routine, the source(s) of the interrupt can be determined by polling the interrupt flag bits in the INTCONx and PIRx registers. The interrupt flag bits must be cleared by software before re-enabling interrupts to avoid repeating the same interrupt. The "return from interrupt" instruction, RETFIE, exits the interrupt routine and sets the GIE/GIEH bit (GIEH or GIEL if priority levels are used), which re-enables interrupts. For external interrupt events, such as the INT pins or the interrupt-on-change pins, the interrupt latency will be three to four instruction cycles. The exact latency is the same for one-cycle or two-cycle instructions. Individual interrupt flag bits are set, regardless of the status of their corresponding enable bits or the Global Interrupt Enable bit. Important: Do not use the MOVFF instruction to modify any of the interrupt control registers while any interrupt is enabled. Doing so may cause erratic microcontroller behavior. (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 207 Filename: Title: Last Edit: First Used: PIC18F26/45/46Q10 10-000010B.vsd Generic Interrupt Logic for PIC18 5/4/2016 Interrupts Figure 14-1. PIC18 Interrupt Logic Rev. 10-000010B 5/4/2016 Wake-up if in Idle or Sleep modes PIR0 PIE0 IPR0 PIR1 PIE1 IPR1 Interrupt to CPU Vector at Location 0008h PIR2 PIE2 IPR2 GIEH/GIE IPEN IPEN GIEL/PEIE IPEN PIRx PIEx IPRx High Priority Interrupt Generation Low Priority Interrupt Generation PIR1 PIE1 IPR1 PIR2 PIE2 IPR2 PIR0 PIE0 IPR0 PIRx PIEx IPRx 14.4 Interrupt to CPU Vector at Location 0018h GIEH/GIE GIEL/PEIE INTCON Registers The INTCON registers are readable and writable registers, which contain various enable and priority bits. 14.5 PIR Registers The PIR registers contain the individual flag bits for the peripheral interrupts. Due to the number of peripheral interrupt sources, there are 8 PIR registers. 14.6 PIE Registers The PIE registers contain the individual enable bits for the peripheral interrupts. Due to the number of peripheral interrupt sources, there are 8 Peripheral Interrupt Enable registers. When IPEN = 0, the PEIE/ GIEL bit must be set to enable any of these peripheral interrupts. (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 208 PIC18F26/45/46Q10 Interrupts 14.7 IPR Registers The IPR registers contain the individual priority bits for the peripheral interrupts. Due to the number of peripheral interrupt sources, there are 8 Peripheral Interrupt Priority registers. Using the priority bits requires that the Interrupt Priority Enable (IPEN) bit be set. 14.8 INTn Pin Interrupts PIC18F26/45/46Q10 devices have 3 external interrupt sources which can be assigned to any pin on PORTA and PORTB using PPS. The external interrupt sources are edge-triggered. If the corresponding INTxEDG bit in the 14.13.1 INTCON register is set (= 1), the interrupt is triggered by a rising edge. It the bit is clear, the trigger is on the falling edge. All external interrupts (INT0, INT1, INT2) can wake-up the processor from Idle or Sleep modes if bit INTxE was set prior to going into those modes. If the Global Interrupt Enable bit (GIE/GIEH) is set, the processor will branch to the interrupt vector following wake-up. Interrupt priority is determined by the value contained in the corresponding interrupt priority bit (INT0P, INT1P, INT2P) of the 14.13.18 IPR0 register. 14.9 TMR0 Interrupt In 8-bit mode (which is the default), an overflow in the TMR0 register (FFh 00h) will set flag bit, TMR0IF. In 16-bit mode, an overflow in the TMR0H:TMR0L register pair (FFFFh 0000h) will set TMR0IF. The interrupt can be enabled/disabled by setting/clearing enable bit, TMR0IE. Interrupt priority for Timer0 is determined by the value contained in the interrupt priority bit, TMR0IP. See "Timer0 Module" for further details on the Timer0 module. 14.10 Interrupt-on-Change An input change on any port pins that support IOC sets Flag bit, IOCIF. The interrupt can be enabled/ disabled by setting/clearing the enable bit, IOCIE. Pins must also be individually enabled in the IOCxP and IOCxN register. IOCIF is a read-only bit and the flag can be cleared by clearing the corresponding IOCxF registers. For more information, refer to chapter "Interrupt-on-Change". Related Links 16. Interrupt-on-Change 14.11 Context Saving During Interrupts During interrupts, the return PC address is saved on the stack. Additionally, the WREG, STATUS and BSR registers are saved on the fast return stack. If a fast return from interrupt is not used the user may need to save the WREG, STATUS and BSR registers on entry to the Interrupt Service Routine. Depending on the user's application, other registers may also need to be saved. Saving Status, WREG and BSR Registers in RAM saves and restores the WREG, STATUS and BSR registers during an Interrupt Service Routine. Example 14-1. Saving Status, WREG and BSR Registers in RAM MOVWF (c) 2019 Microchip Technology Inc. W_TEMP ; W_TEMP is in virtual bank Datasheet Preliminary DS40001996C-page 209 PIC18F26/45/46Q10 Interrupts MOVFF MOVFF STATUS, STATUS_TEMP BSR, BSR_TEMP ; ; USER ISR CODE ; MOVFF BSR_TEMP, BSR MOVF W_TEMP, W MOVFF STATUS_TEMP, STATUS ; STATUS_TEMP located anywhere ; BSR_TEMP located anywhere ; Restore BSR ; Restore WREG ; Restore STATUS Related Links 10.1.2.5 Fast Register Stack (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 210 PIC18F26/45/46Q10 Interrupts 14.12 Register Summary - Interrupt Control Address Name Bit Pos. 0x0EB5 IPR0 7:0 0x0EB6 IPR1 7:0 OSCFIP 0x0EB7 IPR2 7:0 HLVDIP 0x0EB8 IPR3 7:0 RC2IP TX2IP 0x0EB9 IPR4 7:0 0x0EBA IPR5 7:0 TMR0IP IOCIP INT1IP INT0IP CSWIP ADTIP ADIP ZCDIP C2IP C1IP RC1IP TX1IP BCL2IP SSP2IP BCL1IP SSP1IP TMR6IP TMR5IP TMR4IP TMR3IP TMR2IP TMR1IP TMR5GIP TMR3GIP TMR1GIP CLC4IP CLC3IP CLC2IP CLC1IP CLC5IP 0x0EBB IPR6 7:0 CLC8IP CLC7IP CLC6IP 0x0EBC IPR7 7:0 SCANIP CRCIP NVMIP 0x0EBD PIE0 7:0 0x0EBE PIE1 7:0 OSCFIE 0x0EBF PIE2 7:0 HLVDIE 0x0EC0 PIE3 7:0 RC2IE TX2IE 0x0EC1 PIE4 7:0 0x0EC2 PIE5 7:0 0x0EC3 PIE6 0x0EC4 PIE7 0x0EC5 PIR0 7:0 0x0EC6 PIR1 7:0 OSCFIF 0x0EC7 PIR2 7:0 HLVDIF RC2IF TX2IF TMR0IE IOCIE INT0IE CSWIE ADTIE ADIE ZCDIE C2IE C1IE RC1IE TX1IE BCL2IE SSP2IE BCL1IE SSP1IE TMR5IE TMR4IE TMR3IE TMR2IE TMR1IE TMR5GIE TMR3GIE TMR1GIE CLC1IE 7:0 CLC8IE CLC7IE CLC6IE CLC5IE 7:0 SCANIE CRCIE NVMIE 7:0 PIR4 7:0 0x0ECA PIR5 7:0 0x0ECB PIR6 0x0ECC PIR7 INT2IE TMR6IE CLC2IE PIR3 CCP1IP INT1IE CLC3IE 0x0EC8 CCP2IP CWG1IP CLC4IE 0x0EC9 INT2IP TMR0IF CCP2IE CCP1IE CWG1IE IOCIF INT2IF INT1IF INT0IF CSWIF ADTIF ADIF ZCDIF C2IF C1IF RC1IF TX1IF BCL2IF SSP2IF BCL1IF SSP1IF TMR6IF TMR5IF TMR4IF TMR3IF TMR2IF TMR1IF TMR5GIF TMR3GIF TMR1GIF CLC4IF CLC3IF CLC2IF CLC1IF 7:0 CLC8IF CLC7IF CLC6IF CLC5IF 7:0 SCANIF CRCIF NVMIF 7:0 GIE/GIEH PEIE/GIEL IPEN CCP2IF CCP1IF CWG1IF 0x0ECD ... Reserved 0x0FF1 0x0FF2 14.13 INTCON INT2EDG INT1EDG INT0EDG Register Definitions: Interrupt Control (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 211 PIC18F26/45/46Q10 Interrupts 14.13.1 INTCON Name: Address: INTCON 0xFF2 Interrupt Control Register Bit Access Reset 7 6 5 2 1 0 GIE/GIEH PEIE/GIEL IPEN 4 3 INT2EDG INT1EDG INT0EDG R/W R/W R/W R/W R/W R/W 0 0 0 1 1 1 Bit 7 - GIE/GIEH Global Interrupt Enable bit Value Condition Description 1 If IPEN = 1 Enables all unmasked interrupts and cleared by hardware for high-priority interrupts only 0 If IPEN = 1 Disables all interrupts 1 If IPEN = 0 Enables all unmasked interrupts and cleared by hardware for all interrupts 0 If IPEN = 0 Disables all interrupts Bit 6 - PEIE/GIEL Peripheral Interrupt Enable bit Value Condition Description 1 If IPEN = 1 Enables all low-priority interrupts and cleared by hardware for low-priority interrupts only 0 If IPEN = 1 Disables all low-priority interrupts 1 If IPEN = 0 Enables all unmasked peripheral interrupts 0 If IPEN = 0 Disables all peripheral interrupts Bit 5 - IPEN Interrupt Priority Enable bit Value Description 1 Enable priority levels on interrupts 0 Disable priority levels on interrupts Bits 0, 1, 2 - INTxEDG External Interrupt `x' Edge Select bit Value Description 1 Interrupt on rising edge of INTx pin 0 Interrupt on falling edge of INTx pin Important: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature allows for software polling. (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 212 PIC18F26/45/46Q10 Interrupts 14.13.2 PIR0 Name: Address: PIR0 0xEC5 Peripheral Interrupt Request (Flag) Register 0 Bit 7 6 Access Reset 5 4 2 1 0 TMR0IF IOCIF 3 INT2IF INT1IF INT0IF R/W R R/W R/W R/W 0 0 0 0 0 Bit 5 - TMR0IF Timer0 Interrupt Flag bit(1) Value Description 1 TMR0 register has overflowed (must be cleared by software) 0 TMR0 register has not overflowed Bit 4 - IOCIF Interrupt-on-Change Flag bit(1,2) Value Description 1 IOC event has occurred (must be cleared by software) 0 IOC event has not occurred Bits 0, 1, 2 - INTxIF External Interrupt `x' Flag bit(1,3) Value Description 1 External Interrupt `x' has occurred 0 External Interrupt `x' has not occurred Note: 1. Interrupts are not disabled by the PEIE bit. 2. IOCIF is a read-only bit; to clear the interrupt condition, all bits in the IOCF register must be cleared. 3. The external interrupt GPIO pin is selected by the INTPPS register. (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 213 PIC18F26/45/46Q10 Interrupts 14.13.3 PIR1 Name: Address: PIR1 0xEC6 Peripheral Interrupt Request (Flag) Register 1 Bit Access Reset 7 6 1 0 OSCFIF CSWIF 5 4 3 2 ADTIF ADIF R/W R/W R/W R/W 0 0 0 0 Bit 7 - OSCFIF Oscillator Fail Interrupt Flag bit Value Description 1 Device oscillator failed, clock input has changed to HFINTOSC (must be cleared by software) 0 Device clock operating Bit 6 - CSWIF Clock-Switch Interrupt Flag bit(1) Value Description 1 New oscillator is ready for switch (must be cleared by software) 0 New oscillator is not ready for switch or has not been started Bit 1 - ADTIF ADC Threshold Interrupt Flag bit Value Description 1 ADC Threshold interrupt has occurred (must be cleared by software) 0 ADC Threshold event is not complete or has not been started Bit 0 - ADIF ADC Interrupt Flag bit Value Description 1 An A/D conversion completed (must be cleared by software) 0 The A/D conversion is not complete or has not been started Note: 1. The CSWIF interrupt will not wake the system from Sleep. The system will Sleep until another interrupt causes the wake-up. Related Links 4.3.3 Clock Switch and Sleep (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 214 PIC18F26/45/46Q10 Interrupts 14.13.4 PIR2 Name: Address: PIR2 0xEC7 Peripheral Interrupt Request (Flag) Register 2 Bit Access Reset 7 6 1 0 HLVDIF ZCDIF 5 4 3 2 C2IF C1IF R/W R/W R/W R/W 0 0 0 0 Bit 7 - HLVDIF HLVD Interrupt Flag bit Value Description 1 HLVD interrupt event has occurred 0 HLVD interrupt event has not occurred or has not been set up Bit 6 - ZCDIF Zero-Cross Detect Interrupt Flag bit Value Description 1 ZCD Output has changed (must be cleared in software) 0 ZCD Output has not changed Bits 0, 1 - CxIF Comparator `x' Interrupt Flag bit Value Description 1 Comparator Cx output has changed (must be cleared by software) 0 Comparator Cx output has not changed (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 215 PIC18F26/45/46Q10 Interrupts 14.13.5 PIR3 Name: Address: PIR3 0xEC8 Peripheral Interrupt Request (Flag) Register 3 Bit 7 6 5 4 3 2 1 0 RC2IF TX2IF RC1IF TX1IF BCL2IF SSP2IF BCL1IF SSP1IF Access R R R R R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bits 5, 7 - RCxIF EUSARTx Receive Interrupt Flag bit Value Description 1 The EUSARTx receive buffer, RCxREG, is full (cleared by reading RCxREG) 0 The EUSARTx receive buffer is empty Bits 4, 6 - TXxIF EUSARTx Transmit Interrupt Flag bit Value Description 1 The EUSARTx transmit buffer, TXxREG, is empty (cleared by writing TXxREG) 0 The EUSARTx transmit buffer is full Bits 1, 3 - BCLxIF MSSPx Bus Collision Interrupt Flag bit Value Description 1 A bus collision has occurred while the MSSPx module configured in I2C master was transmitting (must be cleared in software) 0 No bus collision occurred Bits 0, 2 - SSPxIF Synchronous Serial Port `x' Interrupt Flag bit Value Description 1 The transmission/reception is complete (must be cleared in software) 0 Waiting to transmit/receive (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 216 PIC18F26/45/46Q10 Interrupts 14.13.6 PIR4 Name: Address: PIR4 0xEC9 Peripheral Interrupt Request (Flag) Register 4 Bit 7 6 Access Reset 5 4 3 2 1 0 TMR6IF TMR5IF TMR4IF TMR3IF TMR2IF TMR1IF R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 Bit 5 - TMR6IF TMR6 to PR6 Match Interrupt Flag bit Value Description 1 TMR6 to PR6 match occurred (must be cleared in software) 0 No TMR6 to PR6 match occurred Bit 4 - TMR5IF TMR5 Overflow Interrupt Flag bit Value Description 1 TMR5 register overflowed (must be cleared in software) 0 TMR5 register did not overflow Bit 3 - TMR4IF TMR4 to PR4 Match Interrupt Flag bit Value Description 1 TMR4 to PR4 match occurred (must be cleared in software) 0 No TMR4 to PR4 match occurred Bit 2 - TMR3IF TMR3 Overflow Interrupt Flag bit Value Description 1 TMR3 register overflowed (must be cleared in software) 0 TMR3 register did not overflow Bit 1 - TMR2IF TMR2 to PR2 Match Interrupt Flag bit Value Description 1 TMR2 to PR2 match occurred (must be cleared in software) 0 No TMR2 to PR2 match occurred Bit 0 - TMR1IF TMR1 Overflow Interrupt Flag bit Value Description 1 TMR1 register overflowed (must be cleared in software) 0 TMR1 register did not overflow (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 217 PIC18F26/45/46Q10 Interrupts 14.13.7 PIR5 Name: Address: PIR5 0xECA Peripheral Interrupt Request (Flag) Register 5 Bit Access Reset 7 6 5 4 2 1 0 CLC4IF CLC3IF CLC2IF CLC1IF 3 TMR5GIF TMR3GIF TMR1GIF R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 Bits 4, 5, 6, 7 - CLCxIF CLCx Interrupt Flag bit Value Description 1 A CLCx interrupt occurred 0 No CLCx interrupt occurred Bit 2 - TMR5GIF TMR5 Gate Interrupt Flag bit Value Description 1 TMR5 gate interrupt occurred (must be cleared in software) 0 No TMR5 gate occurred Bit 1 - TMR3GIF TMR3 Gate Interrupt Flag bit Value Description 1 TMR3 gate interrupt occurred (must be cleared in software) 0 No TMR3 gate occurred Bit 0 - TMR1GIF TMR1 Gate Interrupt Flag bit Value Description 1 TMR1 gate interrupt occurred (must be cleared in software) 0 No TMR1 gate occurred (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 218 PIC18F26/45/46Q10 Interrupts 14.13.8 PIR6 Name: Address: PIR6 0xECB PIR6 Peripheral Interrupt Request (Flag) Register 6 Bit Access Reset 7 6 5 4 1 0 CLC8IF CLC7IF CLC6IF CLC5IF 3 2 CCP2IF CCP1IF R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 Bits 4, 5, 6, 7 - CLCyIF CLCx Interrupt Flag bit Value Description 1 A CLCx interrupt occurred 0 No CLCx interrupt occurred Bit 1 - CCP2IF ECCP2 Interrupt Flag bit Value Condition Description 1 Capture mode A TMR register capture occurred (must be cleared in software) 0 Capture mode No TMR register capture occurred 1 Compare mode A TMR register compare match occurred (must be cleared in software) 0 Compare mode No TMR register compare match occurred -- PWM mode Unused in PWM mode Bit 0 - CCP1IF ECCP1 Interrupt Flag bit Value Condition Description 1 Capture mode A TMR register capture occurred (must be cleared in software) 0 Capture mode No TMR register capture occurred 1 Compare mode A TMR register compare match occurred (must be cleared in software) 0 Compare mode No TMR register compare match occurred -- PWM mode Unused in PWM mode (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 219 PIC18F26/45/46Q10 Interrupts 14.13.9 PIR7 Name: Address: PIR7 0xECC Peripheral Interrupt Request (Flag) Register 7 Bit Access Reset 7 6 5 SCANIF CRCIF NVMIF 4 3 2 1 CWG1IF 0 R/W R/W R/W R/W 0 0 0 0 Bit 7 - SCANIF SCAN Interrupt Flag bit Value Description 1 SCAN interrupt has occurred (must be cleared in software) 0 SCAN interrupt has not occurred or has not been started Bit 6 - CRCIF CRC Interrupt Flag bit Value Description 1 CRC interrupt has occurred (must be cleared in software) 0 CRC interrupt has not occurred or has not been started Bit 5 - NVMIF NVM Interrupt Flag bit Value Description 1 NVM interrupt has occurred (must be cleared in software) 0 NVM interrupt has not occurred or has not been started Bit 0 - CWG1IF CWG Interrupt Flag bit Value Description 1 CWG interrupt has occurred (must be cleared in software) 0 CWG interrupt has not occurred or has not been started (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 220 PIC18F26/45/46Q10 Interrupts 14.13.10 PIE0 Name: Address: PIE0 0xEBD Peripheral Interrupt Enable Register 0 Bit 7 6 Access Reset 5 4 2 1 0 TMR0IE IOCIE 3 INT2IE INT1IE INT0IE R/W R/W R/W R/W R/W 0 0 0 0 0 Bit 5 - TMR0IE Timer0 Interrupt Enable bit(1) Value Description 1 Enabled 0 Disabled Bit 4 - IOCIE Interrupt-on-Change Enable bit(1) Value Description 1 Enabled 0 Disabled Bits 0, 1, 2 - INTxIE External Interrupt `x' Enable bit(1) Value Description 1 Enabled 0 Disabled Note: 1. PIR0 interrupts are not disabled by the PEIE bit in the INTCON register. (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 221 PIC18F26/45/46Q10 Interrupts 14.13.11 PIE1 Name: Address: PIE1 0xEBE Peripheral Interrupt Enable Register 1 Bit Access Reset 7 6 1 0 OSCFIE CSWIE 5 4 3 2 ADTIE ADIE R/W R/W R/W R/W 0 0 0 0 Bit 7 - OSCFIE Oscillator Fail Interrupt Enable bit Value Description 1 Enabled 0 Disabled Bit 6 - CSWIE Clock-Switch Interrupt Enable bit Value Description 1 Enabled 0 Disabled Bit 1 - ADTIE ADC Threshold Interrupt Enable bit Value Description 1 Enabled 0 Disabled Bit 0 - ADIE ADC Interrupt Enable bit Value Description 1 Enabled 0 Disabled (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 222 PIC18F26/45/46Q10 Interrupts 14.13.12 PIE2 Name: Address: PIE2 0xEBF Peripheral Interrupt Enable Register 2 Bit Access Reset 7 6 1 0 HLVDIE ZCDIE 5 4 3 2 C2IE C1IE R/W R/W R/W R/W 0 0 0 0 Bit 7 - HLVDIE HLVD Interrupt Enable bit Value Description 1 Enabled 0 Disabled Bit 6 - ZCDIE Zero-Cross Detect Interrupt Enable bit Value Description 1 Enabled 0 Disabled Bits 0, 1 - CxIE Comparator `x' Interrupt Enable bit Value Description 1 Enabled 0 Disabled (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 223 PIC18F26/45/46Q10 Interrupts 14.13.13 PIE3 Name: Address: PIE3 0xEC0 Peripheral Interrupt Enable Register 3 Bit Access Reset 7 6 5 4 3 2 1 0 RC2IE TX2IE RC1IE TX1IE BCL2IE SSP2IE BCL1IE SSP1IE R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Bits 5, 7 - RCxIE EUSARTx Receive Interrupt Enable bit Value Description 1 Enabled 0 Disabled Bits 4, 6 - TXxIE EUSARTx Transmit Interrupt Enable bit Value Description 1 Enabled 0 Disabled Bits 1, 3 - BCLxIE MSSPx Bus Collision Interrupt Enable bit Value Description 1 Enabled 0 Disabled Bits 0, 2 - SSPxIE Synchronous Serial Port `x' Interrupt Enable bit Value Description 1 Enabled 0 Disabled (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 224 PIC18F26/45/46Q10 Interrupts 14.13.14 PIE4 Name: Address: PIE4 0xEC1 Peripheral Interrupt Enable Register 4 Bit 7 6 Access Reset 5 4 3 2 1 0 TMR6IE TMR5IE TMR4IE TMR3IE TMR2IE TMR1IE R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 Bit 5 - TMR6IE TMR6 to PR6 Match Interrupt Enable bit Value Description 1 Enabled 0 Disabled Bit 4 - TMR5IE TMR5 Overflow Interrupt Enable bit Value Description 1 Enabled 0 Disabled Bit 3 - TMR4IE TMR4 to PR4 Match Interrupt Enable bit Value Description 1 Enabled 0 Disabled Bit 2 - TMR3IE TMR3 Overflow Interrupt Enable bit Value Description 1 Enabled 0 Disabled Bit 1 - TMR2IE TMR2 to PR2 Match Interrupt Enable bit Value Description 1 Enabled 0 Disabled Bit 0 - TMR1IE TMR1 Overflow Interrupt Enable bit Value Description 1 Enabled 0 Disabled (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 225 PIC18F26/45/46Q10 Interrupts 14.13.15 PIE5 Name: Address: PIE5 0xEC2 Peripheral Interrupt Enable Register 5 Bit Access Reset 7 6 5 4 2 1 0 CLC4IE CLC3IE CLC2IE CLC1IE 3 TMR5GIE TMR3GIE TMR1GIE R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 Bits 4, 5, 6, 7 - CLCxIE CLCx Interrupt Enable bit Value Description 1 CLCx Interrupt Enabled 0 CLCx Interrupt Disabled Bit 2 - TMR5GIE TMR5 Gate Interrupt Enable bit Value Description 1 Enabled 0 Disabled Bit 1 - TMR3GIE TMR3 Gate Interrupt Enable bit Value Description 1 Enabled 0 Disabled Bit 0 - TMR1GIE TMR1 Gate Interrupt Enable bit Value Description 1 Enabled 0 Disabled (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 226 PIC18F26/45/46Q10 Interrupts 14.13.16 PIE6 Name: Address: PIE6 0xEC3 Peripheral Interrupt Enable Register 6 Bit Access Reset 7 6 5 4 1 0 CLC8IE CLC7IE CLC6IE CLC5IE 3 2 CCP2IE CCP1IE R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 Bits 4, 5, 6, 7 - CLCyIE CLCx Interrupt Enable bit Value Description 1 CLCx Interrupts Enabled 0 CLCx Interrupts Disabled Bit 1 - CCP2IE ECCP2 Interrupt Enable bit Value Description 1 Enabled 0 Disabled Bit 0 - CCP1IE ECCP1 Interrupt Enable bit Value Description 1 Enabled 0 Disabled (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 227 PIC18F26/45/46Q10 Interrupts 14.13.17 PIE7 Name: Address: PIE7 0xEC4 Peripheral Interrupt Enable Register 7 Bit Access Reset 7 6 5 SCANIE CRCIE NVMIE 4 3 2 1 CWG1IE 0 R/W R/W R/W R/W 0 0 0 0 Bit 7 - SCANIE SCAN Interrupt Enable bit Value Description 1 Enabled 0 Disabled Bit 6 - CRCIE CRC Interrupt Enable bit Value Description 1 Enabled 0 Disabled Bit 5 - NVMIE NVM Interrupt Enable bit Value Description 1 Enabled 0 Disabled Bit 0 - CWG1IE CWG Interrupt Enable bit Value Description 1 Enabled 0 Disabled (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 228 PIC18F26/45/46Q10 Interrupts 14.13.18 IPR0 Name: Address: IPR0 0xEB5 Peripheral Interrupt Priority Register 0 Bit 7 6 Access Reset 5 4 2 1 0 TMR0IP IOCIP 3 INT2IP INT1IP INT0IP R/W R/W R/W R/W R/W 1 1 0 0 1 Bit 5 - TMR0IP Timer0 Interrupt Priority bit Value Description 1 High priority 0 Low priority Bit 4 - IOCIP Interrupt-on-Change Priority bit Value Description 1 High priority 0 Low priority Bits 0, 1, 2 - INTxIP External Interrupt `x' Priority bit Value Description 1 High priority 0 Low priority (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 229 PIC18F26/45/46Q10 Interrupts 14.13.19 IPR1 Name: Address: IPR1 0xEB6 Peripheral Interrupt Priority Register 1 Bit Access Reset 7 6 1 0 OSCFIP CSWIP 5 4 3 2 ADTIP ADIP R/W R/W R/W R/W 1 1 1 1 Bit 7 - OSCFIP Oscillator Fail Interrupt Priority bit Value Description 1 High priority 0 Low priority Bit 6 - CSWIP Clock-Switch Interrupt Priority bit Value Description 1 High priority 0 Low priority Bit 1 - ADTIP ADC Threshold Interrupt Priority bit Value Description 1 High priority 0 Low priority Bit 0 - ADIP ADC Interrupt Priority bit Value Description 1 High priority 0 Low priority (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 230 PIC18F26/45/46Q10 Interrupts 14.13.20 IPR2 Name: Address: IPR2 0xEB7 Peripheral Interrupt Priority Register 2 Bit Access Reset 7 6 1 0 HLVDIP ZCDIP 5 4 3 2 C2IP C1IP R/W R/W R/W R/W 1 1 1 1 Bit 7 - HLVDIP HLVD Interrupt Priority bit Value Description 1 High priority 0 Low priority Bit 6 - ZCDIP Zero-Cross Detect Interrupt Priority bit Value Description 1 High priority 0 Low priority Bits 0, 1 - CxIP Comparator `x' Interrupt Priority bit Value Description 1 High priority 0 Low priority (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 231 PIC18F26/45/46Q10 Interrupts 14.13.21 IPR3 Name: Address: IPR3 0xEB8 Peripheral Interrupt Priority Register 3 Bit Access Reset 7 6 5 4 3 2 1 0 RC2IP TX2IP RC1IP TX1IP BCL2IP SSP2IP BCL1IP SSP1IP R/W R/W R/W R/W R/W R/W R/W R/W 0 0 1 1 0 0 1 1 Bits 5, 7 - RCxIP EUSARTx Receive Interrupt Priority bit Value Description 1 High priority 0 Low priority Bits 4, 6 - TXxIP EUSARTx Transmit Interrupt Priority bit Value Description 1 High priority 0 Low priority Bits 1, 3 - BCLxIP MSSPx Bus Collision Interrupt Priority bit Value Description 1 High priority 0 Low priority Bits 0, 2 - SSPxIP Synchronous Serial Port 'x' Interrupt Priority bit Value Description 1 High priority 0 Low priority (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 232 PIC18F26/45/46Q10 Interrupts 14.13.22 IPR4 Name: Address: IPR4 0xEB9 Peripheral Interrupt Priority Register 4 Bit 7 6 Access Reset 5 4 3 2 1 0 TMR6IP TMR5IP TMR4IP TMR3IP TMR2IP TMR1IP R/W R/W R/W R/W R/W R/W 1 1 1 1 1 1 Bit 5 - TMR6IP TMR6 to PR6 Match Interrupt Priority bit Value Description 1 High priority 0 Low priority Bit 4 - TMR5IP TMR5 Overflow Interrupt Priority bit Value Description 1 High priority 0 Low priority Bit 3 - TMR4IP TMR4 to PR4 Match Interrupt Priority bit Value Description 1 High priority 0 Low priority Bit 2 - TMR3IP TMR3 Overflow Interrupt Priority bit Value Description 1 High priority 0 Low priority Bit 1 - TMR2IP TMR2 to PR2 Match Interrupt Priority bit Value Description 1 High priority 0 Low priority Bit 0 - TMR1IP TMR1 Overflow Interrupt Priority bit Value Description 1 High priority 0 Low priority (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 233 PIC18F26/45/46Q10 Interrupts 14.13.23 IPR5 Name: Address: IPR5 0xEBA Peripheral Interrupt Priority Register 5 Bit Access Reset 7 6 5 4 2 1 0 CLC4IP CLC3IP CLC2IP CLC1IP 3 TMR5GIP TMR3GIP TMR1GIP R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 1 1 1 Bits 4, 5, 6, 7 - CLCxIP CLCx Interrupt Priority bit Value Description 1 High priority 0 Low priority Bit 2 - TMR5GIP TMR5 Gate Interrupt Priority bit Value Description 1 High priority 0 Low priority Bit 1 - TMR3GIP TMR3 Gate Interrupt Priority bit Value Description 1 High priority 0 Low priority Bit 0 - TMR1GIP TMR1 Gate Interrupt Priority bit Value Description 1 High priority 0 Low priority (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 234 PIC18F26/45/46Q10 Interrupts 14.13.24 IPR6 Name: Address: IPR6 0xEBB Peripheral Interrupt Priority Register Bit Access Reset 7 6 5 4 1 0 CLC8IP CLC7IP CLC6IP CLC5IP 3 2 CCP2IP CCP1IP R/W R/W R/W R/W R/W R/W 0 0 0 0 1 1 Bits 4, 5, 6, 7 - CLCyIP CLCx Interrupt Priority bit Value Description 1 High priority 0 Low priority Bit 1 - CCP2IP ECCP2 Interrupt Priority bit Value Description 1 High priority 0 Low priority Bit 0 - CCP1IP ECCP1 Interrupt Priority bit Value Description 1 High priority 0 Low priority (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 235 PIC18F26/45/46Q10 Interrupts 14.13.25 IPR7 Name: Address: IPR7 0xEBC Peripheral Interrupt Priority Register Bit Access Reset 7 6 5 SCANIP CRCIP NVMIP 4 3 2 1 CWG1IP 0 R/W R/W R/W R/W 1 1 1 1 Bit 7 - SCANIP SCAN Interrupt Priority bit Value Description 1 High priority 0 Low priority Bit 6 - CRCIP CRC Interrupt Priority bit Value Description 1 High priority 0 Low priority Bit 5 - NVMIP NVM Interrupt Priority bit Value Description 1 High priority 0 Low priority Bit 0 - CWG1IP CWG Interrupt Priority bit Value Description 1 High priority 0 Low priority (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 236 PIC18F26/45/46Q10 I/O Ports 15. I/O Ports Table 15-1. Port Availability per Device Device PORTA PORTB PORTC PIC18F26Q10 PIC18F45/46Q10 PORTD PORTE Each port has eight registers to control the operation. These registers are: * * * * * * * * PORTx registers (reads the levels on the pins of the device) LATx registers (output latch) TRISx registers (data direction) ANSELx registers (analog select) WPUx registers (weak pull-up) INLVLx (input level control) SLRCONx registers (slew rate control) ODCONx registers (open-drain control) Most port pins share functions with device peripherals, both analog and digital. In general, when a peripheral is enabled on a port pin, that pin cannot be used as a general purpose output; however, the pin can still be read. The Data Latch (LATx registers) is useful for read-modify-write operations on the value that the I/O pins are driving. A write operation to the LATx register has the same effect as a write to the corresponding PORTx register. A read of the LATx register reads of the values held in the I/O PORT latches, while a read of the PORTx register reads the actual I/O pin value. Ports that support analog inputs have an associated ANSELx register. When an ANSELx bit is set, the digital input buffer associated with that bit is disabled. Disabling the input buffer prevents analog signal levels on the pin between a logic high and low from causing excessive current in the logic input circuitry. A simplified model of a generic I/O port, without the interfaces to other peripherals, is shown in the following figure: (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 237 PIC18F26/45/46Q10 I/O Ports Figure 15-1. Generic I/O Port Operation Read LATx D Write LATx Write PORTx TRISx Q CK VDD Data Register Data Bus I/O pin Read PORTx To digital peripherals To analog peripherals 15.1 ANSELx VSS I/O Priorities Each pin defaults to the PORT data latch after Reset. Other functions are selected with the peripheral pin select logic. See "Peripheral Pin Select (PPS) Module" for more information. Analog input functions, such as ADC and comparator inputs, are not shown in the peripheral pin select lists. These inputs are active when the I/O pin is set for Analog mode using the ANSELx register. Digital output functions may continue to control the pin when it is in Analog mode. Analog outputs, when enabled, take priority over digital outputs and force the digital output driver into a high-impedance state. The pin function priorities are as follows: 1. 2. 3. 4. Configuration bits Analog outputs (disable the input buffers) Analog inputs Port inputs and outputs from PPS Related Links 17. (PPS) Peripheral Pin Select Module 15.2 PORTx Registers In this section the generic names such as PORTx, LATx, TRISx, etc. can be associated with all ports. For availability of PORTD refer to Table 15-1. The functionality of PORTE is different compared to other ports and is explained in a separate section. (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 238 PIC18F26/45/46Q10 I/O Ports 15.2.1 Data Register PORTx is an 8-bit wide, bidirectional port. The corresponding data direction register is TRISx. Setting a TRISx bit (`1') will make the corresponding PORTA pin an input (i.e., disable the output driver). Clearing a TRISx bit (`0') will make the corresponding PORTx pin an output (i.e., it enables output driver and puts the contents of the output latch on the selected pin). Example 15-1 shows how to initialize PORTA. Reading the PORTx register reads the status of the pins, whereas writing to it will write to the PORT latch. All write operations are read-modify-write operations. Therefore, a write to a port implies that the port pins are read, this value is modified and then written to the PORT data latch (LATx). The PORT data latch LATx holds the output port data and contains the latest value of a LATx or PORTx write. Example 15-1. EXAMPLE-1: Initializing PORTA ; This code example illustrates initializing the PORTA register. ; The other ports are initialized in the same manner. CLRF LATA ; Set all output bits to zero MOVLW B'11111000' ; Set RA<7:3> as inputs and RA<2:0> as outputs MOVWF TRISA ; BANKSEL ANSELA CLRF ANSELA ; All pins are digital I/O 15.2.2 Direction Control The TRISx register controls the PORTx pin output drivers, even when they are being used as analog inputs. The user should ensure the bits in the TRISx register are maintained set when using them as analog inputs. I/O pins configured as analog inputs always read `0'. Related Links 15.5.6 TRISA 15.5.7 TRISB 15.5.8 TRISC 15.5.9 TRISD 15.5.10 TRISE 15.2.3 Analog Control The ANSELx register is used to configure the Input mode of an I/O pin to analog. Setting the appropriate ANSELx bit high will cause all digital reads on the pin to be read as `0' and allow analog functions on the pin to operate correctly. The state of the ANSELx bits has no effect on digital output functions. A pin with TRIS clear and ANSEL set will still operate as a digital output, but the Input mode will be analog. This can cause unexpected behavior when executing READ-MODIFY-WRITE instructions on the affected port. Important: The ANSELx bits default to the Analog mode after Reset. To use any pins as digital general purpose or peripheral inputs, the corresponding ANSEL bits must be initialized to `0' by user software. Related Links 15.5.16 ANSELA 15.5.17 ANSELB (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 239 PIC18F26/45/46Q10 I/O Ports 15.5.19 ANSELD 15.5.20 ANSELE 15.2.4 Open-Drain Control The ODCONx register controls the open-drain feature of the port. Open-drain operation is independently selected for each pin. When an ODCONx bit is set, the corresponding port output becomes an open-drain driver capable of sinking current only. When an ODCONx bit is cleared, the corresponding port output pin is the standard push-pull drive capable of sourcing and sinking current. Important: It is not necessary to set open-drain control when using the pin for I2C; the I2C module controls the pin and makes the pin open-drain. Related Links 15.5.26 ODCONA 15.5.27 ODCONB 15.5.28 ODCONC 15.5.29 ODCOND 15.5.30 ODCONE 15.2.5 Slew Rate Control The SLRCONx register controls the slew rate option for each port pin. Slew rate for each port pin can be controlled independently. When an SLRCONx bit is set, the corresponding port pin drive is slew rate limited. When an SLRCONx bit is cleared, The corresponding port pin drive slews at the maximum rate possible. Related Links 15.5.31 SLRCONA 15.5.32 SLRCONB 15.5.33 SLRCONC 15.5.34 SLRCOND 15.5.35 SLRCONE 15.2.6 Input Threshold Control The INLVLx register controls the input voltage threshold for each of the available PORTx input pins. A selection between the Schmitt Trigger CMOS or the TTL compatible thresholds is available. The input threshold is important in determining the value of a read of the PORTx register and also the level at which an interrupt-on-change occurs, if that feature is enabled. See link below for more information on threshold levels. Important: Changing the input threshold selection should be performed while all peripheral modules are disabled. Changing the threshold level during the time a module is active may inadvertently generate a transition associated with an input pin, regardless of the actual voltage level on that pin. Related Links 15.5.36 INLVLA (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 240 PIC18F26/45/46Q10 I/O Ports 15.5.37 15.5.38 15.5.39 15.5.40 15.2.7 INLVLB INLVLC INLVLD INLVLE Weak Pull-up Control The WPUx register controls the individual weak pull-ups for each port pin. Related Links 15.5.21 WPUA 15.5.22 WPUB 15.5.23 WPUC 15.5.24 WPUD 15.5.25 WPUE 15.2.8 Edge Selectable Interrupt-on-Change An interrupt can be generated by detecting a signal at the port pin that has either a rising edge or a falling edge. Individual pins can be independently configured to generate an interrupt. The interrupt-on-change module is present on all the pins that are common between 28-pin and 40/44-pin devices. For further details about the IOC module, refer to "Interrupt-on-Change" chapter. Related Links 16. Interrupt-on-Change 15.3 PORTE Registers Depending on the device selected, PORTE is implemented in two different ways. 15.3.1 PORTE on 40/44-Pin Devices For 40/44-pin devices, PORTE is a 4-bit wide port. Three pins (RE0, RE1 and RE2) are individually configurable as inputs or outputs. These pins have Schmitt Trigger input buffers. When selected as an analog input, these pins will read as `0's. The corresponding data direction register is TRISE. Setting a TRISE bit (= 1) will make the corresponding PORTE pin an input (i.e., disable the output driver). Clearing a TRISE bit (= 0) will make the corresponding PORTE pin an output (i.e., enable the output driver and put the contents of the output latch on the selected pin). TRISE controls the direction of the REx pins, even when they are being used as analog pins. The user must make sure to keep the pins configured as inputs when using them as analog inputs. RE<2:0> bits have other registers associated with them (i.e., ANSELE, WPUE, INLVLE, SLRCONE and ODCONE). The functionality is similar to the other ports. The Data Latch register (LATE) is also memory-mapped. Read-modify-write operations on the LATE register read and write the latched output value for PORTE. Important: On a Power-on Reset, RE<2:0> are configured as analog inputs. (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 241 PIC18F26/45/46Q10 I/O Ports The fourth pin of PORTE (MCLR/VPP/RE3) is an input-only pin. Its operation is controlled by the MCLRE Configuration bit. When selected as a port pin (MCLRE = 0), it functions as a digital input-only pin; as such, it does not have TRIS or LAT bits associated with its operation. Otherwise, it functions as the device's Master Clear input. In either configuration, RE3 also functions as the programming voltage input during programming. RE3 in PORTE register is a read-only bit and will read `1' when MCLRE = 1 (i.e., Master Clear enabled). Important: On a Power-on Reset, RE3 is enabled as a digital input-only if Master Clear functionality is disabled. Example 15-2. EXAMPLE-2: Initializing PORTE CLRF PORTE CLRF LATE CLRF ANSELE MOVLW 05h MOVWF TRISE ; ; ; ; ; ; ; ; ; ; ; ; Initialize PORTE by clearing output data latches Alternate method to clear output data latches ; Configure analog pins for digital only Value used to initialize data direction ; Set RE<0> as input RE<1> as output RE<2> as input 15.3.2 PORTE on 28-Pin Devices For 28-pin devices, PORTE is only available when Master Clear functionality is disabled (MCLRE = 0). In this case, PORTE is a single bit, input-only port comprised of RE3 only. The pin operates as previously described. RE3 in PORTE register is a read-only bit and will read `1' when MCLRE = 1 (i.e., Master Clear enabled). 15.3.3 RE3 Weak Pull-Up The port RE3 pin has an individually controlled weak internal pull-up. When set, the WPUE3 bit enables the RE3 pin pull-up. When the RE3 port pin is configured as MCLR, (CONFIG2L, MCLRE = 1 and CONFIG4H, LVP = 0), or configured for Low-Voltage Programming, (MCLRE = x and LVP = 1), the pullup is always enabled and the WPUE3 bit has no effect. 15.3.4 PORTE Interrupt-on-Change The interrupt-on-change feature is available only on the RE3 pin for all devices. Related Links 16. Interrupt-on-Change (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 242 PIC18F26/45/46Q10 I/O Ports 15.4 Register Summary - Input/Output Address Name Bit Pos. 0x0F08 INLVLA 7:0 0x0F09 SLRCONA 7:0 SLRA7 SLRA6 SLRA5 SLRA4 SLRA3 SLRA2 SLRA1 SLRA0 0x0F0A ODCONA 7:0 ODCA7 ODCA6 ODCA5 ODCA4 ODCA3 ODCA2 ODCA1 ODCA0 0x0F0B WPUA 7:0 WPUA7 WPUA6 WPUA5 WPUA4 WPUA3 WPUA2 WPUA1 WPUA0 0x0F0C ANSELA 7:0 ANSELA7 ANSELA6 ANSELA5 ANSELA4 ANSELA3 ANSELA2 ANSELA1 ANSELA0 INLVLB7 INLVLB6 INLVLB5 INLVLB4 INLVLB3 INLVLB2 INLVLB1 INLVLB0 INLVLA7 INLVLA6 INLVLA5 INLVLA4 INLVLA3 INLVLA2 INLVLA1 INLVLA0 0x0F0D ... Reserved 0x0F0F 0x0F10 INLVLB 7:0 0x0F11 SLRCONB 7:0 SLRB7 SLRB6 SLRB5 SLRB4 SLRB3 SLRB2 SLRB1 SLRB0 0x0F12 ODCONB 7:0 ODCB7 ODCB6 ODCB5 ODCB4 ODCB3 ODCB2 ODCB1 ODCB0 0x0F13 WPUB 7:0 WPUB7 WPUB6 WPUB5 WPUB4 WPUB3 WPUB2 WPUB1 WPUB0 0x0F14 ANSELB 7:0 ANSELB7 ANSELB6 ANSELB5 ANSELB4 ANSELB3 ANSELB2 ANSELB1 ANSELB0 0x0F15 ... Reserved 0x0F17 0x0F18 INLVLC 7:0 INLVLC7 INLVLC6 INLVLC5 INLVLC4 INLVLC3 INLVLC2 INLVLC1 INLVLC0 0x0F19 SLRCONC 7:0 SLRC7 SLRC6 SLRC5 SLRC4 SLRC3 SLRC2 SLRC1 SLRC0 0x0F1A ODCONC 7:0 ODCC7 ODCC6 ODCC5 ODCC4 ODCC3 ODCC2 ODCC1 ODCC0 0x0F1B WPUC 7:0 WPUC7 WPUC6 WPUC5 WPUC4 WPUC3 WPUC2 WPUC1 WPUC0 0x0F1C ANSELC 7:0 ANSELC7 ANSELC6 ANSELC5 ANSELC4 ANSELC3 ANSELC2 ANSELC1 ANSELC0 0x0F1D INLVLD 7:0 INLVLD7 INLVLD6 INLVLD5 INLVLD4 INLVLD3 INLVLD2 INLVLD1 INLVLD0 0x0F1E SLRCOND 7:0 SLRD7 SLRD6 SLRD5 SLRD4 SLRD3 SLRD2 SLRD1 SLRD0 0x0F1F ODCOND 7:0 ODCD7 ODCD6 ODCD5 ODCD4 ODCD3 ODCD2 ODCD1 ODCD0 0x0F20 WPUD 7:0 WPUD7 WPUD6 WPUD5 WPUD4 WPUD3 WPUD2 WPUD1 WPUD0 0x0F21 ANSELD 7:0 ANSELD7 ANSELD6 ANSELD5 ANSELD4 ANSELD3 ANSELD2 ANSELD1 ANSELD0 INLVLE3 INLVLE0 0x0F22 ... Reserved 0x0F24 0x0F25 INLVLE 7:0 INLVLE2 INLVLE1 0x0F26 SLRCONE 7:0 SLRE2 SLRE1 SLRE0 0x0F27 ODCONE 7:0 ODCE2 ODCE1 ODCE0 0x0F28 WPUE 7:0 0x0F29 ANSELE 7:0 WPUE3 WPUE2 WPUE1 WPUE0 ANSELE2 ANSELE1 ANSELE0 LATA2 LATA1 LATA0 0x0F2A ... Reserved 0x0F81 0x0F82 LATA 7:0 LATA7 0x0F83 LATB 7:0 LATB7 LATB6 LATB5 LATB4 LATB3 LATB2 LATB1 LATB0 0x0F84 LATC 7:0 LATC7 LATC6 LATC5 LATC4 LATC3 LATC2 LATC1 LATC0 0x0F85 LATD 7:0 LATD7 LATD6 LATD5 LATD4 LATD3 LATD2 LATD1 LATD0 0x0F86 LATE 7:0 LATE2 LATE1 LATE0 0x0F87 TRISA 7:0 TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 0x0F88 TRISB 7:0 TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 (c) 2019 Microchip Technology Inc. LATA6 LATA5 LATA4 LATA3 Datasheet Preliminary DS40001996C-page 243 PIC18F26/45/46Q10 I/O Ports ...........continued Address Name Bit Pos. 0x0F89 TRISC 7:0 TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 0x0F8A TRISD 7:0 TRISD7 TRISD6 TRISD5 TRISD4 TRISD3 TRISD2 TRISD1 TRISD0 0x0F8B TRISE 7:0 TRISE3 TRISE2 TRISE1 TRISE0 0x0F8C PORTA 7:0 RA7 RA6 RA5 RA4 RA3 RA2 RA1 RA0 0x0F8D PORTB 7:0 RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 0x0F8E PORTC 7:0 RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 0x0F8F PORTD 7:0 RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0 0x0F90 PORTE 7:0 RE3 RE2 RE1 RE0 15.5 Register Definitions: Port Control (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 244 PIC18F26/45/46Q10 I/O Ports 15.5.1 PORTA Name: Address: PORTA 0xF8C PORTA Register Note: Writes to PORTA are actually written to the corresponding LATA register. Reads from PORTA register return actual I/O pin values. Bit Access Reset 7 6 5 4 3 2 1 0 RA7 RA6 RA5 RA4 RA3 RA2 RA1 RA0 R/W R/W R/W R/W R/W R/W R/W R/W x x x x x x x x Bits 0, 1, 2, 3, 4, 5, 6, 7 - RAn Port I/O Value bits Reset States: POR/BOR = xxxxxxxx All Other Resets = uuuuuuuu Value Description 1 Port pin is VIH 0 Port pin is VIL (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 245 PIC18F26/45/46Q10 I/O Ports 15.5.2 PORTB Name: Address: PORTB 0xF8D PORTB Register Bit Access Reset 7 6 5 4 3 2 1 0 RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 R/W R/W R/W R/W R/W R/W R/W R/W x x x x x x x x Bits 0, 1, 2, 3, 4, 5, 6, 7 - RBn Port I/O Value bits Note: Bits RB6 and RB7 read `1' while in Debug mode. Reset States: POR/BOR = xxxxxxxx All Other Resets = uuuuuuuu Value Description 1 Port pin is VIH 0 Port pin is VIL Note: Writes to PORTB are actually written to the corresponding LATB register. Reads from PORTB register return actual I/O pin values. (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 246 PIC18F26/45/46Q10 I/O Ports 15.5.3 PORTC Name: Address: PORTC 0xF8E PORTC Register Bit Access Reset 7 6 5 4 3 2 1 0 RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 R/W R/W R/W R/W R/W R/W R/W R/W x x x x x x x x Bits 0, 1, 2, 3, 4, 5, 6, 7 - RCn Port I/O Value bits Reset States: POR/BOR = xxxxxxxx All Other Resets = uuuuuuuu Value Description 1 Port pin is VIH 0 Port pin is VIL Note: Writes to PORTC are actually written to the corresponding LATC register. Reads from PORTC register return actual I/O pin values. (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 247 PIC18F26/45/46Q10 I/O Ports 15.5.4 PORTD Name: Address: PORTD 0xF8F PORTD Register Bit Access Reset 7 6 5 4 3 2 1 0 RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0 R/W R/W R/W R/W R/W R/W R/W R/W x x x x x x x x Bits 0, 1, 2, 3, 4, 5, 6, 7 - RDn Port I/O Value bits Reset States: POR/BOR = xxxxxxxx All Other Resets = uuuuuuuu Value Description 1 Port pin is VIH 0 Port pin is VIL Note: Writes to PORTD are actually written to the corresponding LATD register. Reads from PORTD register return actual I/O pin values. (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 248 PIC18F26/45/46Q10 I/O Ports 15.5.5 PORTE Name: Address: PORTE 0xF90 PORTE Register Note: Writes to PORTE are actually written to the corresponding LATE register. Reads from PORTE register return actual I/O pin values. Bit 7 6 5 Access Reset 4 3 2 1 0 RE3 RE2 RE1 RE0 R/W R/W R/W R/W x x x x Bits 0, 1, 2, 3 - REn Port I/O Value bits Note: 1. Bit RE3 is read-only, and will read `1' when MCLRE = 1 (Master Clear enabled). 2. 28-pin package only has RE3 in this register. Reset States: POR/BOR = xxxx All Other Resets = uuuu Value Description 1 Port pin is VIH 0 Port pin is VIL (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 249 PIC18F26/45/46Q10 I/O Ports 15.5.6 TRISA Name: Address: TRISA 0xF87 Tri-State Control Register Bit Access Reset 7 6 5 4 3 2 1 0 TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 R/W R/W R/W R/W R/W R/W R/W R/W 1 1 1 1 1 1 1 1 Bits 0, 1, 2, 3, 4, 5, 6, 7 - TRISAn TRISA Port I/O Tri-state Control bits Value Description 1 Port output driver is disabled 0 Port output driver is enabled (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 250 PIC18F26/45/46Q10 I/O Ports 15.5.7 TRISB Name: Address: TRISB 0xF88 Tri-State Control Register Bit Access Reset 7 6 5 4 3 2 1 0 TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 R/W R/W R/W R/W R/W R/W R/W R/W 1 1 1 1 1 1 1 1 Bits 0, 1, 2, 3, 4, 5, 6, 7 - TRISBn TRISB Port I/O Tri-state Control bits Note: Bits TRISB6 and TRISB7 read `1' while in Debug mode. Value 1 0 Description Port output driver is disabled Port output driver is enabled (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 251 PIC18F26/45/46Q10 I/O Ports 15.5.8 TRISC Name: Address: TRISC 0xF89 Tri-State Control Register Bit Access Reset 7 6 5 4 3 2 1 0 TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 R/W R/W R/W R/W R/W R/W R/W R/W 1 1 1 1 1 1 1 1 Bits 0, 1, 2, 3, 4, 5, 6, 7 - TRISCn TRISC Port I/O Tri-state Control bits Value Description 1 Port output driver is disabled 0 Port output driver is enabled (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 252 PIC18F26/45/46Q10 I/O Ports 15.5.9 TRISD Name: Address: TRISD 0xF8A Tri-State Control Register Bit Access Reset 7 6 5 4 3 2 1 0 TRISD7 TRISD6 TRISD5 TRISD4 TRISD3 TRISD2 TRISD1 TRISD0 R/W R/W R/W R/W R/W R/W R/W R/W 1 1 1 1 1 1 1 1 Bits 0, 1, 2, 3, 4, 5, 6, 7 - TRISDn TRISD Port I/O Tri-state Control bits Value Description 1 Port output driver is disabled 0 Port output driver is enabled (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 253 PIC18F26/45/46Q10 I/O Ports 15.5.10 TRISE Name: Address: TRISE 0xF8B Tri-State Control Register Bit 7 6 5 4 Access Reset 3 2 1 0 TRISE3 TRISE2 TRISE1 TRISE0 R/W R/W R/W R/W 1 1 1 1 Bits 0, 1, 2, 3 - TRISEn PortE I/O Tri-state Control bits Note: 1. Not available on 28-pin devices. 2. TRISE3 bit is read-only, and will read `1'. Value 1 0 Description Port output driver is disabled Port output driver is enabled (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 254 PIC18F26/45/46Q10 I/O Ports 15.5.11 LATA Name: Address: LATA 0xF82 Output Latch Register Bit Access Reset 7 6 5 4 3 2 1 0 LATA7 LATA6 LATA5 LATA4 LATA3 LATA2 LATA1 LATA0 R/W R/W R/W R/W R/W R/W R/W R/W x x x x x x x x Bits 0, 1, 2, 3, 4, 5, 6, 7 - LATAn Output Latch A Value bits Reset States: POR/BOR = xxxxxxxx All Other Resets = uuuuuuuuu Note: Writes to LATA are equivalent with writes to the corresponding PORTA register. Reads from LATA register return register values, not I/O pin values. (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 255 PIC18F26/45/46Q10 I/O Ports 15.5.12 LATB Name: Address: LATB 0xF83 Output Latch Register Bit Access Reset 7 6 5 4 3 2 1 0 LATB7 LATB6 LATB5 LATB4 LATB3 LATB2 LATB1 LATB0 R/W R/W R/W R/W R/W R/W R/W R/W x x x x x x x x Bits 0, 1, 2, 3, 4, 5, 6, 7 - LATBn Output Latch B Value bits Reset States: POR/BOR = xxxxxxxx All Other Resets = uuuuuuuuu Note: Writes to LATB are equivalent with writes to the corresponding PORTB register. Reads from LATB register return register values, not I/O pin values. (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 256 PIC18F26/45/46Q10 I/O Ports 15.5.13 LATC Name: Address: LATC 0xF84 Output Latch Register Bit Access Reset 7 6 5 4 3 2 1 0 LATC7 LATC6 LATC5 LATC4 LATC3 LATC2 LATC1 LATC0 R/W R/W R/W R/W R/W R/W R/W R/W x x x x x x x x Bits 0, 1, 2, 3, 4, 5, 6, 7 - LATCn Output Latch C Value bits Reset States: POR/BOR = xxxxxxxx All Other Resets = uuuuuuuuu Note: Writes to LATC are equivalent with writes to the corresponding PORTC register. Reads from LATC register return register values, not I/O pin values. (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 257 PIC18F26/45/46Q10 I/O Ports 15.5.14 LATD Name: Address: LATD 0xF85 Output Latch Register Bit Access Reset 7 6 5 4 3 2 1 0 LATD7 LATD6 LATD5 LATD4 LATD3 LATD2 LATD1 LATD0 R/W R/W R/W R/W R/W R/W R/W R/W x x x x x x x x Bits 0, 1, 2, 3, 4, 5, 6, 7 - LATDn Output Latch D Value bits Reset States: POR/BOR = xxxxxxxx All Other Resets = uuuuuuuuu Note: Writes to LATD are equivalent with writes to the corresponding PORTD register. Reads from LATD register return register values, not I/O pin values. (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 258 PIC18F26/45/46Q10 I/O Ports 15.5.15 LATE Name: Address: LATE 0xF86 Output Latch Register Bit 7 6 5 4 3 Access Reset 2 1 0 LATE2 LATE1 LATE0 R/W R/W R/W x x x Bits 0, 1, 2 - LATEn Output Latch E Value bits Reset States: POR/BOR = xxx All Other Resets = uuu Note: Writes to LATE are equivalent with writes to the corresponding PORTE register. Reads from LATE register return register values, not I/O pin values. (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 259 PIC18F26/45/46Q10 I/O Ports 15.5.16 ANSELA Name: Address: ANSELA 0xF0C Analog Select Register Bit Access Reset 7 6 5 4 3 2 1 0 ANSELA7 ANSELA6 ANSELA5 ANSELA4 ANSELA3 ANSELA2 ANSELA1 ANSELA0 R/W R/W R/W R/W R/W R/W R/W R/W 1 1 1 1 1 1 1 1 Bits 0, 1, 2, 3, 4, 5, 6, 7 - ANSELAn Analog Select on Pins RA<7:0> Value Description 1 Digital Input buffers are disabled 0 ST and TTL input buffers are enabled (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 260 PIC18F26/45/46Q10 I/O Ports 15.5.17 ANSELB Name: Address: Reset: ANSELB 0xF14 0x00 Analog Select Register Bit Access Reset 7 6 5 4 3 2 1 0 ANSELB7 ANSELB6 ANSELB5 ANSELB4 ANSELB3 ANSELB2 ANSELB1 ANSELB0 R/W R/W R/W R/W R/W R/W R/W R/W 1 1 1 1 1 1 1 1 Bits 0, 1, 2, 3, 4, 5, 6, 7 - ANSELBn Analog Select on Pins RB<7:0> Value Description 1 Digital Input buffers are disabled 0 ST and TTL input buffers are enabled (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 261 PIC18F26/45/46Q10 I/O Ports 15.5.18 ANSELC Name: Address: ANSELC 0xF1C Analog Select Register Bit Access Reset 7 6 5 4 3 2 1 0 ANSELC7 ANSELC6 ANSELC5 ANSELC4 ANSELC3 ANSELC2 ANSELC1 ANSELC0 R/W R/W R/W R/W R/W R/W R/W R/W 1 1 1 1 1 1 1 1 Bits 0, 1, 2, 3, 4, 5, 6, 7 - ANSELCn Analog Select on Pins RC<7:0> Value Description 1 Digital Input buffers are disabled 0 ST and TTL input buffers are enabled (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 262 PIC18F26/45/46Q10 I/O Ports 15.5.19 ANSELD Name: Address: ANSELD 0xF21 Analog Select Register Bit Access Reset 7 6 5 4 3 2 1 0 ANSELD7 ANSELD6 ANSELD5 ANSELD4 ANSELD3 ANSELD2 ANSELD1 ANSELD0 R/W R/W R/W R/W R/W R/W R/W R/W 1 1 1 1 1 1 1 1 Bits 0, 1, 2, 3, 4, 5, 6, 7 - ANSELDn Analog Select on Pins RD<7:0> Value Description 1 Digital Input buffers are disabled 0 ST and TTL input buffers are enabled (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 263 PIC18F26/45/46Q10 I/O Ports 15.5.20 ANSELE Name: Address: ANSELE 0xF29 Analog Select Register Bit 7 6 5 4 3 Access Reset 2 1 0 ANSELE2 ANSELE1 ANSELE0 R/W R/W R/W 1 1 1 Bits 0, 1, 2 - ANSELEn Analog Select on Pins RE<7:0> Value Description 1 Digital Input buffers are disabled 0 ST and TTL input buffers are enabled (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 264 PIC18F26/45/46Q10 I/O Ports 15.5.21 WPUA Name: Address: WPUA 0xF0B Weak Pull-up Register Bit Access Reset 7 6 5 4 3 2 1 0 WPUA7 WPUA6 WPUA5 WPUA4 WPUA3 WPUA2 WPUA1 WPUA0 R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Bits 0, 1, 2, 3, 4, 5, 6, 7 - WPUAn Weak Pull-up PORTA Control bits Value Description 1 Weak Pull-up enabled 0 Weak Pull-up disabled (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 265 PIC18F26/45/46Q10 I/O Ports 15.5.22 WPUB Name: Address: WPUB 0xF13 Weak Pull-up Register Bit Access Reset 7 6 5 4 3 2 1 0 WPUB7 WPUB6 WPUB5 WPUB4 WPUB3 WPUB2 WPUB1 WPUB0 R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Bits 0, 1, 2, 3, 4, 5, 6, 7 - WPUBn Weak Pull-up PORTA Control bits Value Description 1 Weak Pull-up enabled 0 Weak Pull-up disabled (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 266 PIC18F26/45/46Q10 I/O Ports 15.5.23 WPUC Name: Address: WPUC 0xF1B Weak Pull-up Register Bit Access Reset 7 6 5 4 3 2 1 0 WPUC7 WPUC6 WPUC5 WPUC4 WPUC3 WPUC2 WPUC1 WPUC0 R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Bits 0, 1, 2, 3, 4, 5, 6, 7 - WPUCn Weak Pull-up PORTC Control bits Value Description 1 Weak Pull-up enabled 0 Weak Pull-up disabled (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 267 PIC18F26/45/46Q10 I/O Ports 15.5.24 WPUD Name: Address: WPUD 0xF20 Weak Pull-up Register Bit Access Reset 7 6 5 4 3 2 1 0 WPUD7 WPUD6 WPUD5 WPUD4 WPUD3 WPUD2 WPUD1 WPUD0 R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Bits 0, 1, 2, 3, 4, 5, 6, 7 - WPUDn Weak Pull-up PORTD Control bits Value Description 1 Weak Pull-up enabled 0 Weak Pull-up disabled (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 268 PIC18F26/45/46Q10 I/O Ports 15.5.25 WPUE Name: Address: WPUE 0xF28 Weak Pull-up Register Bit 7 6 5 Access Reset 4 3 2 1 0 WPUE3 WPUE2 WPUE1 WPUE0 R/W R/W R/W R/W 0 0 0 0 Bits 0, 1, 2, 3 - WPUEn Weak Pull-up PORTE Control bits Note: 1. If MCLRE = 1, the weak pull-up in RE3 is always enabled; bit WPUE3 is not affected. 2. 28-pin package only has WPUE3 bit. Value 1 0 Description Weak Pull-up enabled Weak Pull-up disabled (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 269 PIC18F26/45/46Q10 I/O Ports 15.5.26 ODCONA Name: Address: ODCONA 0xF0A Open-Drain Control Register Bit Access Reset 7 6 5 4 3 2 1 0 ODCA7 ODCA6 ODCA5 ODCA4 ODCA3 ODCA2 ODCA1 ODCA0 R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Bits 0, 1, 2, 3, 4, 5, 6, 7 - ODCAn Open-Drain Configuration on Pins Rx<7:0> Value Description 1 Output drives only low-going signals (sink current only) 0 Output drives both high-going and low-going signals (source and sink current) (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 270 PIC18F26/45/46Q10 I/O Ports 15.5.27 ODCONB Name: Address: ODCONB 0xF12 Open-Drain Control Register Bit Access Reset 7 6 5 4 3 2 1 0 ODCB7 ODCB6 ODCB5 ODCB4 ODCB3 ODCB2 ODCB1 ODCB0 R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Bits 0, 1, 2, 3, 4, 5, 6, 7 - ODCBn Open-Drain Configuration on Pins Rx<7:0> Value Description 1 Output drives only low-going signals (sink current only) 0 Output drives both high-going and low-going signals (source and sink current) (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 271 PIC18F26/45/46Q10 I/O Ports 15.5.28 ODCONC Name: Address: ODCONC 0xF1A Open-Drain Control Register Bit Access Reset 7 6 5 4 3 2 1 0 ODCC7 ODCC6 ODCC5 ODCC4 ODCC3 ODCC2 ODCC1 ODCC0 R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Bits 0, 1, 2, 3, 4, 5, 6, 7 - ODCCn Open-Drain Configuration on Pins Rx<7:0> Value Description 1 Output drives only low-going signals (sink current only) 0 Output drives both high-going and low-going signals (source and sink current) (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 272 PIC18F26/45/46Q10 I/O Ports 15.5.29 ODCOND Name: Address: ODCOND 0xF1F Open-Drain Control Register Bit Access Reset 7 6 5 4 3 2 1 0 ODCD7 ODCD6 ODCD5 ODCD4 ODCD3 ODCD2 ODCD1 ODCD0 R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Bits 0, 1, 2, 3, 4, 5, 6, 7 - ODCDn Open-Drain Configuration on Pins Rx<7:0> Value Description 1 Output drives only low-going signals (sink current only) 0 Output drives both high-going and low-going signals (source and sink current) (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 273 PIC18F26/45/46Q10 I/O Ports 15.5.30 ODCONE Name: Address: ODCONE 0xF27 Open-Drain Control Register Bit 7 6 5 4 3 Access Reset 2 1 0 ODCE2 ODCE1 ODCE0 R/W R/W R/W 0 0 0 Bits 0, 1, 2 - ODCEn Open-Drain Configuration on Pins Rx<7:0> Value Description 1 Output drives only low-going signals (sink current only) 0 Output drives both high-going and low-going signals (source and sink current) (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 274 PIC18F26/45/46Q10 I/O Ports 15.5.31 SLRCONA Name: Address: SLRCONA 0xF09 Slew Rate Control Register Bit Access Reset 7 6 5 4 3 2 1 0 SLRA7 SLRA6 SLRA5 SLRA4 SLRA3 SLRA2 SLRA1 SLRA0 R/W R/W R/W R/W R/W R/W R/W R/W 1 1 1 1 1 1 1 1 Bits 0, 1, 2, 3, 4, 5, 6, 7 - SLRAn Slew Rate Control on Pins Rx<7:0>, respectively Value Description 1 Port pin slew rate is limited 0 Port pin slews at maximum rate (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 275 PIC18F26/45/46Q10 I/O Ports 15.5.32 SLRCONB Name: Address: SLRCONB 0xF11 Slew Rate Control Register Bit Access Reset 7 6 5 4 3 2 1 0 SLRB7 SLRB6 SLRB5 SLRB4 SLRB3 SLRB2 SLRB1 SLRB0 R/W R/W R/W R/W R/W R/W R/W R/W 1 1 1 1 1 1 1 1 Bits 0, 1, 2, 3, 4, 5, 6, 7 - SLRBn Slew Rate Control on Pins Rx<7:0>, respectively Value Description 1 Port pin slew rate is limited 0 Port pin slews at maximum rate (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 276 PIC18F26/45/46Q10 I/O Ports 15.5.33 SLRCONC Name: Address: SLRCONC 0xF19 Slew Rate Control Register Bit Access Reset 7 6 5 4 3 2 1 0 SLRC7 SLRC6 SLRC5 SLRC4 SLRC3 SLRC2 SLRC1 SLRC0 R/W R/W R/W R/W R/W R/W R/W R/W 1 1 1 1 1 1 1 1 Bits 0, 1, 2, 3, 4, 5, 6, 7 - SLRCn Slew Rate Control on Pins Rx<7:0>, respectively Value Description 1 Port pin slew rate is limited 0 Port pin slews at maximum rate (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 277 PIC18F26/45/46Q10 I/O Ports 15.5.34 SLRCOND Name: Address: SLRCOND 0xF1E Slew Rate Control Register Bit Access Reset 7 6 5 4 3 2 1 0 SLRD7 SLRD6 SLRD5 SLRD4 SLRD3 SLRD2 SLRD1 SLRD0 R/W R/W R/W R/W R/W R/W R/W R/W 1 1 1 1 1 1 1 1 Bits 0, 1, 2, 3, 4, 5, 6, 7 - SLRDn Slew Rate Control on Pins Rx<7:0>, respectively Value Description 1 Port pin slew rate is limited 0 Port pin slews at maximum rate (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 278 PIC18F26/45/46Q10 I/O Ports 15.5.35 SLRCONE Name: Address: SLRCONE 0xF26 Slew Rate Control Register Bit 7 6 5 4 3 Access 2 1 0 SLRE2 SLRE1 SLRE0 R/W R/W R/W 1 1 1 Reset Bits 0, 1, 2 - SLREn Slew Rate Control on Pins Rx<7:0>, respectively Value Description 1 Port pin slew rate is limited 0 Port pin slews at maximum rate (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 279 PIC18F26/45/46Q10 I/O Ports 15.5.36 INLVLA Name: Address: INLVLA 0xF08 Input Level Control Register Bit Access Reset 7 6 5 4 3 2 1 0 INLVLA7 INLVLA6 INLVLA5 INLVLA4 INLVLA3 INLVLA2 INLVLA1 INLVLA0 R/W R/W R/W R/W R/W R/W R/W R/W 1 1 1 1 1 1 1 1 Bits 0, 1, 2, 3, 4, 5, 6, 7 - INLVLAn Input Level Select on Pins Rx<7:0>, respectively Value Description 1 ST input used for port reads and interrupt-on-change 0 TTL input used for port reads and interrupt-on-change (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 280 PIC18F26/45/46Q10 I/O Ports 15.5.37 INLVLB Name: Address: INLVLB 0xF10 Input Level Control Register Bit Access Reset 7 6 5 4 3 2 1 0 INLVLB7 INLVLB6 INLVLB5 INLVLB4 INLVLB3 INLVLB2 INLVLB1 INLVLB0 R/W R/W R/W R/W R/W R/W R/W R/W 1 1 1 1 1 1 1 1 Bits 0, 1, 2, 3, 4, 5, 6, 7 - INLVLBn Input Level Select on Pins Rx<7:0>, respectively Note: INLVLB2 / INLVLB1: Pins read the I2C ST inputs when MSSP inputs select these pins, and I2C mode is enabled. Value 1 0 Description ST input used for port reads and interrupt-on-change TTL input used for port reads and interrupt-on-change (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 281 PIC18F26/45/46Q10 I/O Ports 15.5.38 INLVLC Name: Address: INLVLC 0xF18 Input Level Control Register Bit Access Reset 7 6 5 4 3 2 1 0 INLVLC7 INLVLC6 INLVLC5 INLVLC4 INLVLC3 INLVLC2 INLVLC1 INLVLC0 R/W R/W R/W R/W R/W R/W R/W R/W 1 1 1 1 1 1 1 1 Bits 0, 1, 2, 3, 4, 5, 6, 7 - INLVLCn Input Level Select on Pins Rx<7:0>, respectively Note: INLVLC4 / INLVLC3: Pins read the I2C ST inputs when MSSP inputs select these pins, and I2C mode is enabled. Value 1 0 Description ST input used for port reads and interrupt-on-change TTL input used for port reads and interrupt-on-change (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 282 PIC18F26/45/46Q10 I/O Ports 15.5.39 INLVLD Name: Address: INLVLD 0xF1D Input Level Control Register Bit Access Reset 7 6 5 4 3 2 1 0 INLVLD7 INLVLD6 INLVLD5 INLVLD4 INLVLD3 INLVLD2 INLVLD1 INLVLD0 R/W R/W R/W R/W R/W R/W R/W R/W 1 1 1 1 1 1 1 1 Bits 0, 1, 2, 3, 4, 5, 6, 7 - INLVLDn Input Level Select on Pins Rx<7:0>, respectively Value Description 1 ST input used for port reads and interrupt-on-change 0 TTL input used for port reads and interrupt-on-change (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 283 PIC18F26/45/46Q10 I/O Ports 15.5.40 INLVLE Name: Address: INLVLE 0xF25 Input Level Control Register Bit 7 6 Access Reset 5 4 3 2 1 0 INLVLE3 INLVLE2 INLVLE1 INLVLE0 R/W R/W R/W R/W 1 1 1 1 Bits 0, 1, 2, 3 - INLVLEn Input Level Select on Pins Rx<3:0>, respectively Note: 28-pin package only has INLVLE3 in this register. Value 1 0 Description ST input used for port reads and interrupt-on-change TTL input used for port reads and interrupt-on-change (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 284 PIC18F26/45/46Q10 Interrupt-on-Change 16. Interrupt-on-Change 16.1 Features * * * * 16.2 Interrupt-on-change Enable (Master Switch) Individual Pin Configuration Rising and Falling Edge Detection Individual Pin Interrupt Flags Overview All the pins of PORTA, PORTB, PORTC, and pin RE3 of PORTE can be configured to operate as Interrupt-on-Change (IOC) pins on PIC18F26/45/46Q10 family devices. An interrupt can be generated by detecting a signal that has either a rising edge or a falling edge. Any individual port pin, or combination of port pins, can be configured to generate an interrupt. (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 285 PIC18F26/45/46Q10 Interrupt-on-Change 16.3 Block Diagram Figure 16-1. Interrupt-on-Change Block Diagram (PORTA Example) Rev. 10-000 037A 6/2/201 4 IOCANx D Q R Q4Q1 edge detect RAx IOCAPx D data bus = 0 or 1 Q D S to data bus IOCAFx Q write IOCAFx R IOCIE Q2 IOC interrupt to CPU core from all other IOCnFx individual pin detectors FOSC Q1 Q1 Q1 Q2 Q3 Q3 Q4 Q4Q1 16.4 Q2 Q2 Q3 Q4 Q4Q1 Q4 Q4Q1 Q4Q1 Enabling the Module To allow individual port pins to generate an interrupt, the IOCIE bit of the PIE0 register must be set. If the IOCIE bit is disabled, the edge detection on the pin will still occur, but an interrupt will not be generated. Related Links 14.13.10 PIE0 16.5 Individual Pin Configuration For each port pin, a rising edge detector and a falling edge detector are present. To enable a pin to detect a rising edge, the associated bit of the IOCxP register is set. To enable a pin to detect a falling edge, the associated bit of the IOCxN register is set. (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 286 PIC18F26/45/46Q10 Interrupt-on-Change A pin can be configured to detect rising and falling edges simultaneously by setting both associated bits of the IOCxP and IOCxN registers, respectively. 16.6 Interrupt Flags The IOCAFx, IOCBFx, IOCCFx and IOCEF3 bits located in the IOCAF, IOCBF, IOCCF and IOCEF registers respectively, are status flags that correspond to the interrupt-on-change pins of the associated port. If an expected edge is detected on an appropriately enabled pin, then the status flag for that pin will be set, and an interrupt will be generated if the IOCIE bit is set. The IOCIF bit of the PIR0 register reflects the status of all IOCAFx, IOCBFx, IOCCFx and IOCEF3 bits. Related Links 14.13.2 PIR0 16.7 Clearing Interrupt Flags The individual status flags, (IOCAFx, IOCBFx, IOCCFx and IOCEF3) bits, can be cleared by resetting them to zero. If another edge is detected during this clearing operation, the associated status flag will be set at the end of the sequence, regardless of the value actually being written. In order to ensure that no detected edge is lost while clearing flags, only AND operations masking out known changed bits should be performed. The following sequence is an example of what should be performed. Example 16-1. Clearing Interrupt Flags (PORTA Example) MOVLW XORWF ANDWF 16.8 0xff IOCAF, W IOCAF, F Operation in Sleep The interrupt-on-change interrupt sequence will wake the device from Sleep mode, if the IOCIE bit is set. If an edge is detected while in Sleep mode, the IOCxF register will be updated prior to the first instruction executed out of Sleep. (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 287 PIC18F26/45/46Q10 Interrupt-on-Change 16.9 Register Summary - Interrupt-on-Change Address Name Bit Pos. 0x0F05 IOCAF 7:0 IOCAF7 IOCAF6 IOCAF5 IOCAF4 IOCAF3 IOCAF2 IOCAF1 IOCAF0 0x0F06 IOCAN 7:0 IOCAN7 IOCAN6 IOCAN5 IOCAN4 IOCAN3 IOCAN2 IOCAN1 IOCAN0 0x0F07 IOCAP 7:0 IOCAP7 IOCAP6 IOCAP5 IOCAP4 IOCAP3 IOCAP2 IOCAP1 IOCAP0 0x0F08 ... Reserved 0x0F0C 0x0F0D IOCBF 7:0 IOCBF7 IOCBF6 IOCBF5 IOCBF4 IOCBF3 IOCBF2 IOCBF1 IOCBF0 0x0F0E IOCBN 7:0 IOCBN7 IOCBN6 IOCBN5 IOCBN4 IOCBN3 IOCBN2 IOCBN1 IOCBN0 0x0F0F IOCBP 7:0 IOCBP7 IOCBP6 IOCBP5 IOCBP4 IOCBP3 IOCBP2 IOCBP1 IOCBP0 0x0F10 ... Reserved 0x0F14 0x0F15 IOCCF 7:0 IOCCF7 IOCCF6 IOCCF5 IOCCF4 IOCCF3 IOCCF2 IOCCF1 IOCCF0 0x0F16 IOCCN 7:0 IOCCN7 IOCCN6 IOCCN5 IOCCN4 IOCCN3 IOCCN2 IOCCN1 IOCCN0 0x0F17 IOCCP 7:0 IOCCP7 IOCCP6 IOCCP5 IOCCP4 IOCCP3 IOCCP2 IOCCP1 IOCCP0 0x0F18 ... Reserved 0x0F21 0x0F22 IOCEF 7:0 IOCEF3 0x0F23 IOCEN 7:0 IOCEN3 0x0F24 IOCEP 7:0 IOCEP3 16.10 Register Definitions: Interrupt-on-Change Control (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 288 PIC18F26/45/46Q10 Interrupt-on-Change 16.10.1 IOCAF Name: Address: IOCAF 0xF05 PORTA Interrupt-on-Change Flag Register Example Bit Access Reset 7 6 5 4 3 2 1 0 IOCAF7 IOCAF6 IOCAF5 IOCAF4 IOCAF3 IOCAF2 IOCAF1 IOCAF0 R/W/HS R/W/HS R/W/HS R/W/HS R/W/HS R/W/HS R/W/HS R/W/HS 0 0 0 0 0 0 0 0 Bits 0, 1, 2, 3, 4, 5, 6, 7 - IOCAFn Interrupt-on-Change Flag bits Value Condition Description 1 IOCAP[n]=1 A positive edge was detected on the RA[n] pin 1 IOCAN[n]=1 A negative edge was detected on the RA[n] pin 0 IOCAP[n]=x and No change was detected, or the user cleared the detected change IOCAN[n]=x (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 289 PIC18F26/45/46Q10 Interrupt-on-Change 16.10.2 IOCBF Name: Address: IOCBF 0xF0D PORTB Interrupt-on-Change Flag Register Example Bit Access Reset 7 6 5 4 3 2 1 0 IOCBF7 IOCBF6 IOCBF5 IOCBF4 IOCBF3 IOCBF2 IOCBF1 IOCBF0 R/W/HS R/W/HS R/W/HS R/W/HS R/W/HS R/W/HS R/W/HS R/W/HS 0 0 0 0 0 0 0 0 Bits 0, 1, 2, 3, 4, 5, 6, 7 - IOCBFn Interrupt-on-Change Flag bits Value Condition Description 1 IOCBP[n]=1 A positive edge was detected on the RB[n] pin 1 IOCBN[n]=1 A negative edge was detected on the RB[n] pin 0 IOCBP[n]=x and No change was detected, or the user cleared the detected change IOCBN[n]=x (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 290 PIC18F26/45/46Q10 Interrupt-on-Change 16.10.3 IOCCF Name: Address: IOCCF 0xF15 PORTC Interrupt-on-Change Flag Register Bit Access Reset 7 6 5 4 3 2 1 0 IOCCF7 IOCCF6 IOCCF5 IOCCF4 IOCCF3 IOCCF2 IOCCF1 IOCCF0 R/W/HS R/W/HS R/W/HS R/W/HS R/W/HS R/W/HS R/W/HS R/W/HS 0 0 0 0 0 0 0 0 Bits 0, 1, 2, 3, 4, 5, 6, 7 - IOCCFn Interrupt-on-Change Flag bits Value Condition Description 1 IOCCP[n]=1 A positive edge was detected on the RC[n] pin 1 IOCCN[n]=1 A negative edge was detected on the RC[n] pin 0 IOCCP[n]=x and No change was detected, or the user cleared the detected change IOCCN[n]=x (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 291 PIC18F26/45/46Q10 Interrupt-on-Change 16.10.4 IOCEF Name: Address: IOCEF 0xF22 PORTE Interrupt-on-Change Flag Register Bit 7 6 5 4 3 2 1 0 IOCEF3 Access R/W/HS Reset 0 Bit 3 - IOCEF3 PORTE Interrupt-on-Change Flag bits(1) Value Condition Description 1 IOCEP[n]=1 A positive edge was detected on the RE[n] pin 1 IOCEN[n]=1 A negative edge was detected on the RE[n] pin 0 IOCEP[n]=x and No change was detected, or the user cleared the detected change IOCEN[n]=x Note: 1. If MCLRE = 1 or LVP = 1, RE3 port functionality is disabled and IOC on RE3 is not available. (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 292 PIC18F26/45/46Q10 Interrupt-on-Change 16.10.5 IOCAN Name: Address: IOCAN 0xF06 Interrupt-on-Change Negative Edge Register Example Bit Access Reset 7 6 5 4 3 2 1 0 IOCAN7 IOCAN6 IOCAN5 IOCAN4 IOCAN3 IOCAN2 IOCAN1 IOCAN0 R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Bits 0, 1, 2, 3, 4, 5, 6, 7 - IOCANn Interrupt-on-Change Negative Edge Enable bits Value Description 1 Interrupt-on-Change enabled on the IOCA pin for a negative-going edge. Associated Status bit and interrupt flag will be set upon detecting an edge. 0 Interrupt-on-Change disabled for the associated pin (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 293 PIC18F26/45/46Q10 Interrupt-on-Change 16.10.6 IOCBN Name: Address: IOCBN 0xF0E Interrupt-on-Change Negative Edge Register Example Bit Access Reset 7 6 5 4 3 2 1 0 IOCBN7 IOCBN6 IOCBN5 IOCBN4 IOCBN3 IOCBN2 IOCBN1 IOCBN0 R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Bits 0, 1, 2, 3, 4, 5, 6, 7 - IOCBNn Interrupt-on-Change Negative Edge Enable bits Value Description 1 Interrupt-on-Change enabled on the IOCA pin for a negative-going edge. Associated Status bit and interrupt flag will be set upon detecting an edge. 0 Interrupt-on-Change disabled for the associated pin. (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 294 PIC18F26/45/46Q10 Interrupt-on-Change 16.10.7 IOCCN Name: Address: IOCCN 0xF16 Interrupt-on-Change Negative Edge Register Example Bit Access Reset 7 6 5 4 3 2 1 0 IOCCN7 IOCCN6 IOCCN5 IOCCN4 IOCCN3 IOCCN2 IOCCN1 IOCCN0 R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Bits 0, 1, 2, 3, 4, 5, 6, 7 - IOCCNn Interrupt-on-Change Negative Edge Enable bits Value Description 1 Interrupt-on-Change enabled on the IOCA pin for a negative-going edge. Associated Status bit and interrupt flag will be set upon detecting an edge. 0 Interrupt-on-Change disabled for the associated pin. (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 295 PIC18F26/45/46Q10 Interrupt-on-Change 16.10.8 IOCEN Name: Address: IOCEN 0xF23 Interrupt-on-Change Negative Edge Register Example Bit 7 6 5 4 3 2 1 0 IOCEN3 Access R/W Reset 0 Bit 3 - IOCEN3 Interrupt-on-Change Negative Edge Enable bits(1) Value Description 1 Interrupt-on-Change enabled on the IOCA pin for a negative-going edge. Associated Status bit and interrupt flag will be set upon detecting an edge. 0 Interrupt-on-Change disabled for the associated pin Note: 1. If MCLRE = 1 or LVP = 1, RE3 port functionality is disabled and IOC on RE3 is not available. (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 296 PIC18F26/45/46Q10 Interrupt-on-Change 16.10.9 IOCAP Name: Address: IOCAP 0xF07 Interrupt-on-Change Positive Edge Register Bit Access Reset 7 6 5 4 3 2 1 0 IOCAP7 IOCAP6 IOCAP5 IOCAP4 IOCAP3 IOCAP2 IOCAP1 IOCAP0 R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Bits 0, 1, 2, 3, 4, 5, 6, 7 - IOCAPn Interrupt-on-Change Positive Edge Enable bits Value Description 1 Interrupt-on-Change enabled on the IOCA pin for a positive-going edge. Associated Status bit and interrupt flag will be set upon detecting an edge. 0 Interrupt-on-Change disabled for the associated pin. (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 297 PIC18F26/45/46Q10 Interrupt-on-Change 16.10.10 IOCBP Name: Address: IOCBP 0xF0F Interrupt-on-Change Positive Edge Register Bit Access Reset 7 6 5 4 3 2 1 0 IOCBP7 IOCBP6 IOCBP5 IOCBP4 IOCBP3 IOCBP2 IOCBP1 IOCBP0 R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Bits 0, 1, 2, 3, 4, 5, 6, 7 - IOCBPn Interrupt-on-Change Positive Edge Enable bits Value Description 1 Interrupt-on-Change enabled on the IOCB pin for a positive-going edge. Associated Status bit and interrupt flag will be set upon detecting an edge. 0 Interrupt-on-Change disabled for the associated pin. (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 298 PIC18F26/45/46Q10 Interrupt-on-Change 16.10.11 IOCCP Name: Address: IOCCP 0xF17 Interrupt-on-Change Positive Edge Register Bit Access Reset 7 6 5 4 3 2 1 0 IOCCP7 IOCCP6 IOCCP5 IOCCP4 IOCCP3 IOCCP2 IOCCP1 IOCCP0 R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Bits 0, 1, 2, 3, 4, 5, 6, 7 - IOCCPn Interrupt-on-Change Positive Edge Enable bits Value Description 1 Interrupt-on-Change enabled on the IOCC pin for a positive-going edge. Associated Status bit and interrupt flag will be set upon detecting an edge. 0 Interrupt-on-Change disabled for the associated pin. (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 299 PIC18F26/45/46Q10 Interrupt-on-Change 16.10.12 IOCEP Name: Address: IOCEP 0xF24 Interrupt-on-Change Positive Edge Register Bit 7 6 5 4 3 2 1 0 IOCEP3 Access R/W Reset 0 Bit 3 - IOCEP3 Interrupt-on-Change Positive Edge Enable bit(1) Value Description 1 Interrupt-on-Change enabled on the IOCE pin for a positive-going edge. Associated Status bit and interrupt flag will be set upon detecting an edge. 0 Interrupt-on-Change disabled for the associated pin. Note: 1. If MCLRE = 1 or LVP = 1, RE3 port functionality is disabled and IOC on RE3 is not available. (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 300 PIC18F26/45/46Q10 (PPS) Peripheral Pin Select Module 17. (PPS) Peripheral Pin Select Module The Peripheral Pin Select (PPS) module connects peripheral inputs and outputs to the device I/O pins. Only digital signals are included in the selections. All analog inputs and outputs remain fixed to their assigned pins. Input and output selections are independent as shown in the figure below. The peripheral input is selected with the peripheral 17.9.1 xxxPPS register, and the peripheral output is selected with the PORT 17.9.2 RxyPPS register . For example, to select PORTC<7> as the EUSART RX input, set RXxPPS to 0x17 as shown in the input table, and to select PORTC<6> as the EUSART TX output set RC6PPS to 0x09 as shown in the output table. Figure 17-1. Simplified PPS Block Diagram Rev. 10-000 262B 2/22/201 7 RA0PPS abcPPS RA0 RA0 Per ipheral ab c RxyPPS Rxy Per ipheral xyz RC7 RC7PPS xyzPPS 17.1 RC7 PPS Inputs Each peripheral has an xxxPPS register with which the input pin to the peripheral is selected. Not all ports are available for input as shown in the following table. Multiple peripherals can operate from the same source simultaneously. Port reads always return the pin level regardless of peripheral PPS selection. If a pin also has analog functions associated, the ANSEL bit for that pin must be cleared to enable the digital input buffer. Important: The notation "xxx" in the generic register name is a place holder for the peripheral identifier. For example, xxx = INT for the INTPPS register. (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 301 PIC18F26/45/46Q10 (PPS) Peripheral Pin Select Module Table 17-1. PPS Input Selection Register Details PPS Input Register Default Pin Selection at POR Register Reset Value at POR Interrupt 0 INT0PPS RB0 Interrupt 1 INT1PPS Interrupt 2 Peripheral PORT From Which Input Is Available 28-Pin Devices 40-Pin Devices 0x08 A B -- A B -- -- RB1 0x09 A B -- A B -- -- INT2PPS RB2 0x0A A B -- A B -- -- Timer0 Clock T0CKIPPS RA4 0x04 A B -- A B -- -- Timer1 Clock T1CKIPPS RC0 0x10 A -- C A -- C -- Timer1 Gate T1GPPS RB5 0x0D -- B C -- B C -- Timer3 Clock T3CKIPPS RC0 0x10 -- B C -- B C -- Timer3 Gate T3GPPS RC0 0x10 A -- C A -- C -- Timer5 Clock T5CKIPPS RC2 0x12 A -- C A -- C -- Timer5 Gate T5GPPS RB4 0x0C -- B C -- B -- D Timer2 Clock T2INPPS RC3 0x13 A -- C A -- C -- Timer4 Clock T4INPPS RC5 0x15 -- B C -- B C -- Timer6 Clock T6INPPS RB7 0x0F -- B C -- B -- D ADC Conversion Trigger ADACTPPS RB4 0x0C -- B C -- B -- D CCP1 CCP1PPS RC2 0x12 -- B C -- B C -- CCP2 CCP2PPS RC1 0x11 -- B C -- B C -- CWG CWG1PPS RB0 0x08 -- B C -- B -- D DSM Carrier Low MDCARLPPS RA3 0x03 A -- C A -- -- D DSM Carrier High MDCARHPPS RA4 0x04 A -- C A -- -- D DSM Source MDSRCPPS RA5 0x05 A -- C A -- -- D EUSART1 Receive RX1PPS RC7 0x17 -- B C -- B C -- EUSART1 Clock CK1PPS RC6 0x16 -- B C -- B C -- EUSART2 Receive RX2PPS RB7 0x0F -- B C -- B -- D EUSART2 Clock CK2PPS RB6 0x0E -- B C -- B -- D (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 302 PIC18F26/45/46Q10 (PPS) Peripheral Pin Select Module ...........continued PPS Input Register Peripheral 17.2 Default Pin Selection at POR Register Reset Value at POR PORT From Which Input Is Available 28-Pin Devices 40-Pin Devices MSSP1 Clock SSP1CLKPPS RC3 0x13 -- B C -- B C -- MSSP1 Data SSP1DATPPS RC4 0x14 -- B C -- B C -- MSSP1 Slave Select SSP1SSPPS RA5 0x05 A -- C A -- -- D MSSP2 Clock SSP2CLKPPS RB1 0x09 -- B C -- B -- D MSSP2 Data SSP2DATPPS RB2 0x0A -- B C -- B -- D MSSP2 Slave Select SSP2SSPPS RB0 0x08 -- B C -- B -- D CLCIN0 CLCIN0PPS RA0 0x00 A -- C A -- C -- CLCIN1 CLCIN1PPS RA1 0x01 A -- C A -- C -- CLCIN2 CLCIN2PPS RB6 0x0E -- B C -- B -- D CLCIN3 CLCIN3PPS RB7 0x0F -- B C -- B -- D CLCIN4 CLCIN4PPS RA0 0x00 A -- C A -- C -- CLCIN5 CLCIN5PPS RA1 0x01 A -- C A -- C -- CLCIN6 CLCIN6PPS RB6 0x0E -- B C -- B -- D CLCIN7 CLCIN7PPS RB7 0x0F -- B C -- B -- D PPS Outputs Each I/O pin has an RxyPPS register with which the pin output source is selected. With few exceptions, the port TRIS control associated with that pin retains control over the pin output driver. Peripherals that control the pin output driver as part of the peripheral operation will override the TRIS control as needed. These peripherals include: * EUSART (synchronous operation) * MSSP (I2C) Although every pin has its own RxyPPS peripheral selection register, the selections are identical for every pin as shown in the following table. Important: The notation "Rxy" is a place holder for the pin identifier. The 'x' holds the place of the PORT letter and the 'y' holds the place of the bit number. For example, Rxy = RA0 for the RA0PPS register. (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 303 PIC18F26/45/46Q10 (PPS) Peripheral Pin Select Module Table 17-2. Peripheral PPS Output Selection Codes PORT To Which Output Can Be Directed RxyPPS Pin Rxy Output Source 0x1F CLC8OUT -- B C -- B -- D -- 0x1E CLC7OUT -- B C -- B -- D -- 0x1D CLC6OUT A -- C A -- C -- -- 0x1C CLC5OUT A -- C A -- C -- -- 0x1B CLC4OUT -- B C -- B -- D -- 0x1A CLC3OUT -- B C -- B -- D -- 0x19 CLC2OUT A -- C A -- C -- -- 0x18 CLC1OUT A -- C A -- C -- -- 0x17 ADGRDB A -- C A -- C -- -- 0x16 ADGRDA A -- C A -- C -- -- 0x15 DSM A -- C A -- -- D -- 0x14 CLKR -- B C -- B C -- -- 0x13 TMR0 -- B C -- B C -- -- 0x12 MSSP2 (SDO/SDA) -- B C -- B -- D -- 0x11 MSSP2 (SCK/SCL) -- B C -- B -- D -- 0x10 MSSP1 (SDO/SDA) -- B C -- B C -- -- 0x0F MSSP1 (SCK/SCL) -- B C -- B C -- -- 0x0E CMP2 A -- C A -- -- -- E 0x0D CMP1 A -- C A -- -- D -- 0x0C EUSART2 (DT) -- B C -- B -- D -- 0x0B EUSART2 (TX/CK) -- B C -- B -- D -- 0x0A EUSART1 (DT) -- B C -- B C -- -- 0x09 EUSART1 (TX/CK) -- B C -- B C -- -- 0x08 PWM4 A -- C A -- C -- -- 0x07 PWM3 A -- C A -- -- D -- 0x06 CCP2 -- B C -- B C -- -- 0x05 CCP1 -- B C -- B C -- -- 0x04 CWG1D -- B C -- B -- D -- 0x03 CWG1C -- B C -- B -- D -- 0x02 CWG1B -- B C -- B -- D -- (c) 2019 Microchip Technology Inc. 28-Pin Devices Datasheet Preliminary 40-Pin Devices DS40001996C-page 304 PIC18F26/45/46Q10 (PPS) Peripheral Pin Select Module ...........continued 17.3 PORT To Which Output Can Be Directed RxyPPS Pin Rxy Output Source 0x01 CWG1A -- B C -- B C -- -- 0x00 LATxy A B C A B C D E 28-Pin Devices 40-Pin Devices Bidirectional Pins PPS selections for peripherals with bidirectional signals on a single pin must be made so that the PPS input and PPS output select the same pin. Peripherals that have bidirectional signals include: * EUSART (DT/RXxPPS and TX/CKxPPS pins for synchronous operation) * MSSP (I2C SDA/SSPxDATPPS and SCL/SSPxCLKPPS) Important: The I2C default inputs, and a limited number of other alternate pins, are I2C and SMBus compatible. Clock and data signals can be routed to any pin, however pins without I2C compatibility will operate at standard TTL/ST logic levels as selected by the INLVL register. See the INLVL register for each port to determine which pins are I2C and SMBus compatible. 17.4 PPS Lock The PPS includes a mode in which all input and output selections can be locked to prevent inadvertent changes. PPS selections are locked by setting the PPSLOCKED bit of the PPSLOCK register. Setting and clearing this bit requires a special sequence as an extra precaution against inadvertent changes. Examples of setting and clearing the PPSLOCKED bit are shown in the following examples. Example 17-1. PPS Lock Sequence ; Disable interrupts: BCF INTCON,GIE ; Bank to PPSLOCK register BANKSEL PPSLOCK MOVLW 55h ; Required sequence, next 4 instructions MOVWF PPSLOCK MOVLW AAh MOVWF PPSLOCK ; Set PPSLOCKED bit to disable writes ; Only a BSF instruction will work BSF PPSLOCK,PPSLOCKED ; Enable Interrupts BSF INTCON,GIE Example 17-2. PPS Unlock Sequence ; Disable interrupts: BCF INTCON,GIE ; Bank to PPSLOCK register BANKSEL PPSLOCK MOVLW 55h ; Required sequence, next 4 instructions MOVWF PPSLOCK MOVLW AAh (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 305 PIC18F26/45/46Q10 (PPS) Peripheral Pin Select Module MOVWF PPSLOCK ; Clear PPSLOCKED bit to enable writes ; Only a BCF instruction will work BCF PPSLOCK,PPSLOCKED ; Enable Interrupts BSF INTCON,GIE 17.5 PPS One-Way Lock Using the PPS1WAY Configuration bit, the PPS settings can be locked in. When this bit is set, the PPSLOCKED bit can only be cleared and set one time after a device Reset. This allows for clearing the PPSLOCKED bit so that the input and output selections can be made during initialization. When the PPSLOCKED bit is set after all selections have been made, it will remain set and cannot be cleared until after the next device Reset event. 17.6 Operation During Sleep PPS input and output selections are unaffected by Sleep. 17.7 Effects of a Reset A device Power-on-Reset (POR) clears all PPS input and output selections to their default values. All other Resets leave the selections unchanged. Default input selections are shown in the input selection register table. The PPS one-way is also removed. (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 306 PIC18F26/45/46Q10 (PPS) Peripheral Pin Select Module 17.8 Register Summary - PPS Address Name Bit Pos. 0x0E1F CLCIN0PPS 7:0 PORT[1:0] PIN[2:0] 0x0E20 CLCIN1PPS 7:0 PORT[1:0] PIN[2:0] 0x0E21 CLCIN2PPS 7:0 PORT[1:0] PIN[2:0] 0x0E22 CLCIN3PPS 7:0 PORT[1:0] PIN[2:0] 0x0E23 CLCIN4PPS 7:0 PORT[1:0] PIN[2:0] 0x0E24 CLCIN5PPS 7:0 PORT[1:0] PIN[2:0] 0x0E25 CLCIN6PPS 7:0 PORT[1:0] PIN[2:0] 0x0E26 CLCIN7PPS 7:0 PORT[1:0] PIN[2:0] RX2PPS 7:0 PORT[1:0] PIN[2:0] 0x0E27 ... Reserved 0x0E87 0x0E88 0x0E89 CK2PPS 7:0 PORT[1:0] PIN[2:0] 0x0E8A SSP2CLKPPS 7:0 PORT[1:0] PIN[2:0] 0x0E8B SSP2DATPPS 7:0 PORT[1:0] PIN[2:0] 0x0E8C SSP2SSPPS 7:0 PORT[1:0] PIN[2:0] 0x0E8D ... Reserved 0x0E9A 0x0E9B PPSLOCK 7:0 0x0E9C INT0PPS 7:0 PORT PIN[2:0] PPSLOCKED 0x0E9D INT1PPS 7:0 PORT PIN[2:0] 0x0E9E INT2PPS 7:0 PORT PIN[2:0] PORT PIN[2:0] 0x0E9F T0CKIPPS 7:0 0x0EA0 T1CKIPPS 7:0 PORT[1:0] PIN[2:0] 0x0EA1 T1GPPS 7:0 PORT[1:0] PIN[2:0] 0x0EA2 T3CKIPPS 7:0 PORT[1:0] PIN[2:0] 0x0EA3 T3GPPS 7:0 PORT[1:0] PIN[2:0] 0x0EA4 T5CKIPPS 7:0 PORT[1:0] PIN[2:0] 0x0EA5 T5GPPS 7:0 PORT[1:0] PIN[2:0] 0x0EA6 T2INPPS 7:0 PORT[1:0] PIN[2:0] 0x0EA7 T4INPPS 7:0 PORT[1:0] PIN[2:0] 0x0EA8 T6INPPS 7:0 PORT[1:0] PIN[2:0] 0x0EA9 ADACTPPS 7:0 PORT[1:0] PIN[2:0] 0x0EAA CCP1PPS 7:0 PORT[1:0] PIN[2:0] 0x0EAB CCP2PPS 7:0 PORT[1:0] PIN[2:0] 0x0EAC CWG1PPS 7:0 PORT[1:0] PIN[2:0] 0x0EAD MDCARLPPS 7:0 PORT[1:0] PIN[2:0] 0x0EAE MDCARHPPS 7:0 PORT[1:0] PIN[2:0] 0x0EAF MDSRCPPS 7:0 PORT[1:0] PIN[2:0] 0x0EB0 RX1PPS 7:0 PORT[1:0] PIN[2:0] 0x0EB1 CK1PPS 7:0 PORT[1:0] PIN[2:0] 0x0EB2 SSP1CLKPPS 7:0 PORT[1:0] PIN[2:0] (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 307 PIC18F26/45/46Q10 (PPS) Peripheral Pin Select Module ...........continued Address Name Bit Pos. 0x0EB3 SSP1DATPPS 7:0 PORT[1:0] PIN[2:0] 0x0EB4 SSP1SSPPS 7:0 PORT[1:0] PIN[2:0] 0x0EB5 ... Reserved 0x0EE1 0x0EE2 RA0PPS 7:0 PPS[4:0] 0x0EE3 RA1PPS 7:0 PPS[4:0] 0x0EE4 RA2PPS 7:0 PPS[4:0] 0x0EE5 RA3PPS 7:0 PPS[4:0] 0x0EE6 RA4PPS 7:0 PPS[4:0] 0x0EE7 RA5PPS 7:0 PPS[4:0] 0x0EE8 RA6PPS 7:0 PPS[4:0] 0x0EE9 RA7PPS 7:0 PPS[4:0] 0x0EEA RB0PPS 7:0 PPS[4:0] 0x0EEB RB1PPS 7:0 PPS[4:0] 0x0EEC RB2PPS 7:0 PPS[4:0] 0x0EED RB3PPS 7:0 PPS[4:0] 0x0EEE RB4PPS 7:0 PPS[4:0] 0x0EEF RB5PPS 7:0 PPS[4:0] 0x0EF0 RB6PPS 7:0 PPS[4:0] 0x0EF1 RB7PPS 7:0 PPS[4:0] 0x0EF2 RC0PPS 7:0 PPS[4:0] 0x0EF3 RC1PPS 7:0 PPS[4:0] 0x0EF4 RC2PPS 7:0 PPS[4:0] 0x0EF5 RC3PPS 7:0 PPS[4:0] 0x0EF6 RC4PPS 7:0 PPS[4:0] 0x0EF7 RC5PPS 7:0 PPS[4:0] 0x0EF8 RC6PPS 7:0 PPS[4:0] 0x0EF9 RC7PPS 7:0 PPS[4:0] 0x0EFA RD0PPS 7:0 PPS[4:0] 0x0EFB RD1PPS 7:0 PPS[4:0] 0x0EFC RD2PPS 7:0 PPS[4:0] 0x0EFD RD3PPS 7:0 PPS[4:0] 0x0EFE RD4PPS 7:0 PPS[4:0] 0x0EFF RD5PPS 7:0 PPS[4:0] 0x0F00 RD6PPS 7:0 PPS[4:0] 0x0F01 RD7PPS 7:0 PPS[4:0] 0x0F02 RE0PPS 7:0 PPS[4:0] 0x0F03 RE1PPS 7:0 PPS[4:0] 0x0F04 RE2PPS 7:0 PPS[4:0] 17.9 Register Definitions: PPS Input and Output Selection (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 308 PIC18F26/45/46Q10 (PPS) Peripheral Pin Select Module 17.9.1 Peripheral xxx Input Selection Name: xxxPPS Important: The Reset value of this register is determined by the device default for each peripheral. Refer to the input selection table for a list of available ports and default pin locations. Bit 7 6 5 4 3 2 PORT[1:0] Access Reset 1 0 PIN[2:0] R/W R/W R/W R/W R/W g g g g g Bits 4:3 - PORT[1:0] Peripheral xxx Input PORT Selection bits See the input selection table for a list of available ports and default pin locations. Value Description 11 PORTD 10 PORTC 01 PORTB 00 PORTA Bits 2:0 - PIN[2:0] Peripheral xxx Input Pin Selection bits Value Description 111 Peripheral input is from PORTx Pin 7 (Rx7) 110 Peripheral input is from PORTx Pin 6 (Rx6) 101 Peripheral input is from PORTx Pin 5 (Rx5) 100 Peripheral input is from PORTx Pin 4 (Rx4) 011 Peripheral input is from PORTx Pin 3 (Rx3) 010 Peripheral input is from PORTx Pin 2 (Rx2) 001 Peripheral input is from PORTx Pin 1 (Rx1) 000 Peripheral input is from PORTx Pin 0 (Rx0) (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 309 PIC18F26/45/46Q10 (PPS) Peripheral Pin Select Module 17.9.2 Pin Rxy Output Source Selection Register Name: RxyPPS Important: See 17.8 Register Summary - PPS for the address offset of each individual register. Bit 7 6 5 4 3 R/W R/W 0 0 2 1 0 R/W R/W R/W 0 0 0 RxyPPS[4:0] Access Reset Bits 4:0 - RxyPPS[4:0] Pin Rxy Output Source Selection bits See output source selection table for source codes. (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 310 PIC18F26/45/46Q10 (PPS) Peripheral Pin Select Module 17.9.3 PPS Lock Register Name: Address: Bit 7 PPSLOCK 0xE9B 6 5 4 3 2 1 0 PPSLOCKED Access R/W Reset 0 Bit 0 - PPSLOCKED PPS Locked bit Value Description 1 PPS is locked. PPS selections can not be changed. 0 PPS is not locked. PPS selections can be changed. (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 311 PIC18F26/45/46Q10 Timer0 Module 18. Timer0 Module Timer0 module has the following features: * * * * * * * * 8-Bit B\Timer with Programmable Period 16-Bit Timer Selectable Clock Sources Synchronous and Asynchronous Operation Programmable Prescaler and Postscaler Interrupt on Match or Overflow Output on I/O Pin (via PPS) or to Other Peripherals Operation During Sleep Figure 18-1. Timer0 Block Diagram Rev. 10-000017I 2/8/2018 See T0CON1 Register T0CKPS Peripherals TMR0 body T0OUTPS T0IF 1 Prescaler IN SYNC OUT TMR0 FOSC/4 T016BIT T0ASYNC PPS T0_out Postscaler 0 Q D T0CKIPPS PPS RxyPPS CK Q T0CS 16-bit TMR0 Body Diagram (T016BIT = 1) 8-bit TMR0 Body Diagram (T016BIT = 0) IN TMR0L R Clear IN TMR0L TMR0 High Byte OUT 8 Read TMR0L COMPARATOR OUT Write TMR0L T0_match 8 8 TMR0H TMR0 High Byte Latch Enable 8 TMR0H 8 Internal Data Bus (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 312 PIC18F26/45/46Q10 Timer0 Module 18.1 Timer0 Operation Timer0 can operate as either an 8-bit or 16-bit timer. The mode is selected with the T016BIT bit. 18.1.1 8-bit Mode In this mode Timer0 increments on the rising edge of the selected clock source. A prescaler on the clock input gives several prescale options (see prescaler control bits, T0CKPS). In this mode as shown in Figure 18-1, a buffered version of TMR0H is maintained. This is compared with the value of TMR0L on each cycle of the selected clock source. When the two values match, the following events occur: * TMR0L is reset * The contents of TMR0H are copied to the TMR0H buffer for next comparison 18.1.2 16-Bit Mode In this mode Timer0 increments on the rising edge of the selected clock source. A prescaler on the clock input gives several prescale options (see prescaler control bits, T0CKPS). In this mode TMR0H:TMR0L form the 16-bit timer value. As shown in Figure 18-1, read and write of the TMR0H register are buffered. TMR0H register is updated with the contents of the high byte of Timer0 during a read of TMR0L register. Similarly, a write to the high byte of Timer0 takes place through the TMR0H buffer register. The high byte is updated with the contents of TMR0H register when a write occurs to TMR0L register. This allows all 16 bits of Timer0 to be read and written at the same time. Timer0 rolls over to 0x0000 on incrementing past 0xFFFF. This makes the timer free-running. TMR0L/H registers cannot be reloaded in this mode once started. 18.2 Clock Selection Timer0 has several options for clock source selections, option to operate synchronously/asynchronously and a programmable prescaler. 18.2.1 Clock Source Selection The T0CS bits are used to select the clock source for Timer0. The possible clock sources are listed in the table below. Table 18-1. Timer 0 Clock Source Selections T0CS Clock Source 111 CLC1_out 110 MFINTOSC (500 kHz) 101 SOSC 100 LFINTOSC 011 HFINTOSC 010 FOSC/4 001 Pin selected by T0CKIPPS (Inverted) 000 Pin selected by T0CKIPPS (Non-inverted) (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 313 PIC18F26/45/46Q10 Timer0 Module 18.2.2 Synchronous Mode When the T0ASYNC bit is clear, Timer0 clock is synchronized to the system clock (FOSC/4). When operating in Synchronous mode, Timer0 clock frequency cannot exceed FOSC/4. During Sleep mode system clock is not available and Timer0 cannot operate. 18.2.3 Asynchronous Mode When the T0ASYNC bit is set, Timer0 increments with each rising edge of the input source (or output of the prescaler, if used). Asynchronous mode allows Timer0 to continue operation during Sleep mode provided the selected clock source is available. 18.2.4 Programmable Prescaler Timer0 has 16 programmable input prescaler options ranging from 1:1 to 1:32768. The prescaler values are selected using the T0CKPS bits. The prescaler counter is not directly readable or writable. The prescaler counter is cleared on the following events: * A write to the TMR0L register * A write to either the T0CON0 or T0CON1 registers * Any device Reset Related Links 8. Resets 18.3 Timer0 Output and Interrupt 18.3.1 Programmable Postscaler Timer0 has 16 programmable output postscaler options ranging from 1:1 to 1:16. The postscaler values are selected using the T0OUTPS bits. The postscaler divides the output of Timer0 by the selected ratio. The postscaler counter is not directly readable or writable. The postscaler counter is cleared on the following events: * A write to the TMR0L register * A write to either the T0CON0 or T0CON1 registers * Any device Reset 18.3.2 Timer0 Output TMR0_out is the output of the postscaler. TMR0_out toggles on every match between TMR0L and TMR0H in 8-bit mode, or when TMR0H:TMR0L rolls over in 16-bit mode. If the output postscaler is used, the output is scaled by the ratio selected. The Timer0 output can be routed to an I/O pin via the RxyPPS output selection register. The Timer0 output can be monitored through software via the T0OUT output bit. Related Links 17.2 PPS Outputs 18.3.3 Timer0 Interrupt The Timer0 Interrupt Flag bit (TMR0IF) is set when the TMR0_out toggles. If the Timer0 interrupt is enabled (TMR0IE), the CPU will be interrupted when the TMR0IF bit is set. (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 314 PIC18F26/45/46Q10 Timer0 Module When the postscaler bits (T0OUTPS) are set to 1:1 operation (no division), the T0IF flag bit will be set with every TMR0 match or rollover. In general, the TMR0IF flag bit will be set every T0OUTPS +1 matches or rollovers. 18.3.4 Timer0 Example Timer0 Configuration: * Timer0 mode = 16-bit * Clock Source = FOSC/4 (250 kHz) * Synchronous operation * Prescaler = 1:1 * Postscaler = 1:2 (T0OUTPS = 1) In this case the TMR0_out toggles every two rollovers of TMR0H:TMR0L. i.e., (0xFFFF)*2*(1/250kHz) = 524.28 ms 18.4 Operation During Sleep When operating synchronously, Timer0 will halt when the device enters Sleep mode. When operating asynchronously and selected clock source is active, Timer0 will continue to increment and wake the device from Sleep mode if Timer0 interrupt is enabled. (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 315 PIC18F26/45/46Q10 Timer0 Module 18.5 Register Summary - Timer0 Address Name Bit Pos. 0x0FD2 TMR0L 7:0 0x0FD3 TMR0H 7:0 0x0FD4 T0CON0 7:0 0x0FD5 T0CON1 7:0 18.6 TMR0L[7:0] TMR0H[7:0] T0EN T0OUT T0CS[2:0] T016BIT T0OUTPS[3:0] T0ASYNC T0CKPS[3:0] Register Definitions: Timer0 Control (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 316 PIC18F26/45/46Q10 Timer0 Module 18.6.1 T0CON0 Name: Address: T0CON0 0xFD4 Timer0 Control Register 0 Bit Access Reset 5 4 T0EN 7 6 T0OUT T016BIT 3 R/W R R/W R/W 0 0 0 0 2 1 0 R/W R/W R/W 0 0 0 T0OUTPS[3:0] Bit 7 - T0EN TMR0 Enable Value Description 1 The module is enabled and operating 0 The module is disabled Bit 5 - T0OUT TMR0 Output Bit 4 - T016BIT TMR0 Operating as 16-Bit Timer Select Value Description 1 TMR0 is a 16-bit timer 0 TMR0 is an 8-bit timer Bits 3:0 - T0OUTPS[3:0] TMR0 Output Postscaler (Divider) Select Value Description 1111 1:16 Postscaler 1110 1:15 Postscaler 1101 1:14 Postscaler 1100 1:13 Postscaler 1011 1:12 Postscaler 1010 1:11 Postscaler 1001 1:10 Postscaler 1000 1:9 Postscaler 0111 1:8 Postscaler 0110 1:7 Postscaler 0101 1:6 Postscaler 0100 1:5 Postscaler 0011 1:4 Postscaler 0010 1:3 Postscaler 0001 1:2 Postscaler 0000 1:1 Postscaler (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 317 PIC18F26/45/46Q10 Timer0 Module 18.6.2 T0CON1 Name: Address: T0CON1 0xFD5 Timer0 Control Register 1 Bit 7 6 5 T0CS[2:0] Access Reset 4 3 2 T0ASYNC 1 0 T0CKPS[3:0] R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Bits 7:5 - T0CS[2:0] Timer0 Clock Source Select Refer the clock source selection table Bit 4 - T0ASYNC TMR0 Input Asynchronization Enable Value Description 1 The input to the TMR0 counter is not synchronized to system clocks 0 The input to the TMR0 counter is synchronized to FOSC/4 Bits 3:0 - T0CKPS[3:0] Prescaler Rate Select Value Description 1111 1:32768 1110 1:16384 1101 1:8192 1100 1:4096 1011 1:2048 1010 1:1024 1001 1:512 1000 1:256 0111 1:128 0110 1:64 0101 1:32 0100 1:16 0011 1:8 0010 1:4 0001 1:2 0000 1:1 (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 318 PIC18F26/45/46Q10 Timer0 Module 18.6.3 TMR0H Name: Address: TMR0H 0xFD3 Timer0 Period/Count High Register Bit 7 6 5 4 3 2 1 0 TMR0H[7:0] Access Reset R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Bits 7:0 - TMR0H[7:0] TMR0 Most Significant Counter Value Condition Description 0 to T016BIT = 0 8-bit Timer0 Period Value. TMR0L continues counting from 0 when this value 255 is reached. 0 to T016BIT = 1 16-bit Timer0 Most Significant Byte 255 (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 319 PIC18F26/45/46Q10 Timer0 Module 18.6.4 TMR0L Name: Address: TMR0L 0xFD2 Timer0 Period/Count Low Register Bit 7 6 5 4 3 2 1 0 TMR0L[7:0] Access Reset R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Bits 7:0 - TMR0L[7:0] TMR0 Least Significant Counter Value Condition Description 0 to T016BIT = 0 8-bit Timer0 Counter bits 255 0 to T016BIT = 1 16-bit Timer0 Least Significant Byte 255 (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 320 PIC18F26/45/46Q10 Timer1 Module with Gate Control 19. Timer1 Module with Gate Control Timer1 module is a 16-bit timer/counter with the following features: * * * * * * * * * * * * * * * 16-Bit Timer/Counter Register Pair (TMRxH:TMRxL) Programmable Internal or External Clock Source 2-Bit Prescaler Optionally Synchronized Comparator Out Multiple Timer1 Gate (count enable) Sources Interrupt-on-Overflow Wake-Up on Overflow (external clock, Asynchronous mode only) 16-Bit Read/Write Operation Time Base for the Capture/Compare Function with the CCP modules Special Event Trigger (with CCP) Selectable Gate Source Polarity Gate Toggle mode Gate Single Pulse mode Gate Value Status Gate Event Interrupt Important: References to module Timer1 apply to all the odd numbered timers on this device. (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 321 PIC18F26/45/46Q10 Timer1 Module with Gate Control Figure 19-1. Timer1 Block Diagram GSS<4:0> Rev. 10-000018L 6/26/2017 5 TxGPPS GSPM PPS 00000 0 NOTE (5) 11111 1 D D GVAL Q 0 Q1 Q GGO/DONE GPOL CK ON Q Interrupt R GTM set bit TMRxGIF det GE set flag bit TMRxIF Tx_overflow 1 Single Pulse Acq. Control TMRxH TMRxL ON EN TMRx(2) Q To Comparators (6) Synchronized Clock Input 0 D 1 TxCLK SYNC CS<4:0> 5 TxCKIPPS (1) PPS 00000 Note Prescaler 1,2,4,8 (4) 11111 2 CKPS<1:0> Synchronize(3) det Fosc/2 Internal Clock Sleep Input Note: 1. This signal comes from the pin seleted by TxCKIPPS. 2. TMRx register increments on rising edge. 3. Synchronize does not operate while in Sleep. 4. See TMRxCLK for clock source selections. 5. See TMRxGATE for gate source selection. 6. Synchronized comparator output should not be used in conjunction with synchronized input clock. 19.1 Timer1 Operation The Timer1 module is a 16-bit incrementing counter that is accessed through the TMRxH:TMRxL register pair. Writes to TMRxH or TMRxL directly update the counter. When used with an internal clock source, the module is a timer and increments on every instruction cycle. When used with an external clock source, the module can be used as either a timer or counter and increments on every selected edge of the external source. (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 322 PIC18F26/45/46Q10 Timer1 Module with Gate Control Timer1 is enabled by configuring the ON and GE bits in the TxCON and TxGCON registers, respectively. The table below displays the Timer1 enable selections. Table 19-1. Timer1 Enable Selections 19.2 ON GE Timer1 Operation 1 1 Count Enabled 1 0 Always On 0 1 Off 0 0 Off Clock Source Selection The CS bits select the clock source for Timer1. These bits allow the selection of several possible synchronous and asynchronous clock sources. The table below lists the clock source selections. Table 19-2. Timer Clock Sources Clock Source CS Timer1 Timer3 Timer5 11000-11111 Reserved Reserved Reserved 10111 CLC8_out CLC8_out CLC8_out 10110 CLC7_out CLC7_out CLC7_out 10101 CLC6_out CLC6_out CLC6_out 10100 CLC5_out CLC5_out CLC5_out 10011 CLC4_out CLC4_out CLC4_out 10010 CLC3_out CLC3_out CLC3_out 10001 CLC2_out CLC2_out CLC2_out 10000 CLC1_out CLC1_out CLC1_out 01111-01100 Reserved Reserved Reserved 01011 TMR5 overflow TMR5 overflow Reserved 01010 TMR3 overflow Reserved TMR3 overflow 01001 Reserved TMR1 overflow TMR1 overflow 01000 TMR0 overflow TMR0 overflow TMR0 overflow 00111 CLKREF CLKREF CLKREF 00110 SOSC SOSC SOSC 00101 MFINTOSC (500 kHz) MFINTOSC (500 kHz) MFINTOSC (500 kHz) 00100 LFINTOSC LFINTOSC LFINTOSC 00011 HFINTOSC HFINTOSC HFINTOSC (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 323 PIC18F26/45/46Q10 Timer1 Module with Gate Control ...........continued Clock Source CS 19.2.1 Timer1 Timer3 Timer5 00010 FOSC FOSC FOSC 00001 FOSC/4 FOSC/4 FOSC/4 00000 T1CKIPPS T3CKIPPS T5CKIPPS Internal Clock Source When the internal clock source is selected the TMRxH:TMRxL register pair will increment on multiples of FOSC as determined by the Timer1 prescaler. When the FOSC internal clock source is selected, the Timer1 register value will increment by four counts every instruction clock cycle. Due to this condition, a 2 LSB error in resolution will occur when reading the Timer1 value. To utilize the full resolution of Timer1, an asynchronous input signal must be used to gate the Timer1 clock input. Important: In Counter mode, a falling edge must be registered by the counter prior to the first incrementing rising edge after any one or more of the following conditions: * Timer1 enabled after POR * Write to TMRxH or TMRxL * Timer1 is disabled * Timer1 is disabled (TMRxON = 0) when TxCKI is high then Timer1 is enabled (TMRxON = 1) when TxCKI is low. Refer to the figure below. Figure 19-2. Timer1 Incrementing Edge Rev. 30-000136A 5/24/2017 TxCKI = 1 when TMRx Enabled TxCKI = 0 when TMRx Enabled Note: 1. Arrows indicate counter increments. 2. In Counter mode, a falling edge must be registered by the counter prior to the first incrementing rising edge of the clock. 19.2.2 External Clock Source When the external clock source is selected, the Timer1 module may work as a timer or a counter. When enabled to count, Timer1 is incremented on the rising edge of the external clock input of the TxCKIPPS pin. This external clock source can be synchronized to the system clock or it can run asynchronously. (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 324 PIC18F26/45/46Q10 Timer1 Module with Gate Control 19.3 Timer1 Prescaler Timer1 has four prescaler options allowing 1, 2, 4 or 8 divisions of the clock input. The CKPS bits control the prescale counter. The prescale counter is not directly readable or writable; however, the prescaler counter is cleared upon a write to TMRxH or TMRxL. 19.4 Secondary Oscillator A secondary low-power 32.768 kHz oscillator circuit is built-in between pins SOSCI (input) and SOSCO (amplifier output). This internal circuit is to be used in conjunction with an external 32.768 kHz crystal. The secondary oscillator is not dedicated only to Timer1; it can also be used by other modules. The oscillator circuit is enabled by setting the SOSCEN bit of the OSCEN register. This can be used as one of the Timer1 clock sources selected with the CS bits. The oscillator will continue to run during Sleep. Important: The oscillator requires a start-up and stabilization time before use. Thus, the SOSCEN bit of the OSCEN register should be set and a suitable delay observed prior to enabling Timer1. A software check can be performed to confirm if the secondary oscillator is enabled and ready to use. This is done by polling the SOR bit of the OSCSTAT. Related Links 4.2.1.5 Secondary Oscillator 19.5 Timer1 Operation in Asynchronous Counter Mode When the SYNC control bit is set, the external clock input is not synchronized. The timer increments asynchronously to the internal phase clocks. If external clock source is selected then the timer will continue to run during Sleep and can generate an interrupt on overflow, which will wake-up the processor. However, special precautions in software are needed to read/write the timer (see 19.5.1 Reading and Writing Timer1 in Asynchronous Counter Mode). Important: When switching from synchronous to asynchronous operation, it is possible to skip an increment. When switching from asynchronous to synchronous operation, it is possible to produce an additional increment. 19.5.1 Reading and Writing Timer1 in Asynchronous Counter Mode Reading TMRxH or TMRxL while the timer is running from an external asynchronous clock will ensure a valid read (taken care of in hardware). However, the user should keep in mind that reading the 16-bit timer in two 8-bit values itself, poses certain problems, since the timer may overflow between the reads. For writes, it is recommended that the user simply stop the timer and write the desired values. A write contention may occur by writing to the timer registers, while the register is incrementing. This may produce an unpredictable value in the TMRxH:TMRxL register pair. 19.6 Timer1 16-Bit Read/Write Mode Timer1 can be configured to read and write all 16 bits of data, to and from, the 8-bit TMRxL and TMRxH registers, simultaneously. The 16-bit read and write operations are enabled by setting the RD16 bit. (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 325 PIC18F26/45/46Q10 Timer1 Module with Gate Control To accomplish this function, the TMRxH register value is mapped to a buffer register called the TMRxH buffer register. While in 16-Bit mode, the TMRxH register is not directly readable or writable and all read and write operations take place through the use of this TMRxH buffer register. When a read from the TMRxL register is requested, the value of the TMRxH register is simultaneously loaded into the TMRxH buffer register. When a read from the TMRxH register is requested, the value is provided from the TMRxH buffer register instead. This provides the user with the ability to accurately read all 16 bits of the Timer1 value from a single instance in time. Refer the figure below for more details. In contrast, when not in 16-Bit mode, the user must read each register separately and determine if the values have become invalid due to a rollover that may have occurred between the read operations. When a write request of the TMRxL register is requested, the TMRxH buffer register is simultaneously updated with the contents of the TMRxH register. The value of TMRxH must be preloaded into the TMRxH buffer register prior to the write request for the TMRxL register. This provides the user with the ability to write all 16 bits to the TMRxL:TMRxH register pair at the same time. Any requests to write to the TMRxH directly does not clear the Timer1 prescaler value. The prescaler value is only cleared through write requests to the TMRxL register. Figure 19-3. Timer1 16-Bit Read/Write Mode Block Diagram From Timer1 Circuitry TMR1 High Byte TMR1L 8 Rev. 30-000135A 5/24/2017 Set TMR1IF on Overflow Read TMR1L Write TMR1L 8 8 TMR1H 8 8 Internal Data Bus 19.7 Timer1 Gate Timer1 can be configured to count freely or the count can be enabled and disabled using Timer1 gate circuitry. This is also referred to as Timer1 gate enable. Timer1 gate can also be driven by multiple selectable sources. 19.7.1 Timer1 Gate Enable The Timer1 Gate Enable mode is enabled by setting the GE bit. The polarity of the Timer1 Gate Enable mode is configured using the GPOL bit. When Timer1 Gate Enable mode is enabled, Timer1 will increment on the rising edge of the Timer1 clock source. When Timer1 Gate signal is inactive, the timer will not increment and hold the current count. Enable mode is disabled, no incrementing will occur and Timer1 will hold the current count. See figure below for timing details. (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 326 PIC18F26/45/46Q10 Timer1 Module with Gate Control Table 19-3. Timer1 Gate Enable Selections TMRxCLK GPOL TxG Timer1 Operation 1 1 Counts 1 0 Holds Count 0 1 Holds Count 0 0 Counts Figure 19-4. Timer1 Gate Enable Mode Rev. 30-000137A 5/24/2017 TMRxGE TxGPOL TxG_IN TxCKI TxGVAL Timer1/3/5/7 19.7.2 N N+1 N+2 N+3 N+4 Timer1 Gate Source Selection The gate source for Timer1 is selected using the GSS bits. The polarity selection for the gate source is controlled by the GPOL bit. The table below lists the gate source selections. Table 19-4. Timer Gate Sources Gate Source GSS Timer1 Timer3 Timer5 11000-11111 Reserved Reserved Reserved 10111 CLC8_out CLC8_out CLC8_out 10110 CLC7_out CLC7_out CLC7_out 10101 CLC6_out CLC6_out CLC6_out 10100 CLC5_out CLC5_out CLC5_out 10011 CLC4_out CLC4_out CLC4_out 10010 CLC3_out CLC3_out CLC3_out (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 327 PIC18F26/45/46Q10 Timer1 Module with Gate Control ...........continued Gate Source GSS Timer1 Timer3 Timer5 10001 CLC2_out CLC2_out CLC2_out 10000 CLC1_out CLC1_out CLC1_out 01111 Reserved Reserved Reserved 01110 ZCDOUT ZCDOUT ZCDOUT 01101 CMP2OUT CMP2OUT CMP2OUT 01100 CMP1OUT CMP1OUT CMP1OUT 01011 PWM4OUT PWM4OUT PWM4OUT 01010 PWM3OUT PWM3OUT PWM3OUT 01001 CCP2OUT CCP2OUT CCP2OUT 01000 CCP1OUT CCP1OUT CCP1OUT 00111 TMR6OUT (post-scaled) TMR6OUT (post-scaled) TMR6OUT (post-scaled) 00110 TMR5 overflow TMR5 overflow Reserved 00101 TMR4OUT (post-scaled) TMR4OUT (post-scaled) TMR4OUT (post-scaled) 00100 TMR3 overflow Reserved TMR3 overflow 00011 TMR2OUT (post-scaled) TMR2OUT (post-scaled) TMR2OUT (post-scaled) 00010 Reserved TMR1 overflow TMR1 overflow 00001 TMR0 overflow TMR0 overflow TMR0 overflow 00000 Pin selected by T1GPPS Pin selected by T3GPPS Pin selected by T5GPPS Any of the above mentioned signals can be used to trigger the gate. The output of the CMPx can be synchronized to the Timer1 clock or left asynchronous. For more information refer to the Comparator Output Synchronization section. Related Links 33.4.1 Comparator Output Synchronization 19.7.3 Timer1 Gate Toggle Mode When Timer1 Gate Toggle mode is enabled, it is possible to measure the full-cycle length of a Timer1 gate signal, as opposed to the duration of a single level pulse. The Timer1 gate source is routed through a flip-flop that changes state on every incrementing edge of the signal. See figure below for timing details. Timer1 Gate Toggle mode is enabled by setting the GTM bit. When the GTM bit is cleared, the flip-flop is cleared and held clear. This is necessary in order to control which edge is measured. (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 328 PIC18F26/45/46Q10 Timer1 Module with Gate Control Important: Enabling Toggle mode at the same time as changing the gate polarity may result in indeterminate operation. Figure 19-5. TIMER1 GATE TOGGLE MODE Rev. 30-000138A 5/25/2017 TMRxGE TxGPOL TxGTM TxTxG_IN TxCKI TxGVAL TIMER1/3/5/7 19.7.4 N N+1 N+2 N+3 N+4 N+5 N+6 N+7 N+8 Timer1 Gate Single Pulse Mode When Timer1 Gate Single Pulse mode is enabled, it is possible to capture a single pulse gate event. Timer1 Gate Single Pulse mode is first enabled by setting the GSPM bit. Next, the GGO/DONE must be set. The Timer1 will be fully enabled on the next incrementing edge. On the next trailing edge of the pulse, the GGO/DONE bit will automatically be cleared. No other gate events will be allowed to increment Timer1 until the GGO/DONE bit is once again set in software. Clearing the GSPM bit will also clear the GGO/DONE bit. See figure below for timing details. Enabling the Toggle mode and the Single Pulse mode simultaneously will permit both sections to work together. This allows the cycle times on the Timer1 gate source to be measured. See figure below for timing details. (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 329 PIC18F26/45/46Q10 Timer1 Module with Gate Control Figure 19-6. TIMER1 GATE SINGLE PULSE MODE Rev. 30-000139A 5/25/2017 TMRxGE TxGPOL TxGSPM TxGGO/ Cleared by hardware on falling edge of TxGVAL Set by software DONE Counting enabled on rising edge of TxG TxG_IN TxCKI TxGVAL TIMER1/3/5/7 TMRxGIF N Cleared by software (c) 2019 Microchip Technology Inc. N+1 N+2 Set by hardware on falling edge of TxGVAL Datasheet Preliminary Cleared by software DS40001996C-page 330 PIC18F26/45/46Q10 Timer1 Module with Gate Control Figure 19-7. TIMER1 GATE SINGLE PULSE AND TOGGLE COMBINED MODE Rev. 30-000140A 5/25/2017 TMRxGE TxGPOL TxGSPM TxGTM TxGGO/ Cleared by hardware on falling edge of TxGVAL Set by software DONE Counting enabled on rising edge of TxG TxG_IN TxCKI TxGVAL TIMER1/3/5/7 TMRxGIF N Cleared by software N+1 N+2 N+3 Set by hardware on falling edge of TxGVAL N+4 Cleared by software 19.7.5 Timer1 Gate Value Status When Timer1 Gate Value Status is utilized, it is possible to read the most current level of the gate control value. The value is stored in the GVAL bit in the TxGCON register. The GVAL bit is valid even when the Timer1 gate is not enabled (GE bit is cleared). 19.7.6 Timer1 Gate Event Interrupt When Timer1 gate event interrupt is enabled, it is possible to generate an interrupt upon the completion of a gate event. When the falling edge of GVAL occurs, the TMRxGIF flag bit in the PIR5 register will be set. If the TMRxGIE bit in the PIE5 register is set, then an interrupt will be recognized. The TMRxGIF flag bit operates even when the Timer1 gate is not enabled (GE bit is cleared). For more information on selecting high or low priority status for the Timer1 gate event interrupt see the Interrupts chapter. Related Links 14.2 Interrupt Priority (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 331 PIC18F26/45/46Q10 Timer1 Module with Gate Control 19.8 Timer1 Interrupt The Timer1 register pair (TMRxH:TMRxL) increments to FFFFh and rolls over to 0000h. When Timer1 rolls over, the Timer1 interrupt flag bit of the PIRx register is set. To enable the interrupt-on-rollover, the following bits must be set: * * * * TMRxON bit of the TxCON register TMRxIE bits of the PIEx register PEIE/GIEL bit of the INTCON register GIE/GIEH bit of the INTCON register The interrupt is cleared by clearing the TMRxIF bit in the Interrupt Service Routine. For more information on selecting high or low priority status for the Timer1 overflow interrupt, see the Interrupts chapter. Important: The TMRxH:TMRxL register pair and the TMRxIF bit should be cleared before enabling interrupts. Related Links 14.2 Interrupt Priority 19.9 Timer1 Operation During Sleep Timer1 can only operate during Sleep when set up in Asynchronous Counter mode. In this mode, an external crystal or clock source can be used to increment the counter. To set up the timer to wake the device: * * * * * * TMRxON bit of the TxCON register must be set TMRxIE bit of the PIEx register must be set PEIE/GIEL bit of the INTCON register must be set TxSYNC bit of the TxCON register must be set Configure the TMRxCLK register for using secondary oscillator as the clock source Enable the SOSCEN bit of the OSCEN register The device will wake-up on an overflow and execute the next instruction. If the GIE/GIEH bit of the INTCON register is set, the device will call the Interrupt Service Routine. The secondary oscillator will continue to operate in Sleep regardless of the TxSYNC bit setting. 19.10 CCP Capture/Compare Time Base The CCP modules use the TMRxH:TMRxL register pair as the time base when operating in Capture or Compare mode. In Capture mode, the value in the TMRxH:TMRxL register pair is copied into the CCPRxH:CCPRxL register pair on a configured event. In Compare mode, an event is triggered when the value in the CCPRxH:CCPRxL register pair matches the value in the TMRxH:TMRxL register pair. This event can be a Special Event Trigger. (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 332 PIC18F26/45/46Q10 Timer1 Module with Gate Control For more information, see Capture/Compare/PWM Module(CCP) chapter. Related Links 21. Capture/Compare/PWM Module 19.11 CCP Special Event Trigger When any of the CCPs are configured to trigger a special event, the trigger will clear the TMRxH:TMRxL register pair. This special event does not cause a Timer1 interrupt. The CCP module may still be configured to generate a CCP interrupt. In this mode of operation, the CCPRxH:CCPRxL register pair becomes the period register for Timer1. Timer1 should be synchronized and FOSC/4 should be selected as the clock source in order to utilize the Special Event Trigger. Asynchronous operation of Timer1 can cause a Special Event Trigger to be missed. In the event that a write to TMRxH or TMRxL coincides with a Special Event Trigger from the CCP, the write will take precedence. 19.12 Peripheral Module Disable When a peripheral is not used or inactive, the module can be disabled by setting the Module Disable bit in the PMD registers. This will reduce power consumption to an absolute minimum. Setting the PMD bits holds the module in Reset and disconnects the module's clock source. The Module Disable bits for Timer1 (TMR1MD) are in the PMD1 register. See Peripheral Module Disable (PMD) chapter for more information. Related Links 7.3 Register Summary - PMD (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 333 PIC18F26/45/46Q10 Timer1 Module with Gate Control 19.13 Register Summary - Timer1 Address Name 0x0FC0 TMR5 0x0FC2 T5CON Bit Pos. 7:0 TMRxL[7:0] 15:8 TMRxH[7:0] 7:0 CKPS[1:0] 0x0FC3 T5GCON 7:0 0x0FC4 TMR5GATE 7:0 GSS[4:0] 0x0FC5 TMR5CLK 7:0 CS[4:0] 0x0FC6 TMR3 0x0FC8 T3CON GTM GSPM GGO/DONE 7:0 TMRxL[7:0] TMRxH[7:0] 7:0 0x0FC9 T3GCON 7:0 TMR3GATE 7:0 0x0FCB TMR3CLK 7:0 TMR1 GPOL 15:8 0x0FCA 0x0FCC GE SYNC CKPS[1:0] GE GPOL GTM GGO/DONE RD16 ON RD16 ON GVAL GSS[4:0] CS[4:0] 7:0 TMRxL[7:0] 15:8 TMRxH[7:0] 0x0FCE T1CON 7:0 0x0FCF T1GCON 7:0 0x0FD0 TMR1GATE 7:0 GSS[4:0] 0x0FD1 TMR1CLK 7:0 CS[4:0] 19.14 ON GVAL SYNC GSPM RD16 CKPS[1:0] GE GPOL GTM GSPM SYNC GGO/DONE GVAL Register Definitions: Timer1 Long bit name prefixes for the odd numbered timers is shown in the following table. Refer to the "Long Bit Names" section for more information. Table 19-5. Timer1 prefixes Peripheral Bit Name Prefix Timer1 T1 Timer3 T3 Timer5 T5 Related Links 1.4.2.2 Long Bit Names (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 334 PIC18F26/45/46Q10 Timer1 Module with Gate Control 19.14.1 TxCON Name: Address: TxCON 0xFCE,0xFC8,0xFC2 Timer Control Register Bit 7 6 5 4 3 CKPS[1:0] Access Reset 2 1 0 SYNC RD16 ON R/W R/W R/W R/W R/W 0 0 0 0 0 Bits 5:4 - CKPS[1:0] Timer Input Clock Prescale Select bits Reset States: POR/BOR = 00 All Other Resets = uu Value Description 11 1:8 Prescale value 10 1:4 Prescale value 01 1:2 Prescale value 00 1:1 Prescale value Bit 2 - SYNC Timer External Clock Input Synchronization Control bit Reset States: POR/BOR = 0 All Other Resets = u Value Condition Description X CS = FOSC/4 or FOSC This bit is ignored. Timer uses the incoming clock as is. 1 Else Do not synchronize external clock input 0 Else Synchronize external clock input with system clock Bit 1 - RD16 16-Bit Read/Write Mode Enable bit Reset States: POR/BOR = 0 All Other Resets = u Value Description 1 Enables register read/write of Timer in one 16-bit operation 0 Enables register read/write of Timer in two 8-bit operations Bit 0 - ON Timer On bit Reset States: POR/BOR = 0 All Other Resets = u Value Description 1 Enables Timer 0 Disables Timer (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 335 PIC18F26/45/46Q10 Timer1 Module with Gate Control 19.14.2 TxGCON Name: Address: TxGCON 0xFCF,0xFC9,0xFC3 Timer Gate Control Register Bit Access Reset 7 6 5 4 3 2 GE GPOL GTM GSPM GGO/DONE GVAL R/W R/W R/W R/W R/W RO 0 0 0 0 0 x 1 0 Bit 7 - GE Timer Gate Enable bit Reset States: POR/BOR = 0 All Other Resets = u Value Condition Description 1 ON = 1 Timer counting is controlled by the Timer gate function 0 ON = 1 Timer is always counting X ON = 0 This bit is ignored Bit 6 - GPOL Timer Gate Polarity bit Reset States: POR/BOR = 0 All Other Resets = u Value Description 1 Timer gate is active-high (Timer counts when gate is high) 0 Timer gate is active-low (Timer counts when gate is low) Bit 5 - GTM Timer Gate Toggle Mode bit Timer Gate Flip-Flop Toggles on every rising edge when Toggle mode is enabled. Reset States: POR/BOR = 0 All Other Resets = u Value Description 1 Timer Gate Toggle mode is enabled 0 Timer Gate Toggle mode is disabled and Toggle flip-flop is cleared Bit 4 - GSPM Timer Gate Single Pulse Mode bit Reset States: POR/BOR = 0 All Other Resets = u Value Description 1 Timer Gate Single Pulse mode is enabled and is controlling Timer gate) 0 Timer Gate Single Pulse mode is disabled Bit 3 - GGO/DONE Timer Gate Single Pulse Acquisition Status bit This bit is automatically cleared when TxGSPM is cleared. Reset States: POR/BOR = 0 All Other Resets = u Value Description 1 Timer Gate Single Pulse Acquisition is ready, waiting for an edge 0 Timer Gate Single Pulse Acquisition has completed or has not been started. (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 336 PIC18F26/45/46Q10 Timer1 Module with Gate Control Bit 2 - GVAL Timer Gate Current State bit Indicates the current state of the timer gate that could be provided to TMRxH:TMRxL Unaffected by Timer Gate Enable (TMRxGE) (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 337 PIC18F26/45/46Q10 Timer1 Module with Gate Control 19.14.3 TMRxCLK Name: Address: TMRxCLK 0xFD1,0xFCB,0xFC5 Timer Clock Source Selection Register Bit 7 6 5 4 3 2 1 0 CS[4:0] Access Reset R/W R/W R/W R/W R/W 0 0 0 0 0 Bits 4:0 - CS[4:0] Timer Clock Source Selection bits Refer to the clock source selection table. Reset States: POR/BOR = 00000 All Other Resets = uuuuu (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 338 PIC18F26/45/46Q10 Timer1 Module with Gate Control 19.14.4 TMRxGATE Name: Address: TMRxGATE 0xFD0,0xFCA,0xFC4 Timer Gate Source Selection Register Bit 7 6 5 4 3 2 1 0 GSS[4:0] Access Reset R/W R/W R/W R/W R/W 0 0 0 0 0 Bits 4:0 - GSS[4:0] Timer Gate Source Selection bits Refer to the gate source selection table. Reset States: POR/BOR = 00000 All Other Resets = uuuuu (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 339 PIC18F26/45/46Q10 Timer1 Module with Gate Control 19.14.5 TMRx Name: Address: TMRx 0xFCC,0xFC6,0xFC0 Timer Low Byte Register Bit 15 14 13 12 11 10 9 8 TMRxH[7:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 TMRxL[7:0] Access Reset Bits 15:8 - TMRxH[7:0] Timer Most Significant Byte Reset States: POR/BOR = 00000000 All Other Resets = uuuuuuuu Bits 7:0 - TMRxL[7:0] Timer Least Significant Byte Reset States: POR/BOR = 00000000 All Other Resets = uuuuuuuu (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 340 PIC18F26/45/46Q10 Timer2 Module 20. Timer2 Module The Timer2 module is a 8-bit timer that incorporates the following features: * * * * * * * * * * * 8-Bit Timer and Period Registers Readable and Writable Software Programmable Prescaler (1:1 to 1:128) Software Programmable Postscaler (1:1 to 1:16) Interrupt on T2TMR Match with T2PR One-Shot Operation Full Asynchronous Operation Includes Hardware Limit Timer (HLT) Alternate Clock Sources External Timer Reset Signal Sources Configurable Timer Reset Operation See Figure 20-1 for a block diagram of Timer2. See table below for the clock source selections. Important: References to module Timer2 apply to all the even numbered timers on this device. (Timer2, Timer4, etc.) (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 341 PIC18F26/45/46Q10 Timer2 Module Figure 20-1. Timer2 with Hardware Limit Timer (HLT) Block Diagram RSEL <4:0> INPPS TxIN PPS External Reset (2) Sources Rev. 10-000168C 9/10/2015 MODE<4:0> TMRx_ers Edge Detector Level Detector Mode Control (2 clock Sync) MODE<3> reset CCP_pset(1) MODE<4:3>=01 enable D MODE<4:1>=1011 Q Clear ON CPOL Prescaler TMRx_clk 3 CKPS<2:0> ON Sync (2 Clocks) 0 Sync 1 Fosc/4 PSYNC TxTMR R Comparator Set flag bit TMRxIF Postscaler TMRx_postscaled 4 1 TxPR OUTPS<3:0> 0 CSYNC Note: 1. Signal to the CCP to trigger the PWM pulse. 2. See TxRST for external Reset sources. Table 20-1. Clock Source Selection Clock Source CS<4:0> Timer2 Timer4 Timer6 11111-11000 Reserved Reserved Reserved 10111 CLC8_out CLC8_out CLC8_out 10110 CLC7_out CLC7_out CLC7_out 10101 CLC6_out CLC6_out CLC6_out 10100 CLC5_out CLC5_out CLC5_out 10011 CLC4_out CLC4_out CLC4_out 10010 CLC3_out CLC3_out CLC3_out 10001 CLC2_out CLC2_out CLC2_out 10000 CLC1_out CLC1_out CLC1_out (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 342 PIC18F26/45/46Q10 Timer2 Module ...........continued Clock Source CS<4:0> 20.1 Timer2 Timer4 Timer6 01111-01001 Reserved Reserved Reserved 01000 ZCD_OUT ZCD_OUT ZCD_OUT 00111 CLKREF_OUT CLKREF_OUT CLKREF_OUT 00110 SOSC SOSC SOSC 00101 MFINTOSC (31 kHz) MFINTOSC (31 kHz) MFINTOSC (31 kHz) 00100 LFINTOSC LFINTOSC LFINTOSC 00011 HFINTOSC HFINTOSC HFINTOSC 00010 FOSC FOSC FOSC 00001 FOSC/4 FOSC/4 FOSC/4 00000 Pin selected by T2INPPS Pin selected by T4INPPS Pin selected by T6INPPS Timer2 Operation Timer2 operates in three major modes: * Free Running Period * One-shot * Monostable Within each mode there are several options for starting, stopping, and reset. Table 20-3 lists the options. In all modes, the T2TMR count register is incremented on the rising edge of the clock signal from the programmable prescaler. When T2TMR equals T2PR, a high level is output to the postscaler counter. T2TMR is cleared on the next clock input. An external signal from hardware can also be configured to gate the timer operation or force a T2TMR count Reset. In Gate modes the counter stops when the gate is disabled and resumes when the gate is enabled. In Reset modes the T2TMR count is reset on either the level or edge from the external source. The T2TMR and T2PR registers are both directly readable and writable. The T2TMR register is cleared and the T2PR register initializes to FFh on any device Reset. Both the prescaler and postscaler counters are cleared on the following events: * * * * A write to the T2TMR register A write to the T2CON register Any device Reset External Reset Source event that resets the timer. Important: T2TMR is not cleared when T2CON is written. (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 343 PIC18F26/45/46Q10 Timer2 Module 20.1.1 Free-Running Period Mode The value of T2TMR is compared to that of the Period register, T2PR, on each clock cycle. When the two values match, the comparator resets the value of T2TMR to 00h on the next cycle and increments the output postscaler counter. When the postscaler count equals the value in the OUTPS bits of the T2CON register then a one clock period wide pulse occurs on the TMR2_postscaled output, and the postscaler count is cleared. 20.1.2 One-Shot Mode The One-Shot mode is identical to the Free-Running Period mode except that the ON bit is cleared and the timer is stopped when T2TMR matches T2PR and will not restart until the ON bit is cycled off and on. Postscaler (OUTPS) values other than zero are ignored in this mode because the timer is stopped at the first period event and the postscaler is reset when the timer is restarted. 20.1.3 Monostable Mode Monostable modes are similar to One-Shot modes except that the ON bit is not cleared and the timer can be restarted by an external Reset event. 20.2 Timer2 Output The Timer2 module's primary output is TMR2_postscaled, which pulses for a single TMR2_clk period upon each match of the postscaler counter and the OUTPS bits of the T2CON register. The postscaler is incremented each time the T2TMR value matches the T2PR value. This signal can be selected as an input to several other input modules: * * * * * * The ADC module, as an auto-conversion trigger CWG, as an auto-shutdown source The CRC memory scanner, as a trigger for triggered mode Gate source for odd numbered timers (Timer1, Timer3, etc.) Alternate SPI clock Reset signals for other instances of even numbered timers (Timer2, Timer4, etc.) In addition, the Timer2 is also used by the CCP module for pulse generation in PWM mode. See "PWM Overview" and "Pulse-width Modulation" sections for more details on setting up Timer2 for use with the CCP and PWM modules. Related Links 21.4 PWM Overview 22. (PWM) Pulse-Width Modulation 20.3 External Reset Sources In addition to the clock source, the Timer2 also takes in an external Reset source. This external Reset source is selected for each timer with the corresponding TxRST register. This source can control starting and stopping of the timer, as well as resetting the timer, depending on which mode the timer is in. Reset source selections are shown in the following table. (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 344 PIC18F26/45/46Q10 Timer2 Module Table 20-2. External Reset Sources Reset Source RSEL[4:0] 20.4 TMR2 TMR4 TMR6 11000-11111 Reserved Reserved Reserved 10111 CLC8_out CLC8_out CLC8_out 10110 CLC7_out CLC7_out CLC7_out 10101 CLC6_out CLC6_out CLC6_out 10100 CLC5_out CLC5_out CLC5_out 10011 CLC4_out CLC4_out CLC4_out 10010 CLC3_out CLC3_out CLC3_out 10001 CLC2_out CLC2_out CLC2_out 10000 CLC1_out CLC1_out CLC1_out 01111 EUSART2 TX/CK EUSART2 TX/CK EUSART2 TX/CK 01110 EUSART2 DT EUSART2 DT EUSART2 DT 01101 EUSART1 TX/CK EUSART1 TX/CK EUSART1 TX/CK 01100 EUSART1 DT EUSART1 DT EUSART1 DT 01011 Reserved Reserved Reserved 01010 ZCD_OUT ZCD_OUT ZCD_OUT 1001 CMP2OUT CMP2OUT CMP2OUT 01000 CMP1OUT CMP1OUT CMP1OUT 00111 PWM4OUT PWM4OUT PWM4OUT 00110 PWM3OUT PWM3OUT PWM3OUT 00101 CCP2OUT CCP2OUT CCP2OUT 00100 CCP1OUT CCP1OUT CCP1OUT 00011 TMR6 post-scaled TMR6 post-scaled Reserved 00010 TMR4 post-scaled Reserved TMR4 post-scaled 00001 Reserved TMR2 post-scaled TMR2 post-scaled 00000 Pin selected by T2INPPS Pin selected by T4INPPS Pin selected by T6INPPS Timer2 Interrupt Timer2 can also generate a device interrupt. The interrupt is generated when the postscaler counter matches with the selected postscaler value (OUTPS bits of T2CON register). The interrupt is enabled by setting the TMR2IE interrupt enable bit. Interrupt timing is illustrated in the figure below. (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 345 PIC18F26/45/46Q10 Timer2 Module Figure 20-2. Timer2 Prescaler, Postscaler, and Interrupt Timing Diagram Rev. 10-000205A 4/7/2016 0b010 CKPS PRx 1 OUTPS 0b0001 TMRx_clk TMRx 0 1 0 1 0 1 0 TMRx_postscaled TMRxIF (1) (2) (1) Note: 1. Setting the interrupt flag is synchronized with the instruction clock. 2. Cleared by software. 20.5 Operating Modes The mode of the timer is controlled by the MODE bits of the T2HLT register. Edge-Triggered modes require six Timer clock periods between external triggers. Level-Triggered modes require the triggering level to be at least three Timer clock periods long. External triggers are ignored while in Debug mode. (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 346 PIC18F26/45/46Q10 Timer2 Module Table 20-3. Operating Modes Table Mode FreeRunning Period MODE<4:0> <4:3> <2:0> 00 Output Operation Operation Timer Control Start Reset Stop 000 Software gate (Figure 20-3) ON = 1 -- ON = 0 ON = 1 and TMRx_ers = 1 -- 001 Hardware gate, activehigh (Figure 20-4) ON = 0 or TMRx_ers = 0 ON = 1 and TMRx_ers = 0 -- 010 Hardware gate, activelow ON = 0 or TMRx_ers = 1 011 Rising or falling edge Reset TMRx_ers Rising edge Reset (Figure 20-5) TMRx_ers 100 101 110 111 (c) 2019 Microchip Technology Inc. Period Pulse Period Pulse with Hardware Reset Falling edge Reset ON = 1 TMRx_ers Low level Reset TMRx_ers =0 High level Reset (Figure 20-6) TMRx_ers =1 Datasheet Preliminary ON = 0 ON = 0 or TMRx_ers = 0 ON = 0 or TMRx_ers = 1 DS40001996C-page 347 PIC18F26/45/46Q10 Timer2 Module ...........continued Mode MODE<4:0> <4:3> <2:0> Output Operation Timer Control Start Reset Software start (Figure 20-7) ON = 1 -- Rising edge start (Figure 20-8) ON = 1 and TMRx_ers -- Falling edge start ON = 1 and TMRx_ers -- 011 Any edge start ON = 1 and TMRx_ers -- 100 Rising edge start and Rising edge Reset (Figure 20-9) ON = 1 and TMRx_ers TMRx_ers 000 One-shot 001 010 EdgeTriggered Start (Note 1) One-shot Operation 01 101 EdgeTriggered Start and 110 111 (c) 2019 Microchip Technology Inc. Hardware Reset (Note 1) Stop ON = 0 or Next clock after TMRx = PRx Falling edge start and Falling edge Reset ON = 1 and TMRx_ers TMRx_ers Rising edge start and Low level Reset (Figure 20-10) ON = 1 and TMRx_ers TMRx_ers =0 Falling edge start and High level Reset ON = 1 and TMRx_ers TMRx_ers =1 Datasheet Preliminary (Note 2) DS40001996C-page 348 PIC18F26/45/46Q10 Timer2 Module ...........continued Mode MODE<4:0> <4:3> <2:0> Output Operation Operation 000 001 Monostable 010 EdgeTriggered Start 011 10 Reserved Level Triggered and xxx ON = 0 or ON = 1 and TMRx_ers -- Any edge start ON = 1 and TMRx_ers -- Reserved Start 11 -- Falling edge start 101 111 Stop ON = 1 and TMRx_ers Reserved One-shot Reset Rising edge start (Figure 20-11) 100 110 Reserved Start Reserved (Note 1) Reserved Timer Control Hardware Reset High level start and Low level Reset (Figure 20-12) ON = 1 and TMRx_ers = 1 Low level start and High level Reset ON = 1 and TMRx_ers = 0 Next clock after TMRx = PRx (Note 3) TMRx_ers =0 ON = 0 or Held in Reset (Note 2) TMRx_ers =1 Reserved Note: 1. If ON = 0 then an edge is required to restart the timer after ON = 1. 2. 3. 20.6 When T2TMR = T2PR then the next clock clears ON and stops T2TMR at 00h. When T2TMR = T2PR then the next clock stops T2TMR at 00h but does not clear ON. Operation Examples Unless otherwise specified, the following notes apply to the following timing diagrams: * Both the prescaler and postscaler are set to 1:1 (both the CKPS and OUTPS bits in the T2CON register are cleared). * The diagrams illustrate any clock except FOSC/4 and show clock-sync delays of at least two full cycles for both ON and Timer2_ers. When using FOSC/4, the clock-sync delay is at least one instruction period for Timer2_ers; ON applies in the next instruction period. * ON and Timer2_ers are somewhat generalized, and clock-sync delays may produce results that are slightly different than illustrated. (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 349 PIC18F26/45/46Q10 Timer2 Module * The PWM Duty Cycle and PWM output are illustrated assuming that the timer is used for the PWM function of the CCP module as described in the "PWM Overview" section. The signals are not a part of the Timer2 module. Related Links 21.4 PWM Overview 22. (PWM) Pulse-Width Modulation 20.6.1 Software Gate Mode This mode corresponds to legacy Timer2 operation. The timer increments with each clock input when ON = 1 and does not increment when ON = 0. When the TMRx count equals the PRx period count the timer resets on the next clock and continues counting from 0. Operation with the ON bit software controlled is illustrated in Figure 20-3. With PRx = 5, the counter advances until TMRx = 5, and goes to zero with the next clock. Figure 20-3. Software Gate Mode Timing Diagram (MODE = 00000) Rev. 10-000195B 5/30/2014 0b00000 MODE TMRx_clk Instruction(1) BSF BCF BSF ON PRx TMRx 5 0 1 2 3 4 5 0 1 2 3 4 5 0 1 2 3 4 5 0 1 TMRx_postscaled PWM Duty Cycle 3 PWM Output Note: 1. BSF and BCF represent Bit-Set File and Bit-Clear File instructions executed by the CPU to set or clear the ON bit of TxCON. CPU execution is asynchronous to the timer clock input. Related Links 21.4 PWM Overview 22. (PWM) Pulse-Width Modulation 20.6.2 Hardware Gate Mode The Hardware Gate modes operate the same as the Software Gate mode except the TMRx_ers external signal can also gate the timer. When used with the CCP, the gating extends the PWM period. If the timer is stopped when the PWM output is high, then the duty cycle is also extended. When MODE<4:0> = 00001 then the timer is stopped when the external signal is high. When MODE<4:0> = 00010, then the timer is stopped when the external signal is low. (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 350 PIC18F26/45/46Q10 Timer2 Module Figure 20-4 illustrates the Hardware Gating mode for MODE<4:0> = 00001 in which a high input level starts the counter. Figure 20-4. Hardware Gate Mode Timing Diagram (MODE = 00001) Rev. 10-000 196B 5/30/201 4 MODE 0b00001 TMRx_clk TMRx_ers 5 PRx TMRx 0 1 2 3 4 5 0 1 2 3 4 5 0 1 TMRx_postscaled PWM Duty Cycle 3 PWM Output Related Links 21.4 PWM Overview 22. (PWM) Pulse-Width Modulation 20.6.3 Edge-Triggered Hardware Limit Mode In Hardware Limit mode, the timer can be reset by the TMRx_ers external signal before the timer reaches the period count. Three types of Resets are possible: * Reset on rising or falling edge (MODE<4:0>= 00011) * Reset on rising edge (MODE<4:0> = 00100) * Reset on falling edge (MODE<4:0> = 00101) When the timer is used in conjunction with the CCP in PWM mode then an early Reset shortens the period and restarts the PWM pulse after a two clock delay. Refer to Figure 20-5. (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 351 PIC18F26/45/46Q10 Timer2 Module Figure 20-5. Edge-Triggered Hardware Limit Mode Timing Diagram (MODE = 00100) Rev. 10-000 197B 5/30/201 4 0b00100 MODE TMRx_clk PRx 5 Instruction(1) BSF BCF BSF ON TMRx_ers TMRx 0 1 2 0 1 2 3 4 5 0 1 2 3 4 5 0 1 TMRx_postscaled PWM Duty Cycle 3 PWM Output Note: 1. BSF and BCF represent Bit-Set File and Bit-Clear File instructions executed by the CPU to set or clear the ON bit of TxCON. CPU execution is asynchronous to the timer clock input. Related Links 21.4 PWM Overview 22. (PWM) Pulse-Width Modulation 20.6.4 Level-Triggered Hardware Limit Mode In the Level-Triggered Hardware Limit Timer modes the counter is reset by high or low levels of the external signal TMRx_ers, as shown in Figure 20-6. Selecting MODE<4:0> = 00110 will cause the timer to reset on a low level external signal. Selecting MODE<4:0> = 00111 will cause the timer to reset on a high level external signal. In the example, the counter is reset while TMRx_ers = 1. ON is controlled by BSF and BCF instructions. When ON = 0 the external signal is ignored. When the CCP uses the timer as the PWM time base then the PWM output will be set high when the timer starts counting and then set low only when the timer count matches the CCPRx value. The timer is reset when either the timer count matches the PRx value or two clock periods after the external Reset signal goes true and stays true. The timer starts counting, and the PWM output is set high, on either the clock following the PRx match or two clocks after the external Reset signal relinquishes the Reset. The PWM output will remain high until the timer counts up to match the CCPRx pulse width value. If the external Reset signal goes true while the PWM output is high then the PWM output will remain high until the Reset signal is released allowing the timer to count up to match the CCPRx value. (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 352 PIC18F26/45/46Q10 Timer2 Module Figure 20-6. Level-Triggered Hardware Limit Mode Timing Diagram (MODE = 00111) Rev. 10-000198B 5/30/2014 MODE 0b00111 TMRx_clk 5 PRx Instruction(1) BSF BCF BSF ON TMRx_ers TMRx 0 1 2 0 1 2 3 4 5 0 0 1 2 3 4 5 0 TMRx_postscaled PWM Duty Cycle 3 PWM Output Note: 1. BSF and BCF represent Bit-Set File and Bit-Clear File instructions executed by the CPU to set or clear the ON bit of TxCON. CPU execution is asynchronous to the timer clock input. Related Links 21.4 PWM Overview 22. (PWM) Pulse-Width Modulation 20.6.5 Software Start One-Shot Mode In One-Shot mode the timer resets and the ON bit is cleared when the timer value matches the PRx period value. The ON bit must be set by software to start another timer cycle. Setting MODE<4:0> = 01000 selects One-Shot mode which is illustrated in Figure 20-7. In the example, ON is controlled by BSF and BCF instructions. In the first case, a BSF instruction sets ON and the counter runs to completion and clears ON. In the second case, a BSF instruction starts the cycle, BCF/BSF instructions turn the counter off and on during the cycle, and then it runs to completion. When One-Shot mode is used in conjunction with the CCP PWM operation the PWM pulse drive starts concurrent with setting the ON bit. Clearing the ON bit while the PWM drive is active will extend the PWM drive. The PWM drive will terminate when the timer value matches the CCPRx pulse width value. The PWM drive will remain off until software sets the ON bit to start another cycle. If software clears the ON bit after the CCPRx match but before the PRx match then the PWM drive will be extended by the length of time the ON bit remains cleared. Another timing cycle can only be initiated by setting the ON bit after it has been cleared by a PRx period count match. (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 353 PIC18F26/45/46Q10 Timer2 Module Figure 20-7. Software Start One-Shot Mode Timing Diagram (MODE = 01000) Rev. 10-000199B 4/7/2016 MODE 0b01000 TMRx_clk 5 PRx Instruction(1) BSF BSF BCF BSF ON TMRx 0 1 2 3 4 5 0 1 2 3 4 5 0 TMRx_postscaled PWM Duty Cycle 3 PWM Output Note: 1. BSF and BCF represent Bit-Set File and Bit-Clear File instructions executed by the CPU to set or clear the ON bit of TxCON. CPU execution is asynchronous to the timer clock input. Related Links 21.4 PWM Overview 22. (PWM) Pulse-Width Modulation 20.6.6 Edge-Triggered One-Shot Mode The Edge-Triggered One-Shot modes start the timer on an edge from the external signal input, after the ON bit is set, and clear the ON bit when the timer matches the PRx period value. The following edges will start the timer: * Rising edge (MODE<4:0> = 01001) * Falling edge (MODE<4:0> = 01010) * Rising or Falling edge (MODE<4:0> = 01011) If the timer is halted by clearing the ON bit then another TMRx_ers edge is required after the ON bit is set to resume counting. Figure 20-8 illustrates operation in the rising edge One-Shot mode. When Edge-Triggered One-Shot mode is used in conjunction with the CCP then the edge-trigger will activate the PWM drive and the PWM drive will deactivate when the timer matches the CCPRx pulse width value and stay deactivated when the timer halts at the PRx period count match. (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 354 PIC18F26/45/46Q10 Timer2 Module Figure 20-8. Edge-Triggered One-Shot Mode Timing Diagram (MODE = 01001) Rev. 10-000200B 5/19/2016 MODE 0b01001 TMRx_clk 5 PRx Instruction(1) BSF BSF BCF ON TMRx_ers TMRx 0 1 2 3 4 5 0 1 2 CCP_pset TMRx_postscaled PWM Duty Cycle 3 PWM Output Note: 1. BSF and BCF represent Bit-Set File and Bit-Clear File instructions executed by the CPU to set or clear the ON bit of TxCON. CPU execution is asynchronous to the timer clock input. Related Links 21.4 PWM Overview 22. (PWM) Pulse-Width Modulation 20.6.7 Edge-Triggered Hardware Limit One-Shot Mode In Edge-Triggered Hardware Limit One-Shot modes the timer starts on the first external signal edge after the ON bit is set and resets on all subsequent edges. Only the first edge after the ON bit is set is needed to start the timer. The counter will resume counting automatically two clocks after all subsequent external Reset edges. Edge triggers are as follows: * Rising edge start and Reset (MODE<4:0> = 01100) * Falling edge start and Reset (MODE<4:0> = 01101) The timer resets and clears the ON bit when the timer value matches the PRx period value. External signal edges will have no effect until after software sets the ON bit. Figure 20-9 illustrates the rising edge hardware limit one-shot operation. When this mode is used in conjunction with the CCP then the first starting edge trigger, and all subsequent Reset edges, will activate the PWM drive. The PWM drive will deactivate when the timer matches the CCPRx pulse-width value and stay deactivated until the timer halts at the PRx period match unless an external signal edge resets the timer before the match occurs. (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 355 PIC18F26/45/46Q10 Timer2 Module Figure 20-9. Edge-Triggered Hardware Limit One-Shot Mode Timing Diagram (MODE = 01100) Rev. 10-000201B 4/7/2016 0b01100 MODE TMRx_clk 5 PRx Instruction(1) BSF BSF ON TMRx_ers TMRx 0 1 2 3 4 5 0 1 2 0 1 2 3 4 5 0 TMRx_postscaled PWM Duty Cycle 3 PWM Output Note: 1. BSF and BCF represent Bit-Set File and Bit-Clear File instructions executed by the CPU to set or clear the ON bit of TxCON. CPU execution is asynchronous to the timer clock input. Related Links 21.4 PWM Overview 22. (PWM) Pulse-Width Modulation 20.6.8 Level Reset, Edge-Triggered Hardware Limit One-Shot Modes In Level -Triggered One-Shot mode the timer count is reset on the external signal level and starts counting on the rising/falling edge of the transition from Reset level to the active level while the ON bit is set. Reset levels are selected as follows: * Low Reset level (MODE<4:0> = 01110) * High Reset level (MODE<4:0> = 01111) When the timer count matches the PRx period count, the timer is reset and the ON bit is cleared. When the ON bit is cleared by either a PRx match or by software control, a new external signal edge is required after the ON bit is set to start the counter. When Level-Triggered Reset One-Shot mode is used in conjunction with the CCP PWM operation, the PWM drive goes active with the external signal edge that starts the timer. The PWM drive goes inactive when the timer count equals the CCPRx pulse width count. The PWM drive does not go active when the timer count clears at the PRx period count match. (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 356 PIC18F26/45/46Q10 Timer2 Module Figure 20-10. Low Level Reset, Edge-Triggered Hardware Limit One-Shot Mode Timing Diagram (MODE = 01110) Rev. 10-000202B 4/7/2016 0b01110 MODE TMRx_clk PRx Instruction(1) 5 BSF BSF ON TMRx_ers TMRx 0 1 2 3 4 5 0 1 0 1 2 3 4 5 0 TMRx_postscaled PWM Duty Cycle 3 PWM Output Note: 1. BSF and BCF represent Bit-Set File and Bit-Clear File instructions executed by the CPU to set or clear the ON bit of TxCON. CPU execution is asynchronous to the timer clock input. Related Links 21.4 PWM Overview 22. (PWM) Pulse-Width Modulation 20.6.9 Edge-Triggered Monostable Modes The Edge-Triggered Monostable modes start the timer on an edge from the external Reset signal input, after the ON bit is set, and stop incrementing the timer when the timer matches the PRx period value. The following edges will start the timer: * Rising edge (MODE<4:0> = 10001) * Falling edge (MODE<4:0> = 10010) * Rising or Falling edge (MODE<4:0> = 10011) When an Edge-Triggered Monostable mode is used in conjunction with the CCP PWM operation, the PWM drive goes active with the external Reset signal edge that starts the timer, but will not go active when the timer matches the PRx value. While the timer is incrementing, additional edges on the external Reset signal will not affect the CCP PWM. (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 357 PIC18F26/45/46Q10 Timer2 Module Figure 20-11. Rising Edge-Triggered Monostable Mode Timing Diagram (MODE = 10001) Rev. 10-000203A 4/7/2016 0b10001 MODE TMRx_clk PRx Instruction(1) 5 BSF BCF BSF BCF BSF ON TMRx_ers TMRx 0 1 2 3 4 5 0 1 2 3 4 5 0 1 2 3 4 5 0 TMRx_postscaled PWM Duty Cycle 3 PWM Output Note: 1. BSF and BCF represent Bit-Set File and Bit-Clear File instructions executed by the CPU to set or clear the ON bit of TxCON. CPU execution is asynchronous to the timer clock input. Related Links 21.4 PWM Overview 22. (PWM) Pulse-Width Modulation 20.6.10 Level-Triggered Hardware Limit One-Shot Modes The Level-Triggered Hardware Limit One-Shot modes hold the timer in Reset on an external Reset level and start counting when both the ON bit is set and the external signal is not at the Reset level. If one of either the external signal is not in Reset or the ON bit is set, then the other signal being set/made active will start the timer. Reset levels are selected as follows: * Low Reset level (MODE<4:0> = 10110) * High Reset level (MODE<4:0> = 10111) When the timer count matches the PRx period count, the timer is reset and the ON bit is cleared. When the ON bit is cleared by either a PRx match or by software control, the timer will stay in Reset until both the ON bit is set and the external signal is not at the Reset level. When Level-Triggered Hardware Limit One-Shot modes are used in conjunction with the CCP PWM operation, the PWM drive goes active with either the external signal edge or the setting of the ON bit, whichever of the two starts the timer. (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 358 PIC18F26/45/46Q10 Timer2 Module Figure 20-12. Level-Triggered hardware Limit one-Shot Mode Timing Diagram (MODE = 10110) Rev. 10-000204A 4/7/2016 0b10110 MODE TMR2_clk 5 PRx Instruction(1) BSF BSF BCF BSF ON TMR2_ers TMRx 0 1 2 3 4 5 0 1 2 3 0 1 2 3 4 5 0 TMR2_postscaled PWM Duty Cycle `D3 PWM Output Note: 1. BSF and BCF represent Bit-Set File and Bit-Clear File instructions executed by the CPU to set or clear the ON bit of TxCON. CPU execution is asynchronous to the timer clock input. Related Links 21.4 PWM Overview 22. (PWM) Pulse-Width Modulation 20.7 Timer2 Operation During Sleep When PSYNC = 1, Timer2 cannot be operated while the processor is in Sleep mode. The contents of the T2TMR and T2PR registers will remain unchanged while processor is in Sleep mode. When PSYNC = 0, Timer2 will operate in Sleep as long as the clock source selected is also still running. If any internal oscillator is selected as the clock source, it will stay active during Sleep mode. (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 359 PIC18F26/45/46Q10 Timer2 Module 20.8 Register Summary - Timer2 Address Name Bit Pos. 0x0FAE T6TMR 7:0 0x0FAF T6PR 7:0 0x0FB0 T6CON 7:0 ON 0x0FB1 T6HLT 7:0 PSYNC 0x0FB2 T6CLKCON 7:0 CS[4:0] 0x0FB3 T6RST 7:0 RSEL[4:0] TxTMR[7:0] TxPR[7:0] 0x0FB4 T4TMR 7:0 0x0FB5 T4PR 7:0 0x0FB6 T4CON 7:0 ON 0x0FB7 T4HLT 7:0 PSYNC 0x0FB8 T4CLKCON 7:0 CKPS[2:0] CPOL OUTPS[3:0] CSYNC MODE[4:0] TxTMR[7:0] TxPR[7:0] CKPS[2:0] CPOL OUTPS[3:0] CSYNC MODE[4:0] CS[4:0] 0x0FB9 T4RST 7:0 0x0FBA T2TMR 7:0 TxTMR[7:0] 0x0FBB T2PR 7:0 TxPR[7:0] 0x0FBC T2CON 7:0 ON 0x0FBD T2HLT 7:0 PSYNC 0x0FBE T2CLKCON 7:0 CS[4:0] 0x0FBF T2RST 7:0 RSEL[4:0] 20.9 RSEL[4:0] CKPS[2:0] CPOL OUTPS[3:0] CSYNC MODE[4:0] Register Definitions: Timer2 Control Long bit name prefixes for the Timer2 peripherals are shown in table below. Refer to Section "Long Bit Names" for more information. Table 20-4. Timer2 long bit name prefixes Peripheral Bit Name Prefix Timer2 T2 Timer4 T4 Timer6 T6 Notice: References to module Timer2 apply to all the even numbered timers on this device. (Timer2, Timer4, etc.) Related Links 1.4.2.2 Long Bit Names (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 360 PIC18F26/45/46Q10 Timer2 Module 20.9.1 TxTMR Name: Address: TxTMR 0xFBA,0xFB4,0xFAE Timer Counter Register Bit 7 6 5 4 3 2 1 0 TxTMR[7:0] Access Reset R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Bits 7:0 - TxTMR[7:0] Timerx Counter bits (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 361 PIC18F26/45/46Q10 Timer2 Module 20.9.2 TxPR Name: Address: TxPR 0xFBB,0xFB5,0xFAF Timer Period Register Bit 7 6 5 4 3 2 1 0 TxPR[7:0] Access Reset R/W R/W R/W R/W R/W R/W R/W R/W 1 1 1 1 1 1 1 1 Bits 7:0 - TxPR[7:0] Timer Period Register bits Value Description 0 - 255 The timer restarts at `0' when TxTMR reaches TxPR value (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 362 PIC18F26/45/46Q10 Timer2 Module 20.9.3 TxCON Name: Address: TxCON 0xFBC,0xFB6,0xFB0 Timerx Control Register Bit 7 6 ON Access Reset 5 4 3 2 CKPS[2:0] 1 0 OUTPS[3:0] R/W/HC R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Bit 7 - ON Timer On bit(1) Value Description 1 Timer is on 0 Timer is off: all counters and state machines are reset Bits 6:4 - CKPS[2:0] Timer Clock Prescale Select bits Value Description 111 1:128 Prescaler 110 1:64 Prescaler 101 1:32 Prescaler 100 1:16 Prescaler 011 1:8 Prescaler 010 1:4 Prescaler 001 1:2 Prescaler 000 1:1 Prescaler Bits 3:0 - OUTPS[3:0] Timer Output Postscaler Select bits Value Description 1111 1:16 Postscaler 1110 1:15 Postscaler 1101 1:14 Postscaler 1100 1:13 Postscaler 1011 1:12 Postscaler 1010 1:11 Postscaler 1001 1:10 Postscaler 1000 1:9 Postscaler 0111 1:8 Postscaler 0110 1:7 Postscaler 0101 1:6 Postscaler 0100 1:5 Postscaler 0011 1:4 Postscaler 0010 1:3 Postscaler 0001 1:2 Postscaler 0000 1:1 Postscaler (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 363 PIC18F26/45/46Q10 Timer2 Module Note: 1. In certain modes, the ON bit will be auto-cleared by hardware. See Table 20-3. (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 364 PIC18F26/45/46Q10 Timer2 Module 20.9.4 TxHLT Name: Address: TxHLT 0xFBD,0xFB7,0xFB1 Timer Hardware Limit Control Register Bit Access Reset 7 6 5 PSYNC CPOL CSYNC 4 3 R/W R/W R/W R/W R/W 0 0 0 0 0 2 1 0 R/W R/W R/W 0 0 0 MODE[4:0] Bit 7 - PSYNC Timer Prescaler Synchronization Enable bit(1, 2) Value Description 1 Timer Prescaler Output is synchronized to FOSC/4 0 Timer Prescaler Output is not synchronized to FOSC/4 Bit 6 - CPOL Timer Clock Polarity Selection bit(3) Value Description 1 Falling edge of input clock clocks timer/prescaler 0 Rising edge of input clock clocks timer/prescaler Bit 5 - CSYNC Timer Clock Synchronization Enable bit(4, 5) Value Description 1 ON bit is synchronized to timer clock input 0 ON bit is not synchronized to timer clock input Bits 4:0 - MODE[4:0] Timer Control Mode Selection bits(6, 7) Value Description 00000 See Table 20-3 to 11111 Note: 1. Setting this bit ensures that reading TxTMR will return a valid data value. 2. When this bit is `1', Timer cannot operate in Sleep mode. 3. CKPOL should not be changed while ON = 1. 4. 5. Setting this bit ensures glitch-free operation when the ON is enabled or disabled. When this bit is set then the timer operation will be delayed by two input clocks after the ON bit is set. Unless otherwise indicated, all modes start upon ON = 1 and stop upon ON = 0 (stops occur without affecting the value of TxTMR). When TxTMR = TxPR, the next clock clears TxTMR, regardless of the operating mode. 6. 7. (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 365 PIC18F26/45/46Q10 Timer2 Module 20.9.5 TxCLKCON Name: Address: TxCLKCON 0xFBE,0xFB8,0xFB2 Timer Clock Source Selection Register Bit 7 6 5 4 3 2 1 0 CS[4:0] Access Reset R/W R/W R/W R/W R/W 0 0 0 0 0 Bits 4:0 - CS[4:0] Timer Clock Source Selection bits Value Description n See Clock Source Selection table (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 366 PIC18F26/45/46Q10 Timer2 Module 20.9.6 TxRST Name: Address: TxRST 0xFBF,0xFB9,0xFB3 Timer External Reset Signal Selection Register Bit 7 6 5 4 3 2 1 0 RSEL[4:0] Access Reset R/W R/W R/W R/W R/W 0 0 0 0 0 Bits 4:0 - RSEL[4:0] External Reset Source Selection Bits Value Description n See External Reset Sources table (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 367 PIC18F26/45/46Q10 Capture/Compare/PWM Module 21. Capture/Compare/PWM Module The Capture/Compare/PWM module is a peripheral that allows the user to time and control different events, and to generate Pulse-Width Modulation (PWM) signals. In Capture mode, the peripheral allows the timing of the duration of an event. The Compare mode allows the user to trigger an external event when a predetermined amount of time has expired. The PWM mode can generate Pulse-Width Modulated signals of varying frequency and duty cycle. This family of devices contains two standard Capture/Compare/PWM modules (CCP1 and CCP2). Each individual CCP module can select the timer source that controls the module. Each module has an independent timer selection which can be accessed using the CxTSEL bits in the CCPTMRS register. The default timer selection is TMR1 when using Capture/Compare mode and T2TMR when using PWM mode in the CCPx module. It should be noted that the Capture/Compare mode operation is described with respect to TMR1 and the PWM mode operation is described with respect to T2TMR in the following sections. The Capture and Compare functions are identical for all CCP modules. Important: 1. In devices with more than one CCP module, it is very important to pay close attention to the register names used. A number placed after the module acronym is used to distinguish between separate modules. For example, the CCP1CON and CCP2CON control the same operational aspects of two completely different CCP modules. 2. Throughout this section, generic references to a CCP module in any of its operating modes may be interpreted as being equally applicable to CCPx module. Register names, module signals, I/O pins, and bit names may use the generic designator `x' to indicate the use of a numeral to distinguish a particular module, when required. 21.1 CCP Module Configuration Each Capture/Compare/PWM module is associated with a control register (CCPxCON), a capture input selection register (CCPxCAP) and a data register (CCPRx). The data register, in turn, is comprised of two 8-bit registers: CCPRxL (low byte) and CCPRxH (high byte). 21.1.1 CCP Modules and Timer Resources The CCP modules utilize Timers 1 through 6 that vary with the selected mode. Various timers are available to the CCP modules in Capture, Compare or PWM modes, as shown in the table below. Table 21-1. CCP Mode - Timer Resources CCP Mode Capture Compare PWM (c) 2019 Microchip Technology Inc. Timer Resource Timer1, Timer3 or Timer5 Timer2, Timer4 or Timer6 Datasheet Preliminary DS40001996C-page 368 PIC18F26/45/46Q10 Capture/Compare/PWM Module The assignment of a particular timer to a module is determined by the timer to CCP enable bits in the CCPTMRS register. All of the modules may be active at once and may share the same timer resource if they are configured to operate in the same mode (Capture/Compare or PWM) at the same time. 21.1.2 Open-Drain Output Option When operating in Output mode (the Compare or PWM modes), the drivers for the CCPx pins can be optionally configured as open-drain outputs. This feature allows the voltage level on the pin to be pulled to a higher level through an external pull-up resistor and allows the output to communicate with external circuits without the need for additional level shifters. 21.2 Capture Mode Capture mode makes use of the 16-bit odd numbered timer resources (Timer1, Timer3, etc.). When an event occurs on the capture source, the 16-bit CCPRx register captures and stores the 16-bit value of the TMRx register. An event is defined as one of the following and is configured by the MODE bits: * * * * * Every falling edge of CCPx input Every rising edge of CCPx input Every 4th rising edge of CCPx input Every 16th rising edge of CCPx input Every edge of CCPx input (rising or falling) When a capture is made, the Interrupt Request Flag bit CCPxIF of the PIRx register is set. The interrupt flag must be cleared in software. If another capture occurs before the value in the CCPRx register is read, the old captured value is overwritten by the new captured value. Important: If an event occurs during a 2-byte read, the high and low-byte data will be from different events. It is recommended while reading the CCPRxH:CCPRxL register pair to either disable the module or read the register pair twice for data integrity. The following figure shows a simplified diagram of the capture operation. Figure 21-1. Capture Mode Operation Block Diagram Rev. 10-000158E 6/26/2017 RxyPPS CCPx PPS CTS TRIS Control CCPRxH Capture Trigger Sources See CCPxCAP register Prescaler 1,4,16 and Edge Detect CCPRxL 16 set CCPxIF 16 CCPx PPS MODE <3:0> TMR1H TMR1L CCPxPPS (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 369 PIC18F26/45/46Q10 Capture/Compare/PWM Module 21.2.1 Capture Sources In Capture mode, the CCPx pin should be configured as an input by setting the associated TRIS control bit. Important: If the CCPx pin is configured as an output, a write to the port can cause a capture condition. The capture source is selected by configuring the CTS bits as shown in the following table: Table 21-2. Capture Trigger Sources 21.2.2 CTS Source 1111 CLC8_out 1110 CLC7_out 1101 CLC6_out 1100 CLC5_out 1011 CLC4_out 1010 CLC3_out 1001 CLC2_out 1000 CLC1_out 0100-0111 Reserved 0011 IOC Interrupt 0010 CMP2_output 0001 CMP1_output 0000 Pin selected by CCPxPPS Timer1 Mode Resource Timer1 must be running in Timer mode or Synchronized Counter mode for the CCP module to use the capture feature. In Asynchronous Counter mode, the capture operation may not work. See section "Timer1 Module with Gate Control" for more information on configuring Timer1. Related Links 19. Timer1 Module with Gate Control 21.2.3 Software Interrupt Mode When the Capture mode is changed, a false capture interrupt may be generated. The user should keep the CCPxIE Interrupt Priority bit of the PIEx register clear to avoid false interrupts. Additionally, the user should clear the CCPxIF interrupt flag bit of the PIRx register following any change in Operating mode. (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 370 PIC18F26/45/46Q10 Capture/Compare/PWM Module Important: Clocking Timer1 from the system clock (FOSC) should not be used in Capture mode. In order for Capture mode to recognize the trigger event on the CCPx pin, Timer1 must be clocked from the instruction clock (FOSC/4) or from an external clock source. 21.2.4 CCP Prescaler There are four prescaler settings specified by the MODE bits. Whenever the CCP module is turned off, or the CCP module is not in Capture mode, the prescaler counter is cleared. Any Reset will clear the prescaler counter. Switching from one capture prescaler to another does not clear the prescaler and may generate a false interrupt. To avoid this unexpected operation, turn the module off by clearing the CCPxCON register before changing the prescaler. The example below demonstrates the code to perform this function. Example 21-1. Changing Between Capture Prescalers BANKSEL CLRF MOVLW MOVWF 21.2.5 CCP1CON CCP1CON NEW_CAPT_PS CCP1CON ;(only needed when CCP1CON is not in ACCESS space) ;Turn CCP module off ;CCP ON and Prescaler select W ;Load CCP1CON with this value Capture During Sleep Capture mode depends upon the Timer1 module for proper operation. There are two options for driving the Timer1 module in Capture mode. It can be driven by the instruction clock (FOSC/4), or by an external clock source. When Timer1 is clocked by FOSC/4, Timer1 will not increment during Sleep. When the device wakes from Sleep, Timer1 will continue from its previous state. Capture mode will operate during Sleep when Timer1 is clocked by an external clock source. 21.3 Compare Mode The Compare mode function described in this section is available and identical for all CCP modules. Compare mode makes use of the 16-bit odd numbered Timer resources (Timer1, Timer3, etc.). The 16-bit value of the CCPRx register is constantly compared against the 16-bit value of the TMRx register. When a match occurs, one of the following events can occur: * * * * * * Toggle the CCPx output and clear TMRx Toggle the CCPx output without clearing TMRx Set the CCPx output Clear the CCPx output Pulse output Pulse output and clear TMRx The action on the pin is based on the value of the MODE control bits. At the same time, the interrupt flag CCPxIF bit is set, and an ADC conversion can be triggered, if selected. All Compare modes can generate an interrupt and trigger an ADC conversion. When MODE = '0001' or '1011', the CCP resets the TMRx register. The following figure shows a simplified diagram of the compare operation. (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 371 PIC18F26/45/46Q10 Capture/Compare/PWM Module Figure 21-2. Compare Mode Operation Block Diagram Rev. 30-000133A 6/27/2017 MODE Auto-conversion Trigger 4 CCPx Q PPS RxyPPS S R CCPRxH CCPRxL Output Logic Comparator TMR1H TRIS TMR1L Set CCPxIF Interrupt Flag 21.3.1 CCPx Pin Configuration The software must configure the CCPx pin as an output by clearing the associated TRIS bit and defining the appropriate output pin through the RxyPPS registers. See section "Peripheral Pin Select (PPS) Module" for more details. The CCP output can also be used as an input for other peripherals. Important: Clearing the CCPxCON register will force the CCPx compare output latch to the default low level. This is not the PORT I/O data latch. Related Links 17. (PPS) Peripheral Pin Select Module 21.3.2 Timer1 Mode Resource In Compare mode, Timer1 must be running in either Timer mode or Synchronized Counter mode. The compare operation may not work in Asynchronous Counter mode. See Section "Timer1 Module with Gate Control" for more information on configuring Timer1. Important: Clocking Timer1 from the system clock (FOSC) should not be used in Compare mode. In order for Compare mode to generate the trigger event on the CCPx pin, Timer1 must be clocked from the instruction clock (FOSC/4) or from an external clock source. 21.3.3 Auto-Conversion Trigger All CCPx modes set the CCP Interrupt Flag (CCPxIF). When this flag is set and a match occurs, an autoconversion trigger can take place if the CCP module is selected as the conversion trigger source. Refer to Section "Auto-Conversion Trigger" for more information. Important: Removing the match condition by changing the contents of the CCPRxH and CCPRxL register pair, between the clock edge that generates the Auto-conversion Trigger and the clock edge that generates the Timer1 Reset, will preclude the Reset from occurring. (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 372 PIC18F26/45/46Q10 Capture/Compare/PWM Module Related Links 32.2.6 Auto-Conversion Trigger 21.3.4 Compare During Sleep Since FOSC is shut down during Sleep mode, the Compare mode will not function properly during Sleep, unless the timer is running. The device will wake on interrupt (if enabled). 21.4 PWM Overview Pulse-Width Modulation (PWM) is a scheme that provides power to a load by switching quickly between fully ON and fully OFF states. The PWM signal resembles a square wave where the high portion of the signal is considered the ON state and the low portion of the signal is considered the OFF state. The high portion, also known as the pulse width, can vary in time and is defined in steps. A larger number of steps applied, which lengthens the pulse width, also supplies more power to the load. Lowering the number of steps applied, which shortens the pulse width, supplies less power. The PWM period is defined as the duration of one complete cycle or the total amount of ON and OFF time combined. PWM resolution defines the maximum number of steps that can be present in a single PWM period. A higher resolution allows for more precise control of the pulse-width time and in turn the power that is applied to the load. The term duty cycle describes the proportion of the ON time to the OFF time and is expressed in percentages, where 0% is fully OFF and 100% is fully ON. A lower duty cycle corresponds to less power applied and a higher duty cycle corresponds to more power applied. The figure below shows a typical waveform of the PWM signal. Figure 21-3. CCP PWM Output Signal Rev. 30-000134A 5/9/2017 Period Pulse Width TMR2 = PR2 TMR2 = CCPRxH:CCPRxL TMR2 = 0 21.4.1 Standard PWM Operation The standard PWM function described in this section is available and identical for all CCP modules. The standard PWM mode generates a Pulse-Width Modulation (PWM) signal on the CCPx pin with up to ten bits of resolution. The period, duty cycle, and resolution are controlled by the following registers: * * * * Even numbered TxPR registers (T2PR, T4PR, etc) Even numbered TxCON registers (T2CON, T4CON, etc) 16-bit CCPRx registers CCPxCON registers It is required to have FOSC/4 as the clock input to TxTMR for correct PWM operation. The following figure shows a simplified block diagram of PWM operation. (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 373 PIC18F26/45/46Q10 Capture/Compare/PWM Module Figure 21-4. Simplified PWM Block Diagram Rev. 10-000 157C 9/5/201 4 Duty cycle registers CCPRxH CCPRxL CCPx_out 10-bit Latch(2) (Not accessible by user) Comparator R S Q PPS RxyPPS TMR2 Module R TMR2 To Peripherals set CCPIF CCPx TRIS Control (1) ERS logic Comparator CCPx_pset PR2 Note: 1. 8-bit timer is concatenated with two bits generated by FOSC or two bits of the internal prescaler to create 10-bit time base. 2. The alignment of the 10 bits from the CCPRx register is determined by the CCPxFMT bit. Important: The corresponding TRIS bit must be cleared to enable the PWM output on the CCPx pin. 21.4.2 Setup for PWM Operation The following steps should be taken when configuring the CCP module for standard PWM operation: 1. 2. 3. 4. 5. Use the desired output pin RxyPPS control to select CCPx as the source and disable the CCPx pin output driver by setting the associated TRIS bit. Load the T2PR register with the PWM period value. Configure the CCP module for the PWM mode by loading the CCPxCON register with the appropriate values. Load the CCPRx register with the PWM duty cycle value and configure the FMT bit to set the proper register alignment. Configure and start Timer2: - Clear the TMR2IF interrupt flag bit of the PIRx register. See Note below. - Select the timer clock source to be as FOSC/4 using the TxCLKCON register. This is required for correct operation of the PWM module. - Configure the T2CKPS bits of the T2CON register with the timer prescale value. - Enable the timer by setting the T2ON bit. (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 374 PIC18F26/45/46Q10 Capture/Compare/PWM Module 6. Enable PWM output pin: - Wait until the timer overflows and the TMR2IF bit of the PIRx register is set. See Note below. - Enable the CCPx pin output driver by clearing the associated TRIS bit. Important: In order to send a complete duty cycle and period on the first PWM output, the above steps must be included in the setup sequence. If it is not critical to start with a complete PWM signal on the first output, then step 6 may be ignored. Related Links 20.9.3 TxCON 21.4.3 Timer2 Timer Resource The PWM standard mode makes use of the 8-bit Timer2 timer resources to specify the PWM period. 21.4.4 PWM Period The PWM period is specified by the T2PR register of Timer2. The PWM period can be calculated using the formula in the equation below. Figure 21-5. PWM Period = 2 + 1 * 4 * * 2Pr where TOSC = 1/FOSC When T2TMR is equal to T2PR, the following three events occur on the next increment cycle: * T2TMR is cleared * The CCPx pin is set. (Exception: If the PWM duty cycle = 0%, the pin will not be set.) * The PWM duty cycle is transferred from the CCPRx register into a 10-bit buffer. Important: The Timer postscaler (see "Timer2 Interrupt") is not used in the determination of the PWM frequency. Related Links 20.4 Timer2 Interrupt 21.4.5 PWM Duty Cycle The PWM duty cycle is specified by writing a 10-bit value to the CCPRx register. The alignment of the 10bit value is determined by the FMT bit (see Figure 21-6). The CCPRx register can be written to at any time. However, the duty cycle value is not latched into the 10-bit buffer until after a match between T2PR and T2TMR. The equations below are used to calculate the PWM pulse width and the PWM duty cycle ratio. (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 375 PIC18F26/45/46Q10 Capture/Compare/PWM Module Figure 21-6. PWM 10-Bit Alignment Rev. 10-000 160A 12/9/201 3 CCPRxH CCPRxL 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 FMT = 1 FMT = 0 CCPRxH CCPRxL 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 10-bit Duty Cycle 9 8 7 6 5 4 3 2 1 0 Figure 21-7. Pulse Width = : * * 2 Pr Figure 21-8. Duty Cycle : = 4 2 + 1 The CCPRx register is used to double buffer the PWM duty cycle. This double buffering is essential for glitchless PWM operation. The 8-bit timer T2TMR register is concatenated with either the 2-bit internal system clock (FOSC), or two bits of the prescaler, to create the 10-bit time base. The system clock is used if the Timer2 prescaler is set to 1:1. When the 10-bit time base matches the CCPRx register, then the CCPx pin is cleared (see Figure 21-4). 21.4.6 PWM Resolution The resolution determines the number of available duty cycles for a given period. For example, a 10-bit resolution will result in 1024 discrete duty cycles, whereas an 8-bit resolution will result in 256 discrete duty cycles. The maximum PWM resolution is ten bits when T2PR is 255. The resolution is a function of the T2PR register value as shown below. Figure 21-9. PWM Resolution log 4 2 + 1 Re = log 2 Important: If the pulse-width value is greater than the period, the assigned PWM pin(s) will remain unchanged. Table 21-3. Example PWM Frequencies and Resolutions (FOSC = 20 MHz) PWM Frequency Timer Prescale T2PR Value Maximum Resolution (bits) (c) 2019 Microchip Technology Inc. 1.22 kHz 4.88 kHz 19.53 kHz 78.12 kHz 156.3 kHz 208.3 kHz 16 4 1 1 1 1 0xFF 0xFF 0xFF 0x3F 0x1F 0x17 10 10 10 8 7 6.6 Datasheet Preliminary DS40001996C-page 376 PIC18F26/45/46Q10 Capture/Compare/PWM Module Table 21-4. Example PWM Frequencies and Resolutions (FOSC = 8 MHz) PWM Frequency Timer Prescale T2PR Value Maximum Resolution (bits) 1.22 kHz 4.90 kHz 19.61 kHz 76.92 kHz 153.85 kHz 200.0 kHz 16 4 1 1 1 1 0x65 0x65 0x65 0x19 0x0C 0x09 8 8 8 6 5 5 21.4.7 Operation in Sleep Mode In Sleep mode, the T2TMR register will not increment and the state of the module will not change. If the CCPx pin is driving a value, it will continue to drive that value. When the device wakes up, T2TMR will continue from the previous state. 21.4.8 Changes in System Clock Frequency The PWM frequency is derived from the system clock frequency. Any changes in the system clock frequency will result in changes to the PWM frequency. See the "Oscillator Module (with Fail-Safe Clock Monitor)" section for additional details. Related Links 4. Oscillator Module (with Fail-Safe Clock Monitor) 21.4.9 Effects of Reset Any Reset will force all ports to Input mode and the CCP registers to their Reset states. (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 377 PIC18F26/45/46Q10 Capture/Compare/PWM Module 21.5 Register Summary - CCP Control Address Name 0x0FA5 CCPR2 0x0FA7 CCP2CON 7:0 0x0FA8 CCP2CAP 7:0 0x0FA9 CCPR1 Bit Pos. 7:0 15:8 CCPRH[7:0] EN OUT FMT MODE[3:0] CTS[3:0] 7:0 CCPRL[7:0] 15:8 CCPRH[7:0] 0x0FAB CCP1CON 7:0 0x0FAC CCP1CAP 7:0 0x0FAD CCPTMRS 7:0 21.6 CCPRL[7:0] EN OUT FMT MODE[3:0] CTS[3:0] P4TSEL[1:0] P3TSEL[1:0] C2TSEL[1:0] C1TSEL[1:0] Register Definitions: CCP Control Long bit name prefixes for the CCP peripherals are shown in the following table. Refer to the "Long Bit Names" section for more information. Table 21-5. CCP Long bit name prefixes Peripheral Bit Name Prefix CCP1 CCP1 CCP2 CCP2 Related Links 1.4.2.2 Long Bit Names (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 378 PIC18F26/45/46Q10 Capture/Compare/PWM Module 21.6.1 CCPxCON Name: Address: CCPxCON 0xFAB,0xFA7 CCP Control Register Bit Access Reset 5 4 EN 7 OUT FMT R/W RO R/W R/W 0 x 0 0 Bit 7 - EN Value 1 0 6 3 2 1 0 R/W R/W R/W 0 0 0 MODE[3:0] CCP Module Enable bit Description CCP is enabled CCP is disabled Bit 5 - OUT CCP Output Data bit (read-only) Bit 4 - FMT CCPW (pulse-width) Value Alignment bit Value Condition Description x Capture mode Not used x Compare mode Not used 1 PWM mode Left-aligned format 0 PWM mode Right-aligned format Bits 3:0 - MODE[3:0] CCP Mode Select bits Table 21-6. CCPx Mode Select Bits MODE Operating Mode Operation Set CCPxIF 11xx PWM PWM Operation Yes 1011 Compare Pulse output; clear TMR1(2) Yes 1010 Pulse output Yes 1001 Clear output(1) Yes 1000 Set output(1) Yes Every 16th rising edge of CCPx input Yes 0110 Every 4th rising edge of CCPx input Yes 0101 Every rising edge of CCPx input Yes 0100 Every falling edge of CCPx input Yes 0011 Every edge of CCPx input Yes Toggle output Yes Toggle output; clear TMR1(2) Yes 0111 0010 Capture Compare 0001 0000 Disabled (c) 2019 Microchip Technology Inc. -- Datasheet Preliminary DS40001996C-page 379 PIC18F26/45/46Q10 Capture/Compare/PWM Module Note: 1. The set and clear operations of the Compare mode are Reset by setting MODE = '0000'. 2. When MODE = '0001' or '1011', then the timer associated with the CCP module is cleared. TMR1 is the default selection for the CCP module, so it is used for indication purpose only. (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 380 PIC18F26/45/46Q10 Capture/Compare/PWM Module 21.6.2 CCPxCAP Name: Address: CCPxCAP 0xFAC,0xFA8 Capture Trigger Input Selection Register Bit 7 6 5 4 3 2 1 0 CTS[3:0] Access R/W R/W R/W R/W 0 0 0 0 Reset Bits 3:0 - CTS[3:0] Capture Trigger Input Selection bits Table 21-7. Capture Trigger Sources CTS Source 1111 CLC8_out 1110 CLC7_out 1101 CLC6_out 1100 CLC5_out 1011 CLC4_out 1010 CLC3_out 1001 CLC2_out 1000 CLC1_out 0100-0111 Reserved 0011 IOC Interrupt 0010 CMP2_output 0001 CMP1_output 0000 Pin selected by CCPxPPS (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 381 PIC18F26/45/46Q10 Capture/Compare/PWM Module 21.6.3 CCPRx Name: Address: CCPRx 0xFA9,0xFA5 Capture/Compare/Pulse Width Register Bit 15 14 13 12 11 10 9 8 CCPRH[7:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset x x x x x x x x Bit 7 6 5 4 3 2 1 0 R/W R/W R/W R/W R/W R/W R/W R/W x x x x x x x x CCPRL[7:0] Access Reset Bits 15:8 - CCPRH[7:0] Capture/Compare/Pulse Width High byte Value Condition 0 to MODE = Capture 255 0 to MODE = Compare 255 0,1,2,3 MODE = PWM and FMT=0 0 to 255 MODE = PWM and FMT=1 Bits 7:0 - CCPRL[7:0] Capture/Compare/Pulse Width Low byte Value Condition 0 to MODE = Capture 255 0 to MODE = Compare 255 0 to MODE = PWM and FMT=0 255 0,64,12 MODE = PWM and FMT=1 8,192 (c) 2019 Microchip Technology Inc. Description High byte of 16-bit captured value High byte of 16-bit compare value CCPRH<1:0>=Bits<9:8> of 10-bit Pulse width value CCPRH<7:2> not used Bits<9:2> of 10-bit Pulse width value Description Low byte of 16-bit captured value Low byte of 16-bit compare value Bits<7:0> of 10-bit Pulse width value CCPRL<7:6>=Bits<1:0> of 10-bit Pulse width value CCPRL<5:0> not used Datasheet Preliminary DS40001996C-page 382 PIC18F26/45/46Q10 Capture/Compare/PWM Module 21.6.4 CCPTMRS Name: Address: CCPTMRS 0xFAD CCP Timers Control Register Bit 7 6 5 P4TSEL[1:0] Access Reset 4 3 P3TSEL[1:0] 2 1 C2TSEL[1:0] 0 C1TSEL[1:0] R/W R/W R/W R/W R/W R/W R/W R/W 0 1 0 1 0 1 0 1 Bits 4:5, 6:7 - PnTSEL PWMn Timer Selection bits Value Description 11 PWMn based on Timer6 10 PWMn based on Timer4 01 PWMn based on Timer2 00 Reserved Bits 0:1, 2:3 - CnTSEL CCPn Timer Selection bits Value Description 11 CCPn is based off Timer5 in Capture/Compare mode and Timer6 in PWM mode 10 CCPn is based off Timer3 in Capture/Compare mode and Timer4 in PWM mode 01 CCPn is based off Timer1 in Capture/Compare mode and Timer2 in PWM mode 00 Reserved (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 383 PIC18F26/45/46Q10 (PWM) Pulse-Width Modulation 22. (PWM) Pulse-Width Modulation The PWM module generates a Pulse-Width Modulated signal determined by the duty cycle, period, and resolution that are configured by the following registers: * * * * TxPR TxCON PWMxDC PWMxCON Important: The corresponding TRIS bit must be cleared to enable the PWM output on the PWMx pin. Each PWM module can select the timer source that controls the module. Each module has an independent timer selection which can be accessed using the CCPTMRS register. Note that the PWM mode operation is described with respect to TMR2 in the following sections. Figure 22-1 shows a simplified block diagram of PWM operation. Figure 22-2 shows a typical waveform of the PWM signal. Figure 22-1. Simplified PWM Block Diagram Duty Cycle registers PWMxDCL<7:6> Rev. 30-000130A 5/17/2017 PWMxDCH Latched (Not visible to user) PWMxOUT to other peripherals R Comparator Q 0 PPS S Q 1 PWMx RxyPPS TMR2 Module TMR2 Output Polarity (PWMxPOL) (1) Comparator PR2 Note 1: Clear Timer, PWMx pin and latch Duty Cycle 8-bit timer is concatenated with the two Least Significant bits of 1/FOSC adjusted by the Timer2 prescaler to create a 10-bit time base. (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 384 PIC18F26/45/46Q10 (PWM) Pulse-Width Modulation Figure 22-2. PWM Output Period Rev. 30-000129A 5/17/2017 Pulse Width TMR2 = PR2 TMR2 = PWMxDCH<7:0>:PWMxDCL<7:6> TMR2 = 0 For a step-by-step procedure on how to set up this module for PWM operation, refer to 22.9 Setup for PWM Operation using PWMx Output Pins. 22.1 Fundamental Operation The PWM module produces a 10-bit resolution output. The PWM timer can be selected using the PxTSEL bits in the CCPTMRS register. The default selection for PWMx is TMR2. Note that the PWM module operation in the following sections is described with respect to TMR2. Timer2 and T2PR set the period of the PWM. The PWMxDCL and PWMxDCH registers configure the duty cycle. The period is common to all PWM modules, whereas the duty cycle is independently controlled. Important: The Timer2 postscaler is not used in the determination of the PWM frequency. The postscaler could be used to have a servo update rate at a different frequency than the PWM output. All PWM outputs associated with Timer2 are set when T2TMR is cleared. Each PWMx is cleared when TxTMR is equal to the value specified in the corresponding PWMxDCH (8 MSb) and PWMxDCL<7:6> (2 LSb) registers. When the value is greater than or equal to T2PR, the PWM output is never cleared (100% duty cycle). Important: The PWMxDCH and PWMxDCL registers are double-buffered. The buffers are updated when T2TMR matches T2PR. Care should be taken to update both registers before the timer match occurs. 22.2 PWM Output Polarity The output polarity is inverted by setting the POL bit. 22.3 PWM Period The PWM period is specified by the TxPR register The PWM period can be calculated using the formula of 22.3 PWM Period. It is required to have FOSC/4 as the selected clock input to the timer for correct PWM operation. Figure 22-3. PWM Period = 2 + 1 * 4 * * 2 Pr Note: TOSC = 1/FOSC When T2TMR is equal to T2PR, the following three events occur on the next increment cycle: (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 385 PIC18F26/45/46Q10 (PWM) Pulse-Width Modulation * T2TMR is cleared * The PWM output is active. (Exception: When the PWM duty cycle = 0%, the PWM output will remain inactive.) * The PWMxDCH and PWMxDCL register values are latched into the buffers. Important: The Timer2 postscaler has no effect on the PWM operation. 22.4 PWM Duty Cycle The PWM duty cycle is specified by writing a 10-bit value to the PWMxDCH and PWMxDCL register pair. The PWMxDCH register contains the eight MSbs and the PWMxDCL<7:6>, the two LSbs. The PWMxDCH and PWMxDCL registers can be written to at any time. The formulas below are used to calculate the PWM pulse width and the PWM duty cycle ratio. Figure 22-4. Pulse Width = : < 7: 6 > * * 2Pr Note: TOSC = 1/FOSC Figure 22-5. Duty Cycle Ratio : < 7: 6 > = 4 2 + 1 The 8-bit timer T2TMR register is concatenated with the two Least Significant bits of 1/FOSC, adjusted by the Timer2 prescaler to create the 10-bit time base. The system clock is used if the Timer2 prescaler is set to 1:1. 22.5 PWM Resolution The resolution determines the number of available duty cycles for a given period. For example, a 10-bit resolution will result in 1024 discrete duty cycles, whereas an 8-bit resolution will result in 256 discrete duty cycles. The maximum PWM resolution is ten bits when T2PR is 255. The resolution is a function of the T2PR register value as shown below. Figure 22-6. PWM Resolution log 4 2 + 1 Re = log 2 Important: If the pulse-width value is greater than the period, the assigned PWM pin(s) will remain unchanged. Table 22-1. Example PWM Frequencies and Resolutions (FOSC = 20 MHz) PWM Frequency Timer Prescale (c) 2019 Microchip Technology Inc. 0.31 kHz 4.88 kHz 19.53 kHz 78.12 kHz 156.3 kHz 208.3 kHz 64 4 1 1 1 1 Datasheet Preliminary DS40001996C-page 386 PIC18F26/45/46Q10 (PWM) Pulse-Width Modulation ...........continued PWM Frequency T2PR Value Maximum Resolution (bits) 0.31 kHz 4.88 kHz 19.53 kHz 78.12 kHz 156.3 kHz 208.3 kHz 0xFF 0xFF 0xFF 0x3F 0x1F 0x17 10 10 10 8 7 6.6 Table 22-2. Example PWM Frequencies and Resolutions (FOSC = 8 MHz) PWM Frequency 0.31 kHz 4.90 kHz 19.61 kHz 76.92 kHz 153.85 kHz 200.0 kHz 64 4 1 1 1 1 0x65 0x65 0x65 0x19 0x0C 0x09 8 8 8 6 5 5 Timer Prescale T2PR Value Maximum Resolution (bits) 22.6 Operation in Sleep Mode In Sleep mode, the T2TMR register will not increment and the state of the module will not change. If the PWMx pin is driving a value, it will continue to drive that value. When the device wakes up, T2TMR will continue from its previous state. 22.7 Changes in System Clock Frequency The PWM frequency is derived from the system clock frequency (FOSC). Any changes in the system clock frequency will result in changes to the PWM frequency. Related Links 4. Oscillator Module (with Fail-Safe Clock Monitor) 22.8 Effects of Reset Any Reset will force all ports to Input mode and the PWM registers to their Reset states. 22.9 Setup for PWM Operation using PWMx Output Pins The following steps should be taken when configuring the module for PWM operation using the PWMx pins: 1. 2. 3. 4. 5. Disable the PWMx pin output driver(s) by setting the associated TRIS bit(s). Clear the PWMxCON register. Load the T2PR register with the PWM period value. Load the PWMxDCH register and bits <7:6> of the PWMxDCL register with the PWM duty cycle value. Configure and start Timer2: - Clear the TMR2IF interrupt flag bit of the PIRx register.(1) - Select the timer clock source to be as FOSC/4 using the TxCLKCON register. This is required for correct operation of the PWM module. - Configure the T2CKPS bits of the T2CON register with the Timer2 prescale value. (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 387 PIC18F26/45/46Q10 (PWM) Pulse-Width Modulation 6. 7. 8. - Enable Timer2 by setting the T2ON bit of the T2CON register. Enable PWM output pin and wait until Timer2 overflows, TMR2IF bit of the PIRx register is set.(2) Enable the PWMx pin output driver(s) by clearing the associated TRIS bit(s) and setting the desired pin PPS control bits. Configure the PWM module by loading the PWMxCON register with the appropriate values. Note: 1. In order to send a complete duty cycle and period on the first PWM output, the above steps must be followed in the order given. If it is not critical to start with a complete PWM signal, then move Step 8 to replace Step 4. 2. For operation with other peripherals only, disable PWMx pin outputs. 22.9.1 PWMx Pin Configuration All PWM outputs are multiplexed with the PORT data latch. The user must configure the pins as outputs by clearing the associated TRIS bits. 22.10 Setup for PWM Operation to Other Device Peripherals The following steps should be taken when configuring the module for PWM operation to be used by other device peripherals: 1. 2. 3. 4. 5. 6. 7. Disable the PWMx pin output driver(s) by setting the associated TRIS bit(s). Clear the PWMxCON register. Load the T2PR register with the PWM period value. Load the PWMxDCH register and bits <7:6> of the PWMxDCL register with the PWM duty cycle value. Configure and start Timer2: - Clear the TMR2IF interrupt flag bit of the PIRx register.(1) - Select the timer clock source to be as FOSC/4 using the TxCLKCON register. This is required for correct operation of the PWM module. - Configure the T2CKPS bits of the T2CON register with the Timer2 prescale value. - Enable Timer2 by setting the T2ON bit of the T2CON register. Wait until Timer2 overflows, TMR2IF bit of the PIRx register is set.(1) Configure the PWM module by loading the PWMxCON register with the appropriate values. Note: 1. In order to send a complete duty cycle and period on the first PWM output, the above steps must be included in the setup sequence. If it is not critical to start with a complete PWM signal on the first output, then step 6 may be ignored. (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 388 PIC18F26/45/46Q10 (PWM) Pulse-Width Modulation 22.11 Register Summary - Registers Associated with PWM Address Name 0x0F9F PWM4DC 0x0FA1 PWM4CON 0x0FA2 PWM3DC 0x0FA4 PWM3CON Bit Pos. 7:0 DCL[1:0] 15:8 7:0 DCH[7:0] EN 7:0 OUT POL OUT POL DCL[1:0] 15:8 7:0 DCH[7:0] EN 0x0FA5 ... Reserved 0x0FAC 0x0FAD 22.12 CCPTMRS 7:0 P4TSEL[1:0] P3TSEL[1:0] C2TSEL[1:0] C1TSEL[1:0] Register Definitions: PWM Control Long bit name prefixes for the PWM peripherals are shown in the table below. Refer to the "Long Bit Names Section" for more information. Table 22-3. PWM Bit Name Prefixes Peripheral Bit Name Prefix PWM3 PWM3 PWM4 PWM4 Related Links 1.4.2.2 Long Bit Names (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 389 PIC18F26/45/46Q10 (PWM) Pulse-Width Modulation 22.12.1 PWMxCON Name: Address: PWMxCON 0xFA4,0xFA1 PWM Control Register Bit Access Reset 5 4 EN 7 OUT POL R/W RO R/W 0 0 0 Bit 7 - EN Value 1 0 6 3 2 1 0 PWM Module Enable bit Description PWM module is enabled PWM module is disabled Bit 5 - OUT PWM Module Output Level When Bit is Read Bit 4 - POL PWM Output Polarity Select bit Value Description 1 PWM output is inverted 0 PWM output is normal (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 390 PIC18F26/45/46Q10 (PWM) Pulse-Width Modulation 22.12.2 CCPTMRS Name: Address: CCPTMRS 0xFAD CCP Timers Control Register Bit 7 6 5 P4TSEL[1:0] Access Reset 4 3 P3TSEL[1:0] 2 1 C2TSEL[1:0] 0 C1TSEL[1:0] R/W R/W R/W R/W R/W R/W R/W R/W 0 1 0 1 0 1 0 1 Bits 7:6 - P4TSEL[1:0] PWM4 Timer Selection bits Value Description 11 PWM4 based on TMR6 10 PWM4 based on TMR4 01 PWM4 based on TMR2 00 Reserved Bits 5:4 - P3TSEL[1:0] PWM3 Timer Selection bits Value Description 11 PWM3 based on TMR6 10 PWM3 based on TMR4 01 PWM3 based on TMR2 00 Reserved Bits 3:2 - C2TSEL[1:0] CCP2 Timer Selection bits Value Description 11 CCP2 is based off Timer5 in Capture/Compare mode and Timer6 in PWM mode 10 CCP2 is based off Timer3 in Capture/Compare mode and Timer4 in PWM mode 01 CCP2 is based off Timer1 in Capture/Compare mode and Timer2 in PWM mode 00 Reserved Bits 1:0 - C1TSEL[1:0] CCP1 Timer Selection bits Value Description 11 CCP1 is based off Timer5 in Capture/Compare mode and Timer6 in PWM mode 10 CCP1 is based off Timer3 in Capture/Compare mode and Timer4 in PWM mode 01 CCP1 is based off Timer1 in Capture/Compare mode and Timer2 in PWM mode 00 Reserved (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 391 PIC18F26/45/46Q10 (PWM) Pulse-Width Modulation 22.12.3 PWMxDC Name: Address: PWMxDC 0xFA2,0xF9F PWM Duty Cycle Register Bit 15 14 13 12 11 10 9 8 DCH[7:0] Access Reset x x x x x x x x Bit 7 6 5 4 3 2 1 0 DCL[1:0] Access Reset x x Bits 15:8 - DCH[7:0] PWM Duty Cycle Most Significant bits These bits are the MSbs of the PWM duty cycle. Reset States: POR/BOR = xxxxxxxx All Other Resets = uuuuuuuu Bits 7:6 - DCL[1:0] PWM Duty Cycle Least Significant bits These bits are the LSbs of the PWM duty cycle. Reset States: POR/BOR = xx All Other Resets = uu (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 392 PIC18F26/45/46Q10 (ZCD) Zero-Cross Detection Module 23. (ZCD) Zero-Cross Detection Module The ZCD module detects when an A/C signal crosses through the ground potential. The actual zero crossing threshold is the zero crossing reference voltage, ZCPINV, which is typically 0.75V above ground. The connection to the signal to be detected is through a series current-limiting resistor. The module applies a current source or sink to the ZCD pin to maintain a constant voltage on the pin, thereby preventing the pin voltage from forward biasing the ESD protection diodes. When the applied voltage is greater than the reference voltage, the module sinks current. When the applied voltage is less than the Filename: 10-000194B.vsd reference module sources The current source and sink action keeps the pin voltage Title: voltage, the ZERO CROSS DETECTcurrent. BLOCK DIAGRAM Last Edit: 5/14/2014 constant over the full range of the applied voltage. The ZCD module is shown in the following simplified First Used: PIC16(L)F1615 block Notes: diagram. Figure 23-1. Simplified ZCD Block Diagram VPULLUP Rev. 10-000194B 5/14/2014 optional VDD RPULLUP - Zcpinv ZCDxIN RSERIES RPULLDOWN + External voltage source optional ZCDx_output D ZCDxPOL Q ZCDxOUT bit Q1 Interrupt det ZCDxINTP ZCDxINTN Set ZCDIF flag Interrupt det The ZCD module is useful when monitoring an A/C waveform for, but not limited to, the following purposes: * A/C period measurement * Accurate long term time measurement * Dimmer phase delayed drive (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 393 PIC18F26/45/46Q10 (ZCD) Zero-Cross Detection Module * Low EMI cycle switching 23.1 External Resistor Selection The ZCD module requires a current-limiting resistor in series with the external voltage source. The impedance and rating of this resistor depends on the external source peak voltage. Select a resistor value that will drop all of the peak voltage when the current through the resistor is nominally 300 A. Make sure that the ZCD I/O pin internal weak pull-up is disabled so it does not interfere with the current source and sink. Figure 23-2. External Resistor = 3 x 10-4 Figure 23-3. External Voltage Source Rev. 30-000001A 7/18/2017 VPEAK VMAXPEAK VMINPEAK Z CPINV 23.2 ZCD Logic Output The ZCD module includes a Status bit, which can be read to determine whether the current source or sink is active. The OUT bit is set when the current sink is active, and cleared when the current source is active. The OUT bit is affected by the polarity bit. The OUT signal can also be used as input to other modules. This is controlled by the registers of the corresponding module. OUT can be used as follows: * Gate source for TMR1/3/5 * Clock source for TMR2/4/6 * Reset source for TMR2/4/6 23.3 ZCD Logic Polarity The POL bit inverts the OUT bit relative to the current source and sink output. When the POL bit is set, a OUT high indicates that the current source is active, and a low output indicates that the current sink is active. The POL bit affects the ZCD interrupts. 23.4 ZCD Interrupts An interrupt will be generated upon a change in the ZCD logic output when the appropriate interrupt enables are set. A rising edge detector and a falling edge detector are present in the ZCD for this purpose. (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 394 PIC18F26/45/46Q10 (ZCD) Zero-Cross Detection Module The ZCDIF bit of the PIRx register will be set when either edge detector is triggered and its associated enable bit is set. The INTP enables rising edge interrupts and the INTN bit enables falling edge interrupts. Priority of the interrupt can be changed if the IPEN bit of the INTCON register is set. The ZCD interrupt can be made high or low priority by setting or clearing the ZCDIP bit of the IPRx register. To fully enable the interrupt, the following bits must be set: * * * * ZCDIE bit of the PIEx register INTP bit for rising edge detection INTN bit for falling edge detection PEIE and GIE bits of the INTCON register Changing the POL bit will cause an interrupt, regardless of the level of the SEN bit. The ZCDIF bit of the PIRx register must be cleared in software as part of the interrupt service. If another edge is detected while this flag is being cleared, the flag will still be set at the end of the sequence. 23.5 Correction for ZCPINV Offset The actual voltage at which the ZCD switches is the reference voltage at the non-inverting input of the ZCD op amp. For external voltage source waveforms other than square waves, this voltage offset from zero causes the zero-cross event to occur either too early or too late. 23.5.1 Correction by AC Coupling When the external voltage source is sinusoidal, the effects of the ZCPINV offset can be eliminated by isolating the external voltage source from the ZCD pin with a capacitor, in addition to the voltage reducing resistor. The capacitor will cause a phase shift resulting in the ZCD output switch in advance of the actual zero crossing event. The phase shift will be the same for both rising and falling zero crossings, which can be compensated for by either delaying the CPU response to the ZCD switch by a timer or other means, or selecting a capacitor value large enough that the phase shift is negligible. To determine the series resistor and capacitor values for this configuration, start by computing the impedance, Z, to obtain a peak current of 300 A. Next, arbitrarily select a suitably large non-polar capacitor and compute its reactance, Xc, at the external voltage source frequency. Finally, compute the series resistor, capacitor peak voltage, and phase shift by the formulas shown below. When this technique is used and the input signal is not present, the ZCD will tend to oscillate. To avoid this oscillation, connect the ZCD pin to VDD or GND with a high-impedance resistor such as 200K. Figure 23-4. R-C Equations VPEAK = external voltage source peak voltage f = external voltage source frequency C = series capacitor R = series resistor VC = Peak capacitor voltage = Capacitor induced zero crossing phase advance in radians T = Time ZC event occurs before actual zero crossing = 3 x 10-4 (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 395 PIC18F26/45/46Q10 (ZCD) Zero-Cross Detection Module = = 1 2 2 - 2 = 3 x 10-4 = tan -1 = 2 Figure 23-5. R-C Calcuation Example = 120 = x 2 = 169.7 = 60 = 0.1 = -4 3 x 10 = = = 169.7 = 565.7 3 x 10-4 1 1 = = 26.53 2 2 x 60 x 10-7 2 - 2 = 565.1 = 560 = 2 + 2 = 560.6 = = 302.7 x 10-6 = x = 8.0 = tan -1 = 23.5.2 = 0.047 = 125.6 2 Correction By Offset Current When the waveform is varying relative to VSS, then the zero cross is detected too early as the waveform falls and too late as the waveform rises. When the waveform is varying relative to VDD, then the zero cross is detected too late as the waveform rises and too early as the waveform falls. The actual offset time can be determined for sinusoidal waveforms with the corresponding equations shown below. Figure 23-6. ZCD Event Offset When External Voltage source is relative to VSS (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 396 PIC18F26/45/46Q10 (ZCD) Zero-Cross Detection Module = sin-1 2 When External Voltage source is relative to VDD = sin-1 - 2 This offset time can be compensated for by adding a pull-up or pull-down biasing resistor to the ZCD pin. A pull-up resistor is used when the external voltage source is varying relative to VSS. A pull-down resistor is used when the voltage is varying relative to VDD. The resistor adds a bias to the ZCD pin so that the target external voltage source must go to zero to pull the pin voltage to the ZCPINV switching voltage. The pull-up or pull-down value can be determined with the equations shown below. Figure 23-7. ZCD Pull-up/Pull-down Resistor When External Voltage source is relative to VSS = - When External Voltage source is relative to VDD = 23.6 - Handling VPEAK Variations If the peak amplitude of the external voltage is expected to vary, the series resistor must be selected to keep the ZCD current source and sink below the design maximum range of 600 A and above a reasonable minimum range. A general rule of thumb is that the maximum peak voltage can be no more than six times the minimum peak voltage. To ensure that the maximum current does not exceed 600 A and the minimum is at least 100 A, compute the series resistance as shown in Figure 23-8. The compensating pull-up for this series resistance can be determined with the equations shown in Figure 23-7 because the pull-up value is independent from the peak voltage. Figure 23-8. Series R for V range _ + _ = 7 x 10-4 23.7 Operation During Sleep The ZCD current sources and interrupts are unaffected by Sleep. (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 397 PIC18F26/45/46Q10 (ZCD) Zero-Cross Detection Module 23.8 Effects of a Reset The ZCD circuit can be configured to default to the Active or Inactive state on Power-on Reset (POR). When the ZCD Configuration bit is cleared, the ZCD circuit will be active at POR. When the ZCD Configuration bit is set, the SEN bit must be set to enable the ZCD module. 23.9 Disabling the ZCD Module The ZCD module can be disabled in two ways: 1. 2. The ZCD Configuration bit disables the ZCD module when set. When this is the case then the ZCD module will be enabled by setting the SEN bit. When the ZCD bit is clear, the ZCD is always enabled and the SEN bit has no effect. The ZCD can also be disabled using the ZCDMD bit of the PMDx register. This is subject to the status of the ZCD bit. (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 398 PIC18F26/45/46Q10 (ZCD) Zero-Cross Detection Module 23.10 Register Summary: ZCD Control Address Name Bit Pos. 0x0F2D ZCDCON 7:0 23.11 SEN OUT POL INTP INTN Register Definitions: ZCD Control Long bit name prefixes for the ZCD peripherals are shown in the table below. Refer to the "Long Bit Names Section" for more information. Table 23-1. ZCD Long Bit Name Prefixes Peripheral Bit Name Prefix ZCD ZCD Related Links 1.4.2.2 Long Bit Names 1.4.2.2 Long Bit Names (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 399 PIC18F26/45/46Q10 (ZCD) Zero-Cross Detection Module 23.11.1 ZCDCON Name: Address: ZCDCON 0xF2D Zero-Cross Detect Control Register Bit Access Reset 5 4 1 0 SEN 7 6 OUT POL 3 2 INTP INTN R/W RO R/W R/W R/W 0 x 0 0 0 Bit 7 - SEN Zero-Cross Detect Software Enable bit This bit is ignored when ZCD fuse is cleared. Value Condition Description X ZCD Config fuse = 0 Zero-cross detect is always enabled. This bit is ignored. 1 ZCD Config fuse = 1 Zero-cross detect is enabled. ZCD pin is forced to output to source and sink current. 0 ZCD Config fuse = 1 Zero-cross detect is disabled. ZCD pin operates according to PPS and TRIS controls. Bit 5 - OUT Zero-Cross Detect Data Output bit Value Condition Description 1 POL = 0 ZCD pin is sinking current 0 POL = 0 ZCD pin is sourcing current 1 POL = 1 ZCD pin is sourcing current 0 POL = 1 ZCD pin is sinking current Bit 4 - POL Zero-Cross Detect Polarity bit Value Description 1 ZCD logic output is inverted 0 ZCD logic output is not inverted Bit 1 - INTP Zero-Cross Detect Positive-Going Edge Interrupt Enable bit Value Description 1 ZCDIF bit is set on low-to-high ZCD_output transition 0 ZCDIF bit is unaffected by low-to-high ZCD_output transition Bit 0 - INTN Zero-Cross Detect Negative-Going Edge Interrupt Enable bit Value Description 1 ZCDIF bit is set on high-to-low ZCD_output transition 0 ZCDIF bit is unaffected by high-to-low ZCD_output transition (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 400 PIC18F26/45/46Q10 (CWG) Complementary Waveform Generator Modul... 24. (CWG) Complementary Waveform Generator Module The Complementary Waveform Generator (CWG) produces half-bridge, full-bridge, and steering of PWM waveforms. It is backwards compatible with previous CCP functions. The PIC18F26/45/46Q10 family has 1 instance(s) of the CWG module. The CWG has the following features: * Six Operating modes: - Synchronous Steering mode - Asynchronous Steering mode - Full-Bridge mode, Forward - Full-Bridge mode, Reverse - Half-Bridge mode - Push-Pull mode * Output Polarity Control * Output Steering * Independent 6-Bit Rising and Falling Event Dead-Band Timers: - Clocked dead band - Independent rising and falling dead-band enables * Auto-Shutdown Control With: - Selectable shutdown sources - Auto-restart option - Auto-shutdown pin override control 24.1 Fundamental Operation The CWG generates two output waveforms from the selected input source. The off-to-on transition of each output can be delayed from the on-to-off transition of the other output, thereby, creating a time delay immediately where neither output is driven. This is referred to as dead time and is covered in 24.7 Dead-Band Control. It may be necessary to guard against the possibility of circuit faults or a feedback event arriving too late or not at all. In this case, the active drive must be terminated before the Fault condition causes damage. This is referred to as auto-shutdown and is covered in 24.11 Auto-Shutdown. 24.2 Operating Modes The CWG module can operate in six different modes, as specified by the MODE bits: * * * * * * Half-Bridge mode Push-Pull mode Asynchronous Steering mode Synchronous Steering mode Full-Bridge mode, Forward Full-Bridge mode, Reverse (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 401 PIC18F26/45/46Q10 (CWG) Complementary Waveform Generator Modul... All modes accept a single pulse data input, and provide up to four outputs as described in the following sections. All modes include auto-shutdown control as described in 24.11 Auto-Shutdown Important: Except as noted for Full-Bridge mode (24.2.3 Full-Bridge Modes), mode changes should only be performed while EN = 0. 24.2.1 Half-Bridge Mode In Half-Bridge mode, two output signals are generated as true and inverted versions of the input as illustrated in Figure 24-1. A non-overlap (dead-band) time is inserted between the two outputs to prevent shoot-through current in various power supply applications. Dead-band control is described in 24.7 Dead-Band Control. The output steering feature cannot be used in this mode. A basic block diagram of this mode is shown in Figure 24-2. The unused outputs CWGxC and CWGxD drive similar signals, with polarity independently controlled by the POLC and POLD bits, respectively. Figure 24-1. CWG Half-Bridge Mode Operation Rev. 30-000097A 4/14/2017 CWGx_clock CWGxA CWGxC Falling Event Dead Band Rising Event Dead Band Rising Event D Falling Event Dead Band CWGxB CWGxD CWGx_data Note: CWGx_rising_src = CCP1_out, CWGx_falling_src = ~CCP1_out (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 402 Filename: Title: Last Edit: First Used: Notes: 10-000209D.vsd SIMPLIFIED CWG BLOCK DIAGRAM (HALF-BRIDGE MODE) 2/2/2016 PIC18(L)F6xK40 (CWG) Complementary PIC18F26/45/46Q10 Waveform Generator Modul... Figure 24-2. Simplified CWG Block Diagram (Half-Bridge Mode, MODE<2:0> = 100) LSAC<1:0> Rev. 10-000209D 2/2/2016 `1' 00 `0' 01 High-Z 10 11 Rising Dead-Band Block CWG Clock clock data out CWG Data 1 CWG Data A data in 0 POLA CWGxA LSBD<1:0> `1' 00 `0' 01 High-Z 10 Falling Dead-Band Block clock data out CWG Data B data in 11 1 CWG Data CWG Data Input 0 POLB D CWGxB Q E LSAC<1:0> EN `1' 00 `0' 01 High-Z 10 11 1 0 POLC Auto-shutdown source (CWGxAS1 register) S CWGxC Q LSBD<1:0> R REN SHUTDOWN = 0 `1' 00 `0' 01 High-Z 10 11 1 0 POLD CWGxD SHUTDOWN FREEZE D Q CWG Data (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 403 PIC18F26/45/46Q10 (CWG) Complementary Waveform Generator Modul... 24.2.2 Push-Pull Mode In Push-Pull mode, two output signals are generated, alternating copies of the input as illustrated in Figure 24-3. This alternation creates the push-pull effect required for driving some transformer-based power supply designs. Steering modes are not used in Push-Pull mode. A basic block diagram for the Push-Pull mode is shown in Figure 24-4. The push-pull sequencer is reset whenever EN = 0 or if an auto-shutdown event occurs. The sequencer is clocked by the first input pulse, and the first output appears on CWG1A. The unused outputs CWGxC and CWGxD drive copies of CWGxA and CWGxB, respectively, but with polarity controlled by the POLC and POLD bits of the CWGxCON1 register, respectively. Figure 24-3. CWG Push-Pull Mode Operation Rev. 30-000098A 4/14/2017 CWGx clock Input source CWGxA CWGxB (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 404 Filename: Title: Last Edit: First Used: Notes: 10-000210D.vsd SIMPLIFIED CWG BLOCK DIAGRAM (PUSH-PULL MODE) 2/2/2016 PIC18(L)F6xK40 (CWG) Complementary PIC18F26/45/46Q10 Waveform Generator Modul... Figure 24-4. Simplified CWG Block Diagram (Push-Pull Mode, MODE<2:0> = 101) LSAC<1:0> Rev. 10-000210D 2/2/2016 `1' 00 `0' 01 High-Z 10 11 CWG Data 1 CWG Data A 0 CWGxA POLA D LSBD<1:0> Q Q `1' 00 `0' 01 High-Z 10 11 CWG Data B 1 CWG Data Input CWG Data D 0 CWGxB POLB Q LSAC<1:0> E `1' 00 `0' 01 High-Z 10 EN 11 1 0 CWGxC POLC Auto-shutdown source (CWGxAS1 register) S Q LSBD<1:0> R REN `1' 00 `0' 01 High-Z 10 SHUTDOWN = 0 11 1 0 CWGxD POLD SHUTDOWN FREEZE D Q CWG Data (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 405 PIC18F26/45/46Q10 (CWG) Complementary Waveform Generator Modul... 24.2.3 Full-Bridge Modes In Forward and Reverse Full-Bridge modes, three outputs drive static values while the fourth is modulated by the input data signal. The mode selection may be toggled between forward and reverse by toggling the MODE<0> bit of the CWGxCON0 while keeping MODE<2:1> static, without disabling the Filename: CWG module.10-000263A.vsd When connected, as shown in Figure 24-5, the outputs are appropriate for a full-bridge Title: Example of Full-Bridge Application motor driver. Each CWG output signal has independent polarity control, so the circuit can be adapted to Last Edit: 12/8/2015 and low-active drivers. A simplified block diagram for the Full-Bridge modes is shown in Firsthigh-active Used: PIC18(L)F2x/4xK40 Note: Figure 24-6. Figure 24-5. Example of Full-Bridge Application Rev. 10-000263A 12/8/2015 VDD FET Driver QA QC FET Driver CWGxA CWGxB CWGxC CWGxD (c) 2019 Microchip Technology Inc. LOAD FET Driver FET Driver QB Datasheet Preliminary QD DS40001996C-page 406 Filename: Title: Last Edit: First Used: Notes: 10-000212D.vsd SIMPLIFIED CWG BLOCK DIAGRAM (FULL-BRIDGE MODES) 2/2/2016 PIC18(L)F6xK40 PIC18F26/45/46Q10 (CWG) Complementary Waveform Generator Modul... Figure 24-6. Simplified CWG Block Diagram (Forward and Reverse Full-Bridge Modes) Rev. 10-000212D 2/2/2016 MODE<2:0> = 010: Forward LSAC<1:0> MODE<2:0> = 011: Reverse Rising Dead-Band Block CWG Clock clock signal out signal in D CWG Data 00 `0' 01 High-Z 10 11 CWG Data MODE<2:0> `1' 1 CWG Data A 0 CWGxA POLA Q Q LSBD<1:0> cwg data signal in signal out clock CWG Clock `1' 00 `0' 01 High-Z 10 11 Falling Dead-Band Block CWG Data Input CWG Data 1 CWG Data B 0 CWGxB POLB D Q LSAC<1:0> E EN `1' 00 `0' 01 High-Z 10 11 1 CWG Data C Auto-shutdown source (CWGxAS1 register) 0 CWGxC POLC S Q LSBD<1:0> R REN SHUTDOWN = 0 `1' 00 `0' 01 High-Z 10 11 1 CWG Data D 0 POLD CWGxD SHUTDOWN FREEZE D Q CWG Data (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 407 PIC18F26/45/46Q10 (CWG) Complementary Waveform Generator Modul... In Forward Full-Bridge mode (MODE = 010), CWGxA is driven to its Active state, CWGxB and CWGxC are driven to their Inactive state, and CWGxD is modulated by the input signal, as shown in Figure 24-7. In Reverse Full-Bridge mode (MODE = 011), CWGxC is driven to its Active state, CWGxA and CWGxD are driven to their Inactive states, and CWGxB is modulated by the input signal, as shown in Figure 24-7. In Full-Bridge mode, the dead-band period is used when there is a switch from forward to reverse or vice versa. This dead-band control is described in 24.7 Dead-Band Control, with additional details in 24.8 Rising Edge and Reverse Dead Band and 24.9 Falling Edge and Forward Dead Band. Steering modes are not used with either of the Full-Bridge modes. The mode selection may be toggled between forward and reverse toggling the MODE<0> bit of the CWGxCON0 while keeping MODE<2:1> static, without disabling the CWG module. Figure 24-7. Example of Full-Bridge Output Rev. 30-000099A 4/14/2017 Forward Mode Period CWGxA (2) CWGxB (2) CWGxC (2) Pulse Width CWGxD (2) (1) Reverse Mode (1) Period CWGxA (2) Pulse Width CWGxB (2) CWGxC (2) CWGxD (2) (1) (1) Note: 1. A rising CWG data input creates a rising event on the modulated output. 2. Output signals shown as active-high; all POLy bits are clear. 24.2.3.1 Direction Change in Full-Bridge Mode In Full-Bridge mode, changing MODE controls the forward/reverse direction. Direction changes occur on the next rising edge of the modulated input. (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 408 PIC18F26/45/46Q10 (CWG) Complementary Waveform Generator Modul... A direction change is initiated in software by changing the MODE bits. The sequence is illustrated in Figure 24-8. * The associated active output CWGxA and the inactive output CWGxC are switched to drive in the opposite direction. * The previously modulated output CWGxD is switched to the Inactive state, and the previously inactive output CWGxB begins to modulate. * CWG modulation resumes after the direction-switch dead band has elapsed. 24.2.3.2 Dead-Band Delay in Full-Bridge Mode Dead-band delay is important when either of the following conditions is true: 1. 2. The direction of the CWG output changes when the duty cycle of the data input is at or near 100%, or The turn-off time of the power switch, including the power device and driver circuit, is greater than the turn-on time. The dead-band delay is inserted only when changing directions, and only the modulated output is affected. The statically-configured outputs (CWGxA and CWGxC) are not afforded dead band, and switch essentially simultaneously. The following figure shows an example of the CWG outputs changing directions from forward to reverse, at near 100% duty cycle. In this example, at time t1, the output of CWGxA and CWGxD become inactive, while output CWGxC becomes active. Since the turn-off time of the power devices is longer than the turnon time, a shoot-through current will flow through power devices QC and QD for the duration of `t'. The same phenomenon will occur to power devices QA and QB for the CWG direction change from reverse to forward. When changing the CWG direction at high duty cycle is required for an application, two possible solutions for eliminating the shoot-through current are: 1. 2. Reduce the CWG duty cycle for one period before changing directions. Use switch drivers that can drive the switches off faster than they can drive them on. (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 409 PIC18F26/45/46Q10 (CWG) Complementary Waveform Generator Modul... Figure 24-8. Example of PWM Direction Change at Near 100% Duty Cycle Rev. 30-000100A 4/14/2017 Forward Period t1 Reverse Period CWGxA Pulse Width CWGxB CWGxC CWGxD Pulse Width T ON External Switch C TOFF External Switch D Potential ShootThrough Current 24.2.4 T = TOFF - TON Steering Modes In both Synchronous and Asynchronous Steering modes, the modulated input signal can be steered to any combination of four CWG outputs. A fixed-value will be presented on all the outputs not used for the PWM output. Each output has independent polarity, steering, and shutdown options. Dead-band control is not used in either steering mode. (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 410 Filename: Title: Last Edit: First Used: Notes: 10-000211D.vsd SIMPLIFIED CWG BLOCK DIAGRAM (OUTPUT STEERING MODES) 5/30/2017 PIC18(L)F6xK40 PIC18F26/45/46Q10 (CWG) Complementary Waveform Generator Modul... Figure 24-9. Simplified CWG Block Diagram (Output Steering Modes) Rev. 10-000211D 5/30/2017 MODE<2:0> = 000: Asynchronous LSAC<1:0> MODE<2:0> = 001: Synchronous `1' 00 `0' 01 High-Z 10 11 CWG Data A 1 1 POLA 0 CWGxA 0 OVRA STRA CWG Data CWG Data Input LSBD<1:0> `1' 00 `0' 01 High-Z 10 11 D CWG Data B Q E 1 1 POLB 0 CWGxB 0 OVRB EN STRB LSAC<1:0> `1' 00 `0' 01 High-Z 10 11 CWG Data C Auto-shutdown source (CWGxAS1 register) S Q 1 1 POLC 0 CWGxC 0 R OVRC STRC REN LSBD<1:0> SHUTDOWN = 0 `1' 00 `0' 01 High-Z 10 11 CWG Data D 1 1 POLD 0 CWGxD 0 OVRD SHUTDOWN STRD FREEZE D Q CWG Data (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 411 PIC18F26/45/46Q10 (CWG) Complementary Waveform Generator Modul... For example, when STRA = 0 then the corresponding pin is held at the level defined by OVRA. When STRA = 1, then the pin is driven by the modulated input signal. The POLy bits control the signal polarity only when STRy = 1. The CWG auto-shutdown operation also applies in Steering modes as described in 24.11 AutoShutdown". An auto-shutdown event will only affect pins that have STRy = 1. 24.2.4.1 Synchronous Steering Mode In Synchronous Steering mode (MODE=001), changes to steering selection registers take effect on the next rising edge of the modulated data input (see figure below). In Synchronous Steering mode, the output will always produce a complete waveform. Important: Only the STRx bits are synchronized; the OVRx bits are not synchronized. Figure 24-10. Example of Synchronous Steering (MODE = 001) Rev. 30-000101A 4/14/2017 CWGx clock Input source CWGxA CWGxB 24.2.4.2 Asynchronous Steering Mode In Asynchronous mode (MODE = 000), steering takes effect at the end of the instruction cycle that writes to STRx. In Asynchronous Steering mode, the output signal may be an incomplete waveform (see figure below). This operation may be useful when the user firmware needs to immediately remove a signal from the output pin. Figure 24-11. Example of Asynchronous Steering (MODE = 000) Rev. 30-000102A 4/14/2017 CWGx INPUT End of Instruction Cycle End of Instruction Cycle STRA CWGxA CWGxA Follows CWGx data input (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 412 PIC18F26/45/46Q10 (CWG) Complementary Waveform Generator Modul... 24.3 Start-up Considerations The application hardware must use the proper external pull-up and/or pull-down resistors on the CWG output pins. This is required because all I/O pins are forced to high-impedance at Reset. The polarity control bits (POLy) allow the user to choose whether the output signals are active-high or active-low. 24.4 Clock Source The clock source is used to drive the dead-band timing circuits. The CWG module allows the following clock sources to be selected: * FOSC (system clock) * HFINTOSC When the HFINTOSC is selected, the HFINTOSC will be kept running during Sleep. Therefore, CWG modes requiring dead band can operate in Sleep, provided that the CWG data input is also active during Sleep. The clock sources are selected using the CS bit. The system clock FOSC, is disabled in Sleep and thus dead-band control cannot be used. 24.5 Selectable Input Sources The CWG generates the output waveforms from the input sources which are selected with the ISM bits as shown below. Table 24-1. CWG Data Input Sources ISM Data Source 1111 CLC8_out 1110 CLC7_out 1101 CLC6_out 1100 CLC5_out 1011 CLC4_out 1010 CLC3_out 1001 CLC2_out 1000 CLC1_out 0111 DSM_out 0110 CMP2_out 0101 CMP1_out 0100 PWM4_out 0011 PWM3_out 0010 CCP2_out (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 413 PIC18F26/45/46Q10 (CWG) Complementary Waveform Generator Modul... ...........continued ISM Data Source 0001 CCP1_out 0000 Pin selected by CWGxPPS 24.6 Output Control 24.6.1 CWG Outputs Each CWG output can be routed to a Peripheral Pin Select (PPS) output via the RxyPPS register. Related Links 17. (PPS) Peripheral Pin Select Module 24.6.2 Polarity Control The polarity of each CWG output can be selected independently. When the output polarity bit is set, the corresponding output is active-high. Clearing the output polarity bit configures the corresponding output as active-low. However, polarity does not affect the override levels. Output polarity is selected with the POLy bits. Auto-shutdown and steering options are unaffected by polarity. 24.7 Dead-Band Control The dead-band control provides non-overlapping PWM signals to prevent shoot-through current in PWM switches. Dead-band operation is employed for Half-Bridge and Full-Bridge modes. The CWG contains two 6-bit dead-band counters. One is used for the rising edge of the input source control in Half-Bridge mode or for reverse dead-band Full-Bridge mode. The other is used for the falling edge of the input source control in Half-Bridge mode or for forward dead band in Full-Bridge mode. Dead band is timed by counting CWG clock periods from zero up to the value in the rising or falling deadband counter registers. 24.7.1 Dead-Band Functionality in Half-Bridge mode In Half-Bridge mode, the dead-band counters dictate the delay between the falling edge of the normal output and the rising edge of the inverted output. This can be seen in Figure 24-1. 24.7.2 Dead-Band Functionality in Full-Bridge mode In Full-Bridge mode, the dead-band counters are used when undergoing a direction change. The MODE<0> bit can be set or cleared while the CWG is running, allowing for changes from Forward to Reverse mode. The CWGxA and CWGxC signals will change immediately upon the first rising input edge following a direction change, but the modulated signals (CWGxB or CWGxD, depending on the direction of the change) will experience a delay dictated by the dead-band counters. 24.8 Rising Edge and Reverse Dead Band In Half-Bridge mode, the rising edge dead band delays the turn-on of the CWGxA output after the rising edge of the CWG data input. In Full-Bridge mode, the reverse dead-band delay is only inserted when changing directions from Forward mode to Reverse mode, and only the modulated output CWGxB is affected. (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 414 PIC18F26/45/46Q10 (CWG) Complementary Waveform Generator Modul... The 24.15.8 CWGxDBR register determines the duration of the dead-band interval on the rising edge of the input source signal. This duration is from 0 to 64 periods of the CWG clock. Dead band is always initiated on the edge of the input source signal. A count of zero indicates that no dead band is present. If the input source signal reverses polarity before the dead-band count is completed, then no signal will be seen on the respective output. The CWGxDBR register value is double-buffered. When EN = 0, the buffer is loaded when CWGxDBR is written. When EN = 1, then the buffer will be loaded at the rising edge following the first falling edge of the data input, after the LD bit is set. Refer to the following figure for an example. Figure 24-12. Dead-Band Operation, CWGxDBR = 0x01, CWGxDBF = 0x02 Rev. 30-000103A 4/14/2017 cwg_clock Input Source CWGxA CWGxB 24.9 Falling Edge and Forward Dead Band In Half-Bridge mode, the falling edge dead band delays the turn-on of the CWGxB output at the falling edge of the CWG data input. In Full-Bridge mode, the forward dead-band delay is only inserted when changing directions from Reverse mode to Forward mode, and only the modulated output CWGxD is affected. The 24.15.9 CWGxDBF register determines the duration of the dead-band interval on the falling edge of the input source signal. This duration is from zero to 64 periods of CWG clock. Dead-band delay is always initiated on the edge of the input source signal. A count of zero indicates that no dead band is present. If the input source signal reverses polarity before the dead-band count is completed, then no signal will be seen on the respective output. The CWGxDBF register value is double-buffered. When EN = 0, the buffer is loaded when CWGxDBF is written. When EN = 1, then the buffer will be loaded at the rising edge following the first falling edge of the data input after the LD is set. Refer to the following figure for an example. Figure 24-13. Dead-Band Operation, CWGxDBR = 0x03, CWGxDBF = 0x06, Source Shorter Than Dead Band Rev. 30-000104A 4/14/2017 cwg_clock Input Source CWGxA CWGxB source shorter than dead band (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 415 PIC18F26/45/46Q10 (CWG) Complementary Waveform Generator Modul... 24.10 Dead-Band Jitter When the rising and falling edges of the input source are asynchronous to the CWG clock, it creates jitter in the dead-band time delay. The maximum jitter is equal to one CWG clock period. Refer to the equations below for more details. Figure 24-14. Dead-Band Delay Time Calculation 1 1 - _ = * < 5: 0 > - _ = * < 5: 0 > + 1 _ _ 1 = - _ - - _ = _ - _ = - _ + Figure 24-15. Dead-Band Delay Example Calculation < 5: 0 > = 00 = 10 _ = 8 = 1 = 125 8 - _ = 125 * 10 = 125 - _ = 1.25 + 0.125 = 1.37 24.11 Filename: Title: Last Edit: First Used: Notes: 10-000172C.vsd CWG SHUTDOWN BLOCK DIAGRAM 8/7/2015 PIC16(L)F1614/5/8/9 LECW Auto-Shutdown Auto-shutdown is a method to immediately override the CWG output levels with specific overrides that allow for safe shutdown of the circuit. The shutdown state can be either cleared automatically or held until cleared by software. The auto-shutdown circuit is illustrated in the following figure. Figure 24-16. CWG Shutdown Block Diagram Write `1' to SHUTDOWN bit Rev. 10-000172C 8/7/2015 PPS AS0E CWGxINPPS C1OUT_sync AS4E C2OUT_sync AS5E TMR2_postscaled AS1E TMR4_postscaled AS2E S Q SHUTDOWN S D FREEZE REN Write `0' to SHUTDOWN bit Q CWG_shutdown R CWG_data TMR6_postscaled AS3E CK 24.11.1 Shutdown The shutdown state can be entered by either of the following two methods: * Software Generated * External Input 24.11.1.1 Software Generated Shutdown Setting the SHUTDOWN bit will force the CWG into the shutdown state. When the auto-restart is disabled, the shutdown state will persist as long as the SHUTDOWN bit is set. (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 416 PIC18F26/45/46Q10 (CWG) Complementary Waveform Generator Modul... When auto-restart is enabled, the SHUTDOWN bit will clear automatically and resume operation on the next rising edge event. The SHUTDOWN bit indicates when a shutdown condition exists. The bit may be set or cleared in software or by hardware. 24.11.1.2 External Input Source External shutdown inputs provide the fastest way to safely suspend CWG operation in the event of a Fault condition. When any of the selected shutdown inputs goes active, the CWG outputs will immediately go to the selected override levels without software delay. The override levels are selected by the LSBD and LSAC bits. Several input sources can be selected to cause a shutdown condition. All input sources are active-low. The shutdown input sources are individually enabled by the ASyE bits as shown in the following table: Table 24-2. Shutdown Sources ASyE Source AS7E CLC6_out (low causes shutdown) AS6E CLC2_out (low causes shutdown) AS5E CMP2_out (low causes shutdown) AS4E CMP1_out (low causes shutdown) AS3E TMR6_postscaled (high causes shutdown) AS2E TMR4_postscaled (high causes shutdown) AS1E TMR2_postscaled (high causes shutdown) AS0E Pin selected by CWGxPPS (low causes shutdown) Important: Shutdown inputs are level sensitive, not edge sensitive. The shutdown state cannot be cleared, except by disabling auto-shutdown, as long as the shutdown input level persists. 24.11.1.3 Pin Override Levels The levels driven to the CWG outputs during an auto-shutdown event are controlled by the LSBD and LSAC bits. The LSBD bits control CWGxB/D output levels, while the LSAC bits control the CWGxA/C output levels. 24.11.1.4 Auto-Shutdown Interrupts When an auto-shutdown event occurs, either by software or hardware setting SHUTDOWN, the CWGxIF flag bit of the PIRx register is set. Related Links 14.13.9 PIR7 24.11.2 Auto-Shutdown Restart After an auto-shutdown event has occurred, there are two ways to resume operation: * Software controlled * Auto-restart (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 417 PIC18F26/45/46Q10 (CWG) Complementary Waveform Generator Modul... In either case, the shutdown source must be cleared before the restart can take place. That is, either the shutdown condition must be removed, or the corresponding ASyE bit must be cleared. 24.11.2.1 Software-Controlled Restart When the REN bit is clear (REN = 0), the CWG module must be restarted after an auto-shutdown event through software. Once all auto-shutdown sources are removed, the software must clear SHUTDOWN. Once SHUTDOWN is cleared, the CWG module will resume operation upon the first rising edge of the CWG data input. Important: The SHUTDOWN bit cannot be cleared in software if the auto-shutdown condition is still present. Figure 24-17. SHUTDOWN FUNCTIONALITY, AUTO-RESTART DISABLED (REN = 0, LSAC = 01, LSBD = 01) Rev. 30-000105A 4/14/2017 Shutdown Event Ceases REN Cleared by Software CWG Input Source Shutdown Source SHUTDOWN Tri-State (No Pulse) CWGxA CWGxC CWGxB CWGxD Tri-State (No Pulse) No Shutdown Shutdown Output Resumes 24.11.2.2 Auto-Restart When the REN bit is set (REN = 1), the CWG module will restart from the shutdown state automatically. Once all auto-shutdown conditions are removed, the hardware will automatically clear SHUTDOWN. Once SHUTDOWN is cleared, the CWG module will resume operation upon the first rising edge of the CWG data input. Important: The SHUTDOWN bit cannot be cleared in software if the auto-shutdown condition is still present. (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 418 PIC18F26/45/46Q10 (CWG) Complementary Waveform Generator Modul... Figure 24-18. SHUTDOWN FUNCTIONALITY, AUTO-RESTART ENABLED (REN = 1, LSAC = 01, LSBD = 01) Rev. 30-000106A 4/14/2017 Shutdown Event Ceases REN auto-cleared by hardware CWG Input Source Shutdown Source SHUTDOWN Tri-State (No Pulse) CWGxA CWGxB CWGxC CWGxD Tri-State (No Pulse) No Shutdown Shutdown 24.12 Output Resumes Operation During Sleep The CWG module operates independently from the system clock and will continue to run during Sleep, provided that the clock and input sources selected remain active. The HFINTOSC remains active during Sleep when all the following conditions are met: * CWG module is enabled * Input source is active * HFINTOSC is selected as the clock source, regardless of the system clock source selected. In other words, if the HFINTOSC is simultaneously selected as the system clock and the CWG clock source, when the CWG is enabled and the input source is active, then the CPU will go idle during Sleep, but the HFINTOSC will remain active and the CWG will continue to operate. This will have a direct effect on the Sleep mode current. 24.13 Configuring the CWG 1. Ensure that the TRIS control bits corresponding to CWG outputs are set so that all are configured as inputs, ensuring that the outputs are inactive during setup. External hardware should ensure that pin levels are held to safe levels. 2. Clear the EN bit, if not already cleared. 3. Configure the MODE bits to set the output operating mode. 4. Configure the POLy bits to set the output polarities. 5. Configure the ISM bits to select the data input source. 6. If a steering mode is selected, configure the STRy bits to select the desired output on the CWG outputs. 7. Configure the LSBD and LSAC bits to select the auto-shutdown output override states (this is necessary even if not using auto-shutdown because start-up will be from a shutdown state). 8. If auto-restart is desired, set the REN bit. 9. If auto-shutdown is desired, configure the ASyE bits to select the shutdown source. 10. Set the desired rising and falling dead-band times with the CWGxDBR and CWGxDBF registers. (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 419 PIC18F26/45/46Q10 (CWG) Complementary Waveform Generator Modul... 11. Select the clock source with the CS bits. 12. Set the EN bit to enable the module. 13. Clear the TRIS bits that correspond to the CWG outputs to set them as outputs. If auto-restart is to be used, set the REN bit and the SHUTDOWN bit will be cleared automatically. Otherwise, clear the SHUTDOWN bit in software to start the CWG. (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 420 PIC18F26/45/46Q10 (CWG) Complementary Waveform Generator Modul... 24.14 Register Summary - CWG Control Address Name Bit Pos. 0x0F3B CWG1CLK 7:0 0x0F3C CWG1ISM 7:0 0x0F3D CWG1DBR 7:0 0x0F3E CWG1DBF 7:0 0x0F3F CWG1CON0 7:0 0x0F40 CWG1CON1 7:0 0x0F41 CWG1AS0 7:0 SHUTDOWN REN 0x0F42 CWG1AS1 7:0 AS7E AS6E AS5E AS4E AS3E AS2E AS1E AS0E 0x0F43 CWG1STR 7:0 OVRD OVRC OVRB OVRA STRD STRC STRB STRA 24.15 CS ISM[3:0] DBR[5:0] DBF[5:0] EN LD MODE[2:0] IN POLD LSBD[1:0] POLC POLB POLA LSAC[1:0] Register Definitions: CWG Control Long bit name prefixes for the CWG peripherals are shown in the table below. Refer to the "Long Bit Names Section" for more information. Table 24-3. CWG Bit Name Prefixes Peripheral Bit Name Prefix CWG1 CWG1 Related Links 1.4.2.2 Long Bit Names (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 421 PIC18F26/45/46Q10 (CWG) Complementary Waveform Generator Modul... 24.15.1 CWGxCON0 Name: Address: CWGxCON0 0x0F3F CWG Control Register 0 Bit Access Reset 7 6 EN LD R/W R/W/HC R/W R/W R/W 0 0 0 0 0 Bit 7 - EN Value 1 0 5 4 3 2 1 0 MODE[2:0] CWG1 Enable bit Description Module is enabled Module is disabled Bit 6 - LD CWG1 Load Buffers bit(1) Value Description 1 Dead-band count buffers to be loaded on CWG data rising edge, following first falling edge after this bit is set 0 Buffers remain unchanged Bits 2:0 - MODE[2:0] CWG1 Mode bits Value Description 111 Reserved 110 Reserved 101 CWG outputs operate in Push-Pull mode 100 CWG outputs operate in Half-Bridge mode 011 CWG outputs operate in Reverse Full-Bridge mode 010 CWG outputs operate in Forward Full-Bridge mode 001 CWG outputs operate in Synchronous Steering mode 000 CWG outputs operate in Asynchronous Steering mode Note: 1. This bit can only be set after EN = 1; it cannot be set in the same cycle when EN is set. (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 422 PIC18F26/45/46Q10 (CWG) Complementary Waveform Generator Modul... 24.15.2 CWGxCON1 Name: Address: CWGxCON1 0x0F40 CWG Control Register 1 Bit 7 6 Access Reset 3 2 1 0 IN 5 4 POLD POLC POLB POLA RO R/W R/W R/W R/W x 0 0 0 0 Bit 5 - IN CWG Input Value bit (read-only) Value Description 1 CWG input is a logic 1 0 CWG input is a logic 0 Bits 0, 1, 2, 3 - POLy CWG Output 'y' Polarity bit Value Description 1 Signal output is inverted polarity 0 Signal output is normal polarity (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 423 PIC18F26/45/46Q10 (CWG) Complementary Waveform Generator Modul... 24.15.3 CWGxCLK Name: Address: CWGxCLK 0x0F3B CWGx Clock Input Selection Register Bit 7 6 5 4 3 2 1 0 CS Access R/W Reset 0 Bit 0 - CS Clock Source CWG Clock Source Selection Select bits Value Description 1 HFINTOSC (remains operating during Sleep) 0 FOSC (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 424 PIC18F26/45/46Q10 (CWG) Complementary Waveform Generator Modul... 24.15.4 CWGxISM Name: Address: CWGxISM 0x0F3C CWGx Input Selection Register Bit 7 6 5 4 3 2 1 0 ISM[3:0] Access Reset R/W R/W R/W R/W 0 0 0 0 Bits 3:0 - ISM[3:0] CWG Data Input Source Select bits Table 24-4. CWG Data Input Sources ISM Data Source 1111 CLC8_out 1110 CLC7_out 1101 CLC6_out 1100 CLC5_out 1011 CLC4_out 1010 CLC3_out 1001 CLC2_out 1000 CLC1_out 0111 DSM_out 0110 CMP2_out 0101 CMP1_out 0100 PWM4_out 0011 PWM3_out 0010 CCP2_out 0001 CCP1_out 0000 Pin selected by CWGxPPS (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 425 PIC18F26/45/46Q10 (CWG) Complementary Waveform Generator Modul... 24.15.5 CWGxSTR Name: Address: CWGxSTR 0x0F43 CWG Steering Control Register (1) Bit Access Reset 7 6 5 4 3 2 1 0 OVRD OVRC OVRB OVRA STRD STRC STRB STRA R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Bits 4, 5, 6, 7 - OVRy Steering Data OVR'y' bit Value Condition Description x STRy = 1 CWGx'y' output has the CWG data input waveform with polarity control from POLy bit 1 STRy = 0 and POLy = x CWGx'y' output is high 0 STRy = 0 and POLy = x CWGx'y' output is low Bits 0, 1, 2, 3 - STRy STR'y' Steering Enable bit(2) Value Description 1 CWGx'y' output has the CWG data input waveform with polarity control from POLy bit 0 CWGx'y' output is assigned to value of OVRy bit Note: 1. The bits in this register apply only when MODE = '00x' (24.15.1 CWGxCON0, Steering modes). 2. This bit is double-buffered when MODE = '001'. (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 426 PIC18F26/45/46Q10 (CWG) Complementary Waveform Generator Modul... 24.15.6 CWGxAS0 Name: Address: CWGxAS0 0x0F41 CWG Auto-Shutdown Control Register 0 Bit Access Reset 7 6 SHUTDOWN REN 5 4 3 R/W/HS/HC R/W R/W R/W R/W R/W 0 0 0 1 0 1 LSBD[1:0] 2 1 0 LSAC[1:0] Bit 7 - SHUTDOWN Auto-Shutdown Event Status bit(1,2) Value Description 1 An auto-shutdown state is in effect 0 No auto-shutdown event has occurred Bit 6 - REN Auto-Restart Enable bit Value Description 1 Auto-restart is enabled 0 Auto-restart is disabled Bits 5:4 - LSBD[1:0] CWGxB and CWGxD Auto-Shutdown State Control bits Value Description 11 A logic `1' is placed on CWGxB/D when an auto-shutdown event occurs. 10 A logic `0' is placed on CWGxB/D when an auto-shutdown event occurs. 01 Pin is tri-stated on CWGxB/D when an auto-shutdown event occurs. 00 The Inactive state of the pin, including polarity, is placed on CWGxB/D after the required dead-band interval when an auto-shutdown event occurs. Bits 3:2 - LSAC[1:0] CWGxA and CWGxC Auto-Shutdown State Control bits Value Description 11 A logic `1' is placed on CWGxA/C when an auto-shutdown event occurs. 10 A logic `0' is placed on CWGxA/C when an auto-shutdown event occurs. 01 Pin is tri-stated on CWGxA/C when an auto-shutdown event occurs. 00 The Inactive state of the pin, including polarity, is placed on CWGxA/C after the required dead-band interval when an auto-shutdown event occurs. Note: 1. This bit may be written while EN = 0 (24.15.1 CWGxCON0), to place the outputs into the shutdown configuration. 2. The outputs will remain in auto-shutdown state until the next rising edge of the CWG data input after this bit is cleared. (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 427 PIC18F26/45/46Q10 (CWG) Complementary Waveform Generator Modul... 24.15.7 CWGxAS1 Name: Address: CWGxAS1 0x0F42 CWG Auto-Shutdown Control Register 1 Bit Access Reset 7 6 5 4 3 2 1 0 AS7E AS6E AS5E AS4E AS3E AS2E AS1E AS0E R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Bits 0, 1, 2, 3, 4, 5, 6, 7 - ASyE CWG Auto-shutdown Source ASyE Enable bit(1) Table 24-5. Shutdown Sources ASyE Source AS7E CLC6_out (low causes shutdown) AS6E CLC2_out (low causes shutdown) AS5E CMP2_out (low causes shutdown) AS4E CMP1_out (low causes shutdown) AS3E TMR6_postscaled (high causes shutdown) AS2E TMR4_postscaled (high causes shutdown) AS1E TMR2_postscaled (high causes shutdown) AS0E Pin selected by CWGxPPS (low causes shutdown) Value 1 0 Description Auto-shutdown for source ASyE is enabled Auto-shutdown for source ASyE is disabled Note: This bit may be written while EN = 0 (24.15.1 CWGxCON0), to place the outputs into the shutdown configuration. The outputs will remain in auto-shutdown state until the next rising edge of the CWG data input after this bit is cleared. (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 428 PIC18F26/45/46Q10 (CWG) Complementary Waveform Generator Modul... 24.15.8 CWGxDBR Name: Address: CWGxDBR 0x0F3D CWG Rising Dead-Band Count Register Bit 7 6 5 4 3 2 1 0 DBR[5:0] Access Reset R/W R/W R/W R/W R/W R/W x x x x x x Bits 5:0 - DBR[5:0] CWG Rising Edge-Triggered Dead-Band Count bits Reset States: POR/BOR = xxxxxx All Other Resets = uuuuuu Value Description n Dead band is active no less than n, and no more than n+1, CWG clock periods after the rising edge 0 0 CWG clock periods. Dead-band generation is bypassed (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 429 PIC18F26/45/46Q10 (CWG) Complementary Waveform Generator Modul... 24.15.9 CWGxDBF Name: Address: CWGxDBF 0x0F3E CWG Falling Dead-Band Count Register Bit 7 6 5 4 3 2 1 0 DBF[5:0] Access Reset R/W R/W R/W R/W R/W R/W x x x x x x Bits 5:0 - DBF[5:0] CWG Falling Edge-Triggered Dead-Band Count bits Reset States: POR/BOR = xxxxxx All Other Resets = uuuuuu Value Description n Dead band is active no less than n, and no more than n+1, CWG clock periods after the falling edge 0 0 CWG clock periods. Dead-band generation is bypassed (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 430 PIC18F26/45/46Q10 (CLC) Configurable Logic Cell 25. (CLC) Configurable Logic Cell The Configurable Logic Cell (CLCx) module provides programmable logic that operates outside the speed limitations of software execution. The logic cell takes up to 64input signals and, through the use of configurable gates, reduces the 64inputs to four logic lines that drive one of eight selectable single-output logic functions. Input sources are a combination of the following: * I/O pins * Internal clocks * Peripherals * Register bits The output can be directed internally to peripherals and to an output pin. Important: There are several CLC instances on this device. Throughout this section, the lower case `x' in register names is a generic reference to the CLC instance number. For example, the first instance of the control register is CLC1CON and is generically described in this chapter as CLCxCON. The following figure is a simplified diagram showing signal flow through the CLC. Possible configurations include: * Combinatorial Logic: - AND - NAND - AND-OR - AND-OR-INVERT - OR-XOR - OR-XNOR * Latches: - S-R - Clocked D with Set and Reset - Transparent D with Set and Reset - Clocked J-K with Reset (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 431 PIC18F26/45/46Q10 (CLC) Configurable Logic Cell Figure 25-1. CLC Simplified Block Diagram Rev. 10-000025H 11/9/2016 D Q OUT CLCxOUT Q1 . . . LCx_in[n-2] LCx_in[n-1] LCx_in[n] CLCx_out Input Data Selection Gates(1) LCx_in[0] LCx_in[1] LCx_in[2] EN lcxg1 lcxg2 lcxg3 to Peripherals CLCxPPS Logic lcxq Function PPS (2) CLCx lcxg4 POL MODE<2:0> TRIS Interrupt det INTP INTN set bit CLCxIF Interrupt det Note: 1. See Figure 25-2 for input data selection and gating. 2. See Figure 25-3 for programmable logic functions. 25.1 CLC Setup Programming the CLC module is performed by configuring the four stages in the logic signal flow. The four stages are: * Data selection * Data gating * Logic function selection * Output polarity Each stage is setup at run time by writing to the corresponding CLC Special Function Registers. This has the added advantage of permitting logic reconfiguration on-the-fly during program execution. 25.1.1 Data Selection There are 64signals available as inputs to the configurable logic. Four 64-input multiplexers are used to select the inputs to pass on to the next stage. Data selection is through four multiplexers as indicated on the left side of the following diagram. Data inputs in the figure are identified by a generic numbered input name. (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 432 PIC18F26/45/46Q10 (CLC) Configurable Logic Cell Figure 25-2. Input Data Selection and Gating Rev. 30-000149A 6/12/2017 LCx_in[0] Data Selection 000000 Data GATE 1 LCx_in[n] d1T G 1 D1 T d1N G 1 D1 N G 1 D2 T 111111 D1S<5:0> G 1 D2 N LCx_in[0] lcxg1 000000 d2T G 1 D3 T G 1 D3 N G 1 D4 T G 1 D4 N G1POL d2N LCx_in[n] 111111 D2S<5:0> LCx_in[0] 000000 Data GATE 2 lcxg2 d3T (Same as Data GATE 1) d3N LCx_in[n] Data GATE 3 111111 lcxg3 D3S<5:0> LCx_in[0] (Same as Data GATE 1) Data GATE 4 000000 lcxg4 (Same as Data GATE 1) d4T d4N LCx_in[n] 111111 D4S<5:0> Note: All controls are undefined at power-up. The following table correlates the generic input name to the actual signal for each CLC module. The column labeled `DyS Value' indicates the MUX selection code for the selected data input. DyS is an abbreviation for the MUX select input codes: D1S through D4S where 'y' is the gate number. (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 433 PIC18F26/45/46Q10 (CLC) Configurable Logic Cell CLC Data Input Sources DyS Value CLC Input Source DyS Value CLC Input Source 111111 [63] Reserved 011111 [31] IOC_flag 111110 [62] Reserved 011110 [30] ZCD_out 111101 [61] Reserved 011101 [29] CMP2_out 111100 [60] Reserved 011100 [28] CMP1_out 111011 [59] Reserved 011011 [27] PWM4_out 111010 58] Reserved 011010 [26] PWM3_out 111001 [57] Reserved 011001 [25] CCP2_out 111000 [56] Reserved 011000 [24] CCP1 _out 110111 [55] Reserved 010111 [23] TMR6_out 110110 [54] Reserved 010110 [22] TMR5 _overflow 110101 [53] Reserved 010101 [21] TMR4 _out 110100 [52] Reserved 010100 [20] TMR3 _overflow 110011 [51] Reserved 010011 [19] TMR2 _out 110010 [50] CWG1B_out 010010 [18] TMR1 _overflow 110001 [49] CWG1A_out 010001 [17] TMR0 _overflow 110000 [48] SCK2 010000 [16] CLKR _out 101111 [47] SDO2 001111 [15] ADCRC 101110 [46] SCK1 001110 [14] SOSC 101101 [45] SDO1 001101 [13] SFINTOSC (1MHz) 101100 [44] EUSART2_TX/CK_out 001100 [12] MFINTOSC (32 kHz) 101011 [43] EUSART2_DT_out 001011 [11] MFINTOSC (500 kHz) 101010 [42] EUSART1_TX/CK_out 001010 [10] LFINTOSC 101001 [41] EUSART1_DT_out 001001 [9] HFINTOSC 101000 [40] CLC8_out 001000 [8] FOSC 100111 [39] CLC7_out 000111 [7] CLCIN7PPS 100110 [38] CLC6_out 000110 [6] CLCIN6PPS 100101 [37] CLC5_out 000101 [5] CLCIN5PPS 100100 [36] CLC4_out 000100 [4] CLCIN4PPS 100011 [35] CLC3_out 000011 [3] CLCIN3PPS 100010 [34] CLC2_out 000010 [2] CLCIN2PPS 100001 [33] CLC1_out 000001 [1] CLCIN1PPS (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 434 PIC18F26/45/46Q10 (CLC) Configurable Logic Cell ...........continued DyS Value CLC Input Source DyS Value CLC Input Source 100000 [32] DSM1_out 000000 [0] CLCIN0PPS Data inputs are selected with CLCxSEL0 through CLCxSEL3 registers. Important: Data selections are undefined at power-up. 25.1.2 Data Gating Outputs from the input multiplexers are directed to the desired logic function input through the data gating stage. Each data gate can direct any combination of the four selected inputs. The gate stage is more than just signal direction. The gate can be configured to direct each input signal as inverted or non-inverted data. Directed signals are ANDed together in each gate. The output of each gate can be inverted before going on to the logic function stage. The gating is in essence a 1-to-4 input AND/NAND/OR/NOR gate. When every input is inverted and the output is inverted, the gate is an AND of all enabled data inputs. When the inputs and output are not inverted, the gate is an OR or all enabled inputs. The following table summarizes the basic logic that can be obtained in gate 1 by using the gate logic select bits. The table shows the logic of four input variables, but each gate can be configured to use less than four. If no inputs are selected, the output will be zero or one, depending on the gate output polarity bit. Table 25-1. Data Gating Logic CLCxGLSy GyPOL Gate Logic 0x55 1 AND 0x55 0 NAND 0xAA 1 NOR 0xAA 0 OR 0x00 0 Logic 0 0x00 1 Logic 1 It is possible (but not recommended) to select both the true and negated values of an input. When this is done, the gate output is zero, regardless of the other inputs, but may emit logic glitches (transientinduced pulses). If the output of the channel must be zero or one, the recommended method is to set all gate bits to zero and use the gate polarity bit to set the desired level. Data gating is configured with the logic gate select registers as follows: * Gate 1: CLCxGLS0 * Gate 2: CLCxGLS1 * Gate 3: CLCxGLS2 * Gate 4: CLCxGLS3 (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 435 PIC18F26/45/46Q10 (CLC) Configurable Logic Cell Register number suffixes are different than the gate numbers because other variations of this module have multiple gate selections in the same register. Data gating is indicated in the right side of Figure 25-2. Only one gate is shown in detail. The remaining three gates are configured identically with the exception that the data enables correspond to the enables for that gate. 25.1.3 Logic Function There are eight available logic functions including: * * * * * * * * AND-OR OR-XOR AND S-R Latch D Flip-Flop with Set and Reset D Flip-Flop with Reset J-K Flip-Flop with Reset Transparent Latch with Set and Reset Logic functions are shown in the following diagram. Each logic function has four inputs and one output. The four inputs are the four data gate outputs of the previous stage. The output is fed to the inversion stage and from there to other peripherals, an output pin, and back to the CLC itself. (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 436 PIC18F26/45/46Q10 (CLC) Configurable Logic Cell Figure 25-3. Programmable Logic Functions Rev. 10-000122B 9/13/2016 AND-OR OR-XOR lcxg1 lcxg1 lcxg2 lcxg2 lcxq lcxq lcxg3 lcxg3 lcxg4 lcxg4 MODE<2:0> = 000 MODE<2:0> = 001 4-input AND S-R Latch lcxg1 lcxg1 S lcxg2 lcxg2 Q lcxq Q lcxq lcxq lcxg3 lcxg3 lcxg4 R lcxg4 MODE<2:0> = 010 MODE<2:0> = 011 1-Input D Flip-Flop with S and R 2-Input D Flip-Flop with R lcxg4 lcxg2 D lcxg1 S Q lcxq lcxg4 D lcxg2 lcxg1 R lcxg3 R lcxg3 MODE<2:0> = 100 MODE<2:0> = 101 J-K Flip-Flop with R 1-Input Transparent Latch with S and R lcxg2 J Q lcxq lcxg4 lcxg2 D lcxg3 LE S Q lcxq lcxg1 lcxg4 K R lcxg3 R lcxg1 MODE<2:0> = 110 MODE<2:0> = 111 25.1.4 Output Polarity The last stage in the CLC is the output polarity. Setting the POL bit inverts the output signal from the logic stage. Changing the polarity while the interrupts are enabled will cause an interrupt for the resulting output transition. 25.2 CLC Interrupts An interrupt will be generated upon a change in the output value of the CLCx when the appropriate interrupt enables are set. A rising edge detector and a falling edge detector are present in each CLC for this purpose. (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 437 PIC18F26/45/46Q10 (CLC) Configurable Logic Cell The CLCxIF bit of the associated PIR register will be set when either edge detector is triggered and its associated enable bit is set. The INTP enables rising edge interrupts and the INTN bit enables falling edge interrupts. To fully enable the interrupt, set the following bits: * CLCxIE bit of the respective PIE register * INTP bit (for a rising edge detection) * INTN bit (for a falling edge detection) * If priority interrupts are not used - Clear the IPEN bit of the INTCON register - Set the GIE bit of the INTCON register - Set the PEIE bit of the INTCON register * If the CLC is a high-priority interrupt - Set the IPEN bit of the INTCON register - Set the CLCxIP bit of the respective IPR register - Set the GIEH bit of the INTCON register * If the CLC is a low-priority interrupt - Set the IPEN bit of the INTCON register - Clear the CLCxIP bit of the respective IPR register - Set the GIEL bit of the INTCON register The CLCxIF bit of the respective PIR register, must be cleared in software as part of the interrupt service. If another edge is detected while this flag is being cleared, the flag will still be set at the end of the sequence. 25.3 Output Mirror Copies Mirror copies of all CLCxOUT bits are contained in the 25.8.11 CLCDATA register. Reading this register reads the outputs of all CLCs simultaneously. This prevents any reading skew introduced by testing or reading the OUT bits in the individual CLCxCON registers. 25.4 Effects of a Reset The CLCxCON register is cleared to zero as the result of a Reset. All other selection and gating values remain unchanged. 25.5 Operation During Sleep The CLC module operates independently from the system clock and will continue to run during Sleep, provided that the input sources selected remain active. The HFINTOSC remains active during Sleep when the CLC module is enabled and the HFINTOSC is selected as an input source, regardless of the system clock source selected. In other words, if the HFINTOSC is simultaneously selected as the system clock and as a CLC input source, when the CLC is enabled, the CPU will go idle during Sleep, but the CLC will continue to operate and the HFINTOSC will remain active. This will have a direct effect on the Sleep mode current. (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 438 PIC18F26/45/46Q10 (CLC) Configurable Logic Cell 25.6 CLC Setup Steps The following steps should be followed when setting up the CLC: * * * * * * * * Disable CLC by clearing the EN bit. Select desired inputs using the CLCxSEL0 through CLCxSEL3 registers (See CLC Data Input Table). Clear any associated ANSEL bits. Set all TRIS bits associated with inputs. Enable the chosen inputs through the four gates using the CLCxGLS0 through CLCxGLS3 registers. Select the gate output polarities with the GyPOL bits Select the desired logic function with the MODE bits Select the desired polarity of the logic output with the POL bit. (This step may be combined with the previous gate output polarity step). * If driving a device pin, set the desired pin PPS control register and also clear the TRIS bit corresponding to that output. * Configure the interrupts (optional). See 25.2 CLC Interrupts * Enable the CLC by setting the EN bit. (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 439 PIC18F26/45/46Q10 (CLC) Configurable Logic Cell 25.7 Register Summary - CLC Control Address Name Bit Pos. 0x0E27 CLC1CON 7:0 EN 0x0E28 CLC1POL 7:0 POL 0x0E29 CLC1SEL0 7:0 D1S[5:0] 0x0E2A CLC1SEL1 7:0 D2S[5:0] 0x0E2B CLC1SEL2 7:0 D3S[5:0] 0x0E2C CLC1SEL3 7:0 D4S[5:0] OUT INTP INTN MODE[2:0] G4POL G3POL G2POL G1POL 0x0E2D CLC1GLS0 7:0 G1D4T G1D4N G1D3T G1D3N G1D2T G1D2N G1D1T G1D1N 0x0E2E CLC1GLS1 7:0 G2D4T G2D4N G2D3T G2D3N G2D2T G2D2N G2D1T G2D1N 0x0E2F CLC1GLS2 7:0 G3D4T G3D4N G3D3T G3D3N G3D2T G3D2N G3D1T G3D1N 0x0E30 CLC1GLS3 7:0 G4D4T G4D4N G4D3T G4D3N G4D2T G4D2N G4D1T G4D1N 0x0E31 CLC2CON 7:0 EN OUT INTP INTN 0x0E32 CLC2POL 7:0 POL 0x0E33 CLC2SEL0 7:0 D1S[5:0] 0x0E34 CLC2SEL1 7:0 D2S[5:0] 0x0E35 CLC2SEL2 7:0 D3S[5:0] 0x0E36 CLC2SEL3 7:0 0x0E37 CLC2GLS0 7:0 G1D4T G1D4N G1D3T G1D3N G1D2T 0x0E38 CLC2GLS1 7:0 G2D4T G2D4N G2D3T G2D3N 0x0E39 CLC2GLS2 7:0 G3D4T G3D4N G3D3T G3D3N 0x0E3A CLC2GLS3 7:0 G4D4T G4D4N G4D3T 0x0E3B CLC3CON 7:0 EN OUT 0x0E3C CLC3POL 7:0 POL 0x0E3D CLC3SEL0 7:0 D1S[5:0] 0x0E3E CLC3SEL1 7:0 D2S[5:0] 0x0E3F CLC3SEL2 7:0 D3S[5:0] 0x0E40 CLC3SEL3 7:0 0x0E41 CLC3GLS0 7:0 G1D4T G1D4N G1D3T G1D3N G1D2T 0x0E42 CLC3GLS1 7:0 G2D4T G2D4N G2D3T G2D3N 0x0E43 CLC3GLS2 7:0 G3D4T G3D4N G3D3T G3D3N 0x0E44 CLC3GLS3 7:0 G4D4T G4D4N G4D3T G4D3N 0x0E45 CLC4CON 7:0 EN OUT INTP 0x0E46 CLC4POL 7:0 POL 0x0E47 CLC4SEL0 7:0 D1S[5:0] 0x0E48 CLC4SEL1 7:0 D2S[5:0] 0x0E49 CLC4SEL2 7:0 D3S[5:0] 0x0E4A CLC4SEL3 7:0 0x0E4B CLC4GLS0 7:0 G1D4T G1D4N G1D3T G1D3N G1D2T 0x0E4C CLC4GLS1 7:0 G2D4T G2D4N G2D3T G2D3N G2D2T 0x0E4D CLC4GLS2 7:0 G3D4T G3D4N G3D3T G3D3N 0x0E4E CLC4GLS3 7:0 G4D4T G4D4N G4D3T G4D3N 0x0E4F CLC5CON 7:0 EN OUT INTP INTN 0x0E50 CLC5POL 7:0 POL 0x0E51 CLC5SEL0 7:0 MODE[2:0] G4POL G3POL G2POL G1POL G1D2N G1D1T G1D1N G2D2T G2D2N G2D1T G2D1N G3D2T G3D2N G3D1T G3D1N G4D3N G4D2T G4D2N G4D1T G4D1N INTP INTN D4S[5:0] MODE[2:0] G4POL G3POL G2POL G1POL G1D2N G1D1T G1D1N G2D2T G2D2N G2D1T G2D1N G3D2T G3D2N G3D1T G3D1N G4D2T G4D2N G4D1T G4D1N D4S[5:0] INTN MODE[2:0] G4POL G3POL G2POL G1POL G1D2N G1D1T G1D1N G2D2N G2D1T G2D1N G3D2T G3D2N G3D1T G3D1N G4D2T G4D2N G4D1T G4D1N D4S[5:0] (c) 2019 Microchip Technology Inc. MODE[2:0] G4POL G3POL G2POL G1POL D1S[5:0] Datasheet Preliminary DS40001996C-page 440 PIC18F26/45/46Q10 (CLC) Configurable Logic Cell ...........continued Address Name Bit Pos. 0x0E52 CLC5SEL1 7:0 D2S[5:0] 0x0E53 CLC5SEL2 7:0 D3S[5:0] 0x0E54 CLC5SEL3 7:0 0x0E55 CLC5GLS0 7:0 G1D4T G1D4N G1D3T G1D3N G1D2T G1D2N G1D1T G1D1N 0x0E56 CLC5GLS1 7:0 G2D4T G2D4N G2D3T G2D3N G2D2T G2D2N G2D1T G2D1N 0x0E57 CLC5GLS2 7:0 G3D4T G3D4N G3D3T G3D3N G3D2T G3D2N G3D1T G3D1N 0x0E58 CLC5GLS3 7:0 G4D4T G4D4N G4D3T G4D3N G4D2T G4D2N G4D1T G4D1N OUT INTP D4S[5:0] 0x0E59 CLC6CON 7:0 EN 0x0E5A CLC6POL 7:0 POL INTN MODE[2:0] 0x0E5B CLC6SEL0 7:0 D1S[5:0] 0x0E5C CLC6SEL1 7:0 D2S[5:0] 0x0E5D CLC6SEL2 7:0 D3S[5:0] 0x0E5E CLC6SEL3 7:0 0x0E5F CLC6GLS0 7:0 G1D4T G1D4N G1D3T G1D3N G1D2T 0x0E60 CLC6GLS1 7:0 G2D4T G2D4N G2D3T G2D3N G2D2T 0x0E61 CLC6GLS2 7:0 G3D4T G3D4N G3D3T G3D3N 0x0E62 CLC6GLS3 7:0 G4D4T G4D4N G4D3T G4D3N 0x0E63 CLC7CON 7:0 EN OUT INTP INTN 0x0E64 CLC7POL 7:0 POL 0x0E65 CLC7SEL0 7:0 D1S[5:0] 0x0E66 CLC7SEL1 7:0 D2S[5:0] 0x0E67 CLC7SEL2 7:0 D3S[5:0] 0x0E68 CLC7SEL3 7:0 D4S[5:0] G4POL G3POL G2POL G1POL G1D2N G1D1T G1D1N G2D2N G2D1T G2D1N G3D2T G3D2N G3D1T G3D1N G4D2T G4D2N G4D1T G4D1N D4S[5:0] MODE[2:0] G4POL G3POL G2POL G1POL 0x0E69 CLC7GLS0 7:0 G1D4T G1D4N G1D3T G1D3N G1D2T G1D2N G1D1T G1D1N 0x0E6A CLC7GLS1 7:0 G2D4T G2D4N G2D3T G2D3N G2D2T G2D2N G2D1T G2D1N 0x0E6B CLC7GLS2 7:0 G3D4T G3D4N G3D3T G3D3N G3D2T G3D2N G3D1T G3D1N 0x0E6C CLC7GLS3 7:0 G4D4T G4D4N G4D3T G4D3N G4D2T G4D2N G4D1T G4D1N 0x0E6D CLC8CON 7:0 EN OUT INTP INTN 0x0E6E CLC8POL 7:0 POL 0x0E6F CLC8SEL0 7:0 D1S[5:0] 0x0E70 CLC8SEL1 7:0 D2S[5:0] 0x0E71 CLC8SEL2 7:0 D3S[5:0] 0x0E72 CLC8SEL3 7:0 0x0E73 CLC8GLS0 7:0 G1D4T G1D4N G1D3T G1D3N G1D2T 0x0E74 CLC8GLS1 7:0 G2D4T G2D4N G2D3T G2D3N 0x0E75 CLC8GLS2 7:0 G3D4T G3D4N G3D3T G3D3N 0x0E76 CLC8GLS3 7:0 G4D4T G4D4N G4D3T G4D3N G4D2T G4D2N G4D1T G4D1N 0x0E77 CLCDATA 7:0 MLC8OUT MLC7OUT MLC6OUT MLC5OUT MLC4OUT MLC3OUT MLC2OUT MLC1OUT 25.8 MODE[2:0] G4POL G3POL G2POL G1POL G1D2N G1D1T G1D1N G2D2T G2D2N G2D1T G2D1N G3D2T G3D2N G3D1T G3D1N D4S[5:0] Register Definitions: Configurable Logic Cell Long bit name prefixes for the CLC peripherals are shown in the table below. Refer to the "Long Bit Names Section" for more information. (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 441 PIC18F26/45/46Q10 (CLC) Configurable Logic Cell Table 25-2. CLC Bit Name Prefixes Peripheral Bit Name Prefix CLC1 LC1 CLC2 LC2 CLC3 LC3 CLC4 LC4 CLC5 LC5 CLC6 LC6 CLC7 LC7 CLC8 LC8 Related Links 1.4.2.2 Long Bit Names (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 442 PIC18F26/45/46Q10 (CLC) Configurable Logic Cell 25.8.1 CLCxCON Name: Address: CLCxCON 0xE27,0xE31,0xE3B,0xE45,0xE4F,0xE59,0xE63,0xE6D Configurable Logic Cell Control Register Bit Access Reset 5 4 3 EN 7 6 OUT INTP INTN 2 1 0 R/W RO R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 MODE[2:0] Bit 7 - EN CLC Enable bit Value Description 1 Configurable logic cell is enabled and mixing signals 0 Configurable logic cell is disabled and has logic zero output Bit 5 - OUT Logic cell output data, after LCPOL. Sampled from CLCxOUT Bit 4 - INTP Configurable Logic Cell Positive Edge Going Interrupt Enable bit Value Description 1 CLCxIF will be set when a rising edge occurs on CLCxOUT 0 Rising edges on CLCxOUT have no effect on CLCxIF Bit 3 - INTN Configurable Logic Cell Negative Edge Going Interrupt Enable bit Value Description 1 CLCxIF will be set when a falling edge occurs on CLCxOUT 0 Falling edges on CLCxOUT have no effect on CLCxIF Bits 2:0 - MODE[2:0] Configurable Logic Cell Functional Mode Selection bits Value Description 111 Cell is 1-input transparent latch with Set and Reset 110 Cell is J-K flip-flop with Reset 101 Cell is 2-input D flip-flop with Reset 100 Cell is 1-input D flip-flop with Set and Reset 011 Cell is S-R latch 010 Cell is 4-input AND 001 Cell is OR-XOR 000 Cell is AND-OR (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 443 PIC18F26/45/46Q10 (CLC) Configurable Logic Cell 25.8.2 CLCxPOL Name: Address: CLCxPOL 0xE28,0xE32,0xE3C,0xE46,0xE50,0xE5A,0xE64,0xE6E Signal Polarity Control Register Bit Access Reset 3 2 1 0 POL 7 6 5 4 G4POL G3POL G2POL G1POL R/W R/W R/W R/W R/W 0 x x x x Bit 7 - POL CLCxOUT Output Polarity Control bit Value Description 1 The output of the logic cell is inverted 0 The output of the logic cell is not inverted Bits 0, 1, 2, 3 - GyPOL Gate Output Polarity Control bit Reset States: Default = xxxx POR/BOR = x All Other Resets = u Value Description 1 The gate output is inverted when applied to the logic cell 0 The output of the gate is not inverted (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 444 PIC18F26/45/46Q10 (CLC) Configurable Logic Cell 25.8.3 CLCxSEL0 Name: Address: CLCxSEL0 0xE29,0xE33,0xE3D,0xE47,0xE51,0xE5B,0xE65,0xE6F Generic CLCx Data 1 Select Register Bit 7 6 5 4 3 2 1 0 D1S[5:0] Access Reset R/W R/W R/W R/W R/W R/W x x x x x x Bits 5:0 - D1S[5:0] CLCx Data1 Input Selection bits Reset States: POR/BOR = xxxxxx All Other Resets = uuuuuu Value Description n Refer to CLC Input Sources for input selections (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 445 PIC18F26/45/46Q10 (CLC) Configurable Logic Cell 25.8.4 CLCxSEL1 Name: Address: CLCxSEL1 0xE2A,0xE34,0xE3E,0xE48,0xE52,0xE5C,0xE66,0xE70 Generic CLCx Data 1 Select Register Bit 7 6 5 4 3 2 1 0 D2S[5:0] Access Reset R/W R/W R/W R/W R/W R/W x x x x x x Bits 5:0 - D2S[5:0] CLCx Data2 Input Selection bits Reset States: POR/BOR = xxxxxx All Other Resets = uuuuuu Value Description n Refer to CLC Input Sources for input selections (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 446 PIC18F26/45/46Q10 (CLC) Configurable Logic Cell 25.8.5 CLCxSEL2 Name: Address: CLCxSEL2 0xE2B,0xE35,0xE3F,0xE49,0xE53,0xE5D,0xE67,0xE71 Generic CLCx Data 1 Select Register Bit 7 6 5 4 3 2 1 0 D3S[5:0] Access Reset R/W R/W R/W R/W R/W R/W x x x x x x Bits 5:0 - D3S[5:0] CLCx Data3 Input Selection bits Reset States: POR/BOR = xxxxxx All Other Resets = uuuuuu Value Description n Refer to CLC Input Sources for input selections (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 447 PIC18F26/45/46Q10 (CLC) Configurable Logic Cell 25.8.6 CLCxSEL3 Name: Address: CLCxSEL3 0xE2C,0xE36,0xE40,0xE4A,0xE54,0xE5E,0xE68,0xE72 Generic CLCx Data 4 Select Register Bit 7 6 5 4 3 2 1 0 D4S[5:0] Access Reset R/W R/W R/W R/W R/W R/W x x x x x x Bits 5:0 - D4S[5:0] CLCx Data4 Input Selection bits Reset States: POR/BOR = xxxxxx All Other Resets = uuuuuu Value Description n Refer to CLC Input Sources for input selections (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 448 PIC18F26/45/46Q10 (CLC) Configurable Logic Cell 25.8.7 CLCxGLS0 Name: Address: CLCxGLS0 0xE2D,0xE37,0xE41,0xE4B,0xE55,0xE5F,0xE69,0xE73 CLCx Gate1 Logic Select Register Bit Access Reset 7 6 5 4 3 2 1 0 G1D4T G1D4N G1D3T G1D3N G1D2T G1D2N G1D1T G1D1N R/W R/W R/W R/W R/W R/W R/W R/W x x x x x x x x Bits 1, 3, 5, 7 - G1DyT dyT: Gate1 Data 'y' True (non-inverted) bit Reset States: Default = xxxx POR/BOR = x All Other Resets = u Value Description 1 dyT is gated into g1 0 dyT is not gated into g1 Bits 0, 2, 4, 6 - G1DyN dyN: Gate1 Data 'y' Negated (inverted) bit Reset States: Default = xxxx POR/BOR = x All Other Resets = u Value Description 1 dyN is gated into g1 0 dyN is not gated into g1 (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 449 PIC18F26/45/46Q10 (CLC) Configurable Logic Cell 25.8.8 CLCxGLS1 Name: Address: CLCxGLS1 0xE2E,0xE38,0xE42,0xE4C,0xE56,0xE60,0xE6A,0xE74 CLCx Gate2 Logic Select Register Bit Access Reset 7 6 5 4 3 2 1 0 G2D4T G2D4N G2D3T G2D3N G2D2T G2D2N G2D1T G2D1N R/W R/W R/W R/W R/W R/W R/W R/W x x x x x x x x Bits 1, 3, 5, 7 - G2DyT dyT: Gate2 Data 'y' True (non-inverted) bit Reset States: Default = xxxx POR/BOR = x All Other Resets = u Value Description 1 dyT is gated into g2 0 dyT is not gated into g2 Bits 0, 2, 4, 6 - G2DyN dyN: Gate2 Data 'y' Negated (inverted) bit Reset States: Default = xxxx POR/BOR = x All Other Resets = u Value Description 1 dyN is gated into g2 0 dyN is not gated into g2 (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 450 PIC18F26/45/46Q10 (CLC) Configurable Logic Cell 25.8.9 CLCxGLS2 Name: Address: CLCxGLS2 0xE2F,0xE39,0xE43,0xE4D,0xE57,0xE61,0xE6B,0xE75 CLCx Gate3 Logic Select Register Bit Access Reset 7 6 5 4 3 2 1 0 G3D4T G3D4N G3D3T G3D3N G3D2T G3D2N G3D1T G3D1N R/W R/W R/W R/W R/W R/W R/W R/W x x x x x x x x Bits 1, 3, 5, 7 - G3DyT dyT: Gate3 Data 'y' True (non-inverted) bit Reset States: Default = xxxx POR/BOR = x All Other Resets = u Value Description 1 dyT is gated into g3 0 dyT is not gated into g3 Bits 0, 2, 4, 6 - G3DyN dyN: Gate3 Data 'y' Negated (inverted) bit Reset States: Default = xxxx POR/BOR = x All Other Resets = u Value Description 1 dyN is gated into g3 0 dyN is not gated into g3 (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 451 PIC18F26/45/46Q10 (CLC) Configurable Logic Cell 25.8.10 CLCxGLS3 Name: Address: CLCxGLS3 0xE30,0xE3A,0xE44,0xE4E,0xE58,0xE62,0xE6C,0xE76 CLCx Gate4 Logic Select Register Bit Access Reset 7 6 5 4 3 2 1 0 G4D4T G4D4N G4D3T G4D3N G4D2T G4D2N G4D1T G4D1N R/W R/W R/W R/W R/W R/W R/W R/W x x x x x x x x Bits 1, 3, 5, 7 - G4DyT dyT: Gate4 Data 'y' True (non-inverted) bit Reset States: Default = xxxx POR/BOR = x All Other Resets = u Value Description 1 dyT is gated into g4 0 dyT is not gated into g4 Bits 0, 2, 4, 6 - G4DyN dyN: Gate4 Data 'y' Negated (inverted) bit Reset States: Default = xxxx POR/BOR = x All Other Resets = u Value Description 1 dyN is gated into g4 0 dyN is not gated into g4 (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 452 PIC18F26/45/46Q10 (CLC) Configurable Logic Cell 25.8.11 CLCDATA Name: Address: CLCDATA 0xE77 CLC Data Ouput Register Mirror copy of Bit Access Reset 7 6 5 4 3 2 1 0 MLC8OUT MLC7OUT MLC6OUT MLC5OUT MLC4OUT MLC3OUT MLC2OUT MLC1OUT R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Bits 0, 1, 2, 3, 4, 5, 6, 7 - MLCxOUT Mirror copy of CLCx_out bit Value Description 1 CLCx_out is 1 0 CLCx_out is 0 (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 453 PIC18F26/45/46Q10 (DSM) Data Signal Modulator Module 26. (DSM) Data Signal Modulator Module The Data Signal Modulator (DSM) is a peripheral that allows the user to mix a data stream, also known as a modulator signal, with a carrier signal to produce a modulated output. Both the carrier and the modulator signals are supplied to the DSM module either internally, from the output of a peripheral, or externally through an input pin. The modulated output signal is generated by performing a logical "AND" operation of both the carrier and modulator signals and then provided to the MDOUT pin. The carrier signal is comprised of two distinct and separate signals. A Carrier High (CARH) signal and a Carrier Low (CARL) signal. During the time in which the modulator (MOD) signal is in a logic high state, the DSM mixes the CARH signal with the modulator signal. When the modulator signal is in a logic low state, the DSM mixes the CARL signal with the modulator signal. Using this method, the DSM can generate the following types of key modulation schemes: * Frequency-Shift Keying (FSK) * Phase-Shift Keying (PSK) * On-Off Keying (OOK) Additionally, the following features are provided within the DSM module: * * * * * Carrier Synchronization Carrier Source Polarity Select Programmable Modulator Data Modulated Output Polarity Select Peripheral Module Disable, which provides the ability to place the DSM module in the lowest power consumption mode The figure below shows a simplified block diagram of the data signal modulator peripheral. (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 454 PIC18F26/45/46Q10 (DSM) Data Signal Modulator Module Figure 26-1. Simplified Block Diagram of the Data Signal Modulator MDCHS<2:0> Rev. 10-000248E 8/7/2015 Data Signal Modulator 000 See MDCARH Register CARH MDCHPOL D SYNC 111 Q 1 MDSRCS<3:0> 0 0000 MDCHSYNC RxyPPS See MDSRC Register MOD PPS MDOPOL 1111 MDCLS<2:0> D SYNC 000 Q 1 0 See MDCARL Register CARL MDCLSYNC MDCLPOL 111 (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 455 PIC18F26/45/46Q10 (DSM) Data Signal Modulator Module 26.1 DSM Operation The DSM module can be enabled by setting the EN bit in the MDCON0 register. Clearing the EN bit, disables the output of the module but retain the carrier and source signal selections. The module will resume operation when the EN bit is set again. The output of the DSM module can be rerouted to several pins using the RxyPPS register. When the EN bit is cleared the output pin is held low. 26.2 Modulator Signal Sources The modulator signal can be supplied from the following sources selected with the SRCS bits: Table 26-1. MDSRC Selection MUX Connections SRCS[3:0] Connection 11000-11111 Reserved 10111 CLC8_out 10110 CLC7_out 10101 CLC6_out 10100 CLC5_out 10011 CLC4_out 10010 CLC3_out 10001 CLC2_out 10000 CLC1_out 01111 Reserved 01110 Reserved 01101 EUSART2 TX (TX/CK output) 01100 EUSART2 RX (DT output) 01011 MSSP2 - SDO 01010 MSSP1 - SDO 01001 EUSART1 TX (TX/CK output) 01000 EUSART1 RX (DT output) 00111 CMP2 OUT 00110 CMP1 OUT 00101 PWM4 OUT 00100 PWM3 OUT 00011 CCP2 OUT 00010 CCP1 OUT 00001 MDBIT (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 456 PIC18F26/45/46Q10 (DSM) Data Signal Modulator Module ...........continued 26.3 SRCS[3:0] Connection 00000 Pin selected by MDSRCPPS Carrier Signal Sources The carrier high signal and carrier low signal can be supplied from the following sources. The carrier high signal is selected by configuring the CHS bits. Table 26-2. MDCARH Source Selections MDCARH CHS[2:0] Connection 1111 CLC8_out 1110 CLC7_out 1101 CLC6_out 1100 CLC5_out 1011 CLC4_out 1010 CLC3_out 1001 CLC2_out 1000 CLC1_out 0111 PWM4 OUT 0110 PWM3 OUT 0101 CCP2 OUT 0100 CCP1 OUT 0011 CLKREF output 0010 HFINTOSC 0001 FOSC (system clock) 0000 Pin selected by MDCARHPPS The carrier low signal is selected by configuring the CLS bits. Table 26-3. MDCARL Source Selections MDCARL CLS[2:0] Connection 1111 CLC8_out 1110 CLC7_out 1101 CLC6_out (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 457 PIC18F26/45/46Q10 (DSM) Data Signal Modulator Module ...........continued MDCARL 26.4 CLS[2:0] Connection 1100 CLC5_out 1011 CLC4_out 1010 CLC3_out 1001 CLC2_out 1000 CLC1_out 0111 PWM4 OUT 0110 PWM3 OUT 0101 CCP2 OUT 0100 CCP1 OUT 0011 CLKREF output 0010 HFINTOSC 0001 FOSC (system clock) 0000 Pin selected by MDCARLPPS Carrier Synchronization During the time when the DSM switches between carrier high and carrier low signal sources, the carrier data in the modulated output signal can become truncated. To prevent this, the carrier signal can be synchronized to the modulator signal. When synchronization is enabled, the carrier pulse that is being mixed at the time of the transition is allowed to transition low before the DSM switches over to the next carrier source. Synchronization is enabled separately for the carrier high and carrier low signal sources. Synchronization for the carrier high signal is enabled by setting the CHSYNC bit. Synchronization for the carrier low signal is enabled by setting the CLSYNC bit. The figures below show the timing diagrams of using various synchronization methods. (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 458 PIC18F26/45/46Q10 (DSM) Data Signal Modulator Module Figure 26-2. On Off Keying (OOK) Synchronization Rev. 30-000144A 5/26/2017 carrier_low carrier_high modulator MDCHSYNC = 1 MDCLSYNC = 0 MDCHSYNC = 1 MDCLSYNC = 1 MDCHSYNC = 0 MDCLSYNC = 0 MDCHSYNC = 0 MDCLSYNC = 1 Figure 26-3. No Synchronization (MDCHSYNC = 0, MDCLSYNC = 0) Rev. 30-000145A 5/26/2017 carrier_high carrier_low modulator MDCHSYNC = 0 MDCLSYNC = 0 Active Carrier State carrier_high carrier_low carrier_high carrier_low Figure 26-4. Carrier High Synchronization (MDCHSYNC = 1, MDCLSYNC = 0) Rev. 30-000146A 5/26/2017 carrier_high carrier_low modulator MDCHSYNC = 1 MDCLSYNC = 0 Active Carrier State carrier_high (c) 2019 Microchip Technology Inc. both carrier_low carrier_high Datasheet Preliminary both carrier_low DS40001996C-page 459 PIC18F26/45/46Q10 (DSM) Data Signal Modulator Module Figure 26-5. Carrier Low Synchronization (MDCHSYNC = 0, MDCLSYNC = 1) Rev. 30-000147A 5/26/2017 carrier_high carrier_low modulator MDCHSYNC = 0 MDCLSYNC = 1 Active Carrier State carrier_high carrier_low carrier_high carrier_low Figure 26-6. Full Synchronization (MDCHSYNC = 1, MDCLSYNC = 1) Rev. 30-000148A 5/26/2017 carrier_high carrier_low modulator Falling edges used to sync MDCHSYNC = 1 MDCLSYNC = 1 Active Carrier State 26.5 carrier_high carrier_low carrier_high CL Carrier Source Polarity Select The signal provided from any selected input source for the carrier high and carrier low signals can be inverted. Inverting the signal for the carrier high and low source is enabled by setting the CHPOL bit and the CLPOL bit, respectively. 26.6 Programmable Modulator Data The BIT control bit can be selected as the modulation source. This gives the user the ability to provide software driven modulation. 26.7 Modulated Output Polarity The modulated output signal provided on the DSM pin can also be inverted. Inverting the modulated output signal is enabled by setting the OPOL bit. 26.8 Operation in Sleep Mode The DSM can still operate during Sleep, if the carrier and modulator input sources are also still operable during Sleep. Refer to "Power-Saving Operation Modes" for more details. Related Links 6.4 Peripheral Operation in Power-Saving Modes (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 460 PIC18F26/45/46Q10 (DSM) Data Signal Modulator Module 26.9 Effects of a Reset Upon any device Reset, the DSM module is disabled. The user's firmware is responsible for initializing the module before enabling the output. All the registers are reset to their default values. 26.10 Peripheral Module Disable The DSM module can be completely disabled using the PMD module to achieve maximum power saving. When the DSMMD bit of PMDx register is set, the DSM module is completely disabled. This puts the module in its lowest power consumption state. When enabled again all the registers of the DSM module default to POR status. Related Links 7.4 Register Definitions: Peripheral Module Disable (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 461 PIC18F26/45/46Q10 (DSM) Data Signal Modulator Module 26.11 Register Summary - DSM Address Name Bit Pos. 0x0F4C MDCON0 7:0 0x0F4D MDCON1 7:0 0x0F4E MDSRC 7:0 0x0F4F MDCARL 7:0 CLS[3:0] 0x0F50 MDCARH 7:0 CHS[3:0] 26.12 EN OUT OPOL CHPOL CHSYNC BIT CLPOL CLSYNC SRCS[4:0] Register Definitions: Modulation Control Long bit name prefixes for the modulation control peripherals are shown in the table below. Refer to the "Long Bit Names Section" for more information. Table 26-4. Modulation Control Long Bit Name Prefixes Peripheral Bit Name Prefix MD MD Related Links 1.4.2.2 Long Bit Names (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 462 PIC18F26/45/46Q10 (DSM) Data Signal Modulator Module 26.12.1 MDCON0 Name: Address: MDCON0 0xF4C Modulation Control Register 0 Bit Access Reset 5 4 EN 7 OUT OPOL BIT R/W R/W R/W R/W 0 0 0 0 Bit 7 - EN Value 1 0 6 3 2 1 0 Modulator Module Enable bit Description Modulator module is enabled and mixing input signals Modulator module is disabled and has no output Bit 5 - OUT Modulator Output bit Displays the current output value of the modulator module. Bit 4 - OPOL Modulator Output Polarity Select bit Value Description 1 Modulator output signal is inverted; idle high output 0 Modulator output signal is not inverted; idle low output Bit 0 - BIT Modulation Source Select Input bit Allows software to manually set modulation source input to module Note: 1. The modulated output frequency can be greater and asynchronous from the clock that updates this register bit, the bit value may not be valid for higher speed modulator or carrier signals. 2. MDBIT must be selected as the modulation source in the MDSRC register for this operation. (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 463 PIC18F26/45/46Q10 (DSM) Data Signal Modulator Module 26.12.2 MDCON1 Name: Address: MDCON1 0xF4D Modulation Control Register 1 Bit 7 6 Access Reset 5 4 1 0 CHPOL CHSYNC 3 2 CLPOL CLSYNC R/W R/W R/W R/W 0 0 0 0 Bit 5 - CHPOL Modulator High Carrier Polarity Select bit Value Description 1 Selected high carrier signal is inverted 0 Selected high carrier signal is not inverted Bit 4 - CHSYNC Modulator High Carrier Synchronization Enable bit Value Description 1 Modulator waits for a falling edge on the high time carrier signal before allowing a switch to the low time carrier 0 Modulator output is not synchronized to the high time carrier signal Bit 1 - CLPOL Modulator Low Carrier Polarity Select bit Value Description 1 Selected low carrier signal is inverted 0 Selected low carrier signal is not inverted Bit 0 - CLSYNC Modulator Low Carrier Synchronization Enable bit Value Description 1 Modulator waits for a falling edge on the low time carrier signal before allowing a switch to the high time carrier 0 Modulator output is not synchronized to the low time carrier signal Note: 1. Narrowed carrier pulse widths or spurs may occur in the signal stream if the carrier is not synchronized. (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 464 PIC18F26/45/46Q10 (DSM) Data Signal Modulator Module 26.12.3 MDCARH Name: Address: MDCARH 0xF50 Modulation High Carrier Control Register Bit 7 6 5 4 3 2 1 0 CHS[3:0] Access R/W R/W R/W R/W 0 0 0 0 Reset Bits 3:0 - CHS[3:0] Modulator Carrier High Selection bits Table 26-5. MDCARH Source Selections MDCARH CHS[2:0] Connection 1111 CLC8_out 1110 CLC7_out 1101 CLC6_out 1100 CLC5_out 1011 CLC4_out 1010 CLC3_out 1001 CLC2_out 1000 CLC1_out 0111 PWM4 OUT 0110 PWM3 OUT 0101 CCP2 OUT 0100 CCP1 OUT 0011 CLKREF output 0010 HFINTOSC 0001 FOSC (system clock) 0000 Pin selected by MDCARHPPS (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 465 PIC18F26/45/46Q10 (DSM) Data Signal Modulator Module 26.12.4 MDCARL Name: Address: MDCARL 0xF4F Modulation Low Carrier Control Register Bit 7 6 5 4 3 2 1 0 CLS[3:0] Access R/W R/W R/W R/W 0 0 0 0 Reset Bits 3:0 - CLS[3:0] Modulator Carrier Low Input Selection bits Table 26-6. MDCARL Source Selections MDCARL CLS[2:0] Connection 1111 CLC8_out 1110 CLC7_out 1101 CLC6_out 1100 CLC5_out 1011 CLC4_out 1010 CLC3_out 1001 CLC2_out 1000 CLC1_out 0111 PWM4 OUT 0110 PWM3 OUT 0101 CCP2 OUT 0100 CCP1 OUT 0011 CLKREF output 0010 HFINTOSC 0001 FOSC (system clock) 0000 Pin selected by MDCARLPPS (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 466 PIC18F26/45/46Q10 (DSM) Data Signal Modulator Module 26.12.5 MDSRC Name: Address: MDSRC 0xF4E Modulation Source Control Register Bit 7 6 5 4 3 2 1 0 SRCS[4:0] Access Reset R/W R/W R/W R/W R/W 0 0 0 0 0 Bits 4:0 - SRCS[4:0] Modulator Source Selection bits Table 26-7. MDSRC Selection MUX Connections SRCS[3:0] Connection 11000-11111 Reserved 10111 CLC8_out 10110 CLC7_out 10101 CLC6_out 10100 CLC5_out 10011 CLC4_out 10010 CLC3_out 10001 CLC2_out 10000 CLC1_out 01111 Reserved 01110 Reserved 01101 EUSART2 TX (TX/CK output) 01100 EUSART2 RX (DT output) 01011 MSSP2 - SDO 01010 MSSP1 - SDO 01001 EUSART1 TX (TX/CK output) 01000 EUSART1 RX (DT output) 00111 CMP2 OUT 00110 CMP1 OUT 00101 PWM4 OUT 00100 PWM3 OUT 00011 CCP2 OUT (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 467 PIC18F26/45/46Q10 (DSM) Data Signal Modulator Module ...........continued SRCS[3:0] Connection 00010 CCP1 OUT 00001 MDBIT 00000 Pin selected by MDSRCPPS (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 468 PIC18F26/45/46Q10 (MSSP) Master Synchronous Serial Port Module 27. (MSSP) Master Synchronous Serial Port Module The Master Synchronous Serial Port (MSSP) module is a serial interface useful for communicating with other peripheral or microcontroller devices. These peripheral devices may be serial EEPROMs, Shift registers, display drivers, A/D converters, etc. The MSSP module can operate in one of two modes: * Serial Peripheral Interface (SPI) * Inter-Integrated Circuit (I2C) The SPI interface supports the following modes and features: * * * * * Master mode Slave mode Clock Parity Slave Select Synchronization (Slave mode only) Daisy-chain connection of slave devices The I2C interface supports the following modes and features: * * * * * * * * * * * * * 27.1 Master mode Slave mode Byte NACKing (Slave mode) Limited multi-master support 7-bit and 10-bit addressing Start and Stop interrupts Interrupt masking Clock stretching Bus collision detection General call address matching Address masking Address Hold and Data Hold modes Selectable SDA hold times SPI Mode Overview The Serial Peripheral Interface (SPI) bus is a synchronous serial data communication bus that operates in Full-Duplex mode. Devices communicate in a master/slave environment where the master device initiates the communication. A slave device is controlled through a Chip Select known as Slave Select. The SPI bus specifies four signal connections: * * * * Serial Clock (SCK) Serial Data Out (SDO) Serial Data In (SDI) Slave Select (SS) The following figure shows the block diagram of the MSSP module when operating in SPI mode. (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 469 PIC18F26/45/46Q10 (MSSP) Master Synchronous Serial Port Module Figure 27-1. MSSP Block Diagram (SPI mode) Rev. 30-000011A 3/31/2017 Data Bus Write Read SSPxBUF Reg SSPxDATPPS SDI PPS SSPSR Reg Shift Clock bit 0 SDO PPS RxyPPS SS SS Control Enable PPS SSPxSSPPS Edge Select SSPxCLKPPS(2) SCK SSPM<3:0> 4 PPS PPS TRIS bit 2 (CKP, CKE) Clock Select Edge Select RxyPPS(1) ( T2_match 2 ) Prescaler TOSC 4, 16, 64 Baud Rate Generator (SSPxADD) Note 1: Output selection for master mode 2: Input selection for slave and master mode The SPI bus operates with a single master device and one or more slave devices. When multiple slave devices are used, an independent Slave Select connection is required from the master device to each slave device. The figure below shows a typical connection between a master device and multiple slave devices. The master selects only one slave at a time. Most slave devices have tri-state outputs so their output signal appears disconnected from the bus when they are not selected. (c)2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 470 PIC18F26/45/46Q10 (MSSP) Master Synchronous Serial Port Module Figure 27-2. SPI Master and Multiple Slave Connection Rev. 30-000012A 3/31/2017 SPI Master SCK SCK SDO SDI SDI SDO General I/O General I/O SS General I/O SCK SDI SDO SPI Slave #1 SPI Slave #2 SS SCK SDI SDO SPI Slave #3 SS 27.1.1 SPI Mode Registers The MSSP module has five registers for SPI mode operation. These are: * * * * * * MSSP STATUS register (SSPxSTAT) MSSP Control register 1 (SSPxCON1) MSSP Control register 3 (SSPxCON3) MSSP Data Buffer register (SSPxBUF) MSSP Address register (SSPxADD) MSSP Shift register (SSPSR) (Not directly accessible) SSPxCON1 and SSPxSTAT are the control and STATUS registers for SPI mode operation. The SSPxCON1 register is readable and writable. The lower six bits of the SSPxSTAT are read-only. The upper two bits of the SSPxSTAT are read/write. One of the five SPI Master modes uses the SSPxADD value to determine the Baud Rate Generator clock frequency. More information on the Baud Rate Generator is available in 27.7 Baud Rate Generator. SSPSR is the Shift register used for shifting data in and out. SSPxBUF provides indirect access to the SSPSR register. SSPxBUF is the Buffer register to which data bytes are written, and from which data bytes are read. In receive operations, SSPSR and SSPxBUF together create a buffered receiver. When SSPSR receives a complete byte, it is transferred to SSPxBUF and the SSPxIF interrupt is set. During transmission, the SSPxBUF is not buffered. A write to SSPxBUF will write to both SSPxBUF and SSPSR. 27.2 SPI Mode Operation Transmissions involve two Shift registers, eight bits in size, one in the master and one in the slave. With either the master or the slave device, data is always shifted out one bit at a time, with the Most Significant (c)2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 471 PIC18F26/45/46Q10 (MSSP) Master Synchronous Serial Port Module bit (MSb) shifted out first. At the same time, a new Least Significant bit (LSb) is shifted into the same register. The following figure shows a typical connection between two processors configured as master and slave devices. Figure 27-3. SPI Master/Slave Connection Rev/ 30-000013A 3/31/2017 SPI Master SSPM<3:0> = 00xx = 1010 SPI Slave SSPM<3:0> = 010x SDO SDI Serial Input Buffer (BUF) LSb SCK General I/O Processor 1 SDO SDI Shift Register (SSPSR) MSb Serial Input Buffer (SSPxBUF) Serial Clock Slave Select (optional) Shift Register (SSPSR) MSb LSb SCK SS Processor 2 Data is shifted out of both Shift registers on the programmed clock edge and latched on the opposite edge of the clock. The master device transmits information out on its SDO output pin, which is connected to and received by the slave's SDI input pin. The slave device transmits information out on its SDO output pin, which is connected to and received by the master's SDI input pin. To begin communication the master device first sends out the clock signal. Both the master and the slave devices should be configured for the same clock polarity. The master device starts a transmission by sending out the MSb from its Shift register. The slave device reads this bit from that same line and saves it into the LSb position of its Shift register. During each SPI clock cycle, a full-duplex data transmission occurs. This means that while the master device is sending out the MSb from its Shift register (on its SDO pin) and the slave device is reading this bit and saving it as the LSb of its Shift register, the slave device is also sending out the MSb from its Shift register (on its SDO pin) and the master device is reading this bit and saving it as the LSb of its Shift register. After eight bits have been shifted out, the master and slave have exchanged register values. If there is more data to exchange, the Shift registers are loaded with new data and the process repeats itself. Whether the data is meaningful or not (dummy data), depends on the application software. This leads to three scenarios for data transmission: * Master sends useful data and slave sends dummy data. * Master sends useful data and slave sends useful data. (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 472 PIC18F26/45/46Q10 (MSSP) Master Synchronous Serial Port Module * Master sends dummy data and slave sends useful data. Transmissions may involve any number of clock cycles. When there is no more data to be transmitted, the master stops sending the clock signal and it deselects the slave. Every slave device connected to the bus that has not been selected through its slave select line must disregard the clock and transmission signals and must not transmit out any data of its own. When initializing the SPI several options need to be specified. This is done by programming the appropriate control bits (SSPxCON1<5:0> and SSPxSTAT<7:6>). These control bits allow the following to be specified: * * * * * * * Master mode (SCK is the clock output) Slave mode (SCK is the clock input) Clock Polarity (Idle state of SCK) Data Input Sample Phase (middle or end of data output time) Clock Edge (output data on rising/falling edge of SCK) Clock Rate (Master mode only) Slave Select mode (Slave mode only) To enable the serial port the SSP Enable bit, SSPEN, must be set. To reset or reconfigure SPI mode, clear the SSPEN bit, re-initialize the SSPxCONx registers and then set the SSPEN bit. The SDI, SDO, SCK and SS serial port pins are selected with the PPS controls. For the pins to behave as the serial port function, some must have their data direction bits (in the TRIS register) appropriately programmed as follows: * * * * * * SDI must have corresponding TRIS bit set SDO must have corresponding TRIS bit cleared SCK (Master mode) must have corresponding TRIS bit cleared SCK (Slave mode) must have corresponding TRIS bit set The RxyPPS and SSPxCLKPPS controls must select the same pin SS must have corresponding TRIS bit set Any serial port function that is not desired may be overridden by programming the corresponding data direction (TRIS) register to the opposite value. The MSSP consists of a transmit/receive shift register (SSPSR) and a buffer register (SSPxBUF). The SSPSR shifts the data in and out of the device, MSb first. The SSPxBUF holds the data that was written to the SSPSR until the received data is ready. Once the eight bits of data have been received, that byte is moved to the SSPxBUF register. Then, the Buffer Full Detect bit, BF, and the Interrupt Flag bit, SSPxIF, are set. This double-buffering of the received data (SSPxBUF) allows the next byte to start reception before reading the data that was just received. Any write to the SSPxBUF register during transmission/ reception of data will be ignored and the write collision detect bit, WCOL, will be set. User software must clear the WCOL bit to allow the following write(s) to the SSPxBUF register to complete successfully. When the application software is expecting to receive valid data, the SSPxBUF should be read before the next byte of data to transfer is written to the SSPxBUF. The Buffer Full bit, BF, indicates when SSPxBUF has been loaded with the received data (transmission is complete). When the SSPxBUF is read, the BF bit is cleared. This data may be irrelevant if the SPI is only a transmitter. Generally, the MSSP interrupt is used to determine when the transmission/reception has completed. If the interrupt method is not going to be used, then software polling can be done to ensure that a write collision does not occur. (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 473 PIC18F26/45/46Q10 (MSSP) Master Synchronous Serial Port Module The SSPSR is not directly readable or writable and can only be accessed by addressing the SSPxBUF register. Additionally, the SSPxSTAT register indicates the various Status conditions. 27.2.1 SPI Master Mode The master can initiate the data transfer at any time because it controls the SCK line. The master determines when the slave (Processor 2, Figure 27-3) is to broadcast data by the software protocol. In Master mode, the data is transmitted/received as soon as the SSPxBUF register is written to. If the SPI is only going to receive, the SDO output could be disabled (programmed as an input). The SSPSR register will continue to shift in the signal present on the SDI pin at the programmed clock rate. As each byte is received, it will be loaded into the SSPxBUF register as if a normal received byte (interrupts and Status bits appropriately set). The clock polarity is selected by appropriately programming the CKP bit and the CKE bit. This then, would give waveforms for SPI communication as shown in Figure 27-4, Figure 27-6, Figure 27-7 and Figure 27-8, where the MSB is transmitted first. In Master mode, the SPI clock rate (bit rate) is user programmable to be one of the following: * * * * * FOSC/4 (or TCY) FOSC/16 (or 4 * TCY) FOSC/64 (or 16 * TCY) Timer2 output/2 FOSC/(4 * (SSPxADD + 1)) Figure 27-4 shows the waveforms for Master mode. When the CKE bit is set, the SDO data is valid before there is a clock edge on SCK. The change of the input sample is shown based on the state of the SMP bit. The time when the SSPxBUF is loaded with the received data is shown. Important: In Master mode the clock signal output to the SCK pin is also the clock signal input to the peripheral. The pin selected for output with the RxyPPS register must also be selected as the peripheral input with the SSPxCLKPPS register. The pin that is selected using the SSPxCLKPPS register should also be made a digital I/O. This is done by clearing the corresponding ANSEL bit. (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 474 PIC18F26/45/46Q10 (MSSP) Master Synchronous Serial Port Module Figure 27-4. SPI Mode Waveform (Master Mode) Rev. 30-000014A 3/13/2017 Write to SSPxBUF SCK (CKP = 0 CKE = 0) SCK (CKP = 1 CKE = 0) 4 Clock Modes SCK (CKP = 0 CKE = 1) SCK (CKP = 1 CKE = 1) SDO (CKE = 0) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 SDO (CKE = 1) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 SDI (SMP = 0) bit 0 bit 7 Input Sample (SMP = 0) SDI (SMP = 1) bit 0 bit 7 Input Sample (SMP = 1) SSPxIF SSPSR to SSPxBUF 27.2.2 SPI Slave Mode In Slave mode, the data is transmitted and received as external clock pulses appear on SCK. When the last bit is latched, the SSPxIF Interrupt Flag bit is set. Before enabling the module in SPI Slave mode, the clock line must match the proper Idle state. The clock line can be observed by reading the SCK pin. The Idle state is determined by the CKP bit. While in Slave mode, the external clock is supplied by the external clock source on the SCK pin. This external clock must meet the minimum high and low times as specified in the electrical specifications. While in Sleep mode, the slave can transmit/receive data. The Shift register is clocked from the SCK pin input and when a byte is received, the device will generate an interrupt. If enabled, the device will wakeup from Sleep. 27.2.3 Daisy-Chain Configuration The SPI bus can sometimes be connected in a daisy-chain configuration. The first slave output is connected to the second slave input, the second slave output is connected to the third slave input, and so on. The final slave output is connected to the master input. Each slave sends out, during a second group of clock pulses, an exact copy of what was received during the first group of clock pulses. The whole (c)2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 475 PIC18F26/45/46Q10 (MSSP) Master Synchronous Serial Port Module chain acts as one large communication shift register. The daisy-chain feature only requires a single Slave Select line from the master device. The following figure shows the block diagram of a typical daisy-chain connection when operating in SPI mode. Figure 27-5. SPI Daisy-Chain Connection Rev. 30-000015A 3/31/2017 SPI Master SCK SCK SDO SDI SDI General I/O SDO SPI Slave #1 SS SCK SDI SDO SPI Slave #2 SS SCK SDI SDO SPI Slave #3 SS In a daisy-chain configuration, only the most recent byte on the bus is required by the slave. Setting the BOEN bit will enable writes to the SSPxBUF register, even if the previous byte has not been read. This allows the software to ignore data that may not apply to it. 27.2.4 Slave Select Synchronization The Slave Select can also be used to synchronize communication. The Slave Select line is held high until the master device is ready to communicate. When the Slave Select line is pulled low, the slave knows that a new transmission is starting. If the slave fails to receive the communication properly, it will be reset at the end of the transmission, when the Slave Select line returns to a high state. The slave is then ready to receive a new transmission when the Slave Select line is pulled low again. If the Slave Select line is not used, there is a risk that the slave will eventually become out of sync with the master. If the slave misses a bit, it will always be one bit off in future transmissions. Use of the Slave Select line allows the slave and master to align themselves at the beginning of each transmission. The SS pin allows a Synchronous Slave mode. The SPI must be in Slave mode with SS pin control enabled (SSPM = 0100). When the SS pin is low, transmission and reception are enabled and the SDO pin is driven. When the SS pin goes high, the SDO pin is no longer driven, even if in the middle of a transmitted byte and becomes a floating output. External pull-up/pull-down resistors may be desirable depending on the application. (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 476 PIC18F26/45/46Q10 (MSSP) Master Synchronous Serial Port Module Note: 1. When the SPI is in Slave mode with SS pin control enabled (SSPM = 0100), the SPI module will reset if the SS pin is set to VDD. 2. When the SPI is used in Slave mode with CKE set; the user must enable SS pin control. 3. While operated in SPI Slave mode the SMP bit must remain clear. When the SPI module resets, the bit counter is forced to `0'. This can be done by either forcing the SS pin to a high level or clearing the SSPEN bit. Figure 27-6. Slave Select Synchronous Waveform Rev. 30-000016A 4/10/2017 SS SCK (CKP = 0 CKE = 0) SCK (CKP = 1 CKE = 0) Write to SSPxBUF Shift register SSPSR and bit count are reset SSPxBUF to SSPSR SDO bit 7 bit 6 bit 7 SDI bit 6 bit 0 bit 0 bit 7 bit 7 Input Sample SSPxIF Interrupt Flag SSPSR to SSPxBUF (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 477 PIC18F26/45/46Q10 (MSSP) Master Synchronous Serial Port Module Figure 27-7. SPI Mode Waveform (Slave Mode with CKE = 0) Rev. 30-000017A 4/3/2017 SS Optional SCK (CKP = 0 CKE = 0) SCK (CKP = 1 CKE = 0) Write to SSPxBUF Valid SDO bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 SDI bit 0 bit 7 Input Sample SSPxIF Interrupt Flag SSPSR to SSPxBUF Write Collision detection active Figure 27-8. SPI Mode Waveform (Slave Mode with CKE = 1) Rev. 30-000018A 4/1/2017 SS Not Optional SCK (CKP = 0 CKE = 1) SCK (CKP = 1 CKE = 1) Write to SSPxBUF Valid SDO bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 SDI bit 0 bit 7 Input Sample SSPxIF Interrupt Flag SSPSR to SSPxBUF Write Collision detection active (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 478 PIC18F26/45/46Q10 (MSSP) Master Synchronous Serial Port Module 27.2.5 SPI Operation in Sleep Mode In SPI Master mode, module clocks may be operating at a different speed than when in Full-Power mode; in the case of the Sleep mode, all clocks are halted. Special care must be taken by the user when the MSSP clock is much faster than the system clock. In Slave mode, when MSSP interrupts are enabled, after the master completes sending data, an MSSP interrupt will wake the controller from Sleep. If an exit from Sleep mode is not desired, MSSP interrupts should be disabled. In SPI Master mode, when the Sleep mode is selected, all module clocks are halted and the transmission/reception will remain in that state until the device wakes. After the device returns to Run mode, the module will resume transmitting and receiving data. In SPI Slave mode, the SPI Transmit/Receive Shift register operates asynchronously to the device. This allows the device to be placed in Sleep mode and data to be shifted into the SPI Transmit/Receive Shift register. When all eight bits have been received, the MSSP interrupt flag bit will be set and if enabled, will wake the device. 27.3 I2C Mode Overview The Inter-Integrated Circuit (I2C) bus is a multi-master serial data communication bus. Devices communicate in a master/slave environment where the master devices initiate the communication. A slave device is controlled through addressing. The following two diagrams show block diagrams of the I2C Master and Slave modes, respectively. (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 479 PIC18F26/45/46Q10 (MSSP) Master Synchronous Serial Port Module Figure 27-9. MSSP Block Diagram (I2C Master mode) Rev. 30-000019A 4/3/2017 Internal data bus SSPxDATPPS(1) Read [SSPM<3:0>] Write SDA SDA in SSPxBUF Baud Rate Generator (SSPxADD) Shift Clock RxyPPS(1) SCL PPS Receive Enable (RCEN) SSPxCLKPPS(2) MSb Clock Cntl SSPSR PPS LSb Start bit, Stop bit, Acknowledge Generate (SSPxCON2) Clock arbitrate/BCOL detect (Hold off clock source) PPS PPS RxyPPS(2) SCL in Bus Collision Start bit detect, Stop bit detect Write collision detect Clock arbitration State counter for end of XMIT/RCV Address Match detect Set/Reset: S, P, SSPxSTAT, WCOL, SSPOV Reset SEN, PEN (SSPxCON2) Set SSP1IF, BCL1IF Note 1: SDA pin selections must be the same for input and output 2: SCL pin selections must be the same for input and output (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 480 PIC18F26/45/46Q10 (MSSP) Master Synchronous Serial Port Module Figure 27-10. MSSP Block Diagram (I2C Slave mode) Rev. 30-000020A 4/3/2017 Internal Data Bus Read Write SSPxCLKPPS(2) SCL SSPxBUF Reg PPS PPS Shift Clock Clock Stretching SSPSR Reg LSb MSb RxyPPS(2) SSPxMSK Reg (1) SSPxDATPPS SDA Addr Match Match Detect PPS SSPxADD Reg PPS Start and Stop bit Detect RxyPPS(1) Set, Reset S, P bits (SSPxSTAT Reg) Note 1: SDA pin selections must be the same for input and output 2: SCL pin selections must be the same for input and output The I2C bus specifies two signal connections: * Serial Clock (SCL) * Serial Data (SDA) Both the SCL and SDA connections are bidirectional open-drain lines, each requiring pull-up resistors for the supply voltage. Pulling the line to ground is considered a logical zero and letting the line float is considered a logical one. The following diagram shows a typical connection between two processors configured as master and slave devices. Figure 27-11. I2C Master/ Slave Connection Rev. 30-000021A 4/3/2017 VDD SCL SCL VDD Master Slave SDA SDA The I2C bus can operate with one or more master devices and one or more slave devices. There are four potential modes of operation for a given device: * Master Transmit mode (master is transmitting data to a slave) (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 481 PIC18F26/45/46Q10 (MSSP) Master Synchronous Serial Port Module * Master Receive mode (master is receiving data from a slave) * Slave Transmit mode (slave is transmitting data to a master) * Slave Receive mode (slave is receiving data from the master) To begin communication, a master device starts out in Master Transmit mode. The master device sends out a Start bit followed by the address byte of the slave it intends to communicate with. This is followed by a single Read/Write bit, which determines whether the master intends to transmit to or receive data from the slave device. If the requested slave exists on the bus, it will respond with an Acknowledge bit, otherwise known as an ACK. The master then continues in either Transmit mode or Receive mode and the slave continues in the complement, either in Receive mode or Transmit mode, respectively. A Start bit is indicated by a high-to-low transition of the SDA line while the SCL line is held high. Address and data bytes are sent out, Most Significant bit (MSb) first. The Read/Write bit is sent out as a logical one when the master intends to read data from the slave, and is sent out as a logical zero when it intends to write data to the slave. The Acknowledge bit (ACK) is an active-low signal, which holds the SDA line low to indicate to the transmitter that the slave device has received the transmitted data and is ready to receive more. The transition of a data bit is always performed while the SCL line is held low. Transitions that occur while the SCL line is held high are used to indicate Start and Stop bits. If the master intends to write to the slave, then it repeatedly sends out a byte of data, with the slave responding after each byte with an ACK bit. In this example, the master device is in Master Transmit mode and the slave is in Slave Receive mode. If the master intends to read from the slave, then it repeatedly receives a byte of data from the slave, and responds after each byte with an ACK bit. In this example, the master device is in Master Receive mode and the slave is Slave Transmit mode. On the last byte of data communicated, the master device may end the transmission by sending a Stop bit. If the master device is in Receive mode, it sends the Stop bit in place of the last ACK bit. A Stop bit is indicated by a low-to-high transition of the SDA line while the SCL line is held high. In some cases, the master may want to maintain control of the bus and re-initiate another transmission. If so, the master device may send another Start bit in place of the Stop bit or last ACK bit when it is in Receive mode. The I2C bus specifies three message protocols: * Single message where a master writes data to a slave. * Single message where a master reads data from a slave. * Combined message where a master initiates a minimum of two writes, or two reads, or a combination of writes and reads, to one or more slaves. When one device is transmitting a logical one, or letting the line float, and a second device is transmitting a logical zero, or holding the line low, the first device can detect that the line is not a logical one. This detection, when used on the SCL line, is called clock stretching. Clock stretching gives slave devices a mechanism to control the flow of data. When this detection is used on the SDA line, it is called arbitration. Arbitration ensures that there is only one master device communicating at any single time. (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 482 PIC18F26/45/46Q10 (MSSP) Master Synchronous Serial Port Module 27.3.1 Register Definitions: I2C Mode The MSSPx module has seven registers for I2C operation. These are: * * * * * * * * MSSP Status register (SSPxSTAT) MSSP Control register 1 (SSPxCON1) MSSP Control register 2 (SSPxCON2) MSSP Control register 3 (SSPxCON3) Serial Receive/Transmit Buffer register (SSPxBUF) MSSP Address register (SSPxADD) I2C Slave Address Mask register (SSPxMSK) MSSP Shift register (SSPSR) - not directly accessible SSPxCON1, SSPxCON2, SSPxCON3 and SSPxSTAT are the Control and STATUS registers in I2C mode operation. The SSPxCON1, SSPxCON2, and SSPxCON3 registers are readable and writable. The lower six bits of the SSPxSTAT are read-only. The upper two bits of the SSPxSTAT are read/write. SSPSR is the Shift register used for shifting data in or out. SSPxBUF is the buffer register to which data bytes are written to or read from. SSPxADD contains the slave device address when the MSSP is configured in I2C Slave mode. When the MSSP is configured in Master mode, the lower seven bits of SSPxADD act as the Baud Rate Generator reload value. SSPxMSK holds the slave address mask value when the module is configured for 7-Bit Address Masking mode. While it is a separate register, it shares the same SFR address as SSPxADD; it is only accessible when the SSPM<3:0> bits are specifically set to permit access. In receive operations, SSPSR and SSPxBUF together, create a double-buffered receiver. When SSPSR receives a complete byte, it is transferred to SSPxBUF and the SSPxIF interrupt is set. During transmission, the SSPxBUF is not double-buffered. A write to SSPxBUF will write to both SSPxBUF and SSPSR. 27.4 I2C Mode Operation All MSSP I2C communication is byte oriented and shifted out MSb first. Six SFR registers and two (R) interrupt flags interface the module with the PIC microcontroller and user software. Two pins, SDA and SCL, are exercised by the module to communicate with other external I2C devices. 27.4.1 Clock Stretching When a slave device has not completed processing data, it can delay the transfer of more data through the process of clock stretching. An addressed slave device may hold the SCL clock line low after receiving or sending a bit, indicating that it is not yet ready to continue. The master that is communicating with the slave will attempt to raise the SCL line in order to transfer the next bit, but will detect that the clock line has not yet been released. Because the SCL connection is open-drain, the slave has the ability to hold that line low until it is ready to continue communicating. Clock stretching allows receivers that cannot keep up with a transmitter to control the flow of incoming data. 27.4.2 Arbitration Each master device must monitor the bus for Start and Stop bits. If the device detects that the bus is busy, it cannot begin a new message until the bus returns to an Idle state. However, two master devices may try to initiate a transmission on or about the same time. When this occurs, the process of arbitration begins. Each transmitter checks the level of the SDA data line and (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 483 PIC18F26/45/46Q10 (MSSP) Master Synchronous Serial Port Module compares it to the level that it expects to find. The first transmitter to observe that the two levels do not match, loses arbitration, and must stop transmitting on the SDA line. For example, if one transmitter holds the SDA line to a logical one (lets it float) and a second transmitter holds it to a logical zero (pulls it low), the result is that the SDA line will be low. The first transmitter then observes that the level of the line is different than expected and concludes that another transmitter is communicating. The first transmitter to notice this difference is the one that loses arbitration and must stop driving the SDA line. If this transmitter is also a master device, it also must stop driving the SCL line. It then can monitor the lines for a Stop condition before trying to reissue its transmission. In the meantime, the other device that has not noticed any difference between the expected and actual levels on the SDA line continues with its original transmission. It can do so without any complications, because so far, the transmission appears exactly as expected with no other transmitter disturbing the message. Slave Transmit mode can also be arbitrated, when a master addresses multiple slaves, but this is less common. If two master devices are sending a message to two different slave devices at the address stage, the master sending the lower slave address always wins arbitration. When two master devices send messages to the same slave address, and addresses can sometimes refer to multiple slaves, the arbitration process must continue into the data stage. Arbitration usually occurs very rarely, but it is a necessary process for proper multi-master support. 27.4.3 Byte Format All communication in I2C is done in 9-bit segments. A byte is sent from a master to a slave or vice versa, followed by an Acknowledge bit sent back. After the eighth falling edge of the SCL line, the device outputting data on the SDA changes that pin to an input and reads in an acknowledge value on the next clock pulse. The clock signal, SCL, is provided by the master. Data is valid to change while the SCL signal is low, and sampled on the rising edge of the clock. Changes on the SDA line while the SCL line is high define special conditions on the bus, explained below. 27.4.4 Definition of I2C Terminology There is language and terminology in the description of I2C communication that have definitions specific to I2C. That word usage is defined below and may be used in the rest of this document without explanation. This table was adapted from the Philips I2C specification. TERM Description Transmitter The device that shifts data out onto the bus. Receiver The device that shifts data in from the bus. Master The device that initiates a transfer, generates clock signals and terminates a transfer. Slave The device addressed by the master. Multi-master A bus with more than one device that can initiate data transfers. Arbitration Procedure to ensure that only one master at a time controls the bus. Winning arbitration ensures that the message is not corrupted. (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 484 PIC18F26/45/46Q10 (MSSP) Master Synchronous Serial Port Module ...........continued TERM Description Synchronization Procedure to synchronize the clocks of two or more devices on the bus. Idle No master is controlling the bus, and both SDA and SCL lines are high. Active Any time one or more master devices are controlling the bus. Addressed Slave Slave device that has received a matching address and is actively being clocked by a master. Matching Address Address byte that is clocked into a slave that matches the value stored in SSPxADD. 27.4.5 Write Request Slave receives a matching address with R/W bit clear, and is ready to clock in data. Read Request Master sends an address byte with the R/W bit set, indicating that it wishes to clock data out of the Slave. This data is the next and all following bytes until a Restart or Stop. Clock Stretching When a device on the bus hold SCL low to stall communication. Bus Collision Any time the SDA line is sampled low by the module while it is outputting and expected high state. SDA and SCL Pins Selection of any I2C mode with the SSPEN bit set, forces the SCL and SDA pins to be open-drain. These pins should be set by the user to inputs by setting the appropriate TRIS bits. Note: 1. SDA is tied to output zero when an I2C mode is enabled. 2. Any device pin can be selected for SDA and SCL functions with the PPS peripheral. These functions are bidirectional. The SDA input is selected with the SSPxDATPPS registers. The SCL input is selected with the SSPxCLKPPS registers. Outputs are selected with the RxyPPS registers. It is the user's responsibility to make the selections so that both the input and the output for each function is on the same pin. 27.4.6 SDA Hold Time The hold time of the SDA pin is selected by the SDAHT bit. Hold time is the time SDA is held valid after the falling edge of SCL. Setting the SDAHT bit selects a longer 300 ns minimum hold time and may help on buses with large capacitance. I2C Bus Terms 27.4.7 Start Condition The I2C specification defines a Start condition as a transition of SDA from a high to a low state while SCL line is high. A Start condition is always generated by the master and signifies the transition of the bus from an Idle to an Active state. Figure 27-12 shows wave forms for Start and Stop conditions. A bus collision can occur on a Start condition if the module samples the SDA line low before asserting it low. This does not conform to the I2C Specification that states no bus collision can occur on a Start. 27.4.8 Stop Condition A Stop condition is a transition of the SDA line from low-to-high state while the SCL line is high. (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 485 PIC18F26/45/46Q10 (MSSP) Master Synchronous Serial Port Module Important: At least one SCL low time must appear before a Stop is valid, therefore, if the SDA line goes low then high again while the SCL line stays high, only the Start condition is detected. Figure 27-12. I2C Start and Stop Conditions Rev. 30-000022A 4/3/2017 SDA SCL S Start Condition 27.4.9 P Change of Change of Data Allowed Data Allowed Stop Condition Restart Condition A Restart is valid any time that a Stop would be valid. A master can issue a Restart if it wishes to hold the bus after terminating the current transfer. A Restart has the same effect on the slave that a Start would, resetting all slave logic and preparing it to clock in an address. The master may want to address the same or another slave. Figure 27-13 shows the wave form for a Restart condition. In 10-bit Addressing Slave mode a Restart is required for the master to clock data out of the addressed slave. Once a slave has been fully addressed, matching both high and low address bytes, the master can issue a Restart and the high address byte with the R/W bit set. The slave logic will then hold the clock and prepare to clock out data. After a full match with R/W clear in 10-bit mode, a prior match flag is set and maintained until a Stop condition, a high address with R/W clear, or high address match fails. Figure 27-13. I2C Restart Condition Rev. 30-000023A 4/3/2017 Sr Change of Change of Data Allowed Restart Condition Data Allowed 27.4.10 Start/Stop Condition Interrupt Masking The SCIE and PCIE bits can enable the generation of an interrupt in Slave modes that do not typically support this function. These bits will have no effect in Slave modes where interrupt on Start and Stop detect are already enabled. (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 486 PIC18F26/45/46Q10 (MSSP) Master Synchronous Serial Port Module 27.4.11 Acknowledge Sequence The ninth SCL pulse for any transferred byte in I2C is dedicated as an Acknowledge. It allows receiving devices to respond back to the transmitter by pulling the SDA line low. The transmitter must release control of the line during this time to shift in the response. The Acknowledge (ACK) is an active-low signal, pulling the SDA line low indicates to the transmitter that the device has received the transmitted data and is ready to receive more. The result of an ACK is placed in the ACKSTAT bit. Slave software, when the AHEN and DHEN bits are set, allow the user to set the ACK value sent back to the transmitter. The ACKDT bit is set/cleared to determine the response. Slave hardware will generate an ACK response if both the AHEN and DHEN bits are clear. However, tf the BF bit or the SSPOV bit are set when a byte is received then the ACK will not be sent by the slave. When the module is addressed, after the eighth falling edge of SCL on the bus, the ACKTIM bit is set. The ACKTIM bit indicates the acknowledge time of the active bus. The ACKTIM Status bit is only active when either the AHEN bit or DHEN bit is enabled. 27.5 I2C Slave Mode Operation The MSSP Slave mode operates in one of four modes selected by the SSPM bits. The modes can be divided into 7-bit and 10-bit Addressing mode. 10-bit Addressing modes operate the same as 7-bit with some additional overhead for handling the larger addresses. Modes with Start and Stop bit interrupts operate the same as the other modes with SSPxIF additionally getting set upon detection of a Start, Restart, or Stop condition. 27.5.1 Slave Mode Addresses The SSPxADD register contains the Slave mode address. The first byte received after a Start or Restart condition is compared against the value stored in this register. If the byte matches, the value is loaded into the SSPxBUF register and an interrupt is generated. If the value does not match, the module goes idle and no indication is given to the software that anything happened. The SSPxMSK register affects the address matching process. See 27.5.9 SSP Mask Register for more information. 27.5.1.1 I2C Slave 7-bit Addressing Mode In 7-bit Addressing mode, the LSb of the received data byte is ignored when determining if there is an address match. 27.5.1.2 I2C Slave 10-bit Addressing Mode In 10-bit Addressing mode, the first received byte is compared to the binary value of `1 1 1 1 0 A9 A8 0'. A9 and A8 are the two MSb's of the 10-bit address and stored in bits 2 and 1 of the SSPxADD register. After the acknowledge of the high byte the UA bit is set and SCL is held low until the user updates SSPxADD with the low address. The low address byte is clocked in and all eight bits are compared to the low address value in SSPxADD. Even if there is not an address match; SSPxIF and UA are set, and SCL is held low until SSPxADD is updated to receive a high byte again. When SSPxADD is updated the UA bit is cleared. This ensures the module is ready to receive the high address byte on the next communication. A high and low address match as a write request is required at the start of all 10-bit addressing communication. A transmission can be initiated by issuing a Restart once the slave is addressed, and clocking in the high address with the R/W bit set. The slave hardware will then acknowledge the read (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 487 PIC18F26/45/46Q10 (MSSP) Master Synchronous Serial Port Module request and prepare to clock out data. This is only valid for a slave after it has received a complete high and low address byte match. 27.5.2 Slave Reception When the R/W bit of a matching received address byte is clear, the R/W bit is cleared. The received address is loaded into the SSPxBUF register and acknowledged. When the overflow condition exists for a received address, then Not Acknowledge (NACK) is given. An overflow condition is defined as either bit BF is set, or bit SSPOV is set. The BOEN bit modifies this operation. For more information see SSPxCON3. An MSSP interrupt is generated for each transferred data byte. Flag bit, SSPxIF, must be cleared by software. When the SEN bit is set, SCL will be held low (clock stretch) following each received byte. The clock must be released by setting the CKP bit, except sometimes in 10-bit mode. See 27.5.6.2 10-bit Addressing Mode for more detail. 27.5.2.1 7-bit Addressing Reception This section describes a standard sequence of events for the MSSP module configured as an I2C slave in 7-bit Addressing mode. Figure 27-14 and Figure 27-15 is used as a visual reference for this description. This is a step by step process of what typically must be done to accomplish I2C communication. 1. 2. 3. 4. Start bit detected. S bit is set; SSPxIF is set if interrupt on Start detect is enabled. Matching address with R/W bit clear is received. The slave pulls SDA low sending an ACK to the master, and sets SSPxIF bit. 5. 6. 7. Software clears the SSPxIF bit. Software reads received address from SSPxBUF clearing the BF flag. If SEN = 1; Slave software sets CKP bit to release the SCL line. 8. 9. 10. 11. 12. 13. The master clocks out a data byte. Slave drives SDA low sending an ACK to the master, and sets SSPxIF bit. Software clears SSPxIF. Software reads the received byte from SSPxBUF clearing BF. Steps 8-12 are repeated for all received bytes from the master. Master sends Stop condition, setting P bit, and the bus goes idle. 27.5.2.2 7-bit Reception with AHEN and DHEN Slave device reception with AHEN and DHEN set operate the same as without these options with extra interrupts and clock stretching added after the eighth falling edge of SCL. These additional interrupts allow the slave software to decide whether it wants to ACK the receive address or data byte, rather than the hardware. This functionality adds support for PMBusTM that was not present on previous versions of this module. This list describes the steps that need to be taken by slave software to use these options for I2C communication. Figure 27-16 displays a module using both address and data holding. Figure 27-17 includes the operation with the SEN bit of the SSPxCON2 register set. 1. 2. S bit is set; SSPxIF is set if interrupt on Start detect is enabled. Matching address with R/W bit clear is clocked in. SSPxIF is set and CKP cleared after the eighth falling edge of SCL. (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 488 PIC18F26/45/46Q10 (MSSP) Master Synchronous Serial Port Module 3. 4. 5. 6. 7. 8. Slave clears the SSPxIF. Slave can look at the ACKTIM bit to determine if the SSPxIF was after or before the ACK. Slave reads the address value from SSPxBUF, clearing the BF flag. Slave sets ACK value clocked out to the master by setting ACKDT. Slave releases the clock by setting CKP. SSPxIF is set after an ACK, not after a NACK. 9. If SEN = 1, the slave hardware will stretch the clock after the ACK. 10. Slave clears SSPxIF. Important: SSPxIF is still set after the ninth falling edge of SCL even if there is no clock stretching and BF has been cleared. Only if NACK is sent to master is SSPxIF not set 11. 12. 13. 14. 15. SSPxIF set and CKP cleared after eighth falling edge of SCL for a received data byte. Slave looks at ACKTIM bit to determine the source of the interrupt. Slave reads the received data from SSPxBUF clearing BF. Steps 7-14 are the same for each received data byte. Communication is ended by either the slave sending an ACK = 1, or the master sending a Stop condition. If a Stop is sent and Interrupt on Stop Detect is disabled, the slave will only know by polling the P bit. (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 489 (c) 2019 Microchip Technology Inc. Figure 27-14. I2C Slave, 7-bit Address, Reception (SEN = 0, AHEN = 0, DHEN = 0) rotatethispage90 Rev. 30-000024A 4/10/2017 Bus Master sends Stop condition From Slave to Master Receiving Address SDA SCL S Receiving Data A7 A6 A5 A4 A3 A2 A1 1 2 3 4 5 6 7 ACK 8 9 Receiving Data D7 D6 D5 D4 D3 D2 D1 1 2 3 4 5 6 7 D0 ACK D7 8 9 1 ACK = 1 D6 D5 D4 D3 D2 D1 D0 2 3 4 5 6 7 8 9 P Cleared by software Cleared by software BF SSPxBUF is read SSPOV First byte of data is available in SSPxBUF SSPOV set because SSPxBUF is still full. ACK is not sent. SSPxIF set on 9th falling edge of SCL PIC18F26/45/46Q10 DS40001996C-page 490 (MSSP) Master Synchronous Serial Port Module Datasheet Preliminary SSPxIF (c) 2019 Microchip Technology Inc. Figure 27-15. I2C Slave, 7-bit Address, Reception (SEN = 1, AHEN = 0, DHEN = 0) rotatethispage90 Rev. 30-000025A 4/3/2017 Bus Master sends Stop condition Receive Address SDA SCL S Receive Data A7 A6 A5 A4 A3 A2 A1 1 2 3 4 5 6 7 R/W=0 ACK 8 9 SEN Receive Data D7 D6 D5 D4 D3 D2 D1 D0 ACK 1 2 3 4 5 6 7 8 9 SEN ACK D7 D6 D5 D4 D3 D2 D1 D0 1 2 3 4 5 6 7 8 9 P Clock is held low until CKP is set to `1' SSPxIF BF SSPxBUF is read Cleared by software SSPxIF set on 9th falling edge of SCL First byte of dat a is avai labl e in SSPx BUF SSPOV SSPOV set because SSPxBUF is still full. ACK is not sent. CKP is written to `1' in software, releasing SCL CKP is written to `1' in software, releasing SCL SCL is not held low because ACK= 1 DS40001996C-page 491 PIC18F26/45/46Q10 CKP (MSSP) Master Synchronous Serial Port Module Datasheet Preliminary Cleared by software (c) 2019 Microchip Technology Inc. Figure 27-16. I2C Slave, 7-bit Address, Reception (SEN = 0, AHEN = 1, DHEN = 1) rotatethispage90 Rev. 30-000026A 4/3/2017 Master sends Stop condition Master Releases SDA to slave for ACK sequence Receiving Address SDA Receiving Data ACK D7 D6 D5 D4 D3 D2 D1 D0 A7 A6 A5 A4 A3 A2 A1 Received Data ACK ACK=1 D7 D6 D5 D4 D3 D2 D1 D0 SCL S 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 P SSPxIF If AHEN = 1: SSPxIF is set ACKDT Address is read from SSBUF Data is read from SSPxBUF Slave software clears ACKDT to CKP Slave software sets ACKDT to not ACK ACK the received byte When AHEN=1: CKP is cleared by hardware and SCL is stretched No interrupt after not ACK from Slave Cleared by software When DHEN=1: CKP is cleared by hardware on 8th falling edge of SCL CKP set by software, SCL is released ACKTIM set by hardware on 8th falling edge of SCL DS40001996C-page 492 S P ACKTIM cleared by hardware in 9th rising edge of SCL ACKTIM set by hardware on 8th falling edge of SCL PIC18F26/45/46Q10 ACKTIM (MSSP) Master Synchronous Serial Port Module Datasheet Preliminary BF SSPxIF is set on 9th falling edge of SCL, after ACK (c) 2019 Microchip Technology Inc. Figure 27-17. I2C Slave, 7-bit Address, Reception (SEN = 1, AHEN = 1, DHEN = 1) rotatethispage90 Rev. 30-000027A 4/3/2017 R/W = 0 Receiving Address SDA ACK A7 A6 A5 A4 A3 A2 A1 SCL S 1 2 3 4 5 6 7 Master sends Stop condition Master releases SDA to slave for ACK sequence 8 9 Receive Data 1 2 3 4 5 6 7 ACK Receive Data D7 D6 D5 D4 D3 D2 D1 D0 8 ACK 9 D7 D6 D5 D4 D3 D2 D1 D0 1 2 3 4 5 6 7 8 9 P SSPxIF Datasheet Preliminary BF Received address is loaded into SSPxBUF Received data is available on SSPxBUF ACKDT Slave software clears ACKDT to ACK the received byte SSPxBUF can be read any time before next byte is loaded Slave sends not ACK CKP When AHEN = 1; on the 8th falling edge of SCL of an address byte, CKP is cleared When DHEN = 1; on the 8th falling edge of SCL of a received data byte, CKP is cleared ACKTIM is set by hardware on 8th falling edge of SCL DS40001996C-page 493 S P ACKTIM is cleared by hardware on 9th rising edge of SCL CKP is not cleared if not ACK PIC18F26/45/46Q10 ACKTIM Set by software, release SCL (MSSP) Master Synchronous Serial Port Module No interrupt after if not ACK from Slave Cleared by software PIC18F26/45/46Q10 (MSSP) Master Synchronous Serial Port Module 27.5.3 Slave Transmission When the R/W bit of the incoming address byte is set and an address match occurs, the R/W bit is set. The received address is loaded into the SSPxBUF register, and an ACK pulse is sent by the slave on the ninth bit. Following the ACK, slave hardware clears the CKP bit and the SCL pin is held low (see 27.5.6 Clock Stretchingfor more detail). By stretching the clock, the master will be unable to assert another clock pulse until the slave is done preparing the transmit data. The transmit data must be loaded into the SSPxBUF register, which also loads the SSPSR register. Then the SCL pin should be released by setting the CKP bit. The eight data bits are shifted out on the falling edge of the SCL input. This ensures that the SDA signal is valid during the SCL high time. The ACK pulse from the master receiver is latched on the rising edge of the ninth SCL input pulse. This ACK value is copied to the ACKSTAT bit. If ACKSTAT is set (not ACK), then the data transfer is complete. In this case, when the not ACK is latched by the slave, the slave goes idle and waits for another occurrence of the Start bit. If the SDA line was low (ACK), the next transmit data must be loaded into the SSPxBUF register. Again, the SCL pin must be released by setting bit CKP. An MSSP interrupt is generated for each data transfer byte. The SSPxIF bit must be cleared by software and the SSPxSTAT register is used to determine the status of the byte. The SSPxIF bit is set on the falling edge of the ninth clock pulse. 27.5.3.1 Slave Mode Bus Collision A slave receives a read request and begins shifting data out on the SDA line. If a bus collision is detected and the SBCDE bit is set, the BCLxIF bit of the PIRx register is set. Once a bus collision is detected, the slave goes idle and waits to be addressed again. User software can use the BCLxIF bit to handle a slave bus collision. 27.5.3.2 7-bit Transmission A master device can transmit a read request to a slave, and then clock data out of the slave. The list below outlines what software for a slave will need to do to accomplish a standard transmission. Figure 27-18 can be used as a reference to this list. 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. Master sends a Start condition on SDA and SCL. S bit is set; SSPxIF is set if interrupt on Start detect is enabled. Matching address with R/W bit set is received by the Slave setting SSPxIF bit. Slave hardware generates an ACK and sets SSPxIF. SSPxIF bit is cleared by user. Software reads the received address from SSPxBUF, clearing BF. R/W is set so CKP was automatically cleared after the ACK. The slave software loads the transmit data into SSPxBUF. CKP bit is set releasing SCL, allowing the master to clock the data out of the slave. SSPxIF is set after the ACK response from the master is loaded into the ACKSTAT register. SSPxIF bit is cleared. The slave software checks the ACKSTAT bit to see if the master wants to clock out more data. (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 494 PIC18F26/45/46Q10 (MSSP) Master Synchronous Serial Port Module Important: 1. If the master ACKs then the clock will be stretched. 2. ACKSTAT is the only bit updated on the rising edge of the ninth SCL clock instead of the falling edge. 13. Steps 9-13 are repeated for each transmitted byte. 14. If the master sends a not ACK; the clock is not held, but SSPxIF is still set. 15. The master sends a Restart condition or a Stop. 16. The slave is no longer addressed. (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 495 (c) 2019 Microchip Technology Inc. Figure 27-18. I2C Slave, 7-bit Address, Transmission (AHEN = 0) rotatethispage90 Rev. 30-000028A 4/3/2017 Master sends Stop condition Receiving Address SDA SCL S R/W = 1 Automatic ACK D7 D6 D5 D4 D3 D2 D1 D0 ACK D7 D6 D5 D4 D3 D2 D1 D0 1 8 1 1 2 3 4 5 6 7 9 Transmitting Data 2 3 4 5 6 Automatic ACK A7 A6 A5 A4 A3 A2 A1 7 8 9 Transmitting Data 2 3 4 5 6 7 8 9 P SSPxIF Cleared by software BF Received address is read from SSPxBUF Data to transmit is loaded into SSPxBUF BF is automatically cleared after 8th falling edge of SCL When R/W is set SCL is always held low after 9th SCL falling edge Set by software CKP is not held for not ACK ACKSTAT Masters not ACK is copied to ACKSTAT R/W D/A Indicates an address has been received S DS40001996C-page 496 P PIC18F26/45/46Q10 R/W is copied from the matching address byte (MSSP) Master Synchronous Serial Port Module Datasheet Preliminary CKP PIC18F26/45/46Q10 (MSSP) Master Synchronous Serial Port Module 27.5.3.3 7-bit Transmission with Address Hold Enabled Setting the AHEN bit enables additional clock stretching and interrupt generation after the eighth falling edge of a received matching address. Once a matching address has been clocked in, CKP is cleared and the SSPxIF interrupt is set. Figure 27-19 displays a standard waveform of a 7-bit address slave transmission with AHEN enabled. 1. 2. 3. Bus starts Idle. Master sends Start condition; the S bit is set; SSPxIF is set if interrupt on Start detect is enabled. Master sends matching address with R/W bit set. After the eighth falling edge of the SCL line the CKP bit is cleared and SSPxIF interrupt is generated. 4. Slave software clears SSPxIF. 5. Slave software reads the ACKTIM, R/W and D/A bits to determine the source of the interrupt. 6. Slave reads the address value from the SSPxBUF register clearing the BF bit. 7. Slave software decides from this information if it wishes to ACK or not ACK and sets the ACKDT bit accordingly. 8. Slave sets the CKP bit releasing SCL. 9. Master clocks in the ACK value from the slave. 10. Slave hardware automatically clears the CKP bit and sets SSPxIF after the ACK if the R/W bit is set. 11. Slave software clears SSPxIF. 12. Slave loads value to transmit to the master into SSPxBUF setting the BF bit. Important: SSPxBUF cannot be loaded until after the ACK. 13. 14. 15. 16. 17. Slave sets the CKP bit releasing the clock. Master clocks out the data from the slave and sends an ACK value on the ninth SCL pulse. Slave hardware copies the ACK value into the ACKSTAT bit. Steps 10-15 are repeated for each byte transmitted to the master from the slave. If the master sends a not ACK the slave releases the bus allowing the master to send a Stop and end the communication. Important: Master must send a not ACK on the last byte to ensure that the slave releases the SCL line to receive a Stop. (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 497 (c) 2019 Microchip Technology Inc. Figure 27-19. I2C Slave, 7-bit Address, Transmission (AHEN = 1) rotatethispage90 Rev. 30-00029A 4/10/2017 Master sends Stop condition Master releases SDA to slave for ACK sequence Receiving Address SDA SCL S 1 2 3 4 5 6 Automatic R/W = 1 ACK A7 A6 A5 A4 A3 A2 A1 7 8 9 Transmitting Data Automatic D7 D6 D5 D4 D3 D2 D1 D0 ACK D7 D6 D5 D4 D3 D2 D1 D0 1 1 2 3 4 5 6 7 8 9 Transmitting Data 2 3 4 5 6 7 ACK 8 9 P SSPxIF Cleared by software BF Received address is read from SSPxBUF Data to transmit is loaded into SSPxBUF BF is automatically cleared after 8th falling edge of SCL Slave clears ACKDT to ACK address ACKSTAT Master's ACK response is copied to SSPxSTAT CKP When AHEN = 1; CKP is cleared by hardware after receiving matching address. R/W DS40001996C-page 498 D/A ACKTIM is set on 8th falling edge of SCL Set by software, releases SCL ACKTIM is cleared on 9th rising edge of SCL after not ACK PIC18F26/45/46Q10 ACKTIM CKP not cleared When R/W = 1; CKP is always cleared after ACK (MSSP) Master Synchronous Serial Port Module Datasheet Preliminary ACKDT PIC18F26/45/46Q10 (MSSP) Master Synchronous Serial Port Module 27.5.4 Slave Mode 10-bit Address Reception This section describes a standard sequence of events for the MSSP module configured as an I2C slave in 10-bit Addressing mode. Figure 27-20 is used as a visual reference for this description. This is a step-by-step process of what must be done by the slave software to accomplish I2C communication. 1. 2. 3. 4. 5. 6. 7. 8. Bus starts Idle. Master sends Start condition; S bit is set; SSPxIF is set if interrupt on Start detect is enabled. Master sends matching high address with R/W bit clear; UA bit is set. Slave sends ACK and SSPxIF is set. Software clears the SSPxIF bit. Software reads received address from SSPxBUF clearing the BF flag. Slave loads low address into SSPxADD, releasing SCL. Master sends matching low address byte to the slave; UA bit is set. Important: Updates to the SSPxADD register are not allowed until after the ACK sequence. 9. Slave sends ACK and SSPxIF is set. Important: If the low address does not match, SSPxIF and UA are still set so that the slave software can set SSPxADD back to the high address. BF is not set because there is no match. CKP is unaffected. 10. 11. 12. 13. 14. 15. 16. 17. 18. 19. 27.5.5 Slave clears SSPxIF. Slave reads the received matching address from SSPxBUF clearing BF. Slave loads high address into SSPxADD. Master clocks a data byte to the slave and clocks out the slaves ACK on the ninth SCL pulse; SSPxIF is set. If SEN bit is set, CKP is cleared by hardware and the clock is stretched. Slave clears SSPxIF. Slave reads the received byte from SSPxBUF clearing BF. If SEN is set the slave sets CKP to release the SCL. Steps 13-17 repeat for each received byte. Master sends Stop to end the transmission. 10-bit Addressing with Address or Data Hold Reception using 10-bit addressing with AHEN or DHEN set is the same as with 7-bit modes. The only difference is the need to update the SSPxADD register using the UA bit. All functionality, specifically when the CKP bit is cleared and SCL line is held low are the same. Figure 27-21 can be used as a reference of a slave in 10-bit addressing with AHEN set. Figure 27-22 shows a standard waveform for a slave transmitter in 10-bit Addressing mode. (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 499 (c) 2019 Microchip Technology Inc. Figure 27-20. I2C Slave, 10-bit Address, Reception (SEN = 1, AHEN = 0, DHEN = 0) rotatethispage90 Rev. 30-000030A 4/3/2017 Master sends Stop condition SCL S SSPxIF Receive Second Address Byte Receive First Address Byte SDA 1 1 1 1 1 2 3 4 0 A9 A8 5 6 7 ACK 8 9 A7 A6 A5 A4 A3 A2 A1 A0 ACK 1 2 3 4 5 6 7 8 9 Receive Data Receive Data D7 D6 D5 D4 D3 D2 D1 D0 ACK 1 2 3 4 5 6 7 8 9 D7 D6 D5 D4 D3 D2 D1 D0 ACK 1 2 3 4 5 6 7 8 9 P SCL is held low while CKP = 0 Set by hardware on 9th falling edge Cleared by software Receive address is read from SSPxBUF If address matches SSPxADD it is loaded into SSPxBUF UA When UA = 1; SCL is held low Data is read from SSPxBUF Software updates SSPxADD and releases SCL DS40001996C-page 500 Set by software, When SEN = 1; releasing SCL CKP is cleared after 9th falling edge of received byte PIC18F26/45/46Q10 CKP (MSSP) Master Synchronous Serial Port Module Datasheet Preliminary BF (c) 2019 Microchip Technology Inc. Figure 27-21. I2C Slave, 10-bit Address, Reception (SEN = 0, AHEN = 1, DHEN = 0) rotatethispage90 Rev. 30-000031A 4/3/2017 Receive First Address Byte SDA SCL S R/W = 0 1 1 1 1 0 A9 A8 1 2 3 4 5 6 7 8 Receive Second Address Byte ACK 9 UA Receive Data A7 A6 A5 A4 A3 A2 A1 A0 ACK 1 2 3 4 5 6 7 8 9 UA Receive Data D7 D6 D5 D4 D3 D2 D1 1 2 3 4 5 6 7 D0 ACK D7 8 9 1 D6 D5 2 SSPxIF Set by hardware on 9th falling edge Cleared by software Cleared by software SSPxBUF can be read anytime before the next received byte Received data is read from SSPxBUF ACKDT Slave software clears ACKDT to ACK the received byte UA CKP DS40001996C-page 501 If when AHEN = 1; on the 8th falling edge of SCL of an address byte, CKP is cleared ACKTIM ACKTIM is set by hardware on 8th falling edge of SCL Update of SSPxADD, clears UA and releases SCL Set CKP with software releases SCL PIC18F26/45/46Q10 Update to SSPxADD is not allowed until 9th falling edge of SCL (MSSP) Master Synchronous Serial Port Module Datasheet Preliminary BF (c) 2019 Microchip Technology Inc. Figure 27-22. I2C Slave, 10-bit Address, Transmission (SEN = 0, AHEN = 0, DHEN = 0) rotatethispage90 Rev. 30-000032A 4/3/2017 Master sends Restart event Receiving Address R/W = 0 1 1 1 1 0 A9 A8 ACK SDA SCL S 1 2 3 4 5 6 7 8 9 Master sends not ACK Receiving Second Address Byte Receive First Address Byte A7 A6 A5 A4 A3 A2 A1 A0 ACK 1 1 1 1 0 A9 A8 1 2 3 4 5 6 7 8 1 9 2 3 4 5 6 7 8 Transmitting Data Byte ACK 9 Master sends Stop condition ACK = 1 D7 D6 D5 D4 D3 D2 D1 D0 1 2 3 4 5 6 7 8 9 P Sr SSPxIF Set by hardware Cleared by software Set by hardware BF Received address is read from SSPxBUF Data to transmit is loaded into SSPxBUF UA UA indicates SSPxADD must be updated CKP After SSPxADD is updated, UA is cleared and SCL is released High address is loaded back into SSPxADD When R/W = 1; CKP is cleared on 9th falling edge of SCL ACKSTAT Set by software releases SCL Masters not ACK is copied R/W is copied from the matching address byte D/A Indicates an address has been received DS40001996C-page 502 PIC18F26/45/46Q10 R/W (MSSP) Master Synchronous Serial Port Module Datasheet Preliminary SSPxBUF loaded with received address PIC18F26/45/46Q10 (MSSP) Master Synchronous Serial Port Module 27.5.6 Clock Stretching Clock stretching occurs when a device on the bus holds the SCL line low, effectively pausing communication. The slave may stretch the clock to allow more time to handle data or prepare a response for the master device. A master device is not concerned with stretching as anytime it is active on the bus and not transferring data it is stretching. Any stretching done by a slave is invisible to the master software and handled by the hardware that generates SCL. The CKP bit is used to control stretching in software. Any time the CKP bit is cleared, the module will wait for the SCL line to go low and then hold it. Setting CKP will release SCL and allow more communication. 27.5.6.1 Normal Clock Stretching Following an ACK if the R/W bit is set, a read request, the slave hardware will clear CKP. This allows the slave time to update SSPxBUF with data to transfer to the master. If the SEN bit is set, the slave hardware will always stretch the clock after the ACK sequence. Once the slave is ready; CKP is set by software and communication resumes. Important: 1. The BF bit has no effect on whether or not the clock will be stretched. This is different than previous versions of the module that would not stretch the clock, clear CKP, if SSPxBUF was read before the ninth falling edge of SCL. 2. Previous versions of the module did not stretch the clock for a transmission if SSPxBUF was loaded before the ninth falling edge of SCL. It is now always cleared for read requests. 27.5.6.2 10-bit Addressing Mode In 10-bit Addressing mode, when the UA bit is set, the clock is always stretched. This is the only time the SCL is stretched without CKP being cleared. SCL is released immediately after a write to SSPxADD. Important: Previous versions of the module did not stretch the clock if the second address byte did not match. 27.5.6.3 Byte NACKing When the AHEN bit is set, CKP is cleared by hardware after the eighth falling edge of SCL for a received matching address byte. When the DHEN bit is set, CKP is cleared after the eighth falling edge of SCL for received data. Stretching after the eighth falling edge of SCL allows the slave to look at the received address or data and decide if it wants to ACK the received data. 27.5.7 Clock Synchronization and the CKP bit Any time the CKP bit is cleared, the module will wait for the SCL line to go low and then hold it. However, clearing the CKP bit will not assert the SCL output low until the SCL output is already sampled low. Therefore, the CKP bit will not assert the SCL line until an external I2C master device has already asserted the SCL line. The SCL output will remain low until the CKP bit is set and all other devices on the I2C bus have released SCL. This ensures that a write to the CKP bit will not violate the minimum high time requirement for SCL (see the following figure). (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 503 PIC18F26/45/46Q10 (MSSP) Master Synchronous Serial Port Module Figure 27-23. Clock Synchronization Timing Rev. 30-000033A 4/3/2017 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 SDA DX - 1 DX SCL Master device asserts clock CKP Master device releases clock WR SSPxCON1 27.5.8 General Call Address Support The addressing procedure for the I2C bus is such that the first byte after the Start condition usually determines which device will be the slave addressed by the master device. The exception is the general call address that can address all devices. When this address is used, all devices should, in theory, respond with an acknowledge. The general call address is a reserved address in the I2C protocol, defined as address 0x00. When the GCEN bit is set, the slave module will automatically ACK the reception of this address regardless of the value stored in SSPxADD. After the slave clocks in an address of all zeros with the R/W bit clear, an interrupt is generated and slave software can read SSPxBUF and respond. The following figure shows a general call reception sequence. Figure 27-24. Slave Mode General Call Address Sequence Rev. 30-000034A 4/3/2017 Address is compared to General Call Address after ACK, set interrupt R/W = 0 ACK D7 General Call Address SDA SCL S 1 2 3 4 5 6 7 8 9 1 Receiving Data ACK D6 D5 D4 D3 D2 D1 D0 2 3 4 5 6 7 8 9 SSPxIF BF (SSPxSTAT<0>) Cleared by software GCEN (SSPxCON2<7>) SSPxBUF is read '1' In 10-bit Address mode, the UA bit will not be set on the reception of the general call address. The slave will prepare to receive the second byte as data, just as it would in 7-bit mode. (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 504 PIC18F26/45/46Q10 (MSSP) Master Synchronous Serial Port Module If the AHEN bit is set, just as with any other address reception, the slave hardware will stretch the clock after the eighth falling edge of SCL. The slave must then set its ACKEN value and release the clock with communication progressing as it would normally. 27.5.9 SSP Mask Register An SSP Mask register (SSPxMSK) is available in I2C Slave mode as a mask for the value held in the SSPSR register during an address comparison operation. A zero (`0') bit in the SSPxMSK register has the effect of making the corresponding bit of the received address a "don't care". This register is reset to all `1's upon any Reset condition and, therefore, has no effect on standard SSP operation until written with a mask value. The SSP Mask register is active during: * 7-bit Address mode: address compare of A<7:1>. * 10-bit Address mode: address compare of A<7:0> only. The SSP mask has no effect during the reception of the first (high) byte of the address. 27.6 I2C Master Mode Master mode is enabled by setting and clearing the appropriate SSPM bits and setting the SSPEN bit. In Master mode, the SDA and SCK pins must be configured as inputs. The MSSP peripheral hardware will override the output driver TRIS controls when necessary to drive the pins low. Master mode of operation is supported by interrupt generation on the detection of the Start and Stop conditions. The Stop (P) and Start (S) bits are cleared from a Reset or when the MSSP module is disabled. Control of the I2C bus may be taken when the P bit is set, or the bus is Idle. In Firmware Controlled Master mode, user code conducts all I2C bus operations based on Start and Stop bit condition detection. Start and Stop condition detection is the only active circuitry in this mode. All other communication is done by the user software directly manipulating the SDA and SCL lines. The following events will cause the SSP Interrupt Flag bit, SSPxIF, to be set (SSP interrupt, if enabled): * * * * * Start condition detected Stop condition detected Data transfer byte transmitted/received Acknowledge transmitted/received Repeated Start generated Important: 1. The MSSP module, when configured in I2C Master mode, does not allow queuing of events. For instance, the user is not allowed to initiate a Start condition and immediately write the SSPxBUF register to initiate transmission before the Start condition is complete. In this case, the SSPxBUF will not be written to and the WCOL bit will be set, indicating that a write to the SSPxBUF did not occur. 2. Master mode suspends Start/Stop detection when sending the Start/Stop condition by means of the SEN/PEN control bits. The SSPxIF bit is set at the end of the Start/Stop generation when hardware clears the control bit. (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 505 PIC18F26/45/46Q10 (MSSP) Master Synchronous Serial Port Module 27.6.1 I2C Master Mode Operation The master device generates all of the serial clock pulses and the Start and Stop conditions. A transfer is ended with a Stop condition or with a Repeated Start condition. Since the Repeated Start condition is also the beginning of the next serial transfer, the I2C bus will not be released. In Master Transmitter mode, serial data is output through SDA, while SCL outputs the serial clock. The first byte transmitted contains the slave address of the receiving device (7 bits) and the R/W bit. In this case, the R/W bit will be logic `0'. Serial data is transmitted eight bits at a time. After each byte is transmitted, an Acknowledge bit is received. Start and Stop conditions are output to indicate the beginning and the end of a serial transfer. In Master Receive mode, the first byte transmitted contains the slave address of the transmitting device (7 bits) and the R/W bit. In this case, the R/W bit will be logic `1'. Thus, the first byte transmitted is a 7-bit slave address followed by a `1' to indicate the receive bit. Serial data is received via SDA, while SCL outputs the serial clock. Serial data is received eight bits at a time. After each byte is received, an Acknowledge bit is transmitted. Start and Stop conditions indicate the beginning and end of transmission. A Baud Rate Generator is used to set the clock frequency output on SCL. See 27.7 Baud Rate Generator for more detail. 27.6.2 Clock Arbitration Clock arbitration occurs when the master, during any receive, transmit or Repeated Start/Stop condition, releases the SCL pin (SCL allowed to float high). When the SCL pin is allowed to float high, the Baud Rate Generator (BRG) is suspended from counting until the SCL pin is actually sampled high. When the SCL pin is sampled high, the Baud Rate Generator is reloaded with the contents of 27.9.6 SSPxADD and begins counting. This ensures that the SCL high time will always be at least one BRG rollover count in the event that the clock is held low by an external device as shown in the following figure. Figure 27-25. Baud Rate Generator Timing with Clock Arbitration Rev. 30-000035A 4/3/2017 SDA DX - 1 DX SCL deasserted but slave holds SCL low (clock arbitration) SCL allowed to transition high SCL BRG decrements on Q2 and Q4 cycles BRG Value 03h 02h 01h 00h (hold off) 03h 02h SCL is sampled high, reload takes place and BRG starts its count BRG Reload 27.6.3 WCOL Status Flag If the user writes the SSPxBUF when a Start, Restart, Stop, Receive or Transmit sequence is in progress, the WCOL bit is set and the contents of the buffer are unchanged (the write does not occur). Any time the WCOL bit is set it indicates that an action on SSPxBUF was attempted while the module was not idle. (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 506 PIC18F26/45/46Q10 (MSSP) Master Synchronous Serial Port Module Important: Because queuing of events is not allowed, writing to the lower five bits of SSPxCON2 is disabled until the Start condition is complete. 27.6.4 I2C Master Mode Start Condition Timing To initiate a Start condition (Figure 27-26), the user sets the SEN Start Enable bit. If the SDA and SCL pins are sampled high, the Baud Rate Generator is reloaded with the contents of SSPxADD and starts its count. If SCL and SDA are both sampled high when the Baud Rate Generator times out (TBRG), the SDA pin is driven low. The action of the SDA being driven low while SCL is high is the Start condition and causes the S bit to be set. Following this, the Baud Rate Generator is reloaded with the contents of SSPxADD and resumes its count. When the Baud Rate Generator times out (TBRG), the SEN bit will be automatically cleared by hardware; the Baud Rate Generator is suspended, leaving the SDA line held low and the Start condition is complete. Important: 1. If at the beginning of the Start condition, the SDA and SCL pins are already sampled low, or if during the Start condition, the SCL line is sampled low before the SDA line is driven low, a bus collision occurs, the Bus Collision Interrupt Flag, BCLxIF, is set, the Start condition is aborted and the I2C module is reset into its Idle state. 2. The Philips I2C specification states that a bus collision cannot occur on a Start. Figure 27-26. First Start Bit Timing Rev. 30-000036A 4/3/2017 Set S bit (SSPxSTAT<3>) Write to SEN bit occurs here At completion of Start bit, hardware clears SEN bit a nd set s SSPx I F bi t SDA = 1, SCL = 1 TBRG TBRG Write to SSPxBUF occurs here SDA 1st bit 2nd bit TBRG SCL S 27.6.5 TBRG I2C Master Mode Repeated Start Condition Timing A Repeated Start condition (Figure 27-27) occurs when the RSEN bit is programmed high and the master state machine is no longer active. When the RSEN bit is set, the SCL pin is asserted low. When the SCL pin is sampled low, the Baud Rate Generator is loaded and begins counting. The SDA pin is released (brought high) for one Baud Rate Generator count (TBRG). When the Baud Rate Generator times out, if SDA is sampled high, the SCL pin will be deasserted (brought high). When SCL is sampled high, the Baud Rate Generator is reloaded and begins counting. SDA and SCL must be sampled high for one TBRG. This action is then followed by assertion of the SDA pin (SDA = 0) for one TBRG while SCL is high. SCL is asserted low. Following this, the RSEN bit will be automatically cleared and the Baud Rate Generator will not be reloaded, leaving the SDA pin held low. As soon as a Start condition is detected on (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 507 PIC18F26/45/46Q10 (MSSP) Master Synchronous Serial Port Module the SDA and SCL pins, the S bit will be set. The SSPxIF bit will not be set until the Baud Rate Generator has timed out. Important: 1. If RSEN is programmed while any other event is in progress, it will not take effect. 2. A bus collision during the Repeated Start condition occurs if: - SDA is sampled low when SCL goes from low-to-high. - SCL goes low before SDA is asserted low. This may indicate that another master is attempting to transmit a data `1'. Figure 27-27. Repeated Start Condition Waveform Rev. 30-000037A 4/10/2017 S bit set by hardware Write to SSPxCON2 occurs here SDA = 1, SCL (no change) At completion of Start bit, hardware clears the RSEN bit and sets SSPxIF SDA = 1, SCL = 1 TBRG TBRG TBRG 1st bit SDA Write to SSPxBUF occurs here TBRG SCL Sr TBRG Repeated Start 27.6.6 I2C Master Mode Transmission Transmission of a data byte, a 7-bit address or the other half of a 10-bit address is accomplished by simply writing a value to the SSPxBUF register. This action will set the Buffer Full flag bit, BF, and allow the Baud Rate Generator to begin counting and start the next transmission. Each bit of address/data will be shifted out onto the SDA pin after the falling edge of SCL is asserted. SCL is held low for one Baud Rate Generator rollover count (TBRG). Data should be valid before SCL is released high. When the SCL pin is released high, it is held that way for TBRG. The data on the SDA pin must remain stable for that duration and some hold time after the next falling edge of SCL. After the eighth bit is shifted out (the falling edge of the eighth clock), the BF flag is cleared and the master releases SDA. This allows the slave device being addressed to respond with an ACK bit during the ninth bit time if an address match occurred, or if data was received properly. The status of ACK is written into the ACKSTAT bit on the rising edge of the ninth clock. If the master receives an Acknowledge, the Acknowledge Status bit, ACKSTAT, is cleared. If not, the bit is set. After the ninth clock, the SSPxIF bit is set and the master clock (Baud Rate Generator) is suspended until the next data byte is loaded into the SSPxBUF, leaving SCL low and SDA unchanged (Figure 27-28). After the write to the SSPxBUF, each bit of the address will be shifted out on the falling edge of SCL until all seven address bits and the R/W bit are completed. On the falling edge of the eighth clock, the master will release the SDA pin, allowing the slave to respond with an Acknowledge. On the falling edge of the ninth clock, the master will sample the SDA pin to see if the address was recognized by a slave. The status of the ACK bit is loaded into the ACKSTAT Status bit of the SSPxCON2 register. Following the falling edge of the ninth clock transmission of the address, the SSPxIF is set, the BF flag is cleared and (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 508 PIC18F26/45/46Q10 (MSSP) Master Synchronous Serial Port Module the Baud Rate Generator is turned off until another write to the SSPxBUF takes place, holding SCL low and allowing SDA to float. 27.6.6.1 BF Status Flag In Transmit mode, the BF bit is set when the CPU writes to SSPxBUF and is cleared when all eight bits are shifted out. 27.6.6.2 WCOL Status Flag If the user writes the SSPxBUF when a transmit is already in progress (i.e., SSPSR is still shifting out a data byte), the WCOL bit is set and the contents of the buffer are unchanged (the write does not occur). The WCOL bit must be cleared by software before the next transmission. 27.6.6.3 ACKSTAT Status Flag In Transmit mode, the ACKSTAT bit is cleared when the slave has sent an Acknowledge (ACK = 0) and is set when the slave does not Acknowledge (ACK = 1). A slave sends an Acknowledge when it has recognized its address (including a general call), or when the slave has properly received its data. 27.6.6.4 Typical transmit sequence: 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. The user generates a Start condition by setting the SEN bit. SSPxIF is set by hardware on completion of the Start. SSPxIF is cleared by software. The MSSP module will wait the required start time before any other operation takes place. The user loads the SSPxBUF with the slave address to transmit. Address is shifted out the SDA pin until all eight bits are transmitted. Transmission begins as soon as SSPxBUF is written to. The MSSP module shifts in the ACK bit from the slave device and writes its value into the ACKSTAT bit. The MSSP module generates an interrupt at the end of the ninth clock cycle by setting the SSPxIF bit. The user loads the SSPxBUF with eight bits of data. Data is shifted out the SDA pin until all eight bits are transmitted. The MSSP module shifts in the ACK bit from the slave device and writes its value into the ACKSTAT bit. Steps 8-11 are repeated for all transmitted data bytes. The user generates a Stop or Restart condition by setting the PEN or RSEN bits. Interrupt is generated once the Stop/Restart condition is complete. (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 509 PIC18F26/45/46Q10 (MSSP) Master Synchronous Serial Port Module Figure 27-28. I2C Master Mode Waveform (Transmission, 7 or 10-bit Address) Rev. 30-000038A 4/3/2017 Write SSPxCON2<0> SEN = 1 Start condition begins From slave, clear ACKSTAT bit SSPxCON2<6> SEN = 0 A7 A6 A5 A4 A3 A2 Transmitting Data or Second Half of 10-bit Address R/W = 0 Transmit Address to Slave SDA ACKSTAT in SSPxCON2 = 1 ACK = 0 A1 ACK D7 D6 D5 D4 D3 D2 D1 D0 1 SCL held low while CPU responds to SSPxIF 2 3 4 5 6 7 8 SSPxBUF written with 7-bit address and R/W start transmit SCL 1 S 2 3 4 5 6 7 8 9 9 P SSPxIF Cleared by software service routine from SSP interrupt Cleared by software Cleared by software BF (SSPxSTAT<0>) SSPxBUF is written by software SSPxBUF written SEN After Start condition, SEN cleared by hardware PEN R/W 27.6.7 I2C Master Mode Reception Master mode reception (Figure 27-29) is enabled by programming the RCEN Receive Enable bit. Important: The MSSP module must be in an Idle state before the RCEN bit is set or the RCEN bit will be disregarded. The Baud Rate Generator begins counting and on each rollover, the state of the SCL pin changes (highto-low/low-to-high) and data is shifted into the SSPSR. After the falling edge of the eighth clock all the following events occur: * The receive enable flag is automatically cleared * The contents of the SSPSR are loaded into the SSPxBUF * The BF flag bit is set * The SSPxIF flag bit is set * The Baud Rate Generator is suspended from counting * The SCL pin is held low The MSSP is now in Idle state awaiting the next command. When the buffer is read by the CPU, the BF flag bit is automatically cleared. The user can then send an Acknowledge bit at the end of reception by setting the Acknowledge Sequence Enable, ACKEN bit. 27.6.7.1 BF Status Flag In receive operation, the BF bit is set when an address or data byte is loaded into SSPxBUF from SSPSR. It is cleared when the SSPxBUF register is read. (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 510 PIC18F26/45/46Q10 (MSSP) Master Synchronous Serial Port Module 27.6.7.2 SSPOV Status Flag In receive operation, the SSPOV bit is set when eight bits are received into the SSPSR while the BF flag bit is already set from a previous reception. 27.6.7.3 WCOL Status Flag If the user writes the SSPxBUF when a receive is already in progress (i.e., SSPSR is still shifting in a data byte), the WCOL bit is set and the contents of the buffer are unchanged (the write does not occur). 27.6.7.4 Typical Receive Sequence: 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. The user generates a Start condition by setting the SEN bit. SSPxIF is set by hardware on completion of the Start. SSPxIF is cleared by software. User writes SSPxBUF with the slave address to transmit and the R/W bit set. Address is shifted out the SDA pin until all eight bits are transmitted. Transmission begins as soon as SSPxBUF is written to. The MSSP module shifts in the ACK bit from the slave device and writes its value into the ACKSTAT bit. The MSSP module generates an interrupt at the end of the ninth clock cycle by setting the SSPxIF bit. User sets the RCEN bit and the master clocks in a byte from the slave. After the eighth falling edge of SCL, SSPxIF and BF are set. Master clears SSPxIF and reads the received byte from SSPUF which clears BF. Master sets the ACK value to be sent to slave in the ACKDT bit and initiates the ACK by setting the ACKEN bit. Master's ACK is clocked out to the slave and SSPxIF is set. User clears SSPxIF. Steps 8-13 are repeated for each received byte from the slave. Master sends a not ACK or Stop to end communication. (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 511 (c) 2019 Microchip Technology Inc. Figure 27-29. I2C Master Mode Waveform (Reception, 7-bit Address) rotatethispage90 Rev. 30-000039A 4/3/2017 Write to SSPxCON2<4> to start Acknowledge sequence SDA = ACKDT (SSPxCON2<5>) = 0 Write to SSPxCON2<0>(SEN = 1), begin Start condition SEN = 0 Write to SSPxBUF occurs here, ACK from Slave start XMIT A6 A5 A4 A3 A2 RCEN = 1, start next receive RCEN cleared automatically Transmit Address to Slave A7 SDA ACK PEN bit = 1 written here RCEN cleared automatically Receiving Data from Slave Receiving Data from Slave A1 R/W Set ACKEN, start Acknowledge sequence SDA = ACKDT = 1 ACK from Master SDA = ACKDT = 0 Master configured as a receiver by programming SSPxCON2<3> (RCEN = 1) D7 D6 D5 D4 D3 D2 D1 ACK D0 D7 D6 D5 D4 D3 D2 D1 D0 ACK Bus master terminates transfer ACK is not sent SCL S 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 Data shifted in on falling edge of CLK Set SSPxIF interrupt at end of receive Cleared by software Cleared by software BF (SSPxSTAT<0>) Cleared by software Cleared in software Last bit is shifted into SSPSR and contents are unloaded into SSPxBUF SSPOV ACKEN DS40001996C-page 512 RCEN Master configured as a receiver by programming SSPxCON2<3> (RCEN = 1) RCEN cleared automatically ACK from Master SDA = ACKDT = 0 RCEN cleared automatically Set P bit (SSPxSTAT<4>) and SSPxIF PIC18F26/45/46Q10 SSPOV is set because SSPxBUF is still full Set SSPxIF interrupt at end of Acknowledge sequence (MSSP) Master Synchronous Serial Port Module Datasheet Preliminary Cleared by software P Set SSPxIF at end of receive Set SSPxIF interrupt at end of Acknowledge sequence SSPxIF SDA = 0, SCL = 1 while CPU responds to SSPxIF 9 8 PIC18F26/45/46Q10 (MSSP) Master Synchronous Serial Port Module 27.6.8 Acknowledge Sequence Timing An Acknowledge sequence is enabled by setting the Acknowledge Sequence Enable ACKEN bit. When this bit is set, the SCL pin is pulled low and the contents of the Acknowledge data bit are presented on the SDA pin. If the user wishes to generate an Acknowledge, then the ACKDT bit should be cleared. If not, the user should set the ACKDT bit before starting an Acknowledge sequence. The Baud Rate Generator then counts for one rollover period (TBRG) and the SCL pin is deasserted (pulled high). When the SCL pin is sampled high (clock arbitration), the Baud Rate Generator counts for TBRG. The SCL pin is then pulled low. Following this, the ACKEN bit is automatically cleared, the Baud Rate Generator is turned off and the MSSP module then goes into Idle mode. Figure 27-30. Acknowledge Sequence Waveform Acknowledge sequence starts here, write to SSPxCON2 ACKEN = 1, ACKDT = 0 ACKEN automatically cleared TBRG TBRG SDA ACK D0 SCL Rev. 30-000040A 4/3/2017 8 9 SSPxIF SSPxIF set at the end of receive Cleared in software Cleared in software SSPxIF set at the end of Acknowledge sequence Note: TBRG = one Baud Rate Generator period. 27.6.8.1 Acknowledge Write Collision If the user writes the SSPxBUF when an Acknowledge sequence is in progress, then the WCOL bit is set and the contents of the buffer are unchanged (the write does not occur). 27.6.9 Stop Condition Timing A Stop bit is asserted on the SDA pin at the end of a receive/transmit by setting the Stop Sequence Enable PEN bit. At the end of a receive/transmit, the SCL line is held low after the falling edge of the ninth clock. When the PEN bit is set, the master will assert the SDA line low. When the SDA line is sampled low, the Baud Rate Generator is reloaded and counts down to `0'. When the Baud Rate Generator times out, the SCL pin will be brought high and one TBRG (Baud Rate Generator rollover count) later, the SDA pin will be deasserted. When the SDA pin is sampled high while SCL is high, the P bit is set. One TBRG later, the PEN bit is cleared and the SSPxIF bit is set. (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 513 PIC18F26/45/46Q10 (MSSP) Master Synchronous Serial Port Module Figure 27-31. Stop Condition in Receive or Transmit Mode SCL = 1 for TBRG, followed by SDA = 1 for TBRG after SDA sampled high. P bit (SSPxSTAT<4>) is set. Write to SSPxCON2, set PEN PEN bit (SSPxCON2<2>) is cleared by hardware and the SSPxIF bit is set Falling edge of 9th clock TBRG SCL SDA Rev. 30-000041A 4/3/2017 ACK P TBRG TBRG TBRG SCL brought high after TBRG SDA asserted low before rising edge of clock to setup Stop condition Note: TBRG = one Baud Rate Generator period. 27.6.9.1 Write Collision on Stop the user writes the SSPxBUF when a Stop sequence is in progress, then the WCOL bit is set and the If contents of the buffer are unchanged (the write does not occur). 27.6.10 Sleep Operation While in Sleep mode, the I2C slave module can receive addresses or data and when an address match or complete byte transfer occurs, wake the processor from Sleep (if the MSSP interrupt is enabled). 27.6.11 Effects of a Reset A Reset disables the MSSP module and terminates the current transfer. 27.6.12 Multi-Master Mode In Multi-Master mode, the interrupt generation on the detection of the Start and Stop conditions allows the determination of when the bus is free. The Stop (P) and Start (S) bits are cleared from a Reset or when the MSSP module is disabled. Control of the I2C bus may be taken when the P bit is set, or the bus is Idle, with both the S and P bits clear. When the bus is busy, enabling the SSP interrupt will generate the interrupt when the Stop condition occurs. In multi-master operation, the SDA line must be monitored for arbitration to see if the signal level is the expected output level. This check is performed by hardware with the result placed in the BCLxIF bit. The states where arbitration can be lost are: * * * * * Address Transfer Data Transfer A Start Condition A Repeated Start Condition An Acknowledge Condition 27.6.13 Multi-Master Communication, Bus Collision and Bus Arbitration Multi-Master mode support is achieved by bus arbitration. When the master outputs address/data bits onto the SDA pin, arbitration takes place when the master outputs a `1' on SDA, by letting SDA float high and another master asserts a `0'. When the SCL pin floats high, data should be stable. If the expected data on SDA is a `1' and the data sampled on the SDA pin is `0', then a bus collision has taken place. The master will set the Bus Collision Interrupt Flag, BCLxIF and reset the I2C port to its Idle state (Figure 27-32). (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 514 PIC18F26/45/46Q10 (MSSP) Master Synchronous Serial Port Module If a transmit was in progress when the bus collision occurred, the transmission is halted, the BF flag is cleared, the SDA and SCL lines are deasserted and the SSPxBUF can be written to. When the user services the bus collision Interrupt Service Routine and if the I2C bus is free, the user can resume communication by asserting a Start condition. If a Start, Repeated Start, Stop or Acknowledge condition was in progress when the bus collision occurred, the condition is aborted, the SDA and SCL lines are deasserted and the respective control bits in the SSPxCON2 register are cleared. When the user services the bus collision Interrupt Service Routine and if the I2C bus is free, the user can resume communication by asserting a Start condition. The master will continue to monitor the SDA and SCL pins. If a Stop condition occurs, the SSPxIF bit will be set. A write to the SSPxBUF will start the transmission of data at the first data bit, regardless of where the transmitter left off when the bus collision occurred. In Multi-Master mode, the interrupt generation on the detection of Start and Stop conditions allows the determination of when the bus is free. Control of the I2C bus can be taken when the P bit is set, or the bus is Idle and the S and P bits are cleared. Figure 27-32. Bus Collision Timing for Transmit and Acknowledge Rev. 30-000042A 4/3/2017 Data changes while SCL = 0 SDA line pulled low by another source SDA released by master Sample SDA. While SCL is high, data does not match what is driven by the master. Bus collision has occurred. SDA SCL Set bus collision interrupt (BCLxIF) BCLxIF 27.6.13.1 Bus Collision During a Start Condition During a Start condition, a bus collision occurs if: 1. 2. SDA or SCL are sampled low at the beginning of the Start condition (Figure 27-33). SCL is sampled low before SDA is asserted low (Figure 27-34). During a Start condition, both the SDA and the SCL pins are monitored. If the SDA pin is already low, or the SCL pin is already low, then all of the following occur: * the Start condition is aborted, * the BCLxIF flag is set and * the MSSP module is reset to its Idle state (Figure 27-33). (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 515 PIC18F26/45/46Q10 (MSSP) Master Synchronous Serial Port Module Figure 27-33. Bus Collision During Start Condition (SDA Only) Rev. 30-000043A 4/3/2017 SDA goes low before the SEN bit is set. Set BCLxIF, S bit and SSPxIF set because SDA = 0, SCL = 1. SDA SCL Set SEN, enable Start condition if SDA = 1, SCL = 1 SEN cleared automatically because of bus collision. SSPx module reset into Idle state. SEN SDA sampled low before Start condition. Set BCLxIF. S bit and SSPxIF set because SDA = 0, SCL = 1. BCLxIF SSPxIF and BCLxIF are cleared by software S SSPxIF SSPxIF and BCLxIF are cleared by software The Start condition begins with the SDA and SCL pins deasserted. When the SDA pin is sampled high, the Baud Rate Generator is loaded and counts down. If the SCL pin is sampled low while SDA is high, a bus collision occurs because it is assumed that another master is attempting to drive a data `1' during the Start condition. Figure 27-34. Bus Collision During Start Condition (SCL = 0) Rev. 30-000044A 4/3/2017 SDA = 0, SCL = 1 TBRG TBRG SDA Set SEN, enable Start sequence if SDA = 1, SCL = 1 SCL SCL = 0 before SDA = 0, bus collision occurs. Set BCLxIF. SEN SCL = 0 before BRG time-out, bus collision occurs. Set BCLxIF. BCLxIF Interrupt cleared by software '0' '0' SSPxIF '0' '0' S (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 516 PIC18F26/45/46Q10 (MSSP) Master Synchronous Serial Port Module If the SDA pin is sampled low during this count, the BRG is reset and the SDA line is asserted early (Figure 27-35). If, however, a `1' is sampled on the SDA pin, the SDA pin is asserted low at the end of the BRG count. The Baud Rate Generator is then reloaded and counts down to zero; if the SCL pin is sampled as `0' during this time, a bus collision does not occur. At the end of the BRG count, the SCL pin is asserted low. Figure 27-35. BRG Reset Due to SDA Arbitration During Start Condition Rev. 30-000045A 4/10/2017 SDA = 0, SCL = 1 Set S Less than TBRG SDA Set SSPxIF TBRG SDA pulled low by other master. Reset BRG and assert SDA. SCL S SCL pulled low after BRG time- out SEN BCLxIF Set SEN, enable Start sequence if SDA = 1, SCL = 1 '0' S SSPxIF SDA = 0, SCL = 1, set SSPxIF Interrupts cleared by software Important: The reason that bus collision is not a factor during a Start condition is that no two bus masters can assert a Start condition at the exact same time. Therefore, one master will always assert SDA before the other. This condition does not cause a bus collision because the two masters must be allowed to arbitrate the first address following the Start condition. If the address is the same, arbitration must be allowed to continue into the data portion, Repeated Start or Stop conditions. 27.6.13.2 Bus Collision During a Repeated Start Condition During a Repeated Start condition, a bus collision occurs if: 1. 2. A low level is sampled on SDA when SCL goes from low level to high level (Case 1). SCL goes low before SDA is asserted low, indicating that another master is attempting to transmit a data `1' (Case 2). When the user releases SDA and the pin is allowed to float high, the BRG is loaded with SSPxADD and counts down to zero. The SCL pin is then deasserted and when sampled high, the SDA pin is sampled. If SDA is low, a bus collision has occurred (i.e., another master is attempting to transmit a data `0', Figure 27-36). If SDA is sampled high, the BRG is reloaded and begins counting. If SDA goes from high-to-low before the BRG times out, no bus collision occurs because no two masters can assert SDA at exactly the same time. (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 517 PIC18F26/45/46Q10 (MSSP) Master Synchronous Serial Port Module Figure 27-36. Bus Collision During a Repeated Start Condition (Case 1) Rev. 30-000046A 4/3/2017 SDA SCL Sample SDA when SCL goes high. If SDA = 0, set BCLxIF and release SDA and SCL. RSEN BCLxIF Cleared by software S '0' SSPxIF '0' If SCL goes from high-to-low before the BRG times out and SDA has not already been asserted, a bus collision occurs. In this case, another master is attempting to transmit a data `1' during the Repeated Start condition, see Figure 27-37. If, at the end of the BRG time-out, both SCL and SDA are still high, the SDA pin is driven low and the BRG is reloaded and begins counting. At the end of the count, regardless of the status of the SCL pin, the SCL pin is driven low and the Repeated Start condition is complete. Figure 27-37. Bus Collision During Repeated Start Condition (Case 2) Rev. 30-000047A 4/3/2017 TBRG TBRG SDA SCL BCLxIF SCL goes low before SDA, set BCLxIF. Release SDA and SCL. Interrupt cleared by software RSEN '0' S SSPxIF 27.6.13.3 Bus Collision During a Stop Condition Bus collision occurs during a Stop condition if: 1. 2. After the SDA pin has been deasserted and allowed to float high, SDA is sampled low after the BRG has timed out (Case 1). After the SCL pin is deasserted, SCL is sampled low before SDA goes high (Case 2). The Stop condition begins with SDA asserted low. When SDA is sampled low, the SCL pin is allowed to float. When the pin is sampled high (clock arbitration), the Baud Rate Generator is loaded with SSPxADD (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 518 PIC18F26/45/46Q10 (MSSP) Master Synchronous Serial Port Module and counts down to zero. After the BRG times out, SDA is sampled. If SDA is sampled low, a bus collision has occurred. This is due to another master attempting to drive a data `0' (Figure 27-38). If the SCL pin is sampled low before SDA is allowed to float high, a bus collision occurs. This is another case of another master attempting to drive a data `0' (Figure 27-39). Figure 27-38. Bus Collision During a Stop Condition (Case 1) Rev. 30-000048A 4/3/2017 TBRG TBRG TBRG SDA SDA sampled low after TBRG, set BCLxIF SDA asserted low SCL PEN BCLxIF P '0' SSPxIF '0' Figure 27-39. Bus Collision During a Stop Condition (Case 2) Rev. 30-000049A 4/3/2017 TBRG TBRG TBRG SDA Assert SDA SCL SCL goes low before SDA goes high, set BCLxIF PEN BCLxIF 27.7 P '0' SSPxIF '0' Baud Rate Generator The MSSP module has a Baud Rate Generator available for clock generation in both I2C and SPI Master modes. The Baud Rate Generator (BRG) reload value is placed in the SSPxADD register. When a write occurs to SSPxBUF, the Baud Rate Generator will automatically begin counting down. Once the given operation is complete, the internal clock will automatically stop counting and the clock pin will remain in its last state. An internal signal "Reload" shown in Figure 27-40 triggers the value from SSPxADD to be loaded into the BRG counter. This occurs twice for each oscillation of the module clock line. The logic dictating when the reload signal is asserted depends on the mode in which the MSSP is being operated. (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 519 PIC18F26/45/46Q10 (MSSP) Master Synchronous Serial Port Module Table 27-1 illustrates clock rates based on instruction cycles and the BRG value loaded into SSPxADD. Example 27-1. MSSP Baud Rate Generator Frequency Equation = 4 x + 1 Figure 27-40. Baud Rate Generator Block Diagram Rev. 30-000050A 4/3/2017 SSPM<3:0> SSPM<3:0> Reload SCL Control SSPCLK SSPxADD<7:0> Reload BRG Down Counter F OSC/2 Important: Values of 0x00, 0x01 and 0x02 are not valid for SSPxADD when used as a Baud Rate Generator for I2C. This is an implementation limitation. Table 27-1. MSSP Clock Rate w/BRG FOSC FCY BRG Value Fclock (2 Rollovers of BRG) 32 MHz 8 MHz 13h 400 kHz 32 MHz 8 MHz 19h 308 kHz 32 MHz 8 MHz 4Fh 100 kHz 16 MHz 4 MHz 09h 400 kHz 16 MHz 4 MHz 0Ch 308 kHz 16 MHz 4 MHz 27h 100 kHz 4 MHz 1 MHz 09h 100 kHz Note: Refer to the I/O port electrical specifications in the "Electrical Specifications" section, Internal Oscillator Parameters, to ensure the system is designed to support Iol requirements. (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 520 PIC18F26/45/46Q10 (MSSP) Master Synchronous Serial Port Module 27.8 Register Summary: MSSP Control Address Name Bit Pos. 0x0E8D SSP2BUF 7:0 0x0E8E SSP2ADD 7:0 0x0E8F SSP2MSK 7:0 BUF[7:0] ADD[7:0] MSK[6:0] MSK0 0x0E90 SSP2STAT 7:0 SMP CKE D/A P 0x0E91 SSP2CON1 7:0 WCOL SSPOV SSPEN CKP S 0x0E92 SSP2CON2 7:0 GCEN ACKSTAT ACKDT ACKEN RCEN 0x0E93 SSP2CON3 7:0 ACKTIM PCIE SCIE BOEN SDAHT R/W UA BF PEN RSEN SEN SBCDE AHEN DHEN R/W UA SSPM[3:0] 0x0E94 ... Reserved 0x0F90 0x0F91 SSP1BUF 7:0 BUF[7:0] 0x0F92 SSP1ADD 7:0 ADD[7:0] 0x0F93 SSP1MSK 7:0 0x0F94 SSP1STAT 7:0 SMP CKE D/A P 0x0F95 SSP1CON1 7:0 WCOL SSPOV SSPEN CKP 0x0F96 SSP1CON2 7:0 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN 0x0F97 SSP1CON3 7:0 ACKTIM PCIE SCIE BOEN SDAHT SBCDE AHEN DHEN 27.9 MSK[6:0] MSK0 S BF SSPM[3:0] Register Definitions: MSSP Control (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 521 PIC18F26/45/46Q10 (MSSP) Master Synchronous Serial Port Module 27.9.1 SSPxSTAT Name: Address: SSPxSTAT 0xF94,0xE90 MSSP Status Register Bit Access Reset 7 6 5 4 3 2 1 0 SMP CKE D/A P S R/W UA BF R/W R/W RO RO RO RO RO RO 0 0 0 0 0 0 0 0 Bit 7 - SMP Slew Rate Control bit Value Mode Description 1 SPI Master Input data is sampled at the end of data output time 0 SPI Master Input data is sampled at the middle of data output time 0 SPI Slave Keep this bit cleared in SPI Slave mode 1 I2C Slew rate control is disabled for Standard Speed mode (100 kHz and 1 MHz) 0 I2C Slew rate control is enabled for High-Speed mode (400 kHz) Bit 6 - CKE SPI: Clock select bit(4) I2C: SMBus Select bit Value 1 0 1 0 Mode SPI SPI I2C I2C Description Transmit occurs on the transition from active to Idle clock state Transmit occurs on the transition from Idle to active clock state Enables SMBus-specific inputs Disables SMBus-specific inputs Bit 5 - D/A Data/Address bit Value Mode x SPI or I2C Master 1 I2C Slave 0 I2C Slave Description Reserved Indicates that the last byte received or transmitted was data Indicates that the last byte received or transmitted was address Bit 4 - P Stop bit(1) Value Mode x SPI 1 I2C 0 I2C Description Reserved Stop bit was detected last Stop bit was not detected last Bit 3 - S Start bit(1) Value x 1 0 Description Reserved Start bit was detected last Start bit was not detected last Mode SPI I2C I2C (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 522 PIC18F26/45/46Q10 (MSSP) Master Synchronous Serial Port Module Bit 2 - R/W Read/Write Information bit(2,3) Value Mode x SPI 1 I2C Slave 0 I2C Slave 1 I2C Master 0 I2C Master Bit 1 - UA Value x 1 0 Description Reserved Read Write Transmit is in progress Transmit is not in progress Update Address bit (10-Bit Slave mode only) Mode Description All other modes Reserved I2C 10-bit Slave Indicates that the user needs to update the address in the SSPxADD register I2C 10-bit Slave Address does not need to be updated Bit 0 - BF Buffer Full Status bit(5) Value Mode 1 I2C Transmit 0 I2C Transmit 1 SPI and I2C Receive 0 SPI and I2C Receive Description Character written to SSPxBUF has not been sent SSPxBUF is ready for next character Received character in SSPxBUF has not been read Received character in SSPxBUF has been read Note: 1. This bit is cleared on Reset and when SSPEN is cleared. 2. In I2C Slave mode this bit holds the R/W bit information following the last address match. This bit is only valid from the address match to the next Start bit, Stop bit or not ACK bit. 3. ORing this bit with SEN, RSEN, PEN, RCEN or ACKEN will indicate if the MSSP is in Active mode. 4. Polarity of clock state is set by the CKP bit. 5. I2C receive status does not include ACK and Stop bits. (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 523 PIC18F26/45/46Q10 (MSSP) Master Synchronous Serial Port Module 27.9.2 SSPxCON1 Name: Address: SSPxCON1 0xF95,0xE91 MSSP Control Register 1 Bit Access Reset 7 6 5 4 WCOL SSPOV SSPEN CKP R/W/HS R/W/HS R/W R/W R/W 0 0 0 0 0 Bit 7 - WCOL Write Collision Detect bit Value Mode 1 SPI 1 I2C Master transmit 1 I2C Slave transmit 0 SPI or I2C Master or Slave transmit Master or Slave receive x Bit 6 - SSPOV Receive Overflow Indicator bit(1) Value Mode 1 SPI Slave 1 I2C Receive 0 SPI Slave or I2C Receive SPI Master or I2C Master transmit x 3 2 1 0 R/W R/W R/W 0 0 0 SSPM[3:0] Description A write to the SSPxBUF register was attempted while the previous byte was still transmitting (must be cleared by software) A write to the SSPxBUF register was attempted while the I2C conditions were not valid for a transmission to be started (must be cleared by software) The SSPxBUF register is written while it is still transmitting the previous word (must be cleared in software) No collision Don't care Description A byte is received while the SSPxBUF register is still holding the previous byte. The user must read SSPxBUF, even if only transmitting data, to avoid setting overflow. (must be cleared in software) A byte is received while the SSPxBUF register is still holding the previous byte (must be cleared in software) No overflow Don't care Bit 5 - SSPEN Master Synchronous Serial Port Enable bit.(2) Value Mode Description 1 SPI Enables the serial port. The SCKx, SDOx, SDIx, and SSx pin selections must be made with the PPS controls. Each signal must be configured with the corresponding TRIS control to the direction appropriate for the mode selected. (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 524 PIC18F26/45/46Q10 (MSSP) Master Synchronous Serial Port Module Value 1 0 Mode Description I2C Enables the serial port. The SDAx and SCLx pin selections must be made with the PPS controls. Since both signals are bidirectional the PPS input pin and PPS output pin selections must be made that specify the same pin. Both pins must be configured as inputs with the corresponding TRIS controls. All Disables serial port and configures these pins as I/O port pins Bit 4 - CKP SCK Release Control bit Value Mode 1 SPI 0 SPI 1 I2C Slave 0 I2C Slave x I2C Master Description Idle state for the clock is a high level Idle state for the clock is a low level Releases clock Holds clock low (clock stretch), used to ensure data setup time Unused in this mode Bits 3:0 - SSPM[3:0] Master Synchronous Serial Port Mode Select bits(4) Value Description 1111 I2C Slave mode: 10-bit address with Start and Stop bit interrupts enabled 1110 I2C Slave mode: 7-bit address with Start and Stop bit interrupts enabled 1101 Reserved - do not use 1100 Reserved - do not use 1011 I2C Firmware Controlled Master mode (slave Idle) 1010 SPI Master mode: Clock = FOSC/(4*(SSPxADD+1)). SSPxADD must be greater than 0.(3) 1001 Reserved - do not use 1000 I2C Master mode: Clock = FOSC/(4 * (SSPxADD + 1)) 0111 I2C Slave mode: 10-bit address 0110 I2C Slave mode: 7-bit address 0101 SPI Slave mode: Clock = SCKx pin. SSx pin control is disabled 0100 SPI Slave mode: Clock = SCKx pin. SSx pin control is enabled 0011 SPI Master mode: Clock = TMR2 output/2 0010 SPI Master mode: Clock = Fosc/64 0001 SPI Master mode: Clock = Fosc/16 0000 SPI Master mode: Clock = Fosc/4 Note: 1. In Master mode, the overflow bit is not set since each new reception (and transmission) is initiated by writing to the SSPxBUF register. 2. When enabled, these pins must be properly configured as inputs or outputs. 3. SSPxADD = 0 is not supported. 4. Bit combinations not specifically listed here are either reserved or implemented in I2C mode only. (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 525 PIC18F26/45/46Q10 (MSSP) Master Synchronous Serial Port Module 27.9.3 SSPxCON2 Name: Address: SSPxCON2 0xF96,0xE92 Control Register for I2C Operation Only MSSP Control Register 2 Bit Access Reset 7 6 5 4 3 2 1 0 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN R/W R/W/HC R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Bit 7 - GCEN General Call Enable bit (Slave mode only) Value Mode x Master mode 1 Slave mode 0 Slave mode Description Don't care General call is enabled General call is not enabled Bit 6 - ACKSTAT Acknowledge Status bit (Master Transmit mode only) Value Description 1 Acknowledge was not received from slave 0 Acknowledge was received from slave Bit 5 - ACKDT Acknowledge Data bit (Master Receive mode only)(1) Value Description 1 Not Acknowledge 0 Acknowledge Bit 4 - ACKEN Acknowledge Sequence Enable bit(2) Value Description 1 Initiates Acknowledge sequence on SDAx and SCLx pins and transmits ACKDT data bit; automatically cleared by hardware 0 Acknowledge sequence is Idle Bit 3 - RCEN Receive Enable bit (Master Receive mode only)(2) Value Description 1 Enables Receive mode for I2C 0 Receive is Idle Bit 2 - PEN Stop Condition Enable bit (Master mode only)(2) Value Description 1 Initiates Stop condition on SDAx and SCLx pins; automatically cleared by hardware 0 Stop condition is Idle (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 526 PIC18F26/45/46Q10 (MSSP) Master Synchronous Serial Port Module Bit 1 - RSEN Repeated Start Condition Enable bit (Master mode only)(2) Value Description 1 Initiates Repeated Start condition on SDAx and SCLx pins; automatically cleared by hardware 0 Repeated Start condition is Idle Bit 0 - SEN Start Condition Enable bit (Master mode only)(2) Value Description 1 Initiates Start condition on SDAx and SCLx pins; automatically cleared by hardware 0 Start condition is Idle Note: 1. The value that will be transmitted when the user initiates an Acknowledge sequence at the end of a receive. 2. If the I2C module is active, these bits may not be set (no spooling) and the SSPxBUF may not be written (or writes to the SSPxBUF are disabled). (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 527 PIC18F26/45/46Q10 (MSSP) Master Synchronous Serial Port Module 27.9.4 SSPxCON3 Name: Address: SSPxCON3 0xF97,0xE93 MSSP Control Register 3 Bit Access Reset 7 6 5 4 3 2 1 0 ACKTIM PCIE SCIE BOEN SDAHT SBCDE AHEN DHEN R/HS/HC R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Bit 7 - ACKTIM Acknowledge Time Status bit Unused in Master mode. Value Mode x SPI or I2C Master 1 I2C Slave and AHEN = 1 or DHEN = 1 0 I2C Slave Description This bit is not used Eighth falling edge of SCL has occurred and the ACK/ NACK state is active ACK/NACK state is not active. Transitions low on ninth rising edge of SCL. Bit 6 - PCIE Stop Condition Interrupt Enable bit(1) Value Mode x SPI or SSPM = 1111 or 0111 1 SSPM 1111 and SSPM 0111 0 SSPM 1111 and SSPM 0111 Description Don't care Enable interrupt on detection of Stop condition Stop detection interrupts are disabled Bit 5 - SCIE Start Condition Interrupt Enable bit Value Mode x SPI or SSPM = 1111 or 0111 1 SSPM 1111 and SSPM 0111 0 SSPM 1111 and SSPM 0111 Description Don't care Enable interrupt on detection of Start condition Start detection interrupts are disabled Bit 4 - BOEN Buffer Overwrite Enable bit(2) Value Mode Description 1 SPI SSPxBUF is updated every time a new data byte is available, ignoring the BF bit 0 SPI If a new byte is receive with BF set then SSPOV is set and SSPxBUF is not updated 1 I2C SSPxBUF is updated every time a new data byte is available, ignoring the SSPOV effect on updating the buffer 0 I2C SSPxBUF is only updated when SSPOV is clear Bit 3 - SDAHT SDA Hold Time Selection bit Value Mode Description x SPI Not used in SPI mode 1 I2C Minimum of 300ns hold time on SDA after the falling edge of SCL 2 0 I C Minimum of 100ns hold time on SDA after the falling edge of SCL (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 528 PIC18F26/45/46Q10 (MSSP) Master Synchronous Serial Port Module Bit 2 - SBCDE Slave Mode Bus Collision Detect Enable bit Unused in Master mode. Value Mode Description 2 x SPI or I C Master Don't care 1 I2C Slave Collision detection is enabled 0 I2C Slave Collision detection is not enabled Bit 1 - AHEN Address Hold Enable bit Value Mode Description x SPI or I2C Master Don't care 1 I2C Slave Address hold is enabled. As a result CKP is cleared after the eighth falling SCL edge of an address byte reception. Software must set the CKP bit to resume operation. 2 0 I C Slave Address hold is not enabled Bit 0 - DHEN Data Hold Enable bit Value Mode Description x SPI or I2C Master Don't care 1 I2C Slave Data hold is enabled. As a result CKP is cleared after the eighth falling SCL edge of a data byte reception. Software must set the CKP bit to resume operation. 2 0 I C Slave Data hold is not enabled Note: 1. This bit has no effect in Slave modes that Start and Stop condition detection is explicitly listed as enabled. 2. For daisy-chained SPI operation; allows the user to ignore all but the last received byte. SSPOV is still set when a new byte is received and BF = 1, but hardware continues to write the most recent byte to SSPxBUF. (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 529 PIC18F26/45/46Q10 (MSSP) Master Synchronous Serial Port Module 27.9.5 SSPxBUF Name: Address: SSPxBUF 0xF91,0xE8D MSSP Data Buffer Register Bit 7 6 5 4 3 2 1 0 BUF[7:0] Access Reset R/W R/W R/W R/W R/W R/W R/W R/W x x x x x x x x Bits 7:0 - BUF[7:0] MSSP Input and Output Data Buffer bits (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 530 PIC18F26/45/46Q10 (MSSP) Master Synchronous Serial Port Module 27.9.6 SSPxADD Name: Address: SSPxADD 0xF92,0xE8E MSSP Baud Rate Divider and Address Register Bit 7 6 5 4 3 2 1 0 ADD[7:0] Access Reset R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Bits 7:0 - ADD[7:0] * SPI and I2C Master: Baud rate divider * I2C Slave: Address bits Value Mode 3 to SPI and I2C Master 255 2,4,6,8 I2C 10-bit Slave MS Address n I2C 10-bit Slave LS Address 2*(1 to I2C 7-bit Slave 127) (c) 2019 Microchip Technology Inc. Description Baud rate divider. SCK/SCL pin clock period = ((n + 1) *4)/FOSC. Values less than 3 are not valid. Bits 7-3 and Bit 0 are not used and are don't care. Bits 2:1 are bits 9:8 of the 10-bit Slave Most Significant Address Bits 7:0 of 10-Bit Slave Least Significant Address Bit 0 is not used and is don't care. Bits 7:1 are the 7-bit Slave Address Datasheet Preliminary DS40001996C-page 531 PIC18F26/45/46Q10 (MSSP) Master Synchronous Serial Port Module 27.9.7 SSPxMSK Name: Address: SSPxMSK 0xF93,0xE8F MSSP Address Mask Register Bit 7 6 5 4 3 2 1 MSK[6:0] Access Reset 0 MSK0 R/W R/W R/W R/W R/W R/W R/W R/W 1 1 1 1 1 1 1 1 Bits 7:1 - MSK[6:0] Mask bits Value Mode Description 1 I2C Slave The received address bit n is compared to SSPxADD bit n to detect I2C address match 2 0 I C Slave The received address bit n is not used to detect I2C address match Bit 0 - MSK0 Mask bit for I2C 10-bit Slave mode Value Mode Description 2 1 I C 10-bit Slave The received address bit 0 is compared to SSPxADD bit 0 to detect I2C address match 0 I2C 10-bit Slave The received address bit 0 is not used to detect I2C address match x SPI or I2C 7-bit Don't care (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 532 PIC18F26/45/46Q10 (EUSART) Enhanced Universal Synchronous Asyn... 28. (EUSART) Enhanced Universal Synchronous Asynchronous Receiver Transmitter The Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART) module is a serial I/O communications peripheral. It contains all the clock generators, shift registers and data buffers necessary to perform an input or output serial data transfer independent of device program execution. The EUSART, also known as a Serial Communications Interface (SCI), can be configured as a full-duplex asynchronous system or half-duplex synchronous system. Full-Duplex mode is useful for communications with peripheral systems, such as CRT terminals and personal computers. Half-Duplex Synchronous mode is intended for communications with peripheral devices, such as A/D or D/A integrated circuits, serial EEPROMs or other microcontrollers. These devices typically do not have internal clocks for baud rate generation and require the external clock signal provided by a master synchronous device. The EUSART module includes the following capabilities: * * * * * * * * * * * Full-duplex asynchronous transmit and receive Two-character input buffer One-character output buffer Programmable 8-bit or 9-bit character length Address detection in 9-bit mode Input buffer overrun error detection Received character framing error detection Half-duplex synchronous master Half-duplex synchronous slave Programmable clock polarity in Synchronous modes Sleep operation The EUSART module implements the following additional features, making it ideally suited for use in Local Interconnect Network (LIN) bus systems: * Automatic detection and calibration of the baud rate * Wake-up on Break reception * 13-bit Break character transmit Block diagrams of the EUSART transmitter and receiver are shown in Figure 28-1 and Figure 28-2. The operation of the EUSART module consists of six registers: * * * * * * Transmit Status and Control (28.6.2 TXxSTA) Receive Status and Control (28.6.1 RCxSTA) Baud Rate Control (28.6.3 BAUDxCON) Baud Rate Value (28.6.4 SPxBRG) Receive Data Register (28.6.5 RCxREG) Transmit Data Register (28.6.6 TXxREG) The RXx/DTx and TXx/CKx input pins are selected with the RXxPPS and TXxPPS registers, respectively. TXx, CKx, and DTx output pins are selected with each pin's RxyPPS register. Since the RX input is coupled with the DT output in Synchronous mode, it is the user's responsibility to select the same pin for both of these functions when operating in Synchronous mode. The EUSART control logic will control the data direction drivers automatically. (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 533 PIC18F26/45/46Q10 (EUSART) Enhanced Universal Synchronous Asyn... Figure 28-1. EUSART Transmit Block Diagram Rev. 10-000 113C 2/15/201 7 Data bu s TXIE 8 Inte rrupt TXREG register SYNC CSRC TXIF 8 RxyPP S(1) TXEN CKx Pi n PPS 1 MSb LSb (8) 0 0 RXx/DTx Pin Pin Buffer and Control PPS Transmit Shift Register (TSR) CKPPS (2) TX_out Bau d Rate Gene rato r TRMT FOSC /n TX9 n BRG16 +1 SPB RG H SPB RG L Multiplier x4 x16 x64 SYNC 1 x 0 0 0 BRGH x 1 1 0 0 BRG16 x 1 0 1 0 TX9D 0 TXx/CKx Pi n PPS 1 RxyPP S(2) SYNC CSRC Not e 1: In S ynchro nous mod e, the DT output an d RX inpu t PPS selectio ns should en able th e same pin. 2: In Master S yn chr onous mo de the TX output an d CK inpu t PPS selections shou ld e nable the sa me pin. (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 534 PIC18F26/45/46Q10 (EUSART) Enhanced Universal Synchronous Asyn... Figure 28-2. EUSART Receive Block Diagram Rev. 10-000 114B 2/15/201 7 CRE N OERR RXPPS (1) RSR Register MSb RXx/DTx pin Pin Buffer and Control PPS RCIDL SPE N Data Recove ry Stop (8) 7 LSb 1 0 Start SYNC CSRC PPS RX9 1 CKx Pi n 0 CKPPS (2) Bau d Rate Gene rato r FOSC /n FERR RX9D RCREG Register FIFO 8 BRG16 +1 SPB RG H SPB RG L Multiplier x4 x16 x64 SYNC 1 x 0 0 0 BRGH x 1 1 0 0 BRG16 x 1 0 1 0 n Data B us RCxIF RCxIE Inte rrupt Not e 1: In S ynchro nous mod e, the DT output an d RX inpu t PPS selectio ns should en able th e same pin. 2: In Master S yn chr onous mo de the TX output an d CK inpu t PPS selections shou ld e nable the sa me pin. 28.1 EUSART Asynchronous Mode The EUSART transmits and receives data using the standard non-return-to-zero (NRZ) format. NRZ is implemented with two levels: a VOH Mark state which represents a `1' data bit, and a VOL Space state which represents a `0' data bit. NRZ refers to the fact that consecutively transmitted data bits of the same value stay at the output level of that bit without returning to a neutral level between each bit transmission. An NRZ transmission port idles in the Mark state. Each character transmission consists of one Start bit followed by eight or nine data bits and is always terminated by one or more Stop bits. The Start bit is always a space and the Stop bits are always marks. The most common data format is eight bits. Each transmitted bit persists for a period of 1/(Baud Rate). An on-chip dedicated 8-bit/16-bit Baud Rate Generator is used to derive standard baud rate frequencies from the system oscillator. See Table 28-2 for examples of baud rate configurations. The EUSART transmits and receives the LSb first. The EUSART's transmitter and receiver are functionally independent, but share the same data format and baud rate. Parity is not supported by the hardware, but can be implemented in software and stored as the ninth data bit. 28.1.1 EUSART Asynchronous Transmitter The Figure 28-1 is a simplified representation of the transmitter. The heart of the transmitter is the serial Transmit Shift Register (TSR), which is not directly accessible by software. The TSR obtains its data from the transmit buffer, which is the TXxREG register. 28.1.1.1 Enabling the Transmitter The EUSART transmitter is enabled for asynchronous operations by configuring the following three control bits: (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 535 PIC18F26/45/46Q10 (EUSART) Enhanced Universal Synchronous Asyn... * TXEN = 1 (enables the transmitter circuitry of the EUSART) * SYNC = 0 (configures the EUSART for asynchronous operation) * SPEN = 1 (enables the EUSART and automatically enables the output drivers for the RxyPPS selected as the TXx/CKx output) All other EUSART control bits are assumed to be in their default state. If the TXx/CKx pin is shared with an analog peripheral, the analog I/O function must be disabled by clearing the corresponding ANSEL bit. Important: The TXxIF Transmitter Interrupt flag is set when the TXEN enable bit is set and the TSR is idle. 28.1.1.2 Transmitting Data A transmission is initiated by writing a character to the TXxREG register. If this is the first character, or the previous character has been completely flushed from the TSR, the data in the TXxREG is immediately transferred to the TSR register. If the TSR still contains all or part of a previous character, the new character data is held in the TXxREG until the Stop bit of the previous character has been transmitted. The pending character in the TXxREG is then transferred to the TSR in one TCY immediately following the Stop bit transmission. The transmission of the Start bit, data bits and Stop bit sequence commences immediately following the transfer of the data to the TSR from the TXxREG. 28.1.1.3 Transmit Data Polarity The polarity of the transmit data can be controlled with the SCKP bit of the BAUDxCON register. The default state of this bit is `0' which selects high true transmit idle and data bits. Setting the SCKP bit to `1' will invert the transmit data resulting in low true idle and data bits. The SCKP bit controls transmit data polarity in Asynchronous mode only. In Synchronous mode, the SCKP bit has a different function. See the 28.3.1.2 Clock Polarity section for more detail. 28.1.1.4 Transmit Interrupt Flag The TXxIF interrupt flag bit of the PIRx register is set whenever the EUSART transmitter is enabled and no character is being held for transmission in the TXxREG. In other words, the TXxIF bit is only clear when the TSR is busy with a character and a new character has been queued for transmission in the TXxREG. The TXxIF flag bit is not cleared immediately upon writing TXxREG. TXxIF becomes valid in the second instruction cycle following the write execution. Polling TXxIF immediately following the TXxREG write will return invalid results. The TXxIF bit is read-only, it cannot be set or cleared by software. The TXxIF interrupt can be enabled by setting the TXxIE interrupt enable bit of the PIEx register. However, the TXxIF flag bit will be set whenever the TXxREG is empty, regardless of the state of TXxIE enable bit. To use interrupts when transmitting data, set the TXxIE bit only when there is more data to send. Clear the TXxIE interrupt enable bit upon writing the last character of the transmission to the TXxREG. 28.1.1.5 TSR Status The TRMT bit of the TXxSTA register indicates the status of the TSR register. This is a read-only bit. The TRMT bit is set when the TSR register is empty and is cleared when a character is transferred to the TSR register from the TXxREG. The TRMT bit remains clear until all bits have been shifted out of the TSR register. No interrupt logic is tied to this bit, so the user needs to poll this bit to determine the TSR status. (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 536 PIC18F26/45/46Q10 (EUSART) Enhanced Universal Synchronous Asyn... Important: The TSR register is not mapped in data memory, so it is not available to the user. 28.1.1.6 Transmitting 9-Bit Characters The EUSART supports 9-bit character transmissions. When the TX9 bit of the TXxSTA register is set, the EUSART will shift nine bits out for each character transmitted. The TX9D bit of the TXxSTA register is the ninth, and Most Significant data bit. When transmitting 9-bit data, the TX9D data bit must be written before writing the eight Least Significant bits into the TXxREG. All nine bits of data will be transferred to the TSR shift register immediately after the TXxREG is written. A special 9-bit Address mode is available for use with multiple receivers. See the 28.1.2.7 Address Detection section for more information on the Address mode. 28.1.1.7 Asynchronous Transmission Setup 1. Initialize the SPxBRGH, SPxBRGL register pair and the BRGH and BRG16 bits to achieve the desired baud rate (see 28.2 EUSART Baud Rate Generator (BRG)). 2. Select the transmit output pin by writing the appropriate value to the RxyPPS register. 3. Enable the asynchronous serial port by clearing the SYNC bit and setting the SPEN bit. 4. If 9-bit transmission is desired, set the TX9 control bit. A set ninth data bit will indicate that the eight Least Significant data bits are an address when the receiver is set for address detection. 5. Set SCKP bit if inverted transmit is desired. 6. Enable the transmission by setting the TXEN control bit. This will cause the TXxIF interrupt bit to be set. 7. If interrupts are desired, set the TXxIE interrupt enable bit of the PIEx register 8. An interrupt will occur immediately provided that the GIE and PEIE bits of the INTCON register are also set. 9. If 9-bit transmission is selected, the ninth bit should be loaded into the TX9D data bit. 10. Load 8-bit data into the TXxREG register. This will start the transmission. Figure 28-3. Asynchronous Transmission Rev. 10-000 115A 2/7/201 7 Word 1 Write to TXxREG BRG Output (Shift Clock) TXx/CKx pin TXxIF bit (Transmit Buffer Reg Empty Flag) TRMT bit (Transmit Shift Reg Empty Flag) Start bit bit 0 bit 1 bit 7/8 Stop bit Word 1 1 TCY (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 537 PIC18F26/45/46Q10 (EUSART) Enhanced Universal Synchronous Asyn... Figure 28-4. Asynchronous Transmission (Back-to-Back) Word 1 Rev. 10-000 116A 2/7/201 7 Word 2 Write to TXxREG BRG Output (Shift Clock) TXx/CKx pin TXxIF bit (Transmit Buffer Reg Empty Flag) TRMT bit (Transmit Shift Reg Empty Flag) 28.1.2 Start bit bit 0 bit 1 bit 7/8 Word 1 Stop bit Start bit bit 0 Word 2 1 TCY EUSART Asynchronous Receiver The Asynchronous mode is typically used in RS-232 systems. A simplified representation of the receiver is shown in the Figure 28-2. The data is received on the RXx/DTx pin and drives the data recovery block. The data recovery block is actually a high-speed shifter operating at 16 times the baud rate, whereas the serial Receive Shift Register (RSR) operates at the bit rate. When all eight or nine bits of the character have been shifted in, they are immediately transferred to a two character First-In-First-Out (FIFO) memory. The FIFO buffering allows reception of two complete characters and the start of a third character before software must start servicing the EUSART receiver. The FIFO and RSR registers are not directly accessible by software. Access to the received data is via the RCxREG register. 28.1.2.1 Enabling the Receiver The EUSART receiver is enabled for asynchronous operation by configuring the following three control bits: * CREN = 1 (enables the receiver circuitry of the EUSART) * SYNC = 0 (configures the EUSART for asynchronous operation) * SPEN = 1 (enables the EUSART) All other EUSART control bits are assumed to be in their default state. The user must set the RXxPPS register to select the RXx/DTx I/O pin and set the corresponding TRIS bit to configure the pin as an input. Important: If the RX/DT function is on an analog pin, the corresponding ANSEL bit must be cleared for the receiver to function. 28.1.2.2 Receiving Data The receiver data recovery circuit initiates character reception on the falling edge of the first bit. The first bit, also known as the Start bit, is always a zero. The data recovery circuit counts one-half bit time to the center of the Start bit and verifies that the bit is still a zero. If it is not a zero then the data recovery circuit aborts character reception, without generating an error, and resumes looking for the falling edge of the Start bit. If the Start bit zero verification succeeds then the data recovery circuit counts a full bit time to the center of the next bit. The bit is then sampled by a majority detect circuit and the resulting `0' or `1' is shifted into the RSR. This repeats until all data bits have been sampled and shifted into the RSR. One final bit time is measured and the level sampled. This is the Stop bit, which is always a `1'. If the data (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 538 PIC18F26/45/46Q10 (EUSART) Enhanced Universal Synchronous Asyn... recovery circuit samples a `0' in the Stop bit position then a framing error is set for this character, otherwise the framing error is cleared for this character. See the 28.1.2.4 Receive Framing Error section for more information on framing errors. Immediately after all data bits and the Stop bit have been received, the character in the RSR is transferred to the EUSART receive FIFO and the RCxIF interrupt flag bit of the PIRx register is set. The top character in the FIFO is transferred out of the FIFO by reading the RCxREG register. Important: If the receive FIFO is overrun, no additional characters will be received until the overrun condition is cleared. See the 28.1.2.5 Receive Overrun Error section for more information. 28.1.2.3 Receive Interrupts The RCxIF interrupt flag bit of the PIRx register is set whenever the EUSART receiver is enabled and there is an unread character in the receive FIFO. The RCxIF interrupt flag bit is read-only, it cannot be set or cleared by software. RCxIF interrupts are enabled by setting all of the following bits: * RCxIE, Interrupt Enable bit of the PIEx register * PEIE, Peripheral Interrupt Enable bit of the INTCON register * GIE, Global Interrupt Enable bit of the INTCON register The RCxIF interrupt flag bit will be set when there is an unread character in the FIFO, regardless of the state of interrupt enable bits. 28.1.2.4 Receive Framing Error Each character in the receive FIFO buffer has a corresponding framing error Status bit. A framing error indicates that a Stop bit was not seen at the expected time. The framing error status is accessed via the FERR bit of the RCxSTA register. The FERR bit represents the status of the top unread character in the receive FIFO. Therefore, the FERR bit must be read before reading the RCxREG. The FERR bit is read-only and only applies to the top unread character in the receive FIFO. A framing error (FERR = 1) does not preclude reception of additional characters. It is not necessary to clear the FERR bit. Reading the next character from the FIFO buffer will advance the FIFO to the next character and the next corresponding framing error. The FERR bit can be forced clear by clearing the SPEN bit of the RCxSTA register which resets the EUSART. Clearing the CREN bit of the RCxSTA register does not affect the FERR bit. A framing error by itself does not generate an interrupt. Important: If all receive characters in the receive FIFO have framing errors, repeated reads of the RCxREG will not clear the FERR bit. 28.1.2.5 Receive Overrun Error The receive FIFO buffer can hold two characters. An overrun error will be generated if a third character, in its entirety, is received before the FIFO is accessed. When this happens the OERR bit of the RCxSTA register is set. The characters already in the FIFO buffer can be read but no additional characters will be received until the error is cleared. The error must be cleared by either clearing the CREN bit of the RCxSTA register or by resetting the EUSART by clearing the SPEN bit of the RCxSTA register. (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 539 PIC18F26/45/46Q10 (EUSART) Enhanced Universal Synchronous Asyn... 28.1.2.6 Receiving 9-Bit Characters The EUSART supports 9-bit character reception. When the RX9 bit of the RCxSTA register is set the EUSART will shift nine bits into the RSR for each character received. The RX9D bit of the RCxSTA register is the ninth and Most Significant data bit of the top unread character in the receive FIFO. When reading 9-bit data from the receive FIFO buffer, the RX9D data bit must be read before reading the eight Least Significant bits from the RCxREG. 28.1.2.7 Address Detection A special Address Detection mode is available for use when multiple receivers share the same transmission line, such as in RS-485 systems. Address detection is enabled by setting the ADDEN bit of the RCxSTA register. Address detection requires 9-bit character reception. When address detection is enabled, only characters with the ninth data bit set will be transferred to the receive FIFO buffer, thereby setting the RCxIF interrupt bit. All other characters will be ignored. Upon receiving an address character, user software determines if the address matches its own. Upon address match, user software must disable address detection by clearing the ADDEN bit before the next Stop bit occurs. When user software detects the end of the message, determined by the message protocol used, software places the receiver back into the Address Detection mode by setting the ADDEN bit. 28.1.2.8 Asynchronous Reception Setup 1. Initialize the SPxBRGH:SPxBRGL register pair and the BRGH and BRG16 bits to achieve the desired baud rate (see the 28.2 EUSART Baud Rate Generator (BRG) section). 2. Set the RXxPPS register to select the RXx/DTx input pin. 3. Clear the ANSEL bit for the RXx pin (if applicable). 4. Enable the serial port by setting the SPEN bit. The SYNC bit must be clear for asynchronous operation. 5. If interrupts are desired, set the RCxIE bit of the PIEx register and the GIE and PEIE bits of the INTCON register. 6. If 9-bit reception is desired, set the RX9 bit. 7. Enable reception by setting the CREN bit. 8. The RCxIF interrupt flag bit will be set when a character is transferred from the RSR to the receive buffer. An interrupt will be generated if the RCxIE interrupt enable bit was also set. 9. Read the RCxSTA register to get the error flags and, if 9-bit data reception is enabled, the ninth data bit. 10. Get the received eight Least Significant data bits from the receive buffer by reading the RCxREG register. 11. If an overrun occurred, clear the OERR flag by clearing the CREN receiver enable bit. 28.1.2.9 9-Bit Address Detection Mode Setup This mode would typically be used in RS-485 systems. To set up an Asynchronous Reception with Address Detect Enable follow these steps: 1. 2. 3. 4. Initialize the SPxBRGH:SPxBRGL register pair and the BRGH and BRG16 bits to achieve the desired baud rate (see the 28.2 EUSART Baud Rate Generator (BRG) section). Set the RXxPPS register to select the RXx input pin. Clear the ANSEL bit for the RXx pin (if applicable). Enable the serial port by setting the SPEN bit. The SYNC bit must be clear for asynchronous operation. (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 540 PIC18F26/45/46Q10 (EUSART) Enhanced Universal Synchronous Asyn... 5. 6. 7. 8. 9. 10. 11. 12. 13. If interrupts are desired, set the RCxIE bit of the PIEx register and the GIE and PEIE bits of the INTCON register. Enable 9-bit reception by setting the RX9 bit. Enable address detection by setting the ADDEN bit. Enable reception by setting the CREN bit. The RCxIF interrupt flag bit will be set when a character with the ninth bit set is transferred from the RSR to the receive buffer. An interrupt will be generated if the RCxIE Interrupt Enable bit is also set. Read the RCxSTA register to get the error flags. The ninth data bit will always be set. Get the received eight Least Significant data bits from the receive buffer by reading the RCxREG register. Software determines if this is the device's address. If an overrun occurred, clear the OERR flag by clearing the CREN receiver enable bit. If the device has been addressed, clear the ADDEN bit to allow all received data into the receive buffer and generate interrupts. Figure 28-5. Asynchronous Reception Rev. 10-000 117A 2/8/201 7 RXx/DTx pin Start bit bit 0 Rcv Shift Reg Rcv Buffer Reg Word 1 bit 7/8 Stop bit Start bit bit 0 Word 2 bit 7/8 Stop bit Word 1 RCxREG Start bit bit 0 Word 3 bit 7/8 Stop bit Word 2 RCxREG RCIDL Read RCxREG RCxIF (Interrupt flag) OERR Flag CREN (software clear) Note: This timing diagram shows three bytes appearing on the RXx input. The OERR flag is set because the RCxREG is not read before the third word is received. 28.1.3 Clock Accuracy with Asynchronous Operation The factory calibrates the internal oscillator block output (INTOSC). However, the INTOSC frequency may drift as VDD or temperature changes, and this directly affects the asynchronous baud rate. Two methods may be used to adjust the baud rate clock, but both require a reference clock source of some kind. The first (preferred) method uses the OSCTUNE register to adjust the INTOSC output. Adjusting the value in the OSCTUNE register allows for fine resolution changes to the system clock source. The other method adjusts the value in the Baud Rate Generator. This can be done automatically with the Auto-Baud Detect feature (see 28.2.1 Auto-Baud Detect). There may not be fine enough resolution when adjusting the Baud Rate Generator to compensate for a gradual change in the peripheral clock frequency. (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 541 PIC18F26/45/46Q10 (EUSART) Enhanced Universal Synchronous Asyn... 28.2 EUSART Baud Rate Generator (BRG) The Baud Rate Generator (BRG) is an 8-bit or 16-bit timer that is dedicated to the support of both the asynchronous and synchronous EUSART operation. By default, the BRG operates in 8-bit mode. Setting the BRG16 bit of the BAUDxCON register selects 16-bit mode. The SPxBRGH, SPxBRGL register pair determines the period of the free-running baud rate timer. In Asynchronous mode the multiplier of the baud rate period is determined by both the BRGH bit of the TXxSTA register and the BRG16 bit of the BAUDxCON register. In Synchronous mode, the BRGH bit is ignored. Table 28-1 contains the formulas for determining the baud rate. Figure 28-6 provides a sample calculation for determining the baud rate and baud rate error. Typical baud rates and error values for various asynchronous modes have been computed and are shown in Table 28-2. It may be advantageous to use the high baud rate (BRGH = 1), or the 16-bit BRG (BRG16 = 1) to reduce the baud rate error. The 16-bit BRG mode is used to achieve slow baud rates for fast oscillator frequencies. The BRGH bit is used to achieve very high baud rates. Writing a new value to the SPxBRGH, SPxBRGL register pair causes the BRG timer to be reset (or cleared). This ensures that the BRG does not wait for a timer overflow before outputting the new baud rate. If the system clock is changed during an active receive operation, a receive error or data loss may result. To avoid this problem, check the status of the RCIDL bit to make sure that the receive operation is idle before changing the system clock. Figure 28-6. Calculating Baud Rate Error For a device with Fosc of 16 MHz, desired baud rate of 9600, Asynchronous mode, 8-bit BRG: = Solving for SPxBRG: = = 64 x + 1 -1 64 x 16000000 -1 64 x 9600 = 25.042 25 = 16000000 64 x 25 + 1 = 9615 = = - 9615 - 9600 9600 = 0.16 % (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 542 PIC18F26/45/46Q10 (EUSART) Enhanced Universal Synchronous Asyn... Table 28-1. Baud Rate Formulas Configuration Bits BRG/EUSART Mode Baud Rate Formula 0 8-bit/Asynchronous FOSC/[64 (n+1)] 0 1 8-bit/Asynchronous 0 1 0 16-bit/Asynchronous 0 1 1 16-bit/Asynchronous 1 0 x 8-bit/Synchronous 1 1 x 16-bit/Synchronous SYNC BRG16 BRGH 0 0 0 FOSC/[16 (n+1)] FOSC/[4 (n+1)] Note: x = Don't care, n = value of SPxBRGH:SPxBRGL register pair. Table 28-2. Sample Baud Rates for Asynchronous Modes SYNC = 0, BRGH = 0, BRG16 = 0 FOSC = 32.000 MHz FOSC = 20.000 MHz FOSC = 18.432 MHz FOSC = 11.0592 MHz BAUD RATE Actual % SPBRG Actual % SPBRG Actual % SPBRG Actual % SPBRG Rate Error value Rate Error value Rate Error value Rate Error value (decimal) (decimal) (decimal) (decimal) 300 -- -- -- -- -- -- -- -- -- -- -- -- 1200 -- -- -- 1221 1.73 255 1200 0.00 239 1200 0.00 143 2400 2404 0.16 207 2404 0.16 129 2400 0.00 119 2400 0.00 71 9600 9615 0.16 51 9470 -1.36 32 9600 0.00 29 9600 0.00 17 10417 10417 0.00 47 10417 0.00 29 10286 -1.26 27 10165 -2.42 16 19.2k 19.23k 0.16 25 19.53k 1.73 15 19.20k 0.00 14 19.20k 0.00 8 57.6k 55.55k -3.55 3 -- -- -- 57.60k 0.00 7 57.60k 0.00 2 115.2k -- -- -- -- -- -- -- -- -- -- -- -- SYNC = 0, BRGH = 0, BRG16 = 0 Fosc = 8.000 MHz Fosc = 4.000 MHz Fosc = 3.6864 MHz Fosc = 1.000 MHz BAUD RATE Actual % SPBRG Actual % SPBRG Actual % SPBRG Actual % SPBRG Rate Error value Rate Error value Rate Error value Rate Error value (decimal) (decimal) (decimal) (decimal) 300 -- -- -- 300 0.16 207 300 0.00 191 300 0.16 51 1200 1202 0.16 103 1202 0.16 51 1200 0.00 47 1202 0.16 12 2400 2404 0.16 51 2404 0.16 25 2400 0.00 23 -- -- -- 9600 9615 0.16 12 -- -- -- 9600 0.00 5 -- -- -- (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 543 PIC18F26/45/46Q10 (EUSART) Enhanced Universal Synchronous Asyn... 10417 10417 0.00 11 10417 0.00 5 19.2k -- -- -- -- -- -- 57.6k -- -- -- -- -- -- 115.2k -- -- -- -- -- -- -- -- -- -- -- -- 19.20k 0.00 2 -- -- -- 57.60k 0.00 0 -- -- -- -- -- -- -- -- -- SYNC = 0, BRGH = 1, BRG16 = 0 BAUD RATE Fosc = 32.000 MHz Actual Rate Fosc = 20.000 MHz % SPBRG Error value (decimal) Actual Rate Fosc = 18.432 MHz Fosc = 11.0592 MHz % SPBRG Actual % SPBRG Actual % SPBRG Error value Rate Error value Rate Error value (decimal) (decimal) (decimal) 300 -- -- -- -- -- -- -- -- -- -- -- -- 1200 -- -- -- -- -- -- -- -- -- -- -- -- 2400 -- -- -- -- -- -- -- -- -- -- -- -- 9600 9615 0.16 207 9615 0.16 129 9600 0.00 119 9600 0.00 71 10417 10417 0.00 191 10417 0.00 119 10378 -0.37 110 10473 0.53 65 19.2k 19.23k 0.16 103 19.23k 0.16 64 19.20k 0.00 59 19.20k 0.00 35 57.6k 57.14k -0.79 34 56.82k -1.36 21 57.60k 0.00 19 57.60k 0.00 11 115.2k 117.64k 2.12 16 113.64k -1.36 10 115.2k 0.00 9 115.2k 0.00 5 SYNC = 0, BRGH = 1, BRG16 = 0 Fosc = 8.000 MHz Fosc = 4.000 MHz Fosc = 3.6864 MHz Fosc = 1.000 MHz BAUD RATE Actual % SPBRG Actual % SPBRG Actual % SPBRG Actual % SPBRG Rate Error value Rate Error value Rate Error value Rate Error value (decimal) (decimal) (decimal) (decimal) 300 -- -- -- -- -- -- -- -- -- 300 0.16 207 1200 -- -- -- 1202 0.16 207 1200 0.00 191 1202 0.16 51 2400 2404 0.16 207 2404 0.16 103 2400 0.00 95 2404 0.16 25 9600 9615 0.16 51 9615 0.16 25 9600 0.00 23 -- -- -- 10417 10417 0.00 47 10417 0.00 23 10473 0.53 21 19.2k 19231 0.16 25 19.23k 0.16 12 19.2k 0.00 11 -- -- -- 57.6k 55556 -3.55 8 -- -- -- 57.60k 0.00 3 -- -- -- 115.2k -- -- -- -- 115.2k 0.00 1 -- -- -- -- -- (c) 2019 Microchip Technology Inc. Datasheet Preliminary 10417 0.00 5 DS40001996C-page 544 PIC18F26/45/46Q10 (EUSART) Enhanced Universal Synchronous Asyn... SYNC = 0, BRGH = 0, BRG16 = 1 Fosc = 32.000 MHz BAUD RATE Actual % SPBRG Rate Error value (decimal) Fosc = 20.000 MHz Fosc = 18.432 MHz Fosc = 11.0592 MHz Actual Rate % SPBRG Actual % SPBRG Actual % SPBRG Error value Rate Error value Rate Error value (decimal) (decimal) (decimal) 300 300.0 0.00 6666 300.0 -0.01 4166 300.0 0.00 3839 300.0 0.00 2303 1200 1200 -0.02 3332 1200 -0.03 1041 1200 0.00 959 1200 0.00 575 2400 2401 -0.04 832 2399 -0.03 520 2400 0.00 479 2400 0.00 287 9600 9615 0.16 207 9615 0.16 129 9600 0.00 119 9600 0.00 71 10417 10417 0.00 191 10417 0.00 119 10378 -0.37 110 10473 0.53 65 19.2k 19.23k 0.16 103 19.23k 0.16 64 19.20k 0.00 59 19.20k 0.00 35 57.6k 57.14k -0.79 34 56.818 -1.36 21 57.60k 0.00 19 57.60k 0.00 11 115.2k 117.6k 2.12 16 113.636 -1.36 10 115.2k 0.00 9 115.2k 0.00 5 SYNC = 0, BRGH = 0, BRG16 = 1 Fosc = 8.000 MHz Fosc = 4.000 MHz Fosc = 3.6864 MHz Fosc = 1.000 MHz BAUD RATE Actual % SPBRG Actual % SPBRG Actual % SPBRG Actual % SPBRG Rate Error value Rate Error value Rate Error value Rate Error value (decimal) (decimal) (decimal) (decimal) 300 299.9 -0.02 1666 300.1 0.04 832 300.0 0.00 767 300.5 0.16 207 1200 1199 -0.08 416 1202 0.16 207 1200 0.00 191 1202 0.16 51 2400 2404 0.16 207 2404 0.16 103 2400 0.00 95 2404 0.16 25 9600 9615 0.16 51 9615 0.16 25 9600 0.00 23 -- -- -- 10417 10417 0.00 47 10417 0.00 23 10473 0.53 21 19.2k 19.23k 0.16 25 19.23k 0.16 12 19.20k 0.00 11 -- -- -- 57.6k 8 -- -- -- 57.60k 0.00 3 -- -- -- -- -- -- -- 115.2k 0.00 1 -- -- -- 115.2k 55556 -3.55 -- -- 10417 0.00 5 SYNC = 0, BRGH = 1, BRG16 = 1 or SYNC = 1, BRG16 = 1 Fosc = 32.000 MHz Fosc = 20.000 MHz Fosc = 18.432 MHz Fosc = 11.0592 MHz BAUD RATE Actual % SPBRG Actual % SPBRG Actual % SPBRG Actual % SPBRG Rate Error value Rate Error value Rate Error value Rate Error value (decimal) (decimal) (decimal) (decimal) 300 300.0 0.00 26666 300.0 0.00 16665 300.0 0.00 15359 300.0 0.00 9215 1200 1200 0.00 6666 1200 -0.01 4166 1200 0.00 3839 1200 0.00 2303 (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 545 PIC18F26/45/46Q10 (EUSART) Enhanced Universal Synchronous Asyn... 2400 2400 0.01 3332 2400 0.02 2082 2400 0.00 1919 2400 0.00 1151 9600 9604 0.04 832 9597 -0.03 520 9600 0.00 479 9600 0.00 287 10417 10417 0.00 767 10417 0.00 479 10425 0.08 441 10433 0.16 264 19.2k 19.18k -0.08 416 19.23k 0.16 259 19.20k 0.00 239 19.20k 0.00 143 57.6k 57.55k -0.08 138 57.47k -0.22 86 57.60k 0.00 79 57.60k 0.00 47 115.2k 115.9k 0.64 68 116.3k 0.94 42 115.2k 0.00 39 115.2k 0.00 23 SYNC = 0, BRGH = 1, BRG16 = 1 or SYNC = 1, BRG16 = 1 Fosc = 8.000 MHz Fosc = 4.000 MHz Fosc = 3.6864 MHz Fosc = 1.000 MHz BAUD RATE Actual % SPBRG Actual % SPBRG Actual % SPBRG Actual % SPBRG Rate Error value Rate Error value Rate Error value Rate Error value (decimal) (decimal) (decimal) (decimal) 300 300.0 0.00 6666 300.0 0.01 3332 300.0 0.00 3071 300.1 0.04 832 1200 1200 -0.02 1666 1200 0.04 832 1200 0.00 767 1202 0.16 207 2400 2401 0.04 832 2398 0.08 416 2400 0.00 383 2404 0.16 103 9600 9615 0.16 207 9615 0.16 103 9600 0.00 95 9615 0.16 25 0 191 10417 0.00 95 10473 0.53 87 10417 0.00 23 19.2k 19.23k 0.16 103 19.23k 0.16 51 19.20k 0.00 47 19.23k 0.16 12 57.6k 57.14k -0.79 34 58.82k 2.12 16 57.60k 0.00 15 -- -- -- 115.2k 117.6k 2.12 16 111.1k -3.55 8 115.2k 0.00 7 -- -- -- 10417 10417 28.2.1 Auto-Baud Detect The EUSART module supports automatic detection and calibration of the baud rate. In the Auto-Baud Detect (ABD) mode, the clock to the BRG is reversed. Rather than the BRG clocking the incoming RX signal, the RX signal is timing the BRG. The Baud Rate Generator is used to time the period of a received 55h (ASCII "U") which is the Sync character for the LIN bus. The unique feature of this character is that it has five rising edges including the Stop bit edge. Setting the ABDEN bit of the BAUDxCON register starts the auto-baud calibration sequence. While the ABD sequence takes place, the EUSART state machine is held in Idle. On the first rising edge of the receive line, after the Start bit, the SPxBRG begins counting up using the BRG counter clock as shown in Figure 28-7. The fifth rising edge will occur on the RXx pin at the end of the eighth bit period. At that time, an accumulated value totaling the proper BRG period is left in the SPxBRGH, SPxBRGL register pair, the ABDEN bit is automatically cleared and the RCxIF interrupt flag is set. The value in the RCxREG needs to be read to clear the RCxIF interrupt. RCxREG content should be discarded. When calibrating for modes that do not use the SPxBRGH register the user can verify that the SPxBRGL register did not overflow by checking for 00h in the SPxBRGH register. The BRG auto-baud clock is determined by the BRG16 and BRGH bits as shown in Table 28-3. During ABD, both the SPxBRGH and SPxBRGL registers are used as a 16-bit counter, independent of the BRG16 bit setting. While calibrating the baud rate period, the SPxBRGH and SPxBRGL registers are (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 546 PIC18F26/45/46Q10 (EUSART) Enhanced Universal Synchronous Asyn... clocked at 1/8th the BRG base clock rate. The resulting byte measurement is the average bit time when clocked at full speed. Note: 1. If the WUE bit is set with the ABDEN bit, auto-baud detection will occur on the byte following the Break character (see 28.2.3 Auto-Wake-up on Break). 2. It is up to the user to determine that the incoming character baud rate is within the range of the selected BRG clock source. Some combinations of oscillator frequency and EUSART baud rates are not possible. 3. During the auto-baud process, the auto-baud counter starts counting at one. Upon completion of the auto-baud sequence, to achieve maximum accuracy, subtract 1 from the SPxBRGH:SPxBRGL register pair. Table 28-3. BRG Counter Clock Rates BRG16 BRGH BRG Base Clock BRG ABD Clock 1 1 FOSC/4 FOSC/32 1 0 FOSC/16 FOSC/128 0 1 FOSC/16 FOSC/128 0 0 FOSC/64 FOSC/512 Note: During the ABD sequence, SPxBRGL and SPxBRGH registers are both used as a 16-bit counter, independent of the BRG16 setting. Figure 28-7. Automatic Baud Rate Calibration Rev. 10-000 120A 2/13/201 7 BRG Value XXXXh 0000h 001Ch Edge #1 RXx/DTx pin Edge #2 Edge #3 Edge #4 Edge #5 start bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 BRG Clock ABDEN Auto cleared Set by user RCxIF bit (Interrupt Flag) Read RCxREG SPxBRGH:L 28.2.2 XXXXh 001Ch Auto-Baud Overflow During the course of automatic baud detection, the ABDOVF bit of the BAUDxCON register will be set if the baud rate counter overflows before the fifth rising edge is detected on the RXx pin. The ABDOVF bit indicates that the counter has exceeded the maximum count that can fit in the 16 bits of the SPxBRGH:SPxBRGL register pair. After the ABDOVF bit has been set, the counter continues to count until the fifth rising edge is detected on the RXx pin. Upon detecting the fifth RX edge, the hardware will set the RCxIF interrupt flag and clear the ABDEN bit of the BAUDxCON register. The RCxIF flag can be (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 547 PIC18F26/45/46Q10 (EUSART) Enhanced Universal Synchronous Asyn... subsequently cleared by reading the RCxREG register. The ABDOVF flag of the BAUDxCON register can be cleared by software directly. To terminate the auto-baud process before the RCxIF flag is set, clear the ABDEN bit then clear the ABDOVF bit of the BAUDxCON register. The ABDOVF bit will remain set if the ABDEN bit is not cleared first. 28.2.3 Auto-Wake-up on Break During Sleep mode, all clocks to the EUSART are suspended. Because of this, the Baud Rate Generator is inactive and a proper character reception cannot be performed. The Auto-Wake-up feature allows the controller to wake-up due to activity on the RX/DT line. This feature is available only in Asynchronous mode. The Auto-Wake-up feature is enabled by setting the WUE bit of the BAUDxCON register. Once set, the normal receive sequence on RX/DT is disabled, and the EUSART remains in an Idle state, monitoring for a wake-up event independent of the CPU mode. A wake-up event consists of a high-to-low transition on the RX/DT line. (This coincides with the start of a Sync Break or a wake-up signal character for the LIN protocol.) The EUSART module generates an RCxIF interrupt coincident with the wake-up event. The interrupt is generated synchronously to the Q clocks in normal CPU operating modes as shown in Figure 28-8, and asynchronously if the device is in Sleep mode as shown in Figure 28-9. The interrupt condition is cleared by reading the RCxREG register. The WUE bit is automatically cleared by the low-to-high transition on the RX line at the end of the Break. This signals to the user that the Break event is over. At this point, the EUSART module is in Idle mode waiting to receive the next character. 28.2.3.1 Special Considerations Break Character To avoid character errors or character fragments during a wake-up event, the wake-up character must be all zeros. When the wake-up is enabled the function works independent of the low time on the data stream. If the WUE bit is set and a valid non-zero character is received, the low time from the Start bit to the first rising edge will be interpreted as the wake-up event. The remaining bits in the character will be received as a fragmented character and subsequent characters can result in framing or overrun errors. Therefore, the initial character in the transmission must be all `0's. This must be ten or more bit times, 13bit times recommended for LIN bus, or any number of bit times for standard RS-232 devices. Oscillator Start-up Time Oscillator start-up time must be considered, especially in applications using oscillators with longer start-up intervals (i.e., LP, XT or HS/PLL mode). The Sync Break (or wake-up signal) character must be of sufficient length, and be followed by a sufficient interval, to allow enough time for the selected oscillator to start and provide proper initialization of the EUSART. WUE Bit The wake-up event causes a receive interrupt by setting the RCxIF bit. The WUE bit is cleared in hardware by a rising edge on RX/DT. The interrupt condition is then cleared in software by reading the RCxREG register and discarding its contents. (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 548 PIC18F26/45/46Q10 (EUSART) Enhanced Universal Synchronous Asyn... To ensure that no actual data is lost, check the RCIDL bit to verify that a receive operation is not in process before setting the WUE bit. If a receive operation is not occurring, the WUE bit may then be set just prior to entering the Sleep mode. Figure 28-8. Auto-Wake-up Bit (WUE) Timing During Normal Operation Rev. 10-000 326A 2/13/201 7 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 FOSC WUE bit Bit set by user Auto cleared RXx/DTx line RCxIF Cleared due to user read of RCxREG Note 1: The EUSART remains in idle while the WUE bit is set. Figure 28-9. Auto-Wake-up Bit (WUE) Timings During Sleep Rev. 10-000 327A 2/13/201 7 q1 q2 q3 q4 q1 q2 q3 q4 q2 q1 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 FOSC WUE bit Bit set by user Auto cleared RXx/DTx line RCxIF Cleared due to user read of RCxREG Sleep command executed Sleep ends Note 1: The EUSART remains in idle while the WUE bit is set. 28.2.4 Break Character Sequence The EUSART module has the capability of sending the special Break character sequences that are required by the LIN bus standard. A Break character consists of a Start bit, followed by 12 `0' bits and a Stop bit. To send a Break character, set the SENDB and TXEN bits of the TXxSTA register. The Break character transmission is then initiated by a write to the TXxREG. The value of data written to TXxREG will be ignored and all `0's will be transmitted. The SENDB bit is automatically reset by hardware after the corresponding Stop bit is sent. This allows the user to preload the transmit FIFO with the next transmit byte following the Break character (typically, the Sync character in the LIN specification). The TRMT bit of the TXxSTA register indicates when the transmit operation is active or idle, just as it does during normal transmission. See Figure 28-10 for more detail. 28.2.4.1 Break and Sync Transmit Sequence The following sequence will start a message frame header made up of a Break, followed by an auto-baud Sync byte. This sequence is typical of a LIN bus master. (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 549 PIC18F26/45/46Q10 (EUSART) Enhanced Universal Synchronous Asyn... 1. 2. 3. 4. 5. Configure the EUSART for the desired mode. Set the TXEN and SENDB bits to enable the Break sequence. Load the TXxREG with a dummy character to initiate transmission (the value is ignored). Write `55h' to TXxREG to load the Sync character into the transmit FIFO buffer. After the Break has been sent, the SENDB bit is reset by hardware and the Sync character is then transmitted. When the TXxREG becomes empty, as indicated by the TXxIF, the next data byte can be written to TXxREG. 28.2.5 Receiving a Break Character The EUSART module can receive a Break character in two ways. The first method to detect a Break character uses the FERR bit of the RCxSTA register and the received data as indicated by RCxREG. The Baud Rate Generator is assumed to have been initialized to the expected baud rate. A Break character has been received when all three of the following conditions are true: * RCxIF bit is set * FERR bit is set * RCxREG = 00h The second method uses the Auto-Wake-up feature described in 28.2.3 Auto-Wake-up on Break. By enabling this feature, the EUSART will sample the next two transitions on RX/DT, cause an RCxIF interrupt, and receive the next data byte followed by another interrupt. Note that following a Break character, the user will typically want to enable the Auto-Baud Detect feature. For both methods, the user can set the ABDEN bit of the BAUDxCON register before placing the EUSART in Sleep mode. Figure 28-10. Send Break Character Sequence Dummy Write Rev. 10-000 118A 2/13/201 7 Write to TXxREG BRG Output (Shift Clock) TXx/CKx pin Start bit bit 0 28.3 bit 11 Stop bit Break TXxIF bit (Transmit Buffer Reg Empty Flag) TRMT bit (Transmit Shift Reg Empty Flag) SENDB (send break control bit) bit 1 SENDB sampled here Auto cleared EUSART Synchronous Mode Synchronous serial communications are typically used in systems with a single master and one or more slaves. The master device contains the necessary circuitry for baud rate generation and supplies the (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 550 PIC18F26/45/46Q10 (EUSART) Enhanced Universal Synchronous Asyn... clock for all devices in the system. Slave devices can take advantage of the master clock by eliminating the internal clock generation circuitry. There are two signal lines in Synchronous mode: a bidirectional data line and a clock line. Slaves use the external clock supplied by the master to shift the serial data into and out of their respective receive and transmit shift registers. Since the data line is bidirectional, synchronous operation is half-duplex only. Halfduplex refers to the fact that master and slave devices can receive and transmit data but not both simultaneously. The EUSART can operate as either a master or slave device. Start and Stop bits are not used in synchronous transmissions. 28.3.1 Synchronous Master Mode The following bits are used to configure the EUSART for synchronous master operation: * SYNC = 1 (configures the EUSART for synchronous operation) * CSRC = 1 (configures the EUSART as the master) * SREN = 0 (for transmit); SREN = 1 (recommended setting to receive 1 byte) * CREN = 0 (for transmit); CREN = 1 (to receive continuously) * SPEN = 1 (enables the EUSART) Important: Clearing the SREN and CREN bits of the RCxSTA register ensures that the device is in the Transmit mode, otherwise the device will be configured to receive. 28.3.1.1 Master Clock Synchronous data transfers use a separate clock line, which is synchronous with the data. A device configured as a master transmits the clock on the TX/CK line. The TXx/CKx pin output driver is automatically enabled when the EUSART is configured for synchronous transmit or receive operation. Serial data bits change on the leading edge to ensure they are valid at the trailing edge of each clock. One clock cycle is generated for each data bit. Only as many clock cycles are generated as there are data bits. 28.3.1.2 Clock Polarity A clock polarity option is provided for Microwire compatibility. Clock polarity is selected with the SCKP bit of the BAUDxCON register. Setting the SCKP bit sets the clock Idle state as high. When the SCKP bit is set, the data changes on the falling edge of each clock. Clearing the SCKP bit sets the Idle state as low. When the SCKP bit is cleared, the data changes on the rising edge of each clock. 28.3.1.3 Synchronous Master Transmission Data is transferred out of the device on the RXx/DTx pin. The RXx/DTx and TXx/CKx pin output drivers are automatically enabled when the EUSART is configured for synchronous master transmit operation. A transmission is initiated by writing a character to the TXxREG register. If the TSR still contains all or part of a previous character the new character data is held in the TXxREG until the last bit of the previous character has been transmitted. If this is the first character, or the previous character has been completely flushed from the TSR, the data in the TXxREG is immediately transferred to the TSR. The transmission of the character commences immediately following the transfer of the data to the TSR from the TXxREG. Each data bit changes on the leading edge of the master clock and remains valid until the subsequent leading clock edge. (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 551 PIC18F26/45/46Q10 (EUSART) Enhanced Universal Synchronous Asyn... Note: The TSR register is not mapped in data memory, so it is not available to the user. 28.3.1.4 Synchronous Master Transmission Setup 1. Initialize the SPxBRGH, SPxBRGL register pair and the BRG16 bit to achieve the desired baud rate (see 28.2 EUSART Baud Rate Generator (BRG)). 2. Select the transmit output pin by writing the appropriate values to the RxyPPS register and RXxPPS register. Both selections should enable the same pin. 3. Select the clock output pin by writing the appropriate values to the RxyPPS register and CKxPPS register. Both selections should enable the same pin. 4. Enable the synchronous master serial port by setting bits SYNC, SPEN and CSRC. 5. Disable Receive mode by clearing bits SREN and CREN. 6. Enable Transmit mode by setting the TXEN bit. 7. If 9-bit transmission is desired, set the TX9 bit. 8. If interrupts are desired, set the TXxIE bit of the PIEx register and the GIE and PEIE bits of the INTCON register. 9. If 9-bit transmission is selected, the ninth bit should be loaded in the TX9D bit. 10. Start transmission by loading data to the TXxREG register. Figure 28-11. Synchronous Transmission Rev. 10-000 115A 2/7/201 7 Word 1 Write to TXxREG BRG Output (Shift Clock) TXx/CKx pin TXxIF bit (Transmit Buffer Reg Empty Flag) TRMT bit (Transmit Shift Reg Empty Flag) Start bit bit 0 bit 1 bit 7/8 Stop bit Word 1 1 TCY 28.3.1.5 Synchronous Master Reception Data is received at the RXx/DTx pin. The RXx/DTx pin output driver is automatically disabled when the EUSART is configured for synchronous master receive operation. In Synchronous mode, reception is enabled by setting either the Single Receive Enable bit (SREN of the RCxSTA register) or the Continuous Receive Enable bit (CREN of the RCxSTA register). When SREN is set and CREN is clear, only as many clock cycles are generated as there are data bits in a single character. The SREN bit is automatically cleared at the completion of one character. When CREN is set, clocks are continuously generated until CREN is cleared. If CREN is cleared in the middle of a character the CK clock stops immediately and the partial character is discarded. If SREN and CREN are both set, then SREN is cleared at the completion of the first character and CREN takes precedence. To initiate reception, set either SREN or CREN. Data is sampled at the RXx/DTx pin on the trailing edge of the TX/CK clock pin and is shifted into the Receive Shift Register (RSR). When a complete character is received into the RSR, the RCxIF bit is set and the character is automatically transferred to the two character receive FIFO. The Least Significant eight bits of the top character in the receive FIFO are available in RCxREG. The RCxIF bit remains set as long as there are unread characters in the receive FIFO. (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 552 PIC18F26/45/46Q10 (EUSART) Enhanced Universal Synchronous Asyn... Note: If the RX/DT function is on an analog pin, the corresponding ANSEL bit must be cleared for the receiver to function. 28.3.1.6 Receive Overrun Error The receive FIFO buffer can hold two characters. An overrun error will be generated if a third character, in its entirety, is received before RCxREG is read to access the FIFO. When this happens the OERR bit of the RCxSTA register is set. Previous data in the FIFO will not be overwritten. The two characters in the FIFO buffer can be read, however, no additional characters will be received until the error is cleared. The OERR bit can only be cleared by clearing the overrun condition. If the overrun error occurred when the SREN bit is set and CREN is clear then the error is cleared by reading RCxREG. If the overrun occurred when the CREN bit is set then the error condition is cleared by either clearing the CREN bit of the RCxSTA register or by clearing the SPEN bit which resets the EUSART. 28.3.1.7 Receiving 9-Bit Characters The EUSART supports 9-bit character reception. When the RX9 bit of the RCxSTA register is set the EUSART will shift nine bits into the RSR for each character received. The RX9D bit of the RCxSTA register is the ninth, and Most Significant, data bit of the top unread character in the receive FIFO. When reading 9-bit data from the receive FIFO buffer, the RX9D data bit must be read before reading the eight Least Significant bits from the RCxREG. 28.3.1.8 Synchronous Master Reception Setup 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. Initialize the SPxBRGH:SPxBRGL register pair and set or clear the BRG16 bit, as required, to achieve the desired baud rate. Select the receive input pin by writing the appropriate values to the RxyPPS register and RXxPPS register. Both selections should enable the same pin. Select the clock output pin by writing the appropriate values to the RxyPPS register and CKxPPS register. Both selections should enable the same pin. Clear the ANSEL bit for the RXx pin (if applicable). Enable the synchronous master serial port by setting bits SYNC, SPEN and CSRC. Ensure bits CREN and SREN are clear. If interrupts are desired, set the RCxIE bit of the PIEx register and the GIE and PEIE bits of the INTCON register. If 9-bit reception is desired, set bit RX9. Start reception by setting the SREN bit or for continuous reception, set the CREN bit. Interrupt flag bit RCxIF will be set when reception of a character is complete. An interrupt will be generated if the enable bit RCxIE was set. Read the RCxSTA register to get the ninth bit (if enabled) and determine if any error occurred during reception. Read the 8-bit received data by reading the RCxREG register. If an overrun error occurs, clear the error by either clearing the CREN bit of the RCxSTA register or by clearing the SPEN bit which resets the EUSART. (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 553 PIC18F26/45/46Q10 (EUSART) Enhanced Universal Synchronous Asyn... Figure 28-12. Synchronous Reception (Master Mode, SREN) Rev. 10-000 121A 2/13/201 7 RXx/DTx pin bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 TXx/CKx pin SCKP = 0 TXx/CKx pin SCKP = 1 Write to SREN SREN bit CREN bit `0' `0' RCxIF (Interrupt) Read RCxREG 28.3.2 Synchronous Slave Mode The following bits are used to configure the EUSART for synchronous slave operation: * SYNC = 1 (configures the EUSART for synchronous operation.) * CSRC = 0 (configures the EUSART as a slave) * SREN = 0 (for transmit); SREN = 1 (for single byte receive) * CREN = 0 (for transmit); CREN = 1 (recommended setting for continuous receive) * SPEN = 1 (enables the EUSART) Important: Clearing the SREN and CREN bits of the RCxSTA register ensures that the device is in the Transmit mode, otherwise the device will be configured to receive. 28.3.2.1 Slave Clock Synchronous data transfers use a separate clock line, which is synchronous with the data. A device configured as a slave receives the clock on the TX/CK line. The TXx/CKx pin output driver is automatically disabled when the device is configured for synchronous slave transmit or receive operation. Serial data bits change on the leading edge to ensure they are valid at the trailing edge of each clock. One data bit is transferred for each clock cycle. Only as many clock cycles should be received as there are data bits. Important: If the device is configured as a slave and the TX/CK function is on an analog pin, the corresponding ANSEL bit must be cleared. (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 554 PIC18F26/45/46Q10 (EUSART) Enhanced Universal Synchronous Asyn... 28.3.2.2 EUSART Synchronous Slave Transmit The operation of the Synchronous Master and Slave modes are identical (see 28.3.1.3 Synchronous Master Transmission), except in the case of the Sleep mode. If two words are written to the TXxREG and then the SLEEP instruction is executed, the following will occur: 1. 2. 3. The first character will immediately transfer to the TSR register and transmit. The second word will remain in the TXxREG register. The TXxIF bit will not be set. 4. After the first character has been shifted out of TSR, the TXxREG register will transfer the second character to the TSR and the TXxIF bit will now be set. If the PEIE and TXxIE bits are set, the interrupt will wake the device from Sleep and execute the next instruction. If the GIE bit is also set, the program will call the Interrupt Service Routine. 5. 28.3.2.3 Synchronous Slave Transmission Setup 1. 2. Set the SYNC and SPEN bits and clear the CSRC bit. Select the transmit output pin by writing the appropriate values to the RxyPPS register and RXxPPS register. Both selections should enable the same pin. 3. Select the clock input pin by writing the appropriate value to the CKxPPS register. 4. Clear the ANSEL bit for the CKx pin (if applicable). 5. Clear the CREN and SREN bits. 6. If interrupts are desired, set the TXxIE bit of the PIEx register and the GIE and PEIE bits of the INTCON register. 7. If 9-bit transmission is desired, set the TX9 bit. 8. Enable transmission by setting the TXEN bit. 9. If 9-bit transmission is selected, insert the Most Significant bit into the TX9D bit. 10. Prepare for transmission by writing the Least Significant eight bits to the TXxREG register. The word will be transmitted in response to the Master clocks at the CKx pin. 28.3.2.4 EUSART Synchronous Slave Reception The operation of the Synchronous Master and Slave modes is identical (see 28.3.1.5 Synchronous Master Reception), with the following exceptions: * Sleep * CREN bit is always set, therefore the receiver is never idle * SREN bit, which is a "don't care" in Slave mode A character may be received while in Sleep mode by setting the CREN bit prior to entering Sleep. Once the word is received, the RSR register will transfer the data to the RCxREG register. If the RCxIE enable bit is set, the interrupt generated will wake the device from Sleep and execute the next instruction. If the GIE bit is also set, the program will branch to the interrupt vector. 28.3.2.5 Synchronous Slave Reception Setup: 1. 2. 3. 4. 5. Set the SYNC and SPEN bits and clear the CSRC bit. Select the receive input pin by writing the appropriate value to the RXxPPS register. Select the clock input pin by writing the appropriate values to the CKxPPS register. Clear the ANSEL bit for both the TXx/CKx and RXx/DTx pins (if applicable). If interrupts are desired, set the RCxIE bit of the PIEx register and the GIE and PEIE bits of the INTCON register. (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 555 PIC18F26/45/46Q10 (EUSART) Enhanced Universal Synchronous Asyn... 6. 7. 8. If 9-bit reception is desired, set the RX9 bit. Set the CREN bit to enable reception. The RCxIF bit will be set when reception is complete. An interrupt will be generated if the RCxIE bit was set. 9. If 9-bit mode is enabled, retrieve the Most Significant bit from the RX9D bit of the RCxSTA register. 10. Retrieve the eight Least Significant bits from the receive FIFO by reading the RCxREG register. 11. If an overrun error occurs, clear the error by either clearing the CREN bit of the RCxSTA register or by clearing the SPEN bit which resets the EUSART. 28.4 EUSART Operation During Sleep The EUSART will remain active during Sleep only in the Synchronous Slave mode. All other modes require the system clock and therefore cannot generate the necessary signals to run the Transmit or Receive Shift registers during Sleep. Synchronous Slave mode uses an externally generated clock to run the Transmit and Receive Shift registers. 28.4.1 Synchronous Receive During Sleep To receive during Sleep, all the following conditions must be met before entering Sleep mode: * RCxSTA and TXxSTA Control registers must be configured for Synchronous Slave Reception (see 28.3.2.5 Synchronous Slave Reception Setup:). * If interrupts are desired, set the RCxIE bit of the PIEx register and the GIE and PEIE bits of the INTCON register. * The RCxIF interrupt flag must be cleared by reading RCxREG to unload any pending characters in the receive buffer. Upon entering Sleep mode, the device will be ready to accept data and clocks on the RXx/DTx and TXx/CKx pins, respectively. When the data word has been completely clocked in by the external device, the RCxIF interrupt flag bit of the PIRx register will be set. Thereby, waking the processor from Sleep. Upon waking from Sleep, the instruction following the SLEEP instruction will be executed. If the Global Interrupt Enable (GIE) bit of the INTCON register is also set, then the Interrupt Service Routine at address 004h will be called. 28.4.2 Synchronous Transmit During Sleep To transmit during Sleep, all the following conditions must be met before entering Sleep mode: * The RCxSTA and TXxSTA Control registers must be configured for synchronous slave transmission (see 28.3.2.3 Synchronous Slave Transmission Setup). * The TXxIF interrupt flag must be cleared by writing the output data to the TXxREG, thereby filling the TSR and transmit buffer. * Interrupt enable bits TXxIE of the PIEx register and PEIE of the INTCON register must set. * If interrupts are desired, set the GIEx bit of the INTCON register. Upon entering Sleep mode, the device will be ready to accept clocks on the TXx/CKx pin and transmit data on the RXx/DTx pin. When the data word in the TSR has been completely clocked out by the external device, the pending byte in the TXxREG will transfer to the TSR and the TXxIF flag will be set. Thereby, waking the processor from Sleep. At this point, the TXxREG is available to accept another character for transmission. Writing TXxREG will clear the TXxIF flag. (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 556 PIC18F26/45/46Q10 (EUSART) Enhanced Universal Synchronous Asyn... Upon waking from Sleep, the instruction following the SLEEP instruction will be executed. If the Global Interrupt Enable (GIE) bit is also set then the Interrupt Service Routine at address 0004h will be called. (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 557 PIC18F26/45/46Q10 (EUSART) Enhanced Universal Synchronous Asyn... 28.5 Register Summary - EUSART Address Name Bit Pos. 0x0E94 RC2REG 7:0 0x0E95 TX2REG 7:0 TXREG[7:0] 7:0 SPBRGL[7:0] RCREG[7:0] 0x0E96 SP2BRG 0x0E98 RC2STA 7:0 SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0x0E99 TX2STA 7:0 CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 0x0E9A BAUD2CON 7:0 ABDOVF RCIDL SCKP BRG16 WUE ABDEN RX9D 15:8 SPBRGH[7:0] 0x0E9B ... Reserved 0x0F97 0x0F98 RC1REG 7:0 RCREG[7:0] 0x0F99 TX1REG 7:0 TXREG[7:0] 0x0F9A SP1BRG 0x0F9C RC1STA 7:0 0x0F9D TX1STA 7:0 0x0F9E BAUD1CON 7:0 28.6 7:0 SPBRGL[7:0] 15:8 SPBRGH[7:0] SPEN RX9 SREN CREN ADDEN FERR OERR CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D ABDOVF RCIDL SCKP BRG16 WUE ABDEN Register Definitions: EUSART Control (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 558 PIC18F26/45/46Q10 (EUSART) Enhanced Universal Synchronous Asyn... 28.6.1 RCxSTA Name: Address: RCxSTA 0xF9C,0xE98 Receive Status and Control Register Bit Access Reset 7 6 5 4 3 2 1 0 SPEN RX9 SREN CREN ADDEN FERR OERR RX9D R/W R/W R/W R/W R/W RO R/HC R/HC 0 0 0 0 0 0 0 0 Bit 7 - SPEN Serial Port Enable bit Value Description 1 Serial port enabled 0 Serial port disabled (held in Reset) Bit 6 - RX9 9-Bit Receive Enable bit Value Description 1 Selects 9-bit reception 0 Selects 8-bit reception Bit 5 - SREN Single Receive Enable bit Controls reception. This bit is cleared by hardware when reception is complete Value Condition Description 1 SYNC = 1 AND CSRC = 1 Start single receive 0 SYNC = 1 AND CSRC = 1 Single receive is complete X SYNC = 0 OR CSRC = 0 Don't care Bit 4 - CREN Continuous Receive Enable bit Value Condition Description 1 SYNC = 1 Enables continuous receive until enable bit CREN is cleared (CREN overrides SREN) 0 SYNC = 1 Disables continuous receive 1 SYNC = 0 Enables receiver 0 SYNC = 0 Disables receiver Bit 3 - ADDEN Address Detect Enable bit Value Condition Description 1 SYNC = 0 AND RX9 = 1 The receive buffer is loaded and the interrupt occurs only when the ninth received bit is set 0 SYNC = 0 AND RX9 = 1 All bytes are received and interrupt always occurs. Ninth bit can be used as parity bit X RX9 = 0 OR SYNC = 1 Don't care Bit 2 - FERR Framing Error bit Value Description 1 Unread byte in 28.6.5 RCxREG has a framing error 0 Unread byte in 28.6.5 RCxREG does not have a framing error (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 559 PIC18F26/45/46Q10 (EUSART) Enhanced Universal Synchronous Asyn... Bit 1 - OERR Overrun Error bit Value Description 1 Overrun error (can be cleared by clearing either SPEN or CREN bit) 0 No overrun error Bit 0 - RX9D Ninth bit of Received Data This can be address/data bit or a parity bit which is determined by user firmware. (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 560 PIC18F26/45/46Q10 (EUSART) Enhanced Universal Synchronous Asyn... 28.6.2 TXxSTA Name: Address: TXxSTA 0xF9D,0xE99 Transmit Status and Control Register Bit Access Reset 7 6 5 4 3 2 1 0 CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D R/W R/W R/W R/W R/W R/W RO R/W 0 0 0 0 0 0 1 0 Bit 7 - CSRC Clock Source Select bit Value Condition Description 1 SYNC= 1 Master mode (clock generated internally from BRG) 0 SYNC= 1 Slave mode (clock from external source) X SYNC= 0 Don't care Bit 6 - TX9 9-bit Transmit Enable bit Value Description 1 Selects 9-bit transmission 0 Selects 8-bit transmission Bit 5 - TXEN Transmit Enable bit Enables transmitter(1) Value Description 1 Transmit enabled 0 Transmit disabled Bit 4 - SYNC EUSART Mode Select bit Value Description 1 Synchronous mode 0 Asynchronous mode Bit 3 - SENDB Send Break Character bit Value Condition Description 1 SYNC= 0 Send Sync Break on next transmission (cleared by hardware upon completion) 0 SYNC= 0 Sync Break transmission disabled or completed X SYNC= 1 Don't care Bit 2 - BRGH High Baud Rate Select bit Value Condition Description 1 SYNC= 0 High speed, if BRG16 = 1, baud rate is baudclk/4; else baudclk/16 0 SYNC= 0 Low speed X SYNC= 1 Don't care Bit 1 - TRMT Transmit Shift Register (TSR) Status bit (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 561 PIC18F26/45/46Q10 (EUSART) Enhanced Universal Synchronous Asyn... Value 1 0 Description TSR is empty TSR is not empty Bit 0 - TX9D Ninth bit of Transmit Data Can be address/data bit or a parity bit. Note: 1. SREN and CREN bits override TXEN in Sync mode. (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 562 PIC18F26/45/46Q10 (EUSART) Enhanced Universal Synchronous Asyn... 28.6.3 BAUDxCON Name: Address: BAUDxCON 0xF9E,0xE9A Baud Rate Control Register Bit Access Reset 7 6 4 3 1 0 ABDOVF RCIDL 5 SCKP BRG16 2 WUE ABDEN RO RO RW RW RW RW 0 0 0 0 0 0 Bit 7 - ABDOVF Auto-Baud Detect Overflow bit Value Condition Description 1 SYNC= 0 Auto-baud timer overflowed 0 SYNC= 0 Auto-baud timer did not overflow X SYNC= 1 Don't care Bit 6 - RCIDL Receive Idle Flag bit Value Condition Description 1 SYNC= 0 Receiver is Idle 0 SYNC= 0 Start bit has been received and the receiver is receiving X SYNC= 1 Don't care Bit 4 - SCKP Synchronous Clock Polarity Select bit Value Condition Description 1 SYNC= 0 Idle state for transmit (TX) is a low level (transmit data inverted) 0 SYNC= 0 Idle state for transmit (TX) is a high level (transmit data is non-inverted) 1 SYNC= 1 Data is clocked on rising edge of the clock 0 SYNC= 1 Data is clocked on falling edge of the clock Bit 3 - BRG16 16-bit Baud Rate Generator Select bit Value Description 1 16-bit Baud Rate Generator is used 0 8-bit Baud Rate Generator is used Bit 1 - WUE Wake-up Enable bit Value Condition Description 1 SYNC= 0 Receiver is waiting for a falling edge. Upon falling edge no character will be received and flag RCxIF will be set. WUE will automatically clear after RCxIF is set. 0 SYNC= 0 Receiver is operating normally X SYNC= 1 Don't care Bit 0 - ABDEN Auto-Baud Detect Enable bit Value Condition Description 1 SYNC= 0 Auto-Baud Detect mode is enabled (clears when auto-baud is complete) 0 SYNC= 0 Auto-Baud Detect is complete or mode is disabled (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 563 PIC18F26/45/46Q10 (EUSART) Enhanced Universal Synchronous Asyn... Value X Condition SYNC= 1 Description Don't care (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 564 PIC18F26/45/46Q10 (EUSART) Enhanced Universal Synchronous Asyn... 28.6.4 SPxBRG Name: Address: SPxBRG 0xF9A,0xE96 Baud Rate Determination Register Bit 15 14 13 12 11 10 9 8 SPBRGH[7:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 SPBRGL[7:0] Access Reset Bits 15:8 - SPBRGH[7:0] Baud Rate High Byte Register Bits 7:0 - SPBRGL[7:0] Baud Rate Low Byte Register (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 565 PIC18F26/45/46Q10 (EUSART) Enhanced Universal Synchronous Asyn... 28.6.5 RCxREG Name: Address: RCxREG 0xF98,0xE94 Receive Data Register Bit 7 6 5 4 3 2 1 0 RCREG[7:0] Access Reset RO RO RO RO RO RO RO RO 0 0 0 0 0 0 0 0 Bits 7:0 - RCREG[7:0] Receive data (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 566 PIC18F26/45/46Q10 (EUSART) Enhanced Universal Synchronous Asyn... 28.6.6 TXxREG Name: Address: TXxREG 0xF99,0xE95 Transmit Data Register Bit 7 6 5 4 3 2 1 0 TXREG[7:0] Access Reset R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Bits 7:0 - TXREG[7:0] Transmit Data (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 567 PIC18F26/45/46Q10 (FVR) Fixed Voltage Reference 29. (FVR) Fixed Voltage Reference The Fixed Voltage Reference (FVR) is a stable voltage reference, independent of VDD, with the following selectable output levels: * 1.024V * 2.048V * 4.096V The output of the FVR can be configured to supply a reference voltage to the following: * * * * ADC input channel ADC positive reference Comparator input Digital-to-Analog Converter (DAC) The FVR can be enabled by setting the FVREN bit of the FVRCON register. Important: Fixed Voltage Reference output cannot exceed VDD. 29.1 Independent Gain Amplifiers The output of the FVR, which is connected to the ADC, Comparators, and DAC, is routed through two independent programmable gain amplifiers. Each amplifier can be programmed for a gain of 1x, 2x or 4x, to produce the three possible voltage levels. The ADFVR<1:0> bits of the FVRCON register are used to enable and configure the gain amplifier settings for the reference supplied to the ADC module. Reference the ADC chapter for additional information. The CDAFVR<1:0> bits of the FVRCON register are used to enable and configure the gain amplifier settings for the reference supplied to the DAC and comparator module. Related Links 32. (ADC2) Analog-to-Digital Converter with Computation Module 33. (CMP) Comparator Module 31. (DAC) 5-Bit Digital-to-Analog Converter Module 29.2 FVR Stabilization Period When the Fixed Voltage Reference module is enabled, it requires time for the reference and amplifier circuits to stabilize. Once the circuits stabilize and are ready for use, the FVRRDY bit of the FVRCON register will be set. (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 568 Filename: Title: Last Edit: First Used: Note: 10-000053C.vsd VOLTAGE REFERENCE BLOCK DIAGRAM (ADC, Comp and DAC) 12/9/2013 PIC16F1613 (LECQ) Any peripheral requiring the Fixed Reference (See Table 13-1) PIC18F26/45/46Q10 (FVR) Fixed Voltage Reference Figure 29-1. Voltage Reference Block Diagram Rev. 10-000 053C 12/9/201 3 ADFVR<1:0> CDAFVR<1:0> 2 1x 2x 4x FVR_buffer1 (To ADC Module) 1x 2x 4x FVR_buffer2 (To Comparators and DAC) 2 FVREN Note 1 + _ FVRRDY Note: 1. Any peripheral requiring the FVR (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 569 PIC18F26/45/46Q10 (FVR) Fixed Voltage Reference 29.3 Register Summary - FVR Address Name Bit Pos. 0x0F2C FVRCON 7:0 29.4 FVREN FVRRDY TSEN TSRNG CDAFVR[1:0] ADFVR[1:0] Register Definitions: FVR Control (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 570 PIC18F26/45/46Q10 (FVR) Fixed Voltage Reference 29.4.1 FVRCON Name: Address: FVRCON 0xF2C Fixed Voltage Reference Control Register Bit Access Reset 7 6 5 4 FVREN FVRRDY TSEN TSRNG 3 2 1 R/W R R/W R/W R/W R/W R/W R/W 0 q 0 0 0 0 0 0 CDAFVR[1:0] 0 ADFVR[1:0] Bit 7 - FVREN Fixed Voltage Reference Enable bit Value Description 1 Fixed Voltage Reference is enabled 0 Fixed Voltage Reference is disabled Bit 6 - FVRRDY Fixed Voltage Reference Ready Flag bit Value Description 1 Fixed Voltage Reference output is ready for use 0 Fixed Voltage Reference output is not ready or not enabled Bit 5 - TSEN Temperature Indicator Enable bit(2) Value Description 1 Temperature Indicator is enabled 0 Temperature Indicator is disabled Bit 4 - TSRNG Temperature Indicator Range Selection bit(2) Value Description 1 VOUT = VDD - 4Vt (High Range) 0 VOUT = VDD - 2Vt (Low Range) Bits 3:2 - CDAFVR[1:0] Comparator FVR Buffer Gain Selection bits Value Description 11 Comparator FVR Buffer Gain is 4x, (4.096V)(1) 10 Comparator FVR Buffer Gain is 2x, (2.048V)(1) 01 Comparator FVR Buffer Gain is 1x, (1.024V) 00 Comparator FVR Buffer is off Bits 1:0 - ADFVR[1:0] ADC FVR Buffer Gain Selection bit Value Description 11 ADC FVR Buffer Gain is 4x, (4.096V)(1) 10 ADC FVR Buffer Gain is 2x, (2.048V)(1) 01 ADC FVR Buffer Gain is 1x, (1.024V) 00 ADC FVR Buffer is off (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 571 PIC18F26/45/46Q10 (FVR) Fixed Voltage Reference Note: 1. Fixed Voltage Reference output cannot exceed VDD. 2. See Temperature Indicator Module section for additional information. Related Links 30. Temperature Indicator Module (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 572 PIC18F26/45/46Q10 Temperature Indicator Module 30. Temperature Indicator Module This family of devices is equipped with a temperature circuit designed to measure the operating temperature of the silicon die. The circuit's range of operating temperature falls between -40C and +85C. The output is a voltage that is proportional to the device temperature. The output of the temperature indicator is internally connected to the device ADC. The circuit may be used as a temperature threshold detector or a more accurate temperature indicator, depending on the level of calibration performed. A one-point calibration allows the circuit to indicate a temperature closely surrounding that point. A two-point calibration allows the circuit to sense the entire range of temperature more accurately. Refer to Application Note AN1333, "Use and Calibration of the Internal Temperature Indicator" (DS00001333) for more details regarding the calibration process. 30.1 Circuit Operation Figure 30-2 shows a simplified block diagram of the temperature circuit. The proportional voltage output is achieved by measuring the forward voltage drop across multiple silicon junctions. The following equation describes the output characteristics of the temperature indicator. Figure 30-1. VOUT Ranges : = - 4 : = - 2 The temperature sense circuit is integrated with the Fixed Voltage Reference (FVR) module. See "Fixed Voltage Reference (FVR)" chapter for more information. The circuit is enabled by setting the TSEN bit of the FVRCON register. When disabled, the circuit draws no current. The circuit operates in either high or low range. The high range, selected by setting the TSRNG bit of the FVRCON register, provides a wider output voltage. This provides more resolution over the temperature range, but may be less consistent from part to part. This range requires a higher bias voltage to operate and thus, a higher VDD is needed. The low range is selected by clearing the TSRNG bit of the FVRCON register. The low range generates a lower voltage drop and thus, a lower bias voltage is needed to operate the circuit. The low range is provided for low voltage operation. (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 573 PIC18F26/45/46Q10 Temperature Indicator Module Figure 30-2. Temperature Circuit Diagram Rev. 10-000069A 7/31/2013 VDD TSEN TSRNG VOUT Temp. Indicator To ADC Related Links 29. (FVR) Fixed Voltage Reference 30.2 Minimum Operating VDD When the temperature circuit is operated in low range, the device may be operated at any operating voltage that is within specifications. When the temperature circuit is operated in high range, the device operating voltage, VDD, must be high enough to ensure that the temperature circuit is correctly biased. Table 30-1 shows the recommended minimum VDD vs. range setting. Table 30-1. Recommended VDD vs. Range 30.3 Min. VDD, TSRNG = 1 Min. VDD, TSRNG = 0 3.6V 1.8V Temperature Output The output of the circuit is measured using the internal Analog-to-Digital Converter. A channel is reserved for the temperature circuit output. Refer to "Analog-to-Digital Converter with Computation (ADC2) Module" chapter for detailed information. Related Links 32. (ADC2) Analog-to-Digital Converter with Computation Module (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 574 PIC18F26/45/46Q10 Temperature Indicator Module 30.4 ADC Acquisition Time To ensure accurate temperature measurements, the user must wait at least 200 s after the ADC input multiplexer is connected to the temperature indicator output before the conversion is performed. In addition, the user must wait 200 s between consecutive conversions of the temperature indicator output. (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 575 PIC18F26/45/46Q10 (DAC) 5-Bit Digital-to-Analog Converter Modu... 31. (DAC) 5-Bit Digital-to-Analog Converter Module The Digital-to-Analog Converter supplies a variable voltage reference, ratiometric with the input source, with 32 selectable output levels. The positive input source (VSOURCE+) of the DAC can be connected to: * FVR Buffer * External VREF+ pin * VDD supply voltage The negative input source (VSOURCE-) of the DAC can be connected to: * External VREF- pin * VSS The output of the DAC (DACx_output) can be selected as a reference voltage to the following: * * * * Comparator positive input ADC input channel DACxOUT1 pin DACxOUT2 pin The Digital-to-Analog Converter (DAC) can be enabled by setting the EN bit. (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 576 Filename: Title: Last Edit: First Used: Note 1: PIC18F26/45/46Q10 10-000026F.vsd 5bit_DAC Block Diagram 8/7/2015 PIC16(L)F1508/9 (LECD) The unbuffered DACx_output is provided on the DACxOUT pin(s). (DAC) 5-Bit Digital-to-Analog Converter Modu... Figure 31-1. Digital-to-Analog Converter Block Diagram Rev. 10-000026F 8/7/2015 Reserved 11 FVR Buffer 10 VREF+ VSOURCE+ 5 R 01 AVDD DACR<4:0> 00 R DACPSS R 32-to-1 MUX R 32 Steps DACEN DACx_output To Peripherals R DACxOUT1(1) R DACOE1 R DACxOUT2(1) VREF- 1 AVSS DACOE2 VSOURCE- 0 DACNSS Note: 1. The unbuffered DACx_output is provided on the DACxOUT pin(s). 31.1 Output Voltage Selection The DAC has 32 voltage level ranges. The 32 levels are set with the DAC1R bits. The DAC output voltage can be determined by using the following equation. Figure 31-2. DAC Output Voltage When EN = 1: _ = + - - 4: 0 25 + - Note: See the DAC1CON0 register for the available VSOURCE+ and VSOURCE- selections. (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 577 PIC18F26/45/46Q10 (DAC) 5-Bit Digital-to-Analog Converter Modu... 31.2 Ratiometric Output Level The DAC output value is derived using a resistor ladder with each end of the ladder tied to a positive and negative voltage reference input source. If the voltage of either input source fluctuates, a similar fluctuation will result in the DAC output value. The value of the individual resistors within the ladder can be found in the "5-Bit DAC Specifications" table from the "Electrical Specifications" chapter. Related Links 39.4.10 5-Bit DAC Specifications 31.3 DAC Voltage Reference Output The unbuffered DAC voltage can be output to the DACxOUTn pin(s) by setting the respective OEn bit(s). Selecting the DAC reference voltage for output on either DACxOUTn pin automatically overrides the digital output buffer, the weak pull-up and digital input threshold detector functions of that pin. Reading the DACxOUTn pin when it has been configured for DAC reference voltage output will always return a `0'. Important: The unbuffered DAC output (DACxOUTn) is not intended to drive an external load. 31.4 Operation During Sleep When the device wakes up from Sleep through an interrupt or a Windowed Watchdog Timer Time-out, the contents of the DACxCON0 register are not affected. To minimize current consumption in Sleep mode, the voltage reference should be disabled. 31.5 Effects of a Reset A device Reset affects the following: * DACx is disabled. * DACx output voltage is removed from the DACxOUTn pin(s). * The DAC1R range select bits are cleared. (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 578 PIC18F26/45/46Q10 (DAC) 5-Bit Digital-to-Analog Converter Modu... 31.6 Register Summary - DAC Control Address Name Bit Pos. 0x0F2E DAC1CON0 7:0 0x0F2F DAC1CON1 7:0 31.7 EN OE1 OE2 PSS[1:0] NSS DAC1R[4:0] Register Definitions: DAC Control Long bit name prefixes for the DAC are shown in the table below. Refer to the "Long Bit Names Section" for more information. Table 31-1. DAC Long Bit Name Prefixes Peripheral Bit Name Prefix DAC DAC Related Links 1.4.2.2 Long Bit Names (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 579 PIC18F26/45/46Q10 (DAC) 5-Bit Digital-to-Analog Converter Modu... 31.7.1 DAC1CON0 Name: Address: DAC1CON0 0xF2E DAC Control Register Bit Access Reset 5 4 EN 7 OE1 OE2 R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 Bit 7 - EN Value 1 0 6 3 2 PSS[1:0] 1 0 NSS DAC Enable bit Description DAC is enabled DAC is disabled Bit 5 - OE1 DAC Voltage Output Enable bit Value Description 1 DAC voltage level is output on the DAC1OUT1 pin 0 DAC voltage level is disconnected from the DAC1OUT1 pin Bit 4 - OE2 DAC Voltage Output Enable bit Value Description 1 DAC voltage level is output on the DAC1OUT2 pin 0 DAC voltage level is disconnected from the DAC1OUT2 pin Bits 3:2 - PSS[1:0] DAC Positive Source Select bit Value Description 11 Reserved 10 FVR buffer 01 VREF+ 00 AVDD Bit 0 - NSS DAC Negative Source Select bit Value Description 1 VREF0 AVSS (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 580 PIC18F26/45/46Q10 (DAC) 5-Bit Digital-to-Analog Converter Modu... 31.7.2 DAC1CON1 Name: Address: DAC1CON1 0xF2F DAC Data Register Bit 7 6 5 4 3 2 1 0 DAC1R[4:0] Access Reset R/W R/W R/W R/W R/W 0 0 0 0 0 Bits 4:0 - DAC1R[4:0] Data Input Register for DAC bits (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 581 PIC18F26/45/46Q10 (ADC2) Analog-to-Digital Converter with Comp... 32. (ADC2) Analog-to-Digital Converter with Computation Module The Analog-to-Digital Converter with Computation (ADC2) allows conversion of an analog input signal to a 10-bit binary representation of that signal. This device uses analog inputs that are multiplexed into a single Sample-and-Hold circuit. The output of the Sample-and-Hold is connected to the input of the converter. The converter generates a 10-bit binary result via successive approximation and stores the conversion result into the ADC result registers (32.7.15 ADRES). Additionally, the following features are provided within the ADC module: * 8-bit Acquisition Timer * Hardware Capacitive Voltage Divider (CVD) support: - 8-bit precharge timer - Adjustable Sample-and-Hold capacitor array - Guard ring digital output drive * Automatic Repeat and Sequencing: - Automated double sample conversion for CVD - Two sets of Result registers (Result and Previous Result) - Auto-conversion trigger - Internal retrigger * Computation Features: - Averaging and low-pass filter functions - Reference comparison - 2-level threshold comparison - Selectable interrupts Figure 32-1 shows the block diagram of the ADC. The ADC voltage reference is software selectable to be either internally generated or externally supplied. The ADC can generate an interrupt upon completion of a conversion and upon threshold comparison. These interrupts can be used to wake-up the device from Sleep. (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 582 PIC18F26/45/46Q10 Filename: Title: Last Edit: First Used: 10-000034C.vsd 10-Bit ADC Block Diagram 5/10/2016 2PIC16(L)F188X5 (MFAF) (ADC2) Analog-to-Digital Converter with Comp... Figure 32-1. ADC Block Diagram ADPREF<1:0> VREF+ pin FVR_buffer1 11 Positive Reference Select 10 Reserved Rev. 10-000034C 5/10/2016 01 00 ADNREF VDD VREF- pin 1 0 External Channel Inputs ANa Vref- . . . ANz Vref+ ADC_clk sampled input VSS Internal Channel Inputs ADCS<2:0> VSS AN0 ADC Clock Select FOSC/n Fosc Divider FRC FOSC FRC Temp Indicator DACx_output ADC CLOCK SOURCE ADC Sample Circuit FVR_buffer1 CHS<x:0> ADFM set bit ADIF Write to bit GO/DONE 10 complete Q1 10-bit Result GO/DONE Q4 16 start Q2 Enable ADRESH ADRESL To Computation module Trigger Select TRIGSEL<x:0> ADON . . . VSS Trigger Sources AUTO CONVERSION TRIGGER 32.1 ADC Configuration When configuring and using the ADC the following functions must be considered: * * * * * * * * Port Configuration Channel Selection ADC Voltage Reference Selection ADC Conversion Clock Source Interrupt Control Result Formatting Conversion Trigger Selection ADC Acquisition Time (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 583 PIC18F26/45/46Q10 (ADC2) Analog-to-Digital Converter with Comp... * * * * 32.1.1 ADC Precharge Time Additional Sample-and-Hold Capacitor Single/Double Sample Conversion Guard Ring Outputs Port Configuration The ADC can be used to convert both analog and digital signals. When converting analog signals, the I/O pin should be configured for analog by setting the associated TRIS and ANSEL bits. Refer to the "I/O Ports" section for more information. Important: Analog voltages on any pin that is defined as a digital input may cause the input buffer to conduct excess current. Related Links 15. I/O Ports 32.1.2 Channel Selection The 32.7.8 ADPCH register determines which channel is connected to the Sample-and-Hold circuit. There are several channel selections available as shown in the following selection table: Table 32-1. ADC Positive Input Channel Selections ADPCH ADC Positive Channel Input 111111 Fixed Voltage Reference (FVR)(2) 111110 DAC1 output(1) 111101 Temperature Indicator(3) 111100 AVSS (Analog Ground) 100011-111011 Reserved. No channel connected. 100010 RE2/ANE2(1) 100001 RE1/ANE1(1) 100000 RE0/ANE0(1) 011111 RD7/AND7(1) 011110 RD6/AND6(1) 011101 RD5/AND5(1) 011100 RD4/AND4(1) 011011 RD3/AND3(1) 011010 RD2/AND2(1) 011001 RD1/AND1(1) 011000 RD0/AND0(1) (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 584 PIC18F26/45/46Q10 (ADC2) Analog-to-Digital Converter with Comp... ...........continued ADPCH ADC Positive Channel Input 010111 RC7/ANC7 010110 RC6/ANC6 010101 RC5/ ANC5 010100 RC4/ ANC4 010011 RC3/ANC3 010010 RC2/ANC2 010001 RC1/ ANC1 010000 RC0/ANC0 001111 RB7/ANB7 001110 RB6/ANB6 001101 RB5/ANB5 001100 RB4/ ANB4 001011 RB3/ANB3 001010 RB2/ ANB2 001001 RB1/ ANB1 001000 RB0/ANB0 000111 RA7/ANA7 000110 RA6/ANA6 000101 RA5/ANA5 000100 RA4/ ANA4 000011 RA3/ ANA3 000010 RA2/ ANA2 000001 RA1/ ANA1 000000 RA0/ANA0 Note: 1. 40/44-pin devices only. When changing channels, a delay is required before starting the next conversion. Refer to Section "ADC Operation" for more information. (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 585 PIC18F26/45/46Q10 (ADC2) Analog-to-Digital Converter with Comp... Important: It is recommended to discharge the Sample-and-Hold capacitor when switching between ADC channels by starting a conversion on a channel connected to VSS and terminating the conversion after the acquisition time has elapsed. If the ADC does not have a dedicated VSS input channel, the VSS selection (DAC1R<4:0> = b'00000') through the DAC output channel can be used. If the DAC is in use, a free input channel can be connected to VSS, and can be used in place of the DAC. 32.1.3 ADC Voltage Reference The ADPREF bits provide control of the positive voltage reference. The positive voltage reference can be: * * * * * VREF+ pin VDD FVR 1.024V FVR 2.048V FVR 4.096V The ADNREF bit provides control of the negative voltage reference. The negative voltage reference can be: * VREF- pin * VSS 32.1.4 Conversion Clock The conversion clock source is software selected with the ADCS bit. When ADCS = 1 the ADC clock source is an internal fixed-frequency clock referred to as FRC. When ADCS = 0 the ADC clock frequencies are derived from FOSC. The 32.7.6 ADCLK register selects one of 64 possible clock options from FOSC/2 to FOSC/128: * FOSC/2 * * * * * * FOSC/4 FOSC/6 FOSC/8 FOSC/10 ... FOSC/128 The time to complete one bit conversion is defined as the TAD. One full 10-bit conversion requires 11.5 TAD periods as shown in Figure 32-2. For correct conversion, the appropriate TAD specification must be met. Refer to the "ADC Timing Specifications" for more information. The "ADC Clock Period" table below gives examples of appropriate ADC clock selections. (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 586 PIC18F26/45/46Q10 (ADC2) Analog-to-Digital Converter with Comp... Important: 1. Except for the FRC clock source, any changes in the system clock frequency will change the ADC clock frequency, which may adversely affect the ADC result. 2. The internal control logic of the ADC runs off of the clock selected by ADCS. When the ADCS is set to `1' (ADC runs on FRC), there may be unexpected delays in operation when setting ADC control bits. Table 32-2. ADC Clock Period (TAD) Vs. Device Operating Frequencies(1,4) ADC Clock Period (TAD) Device Frequency (FOSC) ADC Clock Source ADCLK 64 MHz 32 MHz 20 MHz 16 MHz 8 MHz 4 MHz 1 MHz FOSC/2 000000 31.25 ns(2) 62.5 ns(2) 100 ns(2) 125 ns(2) 250 ns(2) 500 ns(2) 2.0 s FOSC/4 000001 62.5 ns(2) 125 ns(2) 200 ns(2) 250 ns(2) 500 ns(2) 1.0 s 4.0 s FOSC/6 000010 125 ns(2) 187.5 ns(2) 300 ns(2) 375 ns(2) 750 ns(2) 1.5 s 6.0 s FOSC/8 000011 187.5 ns(2) 250 ns(2) 400 ns(2) 500 ns(2) 1.0 s 2.0 s 8.0 s(3) ... ... ... ... ... ... ... ... ... FOSC/16 000111 250 ns(2) 500 ns(2) 800 ns(2) 1.0 s 2.0 s 4.0 s 16.0 s(3) ... ... ... ... ... ... ... ... ... FOSC/128 111111 2.0 s 4.0 s 6.4 s 8.0 s FRC ADCS=1 1.0-6.0 s 1.0-6.0 s 1.0-6.0 s 1.0-6.0 s 16.0 s(3) 32.0 s(2) 1.0-6.0 s 1.0-6.0 s 128.0 s(2) 1.0-6.0 s Note: 1. See TAD parameter in the "Electrical Specifications" section for FRC source typical TAD value. 2. These values violate the required TAD time. 3. Outside the recommended TAD time. 4. The ADC clock period (TAD) and total ADC conversion time can be minimized when the ADC clock is derived from the system clock FOSC. However, the FRC oscillator source must be used when conversions are to be performed with the device in Sleep mode. (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 587 PIC18F26/45/46Q10 (ADC2) Analog-to-Digital Converter with Comp... Figure 32-2. Analog-to-Digital Conversion TAD Cycles Precharge Time 1-255 TCY (TPRE) Acquisition/ Sharing Time 1-255 TCY (TACQ) Rev. 10-000035B 11/3/2016 Conversion Time (Traditional Timing of ADC Conversion) TCY TCY-TAD TAD1 TAD2 TAD3 TAD4 TAD5 TAD6 TAD7 TAD8 TAD9 TAD10TAD11 b9 External and Internal External and Internal Channels are Channels share charged/discharged charge If ADPRE 0 If ADACQ 0 Set GO bit b8 b7 b6 b5 b4 b3 b2 b1 b0 2 TCY Conversion starts Holding capacitor CHOLD is disconnected from analog input (typically 100ns) If ADPRE = 0 If ADACQ = 0 (Traditional Operation Start) On the following cycle: ADRESH:ADRESL is loaded, GO bit is cleared, ADIF bit is set, Related Links 39.4.8 Analog-to-Digital Converter (ADC) Conversion Timing Specifications 32.1.5 Interrupts The ADC module allows for the ability to generate an interrupt upon completion of an Analog-to-Digital Conversion. The ADC Interrupt Flag is the ADIF bit in the PIRx register. The ADC Interrupt Enable is the ADIE bit in the PIEx register. The ADIF bit must be cleared in software. Important: 1. The ADIF bit is set at the completion of every conversion, regardless of whether or not the ADC interrupt is enabled. 2. The ADC operates during Sleep only when the FRC oscillator is selected. This interrupt can be generated while the device is operating or while in Sleep. If the device is in Sleep, the interrupt will wake-up the device. Upon waking from Sleep, the next instruction following the SLEEP instruction is always executed. If the user is attempting to wake-up from Sleep and resume in-line code execution, the ADIE bit and the PEIE bit of the INTCON register must both be set and the GIE bit of the INTCON register must be cleared. If all three of these bits are set, the execution will switch to the Interrupt Service Routine. 32.1.6 Result Formatting The 10-bit ADC conversion result can be supplied in two formats, left justified or right justified. The ADFM bit controls the output format as shown in the following figure. (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 588 PIC18F26/45/46Q10 (ADC2) Analog-to-Digital Converter with Comp... Figure 32-3. 10-Bit ADC Conversion Result Format Rev. 30-000116A 5/16/2017 ADRESH (ADFM = 0) ADRESL MSB LSB bit 7 bit 0 bit 7 bit 0 Unimplemented: Read as `0' 10-bit ADC Result (ADFM = 1) MSB bit 7 LSB bit 0 Unimplemented: Read as `0' bit 7 bit 0 10-bit ADC Result 32.2 ADC Operation 32.2.1 Starting a Conversion To enable the ADC module, the ADON must be set to a `1'. A conversion may be started by any of the following: * Software setting the ADGO bit to '1' * An external trigger (source selected by 32.7.22 ADACT) * A continuous-mode retrigger (see section 32.5.8 Continuous Sampling Mode) . Important: The ADGO bit should not be set in the same instruction that turns on the ADC. Refer to 32.2.7 ADC Conversion Procedure (Basic Mode). 32.2.2 Completion of a Conversion When any individual conversion is complete, the value already in 32.7.15 ADRES is written into 32.7.16 ADPREV (if ADPSIS = 0) and the new conversion results appear in ADRES. When the conversion completes, the ADC module will: * Clear the ADGO bit (unless the ADCONT bit is set) * Set the ADIF Interrupt Flag bit * Set the ADMATH bit * Update 32.7.17 ADACC After every conversion when ADDSEN = 0, or after every other conversion when ADDSEN = 1, the following events occur: * 32.7.19 ADERR is calculated * ADTIF interrupt is set if ADERR calculation meets threshold comparison (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 589 PIC18F26/45/46Q10 (ADC2) Analog-to-Digital Converter with Comp... Important: Filter and threshold computations occur after the conversion itself is complete. As such, interrupt handlers responding to ADIF should check ADTIF before reading filter and threshold results. 32.2.3 Terminating a Conversion If a conversion must be terminated before completion, the ADGO bit can be cleared in software. The partial conversion results will be discarded and the ADRES registers will retain the value from the previous conversion. Important: A device Reset forces all registers to their Reset state. Thus, the ADC module is turned off and any pending conversion is terminated. 32.2.4 ADC Operation During Sleep The ADC module can operate during Sleep. This requires the ADC clock source to be set to the FRC option. When the FRC oscillator source is selected, the ADC waits one additional instruction before starting the conversion. This allows the SLEEP instruction to be executed, which can reduce system noise during the conversion. If the ADC interrupt is enabled, the device will wake-up from Sleep when the conversion completes. If the ADC interrupt is disabled, the ADC module is turned off after the conversion completes, although the ADON bit remains set. 32.2.5 External Trigger During Sleep If the external trigger is received during Sleep while the ADC clock source is set to the FRC, the ADC module will perform the conversion and set the ADIF bit upon completion. If an external trigger is received when the ADC clock source is something other than FRC, the trigger will be recorded, but the conversion will not begin until the device exits Sleep. 32.2.6 Auto-Conversion Trigger The auto-conversion trigger allows periodic ADC measurements without software intervention. When a rising edge of the selected source occurs, the ADGO bit is set by hardware. The auto-conversion trigger source is selected with the ADACT bits. Using the auto-conversion trigger does not assure proper ADC timing. It is the user's responsibility to ensure that the ADC timing requirements are met. See the following table for auto-conversion sources. Table 32-3. ADC Auto-Conversion Trigger Sources ADACT Auto-conversioin Trigger Source 11111 Software write to ADPCH 11110 Reserved, do not use 11101 Software read of ADRESH 11100 Software read of ADERRH 11000 to 11011 Reserved, do not use (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 590 PIC18F26/45/46Q10 (ADC2) Analog-to-Digital Converter with Comp... ...........continued 32.2.7 ADACT Auto-conversioin Trigger Source 10111 CLC8_out 10110 CLC7_out 10101 CLC6_out 10100 CLC5_out 10011 CLC4_out 10010 CLC3_out 10001 CLC2_out 10000 CLC1_out 01111 Interrupt-on-change Interrupt Flag 01110 C2_out 01101 C1_out 01100 PWM4_out 01011 PWM3_out 01010 CCP2_trigger 01001 CCP1_trigger 01000 TMR6_postscaled 00111 TMR5_overflow 00110 TMR4_postscaled 00101 TMR3_overflow 00100 TMR2_postscaled 00011 TMR1_overflow 00010 TMR0_overflow 00001 Pin selected by ADACTPPS 00000 External Trigger Disabled ADC Conversion Procedure (Basic Mode) This is an example procedure for using the ADC to perform an Analog-to-Digital Conversion: 1. 2. Configure Port: 1.1. Disable pin output driver (Refer to the TRISx register) 1.2. Configure pin as analog (Refer to the ANSELx register) Configure the ADC module: 2.1. Select ADC conversion clock 2.2. Configure voltage reference 2.3. Select ADC input channel (precharge+acquisition) (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 591 PIC18F26/45/46Q10 (ADC2) Analog-to-Digital Converter with Comp... 3. 4. 5. 6. 7. 8. 2.4. Turn on ADC module Configure ADC interrupt (optional): 3.1. Clear ADC interrupt flag 3.2. Enable ADC interrupt 3.3. Enable peripheral interrupt (PEIE bit) 3.4. Enable global interrupt (GIE bit)(1) If ADACQ = 0, software must wait the required acquisition time(2). Start conversion by setting the ADGO bit. Wait for ADC conversion to complete by one of the following: 6.1. Polling the ADGO bit 6.2. Waiting for the ADC interrupt (interrupts enabled) Read ADC Result. Clear the ADC interrupt flag (required if interrupt is enabled). Important: 1. With global interrupts disabled, the device will wake from Sleep but will not enter an Interrupt Service Routine. 2. Refer to 32.3 ADC Acquisition Requirements. Example 32-1. ADC Conversion (assembly) ; This code block configures the ADC for polling, Vdd and Vss references, ; FRC oscillator, and AN0 input. ; Conversion start & polling for completion are included. BANKSEL clrf clrf clrf clrf clrf clrf clrf clrf clrf movlw movwf BANKSEL bsf BANKSEL bsf call BANKSEL bsf btfsc goto BANKSEL movf movwf movf movwf ADCON1 ADCON1 ADCON2 ADCON3 ADREF ADPCH ADACQ ADCAP ADRPT ADACT B'10010100' ADCON0 TRISA TRISA,0 ANSEL ANSEL,0 SampleTime ADCON0 ADCON0,ADGO ADCON0,ADGO $-2 ADRESH ADRESH,W RESULTHI ADRESL,W RESULTLO ; ; ; ; ; ; ; ; ; ; Legacy mode, no filtering, ADRES->ADPREV no math functions Vref = Vdd & Vss select RA0/AN0 software controlled acquisition time default S&H capacitance no repeat measurements auto-conversion disabled ADC On, right-justified, FRC clock ; ; Set RA0 to input ; ; Set RA0 to analog ; Acquisiton delay ; ; ; ; ; ; ; ; Start conversion Is conversion done? No, test again Read upper 2 store in GPR Read lower 8 Store in GPR bits space bits space Example 32-2. ADC Conversion (C) /*This code block configures the ADC (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 592 PIC18F26/45/46Q10 (ADC2) Analog-to-Digital Converter with Comp... for polling, VDD and VSS references, ADCRC oscillator and AN0 input. Conversion start & polling for completion are included. */ void main() { //System Initialize initializeSystem(); //Setup ADC ADCON0bits.FM = 1; //right justify ADCON0bits.CS = 1; //FRC Clock ADPCH = 0x00; //RA0 is Analog channel TRISAbits.TRISA0 = 1; //Set RA0 to input ANSELAbits.ANSELA0 = 1; //Set RA0 to analog ADCON0bits.ON = 1; //Turn ADC On } 32.3 while (1) { ADCON0bits.GO = 1; while (ADCON0bits.GO); resultHigh = ADRESH; resultLow = ADRESL; } //Start conversion //Wait for conversion done //Read result //Read result ADC Acquisition Requirements For the ADC to meet its specified accuracy, the charge holding capacitor (CHOLD) must be allowed to fully charge to the input channel voltage level. The analog input model is shown in Figure 32-5. The source impedance (RS) and the internal sampling switch (RSS) impedance directly affect the time required to charge the capacitor CHOLD. The sampling switch (RSS) impedance varies over the device voltage (VDD), refer to Figure 32-5. The maximum recommended impedance for analog sources is 10 k. As the source impedance is decreased, the acquisition time may be decreased. After the analog input channel is selected (or changed), an ADC acquisition must be completed before the conversion can be started. To calculate the minimum acquisition time, Figure 32-4 may be used. This equation assumes that 1/2 LSb error is used (1024 steps for the ADC). The 1/2 LSb error is the maximum error allowed for the ADC to meet its specified resolution. Figure 32-4. Acquisition Time Example Assumptions: Temperature = 50C; External impedance = 10k; VDD = 5.0V TACQ = Amplifier Settling Time + Hold Capacitor Charging Time + Temperature Coefficient = + + = 2 + + - 25 0.05/ The value for TC can be approximated with the following equations: 1 - 1 - 1 - 2 1 +1 - - - 1 = ; [1] VCHOLD charged to within 1/2 lsb = ; [2] VCHOLD charge response to VAPPLIED = 1 - 2 Note: Where n = ADC resolution in bits (c) 2019 Microchip Technology Inc. 1 +1 - 1 ; Combining [1] and [2] Datasheet Preliminary DS40001996C-page 593 PIC18F26/45/46Q10 (ADC2) Analog-to-Digital Converter with Comp... Solving for TC: = - + + 1/2047 = - 10 1 + 7 + 10 0.0004885 = 1.37 Therefore: = 2 + 892 + 50 - 25 = 4.62 0.05/ Note: 1. The reference voltage (VREF) has no effect on the equation, since it cancels itself out. 2. The charge holding capacitor (CHOLD) is not discharged after each conversion. 3. The maximum recommended impedance for analog sources is 10 k. This is required to meet the pin leakage specification. Figure 32-5. Analog Input Model Rev. 30-000114A 5/16/2017 Rs VA Analog Input pin VDD VT 0.6V CPIN 5 pF VT 0.6V RIC 1k Sampling Switch SS Rss I LEAKAGE(1) CHOLD = 10 pF Ref- Legend: CHOLD CPIN = Sample/Hold Capacitance = Input Capacitance I LEAKAGE = Leakage current at the pin due to various junctions RIC = Interconnect Resistance R SS = Resistance of Sampling Switch SS = Sampling Switch VT (c) 2019 Microchip Technology Inc. 6V 5V VDD 4V 3V 2V RSS 5 6 7 8 9 10 11 Sampling Switch (k) = Threshold Voltage Datasheet Preliminary DS40001996C-page 594 PIC18F26/45/46Q10 (ADC2) Analog-to-Digital Converter with Comp... Figure 32-6. ADC Transfer Function Rev. 30-000115A 5/16/2017 Full-Scale Range 3FFh 3FEh ADC Output Code 3FDh 3FCh 3FBh 03h 02h 01h 00h Analog Input Voltage 0.5 LSB REF- 32.4 1.5 LSB Zero-Scale Transition Full-Scale Transition REF+ Capacitive Voltage Divider (CVD) Features The ADC module contains several features that allow the user to perform a relative capacitance measurement on any ADC channel using the internal ADC Sample-and-Hold capacitance as a reference. This relative capacitance measurement can be used to implement capacitive touch or proximity sensing applications. The following figure shows the basic block diagram of the CVD portion of the ADC module. (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 595 PIC18F26/45/46Q10 (ADC2) Analog-to-Digital Converter with Comp... Figure 32-7. Hardware Capacitive Voltage Divider Block Diagram Rev. 10-000322B 10/4/2017 VDD VDD ADPPOL & Precharge ADPPOL & Precharge Precharge ANx ADC ADPPOL & Precharge ADPPOL & Precharge ANx Multiplexer ADCAP Additional Sample Capacitors 32.4.1 CVD Operation A CVD operation begins with the ADC's internal Sample-and-Hold capacitor (CHOLD) being disconnected from the path which connects it to the external capacitive sensor node. While disconnected, CHOLD is precharged to VDD or VSS the sensor node is also charged to VSS or VDD, respectively to the level opposite that of CHOLD. When the precharge phase is complete, the VDD/VSS bias paths for the two nodes are shut off and the paths between CHOLD and the external sensor node is reconnected, at which time the acquisition phase of the CVD operation begins. During acquisition, a capacitive voltage divider is formed between the precharged CHOLD and sensor nodes, which results in a final voltage level setting on CHOLD which is determined by the capacitances and precharge levels of the two nodes. After acquisition, the ADC converts the voltage level on CHOLD. This process is then repeated with the selected precharge levels inverted for both the CHOLD and the sensor nodes. The waveform for two CVD measurements, which is known as differential CVD measurement, is shown in the following figure. (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 596 PIC18F26/45/46Q10 (ADC2) Analog-to-Digital Converter with Comp... Figure 32-8. Differential CVD Measurement Waveform Rev. 10-000335A 10/2/2017 Precharge Acquire Convert Precharge Acquire Convert External Capacitive Sensor VSS ADC Sample-and-Hold Capacitor Voltage VDD Second Sample First Sample Time 32.4.2 Precharge Control The Precharge stage is an optional period of time that brings the external channel and internal Sampleand-Hold capacitor to known voltage levels. Precharge is enabled by writing a nonzero value to the ADPRE register. This stage is initiated when an ADC conversion begins, either from setting the ADGO bit, a Special Event Trigger, or a conversion restart from the computation functionality. If the ADPRE register is cleared when an ADC conversion begins, this stage is skipped. During the precharge time, CHOLD is disconnected from the outer portion of the sample path that leads to the external capacitive sensor and is connected to either VDD or VSS, depending on the value of the ADPPOL bit. At the same time, the port pin logic of the selected analog channel is overridden to drive a digital high or low out, in order to precharge the outer portion of the ADC's sample path, which includes the external sensor. The output polarity of this override is also determined by the ADPPOL bit such that the external sensor cap is charged opposite that of the internal CHOLD cap. The amount of time that this charging needs is controlled by the ADPRE register. Important: The external charging overrides the TRIS setting of the respective I/O pin. If there is a device attached to this pin, precharge should not be used. (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 597 PIC18F26/45/46Q10 (ADC2) Analog-to-Digital Converter with Comp... 32.4.3 Acquisition Control for CVD (ADPRE > 0) The Acquisition stage allows time for the voltage on the internal Sample-and-Hold capacitor to charge or discharge from the selected analog channel. This acquisition time is controlled by the ADACQ register. When ADPRE = 0, acquisition starts at the beginning of conversion. When ADPRE > 0, the acquisition stage begins when precharge ends. At the start of the acquisition stage, the port pin logic of the selected analog channel is overridden to turn off the digital high/low output drivers so they do not affect the final result of the charge averaging. Also, the selected ADC channel is connected to CHOLD. This allows charge averaging to proceed between the precharged channel and the CHOLD capacitor. Important: When ADPRE > 0 setting ADACQ to `0' will set a maximum acquisition time (256 ADC clock cycles). When precharge is disabled, setting ADACQ to `0' will disable hardware acquisition time control. 32.4.4 Guard Ring Outputs Figure 32-9 shows a typical guard ring circuit. CGUARD represents the capacitance of the guard ring trace placed on the PCB board. The user selects values for RA and RB that will create a voltage profile on CGUARD, which will match the selected acquisition channel. The purpose of the guard ring is to generate a signal in phase with the CVD sensing signal to minimize the effects of the parasitic capacitance on sensing electrodes. It also can be used as a mutual drive for mutual capacitive sensing. For more information about active guard and mutual drive, see Application Note AN1478, "mTouchTM Sensing Solution Acquisition Methods Capacitive Voltage Divider". The ADC has two guard ring drive outputs, ADGRDA and ADGRDB. These outputs can be routed through PPS controls to I/O pins (see "Peripheral Pin Select (PPS) Module" for details). The polarity of these outputs are controlled by the ADGPOL and ADIPEN bits. At the start of the first precharge stage, both outputs are set to match the ADGPOL bit. Once the acquisition stage begins, ADGRDA changes polarity, while ADGRDB remains unchanged. When performing a double sample conversion, setting the ADIPEN bit causes both guard ring outputs to transition to the opposite polarity of ADGPOL at the start of the second precharge stage, and ADGRDA toggles again for the second acquisition. For more information on the timing of the guard ring output, refer to Figure 32-9 and Figure 32-10. Figure 32-9. Guard Ring Circuit Rev. 30-000120A 5/16/2017 ADGRDA RA RB CGUARD ADGRDB (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 598 PIC18F26/45/46Q10 (ADC2) Analog-to-Digital Converter with Comp... Figure 32-10. Differential CVD with Guard Ring Output Waveform Rev. 10-000336A 10/2/2017 Precharge Acquire Convert Precharge Acquire Convert VSS Guard Ring Capacitance External Capacitive Sensor Voltage VDD Second Sample First Sample Time ADGRDA ADGRDB Figure 32-11. Hardware CVD Sequence Timing Diagram Rev. 30-000122A 5/16/2017 Precharge Time Acquisition/ Sharing Time 1-255 TINST (TPRE 1-255 TINST (TACQ) ) External and Internal External and Internal Channels share Channels are charged/discharged charge If ADPRE 0 If ADACQ 0 Set GO/DONE bit (c) 2019 Microchip Technology Inc. Conversion Time (Traditional Timing of ADC Conversion) TCY - TAD TAD1 TAD2 TAD3 TAD4 TAD5 TAD6 TAD7 TAD8 TAD9 TAD10 TAD11 b4 b1 b0 b6 b7 b2 b8 b3 b9 b5 Conversion starts Holding capacitor CHOLD is disconnected from analog input (typically 100 ns) If ADPRE = 0 If ADACQ = 0 (Traditional Operation Start) On the following cycle: AADRES0H:AADRES0L is loaded, ADIF bit is set, GO/DONE bit is cleared Datasheet Preliminary DS40001996C-page 599 PIC18F26/45/46Q10 (ADC2) Analog-to-Digital Converter with Comp... 32.4.5 Additional Sample-and-Hold Capacitance Additional capacitance can be added in parallel with the internal Sample-and-Hold capacitor (CHOLD) by using the ADCAP register. This register selects a digitally programmable capacitance that is added to the ADC conversion bus, increasing the effective internal capacitance of the Sample-and-Hold capacitor in the ADC module. This is used to improve the match between internal and external capacitance for a better sensing performance. The additional capacitance does not affect analog performance of the ADC because it is not connected during conversion. See Figure 32-12. 32.5 Computation Operation The ADC module hardware is equipped with post conversion computation features. These features provide data post-processing functions that can be operated on the ADC conversion result, including digital filtering/averaging and threshold comparison functions. Figure 32-12. Computational Features Simplified Block Diagram Rev. 10-000260B 8/4/2015 ADCALC<2:0> ADMD<2:0> ADRES ADFILT Average/ Filter 1 0 Error Calculation ADERR Set Interrupt Flag Threshold Logic ADPREV ADSTPT ADPSIS ADUTHR ADLTHR The operation of the ADC computational features is controlled by the ADMD bits. The module can be operated in one of five modes: * Basic: This is a legacy mode. In this mode, ADC conversion occurs on single (ADDSEN = 0) or double (ADDSEN = 1) samples. ADIF is set after each conversion is complete. * Accumulate: With each trigger, the ADC conversion result is added to the accumulator and ADCNT increments. ADIF is set after each conversion. ADTIF is set according to the calculation mode. * Average: With each trigger, the ADC conversion result is added to the accumulator. When the ADRPT number of samples have been accumulated, a threshold test is performed. Upon the next trigger, the accumulator is cleared. For the subsequent tests, additional ADRPT samples are required to be accumulated. * Burst Average: At the trigger, the accumulator is cleared. The ADC conversion results are then collected repetitively until ADRPT samples are accumulated and finally the threshold is tested. * Low-Pass Filter (LPF): With each trigger, the ADC conversion result is sent through a filter. When ADRPT samples have occurred, a threshold test is performed. Every trigger after that the ADC conversion result is sent through the filter and another threshold test is performed. The five modes are summarized in the following table. (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 600 (c) 2019 Microchip Technology Inc. Table 32-4. Computation Modes Register Clear Event rotatethispage90 Value after Cycle(2) Completion Threshold Operations Value at ADTIF Interrupt ADACC and ADCNT ADACC(1) ADCNT Retrigger Threshold Test Interrupt Basic 0 ADACLR = 1 Unchanged Unchanged No Every Sample If threshold=true Accumulate 1 ADACLR = 1 S1 + ADACC If (ADCNT=FF): or ADCNT, otherwise: (S2-S1) + ADCNT+1 ADACC No Every Sample If ADACC ADACC/ count threshold=true Overflow 2ADCRS Average 2 ADACLR = 1 or S1 + ADACC If (ADCNT=FF): or ADCNT, ADCNT>=ADRPT otherwise: at ADGO or (S2-S1) + ADCNT+1 retrigger ADACC No Burst Average 3 ADACLR = 1 or ADGO set or retrigger Each repetition: same as Average End with sum of all ADAOV ADFLTR ADCNT N/A N/A count If If ADACC ADACC/ count ADCNT>=ADRPT threshold=true Overflow 2ADCRS Each repetition: Repeat while If If ADACC ADACC/ ADRPT same as ADCNT<ADRPT ADCNT>=ADRPT threshold=true Overflow 2ADCRS Average End with ADCNT=ADRPT Low-pass Filter 4 ADACLR = 1 DS40001996C-page 601 S1+ADACC- If (ADCNT=FF): ADACC/ ADCNT, 2ADCRS otherwise: or ADCNT+1 (S2S1)+ADACCADACC/ 2ADCRS No If If ADACC Filtered ADCNT>=ADRPT threshold=true Overflow Value count PIC18F26/45/46Q10 samples (ADC2) Analog-to-Digital Converter with Comp... Datasheet Preliminary ADMD Mode (c) 2019 Microchip Technology Inc. ...........continued Register Clear Event rotatethispage90 Mode ADMD ADACC and ADCNT Value after Cycle(2) Completion ADACC(1) ADCNT Threshold Operations Retrigger Threshold Test Value at ADTIF Interrupt Interrupt ADAOV ADFLTR ADCNT Note: 1. S1 and S2 are abbreviations for Sample 1 and Sample 2, respectively. When ADDSEN = 0, S1 = ADRES; When ADDSEN = 1, S1 = ADPREV and S2 = ADRES. 2. When ADDSEN = 0 then Cycle means one conversion. When ADDSEN = 1 then Cycle means two conversions. PIC18F26/45/46Q10 DS40001996C-page 602 (ADC2) Analog-to-Digital Converter with Comp... Datasheet Preliminary PIC18F26/45/46Q10 (ADC2) Analog-to-Digital Converter with Comp... 32.5.1 Digital Filter/Average The digital filter/average module consists of an accumulator with data feedback options, and control logic to determine when threshold tests need to be applied. The accumulator is a 16-bit wide register that can be accessed through the 32.7.17 ADACC registers. Upon each trigger event (the ADGO bit set or external event trigger), the ADC conversion result is added to the accumulator. If the accumulated value exceeds 2(accumulator_width)-1 = 216 = 65535, the ADAOV overflow bit is set. The number of samples to be accumulated is determined by the ADRPT (A/D Repeat Setting) register. Each time a sample is added to the accumulator, the ADCNT register is incremented. Once ADRPT samples are accumulated (ADCNT = ADRPT), an accumulator clear command can be issued by the software by setting the ADACLR bit. Setting the ADACLR bit will also clear the ADAOV (Accumulator overflow) bit, as well as the ADCNT register. The ADACLR bit is cleared by the hardware when accumulator clearing action is complete. Important: When ADC is operating from FRC, five FRC clock cycles are required to execute the ADACC clearing operation. The ADCRS bits control the data shift on the accumulator result, which effectively divides the value in accumulator (32.7.17 ADACC) registers. For the Accumulate mode of the digital filter, the shift provides a simple scaling operation. For the Average/Burst Average mode, the shift bits are used to determine number of samples for averaging. For the Low-pass Filter mode, the shift is an integral part of the filter, and determines the cutoff frequency of the filter. Table 32-5 shows the -3 dB cutoff frequency in T (radians) and the highest signal attenuation obtained by this filter at nyquist frequency (T = ). Table 32-5. Low-pass Filter -3 dB Cutoff Frequency 32.5.2 ADCRS T (radians) @ -3 dB Frequency dB @ Fnyquist=1/(2T) 1 0.72 -9.5 2 0.284 -16.9 3 0.134 -23.5 4 0.065 -29.8 5 0.032 -36.0 6 0.016 -42.0 Basic Mode Basic mode (ADMD = 000) disables all additional computation features. In this mode, no accumulation occurs but threshold error comparison is performed. Double sampling, Continuous mode, and all CVD features are still available, but no features involving the digital filter/average features are used. 32.5.3 Accumulate Mode In Accumulate mode (ADMD = 001), after every conversion, the ADC result is added to the ADACC register. The ADACC register is right-shifted by the value of the ADCRS bits. This right-shifted value is copied in to the ADFLT register. The Formatting mode does not affect the right-justification of the ADACC value. Upon each sample, ADCNT is also incremented, incrementing the number of samples (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 603 PIC18F26/45/46Q10 (ADC2) Analog-to-Digital Converter with Comp... accumulated. After each sample and accumulation, the ADACC value has a threshold comparison performed on it (see 32.5.7 Threshold Comparison) and the ADTIF interrupt may trigger. 32.5.4 Average Mode In Average Mode (ADMD = 010), the ADACC registers accumulate with each ADC sample, much as in Accumulate mode, and the ADCNT register increments with each sample. The ADFLT register is also updated with the right-shifted value of the ADACC register. The value of the ADCRS bits governs the number of right shifts. However, in Average mode, the threshold comparison is performed upon ADCNT being greater than or equal to a user-defined ADRPT value. In this mode when ADRPT = 2^ADCNT, then the final accumulated value will be divided by number of samples, allowing for a threshold comparison operation on the average of all gathered samples. 32.5.5 Burst Average Mode The Burst Average mode (ADMD = 011) acts the same as the Average mode in most respects. The one way it differs is that it continuously retriggers ADC sampling until the ADCNT value is greater than or equal to ADRPT, even if Continuous Sampling mode (see 32.5.8 Continuous Sampling Mode) is not enabled. This allows for a threshold comparison on the average of a short burst of ADC samples. 32.5.6 Low-pass Filter Mode The Low-pass Filter mode (ADMD = 100) acts similarly to the Average mode in how it handles samples (accumulates samples until ADCNT value greater than or equal to ADRPT, then triggers threshold comparison), but instead of a simple average, it performs a low-pass filter operation on all of the samples, reducing the effect of high-frequency noise on the average, then performs a threshold comparison on the results. (see 32.5 Computation Operation for a more detailed description of the mathematical operation). In this mode, the ADCRS bits determine the cutoff frequency of the low-pass filter (as demonstrated by 32.5.1 Digital Filter/Average). 32.5.7 Threshold Comparison At the end of each computation: * The conversion results are latched and held stable at the end-of-conversion. * The error (32.7.19 ADERR) is calculated based on a difference calculation which is selected by the ADCALC bits. The value can be one of the following calculations (see Table 32-6 for more details): - The first derivative of single measurements - The CVD result when double-sampling is enabled - The current result vs. a setpoint - The current result vs. the filtered/average result - The first derivative of the filtered/average value - Filtered/average value vs. a setpoint * The result of the calculation (ADERR) is compared to the upper and lower thresholds, 32.7.21 ADUTH and 32.7.20 ADLTH registers, to set the ADUTHR and ADLTHR flag bits. The threshold logic is selected by ADTMD bits. The threshold trigger option can be one of the following: - Never interrupt - Error is less than lower threshold - Error is greater than or equal to lower threshold - Error is between thresholds (inclusive) - Error is outside of thresholds - Error is less than or equal to upper threshold (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 604 PIC18F26/45/46Q10 (ADC2) Analog-to-Digital Converter with Comp... - Error is greater than upper threshold - Always interrupt regardless of threshold test results - If the threshold condition is met, the threshold interrupt flag ADTIF is set. Note: 1. The threshold tests are signed operations. 2. If ADAOV is set, a threshold interrupt is signaled. It is good practice for threshold interrupt handlers to verify the validity of the threshold by checking ADAOV. Table 32-6. ADC Error Calculation Mode ADERR ADCALC ADDSEN = 0 SingleSample Mode ADDSEN = 1 CVD Double-Sample Mode(1) Application 111 ADFLTR ADFLTR Filtered results above or below the threshold. 110 ADRES ADRES Measurement above or below the threshold 101 ADLFTR-ADSTPT ADFLTR-ADSTPT Average/filtered value vs. setpoint 100 ADPREV-ADFLTR ADPREV-ADFLTR First derivative of filtered value(3) (negative) 011 Reserved Reserved 010 ADRES-ADFLTR (ADRES-ADPREV)ADFLTR Actual result vs. averaged/filtered value 001 ADRES-ADSTPT (ADRES-ADPREV)ADSTPT Actual result vs.setpoint 000 ADRES-ADPREV ADRES-ADPREV First derivative of single measurement(2) Reserved Actual CVD result(1,2) Note: 1. When ADDSEN=1, ADERR is computed only after every second sample. 2. When ADPSIS = 0. 3. 32.5.8 When ADPSIS = 1. Continuous Sampling Mode Setting the ADCONT bit register automatically retriggers a new conversion cycle after updating the ADACC register. That means the ADGO bit is set to generate automatic retriggering, until the device Reset occurs or the ADSOI A/D Stop-on-interrupt bit is set (correct logic). 32.5.9 Double Sample Conversion Double sampling is enabled by setting the ADDSEN bit. When this bit is set, two conversions are required before the module will calculate threshold error. Each conversion must still be triggered separately when ADCONT = 0. The first conversion will set the ADMATH bit and update ADACC, but will not calculate ADERR or trigger ADTIF. When the second conversion completes, the first value is transferred to (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 605 PIC18F26/45/46Q10 (ADC2) Analog-to-Digital Converter with Comp... ADPREV (depending on the setting of ADPSIS) and the value of the second conversion is placed into ADRES. Only upon the completion of the second conversion is ADERR calculated and ADTIF triggered (depending on the value of ADCALC). (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 606 PIC18F26/45/46Q10 (ADC2) Analog-to-Digital Converter with Comp... 32.6 Register Summary - ADC Control Address Name Bit Pos. 0x0F51 ADACT 7:0 0x0F52 ADCLK 7:0 0x0F53 ADREF 7:0 0x0F54 ADCON1 7:0 ADPPOL 0x0F55 ADCON2 7:0 ADPSIS 0x0F56 ADCON3 7:0 0x0F57 ADACQ 7:0 0x0F58 ADCAP 7:0 0x0F59 ADPRE 7:0 0x0F5A ADPCH 7:0 0x0F5B ADCON0 7:0 0x0F5C ADPREV 0x0F5E ADRES 0x0F60 ADSTAT 7:0 0x0F61 ADRPT 7:0 0x0F62 ADCNT 7:0 ADCNT[7:0] 7:0 ADSTPTL[7:0] 15:8 ADSTPTH[7:0] 0x0F63 ADSTPT 0x0F65 ADLTH 0x0F67 ADUTH 0x0F69 ADERR 0x0F6B 0x0F6D 32.7 ADACC ADFLTR ADACT[4:0] ADCS[5:0] ADNREF ADIPEN ADPREF[1:0] ADGPOL ADDSEN ADCRS[2:0] ADACLR ADMD[2:0] ADCALC[2:0] ADSOI ADTMD[2:0] ADACQ[7:0] ADCAP[4:0] ADPRE[7:0] ADPCH[5:0] ADON ADCONT ADCS 7:0 ADPREVL[7:0] 15:8 ADPREVH[7:0] 7:0 ADRESL[7:0] 15:8 ADFM ADGO ADRESH[7:0] ADAOV ADUTHR ADLTHR ADMATH ADSTAT[2:0] ADRPT[7:0] 7:0 ADLTHL[7:0] 15:8 ADLTHH[7:0] 7:0 ADUTHL[7:0] 15:8 ADUTHH[7:0] 7:0 ADERRL[7:0] 15:8 ADERRH[7:0] 7:0 ADACCL[7:0] 15:8 ADACCH[7:0] 7:0 ADFLTRL[7:0] 15:8 ADFLTRH[7:0] Register Definitions: ADC Control (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 607 PIC18F26/45/46Q10 (ADC2) Analog-to-Digital Converter with Comp... 32.7.1 ADCON0 Name: Address: ADCON0 0xF5B ADC Control Register 0 Bit Access Reset 7 6 ADON ADCONT 5 ADCS 4 3 ADFM 2 1 ADGO 0 R/W R/W R/W R/W R/W/HC 0 0 0 0 0 Bit 7 - ADON ADC Enable bit Value Description 1 ADC is enabled 0 ADC is disabled Bit 6 - ADCONT ADC Continuous Operation Enable bit Value Description 1 ADGO is retriggered upon completion of each conversion trigger until ADTIF is set (if ADSOI is set) or until ADGO is cleared (regardless of the value of ADSOI) 0 ADC is cleared upon completion of each conversion trigger Bit 4 - ADCS ADC Clock Selection bit Value Description 1 Clock supplied from FRC dedicated oscillator 0 Clock supplied by Fosc, divided according to ADCLK register Bit 2 - ADFM ADC results Format/alignment Selection Value Description 1 ADRES and ADPREV data are right justified 0 ADRES and ADPREV data are left justified, zero-filled Bit 0 - ADGO ADC Conversion Status bit Value Description 1 ADC conversion cycle in progress. Setting this bit starts an ADC conversion cycle. The bit is cleared by hardware as determined by the ADCONT bit 0 ADC conversion completed/not in progress (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 608 PIC18F26/45/46Q10 (ADC2) Analog-to-Digital Converter with Comp... 32.7.2 ADCON1 Name: Address: ADCON1 0xF54 ADC Control Register 1 Bit Access Reset 7 6 5 ADPPOL ADIPEN ADGPOL 4 3 ADDSEN R/W R/W R/W R/W 0 0 0 0 Bit 7 - ADPPOL Precharge Polarity bit Action During 1st Precharge Stage Value Condition x ADPRE=0 1 ADPRE>0 and ADC input is I/O pin 0 ADPRE>0 and ADC input is I/O pin 1 ADPRE>0 and ADC input is internal 0 ADPRE>0 and ADC input is internal 2 1 0 Description Bit has no effect Pin shorted to AVDD Pin shorted to VSS CHOLD Shorted to AVDD CHOLD Shorted to VSS Bit 6 - ADIPEN A/D Inverted Precharge Enable bit Value Condition Description x ADDSEN = 0 Bit has no effect 1 ADDSEN = 1 The precharge and guard signals in the second conversion cycle are the opposite polarity of the first cycle 0 ADDSEN = 1 Both Conversion cycles use the precharge and guards specified by ADPPOL and ADGPOL Bit 5 - ADGPOL Guard Ring Polarity Selection bit Value Description 1 ADC guard Ring outputs start as digital high during Precharge stage 0 ADC guard Ring outputs start as digital low during Precharge stage Bit 0 - ADDSEN Double-Sample Enable bit Value Description 1 Two conversions are processed as a pair. The selected computation is performed after every second conversion. 0 Selected computation is performed after every conversion (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 609 PIC18F26/45/46Q10 (ADC2) Analog-to-Digital Converter with Comp... 32.7.3 ADCON2 Name: Address: ADCON2 0xF55 ADC Control Register 2 Bit 7 6 ADPSIS Access Reset 5 4 ADCRS[2:0] 3 2 ADACLR 1 0 ADMD[2:0] R/W R/W R/W R/W R/W/HC R/W R/W R/W 0 0 0 0 0 0 0 0 Bit 7 - ADPSIS ADC Previous Sample Input Select bits Value Description 1 ADFLTR is transferred to ADPREV at start-of-conversion 0 ADRES is transferred to ADPREV at start-of-conversion Bits 6:4 - ADCRS[2:0] ADC Accumulated Calculation Right Shift Select bits Value Condition Description 1 to 6 ADMD = 'b100 Low-pass filter time constant is 2ADCRS, filter gain is 1:1(2) 1 to 6 ADMD =' b011 to 'b001 The accumulated value is right-shifted by ADCRS (divided by 2ADCRS)(1,2) x ADMD ='b000 These bits are ignored Bit 3 - ADACLR A/D Accumulator Clear Command bit(3) Value Description 1 ADACC, ADAOV and ADCNT registers are cleared 0 Clearing action is complete (or not started) Bits 2:0 - ADMD[2:0] ADC Operating Mode Selection bits(4) Value Description 111-101 Reserved 100 Low-pass Filter mode 011 Burst Average mode 010 Average mode 001 Accumulate mode 000 Basic (Legacy) mode Note: 1. To correctly calculate an average, the number of samples (set in ADRPT) must be 2ADCRS. 2. ADCRS = 'b111 and 'b000 are reserved. 3. 4. This bit is cleared by hardware when the accumulator operation is complete; depending on oscillator selections, the delay may be many instructions. See Table 32-4 for Full mode descriptions. (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 610 PIC18F26/45/46Q10 (ADC2) Analog-to-Digital Converter with Comp... 32.7.4 ADCON3 Name: Address: ADCON3 0xF56 ADC Control Register 3 Bit 7 6 5 4 ADCALC[2:0] Access Reset 3 2 ADSOI 1 0 ADTMD[2:0] R/W R/W R/W R/W/HC R/W R/W R/W 0 0 0 0 0 0 0 Bits 6:4 - ADCALC[2:0] ADC Error Calculation Mode Select bits See Table 32-6 table for selection details. Bit 3 - ADSOI ADC Stop-on-Interrupt bit Value Condition Description 1 ADCONT = 1 ADGO is cleared when the threshold conditions are met, otherwise the conversion is retriggered 0 ADCONT = 1 ADGO is not cleared by hardware, must be cleared by software to stop retriggers x ADCONT = 0 This bit is not used Bits 2:0 - ADTMD[2:0] Threshold Interrupt Mode Select bits Value Description 111 Interrupt regardless of threshold test results 110 Interrupt if ADERR>ADUTH 101 Interrupt if ADERRADUTH 100 Interrupt if ADERR<ADLTH or ADERR>ADUTH 011 Interrupt if ADERR>ADLTH and ADERR<ADUTH 010 Interrupt if ADERRADLTH 001 Interrupt if ADERR<ADLTH 000 Never interrupt (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 611 PIC18F26/45/46Q10 (ADC2) Analog-to-Digital Converter with Comp... 32.7.5 ADSTAT Name: Address: ADSTAT 0xF60 ADC Status Register Bit Access Reset 7 6 5 4 ADAOV ADUTHR ADLTHR ADMATH 3 2 1 0 R/C/HS/HC RO RO R/C/HS/HC RO RO RO 0 0 0 0 0 0 0 ADSTAT[2:0] Bit 7 - ADAOV ADC Accumulator Overflow bit Value Description 1 ADC accumulator or ADERR calculation have overflowed 0 ADC accumulator and ADERR calculation have not overflowed Bit 6 - ADUTHR ADC Module Greater-than Upper Threshold Flag bit Value Description 1 ADERR >ADUTH 0 ADERRADUTH Bit 5 - ADLTHR ADC Module Less-than Lower Threshold Flag bit Value Description 1 ADERR<ADLTH 0 ADERRADLTH Bit 4 - ADMATH ADC Module Computation Status bit Value Description 1 Registers ADACC, ADFLTR, ADUTH, ADLTH and the ADAOV bit are updating or have already updated 0 Associated registers/bits have not changed since this bit was last cleared Bits 2:0 - ADSTAT[2:0] ADC Module Cycle Multi-Stage Status bits(1) Value Description 111 ADC module is in 2nd conversion stage 110 ADC module is in 2nd acquisition stage 101 ADC module is in 2nd precharge stage 100 Not used 011 ADC module is in 1st conversion stage 010 ADC module is in 1st acquisition stage 001 ADC module is in 1st precharge stage 000 ADC module is not converting Note: 1. If ADCS = 1, and FOSC<FRC, the indicated status may not be valid. (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 612 PIC18F26/45/46Q10 (ADC2) Analog-to-Digital Converter with Comp... 32.7.6 ADCLK Name: Address: ADCLK 0xF52 ADC Clock Selection Register Bit 7 6 5 4 3 2 1 0 ADCS[5:0] Access Reset R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 Bits 5:0 - ADCS[5:0] ADC Conversion Clock Select bits Value Description n ADC Clock frequency = FOSC/(2*(n+1)) (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 613 PIC18F26/45/46Q10 (ADC2) Analog-to-Digital Converter with Comp... 32.7.7 ADREF Name: Address: ADREF 0xF53 ADC Reference Selection Register Bit 7 6 5 4 3 2 1 ADNREF Access Reset 0 ADPREF[1:0] R/W R/W R/W 0 0 0 Bit 4 - ADNREF ADC Negative Voltage Reference Selection bit Value Description 1 VREF- is connected to external VREF0 VREF- is connected to AVSS Bits 1:0 - ADPREF[1:0] ADC Positive Voltage Reference Selection bits Value Description 11 VREF+ is connected to internal Fixed Voltage Reference (FVR) module 10 VREF+ is connected to external VREF+ 01 Reserved 00 VREF+ is connected to VDD (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 614 PIC18F26/45/46Q10 (ADC2) Analog-to-Digital Converter with Comp... 32.7.8 ADPCH Name: Address: ADPCH 0xF5A ADC Positive Channel Selection Register Bit 7 6 5 4 3 2 1 0 ADPCH[5:0] Access Reset R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 Bits 5:0 - ADPCH[5:0] ADC Positive Input Channel Selection bits See Channel Selection Table for input selection details. (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 615 PIC18F26/45/46Q10 (ADC2) Analog-to-Digital Converter with Comp... 32.7.9 ADPRE Name: Address: ADPRE 0xF59 ADC Precharge Time Control Register Bit 7 6 5 4 3 2 1 0 ADPRE[7:0] Access Reset R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Bits 7:0 - ADPRE[7:0] Precharge Time Select bits Value Description 1 to Number of ADC clocks in the precharge time. 255 0 Precharge time is not included in the data conversion cycle (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 616 PIC18F26/45/46Q10 (ADC2) Analog-to-Digital Converter with Comp... 32.7.10 ADACQ Name: Address: ADACQ 0xF57 ADC Acquisition Time Control Register Bit 7 6 5 4 3 2 1 0 ADACQ[7:0] Access Reset R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Bits 7:0 - ADACQ[7:0] Acquisition (charge share time) Select bits Value Description 0x01 to Number of ADC clock periods in the acquisition time 0xFF 0x00 Acquisition time is not included in the data conversion cycle (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 617 PIC18F26/45/46Q10 (ADC2) Analog-to-Digital Converter with Comp... 32.7.11 ADCAP Name: Address: ADCAP 0xF58 ADC Additional Sample Capacitor Selection Register Bit 7 6 5 4 3 2 1 0 ADCAP[4:0] Access Reset R/W R/W R/W R/W R/W 0 0 0 0 0 Bits 4:0 - ADCAP[4:0] ADC Additional Sample Capacitor Selection bits Value Description 1 to 31 Number of pF in the additional capacitance 0 No additional capacitance (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 618 PIC18F26/45/46Q10 (ADC2) Analog-to-Digital Converter with Comp... 32.7.12 ADRPT Name: Address: ADRPT 0xF61 ADC Repeat Setting Register Bit 7 6 5 4 3 2 1 0 ADRPT[7:0] Access Reset R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Bits 7:0 - ADRPT[7:0] ADC Repeat Threshold bits Determines the number of times that the ADC is triggered for a threshold check. When ADCNT reaches this value the error threshold is checked. Used when the computation mode is Low-pass Filter, Burst Average, or Average. See Table 32-4 for more details. (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 619 PIC18F26/45/46Q10 (ADC2) Analog-to-Digital Converter with Comp... 32.7.13 ADCNT Name: Address: ADCNT 0xF62 ADC Repeat Counter Register Bit 7 6 5 4 3 2 1 0 ADCNT[7:0] Access Reset R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Bits 7:0 - ADCNT[7:0] ADC Repeat Count bits Counts the number of times that the ADC is triggered before the threshold is checked. When this value reaches ADPRT then the threshold is checked. Used when the computation mode is Low-pass Filter, Burst Average, or Average. See Table 32-4 for more details. (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 620 PIC18F26/45/46Q10 (ADC2) Analog-to-Digital Converter with Comp... 32.7.14 ADFLTR Name: Address: ADFLTR 0xF6D ADC Filter Register. In Accumulate, Average, and Burst Average mode, this is equal to ADACC right shifted by the ADCRS bits of ADCON2. In LPF mode, this is the output of the low-pass filter. Bit 15 14 13 12 Access RO RO RO RO Reset x x x x Bit 7 6 5 4 11 10 9 8 RO RO RO RO x x x x 3 2 1 0 ADFLTRH[7:0] ADFLTRL[7:0] Access Reset RO RO RO RO RO RO RO RO x x x x x x x x Bits 15:8 - ADFLTRH[7:0] ADC Filter Output Most Significant bits Bits 7:0 - ADFLTRL[7:0] ADC Filter Output Least Significant bits (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 621 PIC18F26/45/46Q10 (ADC2) Analog-to-Digital Converter with Comp... 32.7.15 ADRES Name: Address: ADRES 0xF5E ADC Result Register Bit 15 14 13 12 11 10 9 8 ADRESH[7:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 ADRESL[7:0] Access Reset Bits 15:8 - ADRESH[7:0] ADC Result Register bits. High bits Value Condition Description 0x00,0x ADFM=1 Upper 2 bits of result 01,0x02 ,0x03 0 to ADFM=0 Upper 8 bits of result 0xFF Bits 7:0 - ADRESL[7:0] ADC Result Register bits. Lower bits Value Condition Description 0 to ADFM=1 Lower 8 bits of result 0xFF 0x00,0x ADFM=0 Lower 2 bits of result 40,0x80 ,0xC0 (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 622 PIC18F26/45/46Q10 (ADC2) Analog-to-Digital Converter with Comp... 32.7.16 ADPREV Name: Address: ADPREV 0xF5C ADC Previous Result Register Bit 15 14 13 12 11 10 9 8 ADPREVH[7:0] Access RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 RO RO RO RO RO RO RO RO 0 0 0 0 0 0 0 0 ADPREVL[7:0] Access Reset Bits 15:8 - ADPREVH[7:0] Previous ADC Result Most Significant bits Value Condition Description 0 to ADPSIS=1 Upper byte of ADFLTR at the start of current ADC conversion 0xFF varies ADPSIS=0 Upper bits of ADRES at the start of current ADC conversion(1) Bits 7:0 - ADPREVL[7:0] Value Condition 0 to ADPSIS=1 0xFF varies ADPSIS=0 Previous ADC Result Least Significant bits Description Lower byte of ADFLTR at the start of current ADC conversion Lower bits of ADRES at the start of current ADC conversion(1) Note: If ADPSIS = 0, ADPREVH and ADPREVL are formatted the same way as ADRES is, depending on the ADFM bit. (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 623 PIC18F26/45/46Q10 (ADC2) Analog-to-Digital Converter with Comp... 32.7.17 ADACC Name: Address: ADACC 0xF6B ADC Accumulator Register See Table 32-4 for more details. Bit 15 14 13 12 11 10 9 8 R/W R/W R/W R/W Reset x x R/W R/W R/W R/W x x x x x x Bit 7 6 5 4 3 2 1 0 ADACCH[7:0] Access ADACCL[7:0] Access Reset R/W R/W R/W R/W R/W R/W R/W R/W x x x x x x x x Bits 15:8 - ADACCH[7:0] ADC Accumulator Most Significant Byte. Reset States: POR/BOR = xxxxxxxx All Other Resets = uuuuuuuu Bits 7:0 - ADACCL[7:0] ADC Accumulator Least Significant Byte. Reset States: POR/BOR = xxxxxxxx All Other Resets = uuuuuuuu (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 624 PIC18F26/45/46Q10 (ADC2) Analog-to-Digital Converter with Comp... 32.7.18 ADSTPT Name: Address: ADSTPT 0xF63 ADC Threshold Setpoint Register Depending on ADCALC, may be used to determine ADERR. See Table 32-6 for more details. Bit 15 14 13 12 R/W R/W R/W R/W Reset 0 0 0 0 Bit 7 6 5 4 11 10 9 8 R/W R/W R/W R/W 0 0 0 0 3 2 1 0 ADSTPTH[7:0] Access ADSTPTL[7:0] Access Reset R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Bits 15:8 - ADSTPTH[7:0] ADC Threshold Setpoint Most Significant Byte. Bits 7:0 - ADSTPTL[7:0] ADC Threshold Setpoint Least Significant Byte. (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 625 PIC18F26/45/46Q10 (ADC2) Analog-to-Digital Converter with Comp... 32.7.19 ADERR Name: Address: ADERR 0xF69 ADC Setpoint Error Register. ADC Setpoint Error calculation is determined by the ADCALC bits. Bit 15 14 13 12 11 10 9 8 ADERRH[7:0] Access RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 RO RO RO RO RO RO RO RO 0 0 0 0 0 0 0 0 ADERRL[7:0] Access Reset Bits 15:8 - ADERRH[7:0] ADC Setpoint Error MSB Bits 7:0 - ADERRL[7:0] ADC Setpoint Error LSB (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 626 PIC18F26/45/46Q10 (ADC2) Analog-to-Digital Converter with Comp... 32.7.20 ADLTH Name: Address: ADLTH 0xF65 ADC Lower Threshold Register ADLTH and ADUTH are compared with ADERR to set the ADUTHR and ADLTHR bits of ADSTAT. Depending on the setting of ADTMD, an interrupt may be triggered by the results of this comparison. Bit 15 14 13 12 11 10 9 8 ADLTHH[7:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 ADLTHL[7:0] Access Reset Bits 15:8 - ADLTHH[7:0] ADC Lower Threshold MSB Bits 7:0 - ADLTHL[7:0] ADC Lower Threshold LSB (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 627 PIC18F26/45/46Q10 (ADC2) Analog-to-Digital Converter with Comp... 32.7.21 ADUTH Name: Address: ADUTH 0xF67 ADC Upper Threshold Register ADLTH and ADUTH are compared with ADERR to set the ADUTHR and ADLTHR bits of ADSTAT. Depending on the setting of ADTMD, an interrupt may be triggered by the results of this comparison. Bit 15 14 13 12 11 10 9 8 ADUTHH[7:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 ADUTHL[7:0] Access Reset Bits 15:8 - ADUTHH[7:0] ADC Upper Threshold MSB Bits 7:0 - ADUTHL[7:0] ADC Upper Threshold LSB (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 628 PIC18F26/45/46Q10 (ADC2) Analog-to-Digital Converter with Comp... 32.7.22 ADACT Name: Address: ADACT 0xF51 ADC AUTO Conversion Trigger Source Selection Register Bit 7 6 5 4 3 2 1 0 ADACT[4:0] Access Reset R/W R/W R/W R/W R/W 0 0 0 0 0 Bits 4:0 - ADACT[4:0] Auto-Conversion Trigger Select Bits Value Description 00000 See Auto-Conversion Trigger Sources table. to 11111 (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 629 PIC18F26/45/46Q10 (CMP) Comparator Module 33. (CMP) Comparator Module Comparators are used to interface analog circuits to a digital circuit by comparing two analog voltages and providing a digital indication of their relative magnitudes. Comparators are very useful mixed-signal building blocks because they provide analog functionality independent of program execution. The PIC18F26/45/46Q10 devices have two comparators (C1/C2). The analog comparator module includes the following features: * * * * * * * * * * * * 33.1 Programmable Input Selection Programmable Output Polarity Rising/Falling Output Edge Interrupts Wake-up from Sleep CWG Auto-shutdown Source Selectable Voltage Reference ADC Auto-Trigger Odd Numbered Timers (Timer1, Timer3, etc.) Gate Even Numbered Timers (Timer2, Timer4, etc.) Reset CCP Capture Mode Input DSM Modulator Source Input and Window Signal-to-Signal Measurement Timer Comparator Overview A single comparator is shown in Figure 33-1 along with the relationship between the analog input levels and the digital output. When the analog voltage at VIN+ is less than the analog voltage at VIN-, the output of the comparator is a digital low level. When the analog voltage at VIN+ is greater than the analog voltage at VIN-, the output of the comparator is a digital high level. Figure 33-1. Single Comparator Rev. 30-000125A 5/17/2017 VIN+ + VIN- - Output VINVIN+ Output Note: 1. The black areas of the output of the comparator represent the uncertainty due to input offsets and response time. (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 630 PIC18F26/45/46Q10 (CMP) Comparator Module Figure 33-2. Comparator Module Simplified Block Diagram Rev. 10-000027R 7/19/2017 EN(1) NCH EN(1) CxVP See CMxNCH Register Interrupt Rising Edge INTP Interrupt Falling Edge INTN - D set bit CxIF Q Cx + CxVN Cx_out CMxCON0.OUT CMOUT.MCxOUT Q1 HYS POL CxOUT_sync See CMxPCH Register SYNC To Other Peripherals TRIS bit 0 PPS D (1) PCH EN Q (From Timer1 Module) T1CLK Note 1: CxOUT 1 RxyPPS When EN = 0, all multiplexer inputs are disconnected and the Comparator will produce a `0' at the output. Related Links 33.15.3 CMxNCH 33.15.4 CMxPCH 33.2 Comparator Control Each comparator has two control registers: CMxCON0 and CMxCON1. The CMxCON0 register contains Control and Status bits for the following: * * * * * Enable Output Output Polarity Hysteresis Enable Timer1 Output Synchronization The CMxCON1 register contains Control bits for the following: * Interrupt on Positive/Negative Edge Enables * Positive Input Channel Selection * Negative Input Channel Selection 33.2.1 Comparator Enable Setting the EN bit enables the comparator for operation. Clearing the CxEN bit disables the comparator, resulting in minimum current consumption. (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 631 PIC18F26/45/46Q10 (CMP) Comparator Module 33.2.2 Comparator Output The output of the comparator can be monitored by reading either the CxOUT bit or the MCxOUT bit. The comparator output can also be routed to an external pin through the RxyPPS register. The corresponding TRIS bit must be clear to enable the pin as an output. Note: 1. The internal output of the comparator is latched with each instruction cycle. Unless otherwise specified, external outputs are not latched. Related Links 17.9.2 RxyPPS 33.2.3 Comparator Output Polarity Inverting the output of the comparator is functionally equivalent to swapping the comparator inputs. The polarity of the comparator output can be inverted by setting the CxPOL bit. Clearing the CxPOL bit results in a non-inverted output. Table 33-1 shows the output state versus input conditions, including polarity control. Table 33-1. Comparator Output State vs. Input Conditions 33.3 Input Condition CxPOL CxOUT CxVn > CxVp 0 0 CxVn < CxVp 0 1 CxVn > CxVp 1 1 CxVn < CxVp 1 0 Comparator Hysteresis A selectable amount of separation voltage can be added to the input pins of each comparator to provide a hysteresis function to the overall operation. Hysteresis is enabled by setting the CxHYS bit. See Comparator Specifications for more information. Related Links 39.4.9 Comparator Specifications 33.4 Operation With Timer1 Gate The output resulting from a comparator operation can be used as a source for gate control of the odd numbered timers (Timer1, Timer3, etc.). See the timer gate section for more information. This feature is useful for timing the duration or interval of an analog event. It is recommended that the comparator output be synchronized to the timer by setting the SYNC bit. This ensures that the timer does not increment while a change in the comparator is occurring. However, synchronization is only possible with the Timer1 clock source. Synchronization with the other odd numbered timers is only possible when they use the same clock source as Timer1. Related Links 19.7 Timer1 Gate (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 632 PIC18F26/45/46Q10 (CMP) Comparator Module 33.4.1 Comparator Output Synchronization The output from a comparator can be synchronized with Timer1 by setting the SYNC bit. Once enabled, the comparator output is latched on the falling edge of the Timer1 source clock. If a prescaler is used with Timer1, the comparator output is latched after the prescaling function. To prevent a race condition, the comparator output is latched on the falling edge of the Timer1 clock source and Timer1 increments on the rising edge of its clock source. See the Figure 33-2 Comparator Block Diagram and the Timer1 Block Diagram for more information. Related Links 19. Timer1 Module with Gate Control 33.5 Comparator Interrupt An interrupt can be generated upon a change in the output value of the comparator for each comparator; a rising edge detector and a falling edge detector are present. When either edge detector is triggered and its associated enable bit is set (CxINTP and/or CxINTN bits), the Corresponding Interrupt Flag bit (CxIF bit of the PIR2 register) will be set. To enable the interrupt, the following bits must be set: * * * * * EN and POL bits CxIE bit of the PIE2 register INTP bit (for a rising edge detection) INTN bit (for a falling edge detection) PEIE and GIE bits of the INTCON register The associated interrupt flag bit, CxIF bit of the PIR2 register, must be cleared in software. If another edge is detected while this flag is being cleared, the flag will still be set at the end of the sequence. Important: Although a comparator is disabled, an interrupt can be generated by changing the output polarity with the CxPOL bit, or by switching the comparator on or off with the CxEN bit. 33.6 Comparator Positive Input Selection Configuring the PCH bits direct an internal voltage reference or an analog pin to the non-inverting input of the comparator: PCH Positive Input Source 111 AVSS 110 FVR_Buffer2 101 DAC_Output 100 CxPCH not connected 011 CxPCH not connected 010 CxPCH not connected (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 633 PIC18F26/45/46Q10 (CMP) Comparator Module ...........continued PCH Positive Input Source 001 CxIN1+ 000 CxIN0+ Important: To use CxINy+ pins as analog input, the appropriate bits must be set in the ANSEL register and the corresponding TRIS bits must also be set to disable the output drivers. See Fixed Voltage Reference (FVR) for more information on the Fixed Voltage Reference module. See 5-Bit Digital-to-Analog Converter (DAC) module for more information on the DAC input signal. Any time the comparator is disabled (CxEN = 0), all comparator inputs are disabled. Related Links 29. (FVR) Fixed Voltage Reference 31. (DAC) 5-Bit Digital-to-Analog Converter Module 33.7 Comparator Negative Input Selection The NCH bits direct an analog input pin and internal reference voltage or analog ground to the inverting input of the comparator: NCH Negative Input Sources 111 AVSS 110 FVR_Buffer2 101 CxNCH not connected 100 CxNCH not connected 011 CxIN3- 010 CxIN2- 001 CxIN1- 000 CxIN0Important: To use CxINy- pins as analog input, the appropriate bits must be set in the ANSEL register and the corresponding TRIS bits must also be set to disable the output drivers. 33.8 Comparator Response Time The comparator output is indeterminate for a period of time after the change of an input source or the selection of a new reference voltage. This period is referred to as the response time. The response time of the comparator differs from the settling time of the voltage reference. Therefore, both of these times (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 634 PIC18F26/45/46Q10 (CMP) Comparator Module must be considered when determining the total response time to a comparator input change. See the Comparator and Voltage Reference Specifications in Comparator Specifications and Fixed Voltage Reference (FVR) Specifications for more details. Related Links 39.4.9 Comparator Specifications 39.4.11 Fixed Voltage Reference (FVR) Specifications 33.9 Analog Input Connection Considerations A simplified circuit for an analog input is shown in Figure 33-3. Since the analog input pins share their connection with a digital input, they have reverse biased ESD protection diodes to VDD and VSS. The analog input, therefore, must be between VSS and VDD. If the input voltage deviates from this range by more than 0.6V in either direction, one of the diodes is forward biased and a latch-up may occur. A maximum source impedance of 10 k is recommended for the analog sources. Also, any external component connected to an analog input pin, such as a capacitor or a Zener diode, should have very little leakage current to minimize inaccuracies introduced. Note: 1. When reading a PORT register, all pins configured as analog inputs will read as a `0'. Pins configured as digital inputs will convert as an analog input, according to the input specification. 2. Analog levels on any pin defined as a digital input, may cause the input buffer to consume more current than is specified. Figure 33-3. Analog Input Model Rev. 10-000071A 8/2/2013 VDD RS < 10K Analog Input pin VA CPIN 5pF VT 0.6V RIC To Comparator ILEAKAGE(1) VT 0.6V VSS Legend: CPIN ILEAKAGE RIC RS VA VT = Input Capacitance = Leakage Current at the pin due to various junctions = Interconnect Resistance = Source Impedance = Analog Voltage = Threshold Voltage Note: See Electrical Specifications chapter. Related Links 39. Electrical Specifications (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 635 PIC18F26/45/46Q10 (CMP) Comparator Module 33.10 CWG1 Auto-Shutdown Source The output of the comparator module can be used as an auto-shutdown source for the CWG1 module. When the output of the comparator is active and the corresponding WGASxE is enabled, the CWG operation will be suspended immediately. Related Links 24.11.1.2 External Input Source 33.11 ADC Auto-Trigger Source The output of the comparator module can be used to trigger an ADC conversion. When the ADACT register is set to trigger on a comparator output, an ADC conversion will trigger when the comparator output goes high. 33.12 Even Numbered Timers Reset The output of the comparator module can be used to reset the even numbered timers (Timer2, Timer4, etc.). When the TxERS register is appropriately set, the timer will reset when the comparator output goes high. 33.13 Operation in Sleep Mode The comparator module can operate during Sleep. The comparator clock source is based on the Timer1 clock source. If the Timer1 clock source is either the system clock (FOSC) or the instruction clock (FOSC/4), Timer1 will not operate during Sleep, and synchronized comparator outputs will not operate. A comparator interrupt will wake the device from Sleep. The CxIE bits of the PIEx register must be set to enable comparator interrupts. (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 636 PIC18F26/45/46Q10 (CMP) Comparator Module 33.14 Register Summary - Comparator Address Name Bit Pos. 0x0F30 CM2CON0 7:0 0x0F31 CM2CON1 0x0F32 CM2NCH 0x0F33 CM2PCH 7:0 0x0F34 CM1CON0 7:0 HYS SYNC 0x0F35 CM1CON1 7:0 INTP INTN 0x0F36 CM1NCH 7:0 NCH[2:0] 0x0F37 CM1PCH 7:0 PCH[2:0] 0x0F38 CMOUT 7:0 MC2OUT 33.15 EN OUT POL HYS SYNC 7:0 INTP INTN 7:0 NCH[2:0] PCH[2:0] EN OUT POL MC1OUT Register Definitions: Comparator Control Long bit name prefixes for the comparator peripherals are shown in the table below. Refer to the "Long Bit Names Section" for more information. Table 33-2. Comparator Bit Name Prefixes Peripheral Bit Name Prefix C1 C1 C2 C2 Related Links 1.4.2.2 Long Bit Names (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 637 PIC18F26/45/46Q10 (CMP) Comparator Module 33.15.1 CMxCON0 Name: Address: CMxCON0 0xF34,0xF30 Comparator x Control Register 0 Bit Access Reset 7 6 1 0 EN OUT POL HYS SYNC R/W RO R/W R/W R/W 0 0 0 0 0 Bit 7 - EN Value 1 0 5 4 3 2 Comparator Enable bit Description Comparator is enabled Comparator is disabled and consumes no active power Bit 6 - OUT Comparator Output bit Value Condition 1 If POL = 0 (non-inverted polarity): 0 If POL = 0 (non-inverted polarity): 1 If POL = 1 (inverted polarity): 0 If POL = 1 (inverted polarity): Description CxVP > CxVN CxVP < CxVN CxVP < CxVN CxVP > CxVN Bit 4 - POL Comparator Output Polarity Select bit Value Description 1 Comparator output is inverted 0 Comparator output is not inverted Bit 1 - HYS Comparator Hysteresis Enable bit Value Description 1 Comparator hysteresis enabled 0 Comparator hysteresis disabled Bit 0 - SYNC Comparator Output Synchronous Mode bit Output updated on the falling edge of prescaled Timer1 clock. Value Description 1 Comparator output to Timer1 and I/O pin is synchronous to changes on the prescaled Timer1 clock. 0 Comparator output to Timer1 and I/O pin is asynchronous (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 638 PIC18F26/45/46Q10 (CMP) Comparator Module 33.15.2 CMxCON1 Name: Address: CMxCON1 0xF35,0xF31 Comparator x Control Register 1 Bit 7 6 5 4 3 Access Reset 2 1 0 INTP INTN R/W R/W 0 0 Bit 1 - INTP Comparator Interrupt on Positive-Going Edge Enable bit Value Description 1 The CxIF interrupt flag will be set upon a positive-going edge of the CxOUT bit 0 No interrupt flag will be set on a positive-going edge of the CxOUT bit Bit 0 - INTN Comparator Interrupt on Negative-Going Edge Enable bit Value Description 1 The CxIF interrupt flag will be set upon a negative-going edge of the CxOUT bit 0 No interrupt flag will be set on a negative-going edge of the CxOUT bit (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 639 PIC18F26/45/46Q10 (CMP) Comparator Module 33.15.3 CMxNCH Name: Address: CMxNCH 0xF36,0xF32 Comparator x Inverting Channel Select Register Bit 7 6 5 4 3 2 1 0 NCH[2:0] Access Reset R/W R/W R/W 0 0 0 Bits 2:0 - NCH[2:0] Comparator Inverting Input Channel Select bits NCH Negative Input Sources 111 AVSS 110 FVR_Buffer2 101 CxNCH not connected 100 CxNCH not connected 011 CxIN3- 010 CxIN2- 001 CxIN1- 000 CxIN0- (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 640 PIC18F26/45/46Q10 (CMP) Comparator Module 33.15.4 CMxPCH Name: Address: CMxPCH 0xF37,0xF33 Comparator x Non-Inverting Channel Select Register Bit 7 PCH Positive Input Source 111 AVSS 110 FVR_Buffer2 101 DAC_Output 100 CxPCH not connected 011 CxPCH not connected 010 CxPCH not connected 001 CxIN1+ 000 CxIN0+ 6 5 4 3 2 1 0 PCH[2:0] Access Reset R/W R/W R/W 0 0 0 Bits 2:0 - PCH[2:0] Comparator Non-Inverting Input Channel Select bits (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 641 PIC18F26/45/46Q10 (CMP) Comparator Module 33.15.5 CMOUT Name: Address: CMOUT 0xF38 Comparator Output Register Bit 7 6 5 4 3 Access Reset 2 1 0 MC2OUT MC1OUT RO RO 0 0 Bits 0, 1 - MCxOUT Mirror copy of CxOUT bit (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 642 PIC18F26/45/46Q10 (HLVD) High/Low-Voltage Detect 34. (HLVD) High/Low-Voltage Detect The HLVD module can be10-000256A.vsd configured to monitor the device voltage. This is useful in battery monitoring Filename: applications. Title: HLVD MODULE BLOCK DIAGRAM (WITHOUT EXTERNAL INPUT) Last Edit: 8/8/2018 Complete control 18(L)F2x/4xK40 of the HLVD module First Used: (MFAE)is provided through the HLVDCON0 and HLVDCON1 registers. Notes: The module's block diagram is shown in the figure below. Figure 34-1. HLVD Module Block Diagram VDD Rev. 10-000256A 8/8/2018 16-to-1 MUX 4 HLVDSEL<3:0> HLVDEN HLVDOUT Trigger/ Interrupt Generation + HLVDRDY HLVDEN HLVDIF HLVDINTH HLVDINTL Band gap Reference Volatge Since the HLVD can be software enabled through the HLVDEN bit, setting and clearing the enable bit does not produce a false HLVD event glitch. Each time the HLVD module is enabled, the RDY bit can be used to detect when the module is stable and ready to use. The INTH and INTL bits determine the overall operation of the module. When INTH is set, the module monitors for rises in VDD above the trip point set by the bits. When INTL is set, the module monitors for drops in VDD below the trip point set by the SEL bits. When both the INTH and INTL bits are set, any changes above or below the trip point set by the SEL bits can be monitored. The OUT bit can be read to determine if the voltage is greater than or less than the selected trip point. 34.1 Operation When the HLVD module is enabled, a comparator uses an internally generated voltage reference as the set point. The set point is compared with the trip point, where each node in the resistor divider represents a trip point voltage. The "trip point" voltage is the voltage level at which the device detects a high or lowvoltage event, depending on the configuration of the module. When the supply voltage is equal to the trip point, the voltage tapped off of the resistor array is equal to the internal reference voltage generated by the voltage reference module. The comparator then generates an interrupt signal by setting the HLVDIF bit. (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 643 PIC18F26/45/46Q10 (HLVD) High/Low-Voltage Detect The trip point voltage is software programmable to any of 16 values. The trip point is selected by programming the SEL bits. 34.2 Setup To set up the HLVD module: 1. 2. 3. 4. 5. Select the desired HLVD trip point by writing the value to the SEL bits of the HLVDCON1 register. Depending on the application to detect high-voltage peaks or low-voltage drops or both, set the INTH or INTL bit appropriately. Enable the HLVD module by setting the EN bit. Clear the HLVD interrupt flag (HLVDIF), which may have been set from a previous interrupt. If interrupts are desired, enable the HLVD interrupt by setting the HLVDIE and GIE bits. An interrupt will not be generated until the RDY bit is set. Important: Before changing any module settings (interrupts and tripping point), first disable the module (EN = 0), make the changes and re-enable the module. This prevents the generation of false HLVD events. Related Links 14.13.4 PIR2 14.13.13 PIE3 34.3 Current Consumption When the module is enabled, the HLVD comparator and voltage divider are enabled and consume static current. The total current consumption, when enabled, is specified in electrical specification Parameter D206. Depending on the application, the HLVD module does not need to operate constantly. To reduce current consumption, the module can be enabled for short periods where the voltage is checked. After such a check, the module could be disabled. Related Links 39.3.3 Power-Down Current (IPD)(1,2) 34.4 HLVD Start-up Time If the HLVD or other circuits using the internal voltage reference are disabled to lower the device's current consumption, the reference voltage circuit will require time to become stable before a low or high-voltage condition can be reliably detected. This start-up time, TFVRST, is an interval that is independent of device clock speed. It is specified in electrical specification. The HLVD interrupt flag is not enabled until TFVRST has expired and a stable reference voltage is reached. For this reason, brief excursions beyond the set point may not be detected during this interval (see the figures below). (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 644 PIC18F26/45/46Q10 (HLVD) High/Low-Voltage Detect Figure 34-2. Low-Voltage Detect Operation (INTL = 1) Rev. 30-000141A 5/26/2017 CASE 1: HLVDIF may not be Set VDD VHLVD HLVDIF Enable HLVD TFVRST HLVDRDY Band Gap Reference Voltage is Stable CASE 2: HLVDIF Cleared in Software VDD VHLVD HLVDIF Enable HLVD TFVRST HLVDRDY Band Gap Reference Voltage is Stable HLVDIF Cleared in Software HLVDIF Cleared in Software, HLVDIF Remains Set since HLVD Condition still Exists (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 645 PIC18F26/45/46Q10 (HLVD) High/Low-Voltage Detect Figure 34-3. High-Voltage Detect Operation (INTH = 1) Rev. 30-000142A 5/26/2017 CASE 1: HLVDIF may not be Set VHLVD VDD HLVDIF Enable HLVD TIRVST HLVDRDY HLVDIF Cleared in Software Band Gap Reference Voltage is Stable CASE 2: VHLVD VDD HLVDIF Enable HLVD TIRVST HLVDRDY Band Gap Reference Voltage is Stable HLVDIF Cleared in Software HLVDIF Cleared in Software, HLVDIF Remains Set since HLVD Condition still Exists 34.5 Applications In many applications, it is desirable to detect a drop below, or rise above, a particular voltage threshold. For example, the HLVD module could be periodically enabled to detect Universal Serial Bus (USB) attach or detach. This assumes the device is powered by a lower voltage source than the USB when detached. An attach would indicate a High-Voltage Detect from, for example, 3.3V to 5V (the voltage on USB) and vice versa for a detach. This feature could save a design a few extra components and an attach signal (input pin). For general battery applications, the figure below shows a possible voltage curve. Over time, the device voltage decreases. When the device voltage reaches voltage, Va, the HLVD logic generates an interrupt at time, Ta. The interrupt could cause the execution of an Interrupt Service Routine (ISR), which would allow the application to perform "housekeeping tasks" and a controlled shutdown before the device voltage exits the valid operating range at TB. This would give the application a time window, represented by the difference between TA and TB, to safely exit. (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 646 PIC18F26/45/46Q10 (HLVD) High/Low-Voltage Detect Figure 34-4. Typical Low-Voltage Detect Application Rev. 30-000143A 5/26/2017 Voltage VA VB Time TA TB Legend: VA = HLVD trip point VB = Minimum valid device o per at ing vol tage 34.6 Operation During Sleep When enabled, the HLVD circuitry continues to operate during Sleep. If the device voltage crosses the trip point, the HLVDIF bit will be set and the device will wake-up from Sleep. Device execution will continue from the interrupt vector address if interrupts have been globally enabled. 34.7 Operation During Idle and Doze Modes In both Idle and Doze modes, the module is active and events are generated if peripheral is enabled. 34.8 Effects of a Reset A device Reset forces all registers to their Reset state. This forces the HLVD module to be turned off. (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 647 PIC18F26/45/46Q10 (HLVD) High/Low-Voltage Detect 34.9 Register Summary - HLVD Address Name Bit Pos. 0x0F2A HLVDCON0 7:0 0x0F2B HLVDCON1 7:0 34.10 EN OUT RDY INTH INTL SEL[3:0] Register Definitions: HLVD Control Long bit name prefixes for the HLVD peripheral is shown in the following table. Refer to the "Long Bit Names" section for more information. Table 34-1. HLVD Long Bit Name Prefixes Peripheral Bit Name Prefix HLVD HLVD Related Links 1.4.2.2 Long Bit Names (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 648 PIC18F26/45/46Q10 (HLVD) High/Low-Voltage Detect 34.10.1 HLVDCON0 Name: Address: HLVDCON0 0xF2A High/Low-Voltage Detect Control Register 0 Bit Access Reset 5 4 1 0 EN 7 OUT RDY INTH INTL R/W RO RO R/W R/W 0 x x 0 0 Bit 7 - EN Value 1 0 6 3 2 High/Low-voltage Detect Power Enable bit Description Enables the HLVD module Disables the HLVD module Bit 5 - OUT HLVD Comparator Output bit Value Description 1 Voltage selected detection limit (SEL) 0 Voltage selected detection limit (SEL) Bit 4 - RDY Band Gap Reference Voltages Stable Status Flag bit Value Description 1 Indicates HLVD Module is ready and output is stable 0 Indicates HLVD Module is not ready Bit 1 - INTH HLVD Positive going (High Voltage) Interrupt Enable Value Description 1 HLVDIF will be set when voltage selected detection limit (SEL) 0 HLVDIF will not be set Bit 0 - INTL HLVD Negative going (Low Voltage) Interrupt Enable Value Description 1 HLVDIF will be set when voltage selected detection limit (SEL) 0 HLVDIF will not be set (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 649 PIC18F26/45/46Q10 (HLVD) High/Low-Voltage Detect 34.10.2 HLVDCON1 Name: Address: HLVDCON1 0xF2B Low-Voltage Detect Control Register 1 Bit 7 6 5 4 3 2 1 0 SEL[3:0] Access Reset R/W R/W R/W R/W 0 0 0 0 Bits 3:0 - SEL[3:0] High/Low-Voltage Detection Limit Selection bits Table 34-2. HLVD Detection Limits SEL Detection Limit 1111 Reserved 1110 to 0000 See High/Low-voltage detect characteristics Reset States: POR/BOR = 0000 All other resets = uuuu Related Links 39.4.6 High/Low-Voltage Detect Characteristics (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 650 PIC18F26/45/46Q10 Register Summary 35. Register Summary Address Name Bit Pos. 0x0E1F CLCIN0PPS 7:0 PORT[1:0] PIN[2:0] 0x0E20 CLCIN1PPS 7:0 PORT[1:0] PIN[2:0] 0x0E21 CLCIN2PPS 7:0 PORT[1:0] PIN[2:0] 0x0E22 CLCIN3PPS 7:0 PORT[1:0] PIN[2:0] 0x0E23 CLCIN4PPS 7:0 PORT[1:0] PIN[2:0] 0x0E24 CLCIN5PPS 7:0 PORT[1:0] PIN[2:0] 0x0E25 CLCIN6PPS 7:0 PORT[1:0] PIN[2:0] 0x0E26 CLCIN7PPS 7:0 PORT[1:0] 0x0E27 CLC1CON 7:0 EN 0x0E28 CLC1POL 7:0 POL 0x0E29 CLC1SEL0 7:0 D1S[5:0] 0x0E2A CLC1SEL1 7:0 D2S[5:0] 0x0E2B CLC1SEL2 7:0 D3S[5:0] 0x0E2C CLC1SEL3 7:0 D4S[5:0] OUT INTP PIN[2:0] INTN MODE[2:0] G4POL G3POL G2POL G1POL 0x0E2D CLC1GLS0 7:0 G1D4T G1D4N G1D3T G1D3N G1D2T G1D2N G1D1T G1D1N 0x0E2E CLC1GLS1 7:0 G2D4T G2D4N G2D3T G2D3N G2D2T G2D2N G2D1T G2D1N 0x0E2F CLC1GLS2 7:0 G3D4T G3D4N G3D3T G3D3N G3D2T G3D2N G3D1T G3D1N 0x0E30 CLC1GLS3 7:0 G4D4T G4D4N G4D3T G4D3N G4D2T G4D2N G4D1T G4D1N 0x0E31 CLC2CON 7:0 EN OUT INTP INTN 0x0E32 CLC2POL 7:0 POL MODE[2:0] G4POL G3POL G2POL G1POL 0x0E33 CLC2SEL0 7:0 D1S[5:0] 0x0E34 CLC2SEL1 7:0 D2S[5:0] 0x0E35 CLC2SEL2 7:0 D3S[5:0] 0x0E36 CLC2SEL3 7:0 0x0E37 CLC2GLS0 7:0 G1D4T G1D4N G1D3T G1D3N G1D2T G1D2N G1D1T G1D1N 0x0E38 CLC2GLS1 7:0 G2D4T G2D4N G2D3T G2D3N G2D2T G2D2N G2D1T G2D1N 0x0E39 CLC2GLS2 7:0 G3D4T G3D4N G3D3T G3D3N G3D2T G3D2N G3D1T G3D1N 0x0E3A CLC2GLS3 7:0 G4D4T G4D4N G4D3T G4D3N G4D2T G4D2N G4D1T G4D1N OUT INTP D4S[5:0] 0x0E3B CLC3CON 7:0 EN 0x0E3C CLC3POL 7:0 POL INTN MODE[2:0] 0x0E3D CLC3SEL0 7:0 D1S[5:0] 0x0E3E CLC3SEL1 7:0 D2S[5:0] 0x0E3F CLC3SEL2 7:0 D3S[5:0] 0x0E40 CLC3SEL3 7:0 0x0E41 CLC3GLS0 7:0 G1D4T G1D4N G1D3T G1D3N G1D2T 0x0E42 CLC3GLS1 7:0 G2D4T G2D4N G2D3T G2D3N G2D2T 0x0E43 CLC3GLS2 7:0 G3D4T G3D4N G3D3T G3D3N 0x0E44 CLC3GLS3 7:0 G4D4T G4D4N G4D3T G4D3N 0x0E45 CLC4CON 7:0 EN OUT INTP 0x0E46 CLC4POL 7:0 POL 0x0E47 CLC4SEL0 7:0 D1S[5:0] 0x0E48 CLC4SEL1 7:0 D2S[5:0] 0x0E49 CLC4SEL2 7:0 D3S[5:0] G4POL G3POL G2POL G1POL G1D2N G1D1T G1D1N G2D2N G2D1T G2D1N G3D2T G3D2N G3D1T G3D1N G4D2T G4D2N G4D1T G4D1N D4S[5:0] (c) 2019 Microchip Technology Inc. INTN MODE[2:0] G4POL Datasheet Preliminary G3POL G2POL G1POL DS40001996C-page 651 PIC18F26/45/46Q10 Register Summary ...........continued Address Name Bit Pos. 0x0E4A CLC4SEL3 7:0 0x0E4B CLC4GLS0 7:0 G1D4T G1D4N G1D3T G1D3N G1D2T D4S[5:0] G1D2N G1D1T G1D1N 0x0E4C CLC4GLS1 7:0 G2D4T G2D4N G2D3T G2D3N G2D2T G2D2N G2D1T G2D1N 0x0E4D CLC4GLS2 7:0 G3D4T G3D4N G3D3T G3D3N G3D2T G3D2N G3D1T G3D1N 0x0E4E CLC4GLS3 7:0 G4D4T G4D4N G4D3T G4D3N G4D2T G4D2N G4D1T G4D1N 0x0E4F CLC5CON 7:0 EN OUT INTP INTN 0x0E50 CLC5POL 7:0 POL MODE[2:0] G4POL G3POL G2POL G1POL 0x0E51 CLC5SEL0 7:0 D1S[5:0] 0x0E52 CLC5SEL1 7:0 D2S[5:0] 0x0E53 CLC5SEL2 7:0 D3S[5:0] 0x0E54 CLC5SEL3 7:0 0x0E55 CLC5GLS0 7:0 G1D4T G1D4N G1D3T G1D3N G1D2T G1D2N G1D1T G1D1N 0x0E56 CLC5GLS1 7:0 G2D4T G2D4N G2D3T G2D3N G2D2T G2D2N G2D1T G2D1N 0x0E57 CLC5GLS2 7:0 G3D4T G3D4N G3D3T G3D3N G3D2T G3D2N G3D1T G3D1N 0x0E58 CLC5GLS3 7:0 G4D4T G4D4N G4D3T G4D3N G4D2T G4D2N G4D1T G4D1N OUT INTP D4S[5:0] 0x0E59 CLC6CON 7:0 EN 0x0E5A CLC6POL 7:0 POL INTN MODE[2:0] 0x0E5B CLC6SEL0 7:0 D1S[5:0] 0x0E5C CLC6SEL1 7:0 D2S[5:0] 0x0E5D CLC6SEL2 7:0 D3S[5:0] 0x0E5E CLC6SEL3 7:0 0x0E5F CLC6GLS0 7:0 G1D4T G1D4N G1D3T G1D3N G1D2T 0x0E60 CLC6GLS1 7:0 G2D4T G2D4N G2D3T G2D3N G2D2T 0x0E61 CLC6GLS2 7:0 G3D4T G3D4N G3D3T G3D3N 0x0E62 CLC6GLS3 7:0 G4D4T G4D4N G4D3T G4D3N 0x0E63 CLC7CON 7:0 EN OUT INTP INTN 0x0E64 CLC7POL 7:0 POL 0x0E65 CLC7SEL0 7:0 D1S[5:0] 0x0E66 CLC7SEL1 7:0 D2S[5:0] 0x0E67 CLC7SEL2 7:0 D3S[5:0] 0x0E68 CLC7SEL3 7:0 D4S[5:0] G4POL G3POL G2POL G1POL G1D2N G1D1T G1D1N G2D2N G2D1T G2D1N G3D2T G3D2N G3D1T G3D1N G4D2T G4D2N G4D1T G4D1N D4S[5:0] MODE[2:0] G4POL G3POL G2POL G1POL 0x0E69 CLC7GLS0 7:0 G1D4T G1D4N G1D3T G1D3N G1D2T G1D2N G1D1T G1D1N 0x0E6A CLC7GLS1 7:0 G2D4T G2D4N G2D3T G2D3N G2D2T G2D2N G2D1T G2D1N 0x0E6B CLC7GLS2 7:0 G3D4T G3D4N G3D3T G3D3N G3D2T G3D2N G3D1T G3D1N 0x0E6C CLC7GLS3 7:0 G4D4T G4D4N G4D3T G4D3N G4D2T G4D2N G4D1T G4D1N 0x0E6D CLC8CON 7:0 EN OUT INTP INTN 0x0E6E CLC8POL 7:0 POL 0x0E6F CLC8SEL0 7:0 D1S[5:0] 0x0E70 CLC8SEL1 7:0 D2S[5:0] 0x0E71 CLC8SEL2 7:0 D3S[5:0] 0x0E72 CLC8SEL3 7:0 0x0E73 CLC8GLS0 7:0 G1D4T G1D4N G1D3T G1D3N G1D2T 0x0E74 CLC8GLS1 7:0 G2D4T G2D4N G2D3T G2D3N 0x0E75 CLC8GLS2 7:0 G3D4T G3D4N G3D3T G3D3N 0x0E76 CLC8GLS3 7:0 G4D4T G4D4N G4D3T G4D3N MODE[2:0] G4POL G3POL G2POL G1POL G1D2N G1D1T G1D1N G2D2T G2D2N G2D1T G2D1N G3D2T G3D2N G3D1T G3D1N G4D2T G4D2N G4D1T G4D1N D4S[5:0] (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 652 PIC18F26/45/46Q10 Register Summary ...........continued Address Name Bit Pos. 0x0E77 CLCDATA 7:0 MLC8OUT MLC7OUT MLC6OUT MLC5OUT MLC4OUT MLC3OUT MLC2OUT MLC1OUT 0x0E78 ... Reserved 0x0E87 0x0E88 RX2PPS 7:0 PORT[1:0] PIN[2:0] 0x0E89 CK2PPS 7:0 PORT[1:0] PIN[2:0] 0x0E8A SSP2CLKPPS 7:0 PORT[1:0] PIN[2:0] 0x0E8B SSP2DATPPS 7:0 PORT[1:0] PIN[2:0] 0x0E8C SSP2SSPPS 7:0 PORT[1:0] PIN[2:0] 0x0E8D SSP2BUF 7:0 BUF[7:0] 0x0E8E SSP2ADD 7:0 0x0E8F SSP2MSK 7:0 0x0E90 SSP2STAT 7:0 SMP 0x0E91 SSP2CON1 7:0 0x0E92 SSP2CON2 7:0 0x0E93 SSP2CON3 7:0 ADD[7:0] MSK[6:0] CKE D/A WCOL SSPOV SSPEN CKP GCEN ACKSTAT ACKDT ACKTIM PCIE SCIE MSK0 P S R/W ACKEN RCEN PEN RSEN SEN BOEN SDAHT SBCDE AHEN DHEN RX9D 0x0E94 RC2REG 7:0 RCREG[7:0] TX2REG 7:0 TXREG[7:0] 0x0E96 SP2BRG 0x0E98 RC2STA 7:0 7:0 SPBRGL[7:0] 15:8 SPBRGH[7:0] RX9 SREN CREN ADDEN FERR OERR TXEN SYNC SENDB BRGH TRMT TX9D SCKP BRG16 WUE ABDEN 0x0E99 TX2STA 7:0 CSRC TX9 0x0E9A BAUD2CON 7:0 ABDOVF RCIDL 0x0E9B PPSLOCK 7:0 0x0E9C INT0PPS 7:0 PORT PIN[2:0] 0x0E9D INT1PPS 7:0 PORT PIN[2:0] 0x0E9E INT2PPS 7:0 PORT PIN[2:0] 0x0E9F T0CKIPPS 7:0 PORT PIN[2:0] 0x0EA0 T1CKIPPS 7:0 PORT[1:0] PIN[2:0] 0x0EA1 T1GPPS 7:0 PORT[1:0] PIN[2:0] 0x0EA2 T3CKIPPS 7:0 PORT[1:0] PIN[2:0] 0x0EA3 T3GPPS 7:0 PORT[1:0] PIN[2:0] 0x0EA4 T5CKIPPS 7:0 PORT[1:0] PIN[2:0] 0x0EA5 T5GPPS 7:0 PORT[1:0] PIN[2:0] 0x0EA6 T2INPPS 7:0 PORT[1:0] PIN[2:0] 0x0EA7 T4INPPS 7:0 PORT[1:0] PIN[2:0] 0x0EA8 T6INPPS 7:0 PORT[1:0] PIN[2:0] PPSLOCKED 0x0EA9 ADACTPPS 7:0 PORT[1:0] PIN[2:0] 0x0EAA CCP1PPS 7:0 PORT[1:0] PIN[2:0] 0x0EAB CCP2PPS 7:0 PORT[1:0] PIN[2:0] 0x0EAC CWG1PPS 7:0 PORT[1:0] PIN[2:0] 0x0EAD MDCARLPPS 7:0 PORT[1:0] PIN[2:0] 0x0EAE MDCARHPPS 7:0 PORT[1:0] PIN[2:0] 0x0EAF MDSRCPPS 7:0 PORT[1:0] PIN[2:0] 0x0EB0 RX1PPS 7:0 PORT[1:0] PIN[2:0] (c) 2019 Microchip Technology Inc. BF SSPM[3:0] 0x0E95 SPEN UA Datasheet Preliminary DS40001996C-page 653 PIC18F26/45/46Q10 Register Summary ...........continued Address Name Bit Pos. 0x0EB1 CK1PPS 7:0 PORT[1:0] PIN[2:0] 0x0EB2 SSP1CLKPPS 7:0 PORT[1:0] PIN[2:0] 0x0EB3 SSP1DATPPS 7:0 PORT[1:0] PIN[2:0] 0x0EB4 SSP1SSPPS 7:0 PORT[1:0] PIN[2:0] 0x0EB5 IPR0 7:0 INT1IP INT0IP 0x0EB6 IPR1 7:0 OSCFIP CSWIP TMR0IP IOCIP INT2IP ADTIP ADIP 0x0EB7 IPR2 7:0 HLVDIP ZCDIP C2IP C1IP 0x0EB8 IPR3 7:0 RC2IP TX2IP 0x0EB9 IPR4 7:0 0x0EBA IPR5 7:0 RC1IP TX1IP BCL2IP SSP2IP BCL1IP SSP1IP TMR6IP TMR5IP TMR4IP TMR3IP TMR2IP TMR1IP TMR5GIP TMR3GIP TMR1GIP CLC4IP CLC3IP CLC2IP CLC1IP CLC5IP 0x0EBB IPR6 7:0 CLC8IP CLC7IP CLC6IP 0x0EBC IPR7 7:0 SCANIP CRCIP NVMIP 0x0EBD PIE0 7:0 INT1IE INT0IE 0x0EBE PIE1 7:0 OSCFIE CSWIE ADTIE ADIE 0x0EBF PIE2 7:0 HLVDIE ZCDIE C2IE C1IE 0x0EC0 PIE3 7:0 RC2IE TX2IE 0x0EC1 PIE4 7:0 0x0EC2 PIE5 7:0 0x0EC3 PIE6 0x0EC4 PIE7 0x0EC5 PIR0 7:0 0x0EC6 PIR1 0x0EC7 TMR0IE CCP2IP CCP1IP CWG1IP IOCIE INT2IE RC1IE TX1IE BCL2IE SSP2IE BCL1IE SSP1IE TMR6IE TMR5IE TMR4IE TMR3IE TMR2IE TMR1IE TMR5GIE TMR3GIE TMR1GIE CLC4IE CLC3IE CLC2IE CLC1IE 7:0 CLC8IE CLC7IE CLC6IE CLC5IE 7:0 SCANIE CRCIE NVMIE INT1IF INT0IF 7:0 OSCFIF CSWIF ADTIF ADIF PIR2 7:0 HLVDIF ZCDIF C2IF C1IF RC2IF TX2IF 0x0EC8 PIR3 7:0 0x0EC9 PIR4 7:0 0x0ECA PIR5 7:0 TMR0IF CCP2IE IOCIF INT2IF RC1IF TX1IF BCL2IF SSP2IF BCL1IF SSP1IF TMR6IF TMR5IF TMR4IF TMR3IF TMR2IF TMR1IF TMR5GIF TMR3GIF TMR1GIF CLC4IF CLC3IF CLC2IF CLC1IF CLC5IF 0x0ECB PIR6 7:0 CLC8IF CLC7IF CLC6IF 0x0ECC PIR7 7:0 SCANIF CRCIF NVMIF 0x0ECD WDTCON0 7:0 0x0ECE WDTCON1 7:0 0x0ECF WDTPSL 7:0 CCP2IF WDTPS[4:0] SEN WDTCS[2:0] WINDOW[2:0] PSCNTL[7:0] 0x0ED0 WDTPSH 7:0 WDTTMR 7:0 0x0ED2 CPUDOZE 7:0 0x0ED3 OSCCON1 7:0 NOSC[2:0] NDIV[3:0] 0x0ED4 OSCCON2 7:0 COSC[2:0] CDIV[3:0] 0x0ED5 OSCCON3 7:0 CSWHOLD SOSCPWR 0x0ED6 OSCSTAT 7:0 EXTOR HFOR MFOR LFOR SOR ADOR 0x0ED7 OSCEN 7:0 EXTOEN HFOEN MFOEN LFOEN SOSCEN ADOEN 0x0ED8 OSCTUNE 7:0 OSCFRQ 7:0 0x0EDA VREGCON 7:0 CCP1IF CWG1IF 0x0ED1 0x0ED9 CCP1IE CWG1IE PSCNTH[7:0] WDTTMR[4:0] IDLEN DOZEN ROI STATE DOE ORDY PSCNT[1:0] DOZE[2:0] NOSCR PLLR HFTUN[5:0] HFFRQ[3:0] PMSYS[1:0] 0x0EDB BORCON 7:0 SBOREN 0x0EDC PMD0 7:0 SYSCMD 0x0EDD PMD1 7:0 (c) 2019 Microchip Technology Inc. VREGPM[1:0] BORRDY FVRMD HLVDMD CRCMD SCANMD NVMMD CLKRMD IOCMD TMR6MD TMR5MD TMR4MD TMR3MD TMR2MD TMR1MD TMR0MD Datasheet Preliminary DS40001996C-page 654 PIC18F26/45/46Q10 Register Summary ...........continued Address Name Bit Pos. 0x0EDE PMD2 7:0 DACMD ADCMD 0x0EDF PMD3 7:0 CLC8MD CLC7MD CLC6MD CLC5MD PWM4MD CMP2MD CMP1MD ZCDMD PWM3MD CCP2MD CCP1MD 0x0EE0 PMD4 7:0 UART2MD UART1MD MSSP2MD MSSP1MD CWG1MD 0x0EE1 PMD5 7:0 CLC4MD CLC3MD CLC2MD CLC1MD DSMMD 0x0EE2 RA0PPS 7:0 PPS[4:0] 0x0EE3 RA1PPS 7:0 PPS[4:0] 0x0EE4 RA2PPS 7:0 PPS[4:0] 0x0EE5 RA3PPS 7:0 PPS[4:0] 0x0EE6 RA4PPS 7:0 PPS[4:0] 0x0EE7 RA5PPS 7:0 PPS[4:0] 0x0EE8 RA6PPS 7:0 PPS[4:0] 0x0EE9 RA7PPS 7:0 PPS[4:0] 0x0EEA RB0PPS 7:0 PPS[4:0] 0x0EEB RB1PPS 7:0 PPS[4:0] 0x0EEC RB2PPS 7:0 PPS[4:0] 0x0EED RB3PPS 7:0 PPS[4:0] 0x0EEE RB4PPS 7:0 PPS[4:0] 0x0EEF RB5PPS 7:0 PPS[4:0] 0x0EF0 RB6PPS 7:0 PPS[4:0] 0x0EF1 RB7PPS 7:0 PPS[4:0] 0x0EF2 RC0PPS 7:0 PPS[4:0] 0x0EF3 RC1PPS 7:0 PPS[4:0] 0x0EF4 RC2PPS 7:0 PPS[4:0] 0x0EF5 RC3PPS 7:0 PPS[4:0] 0x0EF6 RC4PPS 7:0 PPS[4:0] 0x0EF7 RC5PPS 7:0 PPS[4:0] 0x0EF8 RC6PPS 7:0 PPS[4:0] 0x0EF9 RC7PPS 7:0 PPS[4:0] 0x0EFA RD0PPS 7:0 PPS[4:0] 0x0EFB RD1PPS 7:0 PPS[4:0] 0x0EFC RD2PPS 7:0 PPS[4:0] 0x0EFD RD3PPS 7:0 PPS[4:0] 0x0EFE RD4PPS 7:0 PPS[4:0] 0x0EFF RD5PPS 7:0 PPS[4:0] 0x0F00 RD6PPS 7:0 PPS[4:0] 0x0F01 RD7PPS 7:0 PPS[4:0] 0x0F02 RE0PPS 7:0 PPS[4:0] 0x0F03 RE1PPS 7:0 PPS[4:0] 0x0F04 RE2PPS 7:0 PPS[4:0] 0x0F05 IOCAF 7:0 IOCAF7 IOCAF6 IOCAF5 IOCAF4 IOCAF3 IOCAF2 IOCAF1 IOCAF0 0x0F06 IOCAN 7:0 IOCAN7 IOCAN6 IOCAN5 IOCAN4 IOCAN3 IOCAN2 IOCAN1 IOCAN0 0x0F07 IOCAP 7:0 IOCAP7 IOCAP6 IOCAP5 IOCAP4 IOCAP3 IOCAP2 IOCAP1 IOCAP0 0x0F08 INLVLA 7:0 INLVLA7 INLVLA6 INLVLA5 INLVLA4 INLVLA3 INLVLA2 INLVLA1 INLVLA0 0x0F09 SLRCONA 7:0 SLRA7 SLRA6 SLRA5 SLRA4 SLRA3 SLRA2 SLRA1 SLRA0 0x0F0A ODCONA 7:0 ODCA7 ODCA6 ODCA5 ODCA4 ODCA3 ODCA2 ODCA1 ODCA0 (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 655 PIC18F26/45/46Q10 Register Summary ...........continued Address Name Bit Pos. 0x0F0B WPUA 7:0 WPUA7 WPUA6 WPUA5 WPUA4 WPUA3 WPUA2 WPUA1 WPUA0 0x0F0C ANSELA 7:0 ANSELA7 ANSELA6 ANSELA5 ANSELA4 ANSELA3 ANSELA2 ANSELA1 ANSELA0 0x0F0D IOCBF 7:0 IOCBF7 IOCBF6 IOCBF5 IOCBF4 IOCBF3 IOCBF2 IOCBF1 IOCBF0 0x0F0E IOCBN 7:0 IOCBN7 IOCBN6 IOCBN5 IOCBN4 IOCBN3 IOCBN2 IOCBN1 IOCBN0 0x0F0F IOCBP 7:0 IOCBP7 IOCBP6 IOCBP5 IOCBP4 IOCBP3 IOCBP2 IOCBP1 IOCBP0 0x0F10 INLVLB 7:0 INLVLB7 INLVLB6 INLVLB5 INLVLB4 INLVLB3 INLVLB2 INLVLB1 INLVLB0 0x0F11 SLRCONB 7:0 SLRB7 SLRB6 SLRB5 SLRB4 SLRB3 SLRB2 SLRB1 SLRB0 0x0F12 ODCONB 7:0 ODCB7 ODCB6 ODCB5 ODCB4 ODCB3 ODCB2 ODCB1 ODCB0 0x0F13 WPUB 7:0 WPUB7 WPUB6 WPUB5 WPUB4 WPUB3 WPUB2 WPUB1 WPUB0 0x0F14 ANSELB 7:0 ANSELB7 ANSELB6 ANSELB5 ANSELB4 ANSELB3 ANSELB2 ANSELB1 ANSELB0 0x0F15 IOCCF 7:0 IOCCF7 IOCCF6 IOCCF5 IOCCF4 IOCCF3 IOCCF2 IOCCF1 IOCCF0 0x0F16 IOCCN 7:0 IOCCN7 IOCCN6 IOCCN5 IOCCN4 IOCCN3 IOCCN2 IOCCN1 IOCCN0 0x0F17 IOCCP 7:0 IOCCP7 IOCCP6 IOCCP5 IOCCP4 IOCCP3 IOCCP2 IOCCP1 IOCCP0 0x0F18 INLVLC 7:0 INLVLC7 INLVLC6 INLVLC5 INLVLC4 INLVLC3 INLVLC2 INLVLC1 INLVLC0 0x0F19 SLRCONC 7:0 SLRC7 SLRC6 SLRC5 SLRC4 SLRC3 SLRC2 SLRC1 SLRC0 0x0F1A ODCONC 7:0 ODCC7 ODCC6 ODCC5 ODCC4 ODCC3 ODCC2 ODCC1 ODCC0 0x0F1B WPUC 7:0 WPUC7 WPUC6 WPUC5 WPUC4 WPUC3 WPUC2 WPUC1 WPUC0 0x0F1C ANSELC 7:0 ANSELC7 ANSELC6 ANSELC5 ANSELC4 ANSELC3 ANSELC2 ANSELC1 ANSELC0 0x0F1D INLVLD 7:0 INLVLD7 INLVLD6 INLVLD5 INLVLD4 INLVLD3 INLVLD2 INLVLD1 INLVLD0 0x0F1E SLRCOND 7:0 SLRD7 SLRD6 SLRD5 SLRD4 SLRD3 SLRD2 SLRD1 SLRD0 0x0F1F ODCOND 7:0 ODCD7 ODCD6 ODCD5 ODCD4 ODCD3 ODCD2 ODCD1 ODCD0 0x0F20 WPUD 7:0 WPUD7 WPUD6 WPUD5 WPUD4 WPUD3 WPUD2 WPUD1 WPUD0 0x0F21 ANSELD 7:0 ANSELD7 ANSELD6 ANSELD5 ANSELD4 ANSELD3 ANSELD2 ANSELD1 ANSELD0 INLVLE2 INLVLE1 INLVLE0 SLRE2 SLRE1 SLRE0 0x0F22 IOCEF 7:0 IOCEF3 0x0F23 IOCEN 7:0 IOCEN3 0x0F24 IOCEP 7:0 IOCEP3 0x0F25 INLVLE 7:0 INLVLE3 0x0F26 SLRCONE 7:0 0x0F27 ODCONE 7:0 0x0F28 WPUE 7:0 0x0F29 ANSELE 7:0 WPUE3 EN OUT ODCE2 ODCE1 ODCE0 WPUE2 WPUE1 WPUE0 ANSELE2 ANSELE1 ANSELE0 INTH INTL 0x0F2A HLVDCON0 7:0 0x0F2B HLVDCON1 7:0 RDY 0x0F2C FVRCON 7:0 FVREN 0x0F2D ZCDCON 7:0 0x0F2E DAC1CON0 7:0 0x0F2F DAC1CON1 7:0 0x0F30 CM2CON0 7:0 HYS SYNC 0x0F31 CM2CON1 7:0 INTP INTN 0x0F32 CM2NCH 7:0 NCH[2:0] 0x0F33 CM2PCH 7:0 0x0F34 CM1CON0 7:0 0x0F35 CM1CON1 0x0F36 CM1NCH 0x0F37 CM1PCH SEL[3:0] FVRRDY TSEN TSRNG SEN OUT POL EN OE1 OE2 CDAFVR[1:0] ADFVR[1:0] INTP PSS[1:0] INTN NSS DAC1R[4:0] EN OUT POL PCH[2:0] EN HYS SYNC 7:0 INTP INTN 7:0 NCH[2:0] 7:0 PCH[2:0] (c) 2019 Microchip Technology Inc. OUT POL Datasheet Preliminary DS40001996C-page 656 PIC18F26/45/46Q10 Register Summary ...........continued Address Name Bit Pos. 0x0F38 CMOUT 7:0 0x0F39 CLKRCON 7:0 0x0F3A CLKRCLK 7:0 0x0F3B CWG1CLK 7:0 0x0F3C CWG1ISM 7:0 0x0F3D CWG1DBR 7:0 DBR[5:0] 0x0F3E CWG1DBF 7:0 DBF[5:0] 0x0F3F CWG1CON0 7:0 0x0F40 CWG1CON1 7:0 0x0F41 CWG1AS0 7:0 MC2OUT EN DC[1:0] MC1OUT DIV[2:0] CLK[3:0] CS ISM[3:0] EN LD MODE[2:0] IN SHUTDOWN REN POLD LSBD[1:0] POLC POLB POLA LSAC[1:0] 0x0F42 CWG1AS1 7:0 AS7E AS6E AS5E AS4E AS3E AS2E AS1E AS0E 0x0F43 CWG1STR 7:0 OVRD OVRC OVRB OVRA STRD STRC STRB STRA 7:0 SCANLADRL[7:0] 0x0F44 SCANLADR 15:8 SCANLADRH[7:0] 23:16 0x0F47 SCANHADR SCANLADRU[5:0] 7:0 SCANHADRL[7:0] 15:8 SCANHADRH[7:0] 23:16 0x0F4A SCANCON0 7:0 0x0F4B SCANTRIG 7:0 SCANHADRU[5:0] SCANEN SCANGO BUSY INVALID INTM MODE[1:0] TSEL[4:0] 0x0F4C MDCON0 7:0 0x0F4D MDCON1 7:0 0x0F4E MDSRC 7:0 0x0F4F MDCARL 7:0 CLS[3:0] 0x0F50 MDCARH 7:0 CHS[3:0] 0x0F51 ADACT 7:0 0x0F52 ADCLK 7:0 0x0F53 ADREF 7:0 0x0F54 ADCON1 7:0 ADPPOL 0x0F55 ADCON2 7:0 ADPSIS 0x0F56 ADCON3 7:0 0x0F57 ADACQ 7:0 0x0F58 ADCAP 7:0 0x0F59 ADPRE 7:0 0x0F5A ADPCH 7:0 0x0F5B ADCON0 7:0 0x0F5C ADPREV 0x0F5E ADRES 0x0F60 ADSTAT 7:0 0x0F61 ADRPT 7:0 0x0F62 ADCNT 7:0 ADCNT[7:0] 7:0 ADSTPTL[7:0] 15:8 ADSTPTH[7:0] 0x0F63 ADSTPT EN OUT OPOL CHPOL CHSYNC BIT CLPOL CLSYNC SRCS[4:0] ADACT[4:0] ADCS[5:0] ADNREF ADIPEN ADPREF[1:0] ADGPOL ADDSEN ADCRS[2:0] ADACLR ADMD[2:0] ADCALC[2:0] ADSOI ADTMD[2:0] ADACQ[7:0] ADCAP[4:0] ADPRE[7:0] ADPCH[5:0] ADON ADCONT ADCS 7:0 ADPREVL[7:0] 15:8 ADPREVH[7:0] 7:0 ADRESL[7:0] 15:8 ADFM ADGO ADRESH[7:0] ADAOV (c) 2019 Microchip Technology Inc. ADUTHR ADLTHR ADMATH ADSTAT[2:0] ADRPT[7:0] Datasheet Preliminary DS40001996C-page 657 PIC18F26/45/46Q10 Register Summary ...........continued Address Name 0x0F65 ADLTH 0x0F67 ADUTH 0x0F69 ADERR 0x0F6B ADACC 0x0F6D ADFLTR 0x0F6F CRCDAT 0x0F71 CRCACC 0x0F73 CRCSHIFT 0x0F75 CRCXOR Bit Pos. 7:0 ADLTHL[7:0] 15:8 ADLTHH[7:0] 7:0 ADUTHL[7:0] 15:8 ADUTHH[7:0] 7:0 ADERRL[7:0] 15:8 ADERRH[7:0] 7:0 ADACCL[7:0] 15:8 ADACCH[7:0] 7:0 ADFLTRL[7:0] 15:8 ADFLTRH[7:0] 7:0 CRCDATL[7:0] 15:8 CRCDATH[7:0] 7:0 CRCACCL[7:0] 15:8 CRCACCH[7:0] 7:0 CRCSHIFTL[7:0] 15:8 CRCSHIFTH[7:0] 7:0 CRCXORL[6:0] 15:8 CRCXORL0 CRCXORH[7:0] 0x0F77 CRCCON0 7:0 0x0F78 CRCCON1 7:0 EN GO BUSY ACCM SHIFTM 7:0 NVMADRL[7:0] 0x0F79 NVMADR 15:8 NVMADRH[7:0] DLEN[3:0] 23:16 NVMADRU[5:0] 7:0 NVMDATL[7:0] 15:8 NVMDATH[7:0] 0x0F7C NVMDAT 0x0F7E Reserved 0x0F7F NVMCON0 7:0 0x0F80 NVMCON1 7:0 0x0F81 NVMCON2 7:0 0x0F82 LATA 7:0 0x0F83 LATB 0x0F84 0x0F85 FULL PLEN[3:0] NVMEN NVMERR Reserved SECER SECWR WR SECRD RD LATA7 LATA6 LATA5 LATA4 LATA3 LATA2 LATA1 LATA0 7:0 LATB7 LATB6 LATB5 LATB4 LATB3 LATB2 LATB1 LATB0 LATC 7:0 LATC7 LATC6 LATC5 LATC4 LATC3 LATC2 LATC1 LATC0 LATD 7:0 LATD7 LATD6 LATD5 LATD4 LATD3 LATD2 LATD1 LATD0 0x0F86 LATE 7:0 LATE2 LATE1 LATE0 NVMCON2[7:0] 0x0F87 TRISA 7:0 TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 0x0F88 TRISB 7:0 TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 0x0F89 TRISC 7:0 TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 0x0F8A TRISD 7:0 TRISD7 TRISD6 TRISD5 TRISD4 TRISD3 TRISD2 TRISD1 TRISD0 0x0F8B TRISE 7:0 TRISE3 TRISE2 TRISE1 TRISE0 0x0F8C PORTA 7:0 RA7 RA6 RA5 RA4 RA3 RA2 RA1 RA0 0x0F8D PORTB 7:0 RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 0x0F8E PORTC 7:0 RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 0x0F8F PORTD 7:0 RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0 0x0F90 PORTE 7:0 RE3 RE2 RE1 RE0 0x0F91 SSP1BUF 7:0 (c) 2019 Microchip Technology Inc. BUF[7:0] Datasheet Preliminary DS40001996C-page 658 PIC18F26/45/46Q10 Register Summary ...........continued Address Name Bit Pos. 0x0F92 SSP1ADD 7:0 0x0F93 SSP1MSK 7:0 ADD[7:0] MSK[6:0] MSK0 0x0F94 SSP1STAT 7:0 SMP CKE D/A P 0x0F95 SSP1CON1 7:0 WCOL SSPOV SSPEN CKP S R/W UA BF 0x0F96 SSP1CON2 7:0 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN 0x0F97 SSP1CON3 7:0 ACKTIM PCIE SCIE BOEN SDAHT SBCDE AHEN DHEN 0x0F98 RC1REG 7:0 0x0F99 TX1REG 7:0 TXREG[7:0] 7:0 SPBRGL[7:0] 15:8 SPBRGH[7:0] SSPM[3:0] RCREG[7:0] 0x0F9A SP1BRG 0x0F9C RC1STA 7:0 SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0x0F9D TX1STA 7:0 CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 0x0F9E BAUD1CON 7:0 ABDOVF RCIDL SCKP BRG16 WUE ABDEN 0x0F9F PWM4DC 0x0FA1 PWM4CON 0x0FA2 PWM3DC 0x0FA4 PWM3CON 7:0 DCL[1:0] 15:8 7:0 DCH[7:0] EN 7:0 OUT POL DCL[1:0] 15:8 7:0 DCH[7:0] EN OUT POL 7:0 CCPRL[7:0] 0x0FA5 CCPR2 0x0FA7 CCP2CON 7:0 0x0FA8 CCP2CAP 7:0 0x0FA9 CCPR1 0x0FAB CCP1CON 7:0 0x0FAC CCP1CAP 7:0 0x0FAD CCPTMRS 7:0 P4TSEL[1:0] P3TSEL[1:0] 0x0FAD CCPTMRS 7:0 P4TSEL[1:0] P3TSEL[1:0] 0x0FAE T6TMR 7:0 TxTMR[7:0] 0x0FAF T6PR 7:0 TxPR[7:0] 0x0FB0 T6CON 7:0 ON 0x0FB1 T6HLT 7:0 PSYNC 0x0FB2 T6CLKCON 7:0 0x0FB3 T6RST 7:0 0x0FB4 T4TMR 7:0 15:8 CCPRH[7:0] EN OUT FMT MODE[3:0] CTS[3:0] 7:0 CCPRL[7:0] 15:8 CCPRH[7:0] EN OUT FMT MODE[3:0] CTS[3:0] CKPS[2:0] CPOL C2TSEL[1:0] C1TSEL[1:0] C2TSEL[1:0] C1TSEL[1:0] OUTPS[3:0] CSYNC MODE[4:0] CS[4:0] RSEL[4:0] TxTMR[7:0] 0x0FB5 T4PR 7:0 0x0FB6 T4CON 7:0 ON TxPR[7:0] 0x0FB7 T4HLT 7:0 PSYNC 0x0FB8 T4CLKCON 7:0 CS[4:0] 0x0FB9 T4RST 7:0 RSEL[4:0] 0x0FBA T2TMR 7:0 CKPS[2:0] CPOL OUTPS[3:0] CSYNC MODE[4:0] TxTMR[7:0] 0x0FBB T2PR 7:0 0x0FBC T2CON 7:0 ON TxPR[7:0] 0x0FBD T2HLT 7:0 PSYNC (c) 2019 Microchip Technology Inc. CKPS[2:0] CPOL CSYNC Datasheet Preliminary OUTPS[3:0] MODE[4:0] DS40001996C-page 659 PIC18F26/45/46Q10 Register Summary ...........continued Address Name Bit Pos. 0x0FBE T2CLKCON 7:0 CS[4:0] 0x0FBF T2RST 7:0 RSEL[4:0] 0x0FC0 TMR5 7:0 TMRxL[7:0] 15:8 TMRxH[7:0] 0x0FC2 T5CON 7:0 0x0FC3 T5GCON 7:0 0x0FC4 TMR5GATE 7:0 0x0FC5 TMR5CLK 7:0 0x0FC6 TMR3 CKPS[1:0] GE GPOL GTM SYNC GSPM GGO/DONE 15:8 TMRxH[7:0] T3CON 7:0 T3GCON 7:0 0x0FCA TMR3GATE 7:0 0x0FCB TMR3CLK 7:0 CKPS[1:0] GE GPOL GTM SYNC GSPM GGO/DONE RD16 ON GSS[4:0] CS[4:0] 7:0 TMRxL[7:0] TMR1 0x0FCE T1CON 7:0 0x0FCF T1GCON 7:0 0x0FD0 TMR1GATE 7:0 GSS[4:0] 0x0FD1 TMR1CLK 7:0 CS[4:0] 15:8 TMRxH[7:0] CKPS[1:0] GE GPOL GTM SYNC GSPM GGO/DONE 0x0FD2 TMR0L 7:0 TMR0L[7:0] 0x0FD3 TMR0H 7:0 TMR0H[7:0] 0x0FD4 T0CON0 7:0 0x0FD5 T0CON1 7:0 0x0FD6 PCON1 7:0 0x0FD7 PCON0 7:0 0x0FD8 STATUS 7:0 T0EN T0OUT T0CS[2:0] T016BIT GVAL T0OUTPS[3:0] T0ASYNC T0CKPS[3:0] RVREG STKOVF 7:0 WDTWV RWDT RMCLR RI POR BOR TO PD N OV Z DC C FSRL[7:0] FSR2 0x0FDB PLUSW2 7:0 PLUSW[7:0] 0x0FDC PREINC2 7:0 PREINC[7:0] 0x0FDD POSTDEC2 7:0 POSTDEC[7:0] 0x0FDE POSTINC2 7:0 POSTINC[7:0] 0x0FDF INDF2 7:0 INDF[7:0] 0x0FE0 BSR 7:0 15:8 7:0 FSRH[3:0] BSR[3:0] FSRL[7:0] 0x0FE1 FSR1 0x0FE3 PLUSW1 7:0 PLUSW[7:0] 0x0FE4 PREINC1 7:0 PREINC[7:0] 0x0FE5 POSTDEC1 7:0 POSTDEC[7:0] 0x0FE6 POSTINC1 7:0 POSTINC[7:0] 0x0FE7 INDF1 7:0 INDF[7:0] 0x0FE8 WREG 7:0 WREG[7:0] 7:0 FSRL[7:0] 15:8 FSRH[3:0] 15:8 (c) 2019 Microchip Technology Inc. RCM STKUNF 0x0FD9 FSR0 ON GVAL 0x0FCC 0x0FE9 RD16 CS[4:0] TMRxL[7:0] 0x0FC9 ON GSS[4:0] 7:0 0x0FC8 RD16 GVAL FSRH[3:0] Datasheet Preliminary DS40001996C-page 660 PIC18F26/45/46Q10 Register Summary ...........continued Address Name Bit Pos. 0x0FEB PLUSW0 7:0 PLUSW[7:0] 0x0FEC PREINC0 7:0 PREINC[7:0] 0x0FED POSTDEC0 7:0 POSTDEC[7:0] 0x0FEE POSTINC0 7:0 POSTINC[7:0] 0x0FEF INDF0 7:0 INDF[7:0] 0x0FF0 ... Reserved 0x0FF1 0x0FF2 INTCON 0x0FF3 PROD 0x0FF5 TABLAT 0x0FF6 TBLPTR 7:0 GIE/GIEH PCL 0x0FFA PCLAT 0x0FFC STKPTR 0x0FFD TOS IPEN INT2EDG PRODH[7:0] 7:0 TABLAT[7:0] 7:0 TBLPTRL[7:0] 15:8 INT0EDG TBLPTRH[7:0] TBLPTR21 TBLPTRU[4:0] 7:0 PCL[7:0] 7:0 PCLATH[7:0] 15:8 PCLATU[4:0] 7:0 STKPTR[4:0] 7:0 TOSL[7:0] 15:8 TOSH[7:0] 23:16 (c) 2019 Microchip Technology Inc. INT1EDG PRODL[7:0] 15:8 23:16 0x0FF9 PEIE/GIEL 7:0 TOSU[4:0] Datasheet Preliminary DS40001996C-page 661 PIC18F26/45/46Q10 In-Circuit Serial ProgrammingTM (ICSPTM) 36. In-Circuit Serial ProgrammingTM (ICSPTM) ICSPTM programming allows customers to manufacture circuit boards with unprogrammed devices. Programming can be done after the assembly process, allowing the device to be programmed with the most recent firmware or a custom firmware. Five pins are needed for ICSPTM programming: * * * * * ICSPCLK ICSPDAT MCLR/VPP VDD VSS In Program/Verify mode the program memory, User IDs and the Configuration Words are programmed through serial communications. The ICSPDAT pin is a bidirectional I/O used for transferring the serial data and the ICSPCLK pin is the clock input. For more information on ICSPTM refer to the " Memory Programming Specification" (DS40001874). 36.1 High-Voltage Programming Entry Mode The device is placed into High-Voltage Programming Entry mode by holding the ICSPCLK and ICSPDAT pins low then raising the voltage on MCLR/VPP to VIHH. 36.2 Low-Voltage Programming Entry Mode (R) The Low-Voltage Programming Entry mode allows the PIC Flash MCUs to be programmed using VDD only, without high voltage. When the LVP bit of Configuration Words is set to `1', the low-voltage ICSP programming entry is enabled. To disable the Low-Voltage ICSP mode, the LVP bit must be programmed to `0'. Entry into the Low-Voltage Programming Entry mode requires the following steps: 1. 2. MCLR is brought to Vil. A 32-bit key sequence is presented on ICSPDAT, while clocking ICSPCLK. Once the key sequence is complete, MCLR must be held at VIL for as long as Program/Verify mode is to be maintained. If low-voltage programming is enabled (LVP = 1), the MCLR Reset function is automatically enabled and cannot be disabled. See the MCLR Section for more information. The LVP bit can only be reprogrammed to `0' by using the High-Voltage Programming mode. Related Links 8.4 MCLR Reset 36.3 Common Programming Interfaces Connection to a target device is typically done through an ICSPTM header. A commonly found connector on development tools is the RJ-11 in the 6P6C (6-pin, 6-connector) configuration. See Figure 36-1. (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 662 PIC18F26/45/46Q10 In-Circuit Serial ProgrammingTM (ICSPTM) Figure 36-1. ICD RJ-11 Style Connector Interface VDD ICSPDAT NC 2 4 6 ICSPCLK 1 3 5 Target VPP/MCLR VSS PC Board Bottom Side Pin Description* 1 = VPP/MCLR 2 = VDD Target 3 = VSS (ground) 4 = ICSPDAT 5 = ICSPCLK 6 = No Connect Another connector often found in use with the PICkitTM programmers is a standard 6-pin header with 0.1 inch spacing. Refer to Figure 36-2. For additional interface recommendations, refer to the specific device programmer manual prior to PCB design. It is recommended that isolation devices be used to separate the programming pins from other circuitry. The type of isolation is highly dependent on the specific application and may include devices such as resistors, diodes, or even jumpers. See Figure 36-3 for more information. Figure 36-2. PICkitTM Programmer Style Connector Interface Pin 1 Indicator 1 2 3 4 5 6 Pin Description1 1 = VPP/MCLR 2 = VDD Target 3 = VSS (ground) 4 = ICSPDAT (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 663 PIC18F26/45/46Q10 In-Circuit Serial ProgrammingTM (ICSPTM) 5 = ICSPCLK 6 = No Connect Note: 1. Note: The 6-pin header (0.100" spacing) accepts 0.025" square pins. Figure 36-3. Typical Connection for ICSPTM Programming External Programming Signals Device to be Programmed VDD VDD VDD VPP MCLR/VPP VSS VSS Data ICSPDAT Clock ICSPCLK * * * To Normal Connections * Isolation devices (as required). (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 664 PIC18F26/45/46Q10 Instruction Set Summary 37. Instruction Set Summary PIC18F26/45/46Q10 devices incorporate the standard set of 75 PIC18 core instructions, as well as an extended set of eight new instructions, for the optimization of code that is recursive or that utilizes a software stack. The extended set is discussed later in this section. 37.1 Standard Instruction Set (R) The standard PIC18 instruction set adds many enhancements to the previous PIC MCU instruction sets, (R) while maintaining an easy migration from these PIC MCU instruction sets. Most instructions are a single program memory word (16 bits), but there are four instructions that require two program memory locations. Each single-word instruction is a 16-bit word divided into an opcode, which specifies the instruction type and one or more operands, which further specify the operation of the instruction. The instruction set is highly orthogonal and is grouped into four basic categories: * * * * Byte-oriented operations Bit-oriented operations Literal operations Control operations The PIC18 instruction set summary in Table 37-2 lists byte-oriented, bit-oriented, literal and control operations. Table 37-1 shows the opcode field descriptions. Most byte-oriented instructions have three operands: 1. 2. 3. The file register (specified by `f') The destination of the result (specified by `d') The accessed memory (specified by `a') The file register designator `f' specifies which file register is to be used by the instruction. The destination designator `d' specifies where the result of the operation is to be placed. If `d' is zero, the result is placed in the WREG register. If `d' is one, the result is placed in the file register specified in the instruction. All bit-oriented instructions have three operands: 1. 2. 3. The file register (specified by `f') The bit in the file register (specified by `b') The accessed memory (specified by `a') The bit field designator `b' selects the number of the bit affected by the operation, while the file register designator `f' represents the number of the file in which the bit is located. The literal instructions may use some of the following operands: * A literal value to be loaded into a file register (specified by `k') * The desired FSR register to load the literal value into (specified by `f') * No operand required (specified by `--') The control instructions may use some of the following operands: * A program memory address (specified by `n') (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 665 PIC18F26/45/46Q10 Instruction Set Summary * The mode of the CALL or RETURN instructions (specified by `s') * The mode of the table read and table write instructions (specified by `m') * No operand required (specified by `--') All instructions are a single word, except for four double-word instructions. These instructions were made double-word to contain the required information in 32 bits. In the second word, the four MSbs are `1's. If this second word is executed as an instruction (by itself), it will execute as a NOP. All single-word instructions are executed in a single instruction cycle, unless a conditional test is true or the Program Counter is changed as a result of the instruction. In these cases, the execution takes two instruction cycles, with the additional instruction cycle(s) executed as a NOP. The double-word instructions execute in two instruction cycles. One instruction cycle consists of four oscillator periods. Thus, for an oscillator frequency of 4 MHz, the normal instruction execution time is 1 s. If a conditional test is true, or the Program Counter is changed as a result of an instruction, the instruction execution time is 2 s. Two-word branch instructions (if true) would take 3 s. Figure 37-1 shows the general formats that the instructions can have. All examples use the convention `nnh' to represent a hexadecimal number. The Instruction Set Summary, shown in Table 37-2, lists the standard instructions recognized by the Microchip Assembler (MPASMTM). 37.1.1 Standard Instruction Set provides a description of each instruction. Table 37-1. Opcode Field Descriptions Field Description RAM access bit a = 0: RAM location in Access RAM (BSR register is ignored) a a = 1: RAM bank is specified by BSR register bbb Bit address within an 8-bit file register (0 to 7). BSR Bank Select Register. Used to select the current RAM bank. C, DC, Z, OV, N ALU Status bits: Carry, Digit Carry, Zero, Overflow, Negative. Destination select bit d = 0: store result in WREG d d = 1: store result in file register f dest Destination: either the WREG register or the specified register file location. f 8-bit Register file address (00h to FFh) or 2-bit FSR designator (0h to 3h). fs 12-bit Register file address (000h to FFFh). This is the source address. (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 666 PIC18F26/45/46Q10 Instruction Set Summary ...........continued Field Description 12-bit Register file address (000h to FFFh). This is the destination address. fd Global Interrupt Enable bit. GIE Literal field, constant data or label (may be either an 8-bit, 12-bit or a 20-bit value). k Label name. label The mode of the TBLPTR register for the table read and table write instructions. Only used with table read and table write instructions: mm n * No change to register (such as TBLPTR with table reads and writes) *+ Post-Increment register (such as TBLPTR with table reads and writes) *- Post-Decrement register (such as TBLPTR with table reads and writes) +* Pre-Increment register (such as TBLPTR with table reads and writes) The relative address (2's complement number) for relative branch instructions or the direct address for CALL/BRANCH and RETURN instructions. PC Program Counter. PCL Program Counter Low Byte. PCH Program Counter High Byte. PCLATH Program Counter High Byte Latch. PCLATU Program Counter Upper Byte Latch. PD Power-down bit. PRODH Product of Multiply High Byte. PRODL Product of Multiply Low Byte. s Fast Call/Return mode select bit s = 0: do not update into/from shadow registers s = 1: certain registers loaded into/from shadow registers (Fast mode) TBLPTR 21-bit Table Pointer (points to a Program Memory location). TABLAT 8-bit Table Latch. (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 667 PIC18F26/45/46Q10 Instruction Set Summary ...........continued Field Description TO Time-out bit. TOS Top-of-Stack. Unused or unchanged. u Watchdog Timer. WDT Working register (accumulator). WREG Don't care (`0' or `1'). The assembler will generate code with x = 0. It is the recommended form of use for compatibility with all Microchip software tools. x zs 7-bit offset value for Indirect Addressing of register files (source). zd 7-bit offset value for Indirect Addressing of register files (destination). {} Optional argument. [text] Indicates an indexed address. The contents of text. (text) [expr]<n> Specifies bit n of the register indicated by the pointer expr. Assigned to. Register bit field. < > In the set of. italics User defined term (font is Courier). (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 668 PIC18F26/45/46Q10 Instruction Set Summary Figure 37-1. General Format for Instructions Byte-oriented file register operations 15 10 9 8 7 OPCODE d a Example Instruction 0 f (FILE #) ADDWF MYREG, W, B d = 0 for result destination to be WREG register d = 1 for result destination to be file register (f) a = 0 to force Access Bank a = 1 for BSR to select bank f = 8-bit file register address Byte to Byte move operations (2-word) 15 12 11 OPCODE 15 0 f (Source FILE #) 12 11 MOVFF MYREG1, MYREG2 0 f (Destination FILE #) 1111 f = 12-bit file register address Bit-oriented file register operations 15 12 11 9 8 7 OPCODE b (BIT #) a 0 f (FILE #) BSF MYREG, bit, B b = 3-bit position of bit in file register (f) a = 0 to force Access Bank a = 1 for BSR to select bank f = 8-bit file register address Literal operations 15 8 7 OP CODE k 0 (l iter al ) MOVLW 7Fh k = 8-bit immediate value Control operations CALL, GOTO and Branch operations 15 8 7 OPCODE 15 0 n<7:0> (literal) 12 11 GOTO Label 0 n<19:8> (literal) 1111 n = 20-bit immediate value 15 8 7 OPCODE 15 S 0 CALL MYFUNC n<7:0> (literal) 12 11 0 n<19:8> (literal) 1111 S = Fast bit 15 OPCODE n 15 OPCODE (c) 2019 Microchip Technology Inc. 11 10 0 BRA MYFUNC <10: 0> (l iter al ) 8 7 0 n<7:0> (literal) Datasheet Preliminary BC MYFUNC DS40001996C-page 669 PIC18F26/45/46Q10 Instruction Set Summary Table 37-2. Instruction Set Mnemonic, Operands Description Cycles 16-Bit Instruction Word MSb LSb Status Affected Notes BYTE-ORIENTED OPERATIONS ADDWF f, d, a Add WREG and f 1 0010 01da ffff ffff C, DC, Z, OV, N 1, 2 ADDWFC f, d, a Add WREG and CARRY bit to f 1 0010 00da ffff ffff C, DC, Z, OV, N 1, 2 ANDWF f, d, a AND WREG with f 1 0001 01da ffff ffff Z, N 1, 2 CLRF f, a Clear f 1 0110 101a ffff ffff Z 2 COMF f, d, a Complement f 1 0001 11da ffff ffff Z, N 1, 2 CPFSEQ f, a Compare f with WREG, skip = 1 (2 or 3) 0110 001a ffff ffff None 4 CPFSGT f, a Compare f with WREG, skip > 1 (2 or 3) 0110 010a ffff ffff None 4 CPFSLT f, a Compare f with WREG, skip < 1 (2 or 3) 0110 000a ffff ffff None 1, 2 DECF f, d, a Decrement f 1 0000 01da ffff ffff C, DC, Z, OV, N 1, 2, 3, 4 f, d, Decrement f, Skip if 1 (2 or 3) a 0 0010 11da ffff ffff None 1, 2, 3, 4 DCFSNZ f, d, Decrement f, Skip if 1 (2 or 3) a Not 0 0100 11da ffff ffff None 1, 2 0010 10da ffff ffff C, DC, Z, OV, N 1, 2, 3, 4 DECFSZ INCF f, d, a Increment f INCFSZ f, d, a Increment f, Skip if 1 (2 or 3) 0 0011 11da ffff ffff None 4 INFSNZ f, d, a Increment f, Skip if 1 (2 or 3) Not 0 0100 11da ffff ffff None 1, 2 IORWF f, d, a Inclusive OR WREG with f 1 0001 00da ffff ffff Z, N 1, 2 MOVF f, d, a Move f 1 0101 00da ffff ffff Z, N 1 (c) 2019 Microchip Technology Inc. 1 Datasheet Preliminary DS40001996C-page 670 PIC18F26/45/46Q10 Instruction Set Summary ...........continued Mnemonic, Operands MOVFF Description Cycles fs, fd Move fs (source) to 1st word 2 fd (destination) 2nd word 16-Bit Instruction Word MSb LSb 1100 ffff ffff ffff 1111 ffff ffff ffff Status Affected None MOVWF f, a Move WREG to f 1 0110 111a ffff ffff None MULWF f, a Multiply WREG with f 1 0000 001a ffff ffff None NEGF f, a Negate f 1 0110 110a ffff ffff C, DC, Z, OV, N RLCF f, d, a Rotate Left f through Carry 1 0011 01da ffff ffff C, Z, N RLNCF f, d, a Rotate Left f (No Carry) 1 0100 01da ffff ffff Z, N RRCF f, d, a Rotate Right f through Carry 1 0011 00da ffff ffff C, Z, N RRNCF f, d, a Rotate Right f (No Carry) 1 0100 00da ffff ffff Z, N SETF f, a Set f 1 0110 00da ffff ffff None Subtract f from WREG with borrow 1 0101 01da ffff ffff C, DC, Z, OV, N f, d, a Subtract WREG from f 1 0101 11da ffff ffff C, DC, Z, OV, N SUBWFB f, d, a Subtract WREG from f with borrow 1 0101 10da ffff ffff C, DC, Z, OV, N SUBFWB f, d, a SUBWF Notes 1, 2 1, 2 1, 2 1, 2 SWAPF f, d, a Swap nibbles in f 1 0011 10da ffff ffff None 4 TSTFSZ f, a Test f, skip if 0 1 (2 or 3) 0110 011a ffff ffff None 1, 2 XORWF f, d, a Exclusive OR WREG with f 1 0001 10da ffff ffff Z, N ffff ffff None BIT-ORIENTED OPERATIONS BCF f, b, a Bit Clear f (c) 2019 Microchip Technology Inc. 1 1001 bbba Datasheet Preliminary 1, 2 DS40001996C-page 671 PIC18F26/45/46Q10 Instruction Set Summary ...........continued Mnemonic, Operands Description Cycles 16-Bit Instruction Word MSb LSb Status Affected Notes BSF f, b, a Bit Set f 1 1000 bbba ffff ffff None 1, 2 BTFSC f, b, a Bit Test f, Skip if Clear 1 (2 or 3) 1011 bbba ffff ffff None 3, 4 BTFSS f, b, a Bit Test f, Skip if Set 1 (2 or 3) 1010 bbba ffff ffff None 3, 4 BTG f, b, a Bit Toggle f 1 0111 bbba ffff ffff None 1, 2 CONTROL OPERATIONS (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 672 PIC18F26/45/46Q10 Instruction Set Summary ...........continued Mnemonic, Operands Description Cycles 16-Bit Instruction Word MSb LSb Status Affected Notes 4 BC n Branch if Carry 1 (2) 1110 0010 nnnn nnnn None BN n Branch if Negative 1 (2) 1110 0110 nnnn nnnn None BNC n Branch if Not Carry 1 (2) 1110 0011 nnnn nnnn None BNN n Branch if Not Negative 1 (2) 1110 0111 nnnn nnnn None BNOV n Branch if Not Overflow 1 (2) 1110 0101 nnnn nnnn None BNZ n Branch if Not Zero 1 (2) 1110 0001 nnnn nnnn None BOV n Branch if Overflow 1 (2) 1110 0100 nnnn nnnn None BRA n Branch Unconditionally 2 1101 0nnn nnnn nnnn None BZ n Branch if Zero 1 (2) 1110 0000 nnnn nnnn None CALL k, s Call subroutine 1st word 2 1110 110s kkkk kkkk None 1111 kkkk kkkk kkkk 2nd word CLRWDT -- Clear Watchdog Timer 1 0000 0000 0000 0100 TO, PD DAW -- Decimal Adjust WREG 1 0000 0000 0000 0111 C GOTO k Go to address 1st word 2 1110 1111 kkkk kkkk None 1111 kkkk kkkk kkkk 2nd word NOP -- No Operation 1 0000 0000 0000 0000 None NOP -- No Operation 1 1111 xxxx xxxx xxxx None POP -- Pop top of return stack (TOS) 1 0000 0000 0000 0110 None PUSH -- Push top of return stack (TOS) 1 0000 0000 0000 0101 None RCALL n Relative Call 2 1101 1nnn nnnn nnnn None 1 0000 0000 1111 Datasheet Preliminary 1111 RESET Software device (c) 2019 Microchip Technology Inc. Reset RETFIE s Return from 2 All DS40001996C-page 673 GIE/GIEH, PIC18F26/45/46Q10 Instruction Set Summary ...........continued Mnemonic, Operands SLEEP -- Description Cycles Go into Standby mode 1 16-Bit Instruction Word MSb 0000 LSb 0000 Status Affected 0000 0011 TO, PD Notes LITERAL OPERATIONS ADDLW k Add literal and WREG 1 0000 1111 kkkk kkkk C, DC, Z, OV, N ANDLW k AND literal with WREG 1 0000 1011 kkkk kkkk Z, N IORLW k Inclusive OR literal with WREG 1 0000 1001 kkkk kkkk Z, N LFSR f, k Move literal (12-bit) 2nd word 2 1110 1110 00ff kkkk None 1111 0000 kkkk kkkk to FSR(f) 1st word MOVLB k Move literal to BSR<3:0> 1 0000 0001 0000 kkkk None MOVLW k Move literal to WREG 1 0000 1110 kkkk kkkk None MULLW k Multiply literal with WREG 1 0000 1101 kkkk kkkk None RETLW k Return with literal in WREG 2 0000 1100 kkkk kkkk None SUBLW k Subtract WREG from literal 1 0000 1000 kkkk kkkk C, DC, Z, OV, N XORLW k Exclusive OR literal with WREG 1 0000 1010 kkkk kkkk Z, N DATA MEMORY PROGRAM MEMORY OPERATIONS TBLRD* Table Read TBLRD*+ 0000 0000 0000 1000 None Table Read with post-increment 0000 0000 0000 1001 None TBLRD*- Table Read with post-decrement 0000 0000 0000 1010 None TBLRD+* Table Read with pre-increment 0000 0000 0000 1011 None TBLWT* Table Write 0000 0000 0000 1100 None (c) 2019 Microchip Technology Inc. 2 2 Datasheet Preliminary DS40001996C-page 674 PIC18F26/45/46Q10 Instruction Set Summary ...........continued Mnemonic, Operands Description Cycles 16-Bit Instruction Word MSb LSb Status Affected TBLWT*+ Table Write with post-increment 0000 0000 0000 1101 None TBLWT*- Table Write with post-decrement 0000 0000 0000 1110 None TBLWT+* Table Write with pre-increment 0000 0000 0000 1111 None Notes Note: 1. When a PORT register is modified as a function of itself (e.g., MOVF PORTB, 1, 0), the value used will be that value present on the pins themselves. For example, if the data latch is `1' for a pin configured as input and is driven low by an external device, the data will be written back with a `0'. 2. If this instruction is executed on the TMR0 register (and where applicable, `d' = 1), the prescaler will be cleared if assigned. 3. If Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second cycle is executed as a NOP. 4. 37.1.1 Some instructions are two-word instructions. The second word of these instructions will be executed as a NOP unless the first word of the instruction retrieves the information embedded in these 16 bits. This ensures that all program memory locations have a valid instruction. Standard Instruction Set ADDLW ADD literal to W Syntax: ADDLW k Operands: 0 k 255 Operation: (W) + k W Status Affected: N, OV, C, DC, Z Encoding: 0000 1111 Description: The contents of W are added to the 8-bit literal `k' and the result is placed in W. Words: 1 Cycles: 1 kkkk kkkk Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read literal `k' Process Data Write to W (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 675 PIC18F26/45/46Q10 Instruction Set Summary Example: ADDLW 15h Before Instruction W = 10h After Instruction W = 25h ADDWF ADD W to f Syntax: ADDWF f {,d {,a}} Operands: 0 f 255 d [0,1] a [0,1] Operation: (W) + (f) dest Status Affected: N, OV, C, DC, Z Encoding: Description: 0010 01da ffff ffff Add W to register `f'. If `d' is `0', the result is stored in W. If `d' is `1', the result is stored back in register `f' (default). If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank. If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See 37.2.3 ByteOriented and Bit-Oriented Instructions in Indexed Literal Offset Mode for details. Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read register `f' Process Data Write to destination Example: (c) 2019 Microchip Technology Inc. ADDWF REG, Datasheet Preliminary 0, 0 DS40001996C-page 676 PIC18F26/45/46Q10 Instruction Set Summary Before Instruction W = 17h REG = 0C2h After Instruction W = 0D9h REG = 0C2h Important: All PIC18 instructions may take an optional label argument preceding the instruction mnemonic for use in symbolic addressing. If a label is used, the instruction format then becomes: {label} instruction argument(s). ADDWFC ADD W and CARRY bit to f Syntax: ADDWFC f {,d {,a}} Operands: 0 f 255 d [0,1] a [0,1] Operation: (W) + (f) + (C) dest Status Affected: N,OV, C, DC, Z Encoding: Description: 0010 00da ffff ffff Add W, the CARRY flag and data memory location `f'. If `d' is `0', the result is placed in W. If `d' is `1', the result is placed in data memory location `f'. If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank. If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh).See 37.2.3 Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode for details. Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read register `f' Process Data Write to destination Example: (c) 2019 Microchip Technology Inc. ADDWFC REG, Datasheet Preliminary 0, 1 DS40001996C-page 677 PIC18F26/45/46Q10 Instruction Set Summary Before Instruction CARRY bit = 1 REG = 02h W = 4Dh After Instruction CARRY bit = 0 REG = 02h W = 50h ANDLW AND literal with W Syntax: ANDLW k Operands: 0 k 255 Operation: (W) .AND. k W Status Affected: N, Z Encoding: 0000 1011 kkkk kkkk Description: The contents of W are AND'ed with the 8-bit literal `k'. The result is placed in W. Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read literal `k' Process Data Write to W Example: ANDLW 05Fh Before Instruction W = A3h After Instruction W = 03h ANDWF AND W with f Syntax: ANDWF f {,d {,a}} Operands: 0 f 255 d [0,1] a [0,1] Operation: (W) .AND. (f) dest (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 678 PIC18F26/45/46Q10 Instruction Set Summary ...........continued ANDWF AND W with f Status Affected: N, Z Encoding: Description: 0001 01da ffff ffff The contents of W are AND'ed with register `f'. If `d' is `0', the result is stored in W. If `d' is `1', the result is stored back in register `f' (default). If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank. If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See 37.2.3 ByteOriented and Bit-Oriented Instructions in Indexed Literal Offset Mode for details. Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read register `f' Process Data Write to destination Example: ANDWF REG, 0, 0 Before Instruction W = 17h REG = C2h After Instruction W = 02h REG = C2h BC Branch if Carry Syntax: BC n Operands: -128 n 127 Operation: if CARRY bit is `1' (PC) + 2 + 2n PC Status Affected: None Encoding: 1110 (c) 2019 Microchip Technology Inc. 0010 Datasheet Preliminary nnnn nnnn DS40001996C-page 679 PIC18F26/45/46Q10 Instruction Set Summary ...........continued BC Branch if Carry Description: If the CARRY bit is `1', then the program will branch. The 2's complement number `2n' is added to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC + 2 + 2n. This instruction is then a 2-cycle instruction. Words: 1 Cycles: 1(2) Q Cycle Activity: If Jump: Q1 Q2 Q3 Q4 Decode Read literal `n' Process Data Write to PC No operation No operation No operation No operation If No Jump: Q1 Q2 Decode Read literal `n' Example: Q3 Q4 Process Data HERE No operation BC 5 Before Instruction PC = address (HERE) After Instruction If CARRY = 1; PC = address (HERE + 12) If CARRY = 0; PC = address (HERE + 2) BCF Bit Clear f Syntax: BCF f, b {,a} Operands: 0 f 255 0b7 a [0,1] Operation: 0 f<b> Status Affected: None (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 680 PIC18F26/45/46Q10 Instruction Set Summary ...........continued BCF Bit Clear f Encoding: Description: 1001 bbba ffff ffff Bit `b' in register `f' is cleared. If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank. If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See 37.2.3 ByteOriented and Bit-Oriented Instructions in Indexed Literal Offset Mode for details. Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read register `f' Process Data Write register `f' Example: BCF FLAG_REG, 7, 0 Before Instruction FLAG_REG = C7h After Instruction FLAG_REG = 47h BN Branch if Negative Syntax: BN n Operands: -128 n 127 Operation: if NEGATIVE bit is `1' (PC) + 2 + 2n PC Status Affected: None Encoding: Description: 1110 0110 nnnn nnnn If the NEGATIVE bit is `1', then the program will branch. The 2's complement number `2n' is added to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC + 2 + 2n. This instruction is then a 2-cycle instruction. (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 681 PIC18F26/45/46Q10 Instruction Set Summary ...........continued BN Branch if Negative Words: 1 Cycles: 1(2) Q Cycle Activity: If Jump: Q1 Q2 Q3 Q4 Decode Read literal `n' Process Data Write to PC No operation No operation No operation No operation If No Jump: Q1 Q2 Decode Q3 Read literal `n' Example: Q4 Process Data HERE No operation BN Jump Before Instruction PC = address (HERE) After Instruction If NEGATIVE = 1; PC = address (Jump) If NEGATIVE = 0; PC = address (HERE + 2) BNC Branch if Not Carry Syntax: BNC n Operands: -128 n 127 Operation: if CARRY bit is `0' (PC) + 2 + 2n PC Status Affected: None Encoding: Description: 1110 0011 nnnn nnnn If the CARRY bit is `0', then the program will branch. The 2's complement number `2n' is added to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC + 2 + 2n. This instruction is then a 2-cycle instruction. (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 682 PIC18F26/45/46Q10 Instruction Set Summary ...........continued BNC Branch if Not Carry Words: 1 Cycles: 1(2) Q Cycle Activity: If Jump: Q1 Q2 Q3 Q4 Decode Read literal `n' Process Data Write to PC No operation No operation No operation No operation If No Jump: Q1 Q2 Decode Read literal `n' Example: HERE Q3 Q4 Process Data No operation BNC Jump Before Instruction PC = address (HERE) After Instruction If CARRY = 0; PC = address (Jump) If CARRY = 1; PC = address (HERE + 2) BNN Branch if Not Negative Syntax: BNN n Operands: -128 n 127 Operation: if NEGATIVE bit is `0' (PC) + 2 + 2n PC Status Affected: None Encoding: 1110 (c) 2019 Microchip Technology Inc. 0111 Datasheet Preliminary nnnn nnnn DS40001996C-page 683 PIC18F26/45/46Q10 Instruction Set Summary ...........continued BNN Branch if Not Negative Description: If the NEGATIVE bit is `0', then the program will branch. The 2's complement number `2n' is added to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC + 2 + 2n. This instruction is then a 2-cycle instruction. Words: 1 Cycles: 1(2) Q Cycle Activity: If Jump: Q1 Q2 Q3 Q4 Decode Read literal `n' Process Data Write to PC No operation No operation No operation No operation If No Jump: Q1 Q2 Decode Read literal `n' Example: HERE Q3 Process Data BNN Q4 No operation Jump Before Instruction PC = address (HERE) After Instruction If NEGATIVE = 0; PC = address (Jump) If NEGATIVE = 1; PC = address (HERE + 2) BNOV Branch if Not Overflow Syntax: BNOV n Operands: -128 n 127 Operation: if OVERFLOW bit is `0' (PC) + 2 + 2n PC Status Affected: None (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 684 PIC18F26/45/46Q10 Instruction Set Summary ...........continued BNOV Branch if Not Overflow Encoding: 1110 0101 nnnn nnnn Description: If the OVERFLOW bit is `0', then the program will branch. The 2's complement number `2n' is added to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC + 2 + 2n. This instruction is then a 2-cycle instruction. Words: 1 Cycles: 1(2) Q Cycle Activity: If Jump: Q1 Q2 Q3 Q4 Decode Read literal `n' Process Data Write to PC No operation No operation No operation No operation If No Jump: Q1 Q2 Decode Read literal `n' Example: HERE Q3 Process Data BNOV Q4 No operation Jump Before Instruction PC = address (HERE) After Instruction If OVERFLOW = 0; PC = address (Jump) If OVERFLOW = 1; PC = address (HERE + 2) BNZ Branch if Not Zero Syntax: BNZ n Operands: -128 n 127 Operation: if ZERO bit is `0' (PC) + 2 + 2n PC (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 685 PIC18F26/45/46Q10 Instruction Set Summary ...........continued BNZ Branch if Not Zero Status Affected: None Encoding: 1110 0001 nnnn nnnn Description: If the ZERO bit is `0', then the program will branch. The 2's complement number `2n' is added to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC + 2 + 2n. This instruction is then a 2-cycle instruction. Words: 1 Cycles: 1(2) Q Cycle Activity: If Jump: Q1 Q2 Q3 Q4 Decode Read literal `n' Process Data Write to PC No operation No operation No operation No operation If No Jump: Q1 Q2 Decode Read literal `n' Example: HERE Q3 Process Data BNZ Q4 No operation Jump Before Instruction PC = address (HERE) After Instruction If ZERO = 0; PC = address (Jump) If ZERO = 1; PC = address (HERE + 2) BRA Unconditional Branch Syntax: BRA n Operands: -1024 n 1023 Operation: (PC) + 2 + 2n PC (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 686 PIC18F26/45/46Q10 Instruction Set Summary ...........continued BRA Unconditional Branch Status Affected: None Encoding: 1101 0nnn nnnn nnnn Description: Add the 2's complement number `2n' to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC + 2 + 2n. This instruction is a 2cycle instruction. Words: 1 Cycles: 2 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read literal `n' Process Data Write to PC No operation No operation No operation No operation Example: HERE BRA Jump Before Instruction PC = address (HERE) After Instruction PC = address (Jump) BSF Bit Set f Syntax: BSF f, b {,a} Operands: 0 f 255 0b7 a [0,1] Operation: 1 f<b> Status Affected: None Encoding: 1000 (c) 2019 Microchip Technology Inc. bbba Datasheet Preliminary ffff ffff DS40001996C-page 687 PIC18F26/45/46Q10 Instruction Set Summary ...........continued BSF Bit Set f Description: Bit `b' in register `f' is set. If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank. If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See 37.2.3 ByteOriented and Bit-Oriented Instructions in Indexed Literal Offset Mode for details. Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read register `f' Process Data Write register `f' Example: BSF FLAG_REG, 7, 1 Before Instruction FLAG_REG = 0Ah After Instruction FLAG_REG = 8Ah BTFSC Bit Test File, Skip if Clear Syntax: BTFSC f, b {,a} Operands: 0 f 255 0b7 a [0,1] Operation: skip if (f<b>) = 0 Status Affected: None Encoding: 1011 (c) 2019 Microchip Technology Inc. bbba Datasheet Preliminary ffff ffff DS40001996C-page 688 PIC18F26/45/46Q10 Instruction Set Summary ...........continued BTFSC Bit Test File, Skip if Clear Description: If bit `b' in register `f' is `0', then the next instruction is skipped. If bit `b' is `0', then the next instruction fetched during the current instruction execution is discarded and a NOP is executed instead, making this a 2-cycle instruction. If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank. If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See 37.2.3 Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode for details. Words: 1 Cycles: 1(2) Note: Three cycles if skip and followed by a 2-word instruction. Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read register `f' Process Data No operation If skip: Q1 Q2 Q3 Q4 No operation No operation No operation No operation If skip and followed by 2-word instruction: Q1 Q2 Q3 Q4 No operation No operation No operation No operation No operation No operation No operation No operation Example: (c) 2019 Microchip Technology Inc. HERE FALSE TRUE BTFSC : : Datasheet Preliminary FLAG, 1, 0 DS40001996C-page 689 PIC18F26/45/46Q10 Instruction Set Summary Before Instruction PC = address (HERE) After Instruction If FLAG<1> = 0; PC = address (TRUE) If FLAG<1> = 1; PC = address (FALSE) BTFSS Bit Test File, Skip if Set Syntax: BTFSS f, b {,a} Operands: 0 f 255 0b<7 a [0,1] Operation: skip if (f<b>) = 1 Status Affected: None Encoding: Description: 1010 bbba ffff ffff If bit `b' in register `f' is `1', then the next instruction is skipped. If bit `b' is `1', then the next instruction fetched during the current instruction execution is discarded and a NOP is executed instead, making this a 2-cycle instruction. If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank. If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See 37.2.3 Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode for details. Words: 1 Cycles: 1(2) Note: Three cycles if skip and followed by a 2-word instruction. Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read register `f' Process Data No operation If skip: Q1 (c) 2019 Microchip Technology Inc. Q2 Q3 Datasheet Preliminary Q4 DS40001996C-page 690 PIC18F26/45/46Q10 Instruction Set Summary No operation No operation No operation No operation If skip and followed by 2-word instruction: Q1 Q2 Q3 Q4 No operation No operation No operation No operation No operation No operation No operation No operation Example: HERE FALSE TRUE BTFSS : : FLAG, 1, 0 Before Instruction PC = address (HERE) After Instruction If FLAG<1> = 0; PC = address (FALSE) If FLAG<1> = 1; PC = address (TRUE) BTG Bit Toggle f Syntax: BTG f, b {,a} Operands: 0 f 255 0b<7 a [0,1] Operation: (f<b>) f<b> Status Affected: None Encoding: Description: 0111 bbba ffff ffff Bit `b' in data memory location `f' is inverted. If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank. If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See 37.2.3 ByteOriented and Bit-Oriented Instructions in Indexed Literal Offset Mode for details. Words: 1 Cycles: 1 (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 691 PIC18F26/45/46Q10 Instruction Set Summary Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read register `f' Process Data Write register `f' Example: BTG PORTC, 4, 0 Before Instruction: PORTC = 0111 0101 [75h] After Instruction: PORTC = 0110 0101 [65h] BOV Branch if Overflow Syntax: BOV n Operands: -128 n 127 Operation: if OVERFLOW bit is `1' (PC) + 2 + 2n PC Status Affected: None Encoding: 1110 0100 nnnn nnnn Description: If the OVERFLOW bit is `1', then the program will branch. The 2's complement number `2n' is added to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC + 2 + 2n. This instruction is then a 2-cycle instruction. Words: 1 Cycles: 1(2) Q Cycle Activity: If Jump: Q1 Q2 Q3 Q4 Decode Read literal `n' Process Data Write to PC No operation No operation No operation No operation Q2 Q3 Q4 If No Jump: Q1 (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 692 PIC18F26/45/46Q10 Instruction Set Summary Decode Read literal `n' Example: HERE Process Data No operation BOV Jump Before Instruction PC = address (HERE) After Instruction If OVERFLOW = 1; PC = address (Jump) If OVERFLOW = 0; PC = address (HERE + 2) BZ Branch if Zero Syntax: BZ n Operands: -128 n 127 Operation: if ZERO bit is `1' (PC) + 2 + 2n PC Status Affected: None Encoding: 1110 0000 nnnn nnnn Description: If the ZERO bit is `1', then the program will branch. The 2's complement number `2n' is added to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC + 2 + 2n. This instruction is then a 2-cycle instruction. Words: 1 Cycles: 1(2) Q Cycle Activity: If Jump: Q1 Q2 Q3 Q4 Decode Read literal `n' Process Data Write to PC No operation No operation No operation No operation If No Jump: Q1 Q2 Q3 Q4 Decode Read literal `n' Process Data No operation (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 693 PIC18F26/45/46Q10 Instruction Set Summary Example: HERE BZ Jump Before Instruction PC = address (HERE) After Instruction If ZERO = 1; PC = address (Jump) If ZERO = 0; PC = address (HERE + 2) CALL Subroutine Call Syntax: CALL k {,s} Operands: 0 k 1048575 s [0,1] Operation: (PC) + 4 TOS, k PC<20:1>, if s = 1 (W) WS, (Status) STATUSS, (BSR) BSRS Status Affected: None Encoding: 1st word (k<7:0>) 1110 1111 2nd word(k<19:8>) 110s k19kkk k7kkk kkkk kkkk0 kkkk8 Description: Subroutine call of entire 2-Mbyte memory range. First, return address (PC + 4) is pushed onto the return stack. If `s' = 1, the W, Status and BSR registers are also pushed into their respective shadow registers, WS, STATUSS and BSRS. If `s' = 0, no update occurs (default). Then, the 20-bit value `k' is loaded into PC<20:1>. CALL is a 2-cycle instruction. Words: 2 Cycles: 2 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read literal `k'<7:0>, PUSH PC to stack Read literal `k'<19:8>, Write to PC (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 694 PIC18F26/45/46Q10 Instruction Set Summary No operation No operation No operation Example: HERE No operation CALL THERE, 1 Before Instruction PC = address (HERE) After Instruction PC = address (THERE) TOS = address (HERE + 4) WS = W BSRS = BSR STATUSS = Status CLRF Clear f Syntax: CLRF f {,a} Operands: 0 f 255 a [0,1] Operation: 000h f 1Z Status Affected: Z Encoding: Description: 0110 101a ffff ffff Clears the contents of the specified register. If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank. If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See 37.2.3 ByteOriented and Bit-Oriented Instructions in Indexed Literal Offset Mode for details. Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read register `f' Process Data Write register `f' (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 695 PIC18F26/45/46Q10 Instruction Set Summary Example: CLRF FLAG_REG, 1 Before Instruction FLAG_REG = 5Ah After Instruction FLAG_REG = 00h CLRWDT Clear Watchdog Timer Syntax: CLRWDT Operands: None Operation: 000h WDT, 000h WDT postscaler, 1 TO, 1 PD Status Affected: TO, PD Encoding: 0000 0000 0000 0100 Description: CLRWDT instruction resets the Watchdog Timer. It also resets the postscaler of the WDT. Status bits, TO and PD, are set. Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode No operation Process Data No operation Example: CLRWDT Before Instruction WDT Counter = ? After Instruction WDT Counter = 00h WDT Postscaler = 0 TO = 1 PD = 1 (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 696 PIC18F26/45/46Q10 Instruction Set Summary COMF Complement f Syntax: COMF f {,d {,a}} Operands: 0 f 255 d [0,1] a [0,1] Operation: (f) dest Status Affected: N, Z Encoding: Description: 0001 11da ffff ffff The contents of register `f' are complemented. If `d' is `0', the result is stored in W. If `d' is `1', the result is stored back in register `f' (default). If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank. If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See 37.2.3 ByteOriented and Bit-Oriented Instructions in Indexed Literal Offset Mode for details. Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read register `f' Process Data Write to destination Example: COMF REG, 0, 0 Before Instruction REG = 13h After Instruction REG = 13h W = ECh CPFSEQ Compare f with W, skip if f = W Syntax: CPFSEQ f {,a} Operands: 0 f 255 a [0,1] (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 697 PIC18F26/45/46Q10 Instruction Set Summary ...........continued CPFSEQ Compare f with W, skip if f = W Operation: (f) - (W), skip if (f) = (W) (unsigned comparison) Status Affected: None Encoding: 0110 Description: 001a ffff ffff Compares the contents of data memory location `f' to the contents of W by performing an unsigned subtraction. If `f' = W, then the fetched instruction is discarded and a NOP is executed instead, making this a 2-cycle instruction. If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank. If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See 37.2.3 Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode for details. Words: 1 Cycles: 1(2) Note: Three cycles if skip and followed by a 2-word instruction. Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read register `f' Process Data No operation If skip: Q1 Q2 Q3 Q4 No operation No operation No operation No operation If skip and followed by 2-word instruction: Q1 Q2 Q3 Q4 No operation No operation No operation No operation No operation No operation No operation No operation (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 698 PIC18F26/45/46Q10 Instruction Set Summary Example: HERE NEQUAL EQUAL CPFSEQ REG, 0 : : Before Instruction PC Address = HERE W=? REG = ? After Instruction If REG = W; PC = Address (EQUAL) If REG ; PC = Address (NEQUAL) CPFSGT Compare f with W, skip if f > W Syntax: CPFSGT f {,a} Operands: 0 f 255 a [0,1] Operation: (f) - (), skip if (f) > (W) (unsigned comparison) Status Affected: None Encoding: Description: 0110 010a ffff ffff Compares the contents of data memory location `f' to the contents of the W by performing an unsigned subtraction. If the contents of `f' are greater than the contents of WREG, then the fetched instruction is discarded and a NOP is executed instead, making this a 2-cycle instruction. If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank. If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See 37.2.3 Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode for details. Words: 1 Cycles: 1(2) Note: Three cycles if skip and followed by a 2-word instruction. Q Cycle Activity: (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 699 PIC18F26/45/46Q10 Instruction Set Summary Q1 Q2 Q3 Q4 Decode Read register `f' Process Data No operation If skip: Q1 Q2 Q3 Q4 No operation No operation No operation No operation If skip and followed by 2-word instruction: Q1 Q2 Q3 Q4 No operation No operation No operation No operation No operation No operation No operation No operation Example: HERE NGREATER GREATER CPFSGT REG, 0 : : Before Instruction PC = Address (HERE) W=? After Instruction If REG > W; PC = Address (GREATER) If REG W; PC = Address (NGREATER) CPFSLT Compare f with W, skip if f < W Syntax: CPFSLT f {,a} Operands: 0 f 255 a [0,1] Operation: (f) - (), skip if (f) < (W) (unsigned comparison) Status Affected: None Encoding: 0110 (c) 2019 Microchip Technology Inc. 000a Datasheet Preliminary ffff ffff DS40001996C-page 700 PIC18F26/45/46Q10 Instruction Set Summary ...........continued CPFSLT Compare f with W, skip if f < W Description: Compares the contents of data memory location `f' to the contents of W by performing an unsigned subtraction. If the contents of `f' are less than the contents of W, then the fetched instruction is discarded and a NOP is executed instead, making this a 2-cycle instruction. If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank. Words: 1 Cycles: 1(2) Note: Three cycles if skip and followed by a 2-word instruction. Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read register `f' Process Data No operation If skip: Q1 Q2 Q3 Q4 No operation No operation No operation No operation If skip and followed by 2-word instruction: Q1 Q2 Q3 Q4 No operation No operation No operation No operation No operation No operation No operation No operation Example: (c) 2019 Microchip Technology Inc. HERE NLESS LESS CPFSLT REG, 1 : : Datasheet Preliminary DS40001996C-page 701 PIC18F26/45/46Q10 Instruction Set Summary Before Instruction PC = Address (HERE) W=? After Instruction If REG < W; PC = Address (LESS) If REG W; PC = Address (NLESS) DAW Decimal Adjust W Register Syntax: DAW Operands: None Operation: If [W<3:0> > 9] or [DC = 1] then (W<3:0>) + 6 W<3:0>; else (W<3:0>) W<3:0>; If [W<7:4> + DC > 9] or [C = 1] then (W<7:4>) + 6 + DC W<7:4> ; else (W<7:4>) + DC W<7:4> Status Affected: C Encoding: 0000 0000 0000 0111 Description: DAW adjusts the 8-bit value in W, resulting from the earlier addition of two variables (each in packed BCD format) and produces a correct packed BCD result. Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read register W Process Data Write W Example1: (c) 2019 Microchip Technology Inc. DAW Datasheet Preliminary DS40001996C-page 702 PIC18F26/45/46Q10 Instruction Set Summary Before Instruction W = A5h C=0 DC = 0 After Instruction W = 05h C=1 DC = 0 Example 2: Before Instruction W = CEh C=0 DC = 0 After Instruction W = 34h C=1 DC = 0 DECF Decrement f Syntax: DECF f {,d {,a}} Operands: 0 f 255 d [0,1] a [0,1] Operation: (f) - 1 dest Status Affected: C, DC, N, OV, Z Encoding: Description: 0000 01da ffff ffff Decrement register `f'. If `d' is `0', the result is stored in W. If `d' is `1', the result is stored back in register `f' (default). If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank. If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See 37.2.3 ByteOriented and Bit-Oriented Instructions in Indexed Literal Offset Mode for details. Words: 1 (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 703 PIC18F26/45/46Q10 Instruction Set Summary ...........continued DECF Decrement f Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read register `f' Process Data Write to destination Example: DECF CNT, 1, 0 Before Instruction CNT = 01h Z=0 After Instruction CNT = 00h Z=1 DECFSZ Decrement f, skip if 0 Syntax: DECFSZ f {,d {,a}} Operands: 0 f 255 d [0,1] a [0,1] Operation: (f) - 1 dest, skip if result = 0 Status Affected: None Encoding: Description: 0010 11da ffff ffff The contents of register `f' are decremented. If `d' is `0', the result is placed in W. If `d' is `1', the result is placed back in register `f' (default). If the result is `0', the next instruction, which is already fetched, is discarded and a NOP is executed instead, making it a 2-cycle instruction. If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank. If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See 37.2.3 Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode for details. Words: 1 (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 704 PIC18F26/45/46Q10 Instruction Set Summary ...........continued DECFSZ Decrement f, skip if 0 Cycles: 1(2) Note: Three cycles if skip and followed by a 2-word instruction. Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read register `f' Process Data Write to destination If skip: Q1 Q2 Q3 Q4 No operation No operation No operation No operation If skip and followed by 2-word instruction: Q1 Q2 Q3 Q4 No operation No operation No operation No operation No operation No operation No operation No operation Example: HERE DECFSZ GOTO LOOP CONTINUE CNT, 1, 1 Before Instruction PC = Address (HERE) After Instruction CNT = CNT - 1 If CNT = 0; PC = Address (CONTINUE) If CNT 0; PC = Address (HERE + 2) DCFSNZ Decrement f, skip if not 0 Syntax: DCFSNZ f {,d {,a}} (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 705 PIC18F26/45/46Q10 Instruction Set Summary ...........continued DCFSNZ Decrement f, skip if not 0 Operands: 0 f 255 d [0,1] a [0,1] Operation: (f) - 1 dest, skip if result 0 Status Affected: None Encoding: 0100 Description: 11da ffff ffff The contents of register `f' are decremented. If `d' is `0', the result is placed in W. If `d' is `1', the result is placed back in register `f' (default). If the result is not `0', the next instruction, which is already fetched, is discarded and a NOP is executed instead, making it a 2-cycle instruction. If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank. If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See 37.2.3 Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode for details. Words: 1 Cycles: 1(2) Note: Three cycles if skip and followed by a 2-word instruction. Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read register `f' Process Data Write to destination If skip: Q1 Q2 Q3 Q4 No operation No operation No operation No operation If skip and followed by 2-word instruction: Q1 (c) 2019 Microchip Technology Inc. Q2 Q3 Datasheet Preliminary Q4 DS40001996C-page 706 PIC18F26/45/46Q10 Instruction Set Summary No operation No operation No operation No operation No operation No operation No operation No operation Example: HERE ZERO NZERO DCFSNZ : : TEMP, 1, 0 Before Instruction TEMP = ? After Instruction TEMP = TEMP - 1, If TEMP = 0; PC = Address (ZERO) If TEMP 0; PC = Address (NZERO) GOTO Unconditional Branch Syntax: GOTO k Operands: 0 k 1048575 Operation: k PC<20:1> Status Affected: None Encoding: 1st word (k<7:0>) 1110 1111 2nd word(k<19:8>) 1111 k19kkk k7kkk kkkk kkkk0 kkkk8 Description: GOTO allows an unconditional branch anywhere within entire 2-Mbyte memory range. The 20-bit value `k' is loaded into PC<20:1>. GOTO is always a 2-cycle instruction. Words: 2 Cycles: 2 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read literal `k'<7:0>, No operation Read literal `k'<19:8>, Write to PC No operation No operation No operation No operation (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 707 PIC18F26/45/46Q10 Instruction Set Summary Example: GOTO THERE After Instruction PC = Address (THERE) INCF Increment f Syntax: INCF f {,d {,a}} Operands: 0 f 255 d [0,1] a [0,1] Operation: (f) + 1 dest Status Affected: C, DC, N, OV, Z Encoding: Description: 0010 10da ffff ffff The contents of register `f' are incremented. If `d' is `0', the result is placed in W. If `d' is `1', the result is placed back in register `f' (default). If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank. If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See 37.2.3 ByteOriented and Bit-Oriented Instructions in Indexed Literal Offset Mode for details. Words: 1 Cycles: 1 Q Cycle Activity: Q1 Decode Q2 Read register `f' Example: (c) 2019 Microchip Technology Inc. Q3 Q4 Process Data INCF Write to destination CNT, Datasheet Preliminary 1, 0 DS40001996C-page 708 PIC18F26/45/46Q10 Instruction Set Summary Before Instruction CNT = FFh Z=0 C=? DC = ? After Instruction CNT = 00h Z=1 C=1 DC = 1 INCFSZ Increment f, skip if 0 Syntax: INCFSZ f {,d {,a}} Operands: 0 f 255 d [0,1] a [0,1] Operation: (f) + 1 dest, skip if result = 0 Status Affected: None Encoding: Description: 0011 11da ffff ffff The contents of register `f' are incremented. If `d' is `0', the result is placed in W. If `d' is `1', the result is placed back in register `f' (default). If the result is `0', the next instruction, which is already fetched, is discarded and a NOP is executed instead, making it a 2-cycle instruction. If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank. If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See 37.2.3 Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode for details. Words: 1 Cycles: 1(2) Note: Three cycles if skip and followed by a 2-word instruction. Q Cycle Activity: Q1 (c) 2019 Microchip Technology Inc. Q2 Q3 Datasheet Preliminary Q4 DS40001996C-page 709 PIC18F26/45/46Q10 Instruction Set Summary Decode Read register `f' Process Data Write to destination If skip: Q1 Q2 Q3 Q4 No operation No operation No operation No operation If skip and followed by 2-word instruction: Q1 Q2 Q3 Q4 No operation No operation No operation No operation No operation No operation No operation No operation Example: HERE NZERO ZERO INCFSZ : : CNT, 1, 0 Before Instruction PC = Address (HERE) After Instruction CNT = CNT + 1 If CNT = 0; PC = Address (ZERO) If CNT 0; PC = Address (NZERO) INFSNZ Increment f, skip if not 0 Syntax: INFSNZ f {,d {,a}} Operands: 0 f 255 d [0,1] a [0,1] Operation: (f) + 1 dest, skip if result 0 Status Affected: None Encoding: 0100 (c) 2019 Microchip Technology Inc. 10da Datasheet Preliminary ffff ffff DS40001996C-page 710 PIC18F26/45/46Q10 Instruction Set Summary ...........continued INFSNZ Increment f, skip if not 0 Description: The contents of register `f' are incremented. If `d' is `0', the result is placed in W. If `d' is `1', the result is placed back in register `f' (default). If the result is not `0', the next instruction, which is already fetched, is discarded and a NOP is executed instead, making it a 2-cycle instruction. If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank. If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See 37.2.3 Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode for details. Words: 1 Cycles: 1(2) Note: Three cycles if skip and followed by a 2-word instruction. Q Cycle Activity: Q1 Q2 Decode Q3 Read register `f' Q4 Process Data Write to destination If skip: Q1 No operation Q2 Q3 No operation No operation Q4 No operation If skip and followed by 2-word instruction: Q1 Q2 Q3 Q4 No operation No operation No operation No operation No operation No operation No operation No operation Example: (c) 2019 Microchip Technology Inc. HERE ZERO NZERO INFSNZ REG, 1, 0 Datasheet Preliminary DS40001996C-page 711 PIC18F26/45/46Q10 Instruction Set Summary Before Instruction PC = Address (HERE) After Instruction REG = REG + 1 If REG 0; PC = Address (NZERO) If REG = 0; PC = Address (ZERO) IORLW Inclusive OR literal with W Syntax: IORLW k Operands: 0 k 255 Operation: (W) .OR. k W Status Affected: N, Z Encoding: 0000 1001 kkkk kkkk Description: The contents of W are ORed with the 8-bit literal `k'. The result is placed in W. Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read literal `k' Process Data Write to W Example: IORLW 35h Before Instruction W = 9Ah After Instruction W = BFh IORWF Inclusive OR W with f Syntax: IORWF f {,d {,a}} Operands: 0 f 255 d [0,1] a [0,1] (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 712 PIC18F26/45/46Q10 Instruction Set Summary ...........continued IORWF Inclusive OR W with f Operation: (W) .OR. (f) dest Status Affected: N, Z Encoding: Description: 0001 00da ffff ffff Inclusive OR W with register `f'. If `d' is `0', the result is placed in W. If `d' is `1', the result is placed back in register `f' (default). If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank. If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See 37.2.3 ByteOriented and Bit-Oriented Instructions in Indexed Literal Offset Mode for details. Words: 1 Cycles: 1 Q Cycle Activity: Q1 Decode Q2 Read register `f' Example: Q3 Process Data IORWF Q4 Write to destination RESULT, 0, 1 Before Instruction RESULT = 13h W = 91h After Instruction RESULT = 13h W = 93h LFSR Load FSR Syntax: LFSR f, k Operands: 0f2 0 k 4095 Operation: k FSRf Status Affected: None (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 713 PIC18F26/45/46Q10 Instruction Set Summary ...........continued LFSR Load FSR Encoding: 1110 1111 1110 0000 00ff k7kkk k11kkk kkkk Description: The 12-bit literal `k' is loaded into the File Select Register pointed to by `f'. Words: 2 Cycles: 2 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read literal `k' MSB Process Data Write literal `k' MSB to FSRfH Decode Read literal `k' LSB Process Data Write literal `k' to FSRfL Example: LFSR 2, 3ABh After Instruction FSR2H = 03h FSR2L = ABh MOVF Move f Syntax: MOVF f {,d {,a}} Operands: 0 f 255 d [0,1] a [0,1] Operation: f dest Status Affected: N, Z Encoding: Description: 0101 00da ffff ffff The contents of register `f' are moved to a destination dependent upon the status of `d'. If `d' is `0', the result is placed in W. If `d' is `1', the result is placed back in register `f' (default). Location `f' can be anywhere in the 256-byte bank. If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank. If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See 37.2.3 ByteOriented and Bit-Oriented Instructions in Indexed Literal Offset Mode for details. (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 714 PIC18F26/45/46Q10 Instruction Set Summary ...........continued MOVF Move f Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read register `f' Process Data Write W Example: MOVF REG, 0, 0 Before Instruction REG = 22h W = FFh After Instruction REG = 22h W = 22h MOVFF Move f to f Syntax: MOVFF fs,fd Operands: 0 fs 4095 0 fd 4095 Operation: (fs) fd Status Affected: None Encoding: 1st word (source) 2nd word (destin.) 1100 1111 (c) 2019 Microchip Technology Inc. ffff ffff Datasheet Preliminary ffff ffff ffffs ffffd DS40001996C-page 715 PIC18F26/45/46Q10 Instruction Set Summary ...........continued MOVFF Move f to f Description: The contents of source register `fs' are moved to destination register `fd'. Location of source `fs' can be anywhere in the 4096-byte data space (000h to FFFh) and location of destination `fd' can also be anywhere from 000h to FFFh. Either source or destination can be W (a useful special situation). MOVFF is particularly useful for transferring a data memory location to a peripheral register (such as the transmit buffer or an I/O port). The MOVFF instruction cannot use the PCL, TOSU, TOSH or TOSL as the destination register. Words: 2 Cycles: 2 (3) Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read register `f' (src) Process Data No operation Decode No operation No dummy read No operation Write register `f' (dest) Example: MOVFF REG1, REG2 Before Instruction REG1 = 33h REG2 = 11h After Instruction REG1 = 33h REG2 = 33h MOVLB Move literal to low nibble in BSR Syntax: MOVLW k Operands: 0 k 255 Operation: k BSR Status Affected: None Encoding: 0000 (c) 2019 Microchip Technology Inc. 0001 Datasheet Preliminary kkkk kkkk DS40001996C-page 716 PIC18F26/45/46Q10 Instruction Set Summary ...........continued MOVLB Move literal to low nibble in BSR Description: The 8-bit literal `k' is loaded into the Bank Select Register (BSR). The value of BSR<7:4> always remains `0', regardless of the value of k7:k4. Words: 1 Cycles: 1 Q Cycle Activity: Q1 Decode Q2 Q3 Read literal `k' Q4 Process Data Example: Write literal `k' to BSR MOVLB 5 Before Instruction BSR Register = 02h After Instruction BSR Register = 05h MOVLW Move literal to W Syntax: MOVLW k Operands: 0 k 255 Operation: kW Status Affected: None Encoding: 0000 1110 Description: The 8-bit literal `k' is loaded into W. Words: 1 Cycles: 1 kkkk kkkk Q Cycle Activity: Q1 Decode Q2 Read literal `k' Example: Q3 Process Data MOVLW Q4 Write to W 5Ah After Instruction W = 5Ah (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 717 PIC18F26/45/46Q10 Instruction Set Summary MOVWF Move W to f Syntax: MOVWF f {,a} Operands: 0 f 255 a [0,1] Operation: (W) f Status Affected: None Encoding: Description: 0110 111a ffff ffff Move data from W to register `f'. Location `f' can be anywhere in the 256-byte bank. If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank. If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See 37.2.3 ByteOriented and Bit-Oriented Instructions in Indexed Literal Offset Mode for details. Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read register `f' Process Data Write register `f' Example: MOVWF REG, 0 Before Instruction W = 4Fh REG = FFh After Instruction W = 4Fh REG = 4Fh MULLW Multiply literal with W Syntax: MULLW k Operands: 0 k 255 Operation: (W) x k PRODH:PRODL (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 718 PIC18F26/45/46Q10 Instruction Set Summary ...........continued MULLW Multiply literal with W Status Affected: None Encoding: 0000 Description: 1101 kkkk kkkk An unsigned multiplication is carried out between the contents of W and the 8-bit literal `k'. The 16-bit result is placed in the PRODH:PRODL register pair. PRODH contains the high byte. W is unchanged. None of the Status flags are affected. Note that neither overflow nor carry is possible in this operation. A zero result is possible but not detected. Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Decode Read literal `k' Example: Q3 Process Data MULLW Q4 Write registers PRODH: PRODL 0C4h Before Instruction W = E2h PRODH = ? PRODL = ? After Instruction W = E2h PRODH = ADh PRODL = 08h MULWF Multiply W with f Syntax: MULWF f {,a} Operands: 0 f 255 a [0,1] Operation: (W) x (f) PRODH:PRODL (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 719 PIC18F26/45/46Q10 Instruction Set Summary ...........continued MULWF Multiply W with f Status Affected: None Encoding: Description: 0000 001a ffff ffff An unsigned multiplication is carried out between the contents of W and the register file location `f'. The 16-bit result is stored in the PRODH:PRODL register pair. PRODH contains the high byte. Both W and `f' are unchanged. None of the Status flags are affected. Note that neither overflow nor carry is possible in this operation. A zero result is possible but not detected. If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank. If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 35.2.3 "Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode" for details. Words: 1 Cycles: 1 Q Cycle Activity: Q1 Decode Q2 Read register `f' Example: Q3 Process Data MULWF Q4 Write registers PRODH: PRODL REG, 1 Before Instruction W = C4h REG = B5h PRODH = ? PRODL = ? After Instruction W = C4h REG = B5h PRODH = 8Ah PRODL = 94h (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 720 PIC18F26/45/46Q10 Instruction Set Summary NEGF Negate f Syntax: NEGF f {,a} Operands: 0 f 255 a [0,1] Operation: (f)+1f Status Affected: N, OV, C, DC, Z Encoding: Description: 0110 110a ffff ffff Location `f' is negated using two's complement. The result is placed in the data memory location `f'. If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank. If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See 37.2.3 ByteOriented and Bit-Oriented Instructions in Indexed Literal Offset Mode for details. Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read register `f' Process Data Write register `f' Example: NEGF REG, 1 Before Instruction REG = 0011 1010 [3Ah] After Instruction REG = 1100 0110 [C6h] NOP No Operation Syntax: NOP Operands: None Operation: No operation Status Affected: None Encoding: (c) 2019 Microchip Technology Inc. 0000 1111 0000 xxxx Datasheet Preliminary 0000 xxxx 0000 xxxx DS40001996C-page 721 PIC18F26/45/46Q10 Instruction Set Summary ...........continued NOP No Operation Description: No operation. Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode No operation No operation No operation Example: None. POP Pop Top of Return Stack Syntax: POP Operands: None Operation: (TOS) bit bucket Status Affected: None Encoding: 0000 0000 0000 0110 Description: The TOS value is pulled off the return stack and is discarded. The TOS value then becomes the previous value that was pushed onto the return stack. This instruction is provided to enable the user to properly manage the return stack to incorporate a software stack. Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode No operation POP TOS value No operation Example: (c) 2019 Microchip Technology Inc. POP GOTO Datasheet Preliminary NEW DS40001996C-page 722 PIC18F26/45/46Q10 Instruction Set Summary Before Instruction TOS = 0031A2h Stack (1 level down) = 014332h After Instruction TOS = 014332h PC = NEW PUSH Push Top of Return Stack Syntax: PUSH Operands: None Operation: (PC + 2) TOS Status Affected: None Encoding: 0000 0000 0000 0101 Description: The PC + 2 is pushed onto the top of the return stack. The previous TOS value is pushed down on the stack. This instruction allows implementing a software stack by modifying TOS and then pushing it onto the return stack. Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode PUSH PC + 2 onto return stack No operation No operation Example: PUSH Before Instruction TOS = 345Ah PC = 0124h After Instruction PC = 0126h TOS = 0126h Stack (1 level down) = 345Ah (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 723 PIC18F26/45/46Q10 Instruction Set Summary RCALL Relative Call Syntax: RCALL n Operands: -1024 n 1023 Operation: (PC) + 2 TOS, (PC) + 2 + 2n PC Status Affected: None Encoding: 1101 1nnn nnnn nnnn Description: Subroutine call with a jump up to 1K from the current location. First, return address (PC + 2) is pushed onto the stack. Then, add the 2's complement number `2n' to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC + 2 + 2n. This instruction is a 2-cycle instruction. Words: 1 Cycles: 2 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read literal `n' PUSH PC to stack Process Data Write to PC No operation No operation No operation No operation Example: HERE RCALL Jump Before Instruction PC = Address (HERE) After Instruction PC = Address (Jump) TOS = Address (HERE + 2) RESET Reset Syntax: RESET Operands: None Operation: Reset all registers and flags that are affected by a MCLR Reset. Status Affected: All Encoding: (c) 2019 Microchip Technology Inc. 0000 0000 Datasheet Preliminary 1111 1111 DS40001996C-page 724 PIC18F26/45/46Q10 Instruction Set Summary ...........continued RESET Reset Description: This instruction provides a way to execute a MCLR Reset by software. Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Start Reset No operation No operation Example: RESET After Instruction Registers = Reset Value Flags* = Reset Value RETFIE Return from Interrupt Syntax: RETFIE {s} Operands: s [0,1] Operation: (TOS) PC, 1 GIE/GIEH or PEIE/GIEL, if s = 1 (WS) W, (STATUSS) Status, (BSRS) BSR, PCLATU, PCLATH are unchanged. Status Affected: GIE/GIEH, PEIE/GIEL. Encoding: 0000 0000 0001 000s Description: Return from interrupt. Stack is popped and Top-of-Stack (TOS) is loaded into the PC. Interrupts are enabled by setting either the high or low priority global interrupt enable bit. If `s' = 1, the contents of the shadow registers, WS, STATUSS and BSRS, are loaded into their corresponding registers, W, Status and BSR. If `s' = 0, no update of these registers occurs (default). Words: 1 (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 725 PIC18F26/45/46Q10 Instruction Set Summary ...........continued RETFIE Return from Interrupt Cycles: 2 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode No operation No operation POP PC from stack Set GIEH or GIEL No operation No operation No operation No operation Example: RETFIE 1 After Interrupt PC = TOS W = WS BSR = BSRS Status = STATUSS GIE/GIEH, PEIE/GIEL = 1 RETLW Return literal to W Syntax: RETLW k Operands: 0 k 255 Operation: k W, (TOS) PC, PCLATU, PCLATH are unchanged Status Affected: None Encoding: 0000 1100 kkkk kkkk Description: W is loaded with the 8-bit literal `k'. The Program Counter is loaded from the top of the stack (the return address). The high address latch (PCLATH) remains unchanged. Words: 1 Cycles: 2 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read literal `k' Process Data POP PC from stack, Write to W (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 726 PIC18F26/45/46Q10 Instruction Set Summary No operation No operation No operation No operation Example: CALL TABLE ; offset value ; W now has ; table value : TABLE ADDWF PCL RETLW k0 RETLW k1 : : RETLW kn ; contains table ; W = offset ; Begin table ; ; End of table Before Instruction W = 07h After Instruction W = value of kn RETURN Return from Subroutine Syntax: RETURN {s} Operands: s [0,1] Operation: (TOS) PC, if s = 1 (WS) W, (STATUSS) Status, (BSRS) BSR, PCLATU, PCLATH are unchanged Status Affected: None Encoding: 0000 0000 0001 001s Description: Return from subroutine. The stack is popped and the top of the stack (TOS) is loaded into the Program Counter. If `s'= 1, the contents of the shadow registers, WS, STATUSS and BSRS, are loaded into their corresponding registers, W, Status and BSR. If `s' = 0, no update of these registers occurs (default). Words: 1 Cycles: 2 Q Cycle Activity: Q1 Q2 (c) 2019 Microchip Technology Inc. Q3 Q4 Datasheet Preliminary DS40001996C-page 727 PIC18F26/45/46Q10 Instruction Set Summary Decode No operation Process Data POP PC from stack No operation No operation No operation No operation Example: RETURN After Instruction: PC = TOS RLCF Rotate Left f through Carry Syntax: RLCF f {,d {,a}} Operands: 0 f 255 d [0,1] a [0,1] Operation: (f<n>) dest<n + 1>, (f<7>) C, (C) dest<0> Status Affected: C, N, Z Encoding: Description: 0011 01da ffff ffff The contents of register `f' are rotated one bit to the left through the CARRY flag. If `d' is `0', the result is placed in W. If `d' is `1', the result is stored back in register `f' (default). If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank. If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 35.2.3 "Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode" for details. C Words: 1 Cycles: 1 register f Q Cycle Activity: Q1 Q2 Decode (c) 2019 Microchip Technology Inc. Q3 Read register `f' Q4 Process Data Datasheet Preliminary Write to destination DS40001996C-page 728 PIC18F26/45/46Q10 Instruction Set Summary Example: RLCF REG, 0, 0 Before Instruction REG = 1110 0110 C=0 After Instruction REG = 1110 0110 W = 1100 1100 C=1 RLNCF Rotate Left f (No Carry) Syntax: RLNCF f {,d {,a}} Operands: 0 f 255 d [0,1] a [0,1] Operation: (f<n>) dest<n + 1>, (f<7>) dest<0> Status Affected: N, Z Encoding: Description: 0100 01da ffff ffff The contents of register `f' are rotated one bit to the left. If `d' is `0', the result is placed in W. If `d' is `1', the result is stored back in register `f' (default). If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank. If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See 37.2.3 Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode for details. register f Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Decode Example: (c) 2019 Microchip Technology Inc. Q3 Read register `f' Q4 Process Data RLNCF Write to destination REG, 1, 0 Datasheet Preliminary DS40001996C-page 729 PIC18F26/45/46Q10 Instruction Set Summary Before Instruction REG = 1010 1011 After Instruction REG = 0101 0111 RRCF Rotate Right f through Carry Syntax: RRCF f {,d {,a}} Operands: 0 f 255 d [0,1] a [0,1] Operation: (f<n>) dest<n - 1>, (f<0>) C, (C) dest<7> Status Affected: C, N, Z Encoding: Description: 0011 00da ffff ffff The contents of register `f' are rotated one bit to the right through the CARRY flag. If `d' is `0', the result is placed in W. If `d' is `1', the result is placed back in register `f' (default). If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank. If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See 37.2.3 ByteOriented and Bit-Oriented Instructions in Indexed Literal Offset Mode for details. C Words: 1 Cycles: 1 register f Q Cycle Activity: Q1 Q2 Decode Example: (c) 2019 Microchip Technology Inc. Q3 Read register `f' Q4 Process Data RRCF Write to destination REG, 0, 0 Datasheet Preliminary DS40001996C-page 730 PIC18F26/45/46Q10 Instruction Set Summary Before Instruction REG = 1110 0110 C=0 After Instruction REG = 1110 0110 W = 0111 0011 C=0 RRNCF Rotate Right f (No Carry) Syntax: RRNCF f {,d {,a}} Operands: 0 f 255 d [0,1] a [0,1] Operation: (f<n>) dest<n - 1>, (f<0>) dest<7> Status Affected: N, Z Encoding: Description: 0100 00da ffff ffff The contents of register `f' are rotated one bit to the right. If `d' is `0', the result is placed in W. If `d' is `1', the result is placed back in register `f' (default). If `a' is `0', the Access Bank will be selected (default), overriding the BSR value. If `a' is `1', then the bank will be selected as per the BSR value. If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See 37.2.3 ByteOriented and Bit-Oriented Instructions in Indexed Literal Offset Mode for details. register f Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Decode Example 1: (c) 2019 Microchip Technology Inc. Q3 Read register `f' Q4 Process Data RRNCF Write to destination REG, 1, 0 Datasheet Preliminary DS40001996C-page 731 PIC18F26/45/46Q10 Instruction Set Summary Before Instruction REG = 1101 0111 After Instruction REG = 1110 1011 Example 2: RRNCF REG, 0, 0 Before Instruction W=? REG = 1101 0111 After Instruction W = 1110 1011 REG = 1101 0111 SETF Set f Syntax: SETF f {,a} Operands: 0 f 255 a [0,1] Operation: FFh f Status Affected: None Encoding: Description: 0110 100a ffff ffff The contents of the specified register are set to FFh. If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank. If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See 37.2.3 ByteOriented and Bit-Oriented Instructions in Indexed Literal Offset Mode for details. Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Decode Example: (c) 2019 Microchip Technology Inc. Q3 Read register `f' Q4 Process Data SETF Datasheet Preliminary Write register `f' REG, 1 DS40001996C-page 732 PIC18F26/45/46Q10 Instruction Set Summary Before Instruction REG = 5Ah After Instruction REG = FFh SLEEP Enter Sleep mode Syntax: SLEEP Operands: None Operation: 00h WDT, 0 WDT postscaler, 1 TO, 0 PD Status Affected: TO, PD Encoding: 0000 0000 0000 0011 Description: The Power-down Status bit (PD) is cleared. The Time-out Status bit (TO) is set. Watchdog Timer and its postscaler are cleared. The processor is put into Sleep mode with the oscillator stopped. Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode No operation Process Data Go to Sleep Example: SLEEP Before Instruction TO = ? PD = ? After Instruction TO = 1 PD = 0 If WDT causes wake-up, this bit is cleared. (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 733 PIC18F26/45/46Q10 Instruction Set Summary SUBFWB Subtract f from W with borrow (Continued) Syntax: SUBFWB f {,d {,a}} Operands: 0 f 255 d [0,1] a [0,1] Operation: (W) - (f) - (C) dest Status Affected: N, OV, C, DC, Z Encoding: Description: 0101 01da ffff ffff Subtract register `f' and CARRY flag (borrow) from W (2's complement method). If `d' is `0', the result is stored in W. If `d' is `1', the result is stored in register `f' (default). If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank. If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 35.2.3 "Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode" for details. Words: 1 Cycles: 1 Q Cycle Activity: Q1 Decode Q2 Q3 Read register `f' Example 1: Process Data SUBFWB Q4 Write to destination REG, 1, 0 Before Instruction REG = 3 W=2 C=1 After Instruction REG = FF W=2 C=0 Z=0 N = 1 ; result is negative (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 734 PIC18F26/45/46Q10 Instruction Set Summary Example 2: SUBFWB REG, 0, 0 SUBFWB REG, 1, 0 Before Instruction REG = 2 W=5 C=1 After Instruction REG = 2 W=3 C=1 Z=0 N = 0 ; result is positive Example 3: Before Instruction REG = 1 W=2 C=0 After Instruction REG = 0 W=2 C=1 Z = 1 ; result is zero N=0 SUBLW Subtract W from literal Syntax: SUBLW k Operands: 0 k 255 Operation: k - (W) Status Affected: N, OV, C, DC, Z Encoding: 0000 1000 Description W is subtracted from the 8-bit literal `k'. The result is placed in W. Words: 1 Cycles: 1 (c) 2019 Microchip Technology Inc. Datasheet Preliminary kkkk kkkk DS40001996C-page 735 PIC18F26/45/46Q10 Instruction Set Summary Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read literal `k' Process Data Write to W Example 1: SUBLW 02h SUBLW 02h SUBLW 02h Before Instruction W = 01h C=? After Instruction W = 01h C = 1 ; result is positive Z=0 N=0 Example 2: Before Instruction W = 02h C=? After Instruction W = 00h C = 1 ; result is zero Z=1 N=0 Example 3: Before Instruction W = 03h C=? After Instruction W = FFh ; (2's complement) C = 0 ; result is negative Z=0 N=1 (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 736 PIC18F26/45/46Q10 Instruction Set Summary SUBWF Subtract W from f Syntax: SUBWF f {,d {,a}} Operands: 0 f 255 d [0,1] a [0,1] Operation: (f) - (W) dest Status Affected: N, OV, C, DC, Z Encoding: Description: 0101 11da ffff ffff Subtract W from register `f' (2's complement method). If `d' is `0', the result is stored in W. If `d' is `1', the result is stored back in register `f' (default). If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank. If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 35.2.3 "Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode" for details. Words: 1 Cycles: 1 Q Cycle Activity: Q1 Decode Q2 Q3 Read register `f' Example 1: Process Data SUBWF Q4 Write to destination REG, 1, 0 Before Instruction REG = 3 W=2 C=? After Instruction REG = 1 W=2 C = 1 ; result is positive Z=0 N=0 (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 737 PIC18F26/45/46Q10 Instruction Set Summary Example 2: SUBWF REG, 0, 0 SUBWF REG, 1, 0 Before Instruction REG = 2 W=2 C=? After Instruction REG = 2 W=0 C = 1 ; result is zero Z=1 N=0 Example 3: Before Instruction REG = 1 W=2 C=? After Instruction REG = FFh ;(2's complement) W=2 C = 0 ; result is negative Z=0 N=1 SUBWFB Subtract W from f with Borrow Syntax: SUBWFB f {,d {,a}} Operands: 0 f 255 d [0,1] a [0,1] Operation: (f) - (W) - (C) dest Status Affected: N, OV, C, DC, Z Encoding: 0101 (c) 2019 Microchip Technology Inc. 10da Datasheet Preliminary ffff ffff DS40001996C-page 738 PIC18F26/45/46Q10 Instruction Set Summary ...........continued SUBWFB Subtract W from f with Borrow Description: Subtract W and the CARRY flag (borrow) from register `f' (2's complement method). If `d' is `0', the result is stored in W. If `d' is `1', the result is stored back in register `f' (default). If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank. If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See 37.2.3 ByteOriented and Bit-Oriented Instructions in Indexed Literal Offset Mode for details. Words: 1 Cycles: 1 Q Cycle Activity: Q1 Decode Q2 Read register `f' Example 1: Q3 Process Data SUBWFB Q4 Write to destination REG, 1, 0 Before Instruction REG = 19h (0001 1001) W = 0Dh (0000 1101) C=1 After Instruction REG = 0Ch (0000 1100) W = 0Dh (0000 1101) C=1 Z=0 N = 0 ; result is positive Example 2: (c) 2019 Microchip Technology Inc. SUBWFB REG, 0, 0 Datasheet Preliminary DS40001996C-page 739 PIC18F26/45/46Q10 Instruction Set Summary Before Instruction REG = 1Bh (0001 1011) W = 1Ah (0001 1010) C=0 After Instruction REG = 1Bh (0001 1011) W = 00h C=1 Z = 1 ; result is zero N=0 Example 3: SUBWFB REG, 1, 0 Before Instruction REG = 03h (0000 0011) W = 0Eh (0000 1110) C=1 After Instruction REG = F5h (1111 0101) ; [2's comp] W = 0Eh (0000 1110) C=0 Z=0 N = 1 ; result is negative SWAPF Swap f Syntax: SWAPF f {,d {,a}} Operands: 0 f 255 d [0,1] a [0,1] Operation: (f<3:0>) dest<7:4>, (f<7:4>) dest<3:0> Status Affected: None Encoding: 0011 (c) 2019 Microchip Technology Inc. 10da Datasheet Preliminary ffff ffff DS40001996C-page 740 PIC18F26/45/46Q10 Instruction Set Summary ...........continued SWAPF Swap f Description: The upper and lower nibbles of register `f' are exchanged. If `d' is `0', the result is placed in W. If `d' is `1', the result is placed in register `f' (default). If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank. If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See 37.2.3 ByteOriented and Bit-Oriented Instructions in Indexed Literal Offset Mode for details. Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read register `f' Process Data Write to destination Example: SWAPF REG, 1, 0 Before Instruction REG = 53h After Instruction REG = 35h TBLRD Table Read Syntax: TBLRD ( *; *+; *-; +*) Operands: None (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 741 PIC18F26/45/46Q10 Instruction Set Summary ...........continued TBLRD Table Read Operation: if TBLRD *, (Prog Mem (TBLPTR)) TABLAT; TBLPTR - No Change; if TBLRD *+, (Prog Mem (TBLPTR)) TABLAT; (TBLPTR) + 1 TBLPTR; if TBLRD *-, (Prog Mem (TBLPTR)) TABLAT; (TBLPTR) - 1 TBLPTR; if TBLRD +*, (TBLPTR) + 1 TBLPTR; (Prog Mem (TBLPTR)) TABLAT; Status Affected: None Encoding: 10nn nn=0 * 0000 0000 0000 =1 *+ =2 *=3 +* Description: This instruction is used to read the contents of Program Memory (P.M.). To address the program memory, a pointer called Table Pointer (TBLPTR) is used. The TBLPTR (a 21-bit pointer) points to each byte in the program memory. TBLPTR has a 2-Mbyte address range. TBLPTR[0] = 0: Least Significant Byte of Program Memory Word TBLPTR[0] = 1: Most Significant Byte of Program Memory Word The TBLRD instruction can modify the value of TBLPTR as follows: * * * * Words: 1 Cycles: 2 no change post-increment post-decrement pre-increment Q Cycle Activity: (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 742 PIC18F26/45/46Q10 Instruction Set Summary Q1 Q3 Q2 Q4 Decode No operation No operation No operation No operation No operation (Read Program Memory) No operation No operation (Write TABLAT) TBLRD Table Read (Continued) Example1: TBLRD *+ ; TBLRD +* ; Before Instruction TABLAT = 55h TBLPTR = 00A356h MEMORY (00A356h) = 34h After Instruction TABLAT = 34h TBLPTR = 00A357h Example2: Before Instruction TABLAT = AAh TBLPTR = 01A357h MEMORY (01A357h) = 12h MEMORY (01A358h) = 34h After Instruction TABLAT = 34h TBLPTR = 01A358h TBLWT (Continued) Table Write Syntax: TBLWT ( *; *+; *-; +*) Operands: None (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 743 PIC18F26/45/46Q10 Instruction Set Summary ...........continued TBLWT (Continued) Operation: Table Write if TBLWT*, (TABLAT) Holding Register; TBLPTR - No Change; if TBLWT*+, (TABLAT) Holding Register; (TBLPTR) + 1 TBLPTR; if TBLWT*-, (TABLAT) Holding Register; (TBLPTR) - 1 TBLPTR; if TBLWT+*, (TBLPTR) + 1 TBLPTR; (TABLAT) Holding Register; Status Affected: None Encoding: 11nn nn=0 * 0000 0000 0000 =1 *+ =2 *=3 +* Description: This instruction uses the LSBs of TBLPTR to determine which of the holding registers the TABLAT is written to. The holding registers are used to program the contents of Program Memory (P.M.). (Refer to the "Program Flash Memory" section for additional details on programming Flash memory.) The TBLPTR (a 21-bit pointer) points to each byte in the program memory. TBLPTR has a 2-MByte address range. The LSb of the TBLPTR selects which byte of the program memory location to access. TBLPTR[0] = 0: Least Significant Byte of Program Memory Word TBLPTR[0] = 1: Most Significant Byte of Program Memory Word The TBLWT instruction can modify the value of TBLPTR as follows: * * * * Words: no change post-increment post-decrement pre-increment 1 (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 744 PIC18F26/45/46Q10 Instruction Set Summary ...........continued TBLWT (Continued) Table Write Cycles: 2 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode No operation No operation No operation No operation No operation (Read TABLAT) No operation No operation (Write to Holding Register ) TBLWT Table Write (Continued) Example1: TBLWT *+; Before Instruction TABLAT = 55h TBLPTR = 00A356h HOLDING REGISTER (00A356h) = FFh After Instructions (table write completion) TABLAT = 55h TBLPTR = 00A357h HOLDING REGISTER (00A356h) = 55h Example 2: (c) 2019 Microchip Technology Inc. TBLWT +*; Datasheet Preliminary DS40001996C-page 745 PIC18F26/45/46Q10 Instruction Set Summary Before Instruction TABLAT = 34h TBLPTR = 01389Ah HOLDING REGISTER (01389Ah) = FFh HOLDING REGISTER (01389Bh) = FFh After Instruction (table write completion) TABLAT = 34h TBLPTR = 01389Bh HOLDING REGISTER (01389Ah) = FFh HOLDING REGISTER (01389Bh) = 34h TSTFSZ Test f, skip if 0 Syntax: TSTFSZ f {,a} Operands: 0 f 255 a [0,1] Operation: skip if f = 0 Status Affected: None Encoding: Description: 0110 011a ffff ffff If `f' = 0, the next instruction fetched during the current instruction execution is discarded and a NOP is executed, making this a 2-cycle instruction. If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank. If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See 37.2.3 ByteOriented and Bit-Oriented Instructions in Indexed Literal Offset Mode for details. Words: 1 Cycles: 1(2) Note: Three cycles if skip and followed by a 2-word instruction. Q Cycle Activity: Q1 (c) 2019 Microchip Technology Inc. Q2 Q3 Datasheet Preliminary Q4 DS40001996C-page 746 PIC18F26/45/46Q10 Instruction Set Summary Decode Read register `f' Process Data No operation If skip: Q1 Q2 Q3 Q4 No operation No operation No operation No operation Q3 Q4 If skip and followed by 2-word instruction: Q1 Q2 No operation No operation No operation No operation No operation No operation No operation No operation Example: HERE NZERO ZERO TSTFSZ : : CNT, 1 Before Instruction PC = Address (HERE) After Instruction If CNT = 00h, PC = Address (ZERO) If CNT 00h, PC = Address (NZERO) XORLW Exclusive OR literal with W Syntax: XORLW k Operands: 0 k 255 Operation: (W) .XOR. k Status Affected: N, Z Encoding: 0000 1010 kkkk kkkk Description: The contents of W are XORed with the 8-bit literal `k'. The result is placed in W. Words: 1 Cycles: 1 Q Cycle Activity: Q1 (c) 2019 Microchip Technology Inc. Q2 Q3 Datasheet Preliminary Q4 DS40001996C-page 747 PIC18F26/45/46Q10 Instruction Set Summary Decode Read literal `k' Example: Process Data Write to W XORLW 0AFh Before Instruction W = B5h After Instruction W = 1Ah XORWF Exclusive OR W with f Syntax: XORWF f {,d {,a}} Operands: 0 f 255 d [0,1] a [0,1] Operation: (W) .XOR. (f) dest Status Affected: N, Z Encoding: Description: 0001 10da ffff ffff Exclusive OR the contents of W with register `f'. If `d' is `0', the result is stored in W. If `d' is `1', the result is stored back in the register `f' (default). If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank. If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See 37.2.3 ByteOriented and Bit-Oriented Instructions in Indexed Literal Offset Mode for details. Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read register `f' Process Data Write to destination Example: (c) 2019 Microchip Technology Inc. XORWF REG, 1, 0 Datasheet Preliminary DS40001996C-page 748 PIC18F26/45/46Q10 Instruction Set Summary Before Instruction REG = AFh W = B5h After Instruction REG = 1Ah W = B5h 37.2 Extended Instruction Set In addition to the standard 75 instructions of the PIC18 instruction set, PIC18F26/45/46Q10 devices also provide an optional extension to the core CPU functionality. The added features include eight additional instructions that augment Indirect and Indexed Addressing operations and the implementation of Indexed Literal Offset Addressing mode for many of the standard PIC18 instructions. The additional features of the extended instruction set are disabled by default. To enable them, users must set the XINST Configuration bit. The instructions in the extended set can all be classified as literal operations, which either manipulate the File Select Registers, or use them for Indexed Addressing. Two of the instructions, ADDFSR and SUBFSR, each have an additional special instantiation for using FSR2. These versions (ADDULNK and SUBULNK) allow for automatic return after execution. The extended instructions are specifically implemented to optimize re-entrant program code (that is, code that is recursive or that uses a software stack) written in high-level languages, particularly C. Among other things, they allow users working in high-level languages to perform certain operations on data structures more efficiently. These include: * * * * dynamic allocation and deallocation of software stack space when entering and leaving subroutines function pointer invocation software Stack Pointer manipulation manipulation of variables located in a software stack A summary of the instructions in the extended instruction set is provided in 37.2.1 Extended Instruction Syntax. Detailed descriptions are provided in 37.2.2 Extended Instruction Set. The opcode field descriptions in 37.1 Standard Instruction Set apply to both the standard and extended PIC18 instruction sets. Important: The instruction set extension and the Indexed Literal Offset Addressing mode were designed for optimizing applications written in C; the user may likely never use these instructions directly in assembler. The syntax for these commands is provided as a reference for users who may be reviewing code that has been generated by a compiler. 37.2.1 Extended Instruction Syntax Most of the extended instructions use indexed arguments, using one of the File Select Registers and some offset to specify a source or destination register. When an argument for an instruction serves as part of Indexed Addressing, it is enclosed in square brackets ("[ ]"). This is done to indicate that the (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 749 PIC18F26/45/46Q10 Instruction Set Summary argument is used as an index or offset. MPASMTM Assembler will flag an error if it determines that an index or offset value is not bracketed. When the extended instruction set is enabled, brackets are also used to indicate index arguments in byteoriented and bit-oriented instructions. This is in addition to other changes in their syntax. For more details, see 37.2.3.1 Extended Instruction Syntax with Standard PIC18 Commands. Important: In the past, square brackets have been used to denote optional arguments in the PIC18 and earlier instruction sets. In this text and going forward, optional arguments are denoted by braces ("{ }"). Table 37-3. Extensions to the PIC18 Instruction Set Mnemonic, Operands ADDFSR Cycles MSb LSb Status Affected 1 1110 1000 ffkk kkkk None Add literal to FSR2 and return 2 1110 1000 11kk kkkk None CALLW Call subroutine using WREG 2 0000 0000 0001 0100 None MOVSF zs, fd Move zs (source) to 1st word 2 1110 1011 0zzz zzzz None 1111 ffff ffff ffff 1110 1011 1zzz zzzz 1111 xxxx xzzz zzzz k fd (destination) 2nd word MOVSS zs, zd Move zs (source) to 1st word 2 zd (destination) 2nd word PUSHL SUBFSR SUBULNK 37.2.2 16-Bit Instruction Word Add literal to FSR ADDULNK f, k Description k f, k k None Store literal at FSR2, decrement FSR2 1 1110 1010 kkkk kkkk None Subtract literal from FSR 1 1110 1001 ffkk kkkk None Subtract literal from FSR2 and return 2 1110 1001 11kk kkkk None Extended Instruction Set ADDFSR Add Literal to FSR Syntax: ADDFSR f, k Operands: 0 k 63 f [ 0, 1, 2 ] Operation: FSR(f) + k FSR(f) Status Affected: None (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 750 PIC18F26/45/46Q10 Instruction Set Summary ...........continued ADDFSR Add Literal to FSR Encoding: 1110 1000 ffkk kkkk Description: The 6-bit literal `k' is added to the contents of the FSR specified by `f'. Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Decode Read literal `k' Q3 Q4 Process Data Example: Write to FSR ADDFSR 2, 23h Before Instruction FSR2 = 03FFh After Instruction FSR2 = 0422h ADDULNK Add Literal to FSR2 and Return Syntax: ADDULNK k Operands: 0 k 63 Operation: FSR2 + k FSR2, (TOS) PC Status Affected: None Encoding: 1110 Description: 1000 11kk kkkk The 6-bit literal `k' is added to the contents of FSR2. A RETURN is then executed by loading the PC with the TOS. The instruction takes two cycles to execute; a NOP is performed during the second cycle. This may be thought of as a special case of the ADDFSR instruction, where f = 3 (binary `11'); it operates only on FSR2. Words: 1 Cycles: 2 Q Cycle Activity: Q1 (c) 2019 Microchip Technology Inc. Q2 Q3 Datasheet Preliminary Q4 DS40001996C-page 751 PIC18F26/45/46Q10 Instruction Set Summary Decode Read literal `k' Process Data Write to FSR No Operation No Operation No Operation No Operation Example: ADDULNK 23h Before Instruction FSR2 = 03FFh PC = 0100h After Instruction FSR2 = 0422h PC = (TOS) Important: All PIC18 instructions may take an optional label argument preceding the instruction mnemonic for use in symbolic addressing. If a label is used, the instruction syntax then becomes: {label} instruction argument(s). CALLW Subroutine Call Using WREG Syntax: CALLW Operands: None Operation: (PC + 2) TOS, (W) PCL, (PCLATH) PCH, (PCLATU) PCU Status Affected: None Encoding: 0000 0000 0001 0100 Description First, the return address (PC + 2) is pushed onto the return stack. Next, the contents of W are written to PCL; the existing value is discarded. Then, the contents of PCLATH and PCLATU are latched into PCH and PCU, respectively. The second cycle is executed as a NOP instruction while the new next instruction is fetched. Unlike CALL, there is no option to update W, Status or BSR. Words: 1 Cycles: 2 Q Cycle Activity: Q1 Q2 (c) 2019 Microchip Technology Inc. Q3 Datasheet Preliminary Q4 DS40001996C-page 752 PIC18F26/45/46Q10 Instruction Set Summary Decode Read WREG PUSH PC to stack No operation No operation No operation No operation No operation Example: HERE CALLW Before Instruction PC = address (HERE) PCLATH = 10h PCLATU = 00h W = 06h After Instruction PC = 001006h TOS = address (HERE + 2) PCLATH = 10h PCLATU = 00h W = 06h MOVSF Move Indexed to f Syntax: MOVSF [zs], fd Operands: 0 zs 127 0 fd 4095 Operation: ((FSR2) + zs) fd Status Affected: None Encoding: 1st word (source) 2nd word (destin.) 1110 1111 (c) 2019 Microchip Technology Inc. 1011 ffff Datasheet Preliminary 0zzz ffff zzzzs ffffd DS40001996C-page 753 PIC18F26/45/46Q10 Instruction Set Summary ...........continued MOVSF Move Indexed to f Description: The contents of the source register are moved to destination register `fd'. The actual address of the source register is determined by adding the 7-bit literal offset `zs' in the first word to the value of FSR2. The address of the destination register is specified by the 12-bit literal `fd' in the second word. Both addresses can be anywhere in the 4096byte data space (000h to FFFh). The MOVSF instruction cannot use the PCL, TOSU, TOSH or TOSL as the destination register. If the resultant source address points to an Indirect Addressing register, the value returned will be 00h. Words: 2 Cycles: 2 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Determine source addr Determine source addr Read source reg Decode No operation No dummy read No operation Write register `f' (dest) Example: MOVSF [05h], REG2 Before Instruction FSR2 = 80h Contents of 85h = 33h REG2 = 11h After Instruction FSR2 = 80h Contents of 85h = 33h REG2 = 33h MOVSS Move Indexed to Indexed Syntax: MOVSS [zs], [zd] Operands: 0 zs 127 0 zd 127 (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 754 PIC18F26/45/46Q10 Instruction Set Summary ...........continued MOVSS Move Indexed to Indexed Operation: ((FSR2) + zs) ((FSR2) + zd) Status Affected: None Encoding: 1st word (source) 1110 1111 2nd word (dest.) Description 1011 xxxx 1zzz xzzz zzzzs zzzzd The contents of the source register are moved to the destination register. The addresses of the source and destination registers are determined by adding the 7-bit literal offsets `zs' or `zd', respectively, to the value of FSR2. Both registers can be located anywhere in the 4096byte data memory space (000h to FFFh). The MOVSS instruction cannot use the PCL, TOSU, TOSH or TOSL as the destination register. If the resultant source address points to an Indirect Addressing register, the value returned will be 00h. If the resultant destination address points to an Indirect Addressing register, the instruction will execute as a NOP. Words: 2 Cycles: 2 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Determine source addr Determine source addr Read source reg Decode Determine dest addr Determine dest addr Write to dest reg Example: (c) 2019 Microchip Technology Inc. MOVSS [05h], [06h] Datasheet Preliminary DS40001996C-page 755 PIC18F26/45/46Q10 Instruction Set Summary Before Instruction FSR2 = 80h Contents of 85h = 33h Contents of 86h = 11h After Instruction FSR2 = 80h Contents of 85h = 33h Contents of 86h = 33h PUSHL Store Literal at FSR2, Decrement FSR2 Syntax: PUSHL k Operands: 0 k 255 Operation: k (FSR2), FSR2 - 1 FSR2 Status Affected: None Encoding: 1111 1010 kkkk kkkk Description: The 8-bit literal `k' is written to the data memory address specified by FSR2. FSR2 is decremented by 1 after the operation. This instruction allows users to push values onto a software stack. Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read `k' Process data Write to destination Example: (c) 2019 Microchip Technology Inc. PUSHL 08h Datasheet Preliminary DS40001996C-page 756 PIC18F26/45/46Q10 Instruction Set Summary Before Instruction FSR2H:FSR2L = 01ECh Memory (01ECh) = 00h After Instruction FSR2H:FSR2L = 01EBh Memory (01ECh) = 08h SUBFSR Subtract Literal from FSR Syntax: SUBFSR f, k Operands: 0 k 63 f [ 0, 1, 2 ] Operation: FSR(f) - k FSRf Status Affected: None Encoding: 1110 1001 ffkk kkkk Description: The 6-bit literal `k' is subtracted from the contents of the FSR specified by `f'. Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read register `f' Process Data Write to destination Example: SUBFSR 2, 23h Before Instruction FSR2 = 03FFh After Instruction FSR2 = 03DCh SUBULNK Subtract Literal from FSR2 and Return Syntax: SUBULNK k Operands: 0 k 63 Operation: FSR2 - k FSR2 (TOS) PC Status Affected: None (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 757 PIC18F26/45/46Q10 Instruction Set Summary ...........continued SUBULNK Subtract Literal from FSR2 and Return Encoding: 1110 Description: 1001 11kk kkkk The 6-bit literal `k' is subtracted from the contents of the FSR2. A RETURN is then executed by loading the PC with the TOS. The instruction takes two cycles to execute; a NOP is performed during the second cycle. This may be thought of as a special case of the SUBFSR instruction, where f = 3 (binary `11'); it operates only on FSR2. Words: 1 Cycles: 2 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read register `f' Process Data Write to destination No Operation No Operation No Operation No Operation Example: SUBULNK 23h Before Instruction FSR2 = 03FFh PC = 0100h After Instruction FSR2 = 03DCh PC = (TOS) 37.2.3 Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode Important: Enabling the PIC18 instruction set extension may cause legacy applications to behave erratically or fail entirely. In addition to eight new commands in the extended set, enabling the extended instruction set also enables Indexed Literal Offset Addressing mode (Section "Indexed Addressing with Literal Offset"). This has a significant impact on the way that many commands of the standard PIC18 instruction set are interpreted. When the extended set is disabled, addresses embedded in opcodes are treated as literal memory locations: either as a location in the Access Bank (`a' = 0), or in a GPR bank designated by the BSR (`a' = 1). When the extended instruction set is enabled and `a' = 0, however, a file register argument of 5Fh or (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 758 PIC18F26/45/46Q10 Instruction Set Summary less is interpreted as an offset from the pointer value in FSR2 and not as a literal address. For practical purposes, this means that all instructions that use the Access RAM bit as an argument - that is, all byteoriented and bit-oriented instructions, or almost half of the core PIC18 instructions - may behave differently when the extended instruction set is enabled. When the content of FSR2 is 00h, the boundaries of the Access RAM are essentially remapped to their original values. This may be useful in creating backward compatible code. If this technique is used, it may be necessary to save the value of FSR2 and restore it when moving back and forth between C and assembly routines in order to preserve the Stack Pointer. Users must also keep in mind the syntax requirements of the extended instruction set (see 37.2.3.1 Extended Instruction Syntax with Standard PIC18 Commands). Although the Indexed Literal Offset Addressing mode can be very useful for dynamic stack and pointer manipulation, it can also be very annoying if a simple arithmetic operation is carried out on the wrong register. Users who are accustomed to the PIC18 programming must keep in mind that, when the extended instruction set is enabled, register addresses of 5Fh or less are used for Indexed Literal Offset Addressing. Representative examples of typical byte-oriented and bit-oriented instructions in the Indexed Literal Offset Addressing mode are provided on the following page to show how execution is affected. The operand conditions shown in the examples are applicable to all instructions of these types. Related Links 10.5 Data Memory and the Extended Instruction Set 37.2.3.1 Extended Instruction Syntax with Standard PIC18 Commands When the extended instruction set is enabled, the file register argument, `f', in the standard byte-oriented and bit-oriented commands is replaced with the literal offset value, `k'. As already noted, this occurs only when `f' is less than or equal to 5Fh. When an offset value is used, it must be indicated by square brackets ("[ ]"). As with the extended instructions, the use of brackets indicates to the compiler that the value is to be interpreted as an index or an offset. Omitting the brackets, or using a value greater than 5Fh within brackets, will generate an error in the MPASM assembler. If the index argument is properly bracketed for Indexed Literal Offset Addressing, the Access RAM argument is never specified; it will automatically be assumed to be `0'. This is in contrast to standard operation (extended instruction set disabled) when `a' is set on the basis of the target address. Declaring the Access RAM bit in this mode will also generate an error in the MPASM assembler. The destination argument, `d', functions as before. In the latest versions of the MPASMTM assembler, language support for the extended instruction set must be explicitly invoked. This is done with either the command-line option, /y, or the PE directive in the source listing. Related Links 10.5 Data Memory and the Extended Instruction Set 37.2.4 Considerations when Enabling the Extended Instruction Set It is important to note that the extensions to the instruction set may not be beneficial to all users. In particular, users who are not writing code that uses a software stack may not benefit from using the extensions to the instruction set. Additionally, the Indexed Literal Offset Addressing mode may create issues with legacy applications written to the PIC18 assembler. This is because instructions in the legacy code may attempt to address (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 759 PIC18F26/45/46Q10 Instruction Set Summary registers in the Access Bank below 5Fh. Since these addresses are interpreted as literal offsets to FSR2 when the instruction set extension is enabled, the application may read or write to the wrong data addresses. When porting an application to the PIC18F26/45/46Q10 it is very important to consider the type of code. A large, re-entrant application that is written in `C' and would benefit from efficient compilation will do well when using the instruction set extensions. Legacy applications that heavily use the Access Bank will most likely not benefit from using the extended instruction set. ADDWF ADD W to Indexed (Indexed Literal Offset mode) Syntax: ADDWF [k] {,d} Operands: 0 k 95 d [0,1] Operation: (W) + ((FSR2) + k) dest Status Affected: N, OV, C, DC, Z Encoding: 0010 01d0 kkkk kkkk Description: The contents of W are added to the contents of the register indicated by FSR2, offset by the value `k'. If `d' is `0', the result is stored in W. If `d' is `1', the result is stored back in register `f' (default). Words: 1 Cycles: 1 Q Cycle Activity: Q1 Decode Q2 Read `k' Example: (c) 2019 Microchip Technology Inc. Q3 Q4 Process Data ADDWF Write to destination [OFST] Datasheet Preliminary , 0 DS40001996C-page 760 PIC18F26/45/46Q10 Instruction Set Summary Before Instruction W = 17h OFST = 2Ch FSR2 = 0A00h Contents of 0A2Ch = 20h After Instruction W = 37h Contents of 0A2Ch = 20h BSF Bit Set Indexed (Indexed Literal Offset mode) Syntax: BSF [k], b Operands: 0 f 95 0b7 Operation: 1 ((FSR2) + k)<b> Status Affected: None Encoding: 1000 bbb0 kkkk kkkk Description: Bit `b' of the register indicated by FSR2, offset by the value `k', is set. Words: 1 Cycles: 1 Q Cycle Activity: Q1 Decode Q2 Read register `f' Example: Q3 Process Data BSF Q4 Write to destination [FLAG_OFST], 7 Before Instruction FLAG_OFST = 0Ah FSR2 = 0A00h Contents of 0A0Ah = 55h After Instruction Contents of 0A0Ah = D5h (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 761 PIC18F26/45/46Q10 Instruction Set Summary SETF Set Indexed (Indexed Literal Offset mode) Syntax: SETF [k] Operands: 0 k 95 Operation: FFh ((FSR2) + k) Status Affected: None Encoding: 0110 1000 kkkk kkkk Description: The contents of the register indicated by FSR2, offset by `k', are set to FFh. Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Decode Example: Q3 Read `k' Q4 Process Data SETF Write register [OFST] Before Instruction OFST = 2Ch FSR2 = 0A00h Contents of 0A2Ch = 00h After Instruction Contents of 0A2Ch = FFh 37.2.5 (R) Special Considerations with Microchip MPLAB IDE Tools The latest versions of Microchip's software tools have been designed to fully support the extended instruction set of the PIC18F26/45/46Q10 family of devices. This includes the MPLAB C18 C compiler, MPASM assembly language and MPLAB Integrated Development Environment (IDE). When selecting a target device for software development, MPLAB IDE will automatically set default Configuration bits for that device. The default setting for the XINST Configuration bit is `0', disabling the extended instruction set and Indexed Literal Offset Addressing mode. For proper execution of applications developed to take advantage of the extended instruction set, XINST must be set during programming. To develop software for the extended instruction set, the user must enable support for the instructions and the Indexed Addressing mode in their language tool(s). Depending on the environment being used, this may be done in several ways: (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 762 PIC18F26/45/46Q10 Instruction Set Summary * A menu option, or dialog box within the environment, that allows the user to configure the language tool and its settings for the project * A command-line option * A directive in the source code These options vary between different compilers, assemblers and development environments. Users are encouraged to review the documentation accompanying their development systems for the appropriate information. (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 763 PIC18F26/45/46Q10 Development Support 38. Development Support (R) (R) The PIC microcontrollers (MCU) and dsPIC digital signal controllers (DSC) are supported with a full range of software and hardware development tools: * Integrated Development Environment (R) - MPLAB X IDE Software * Compilers/Assemblers/Linkers - MPLAB XC Compiler TM - MPASM Assembler TM - MPLINK Object Linker/ TM MPLIB Object Librarian - MPLAB Assembler/Linker/Librarian for Various Device Families * Simulators - MPLAB X SIM Software Simulator * Emulators - MPLAB REAL ICETM In-Circuit Emulator * In-Circuit Debuggers/Programmers - MPLAB ICD 3 - PICkitTM 3 In-Circuit Debugger * Device Programmers - MPLAB PM3 Device Programmer * Low-Cost Demonstration/Development Boards, Evaluation Kits and Starter Kits * Third-party development tools 38.1 MPLAB X Integrated Development Environment Software The MPLAB X IDE is a single, unified graphical user interface for Microchip and third-party software, and (R) (R) hardware development tool that runs on Windows , Linux and Mac OS X. Based on the NetBeans IDE, MPLAB X IDE is an entirely new IDE with a host of free software components and plug-ins for highperformance application development and debugging. Moving between tools and upgrading from software simulators to hardware debugging and programming tools is simple with the seamless user interface. With complete project management, visual call graphs, a configurable watch window and a feature-rich editor that includes code completion and context menus, MPLAB X IDE is flexible and friendly enough for new users. With the ability to support multiple tools on multiple projects with simultaneous debugging, MPLAB X IDE is also suitable for the needs of experienced users. Feature-Rich Editor: * * * * Color syntax highlighting Smart code completion makes suggestions and provides hints as you type Automatic code formatting based on user-defined rules Live parsing User-Friendly, Customizable Interface: (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 764 PIC18F26/45/46Q10 Development Support * Fully customizable interface: toolbars, toolbar buttons, windows, window placement, etc. * Call graph window Project-Based Workspaces: * * * * Multiple projects Multiple tools Multiple configurations Simultaneous debugging sessions File History and Bug Tracking: * Local file history feature * Built-in support for Bugzilla issue tracker 38.2 MPLAB XC Compilers The MPLAB XC Compilers are complete ANSI C compilers for all of Microchip's 8, 16, and 32-bit MCU and DSC devices. These compilers provide powerful integration capabilities, superior code optimization and ease of use. MPLAB XC Compilers run on Windows, Linux or MAC OS X. For easy source level debugging, the compilers provide debug information that is optimized to the MPLAB X IDE. The free MPLAB XC Compiler editions support all devices and commands, with no time or memory restrictions, and offer sufficient code optimization for most applications. MPLAB XC Compilers include an assembler, linker and utilities. The assembler generates relocatable object files that can then be archived or linked with other relocatable object files and archives to create an executable file. MPLAB XC Compiler uses the assembler to produce its object file. Notable features of the assembler include: * * * * * * 38.3 Support for the entire device instruction set Support for fixed-point and floating-point data Command-line interface Rich directive set Flexible macro language MPLAB X IDE compatibility MPASM Assembler The MPASM Assembler is a full-featured, universal macro assembler for PIC10/12/16/18 MCUs. (R) The MPASM Assembler generates relocatable object files for the MPLINK Object Linker, Intel standard HEX files, MAP files to detail memory usage and symbol reference, absolute LST files that contain source lines and generated machine code, and COFF files for debugging. The MPASM Assembler features include: * Integration into MPLAB X IDE projects * User-defined macros to streamline assembly code (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 765 PIC18F26/45/46Q10 Development Support * Conditional assembly for multipurpose source files * Directives that allow complete control over the assembly process 38.4 MPLINK Object Linker/MPLIB Object Librarian The MPLINK Object Linker combines relocatable objects created by the MPASM Assembler. It can link relocatable objects from precompiled libraries, using directives from a linker script. The MPLIB Object Librarian manages the creation and modification of library files of precompiled code. When a routine from a library is called from a source file, only the modules that contain that routine will be linked in with the application. This allows large libraries to be used efficiently in many different applications. The object linker/library features include: * Efficient linking of single libraries instead of many smaller files * Enhanced code maintainability by grouping related modules together * Flexible creation of libraries with easy module listing, replacement, deletion and extraction 38.5 MPLAB Assembler, Linker and Librarian for Various Device Families MPLAB Assembler produces relocatable machine code from symbolic assembly language for PIC24, PIC32 and dsPIC DSC devices. MPLAB XC Compiler uses the assembler to produce its object file. The assembler generates relocatable object files that can then be archived or linked with other relocatable object files and archives to create an executable file. Notable features of the assembler include: * * * * * * 38.6 Support for the entire device instruction set Support for fixed-point and floating-point data Command-line interface Rich directive set Flexible macro language MPLAB X IDE compatibility MPLAB X SIM Software Simulator The MPLAB X SIM Software Simulator allows code development in a PC-hosted environment by simulating the PIC MCUs and dsPIC DSCs on an instruction level. On any given instruction, the data areas can be examined or modified and stimuli can be applied from a comprehensive stimulus controller. Registers can be logged to files for further run-time analysis. The trace buffer and logic analyzer display extend the power of the simulator to record and track program execution, actions on I/O, most peripherals and internal registers. The MPLAB X SIM Software Simulator fully supports symbolic debugging using the MPLAB XC Compilers, and the MPASM and MPLAB Assemblers. The software simulator offers the flexibility to develop and debug code outside of the hardware laboratory environment, making it an excellent, economical software development tool. (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 766 PIC18F26/45/46Q10 Development Support 38.7 MPLAB REAL ICE In-Circuit Emulator System The MPLAB REAL ICE In-Circuit Emulator System is Microchip's next generation high-speed emulator for Microchip Flash DSC and MCU devices. It debugs and programs all 8, 16 and 32-bit MCU, and DSC devices with the easy-to-use, powerful graphical user interface of the MPLAB X IDE. The emulator is connected to the design engineer's PC using a high-speed USB 2.0 interface and is connected to the target with either a connector compatible with in-circuit debugger systems (RJ-11) or with the new high-speed, noise tolerant, Low-Voltage Differential Signal (LVDS) interconnection (CAT5). The emulator is field upgradable through future firmware downloads in MPLAB X IDE. MPLAB REAL ICE offers significant advantages over competitive emulators including full-speed emulation, run-time variable watches, trace analysis, complex breakpoints, logic probes, a ruggedized probe interface and long (up to three meters) interconnection cables. 38.8 MPLAB ICD 3 In-Circuit Debugger System The MPLAB ICD 3 In-Circuit Debugger System is Microchip's most cost-effective, high-speed hardware debugger/programmer for Microchip Flash DSC and MCU devices. It debugs and programs PIC Flash microcontrollers and dsPIC DSCs with the powerful, yet easy-to-use graphical user interface of the MPLAB IDE. The MPLAB ICD 3 In-Circuit Debugger probe is connected to the design engineer's PC using a highspeed USB 2.0 interface and is connected to the target with a connector compatible with the MPLAB ICD 2 or MPLAB REAL ICE systems (RJ-11). MPLAB ICD 3 supports all MPLAB ICD 2 headers. 38.9 PICkit 3 In-Circuit Debugger/Programmer The MPLAB PICkit 3 allows debugging and programming of PIC and dsPIC Flash microcontrollers at a most affordable price point using the powerful graphical user interface of the MPLAB IDE. The MPLAB PICkit 3 is connected to the design engineer's PC using a full-speed USB interface and can be connected to the target via a Microchip debug (RJ-11) connector (compatible with MPLAB ICD 3 and MPLAB REAL ICE). The connector uses two device I/O pins and the Reset line to implement in-circuit debugging and In-Circuit Serial ProgrammingTM (ICSPTM). 38.10 MPLAB PM3 Device Programmer The MPLAB PM3 Device Programmer is a universal, CE compliant device programmer with programmable voltage verification at Vddmin and Vddmax for maximum reliability. It features a large LCD display (128 x 64) for menus and error messages, and a modular, detachable socket assembly to support various package types. The ICSP cable assembly is included as a standard item. In Stand-Alone mode, the MPLAB PM3 Device Programmer can read, verify and program PIC devices without a PC connection. It can also set code protection in this mode. The MPLAB PM3 connects to the host PC via an RS-232 or USB cable. The MPLAB PM3 has high-speed communications and optimized algorithms for quick programming of large memory devices, and incorporates an MMC card for file storage and data applications. 38.11 Demonstration/Development Boards, Evaluation Kits, and Starter Kits A wide variety of demonstration, development and evaluation boards for various PIC MCUs and dsPIC DSCs allows quick application development on fully functional systems. Most boards include prototyping (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 767 PIC18F26/45/46Q10 Development Support areas for adding custom circuitry and provide application firmware and source code for examination and modification. The boards support a variety of features, including LEDs, temperature sensors, switches, speakers, RS-232 interfaces, LCD displays, potentiometers and additional EEPROM memory. The demonstration and development boards can be used in teaching environments, for prototyping custom circuits and for learning about various microcontroller applications. In addition to the PICDEMTM and dsPICDEMTM demonstration/development board series of circuits, (R) Microchip has a line of evaluation kits and demonstration software for analog filter design, KeeLoq (R) (R) security ICs, CAN, IrDA , PowerSmart battery management, SEEVAL evaluation system, Sigma-Delta ADC, flow rate sensing, plus many more. Also available are starter kits that contain everything needed to experience the specified device. This usually includes a single application and debug capability, all on one board. Check the Microchip webpage (www.microchip.com) for the complete list of demonstration, development and evaluation kits. 38.12 Third-Party Development Tools Microchip also offers a great collection of tools from third-party vendors. These tools are carefully selected to offer good value and unique functionality. * * * * * Device Programmers and Gang Programmers from companies, such as SoftLog and CCS Software Tools from companies, such as Gimpel and Trace Systems Protocol Analyzers from companies, such as Saleae and Total Phase (R) Demonstration Boards from companies, such as MikroElektronika, Digilent and Olimex (R) Embedded Ethernet Solutions from companies, such as EZ Web Lynx, WIZnet and IPLogika (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 768 PIC18F26/45/46Q10 Electrical Specifications 39. Electrical Specifications 39.1 Absolute Maximum Ratings() Parameter Ambient temperature under bias Storage temperature Voltage on pins with respect to VSS Rating -40C to +125C -65C to +150C * on VDD pin: -0.3V to +6.5V * on MCLR pin: -0.3V to +9.0V * on all other pins: -0.3V to (VDD + 0.3V) Maximum current(1) * on VSS pin * on VDD pin (28-pin devices) * on VDD pin (40-pin devices) -40C TA +85C 85C < TA +125C -40C TA +85C 85C < TA +125C -40C TA +85C 85C < TA +125C * on any standard I/O pin Clamp current, IK (VPIN < 0 or VPIN > VDD) Total power dissipation(2) 350 mA 120 mA 250 mA 85 mA 350 mA 120 mA 50 mA 20 mA 800 mW Important: 1. Maximum current rating requires even load distribution across I/O pins. Maximum current rating may be limited by the device package power dissipation characterizations, see Thermal Characteristics to calculate device specifications. 2. Power dissipation is calculated as follows: PDIS = VDD x {IDD - IOH} + {(VDD - VOH) x IOH} + (VOI x IOL) 3. Internal Power Dissipation is calculated as follows: PINTERNAL = IDD x VDD where IDD is current to run the chip alone without driving any load on the output pins. 4. I/O Power Dissipation is calculated as follows: PI/O =(IOL*VOL)+(IOH*(VDD-VOH)) 5. Derated Power is calculated as follows: PDER = PDMAX(TJ-TA)/JA where TA=Ambient Temperature, TJ = Junction Temperature. NOTICE: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure above maximum rating conditions for extended periods may affect device reliability. 39.2 Standard Operating Conditions The standard operating conditions for any device are defined as: (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 769 PIC18F26/45/46Q10 Electrical Specifications Operating Voltage: VDDMIN VDD VDDMAX TA_MIN TA TA_MAX Operating Temperature: Parameter VDD -- Operating Supply Voltage(1) TA -- Operating Ambient Temperature Range Industrial Temperature Extended Temperature VDDMIN VDDMAX Ratings +1.8V +5.5V TA_MIN TA_MAX TA_MIN TA_MAX -40C +85C -40C +125C Figure 39-1. Voltage Frequency Graph, -40C TA +125C Rev. 30-000069B 6/1/2017 VDD (V) 5.5 1.8 0 4 10 16 32 64 Frequency (MHz) Note: 1. The shaded region indicates the permissible combinations of voltage and frequency. 2. Refer to 39.4.1 External Clock/Oscillator Timing Requirements for each Oscillator mode's supported frequencies. (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 770 PIC18F26/45/46Q10 Electrical Specifications 39.3 DC Characteristics 39.3.1 Supply Voltage Table 39-1. Standard Operating Conditions (unless otherwise stated) Param. No. Sym. Characteristic Min. Typ. Max. Units Conditions 1.8 -- 5.5 V 1.7 -- -- V Device in SLEEP mode -- 1.6 -- V BOR and LPBOR disabled(3) -- 1 -- V BOR and LPBOR disabled(3) -- V/ms BOR and LPBOR disabled(3) Supply Voltage D002 VDD RAM Data Retention(1) D003 VDR Power-on Reset Release Voltage(2) D004 VPOR Power-on Reset Rearm Voltage(2) D005 VPORR VDD Rise Rate to ensure internal Power-on Reset signal(2) D006 SVDD 0.05 -- Data in "Typ." column is at 3.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note: 1. This is the limit to which VDD can be lowered in Sleep mode without losing RAM data. 2. See the following figure, POR and POR REARM with Slow Rising VDD. 3. See 39.4.5 Reset, WDT, Oscillator Start-up Timer, Power-up Timer, Brown-Out Reset and LowPower Brown-Out Reset Specifications for BOR and LPBOR trip point information. (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 771 PIC18F26/45/46Q10 Electrical Specifications Figure 39-2. POR and POR Rearm with Slow Rising VDD Rev. 30-000071A 4/6/2017 VDD VPOR VPORR SVDD VSS NPOR(1) POR REARM VSS TPOR(2) TVLOW(3) Note: 1. When NPOR is low, the device is held in Reset. 2. TPOR 1 s typical. 3. TVLOW 2.7 s typical. 39.3.2 Supply Current (IDD)(1,2,4) Table 39-2. Standard Operating Conditions (unless otherwise stated) Param. No. Sym. Device Characteristics D100 IDDXT4 XT = 4 MHz -- 490 770 A 3.0V D100A IDDXT4 XT = 4 MHz -- 410 -- A 3.0V D101 IDDHFO16 HFINTOSC = 16 MHz -- 1.3 1.7 mA 3.0V D101A IDDHFO16 HFINTOSC = 16 MHz -- 1.1 -- mA 3.0V D102 IDDHFOPLL HFINTOSC = 64 MHz -- 4.4 5.8 mA 3.0V D102A IDDHFOPLL HFINTOSC = 64 MHz -- 3.4 -- mA 3.0V D103 IDDHSPLL64 HS+PLL = 64 MHz -- 4.3 5.7 mA 3.0V D103A IDDHSPLL64 HS+PLL = 64 MHz -- 3.3 -- mA 3.0V (c) 2019 Microchip Technology Inc. Min. Typ. Max. Units Conditions VDD Datasheet Preliminary Note PMD's all 1's PMD's all 1's PMD's all 1's PMD's all 1's DS40001996C-page 772 PIC18F26/45/46Q10 Electrical Specifications ...........continued Standard Operating Conditions (unless otherwise stated) Param. No. Sym. Device Characteristics Min. D104 D105 Typ. Max. Units Conditions IDDIDLE IDLE mode, HFINTOSC = 16 MHz -- 0.6 -- mA 3.0V IDDDOZE(3) DOZE mode, HFINTOSC = 16 MHz, Doze Ratio = 16 -- 0.7 -- mA 3.0V VDD Note Data in "Typ." column is at 3.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note: 1. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins are outputs driven low; MCLR = VDD; WDT disabled. 2. The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O pin loading and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact on the current consumption. 3. IDDDOZE = [IDDIDLE*(N-1)/N] + IDDHFO16/N where N = DOZE Ratio (see CPUDOZE register). 4. PMD bits are all in the default state, no modules are disabled. Related Links 6.6.2 CPUDOZE 39.3.3 Power-Down Current (IPD)(1,2) Table 39-3. Standard Operating Conditions (unless otherwise stated) Param. Sym. No. Device Min. Typ. Max. Max. Units Characteristics +85C +125C D200 IPD IPD Base -- -- -- -- -- -- b'11' D200A IPD IPD Base -- 0.6 4.0 12 A 3.0V b'10' D200B -- 50 -- 90 A 3.0V b'01' D200C -- 170 -- 280 A 3.0V b'00' -- 0.9 5.0 13 A 3.0V b'10' D201 IPD_WDT Low-Frequency Internal Oscillator/WDT (c) 2019 Microchip Technology Inc. Datasheet Preliminary Conditions VDD VREGPM Note Reserved DS40001996C-page 773 PIC18F26/45/46Q10 Electrical Specifications ...........continued Standard Operating Conditions (unless otherwise stated) Param. Sym. No. Device Min. Typ. Max. Max. Units Characteristics +85C +125C D202* IPD_SOSC Secondary Oscillator (SOSC) D203 Conditions VDD VREGPM Note -- 1.6 4.3 10 A 3.0V b'10' IPD_LPBOR Low-Power Brown-out Reset (LPBOR) -- 0.9 5.0 13 A 3.0V b'10' D204 IPD_FVR FVR -- 70 105 110 A 3.0V b'10' or b'01' D205 IPD_BOR Brown-out Reset (BOR) -- 30 60 63 A 3.0V b'10' D206 IPD_HLVD High/Low Voltage Detect (HLVD) -- 22 -- -- A 3.0V b'10' D207 IPD_ADCA ADC - Active -- 330 -- -- A 3.0V b'10' or b'01' FVRCON = 0x81 or 0x84 ADC is converting (4) D208 IPD_CMP Comparator -- 60 85 90 A 3.0V b'10' * - These parameters are characterized but not tested. - Data in "Typ." column is at 3.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note: 1. The peripheral current is the sum of the base IDD and the additional current consumed when this peripheral is enabled. The peripheral current can be determined by subtracting the base IDD or IPDcurrent from this limit. Max. values should be used when calculating total current consumption. 2. The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode with all I/O pins in high-impedance state and tied to VSS. 3. All peripheral currents listed are on a per-peripheral basis if more than one instance of a peripheral is available. 4. ADC clock source is FRC. (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 774 PIC18F26/45/46Q10 Electrical Specifications 39.3.4 I/O Ports Table 39-4. Standard Operating Conditions (unless otherwise stated) Param. No. Sym. Device Characteristics Min. Typ. Max. Units Conditions -- -- 0.8 V 4.5VVDD5.5V -- -- 0.15 VDD V 1.8VVDD<4.5V 2.0VVDD5.5V Input Low Voltage VIL I/O PORT: D300 * with TTL buffer D301 D302 * with Schmitt Trigger buffer -- -- 0.2 VDD V D303 * with I2C levels -- -- 0.3 VDD V D304 * with SMBus levels -- -- 0.8 V -- -- 0.2 VDD V 2.0 -- -- V 4.5VVDD5.5V 0.25 VDD+0.8 -- -- V 1.8VVDD<4.5V 2.0VVDD5.5V D305 MCLR 2.7VVDD5.5V High Low Voltage VIH I/O PORT: D320 * with TTL buffer D321 D322 * with Schmitt Trigger buffer 0.8VDD -- -- V D323 * with I2C levels 0.7 VDD -- -- V D324 * with SMBus levels 2.1 -- -- V 0.7 VDD -- -- V -- 5 125 nA VSSVPINVDD, Pin at highimpedance, 85C -- 5 1000 nA VSSVPINVDD, Pin at highimpedance, 125C -- 50 200 nA VSSVPINVDD, Pin at highimpedance, 85C 80 140 200 A VDD=3.0V, VPIN=VSS -- -- 0.6 V IOL=10.0 mA, VDD=3.0V D325 MCLR Input Leakage D340 2.7VVDD5.5V Current(1) IIL I/O PORTS D341 MCLR(2) D342 Weak Pull-up Current D350 IPUR Output Low Voltage D360 VOL I/O PORTS Output High Voltage (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 775 PIC18F26/45/46Q10 Electrical Specifications ...........continued Standard Operating Conditions (unless otherwise stated) Param. No. Sym. Device Characteristics D370 I/O PORTS VOH Min. Typ. Max. Units Conditions VDD-0.7 -- -- V IOH=6.0 mA, VDD=3.0V -- 5 50 pF All I/O Pins D380 CIO Data in "Typ" column is at 3.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note: 1. Negative current is defined as current sourced by the pin. 2. The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. 39.3.5 Memory Programming Specifications Table 39-5. Standard Operating Conditions (unless otherwise stated) Param No. Sym. Device Characteristics Min. Typ Max. Units Conditions 100k -- -- E/W -40CTA+85C -- 40 -- Provided no other Year specifications are violated 1M 10M -- VDDMIN -- VDDMAX V -- 10 11 ms 10k -- -- -40CTa+85C E/W (Note 1) -- 40 -- Provided no other Year specifications are violated VDDMIN -- VDDMAX V VDDMIN -- VDDMAX V Data EEPROM Memory Specifications MEM20 ED DataEE Byte Endurance MEM21 TD_RET Characteristic Retention MEM22 ND_REF Total Erase/Write Cycles before Refresh MEM23 VD_RW VDD for Read or Erase/Write operation MEM24 TD_BEW Byte Erase and Write Cycle Time E/W -40C TA+85C Program Flash Memory Specifications MEM30 EP Flash Memory Cell Endurance MEM32 TP_RET Characteristic Retention MEM33 VP_RD VDD for Read operation MEM34 VP_REW VDD for Row Erase or Write operation (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 776 PIC18F26/45/46Q10 Electrical Specifications ...........continued Standard Operating Conditions (unless otherwise stated) Param No. Sym. Device Characteristics Min. Typ Max. Units MEM35 TP_REW Self-Timed Sector Write -- 6 10 ms MEM36 TSE -- 10 14 ms -- 55 80 s Self-Timed Sector Erase MEM37 TP_WRD Self-Timed Word Write Conditions Data in "Typ" column is at 3.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note: 1. Flash Memory Cell Endurance for the Flash memory is defined as: One Row Erase operation and one Self-Timed Write. 39.3.6 Thermal Characteristics Table 39-6. Standard Operating Conditions (unless otherwise stated) Param No. Sym. Characteristic TH01 JA Typ. Units Conditions Thermal Resistance Junction to Ambient 60 C/W 28-pin SPDIP package 80 C/W 28-pin SOIC package 90 C/W 28-pin SSOP package 27.5 C/W 28-pin VQFN 4x4 mm package 27.5 C/W 28-pin QFN 6x6 mm package 47.2 C/W 40-pin PDIP package 28.9 C/W 40-pin QFN package 46 TH03 TJMAX Maximum Junction Temperature C/W 44-pin TQFP package 150 C Note: 1. See "Absolute Maximum Ratings" for total power dissipation. (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 777 Filename: Title: Last Edit: First Used: Note: 39.4 PIC18F26/45/46Q10 10-000133A.vsd LOAD CONDITION 8/1/2013 PIC16F1508/9 Electrical Specifications AC Characteristics Figure 39-3. Load Conditions Rev. 10-000133A 8/1/2013 Load Condition Pin CL VSS Legend: CL=50 pF for all pins 39.4.1 External Clock/Oscillator Timing Requirements Figure 39-4. Clock Timing Rev. 30-000072A 4/6/2017 Q4 Q1 Q2 Q3 Q4 Q1 CLKIN OS2 OS1 OS2 OS20 CLKOUT (CLKOUT Mode) Note: See table below. Table 39-7. Standard Operating Conditions (unless otherwise stated) Param No. Sym. Characteristic Min. Typ. Max. Units Conditions ECL Oscillator OS1 FECL Clock Frequency -- -- 1 MHz OS2 TECL_DC Clock Duty Cycle 40 -- 60 % ECM Oscillator OS3 FECM Clock Frequency -- -- 16 MHz OS4 TECM_DC Clock Duty Cycle 40 -- 60 % ECH Oscillator OS5 FECH Clock Frequency -- -- 64 MHz OS6 TECH_DC Clock Duty Cycle 40 -- 60 % Clock Frequency -- -- 100 kHz LP Oscillator OS7 FLP (c) 2019 Microchip Technology Inc. Datasheet Preliminary Note 4 DS40001996C-page 778 PIC18F26/45/46Q10 Electrical Specifications ...........continued Standard Operating Conditions (unless otherwise stated) Param No. Sym. Characteristic Min. Typ. Max. Units Conditions Clock Frequency -- -- 4 MHz Note 4 Clock Frequency -- -- 20 MHz VDD>2.5V Note 4 Clock Frequency 32.4 32.768 33.1 kHz Note 4 (Note 2, Note 3) XT Oscillator OS8 FXT HS Oscillator OS9 FHS Secondary Oscillator OS10 FSEC System Oscillator OS20 FOSC System Clock Frequency -- -- 64 MHz OS21 FCY Instruction Frequency -- FOSC/4 -- MHz OS22 TCY Instruction Period 62.5 1/FCY -- ns Note: 1. Instruction cycle period (TCY) equals four times the input oscillator time base period. All specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested to operate at "min" values with an external clock applied to OSC1 pin. When an external clock input is used, the "max" cycle time limit is "DC" (no clock) for all devices. 2. The system clock frequency (FOSC) is selected by the "main clock switch controls" as described in the "Power Saving Operation Modes" section. 3. The system clock frequency (FOSC) must meet the voltage requirements defined in the "Standard Operating Conditions" section. 4. LP, XT and HS oscillator modes require an appropriate crystal or resonator to be connected to the device. For clocking the device with the external square wave, one of the EC mode selections must be used. Related Links 39.2 Standard Operating Conditions 6. Power-Saving Operation Modes (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 779 PIC18F26/45/46Q10 Electrical Specifications 39.4.2 Internal Oscillator Parameters(1) Table 39-8. Standard Operating Conditions (unless otherwise stated) Param No. Sym. Characteristic OS50 FHFOSC Precision Calibrated HFINTOSC Frequency Min. Typ. Max. Units Conditions -- 4 -- MHz (Note 2) Fundamental Freq.1 MHz 8 12 16 32 48 64 OS51 FHFOSCLP Low-Power Optimized HFINTOSC Frequency -- 1 -- MHz -- 2 -- MHz Fundamental Freq. 2 MHz OS52 FMFOSC Internal Calibrated MFINTOSC Frequency -- 500 -- kHz OS53* FLFOSC Internal LFINTOSC Frequency -- 31 -- kHz OS54* THFOSCST HFINTOSC Wakeup from Sleep Start-up Time -- 11 20 s VREGPM=0x -- 100 -- s VREGPM=1x LFINTOSC Wakeup from Sleep Start-up Time -- 0.3 -- ms OS56 TLFOSCST * - These parameters are characterized but not tested. Data in "Typ" column is at 3.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note: 1. To ensure these oscillator frequency tolerances, VDD and VSS must be capacitively decoupled as close to the device as possible. 0.1 F and 0.01 F values in parallel are recommended. 2. See the figure below. (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 780 PIC18F26/45/46Q10 Electrical Specifications Figure 39-5. Precision Calibrated HFINTOSC Frequency Accuracy Over Device VDD and Temperature Rev. 30-000073A 9/7/2017 125 5% Temperature (C) 85 3% 60 2% 0 5% -40 1.8 2.0 2.3 3.5 3.0 4.0 4.5 5.0 5.5 VDD (V) 39.4.3 PLL Specifications Table 39-9. Standard Operating Conditions (unless otherwise stated) Param No. Sym. Characteristic Min. Typ. Max. Units PLL01 FPLLIN PLL Input Frequency Range 4 -- 16 MHz PLL02 FPLLOUT PLL Output Frequency Range 16 -- 64 MHz PLL03* FPLLST PLL Lock Time -- 10 -- s PLL04* FPLLJIT PLL Output Frequency Stability -0.25 -- 0.25 % Conditions (Note 1) * - These parameters are characterized but not tested. Data in "Typ" column is at 3.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note: 1. The output frequency of the PLL must meet the FOSC requirements listed in Parameter D002. (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 781 PIC18F26/45/46Q10 Electrical Specifications 39.4.4 I/O and CLKOUT Timing Specifications Figure 39-6. CLKOUT and I/O Timing Rev. 30-000074A 4/6/2017 Cycle Write Fetch Q1 Q4 Read Execute Q2 Q3 FOSC IO2 IO1 IO10 CLKOUT IO8 IO7 IO4 IO5 I/O pin (Input) IO3 I/O pin (Output) New Value Old Value IO7, IO8 Table 39-10. I/O and CLKOUT Timing Specifications Standard Operating Conditions (unless otherwise stated) Param No. Sym. Characteristic Min. Typ. Max. Units Conditions IO1* TCLKOUTH CLKOUT rising edge delay (rising edge FOSC (Q1 cycle) to falling edge CLKOUT -- -- 70 ns IO2* TCLKOUTL CLKOUT falling edge delay (rising edge FOSC (Q3 cycle) to rising edge CLKOUT -- -- 72 ns IO3* TIO_VALID Port output valid time (rising edge FOSC (Q1 cycle) to port valid) -- 50 70 ns IO4* TIO_SETUP Port input setup time (Setup time before rising edge FOSC - Q2 cycle) 20 -- -- ns IO5* TIO_HOLD Port input hold time (Hold time after rising edge FOSC - Q2 cycle) 50 -- -- ns IO6* TIOR_SLREN Port I/O rise time, slew rate enabled -- 25 -- ns VDD=3.0V IO7* TIOR_SLRDIS Port I/O rise time, slew rate disabled -- 5 -- ns VDD=3.0V IO8* TIOF_SLREN Port I/O fall time, slew rate enabled -- 25 -- ns VDD=3.0V IO9* TIOF_SLRDIS Port I/O fall time, slew rate disabled -- 5 -- ns VDD=3.0V IO10* TINT INT pin high or low time to trigger an interrupt 25 -- -- ns IO11* TIOC Interrupt-on-Change minimum high or low time to trigger interrupt 25 -- -- ns * - These parameters are characterized but not tested. (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 782 PIC18F26/45/46Q10 Electrical Specifications 39.4.5 Reset, WDT, Oscillator Start-up Timer, Power-up Timer, Brown-Out Reset and Low-Power BrownOut Reset Specifications Figure 39-7. Reset, Watchdog Timer, Oscillator Start-up Timer and Power-up Timer Timing Rev. 30-000075A 4/6/2017 VDD MCLR RST01 Internal POR RST04 PWRT Time-out RST05 OSC Start-up Time Internal Reset(1) Watchdog Timer Reset(1) RST03 RST02 RST02 I/O pins Note: 1. Asserted low. Figure 39-8. Brown-out Reset Timing and Characteristics Rev. 30-000076A 4/6/2017 VDD VBOR and VHYST VBOR (Device in Brown-out Reset) (Device not in Brown-out Reset) RST08 Reset (due to BOR) RST04(1) Note: 1. Only if PWRTE bit in the Configuration Word register is programmed to `1'; 2 ms delay if PWRTE = 0. (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 783 PIC18F26/45/46Q10 Electrical Specifications Table 39-11. Standard Operating Conditions (unless otherwise stated) Param No. Sym. Characteristic Min. Typ. Max. Units RST01* TMCLR RST02* MCLR Pulse Width Low to ensure Reset 2 -- -- s TIOZ I/O high-impedance from Reset detection -- -- 2 s RST03 TWDT Watchdog Timer Time-out Period -- 16 -- ms RST04* TPWRT Power-up Timer Period -- 65 -- ms RST05 TOST Oscillator Start-up Timer Period(1,2) -- 1024 -- TOSC RST06 VBOR Brown-out Reset Voltage 2.7 2.85 3.0 V BORV=00 2.55 2.7 2.85 V BORV=01 2.3 2.45 2.6 V BORV=10 1.8 1.9 2.1 V BORV=11 BORV=00 RST07 VBORHYS Brown-out Reset Hysteresis -- 60 -- mV RST08 TBORDC Brown-out Reset Response Time -- 3 -- s RST09 VLPBOR Low-Power Brownout Reset Voltage 1.8 1.9 2.2 V Conditions WDTCPS=00100 * - These parameters are characterized but not tested. Data in "Typ" column is at 3.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note: 1. By design, the Oscillator Start-up Timer (OST) counts the first 1024 cycles, independent of frequency. 2. To ensure these voltage tolerances, VDD and VSS must be capacitively decoupled as close to the device as possible. 0.1 F and 0.01 F values in parallel are recommended. 39.4.6 High/Low-Voltage Detect Characteristics Table 39-12. Standard Operating Conditions (unless otherwise stated) Param No. Sym. Characteristic Min. Typ. Max. HLVD01 VDET Voltage Detect -- 1.90 -- V HLVDSEL=b'0000' -- 2.10 -- V HLVDSEL=b'0001' -- 2.25 -- V HLVDSEL=b'0010' (c) 2019 Microchip Technology Inc. Datasheet Preliminary Units Conditions DS40001996C-page 784 PIC18F26/45/46Q10 Electrical Specifications ...........continued Standard Operating Conditions (unless otherwise stated) Param No. 39.4.7 Sym. Characteristic Min. Typ. Max. Units Conditions -- 2.50 -- V HLVDSEL=b'0011' -- 2.60 -- V HLVDSEL=b'0100' -- 2.75 -- V HLVDSEL=b'0101' -- 2.90 -- V HLVDSEL=b'0110' -- 3.15 -- V HLVDSEL=b'0111' -- 3.35 -- V HLVDSEL=b'1000' -- 3.60 -- V HLVDSEL=b'1001' -- 3.75 -- V HLVDSEL=b'1010' -- 4.00 -- V HLVDSEL=b'1011' -- 4.20 -- V HLVDSEL=b'1100' -- 4.35 -- V HLVDSEL=b'1101' -- 4.65 -- V HLVDSEL=b'1110' Analog-to-Digital Converter (ADC) Accuracy Specifications(1,2) Table 39-13. Standard Operating Conditions (unless otherwise stated) VDD = 3.0V, TA = 25C, TAD = 1s Param No. Sym. Characteristic Min. Typ. Max. AD01 NR AD02 Resolution -- -- 10 bit EIL Integral Non-Linearity Error -- 0.1 1.0 LSb ADCREF+=3.0V, ADCREF- = 0V AD03 EDL Differential Non-Linearity Error -- 0.1 1.0 LSb ADCREF+=3.0V, ADCREF- = 0V AD04 EOFF Offset Error -- 0.5 2.0 LSb ADCREF+=3.0V, ADCREF- = 0V AD05 EGN Gain Error -- 0.2 2.0 LSb ADCREF+=3.0V, ADCREF- = 0V AD06 VADREF ADC Reference Voltage (ADREF+ - ADREF-) 1.8 -- VDD V AD07 VAIN Full-Scale Range ADREF- -- ADREF+ V AD08 ZAIN Recommended Impedance of Analog Voltage Source -- 10 -- k AD09 RVREF ADC Voltage Reference Ladder Impedance -- 50 -- k (c) 2019 Microchip Technology Inc. Datasheet Preliminary Units Conditions (Note 3) DS40001996C-page 785 PIC18F26/45/46Q10 Electrical Specifications ...........continued Standard Operating Conditions (unless otherwise stated) VDD = 3.0V, TA = 25C, TAD = 1s Param No. Sym. Characteristic Min. Typ. Max. Units Conditions * - These parameters are characterized but not tested. Data in "Typ" column is at 3.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note: 1. Total Absolute Error is the sum of the offset, gain and integral non-linearity (INL) errors. 2. The ADC conversion result never decreases with an increase in the input and has no missing codes. 3. This is the impedance seen by the VREF pads when the external reference pads are selected. 39.4.8 Analog-to-Digital Converter (ADC) Conversion Timing Specifications Table 39-14. Standard Operating Conditions (unless otherwise stated) Param No. Sym. Characteristic AD20 TAD ADC Clock Period AD21 Min. Typ. Max. Units Conditions 1 -- 9 s Using FOSC as the ADC clock source ADOCS = 0 1 2 6 s Using FRC as the ADC clock source ADOCS = 1 Set of GO/DONE bit to Clear of GO/ DONE bit AD22 TCNV Conversion Time(1) -- 11+3TCY -- TAD AD23 TACQ Acquisition Time -- 2 -- s AD24 THCD Sample-and-Hold Capacitor Disconnect Time -- -- -- s FOSC-based clock source FRC-based clock source * - These parameters are characterized but not tested. Data in "Typ" column is at 3.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note: 1. Does not apply for the ADCRC oscillator. (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 786 PIC18F26/45/46Q10 Electrical Specifications Figure 39-9. ADC Conversion Timing (ADC Clock FOSC-Based) Rev. 10-000321B 4/16/2019 BSF ADCON0, GO 1 TCY AD22 AD24 1 TCY 1 TCY AD20 ADC_clk ADRES OLD DATA NEW DATA ADIF GO DONE Sample Sampling Stopped Figure 39-10. ADC Conversion Timing (ADC Clock from ADCRC) Rev. 10-000328B 4/16/2019 BSF ADCON0, GO 1 TCY AD22 AD24 2 TCY (1) AD21 ADC_clk ADRES OLD DATA NEW DATA ADIF GO Sample DONE Sampling Stopped Note: 1. If the ADC clock source is selected as ADCRC, a time of TCY is added before the ADC clock starts. This allows the SLEEP instruction to be executed. (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 787 PIC18F26/45/46Q10 Electrical Specifications 39.4.9 Comparator Specifications Table 39-15. Standard Operating Conditions (unless otherwise stated) VDD = 3.0V, TA = 25C Param No. Sym. Characteristic Min. Typ. Max. Units Conditions CM01 VIOFF Input Offset Voltage -- -- 30 mV VICM=VDD/2 CM02 VICM Input Common Mode Range GND -- VDD V CM03 CMRR Common Mode Input Rejection Ratio -- 50 -- dB CM04 VHYST Comparator Hysteresis 10 25 40 mV CM05 TRESP(1) Response Time, Rising Edge -- 300 600 ns Response Time, Falling Edge -- 220 500 ns * - These parameters are characterized but not tested. Data in "Typ" column is at 3.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note: 1. Response time measured with one comparator input at VDD/2, while the other input transitions from VSS to VDD. 39.4.10 5-Bit DAC Specifications Table 39-16. Standard Operating Conditions (unless otherwise stated) VDD = 3.0V, TA = 25C Param No. Sym. Characteristic Min. Typ. Max. Units DSB01 VLSB Step-Size -- (VDACREF+VDACREF-)/32 -- V DSB02 VACC Absolute Accuracy -- -- 0.5 LSb DSB03* RUNIT Unit Resistor Value -- 5000 -- DSB04* TST Settling Time(1) -- -- 10 s (c) 2019 Microchip Technology Inc. Datasheet Preliminary Conditions DS40001996C-page 788 PIC18F26/45/46Q10 Electrical Specifications ...........continued Standard Operating Conditions (unless otherwise stated) VDD = 3.0V, TA = 25C Param No. Sym. Characteristic Min. Typ. Max. Units Conditions * - These parameters are characterized but not tested. Data in "Typ" column is at 3.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note: 1. Settling time measured while DACR<4:0> transitions from `00000' to `01111'. 39.4.11 Fixed Voltage Reference (FVR) Specifications Table 39-17. Standard Operating Conditions (unless otherwise stated) Param No. Sym. Characteristic Min. Typ. Max. Units Conditions FVR01 VFVR1 1x Gain (1.024V) -4 -- +4 % VDD2.5V, -40C to 85C FVR02 VFVR2 2x Gain (2.048V) -4 -- +4 % VDD2.5V, -40C to 85C FVR03 VFVR4 4x Gain (4.096V) -4 -- +4 % VDD4.75V, -40C to 85C FVR04 TFVRST FVR Start-up Time -- 25 -- s 39.4.12 Zero-Cross Detect (ZCD) Specifications Table 39-18. Standard Operating Conditions (unless otherwise stated) VDD = 3.0V, TA = 25C Param No. Sym. Characteristic Min. Typ. Max. Units ZC01 VPINZC Voltage on Zero Cross Pin -- 0.9 -- V ZC02 IZCD_MAX Maximum source or sink current -- -- 600 A ZC03 TRESPH Response Time, Rising Edge -- 1 -- s TRESPL Response Time, Falling Edge -- 1 -- s Conditions Data in "Typ" column is at 3.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 789 PIC18F26/45/46Q10 Electrical Specifications 39.4.13 Timer0 and Timer1 External Clock Requirements Table 39-19. Standard Operating Conditions (unless otherwise stated) Operating Temperature: -40CTA+125C Param No. Sym. Characteristic 40* TT0H T0CKI High Pulse Width 41* TT0L T0CKI Low Pulse Width Min. Typ. Max. 0.5TCY +20 -- -- ns 10 -- -- ns 0.5TCY +20 -- -- ns 10 -- -- ns Greater of: 20 or (TCY +40)/N -- -- ns Synchronous, No Prescaler 0.5TCY +20 -- -- ns Synchronous, with Prescaler 15 -- -- ns Asynchronous 30 -- -- ns 0.5TCY +20 -- -- ns Synchronous, with Prescaler 15 -- -- ns Asynchronous 30 -- -- ns Synchronous Greater of: 30 or (TCY +40)/N -- -- ns Asynchronous 60 -- -- ns 2 TOSC -- 7 TOSC -- No Prescaler With Prescaler No Prescaler With Prescaler 42* TT0P T0CKI Period 45* TT1H T1CKI High Time 46* 47* 49* TT1L TT1P T1CKI Synchronous, Low Time No Prescaler T1CKI Input Period TCKEZTMR1 Delay from External Clock Edge to Timer Increment Units Conditions N = Prescale value N = Prescale value Timers in Sync mode * - These parameters are characterized but not tested. Data in "Typ" column is at 3.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 790 PIC18F26/45/46Q10 Electrical Specifications Figure 39-11. Timer0 and Timing1 External Clock Timings Rev. 30-000079A 4/6/2017 T0CKI 40 41 42 T1CKI 45 46 49 47 TMR0 or TMR1 39.4.14 Capture/Compare/PWM Requirements (CCP) Table 39-20. Standard Operating Conditions (unless otherwise stated) Operating Temperature: -40CTA+125C Param No. Sym. Characteristic CC01* TCCL CCPx Input Low Time No Prescaler 0.5TCY+20 CCPx Input High Time No Prescaler 0.5TCY+20 CC02* CC03* TCCH TCCP CCPx Input Period Min. With Prescaler With Prescaler Typ. Max. -- -- ns -- -- ns -- -- ns 20 -- -- ns (3TCY +40)/N -- -- ns 20 Units Conditions N = Prescale value * - These parameters are characterized but not tested. Data in "Typ" column is at 3.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 791 PIC18F26/45/46Q10 Electrical Specifications Figure 39-12. Capture/Compare/PWM Timings (CCP) Rev. 30-000080A 4/6/2017 CCPx (Capture mode) CC01 CC02 CC03 Note: Refer to Figure 39-3 for load conditions. 39.4.15 EUSART Synchronous Transmission Requirements Table 39-21. Standard Operating Conditions (unless otherwise stated) Param No. Sym. Characteristic US120 TCKH2DTV SYNC XMIT (Master and Slave) -- 80 ns 3.0VVDD5.5V Clock high to data-out valid -- 100 ns 1.8VVDD5.5V Clock out rise time and fall time -- 45 ns 3.0VVDD5.5V (Master mode) -- 50 ns 1.8VVDD5.5V Data-out rise time and fall time -- 45 ns 3.0VVDD5.5V -- 50 ns 1.8VVDD5.5V US121 TCKRF US122 TDTRF Min. Max. Units Conditions Figure 39-13. EUSART Synchronous Transmission (Master/Slave) Timing Rev. 30-000081A 4/6/2017 CK US121 US121 DT US122 US120 Note: Refer to Figure 39-3 for load conditions. 39.4.16 EUSART Synchronous Receive Requirements Table 39-22. Standard Operating Conditions (unless otherwise stated) Param No. Sym. Characteristic Min. Max. Units Conditions US125 TDTV2CKL SYNC RCV (Master and Slave) 10 -- ns 15 -- ns Data-setup before CK (DT hold time) US126 TCKL2DTL (c) 2019 Microchip Technology Inc. Data-hold after CK (DT hold time) Datasheet Preliminary DS40001996C-page 792 PIC18F26/45/46Q10 Electrical Specifications Figure 39-14. EUSART Synchronous Receive (Master/Slave) Timing Rev. 30-000082A 4/6/2017 CK US125 DT US126 Note: Refer to Figure 39-3 for load conditions. 39.4.17 SPI Mode Requirements Table 39-23. Standard Operating Conditions (unless otherwise stated) Param No. Sym. Characteristic Min. Typ. Max. SP70* TSSL2SCH, SS to SCK or SCK input 2.25*TCY -- -- ns TSSL2SCL Units Conditions SP71* TSCH SCK input high time (Slave mode) TCY + 20 -- -- ns SP72* TSCL SCK input low time (Slave mode) TCY + 20 -- -- ns SP73* TDIV2SCH, Setup time of SDI data input to SCK edge 100 -- -- ns Hold time of SDI data input to SCK edge 100 -- -- ns SDO data output rise time -- 10 25 ns 3.0VVDD5.5V -- 25 50 ns 1.8VVDD5.5V TDIV2SCL SP74* TSCH2DIL, TSCL2DIL SP75* TDOR SP76* TDOF SDO data output fall time -- 10 25 ns SP77* TSSH2DOZ SS to SDO output high-impedance 10 -- 50 ns SP78* TSCR SCK output rise time (Master mode) -- 10 25 ns 3.0VVDD5.5V -- 25 50 ns 1.8VVDD5.5V SP79* TSCF SCK output fall time (Master mode) -- 10 25 ns SP80* TSCH2DOV, SDO data output valid after SCK edge -- -- 50 ns 3.0VVDD5.5V -- -- 145 ns 1.8VVDD5.5V TSCL2DOV (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 793 PIC18F26/45/46Q10 Electrical Specifications ...........continued Standard Operating Conditions (unless otherwise stated) Param No. Sym. Characteristic Min. Typ. Max. SP81* TDOV2SCH, SDO data output setup to SCK edge 1 TCY -- -- ns -- -- 50 ns 1.5 TCY + 40 -- -- ns TDOV2SCL SP82* TSSL2DOV SDO data output valid after SS edge SP83* TSCH2SSH, SS after SCK edge TSCL2SSH Units Conditions * - These parameters are characterized but not tested. Data in "Typ" column is at 3.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Figure 39-15. SPI Master Mode Timing (CKE = 0, SMP = 0) Rev. 30-000083A 4/6/2017 SS SP81 SCK (CKP = 0) SP71 SP72 SP78 SP79 SP79 SP78 SCK (CKP = 1) SP80 bit 6 - - - - - -1 MSb SDO LSb SP75, SP76 SDI MSb In bit 6 - - - -1 LSb In SP74 SP73 Note: Refer to Figure 39-3 for load conditions. (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 794 PIC18F26/45/46Q10 Electrical Specifications Figure 39-16. SPI Master Mode Timing (CKE = 1, SMP = 1) Rev. 30-000084A 4/6/2017 SS SP81 SCK (CKP = 0) SP71 SP72 SP79 SP73 SCK (CKP = 1) SP80 SDO MSb SP78 LSb bit 6 - - - - - -1 SP75, SP76 SDI MSb In bit 6 - - - -1 LSb In SP74 Note: Refer to Figure 39-3 for load conditions. Figure 39-17. SPI Slave Mode Timing (CKE = 0) Rev. 30-000085A 4/6/2017 SS SP70 SCK (CKP = 0) SP83 SP71 SP72 SP78 SP79 SP79 SP78 SCK (CKP = 1) SP80 SDO MSb bit 6 - - - - - -1 LSb SP77 SP75, SP76 SDI MSb In bit 6 - - - -1 LSb In SP74 SP73 Note: Refer to Figure 39-3 for load conditions. (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 795 PIC18F26/45/46Q10 Electrical Specifications Figure 39-18. SPI Slave Mode Timing (CKE = 1) Rev. 30-000086A 4/6/2017 SP82 SS SP70 SP83 SCK (CKP = 0) SP71 SP72 SCK (CKP = 1) SP80 MSb SDO bit 6 - - - - - -1 LSb SP77 SP75, SP76 SDI MSb In bit 6 - - - -1 LSb In SP74 Note: Refer to Figure 39-3 for load conditions. 39.4.18 I2C Bus Start/Stop Bits Requirements Table 39-24. Standard Operating Conditions (unless otherwise stated) Param. No. Sym. SP90* SP91* SP92* Characteristic Min. Typ. Max. Units Conditions TSU:STA Start condition 100 kHz mode Setup time 400 kHz mode 4700 -- -- 600 -- -- THD:STA Start condition 100 kHz mode Hold time 400 kHz mode 4000 -- -- 600 -- -- TSU:STO Stop condition 100 kHz mode Setup time 400 kHz mode 4700 -- -- 600 -- -- (c) 2019 Microchip Technology Inc. Datasheet Preliminary ns Only relevant for Repeated Start Setup time 400 kHz mode 600 condition ns After this period, the first clock Hold time 400 kHz mode 600 -- -- pulse is generated ns DS40001996C-page 796 PIC18F26/45/46Q10 Electrical Specifications ...........continued Standard Operating Conditions (unless otherwise stated) Param. No. Sym. SP93* Characteristic Min. Typ. Max. Units Conditions THD:STO Stop condition 100 kHz mode Hold time 400 kHz mode 4000 -- -- 600 -- -- ns * - These parameters are characterized but not tested. Figure 39-19. I2C Bus Start/Stop Bits Timing Rev. 30-000087A 4/6/2017 SCL SP93 SP91 SP90 SP92 SDA Stop Condition Start Condition Note: Refer to Figure 39-3 for load conditions. 39.4.19 I2C Bus Data Requirements Table 39-25. Standard Operating Conditions (unless otherwise stated) Param. No. Sym. Characteristic SP100* THIGH Clock high time (c) 2019 Microchip Technology Inc. Min. Max. Units 100 kHz mode 4.0 -- s Device must operate at a minimum of 1.5 MHz 400 kHz mode 0.6 -- s Device must operate at a minimum of 10 MHz SSP module 1.5TCY -- Datasheet Preliminary Conditions DS40001996C-page 797 PIC18F26/45/46Q10 Electrical Specifications ...........continued Standard Operating Conditions (unless otherwise stated) Param. No. Sym. Characteristic SP101* TLOW Clock low time SP102* SP103* SP106* SP107* SP109* SP110* TR TF THD:DAT TSU:DAT TAA TBUF Min. Max. Units 100 kHz mode 4.7 -- s Device must operate at a minimum of 1.5 MHz 400 kHz mode 1.3 -- s Device must operate at a minimum of 10 MHz SSP module 1.5TCY -- SDA and SCL rise time 100 kHz mode -- 1000 ns 400 kHz mode 20 + 0.1CB 300 ns SDA and SCL fall time 100 kHz mode -- 250 ns 400 kHz mode 20 + 0.1CB 250 ns Data input hold time 100 kHz mode 0 -- ns 400 kHz mode 0 0.9 s 100 kHz mode 250 -- ns 400 kHz mode 100 -- ns 100 kHz mode -- 3500 ns 400 kHz mode -- -- ns 100 kHz mode 4.7 -- s 400 kHz mode 1.3 -- s Data input setup time Output valid from clock Bus free time (c) 2019 Microchip Technology Inc. Datasheet Preliminary Conditions CB is specified to be from 10-400 pF CB is specified to be from 10-400 pF (Note 2) (Note 1) Time the bus must be free before a new transmission can start DS40001996C-page 798 PIC18F26/45/46Q10 Electrical Specifications ...........continued Standard Operating Conditions (unless otherwise stated) Param. No. Sym. Characteristic Min. SP111 CB Bus capacitive loading Max. Units -- Conditions pF * - These parameters are characterized but not tested. Note: 1. As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region (min. 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions. 2. A Fast mode (400 kHz) I2C bus device can be used in a Standard mode (100 kHz) I2C bus system, but the requirement TSU:DAT250 ns must then be met. This will automatically be the case if the device does not stretch the low period of the SCL signal. If such a device does stretch the low period of the SCL signal, it must output the next data bit to the SDA line TR max. + TSU:DAT = 1000 + 250 = 1250 ns (according to the Standard mode I2C bus specification), before the SCL line is released. Figure 39-20. I2C Bus Data Timing Rev. 30-000088A 4/6/2017 SP100 SP103 SCL SP102 SP101 SP90 SP106 SP107 SP92 SP91 SDA In SP110 SP109 SP109 SDA Out Note: Refer to Figure 39-3 for load conditions. 39.4.20 Configurable Logic Cell (CLC) Characteristics Table 39-26. Standard Operating Conditions (unless otherwise stated) Operating Temperature: -40CTA+125C Param No. Sym. Characteristic Min. Typ. Max. Units Conditions CLC01* TCLCIN CLC input time -- 7 OS17 ns (Note1) CLC02* TCLC CLC module input to output propagation time -- 24 -- ns VDD = 1.8V -- 12 -- ns VDD > 3.6V CLC output time Rise Time -- OS18 -- -- (Note1) Fall Time -- OS19 -- -- (Note1) CLC03* TCLCOUT (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 799 PIC18F26/45/46Q10 Electrical Specifications ...........continued Standard Operating Conditions (unless otherwise stated) Operating Temperature: -40CTA+125C Param No. Sym. Characteristic CLC04* CLC maximum switching frequency FCLCMAX Min. Typ. Max. Units -- -- OS20 -- Conditions * - These parameters are characterized but not tested. - Data in "Typ" column is at 3.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note: 1. See "I/O and CLKOUT Timing Specifications" for OS7, OS8 and OS9 rise and fall times. Figure 39-21. CLC Propagation Timing Rev. 30-000153A 10/27/2017 CLCxINn CLC Input time CLCxINn CLC Input time CLC01 (c) 2019 Microchip Technology Inc. LCx_in[n](1) LCx_in[n](1) CLC Module LCx_out(1) CLC Output time CLCx CLC Module LCx_out(1) CLC Output time CLCx CLC02 Datasheet Preliminary CLC03 DS40001996C-page 800 PIC18F26/45/46Q10 DC and AC Characteristics Graphs and Tables 40. DC and AC Characteristics Graphs and Tables Graphs and tables are not available at this time. (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 801 PIC18F26/45/46Q10 Packaging Information 41. Packaging Information Package Marking Information Rev. 30-009000A 5/17/2017 Legend: XX...X Y YY WW NNN Pe3 * Note: Customer-specific information or Microchip part number Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week `01') Alphanumeric traceability code b - free JEDEC (R) designator for Matte Tin (Sn) This package is Pb-free. The Pb-free JEDEC designator ( e3 ) can be found on the outer packaging for this package. In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. Rev. 30-009028A 5/17/2017 28-Lead SPDIP (.300") Example PIC18F27Q10 /SP e3 1526017 Rev. 30-009028B 5/17/2017 28-Lead SOIC (7.50 mm) Example XXXXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXXXX PIC18F27Q10 /SO e3 1526017 YYWWNNN (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 802 PIC18F26/45/46Q10 Packaging Information Rev. 30-009028C5/17/2017 28-Lead SSOP (5.30 mm) Example PIC18F27Q10 /SS e3 1526017 Rev. 30-009028D 5/17/2017 28-Lead QFN (6x6 mm) PIN 1 Example PIN 1 18F27Q10 /ML e3 1526017 XXXXXXXX XXXXXXXX YYWWNNN Rev. 30-009028F4/2/2018 28-Lead VQFN (4x4x1 mm) PIN 1 Example PIN 1 PIC18 F27Q10 /MV e 526017 3 (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 803 PIC18F26/45/46Q10 Packaging Information Rev. 30-009040A5/17/2017 40-Lead PDIP (600 mil) Example PIC18F45Q10 /P e3 XXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXX YYWWNNN 1526017 Rev. 30-009040D6/25/2018 Example 40-Lead QFN (5x5x0.9 mm) PIN 1 PIN 1 PIC18 F47Q10 /MP e 1526017 3 Rev. 30-009044B 5/18/2017 Example 44-Lead TQFP (10x10x1 mm) 18F47Q10 /PT e3 XXXXXXXXXX XXXXXXXXXX XXXXXXXXXX YYWWNNN 41.1 1526017 Package Details The following sections give the technical details of the packages. (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 804 M PIC18F26/45/46Q10 Packaging Diagrams and Parameters Packaging Information 28-Lead Skinny Plastic Dual In-Line (SP) - 300 mil Body [SPDIP] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging N NOTE 1 E1 1 2 3 D E A2 A L c b1 A1 b e eB Units Dimension Limits Number of Pins INCHES MIN NOM N MAX 28 Pitch e Top to Seating Plane A - - .200 Molded Package Thickness A2 .120 .135 .150 Base to Seating Plane A1 .015 - - Shoulder to Shoulder Width E .290 .310 .335 Molded Package Width E1 .240 .285 .295 Overall Length D 1.345 1.365 1.400 Tip to Seating Plane L .110 .130 .150 Lead Thickness c .008 .010 .015 b1 .040 .050 .070 b .014 .018 .022 eB - - Upper Lead Width Lower Lead Width Overall Row Spacing .100 BSC .430 Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. Significant Characteristic. 3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" per side. 4. Dimensioning and tolerancing per ASME Y14.5M. BSC: Basic Dimension. Theoretically exact value shown without tolerances. Microchip Technology Drawing C04-070B (c) 2007 Microchip Technology Inc. (c) 2019 Microchip Technology Inc. DS00049AR-page 57 Datasheet Preliminary DS40001996C-page 805 M Note: PIC18F26/45/46Q10 Packaging Diagrams and Parameters Packaging Information For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 2009 Microchip Technology Inc. DS00049BC-page 110 (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 806 M PIC18F26/45/46Q10 Packaging Diagrams and Parameters Packaging Information Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 2009 Microchip Technology Inc. (c) 2019 Microchip Technology Inc. DS00049BC-page 109 Datasheet Preliminary DS40001996C-page 807 M Note: PIC18F26/45/46Q10 Packaging Diagrams and Parameters Packaging Information For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 2009 Microchip Technology Inc. DS00049BC-page 104 (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 808 PIC18F26/45/46Q10 Packaging Information R 28-Lead Plastic Shrink Small Outline (SS) - 5.30 mm Body [SSOP] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging D A B N (DATUM A) (DATUM B) E1 E 1 2 28X b 0.15 e C A B TOP VIEW A A1 C A A2 SEATING PLANE 28X 0.10 C SIDE VIEW A H c L VIEW A-A (L1) Microchip Technology Drawing C04-073 Rev C Sheet 1 of 2 (c) 2017 Microchip Technology Inc. (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 809 PIC18F26/45/46Q10 Packaging Information R 28-Lead Plastic Shrink Small Outline (SS) - 5.30 mm Body [SSOP] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging G1 28 SILK SCREEN C Y1 1 2 X1 E RECOMMENDED LAND PATTERN Units Dimension Limits Contact Pitch E Contact Pad Spacing C Contact Pad Width (X28) X1 Contact Pad Length (X28) Y1 Contact Pad to Center Pad (X26) G1 MIN MILLIMETERS NOM 0.65 BSC 7.00 MAX 0.45 1.85 0.20 Notes: 1. Dimensioning and tolerancing per ASME Y14.5M BSC: Basic Dimension. Theoretically exact value shown without tolerances. 2. For best soldering results, thermal vias, if used, should be filled or tented to avoid solder loss during reflow process Microchip Technology Drawing C04-2073 Rev B (c) 2017 Microchip Technology Inc. (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 810 PIC18F26/45/46Q10 Packaging Information (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 811 PIC18F26/45/46Q10 Packaging Information (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 812 M PIC18F26/45/46Q10 Land Pattern (Footprint) Packaging Information 28-Lead Plastic Quad Flat, No Lead Package (ML) - 6x6 mm Body [QFN] with 0.55 mm Contact Length Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging (c) 2007 Microchip Technology Inc. (c) 2019 Microchip Technology Inc. DS00049AR-page 101 Datasheet Preliminary DS40001996C-page 813 PIC18F26/45/46Q10 Packaging Information 28-Lead Very Thin Plastic Quad Flat, No Lead (STX) - 4x4 mm Body [VQFN] With 2.65x2.65 mm Exposed Pad Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging D NOTE 1 A B N 1 2 E (DATUM B) (DATUM A) 2X 0.10 C 2X TOP VIEW 0.10 C 0.10 C C A A SEATING PLANE 28X (A3) 0.08 C SIDE VIEW 0.10 C A B D2 L 0.10 C A B E2 2 1 CH (K) N NOTE 1 28X b 0.07 e C A B BOTTOM VIEW Microchip Technology Drawing C04-456 Rev A Sheet 1 of 2 (c) 2017 Microchip Technology Inc. (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 814 PIC18F26/45/46Q10 Packaging Information 28-Lead Very Thin Plastic Quad Flat, No Lead (STX) - 4x4 mm Body [VQFN] With 2.65x2.65 mm Exposed Pad Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging Units Dimension Limits N Number of Terminals e Pitch Overall Height A Standoff A1 A3 Terminal Thickness Overall Length D Exposed Pad Length D2 E Overall Width Exposed Pad Width E2 Exposed Pad Corner Chamfer CH b Terminal Width L Terminal Length Terminal-to-Exposed-Pad K MIN 0.80 0.00 2.55 2.55 0.15 0.30 MILLIMETERS NOM 28 0.40 BSC 0.90 0.02 0.127 REF 4.00 BSC 2.65 4.00 BSC 2.65 0.25 0.20 0.40 0.275 REF MAX 1.00 0.05 2.75 2.75 0.25 0.50 Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. Package is saw singulated 3. Dimensioning and tolerancing per ASME Y14.5M BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. Microchip Technology Drawing C04-456 Rev A Sheet 2 of 2 (c) 2017 Microchip Technology Inc. (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 815 PIC18F26/45/46Q10 Packaging Information 28-Lead Very Thin Plastic Quad Flat, No Lead (STX) - 4x4 mm Body [VQFN] With 2.65x2.65 mm Exposed Pad Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging C1 X2 EV OV C2 Y2 EV G1 Y1 SILK SCREEN G2 X1 E RECOMMENDED LAND PATTERN Units Dimension Limits E Contact Pitch Optional Center Pad Width X2 Optional Center Pad Length Y2 Contact Pad Spacing C1 Contact Pad Spacing C2 Contact Pad Width (X28) X1 Contact Pad Length (X28) Y1 Contact Pad to Center Pad (X28) G1 Contact Pad to Contact Pad (X24) G2 Thermal Via Diameter V Thermal Via Pitch EV MIN MILLIMETERS NOM 0.40 BSC MAX 2.75 2.75 4.00 4.00 0.20 0.80 0.23 0.20 0.30 1.00 Notes: 1. Dimensioning and tolerancing per ASME Y14.5M BSC: Basic Dimension. Theoretically exact value shown without tolerances. 2. For best soldering results, thermal vias, if used, should be filled or tented to avoid solder loss during reflow process Microchip Technology Drawing C04-2456 Rev A (c) 2017 Microchip Technology Inc. (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 816 M PIC18F26/45/46Q10 Packaging Diagrams and Parameters Packaging Information 40-Lead Plastic Dual In-Line (P) - 600 mil Body [PDIP] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging N NOTE 1 E1 1 2 3 D E A2 A L c b1 A1 b e eB Units Dimension Limits Number of Pins INCHES MIN NOM N MAX 40 Pitch e Top to Seating Plane A - - .250 Molded Package Thickness A2 .125 - .195 Base to Seating Plane A1 .015 - - Shoulder to Shoulder Width E .590 - .625 Molded Package Width E1 .485 - .580 Overall Length D 1.980 - 2.095 Tip to Seating Plane L .115 - .200 Lead Thickness c .008 - .015 b1 .030 - .070 b .014 - .023 eB - - Upper Lead Width Lower Lead Width Overall Row Spacing .100 BSC .700 Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. Significant Characteristic. 3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" per side. 4. Dimensioning and tolerancing per ASME Y14.5M. BSC: Basic Dimension. Theoretically exact value shown without tolerances. Microchip Technology Drawing C04-016B (c) 2007 Microchip Technology Inc. (c) 2019 Microchip Technology Inc. DS00049AR-page 61 Datasheet Preliminary DS40001996C-page 817 PIC18F26/45/46Q10 Packaging Information 40-Lead Plastic Quad Flat, No Lead Package (MP) - 5x5 mm Body [QFN] With 3.7x3.7 mm Exposed Pad Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging D A B N 1 2 NOTE 1 E (DATUM B) (DATUM A) 2X 0.20 C 2X TOP VIEW 0.20 C C SEATING PLANE 0.10 C A1 A (A3) SIDE VIEW 0.08 C 0.10 C A B D2 0.10 C A B E2 K 2 1 N L e 40X b 0.07 0.05 C A B C Microchip Technology Drawing C04-047-002A Sheet 1 of 2 (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 818 PIC18F26/45/46Q10 Packaging Information 40-Lead Plastic Quad Flat, No Lead Package (MP) - 5x5 mm Body [QFN] With 3.7x3.7 mm Exposed Pad Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging Units Dimension Limits Number of Terminals N e Pitch A Overall Height Standoff A1 A3 Terminal Thickness Overall Width E E2 Exposed Pad Width D Overall Length D2 Exposed Pad Length b Terminal Width Terminal Length L K Terminal-to-Exposed-Pad MIN 0.80 0.00 0.15 0.30 0.20 MILLIMETERS NOM 40 0.40 BSC 0.85 0.02 0.20 REF 5.00 BSC 3.70 BSC 5.00 BSC 3.70 BSC 0.20 0.40 - MAX 0.90 0.05 0.25 0.50 - Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. Package is saw singulated 3. Dimensioning and tolerancing per ASME Y14.5M BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. Microchip Technology Drawing C04-047-002A Sheet 2 of 2 (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 819 PIC18F26/45/46Q10 Packaging Information 40-Lead Plastic Quad Flat, No Lead Package (MP) - 5x5 mm Body [QFN] With 3.7x3.7 mm Exposed Pad Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging C1 X2 E C2 Y2 Y1 X1 SILK SCREEN RECOMMENDED LAND PATTERN Units Dimension Limits E Contact Pitch X2 Optional Center Pad Width Optional Center Pad Length Y2 C1 Contact Pad Spacing Contact Pad Spacing C2 Contact Pad Width (X40) X1 Contact Pad Length (X40) Y1 MIN MILLIMETERS NOM 0.40 BSC MAX 3.80 3.80 5.00 5.00 0.20 0.80 Notes: 1. Dimensioning and tolerancing per ASME Y14.5M BSC: Basic Dimension. Theoretically exact value shown without tolerances. Microchip Technology Drawing C04-2047-002A (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 820 PIC18F26/45/46Q10 Packaging Information 44-Lead Plastic Thin Quad Flatpack (PT) - 10x10x1.0 mm Body [TQFP] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging A D D1 NOTE 2 B (DATUM A) (DATUM B) E1 A NOTE 1 2X 0.20 H A B E A N 2X 1 2 3 0.20 H A B TOP VIEW 4X 11 TIPS 0.20 C A B A C A2 SEATING PLANE 0.10 C SIDE VIEW A1 1 2 3 N NOTE 1 44 X b 0.20 e C A B BOTTOM VIEW Microchip Technology Drawing C04-076C Sheet 1 of 2 (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 821 PIC18F26/45/46Q10 Packaging Information 44-Lead Plastic Thin Quad Flatpack (PT) - 10x10x1.0 mm Body [TQFP] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging H c L (L1) SECTION A-A Units Dimension Limits N Number of Leads e Lead Pitch A Overall Height Standoff A1 A2 Molded Package Thickness E Overall Width Molded Package Width E1 D Overall Length D1 Molded Package Length b Lead Width c Lead Thickness Lead Length L Footprint L1 Foot Angle MIN 0.05 0.95 0.30 0.09 0.45 0 MILLIMETERS NOM 44 0.80 BSC 1.00 12.00 BSC 10.00 BSC 12.00 BSC 10.00 BSC 0.37 0.60 1.00 REF 3.5 MAX 1.20 0.15 1.05 0.45 0.20 0.75 7 Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. Exact shape of each corner is optional. 3. Dimensioning and tolerancing per ASME Y14.5M BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. Microchip Technology Drawing C04-076C Sheet 2 of 2 (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 822 PIC18F26/45/46Q10 Packaging Information 44-Lead Plastic Thin Quad Flatpack (PT) - 10X10X1 mm Body, 2.00 mm Footprint [TQFP] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging C1 44 1 2 G C2 Y1 X1 E SILK SCREEN RECOMMENDED LAND PATTERN Units Dimension Limits Contact Pitch E Contact Pad Spacing C1 Contact Pad Spacing C2 Contact Pad Width (X44) X1 Contact Pad Length (X44) Y1 Distance Between Pads G MIN MILLIMETERS NOM 0.80 BSC 11.40 11.40 MAX 0.55 1.50 0.25 Notes: 1. Dimensioning and tolerancing per ASME Y14.5M BSC: Basic Dimension. Theoretically exact value shown without tolerances. Microchip Technology Drawing No. C04-2076B (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 823 PIC18F26/45/46Q10 Revision History 42. Revision History Doc Rev. Date Comments C 5/2019 Removed 44-pin QFN packages Corrected Tables 1, 2, 39-3, 39-5, 39-6, 39-8, 39-13, 39-15, and 39-18; Corrected Figures 39-9 and 39-10 B 11/2018 Corrected capitalization and hyphens. Changes to: Sections 14.12.7, 22.3.2 (note), 22.6.1(note), 24.11.1, 25.11.1.3, 26, 26.4.5(note1), 33.1.2(note) Figures 1, 25-3 through 25-11, 25-14, 25-15 Tables 2, 39-4, 39-6 Trademarks A 03/2018 Initial document release. (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 824 PIC18F26/45/46Q10 The Microchip Web Site Microchip provides online support via our web site at http://www.microchip.com/. This web site is used as a means to make files and information easily available to customers. Accessible by using your favorite Internet browser, the web site contains the following information: * Product Support - Data sheets and errata, application notes and sample programs, design resources, user's guides and hardware support documents, latest software releases and archived software * General Technical Support - Frequently Asked Questions (FAQ), technical support requests, online discussion groups, Microchip consultant program member listing * Business of Microchip - Product selector and ordering guides, latest Microchip press releases, listing of seminars and events, listings of Microchip sales offices, distributors and factory representatives Customer Change Notification Service Microchip's customer notification service helps keep customers current on Microchip products. Subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or development tool of interest. To register, access the Microchip web site at http://www.microchip.com/. Under "Support", click on "Customer Change Notification" and follow the registration instructions. Customer Support Users of Microchip products can receive assistance through several channels: * * * * Distributor or Representative Local Sales Office Field Application Engineer (FAE) Technical Support Customers should contact their distributor, representative or Field Application Engineer (FAE) for support. Local sales offices are also available to help customers. A listing of sales offices and locations is included in the back of this document. Technical support is available through the web site at: http://www.microchip.com/support (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 825 PIC18F26/45/46Q10 Product Identification System To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. Device [X](1) -X /XX Tape Temperature and Reel Range Package Device: PIC18F26Q10, PIC18F45Q10, PIC18F46Q10 Tape & Reel Option: Blank = Tube T = Tape & Reel I = -40C to +85C (Industrial) E = -40C to +125C (Extended) STX = 28-lead VQFN 4x4x1 mm ML = 28-lead QFN 6x6x0.9 mm SO = 28-lead SOIC SP = 28-lead Skinny Plastic DIP SS = 28-lead SSOP P = 40-lead PDIP MP = 40-lead QFN 5x5x0.9 mm PT = 44-lead TQFP Temperature Range: Package: Examples: * PIC18F26Q10-E/P 301: Extended temp., PDIP package, QTP pattern #301. * PIC18F45Q10-E/PT = Extended temp., TQFP package. * PIC18F46Q10T-I/MP = Tape and reel, Industrial temp., QFN package. Note: 1. Tape and Reel identifier only appears in the catalog part number description. This identifier is used for ordering purposes and is not printed on the device package. Check with your Microchip Sales Office for package availability with the Tape and Reel option. 2. Small form-factor packaging options may be available. Please check http://www.microchip.com/ packaging for small-form factor package availability, or contact your local Sales Office. Microchip Devices Code Protection Feature Note the following details of the code protection feature on Microchip devices: * Microchip products meet the specification contained in their particular Microchip Data Sheet. * Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. * There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 826 PIC18F26/45/46Q10 operating specifications contained in Microchip's Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. * Microchip is willing to work with the customer who is concerned about the integrity of their code. * Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as "unbreakable." Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip's code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Legal Notice Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer's risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights unless otherwise stated. Trademarks The Microchip name and logo, the Microchip logo, AnyRate, AVR, AVR logo, AVR Freaks, BitCloud, chipKIT, chipKIT logo, CryptoMemory, CryptoRF, dsPIC, FlashFlex, flexPWR, Heldo, JukeBlox, KeeLoq, Kleer, LANCheck, LINK MD, maXStylus, maXTouch, MediaLB, megaAVR, MOST, MOST logo, MPLAB, OptoLyzer, PIC, picoPower, PICSTART, PIC32 logo, Prochip Designer, QTouch, SAM-BA, SpyNIC, SST, SST Logo, SuperFlash, tinyAVR, UNI/O, and XMEGA are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. ClockWorks, The Embedded Control Solutions Company, EtherSynch, Hyper Speed Control, HyperLight Load, IntelliMOS, mTouch, Precision Edge, and Quiet-Wire are registered trademarks of Microchip Technology Incorporated in the U.S.A. Adjacent Key Suppression, AKS, Analog-for-the-Digital Age, Any Capacitor, AnyIn, AnyOut, BodyCom, CodeGuard, CryptoAuthentication, CryptoAutomotive, CryptoCompanion, CryptoController, dsPICDEM, dsPICDEM.net, Dynamic Average Matching, DAM, ECAN, EtherGREEN, In-Circuit Serial Programming, ICSP, INICnet, Inter-Chip Connectivity, JitterBlocker, KleerNet, KleerNet logo, memBrain, Mindi, MiWi, motorBench, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach, Omniscient Code Generation, PICDEM, PICDEM.net, PICkit, PICtail, PowerSmart, PureSilicon, QMatrix, REAL ICE, Ripple Blocker, SAM-ICE, Serial Quad I/O, SMART-I.S., SQI, SuperSwitcher, SuperSwitcher II, Total Endurance, TSHARC, USBCheck, VariSense, ViewSpan, WiperLock, Wireless DNA, and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. Silicon Storage Technology is a registered trademark of Microchip Technology Inc. in other countries. (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 827 PIC18F26/45/46Q10 GestIC is a registered trademark of Microchip Technology Germany II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in other countries. All other trademarks mentioned herein are property of their respective companies. (c) 2019, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. ISBN: 978-1-5224-4460-2 Quality Management System Certified by DNV ISO/TS 16949 Microchip received ISO/TS-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California (R) (R) and India. The Company's quality system processes and procedures are for its PIC MCUs and dsPIC (R) DSCs, KEELOQ code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip's quality system for the design and manufacture of development systems is ISO 9001:2000 certified. (c) 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 828 Worldwide Sales and Service AMERICAS ASIA/PACIFIC ASIA/PACIFIC EUROPE Corporate Office 2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 480-792-7200 Fax: 480-792-7277 Technical Support: http://www.microchip.com/ support Web Address: www.microchip.com Atlanta Duluth, GA Tel: 678-957-9614 Fax: 678-957-1455 Austin, TX Tel: 512-257-3370 Boston Westborough, MA Tel: 774-760-0087 Fax: 774-760-0088 Chicago Itasca, IL Tel: 630-285-0071 Fax: 630-285-0075 Dallas Addison, TX Tel: 972-818-7423 Fax: 972-818-2924 Detroit Novi, MI Tel: 248-848-4000 Houston, TX Tel: 281-894-5983 Indianapolis Noblesville, IN Tel: 317-773-8323 Fax: 317-773-5453 Tel: 317-536-2380 Los Angeles Mission Viejo, CA Tel: 949-462-9523 Fax: 949-462-9608 Tel: 951-273-7800 Raleigh, NC Tel: 919-844-7510 New York, NY Tel: 631-435-6000 San Jose, CA Tel: 408-735-9110 Tel: 408-436-4270 Canada - Toronto Tel: 905-695-1980 Fax: 905-695-2078 Australia - Sydney Tel: 61-2-9868-6733 China - Beijing Tel: 86-10-8569-7000 China - Chengdu Tel: 86-28-8665-5511 China - Chongqing Tel: 86-23-8980-9588 China - Dongguan Tel: 86-769-8702-9880 China - Guangzhou Tel: 86-20-8755-8029 China - Hangzhou Tel: 86-571-8792-8115 China - Hong Kong SAR Tel: 852-2943-5100 China - Nanjing Tel: 86-25-8473-2460 China - Qingdao Tel: 86-532-8502-7355 China - Shanghai Tel: 86-21-3326-8000 China - Shenyang Tel: 86-24-2334-2829 China - Shenzhen Tel: 86-755-8864-2200 China - Suzhou Tel: 86-186-6233-1526 China - Wuhan Tel: 86-27-5980-5300 China - Xian Tel: 86-29-8833-7252 China - Xiamen Tel: 86-592-2388138 China - Zhuhai Tel: 86-756-3210040 India - Bangalore Tel: 91-80-3090-4444 India - New Delhi Tel: 91-11-4160-8631 India - Pune Tel: 91-20-4121-0141 Japan - Osaka Tel: 81-6-6152-7160 Japan - Tokyo Tel: 81-3-6880- 3770 Korea - Daegu Tel: 82-53-744-4301 Korea - Seoul Tel: 82-2-554-7200 Malaysia - Kuala Lumpur Tel: 60-3-7651-7906 Malaysia - Penang Tel: 60-4-227-8870 Philippines - Manila Tel: 63-2-634-9065 Singapore Tel: 65-6334-8870 Taiwan - Hsin Chu Tel: 886-3-577-8366 Taiwan - Kaohsiung Tel: 886-7-213-7830 Taiwan - Taipei Tel: 886-2-2508-8600 Thailand - Bangkok Tel: 66-2-694-1351 Vietnam - Ho Chi Minh Tel: 84-28-5448-2100 Austria - Wels Tel: 43-7242-2244-39 Fax: 43-7242-2244-393 Denmark - Copenhagen Tel: 45-4450-2828 Fax: 45-4485-2829 Finland - Espoo Tel: 358-9-4520-820 France - Paris Tel: 33-1-69-53-63-20 Fax: 33-1-69-30-90-79 Germany - Garching Tel: 49-8931-9700 Germany - Haan Tel: 49-2129-3766400 Germany - Heilbronn Tel: 49-7131-67-3636 Germany - Karlsruhe Tel: 49-721-625370 Germany - Munich Tel: 49-89-627-144-0 Fax: 49-89-627-144-44 Germany - Rosenheim Tel: 49-8031-354-560 Israel - Ra'anana Tel: 972-9-744-7705 Italy - Milan Tel: 39-0331-742611 Fax: 39-0331-466781 Italy - Padova Tel: 39-049-7625286 Netherlands - Drunen Tel: 31-416-690399 Fax: 31-416-690340 Norway - Trondheim Tel: 47-72884388 Poland - Warsaw Tel: 48-22-3325737 Romania - Bucharest Tel: 40-21-407-87-50 Spain - Madrid Tel: 34-91-708-08-90 Fax: 34-91-708-08-91 Sweden - Gothenberg Tel: 46-31-704-60-40 Sweden - Stockholm Tel: 46-8-5090-4654 UK - Wokingham Tel: 44-118-921-5800 Fax: 44-118-921-5820 (c) 2019 Microchip Technology Inc. Preliminary Datasheet DS40001996C-page 829