PIC18F46Q10-I/MP - MICROCHIP TECHNOLOGY

PIC18F26/45/46Q10

28/40-Pin, Low-Power, High-Performance Microcontrollers

Description

PIC18F26/45/46Q10 microcontrollers feature analog, core independent, and communication peripherals

for a wide range of general purpose and low-power applications. These 28/40/44-pin devices are

equipped with a 10-bit ADC with Computation (ADC2) automating Capacitive Voltage Divider (CVD)

techniques for advanced touch sensing, averaging, filtering, oversampling and performing automatic

threshold comparisons. They also offer a set of core independent peripherals such as Complementary

Waveform Generator (CWG), Windowed Watchdog Timer (WWDT), Cyclic Redundancy Check (CRC)/

Memory Scan, Zero-Cross Detect (ZCD), Configurable Logic Cell (CLC), and Peripheral Pin Select

(PPS), providing increased design flexibility and lower system cost.

Core Features

• C Compiler Optimized RISC Architecture

• Operating Speed:

– DC – 64 MHz clock input over the full VDD range

– 62.5 ns minimum instruction cycle

• Programmable 2-Level Interrupt Priority

• 31-Level Deep Hardware Stack

• Three 8-Bit Timers (TMR2/4/6) with Hardware Limit Timer (HLT)

• Four 16-Bit Timers (TMR0/1/3/5)

• Low-Current Power-on Reset (POR)

• Power-up Timer (PWRT)

• Brown-out Reset (BOR)

• Low-Power BOR (LPBOR) Option

• Windowed Watchdog Timer (WWDT):

– Watchdog Reset on too long or too short interval between watchdog clear events

– Variable prescaler selection

– Variable window size selection

– All sources configurable in hardware or software

Memory

• Up to 64K Bytes Program Flash Memory

• Up to 3615 Bytes Data SRAM Memory

• Up to 1024 Bytes Data EEPROM

• Programmable Code Protection

• Direct, Indirect and Relative Addressing modes

Operating Characteristics

• Operating Voltage Range:

– 1.8V to 5.5V

• Temperature Range:

– Industrial: -40°C to 85°C

– Extended: -40°C to 125°C

Power-Saving Operation Modes

• Doze: CPU and Peripherals Running at Different Cycle Rates (typically CPU is lower)

• Idle: CPU Halted While Peripherals Operate

• Sleep: Lowest Power Consumption

• Peripheral Module Disable (PMD):

– Ability to selectively disable hardware module to minimize active power consumption of unused

peripherals

• Extreme Low-Power mode (XLP)

– Sleep: 500 nA typical @ 1.8V

– Sleep and Watchdog Timer: 900 nA typical @ 1.8V

Digital Peripherals

• Configurable Logic Cell (CLC):

– Integrated combinational and sequential logic

• Complementary Waveform Generator (CWG):

– Rising and falling edge dead-band control

– Full-bridge, half-bridge, 1-channel drive

– Multiple signal sources

• Capture/Compare/PWM (CCP) modules:

– Two CCPs

– 16-bit resolution for Capture/Compare modes

– 10-bit resolution for PWM mode

• 10-Bit Pulse-Width Modulators (PWM):

– Two 10-bit PWMs

• Serial Communications:

– Two Enhanced USART (EUSART) with Auto-Baud Detect, Auto-wake-up on Start.

RS-232, RS-485, LIN compatible

– SPI

– I2C, SMBus and PMBus™ compatible

• Up to 35 I/O Pins and One Input Pin:

– Individually programmable pull-ups

– Slew rate control

PIC18F26/45/46Q10

– Interrupt-on-change on all pins

– Input level selection control

• Programmable CRC with Memory Scan:

– Reliable data/program memory monitoring for Fail-Safe operation (e.g., Class B)

– Calculate CRC over any portion of Flash or EEPROM

– High-speed or background operation

• Hardware Limit Timer (TMR2/4/6+HLT):

– Hardware monitoring and Fault detection

• Peripheral Pin Select (PPS):

– Enables pin mapping of digital I/O

• Data Signal Modulator (DSM)

Analog Peripherals

• 10-Bit Analog-to-Digital Converter with Computation (ADC2):

– 35 external channels

– Conversion available during Sleep

– Four internal analog channels

– Internal and external trigger options

– Automated math functions on input signals:

• Averaging, filter calculations, oversampling and threshold comparison

– 8-bit hardware acquisition timer

• Hardware Capacitive Voltage Divider (CVD) Support:

– 8-bit precharge timer

– Adjustable Sample-and-Hold capacitor array

– Guard ring digital output drive

• Zero-Cross Detect (ZCD):

– Detect when AC signal on pin crosses ground

• 5-Bit Digital-to-Analog Converter (DAC):

– Output available externally

– Programmable 5-bit voltage (% of VDD,[VREF+ - VREF-], FVR)

– Internal connections to comparators and ADC

• Two Comparators (CMP):

– Four external inputs

– External output via PPS

• Fixed Voltage Reference (FVR) Module:

– 1.024V, 2.048V and 4.096V output levels

– Two buffered outputs: One for DAC/CMP and one for ADC

Clocking Structure

• High-Precision Internal Oscillator Block (HFINTOSC):

– Selectable frequencies up to 64 MHz

– ±1% at calibration

PIC18F26/45/46Q10

• 32 kHz Low-Power Internal Oscillator (LFINTOSC)

• External 32 kHz Crystal Oscillator (SOSC)

• External High-frequency Oscillator Block:

– Three crystal/resonator modes

– Digital Clock Input mode

– 4x PLL with external sources

• Fail-Safe Clock Monitor:

– Allows for safe shutdown if external clock stops

• Oscillator Start-up Timer (OST)

Programming/Debug Features

• In-Circuit Serial Programming™ (ICSP™) via Two Pins

• In-Circuit Debug (ICD) with Three Breakpoints via Two Pins

• Debug Integrated On-Chip

PIC18F26/45/46Q10 Family Types

Table 1. Devices included in this data sheet

Device

Program Memory Flash

(bytes)

Data SRAM

(bytes)(2)

Data EEPROM

(bytes)

I/O Pins

16-bit Timers

Comparators

10-bit ADC2 with

Computation (ch)

5-bit DAC

Zero-Cross Detect

CCP/10-bit PWM

CWG

CLC

Low Voltage Detect (LVD)

8-bit TMR with HLT

Windowed Watchdog

Timer

CRC with Memory Scan

EUSART

I2C/SPI

PPS

Peripheral Module Disable

Temperature Indicator

Debug(1)

PIC18F26Q10 64k 3615 1024 25 4 2 24 1 1 2/2 1 8 1 3 Y Y 2 2 Y Y Y I

PIC18F45Q10 32k 2304 256 36 4 2 35 1 1 2/2 1 8 1 3 Y Y 2 2 Y Y Y I

PIC18F46Q10 64k 3615 1024 36 4 2 35 1 1 2/2 1 8 1 3 Y Y 2 2 Y Y Y I

Note:

1. Debugging Methods: (I) – Integrated on-chip.

2. SRAM includes 256 bytes of SECTOR space which is not included in the data size displayed by MPLAB X.

Table 2. Devices not included in this data sheet

Device

Program Memory Flash

(bytes)

Data SRAM

(bytes)(2)

Data EEPROM

(bytes)

I/O Pins

16-bit Timers

Comparators

10-bit ADC2 with

Computation (ch)

5-bit DAC

Zero-Cross Detect

CCP/10-bit PWM

CWG

CLC

Low Voltage Detect (LVD)

8-bit TMR with HLT

Windowed Watchdog

Timer

CRC with Memory Scan

EUSART

I2C/SPI

PPS

Peripheral Module Disable

Temperature Indicator

Debug(1)

PIC18F24Q10 16k 1280 256 25 4 2 24 1 1 2/2 1 0 1 3 Y Y 1 1 Y Y Y I

PIC18F25Q10 32k 2304 256 25 4 2 24 1 1 2/2 1 0 1 3 Y Y 1 1 Y Y Y I

PIC18F27Q10 128k 3615 1024 25 4 2 24 1 1 2/2 1 8 1 3 Y Y 2 2 Y Y Y I

PIC18F26/45/46Q10

...........continued

Device

Program Memory Flash

(bytes)

Data SRAM

(bytes)(2)

Data EEPROM

(bytes)

I/O Pins

16-bit Timers

Comparators

10-bit ADC2 with

Computation (ch)

5-bit DAC

Zero-Cross Detect

CCP/10-bit PWM

CWG

CLC

Low Voltage Detect (LVD)

8-bit TMR with HLT

Windowed Watchdog

Timer

CRC with Memory Scan

EUSART

I2C/SPI

PPS

Peripheral Module Disable

Temperature Indicator

Debug(1)

PIC18F47Q10 128k 3615 1024 36 4 2 35 1 1 2/2 1 8 1 3 Y Y 2 2 Y Y Y I

Note:

1. Debugging Methods: (I) – Integrated on-chip.

2. SRAM includes 256 bytes of SECTOR space which is not included in the data size displayed by MPLAB X.

Data Sheet Index:

1. DS40001945 Data Sheet, 28-Pin, 8-bit Flash Microcontrollers

2. DS40002043 Data Sheet, 28/40-Pin, 8-bit Flash Microcontrollers

Packages

Important: For other small form-factor package availability and marking information, visit

http://www.microchip.com/packaging or contact your local Microchip sales office.

Packages SPDIP

(SP)

SOIC

(SO)

SSOP

(SS)

QFN

(ML)

(6x6x0.9)

VQFN

(STX)

(4x4x1)

TQFP

(PT)

PDIP

(P)

QFN

(MP)

(5x5x0.9)

PIC18F26Q10 ● ● ● ● ●

PIC18F45Q10 ● ● ●

PIC18F46Q10 ● ● ●

Important: Pin details are subject to change.

PIC18F26/45/46Q10

Pin Diagrams

Figure 1. 28-pin SPDIP, SSOP, SOIC

Filename: 00-000028A.vsd

Title: 28-pin DIP

Last Edit: 10/3/2018

First Used: N/A

Notes: Generic 28-pin dual in-line diagram

Rev. 00-000028A

10/3/2018

MCLR/VPP/RE3 28

27

26

25

24

23

22

21

20

19

18

17

16

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

RA0

RA1

RA2

RA3

RA4

RA5

VSS

RA7

RA6

RC0

RC1

RC2

RC3 RC4

RC5

RC6

RC7

VSS

VDD

RB0

RB1

RB2

RB3

RB4

RB5

RB6/ICSPCLK

RB7/ICSPDAT

Figure 2. 28-pin QFN VQFN

Rev. 00-000028B

6/23/2017

28 27

RB3

RB2

RC7

RB5

RB4

VSS

RB1

RB0

VDD

RB6/ICSPCLK

RB7/ICSPDAT

RE3/MCLR/VPP

RA0

RA1

26 25 24 23 22

8 9 10 11 12 13 14

15

16

17

18

19

20

21

7

6

5

4

3

2

1

RC5

RC6

RC4

RC3

RC2

RC1

RC0

RA2

RA3

RA6

RA7

RA4

RA5

VSS

Note: It is recommended that the exposed bottom pad be connected to VSS, however it must not be the

only VSS connection to the device.

PIC18F26/45/46Q10

Figure 3. 40-pin PDIP

Filename: 00-000040A.vsd

Title: 40-pin DIP

Last Edit: 10/3/2018

First Used: N/A

Notes: Generic 40-pin dual in-line diagram

Rev. 00-000040A

10/3/2018

MCLR/VPP/RE3 40

39

38

37

36

35

34

33

32

31

30

29

28

27

14

13

12

11

10

9

8

7

6

5

4

3

2

1

RA0

RA1

RA2

RA3

RA4

RA5

VSS

RA7

RA6

RC0

RC1

RC2

RC3

RD4

RD5

RD6

RD7

VSS

VDD

RB0

RB1

RB2

RB3

RB4

RB5

RB6/ICSPCLK

RB7/ICSPDAT

15

16

17

18

19

20

26

25

24

23

22

21

RD0

RD1

VDD

RE0

RE1

RE2

RD2

RD3

RC4

RC5

RC6

RC7

Figure 4. 40-pin QFN

Filename: 00-000040B.vsd

Title: 40-pin QFN

Last Edit: 11/6/2017

First Used: N/A

Notes: Generic 40-pin QFN diagram

Rev. 00-000040B

11/6/2017

40 39

RC0

RA6

RE1

RE0

RA5

RA4

RC1

RC2

RC3

RD1

RD0

RE2

RA7

VSS

VDD

RD2

RD3

RC4

RC5

RC6

38 37 36 35 34 33 32 31

11 12 13 14 15 16 17 18 19 20

21

22

23

24

25

26

27

28

29

30

10

9

8

7

6

5

4

3

2

1

RA3

RA2

RA1

VPP/MCLR/RE3

RA0

ICSPDAT/RB7

ICSPCLK/RB6

RB5

RB4

RB3

RC7

RD4

VDD

RB0

RB1

RB2

VSS

RD5

RD6

RD7

Note: It is recommended that the exposed bottom pad be connected to VSS, however it must not be the

only VSS connection to the device.

PIC18F26/45/46Q10

Figure 5. 44-pin TQFP

Filename: 00-000044A.vsd

Title: 44-pin TQFP

Last Edit: 11/6/2017

First Used: N/A

Notes: Generic 44-pin TQFP diagram

Rev. 00-000044A

11/6/2017

40 39

RA6

RA7

RE1

RE0

RA5

RA4

RC1

RC2

RC3

RD1

RD0

RE2

NC

VSS

VDD

RD2

RD3

RC4

RC5

RC6

38 37 36 35 34

33

32

31

12 13 14 15 16 17 18 19 20 21 22

23

24

25

26

27

28

29

30

10

9

8

7

6

5

4

3

2

1

RA3

RA2

RA1

VPP/MCLR/RE3

RA0

ICSPDAT/RB7

ICSPCLK/RB6

RB5

RB4

RB3

RC7

RD4

VDD

RB0

RB1

RB2

VSS

RD5

RD6

RD7

11

44 43 42 41

NC

RC0

Pin Allocation Tables

Table 3. 28-Pin Allocation Table

I/O(2)

28-Pin

SPDIP,

SOIC,

SSOP

28-Pin

(V)QFN A/D Reference Comparator Timers CCP CWG ZCD Interrupt EUSART DSM MSSP Pull-

up Basic

RA0 2 27 ANA0 — C1IN0-

C2IN0-

— — — — IOCA0 — — — Y —

RA1 3 28 ANA1 — C1IN1-

C2IN1-

— — — — IOCA1 — — — Y —

RA2 4 1 ANA2 DAC1OUT1

VREF- (DAC)

VREF- (ADC)

C1IN0+

C2IN0+

— — — — IOCA2 — — — Y —

RA3 5 2 ANA3 VREF+ (DAC)

VREF+ (ADC)

C1IN1+ — — — — IOCA3 — MDCARL(1) — Y —

RA4 6 3 ANA4 — — T0CKI(1) — — — IOCA4 — MDCARH(1) — Y —

RA5 7 4 ANA5 — — — — — — IOCA5 — MDSRC(1) SS1(1) Y —

RA6 10 7 ANA6 — — — — — — IOCA6 — — — Y CLKOUT

OSC2

RA7 9 6 ANA7 — — — — — — IOCA7 — — — Y OSC1

CLKIN

RB0 21 18 ANB0 — C2IN1+ — — CWG1(1) ZCDIN IOCB0

INT0(1)

— — SS2(1) Y —

RB1 22 19 ANB1 — C1IN3-

C2IN3-

— — — — IOCB1

INT1(1)

— — SCK2(1)

SCL2(3,4)

Y —

PIC18F26/45/46Q10

...........continued

I/O(2)

28-Pin

SPDIP,

SOIC,

SSOP

28-Pin

(V)QFN A/D Reference Comparator Timers CCP CWG ZCD Interrupt EUSART DSM MSSP Pull-

up Basic

RB2 23 20 ANB2 — — — — — — IOCB2

INT2(1)

— — SDI2(1)

SDA2(3,4)

Y —

RB3 24 21 ANB3 — C1IN2-

C2IN2-

— — — — IOCB3 — — — Y —

RB4 25 22 ANB4 — — T5G(1) — — — IOCB4 — — — Y —

RB5 26 23 ANB5 — — T1G(1) — — — IOCB5 — — — Y —

RB6 27 24 ANB6 — — — — — — IOCB6 — — — Y ICSPCLK

RB7 28 25 ANB7 DAC1OUT2 — T6IN(1) — — — IOCB7 — — — Y ICSPDAT

RC0 11 8 ANC0 — — T1CKI(1)

T3CKI(1)

T3G(1)

— — — IOCC0 — — — Y SOSCO

RC1 12 9 ANC1 — — — CCP2(1) — — IOCC1 — — — Y SOSCIN

SOSCI

RC2 13 10 ANC2 — — T5CKI(1) CCP1(1) — — IOCC2 — — — Y —

RC3 14 11 ANC3 — — T2IN(1) — — — IOCC3 — — SCK1(1)

SCL1(3,4)

Y —

RC4 15 12 ANC4 — — — — — — IOCC4 — — SDI1(1)

SDA1(3,4)

Y —

RC5 16 13 ANC5 — — T4IN(1) — — — IOCC5 — — — Y —

RC6 17 14 ANC6 — — — — — — IOCC6 CK1(1,3) — — Y —

RC7 18 15 ANC7 — — — — — — IOCC7 RX1/

DT1(1,3)

— — Y —

RE3 1 26 — — — — — — — IOCE3 — — — Y Vpp/MCLR

VSS 19 16 — — — — — — — — — — — — VSS

VDD(5) 20 17 — — — — — — — — — — — — VDD

VSS 8 5 — — — — — — — — — — — — VSS

OUT(2) — — ADGRDA

ADGRDB

— C1OUT

C2OUT

TMR0 CCP1

CCP2

PWM3

PWM4

CWG1A

CWG1B

CWG1C

CWG1D

— — TX1/

CK1(3)

DT1(3)

DSM SDO1

SCK1

— —

Note:

1. This is a PPS remappable input signal. The input function may be moved from the default location shown to one of several other PORTx pins. Refer to the

peripheral input selection table for details on which port pins may be used for this signal.

2. All output signals shown in this row are PPS remappable. These signals may be mapped to output onto one of several PORTx pin options as described in the

peripheral output selection table.

3. This is a bidirectional signal. For normal module operation, the firmware should map this signal to the same pin in both the PPS input and PPS output registers.

4. These pins are configured for I2C logic levels; The SCLx/SDAx signals may be assigned to any of these pins. PPS assignments to the other pins (e.g., RB1) will

operate, but input logic levels will be standard TTL/ST as selected by the INLVL register, instead of the I2C specific or SMBus input buffer thresholds.

5. A 0.1 uF bypass capacitor to VSS is required on the VDD pin.

Table 4. 40/44-Pin Allocation Table

I/O(2) 40-Pin

PDIP

40-

QFN

44-Pin

TQFP A/D Reference Comparator Timers CCP CWG ZCD Interrupt EUSART DSM MSSP Pull-

up Basic

RA0 2 17 19 ANA0 — C1INO-

C2IN0-

— — — — IOCA0 — — — Y —

RA1 3 18 20 ANA1 — C1IN1-

C2IN1-

— — — — IOCA1 — — — Y —

PIC18F26/45/46Q10

...........continued

I/O(2) 40-Pin

PDIP

40-

QFN

44-Pin

TQFP A/D Reference Comparator Timers CCP CWG ZCD Interrupt EUSART DSM MSSP Pull-

up Basic

RA2 4 19 21 ANA2 DAC1OUT1

VREF-

(DAC5)

VREF-

(ADC)

C1IN0+

C2IN0+

— — — — IOCA2 — — — Y —

RA3 5 20 22 ANA3 VREF+

(DAC5)

VREF+

(ADC)

C1IN1+ — — — — IOCA3 — MDCARL(1) — Y —

RA4 6 21 23 ANA4 — — T0CKI(1) — — — IOCA4 — MDCARH(1) — Y —

RA5 7 22 24 ANA5 — — — — — — IOCA5 — MDSRC(1) SS1(1) Y —

RA6 14 29 31 ANA6 — — — — — — IOCA6 — — — Y CLKOUT

OSC2

RA7 13 28 30 ANA7 — — — — — — IOCA7 — — — Y OSC1

CLKIN

RB0 33 8 8 ANB0 — C2IN1+ — — CWG1(1) ZCDIN IOCB0

INT0(1)

— — SS2(1) Y —

RB1 34 9 9 ANB1 — C1IN3-

C2IN3-

— — — — IOCB1

INT1(1)

— — SCK2(1)

SCL2(3,4)

Y —

RB2 35 10 10 ANB2 — — — — — — IOCB2

INT2(1)

— — SDI2(1)

SDA2(3,4)

Y —

RB3 36 11 11 ANB3 — C1IN2-

C2IN2-

— — — — IOCB3 — — — Y —

RB4 37 12 14 ANB4 — — T5G(1) — — — IOCB4 — — — Y —

RB5 38 13 15 ANB5 — — T1G(1) — — — IOCB5 — — — Y —

RB6 39 14 16 ANB6 — — — — — — IOCB6 CK2(1,3) — — Y ICSPCLK

RB7 40 15 17 ANB7 DAC1OUT2 — T6IN(1) — — — IOCB7 RX2/

DT2(1,3)

— — Y ICSPDAT

RC0 15 30 32 ANC0 — — T1CKI(1)

T3CKI(1)

T3G(1)

— — — IOCC0 — — — Y SOSCO

RC1 16 31 35 ANC1 — — — CCP2(1) — — IOCC1 — — — Y SOSCIN

SOSCI

RC2 17 32 36 ANC2 — — T5CKI(1) CCP1(1) — — IOCC2 — — — Y —

RC3 18 33 37 ANC3 — — T2IN(1) — — — IOCC3 — — SCK1(1)

SCL1(3,4)

Y —

RC4 23 38 42 ANC4 — — — — — — IOCC4 — — SDI1(1)

SDA1(3,4)

— —

RC5 24 39 43 ANC5 — — T4IN(1) — — — IOCC5 — — — Y —

RC6 25 40 44 ANC6 — — — — — — IOCC6 CK1(1,3) — — Y —

RC7 26 1 1 ANC7 — — — — — — IOCC7 RX1/

DT1(1,3)

— — Y —

RD0 19 34 38 AND0 — — — — — — — — — — Y —

RD1 20 35 39 AND1 — — — — — — — — — — Y —

PIC18F26/45/46Q10

...........continued

I/O(2) 40-Pin

PDIP

40-

QFN

44-Pin

TQFP A/D Reference Comparator Timers CCP CWG ZCD Interrupt EUSART DSM MSSP Pull-

up Basic

RD2 21 36 40 AND2 — — — — — — — — — — Y —

RD3 22 37 41 AND3 — — — — — — — — — — Y —

RD4 27 2 2 AND4 — — — — — — — — — — Y —

RD5 28 3 3 AND5 — — — — — — — — — — Y —

RD6 29 4 4 AND6 — — — — — — — — — — Y —

RD7 30 5 5 AND7 — — — — — — — — — — Y —

RE0 8 23 25 ANE0 — — — — — — — — — — Y —

RE1 9 24 26 ANE1 — — — — — — — — — — Y —

RE2 10 25 27 ANE2 — — — — — — — — — — Y —

RE3 1 16 18 — — — — — — — IOCE3 — — — Y Vpp/MCLR

VSS 12 6 6 — — — — — — — — — — — — VSS

VDD(5) 11 7 7 — — — — — — — — — — — — VDD

VDD(5) 32 26 28 — — — — — — — — — — — — VSS

VSS 31 27 29 — — — — — — — — — — — — VSS

OUT(2) — — — ADGRDA

ADGRDB

— C1OUT

C2OUT

TMR0 CCP1

CCP2

PWM3

PWM4

CWG1A

CWG1B

CWG1C

CWG1D

— — TX1/

CK1(3)

DT1(3)

TX2/

CK2(3)

DT2(3)

DSM SDO1

SCK1

SDO2

SCK2

— —

Note:

1. This is a PPS remappable input signal. The input function may be moved from the default location shown to one of several other PORTx pins. Refer to the

peripheral input selection table for details on which port pins may be used for this signal.

2. All output signals shown in this row are PPS remappable. These signals may be mapped to output onto one of several PORTx pin options as described in the

peripheral output selection table.

3. This is a bidirectional signal. For normal module operation, the firmware should map this signal to the same pin in both the PPS input and PPS output registers.

4. These pins are configured for I2C logic levels; The SCLx/SDAx signals may be assigned to any of these pins. PPS assignments to the other pins (e.g., RB1) will

operate, but input logic levels will be standard TTL/ST as selected by the INLVL register, instead of the I2C specific or SMBus input buffer thresholds.

5. A 0.1 uF bypass capacitor to VSS is required on all VDD pins.

PIC18F26/45/46Q10

Table of Contents

Description.......................................................................................................................1

Core Features..................................................................................................................1

Memory............................................................................................................................1

Operating Characteristics................................................................................................2

Power-Saving Operation Modes......................................................................................2

Digital Peripherals........................................................................................................... 2

Analog Peripherals.......................................................................................................... 3

Clocking Structure........................................................................................................... 3

Programming/Debug Features........................................................................................ 4

PIC18F26/45/46Q10 Family Types................................................................................. 4

Packages.........................................................................................................................5

Pin Diagrams...................................................................................................................6

Pin Allocation Tables....................................................................................................... 8

1. Device Overview......................................................................................................15

2. Guidelines for Getting Started with PIC18F26/45/46Q10 Microcontrollers............. 23

3. Device Configuration............................................................................................... 28

4. Oscillator Module (with Fail-Safe Clock Monitor).....................................................44

5. Reference Clock Output Module............................................................................. 66

6. Power-Saving Operation Modes..............................................................................72

7. (PMD) Peripheral Module Disable........................................................................... 81

8. Resets..................................................................................................................... 90

9. (WWDT) Windowed Watchdog Timer....................................................................104

10. Memory Organization............................................................................................ 116

11. (NVM) Nonvolatile Memory Control.......................................................................151

PIC18F26/45/46Q10

12. 8x8 Hardware Multiplier.........................................................................................180

13. (CRC) Cyclic Redundancy Check Module with Memory Scanner.........................185

14. Interrupts............................................................................................................... 206

15. I/O Ports................................................................................................................ 237

16. Interrupt-on-Change.............................................................................................. 285

17. (PPS) Peripheral Pin Select Module......................................................................301

18. Timer0 Module.......................................................................................................312

19. Timer1 Module with Gate Control..........................................................................321

20. Timer2 Module.......................................................................................................341

21. Capture/Compare/PWM Module........................................................................... 368

22. (PWM) Pulse-Width Modulation............................................................................ 384

23. (ZCD) Zero-Cross Detection Module.....................................................................393

24. (CWG) Complementary Waveform Generator Module..........................................401

25. (CLC) Configurable Logic Cell...............................................................................431

26. (DSM) Data Signal Modulator Module...................................................................454

27. (MSSP) Master Synchronous Serial Port Module................................................. 469

28. (EUSART) Enhanced Universal Synchronous Asynchronous Receiver Transmitter

...............................................................................................................................533

29. (FVR) Fixed Voltage Reference.............................................................................568

30. Temperature Indicator Module...............................................................................573

31. (DAC) 5-Bit Digital-to-Analog Converter Module...................................................576

32. (ADC2) Analog-to-Digital Converter with Computation Module............................. 582

33. (CMP) Comparator Module................................................................................... 630

34. (HLVD) High/Low-Voltage Detect.......................................................................... 643

35. Register Summary.................................................................................................651

36. In-Circuit Serial Programming™ (ICSP™) .............................................................662

37. Instruction Set Summary....................................................................................... 665

PIC18F26/45/46Q10

38. Development Support............................................................................................764

39. Electrical Specifications.........................................................................................769

40. DC and AC Characteristics Graphs and Tables.................................................... 801

41. Packaging Information...........................................................................................802

42. Revision History.....................................................................................................824

The Microchip Web Site.............................................................................................. 825

Customer Change Notification Service........................................................................825

Customer Support....................................................................................................... 825

Product Identification System......................................................................................826

Microchip Devices Code Protection Feature............................................................... 826

Legal Notice.................................................................................................................827

Trademarks................................................................................................................. 827

Quality Management System Certified by DNV...........................................................828

Worldwide Sales and Service......................................................................................829

PIC18F26/45/46Q10

1. Device Overview

This document contains device specific information for the following devices:

• PIC18F26Q10

• PIC18F45Q10

• PIC18F46Q10

This family offers the advantages of all PIC18 microcontrollers – namely, high computational performance

at an economical price – with the addition of high-endurance Program Flash Memory. In addition to these

features, the PIC18F26/45/46Q10 family introduces design enhancements that make these

microcontrollers a logical choice for many high-performance, power sensitive applications.

1.1 New Core Features

1.1.1 Low-Power Technology

All of the devices in the PIC18F26/45/46Q10 family incorporate a range of features that can significantly

reduce power consumption during operation. Key items include:

• Alternate Run modes: By clocking the microcontroller from the secondary oscillator or the internal

oscillator block, power consumption during code execution can be reduced by as much as 90%.

• Multiple Idle modes: The controller can also run with its CPU core disabled but the peripherals are

still active. In these states, power consumption can be reduced even further, to as little as 4% of

normal operation requirements.

• On-the-fly mode switching: The Power-Managed modes are invoked by user code during operation,

allowing the user to incorporate power-saving ideas into their application’s software design.

• Peripheral Module Disable: Modules that are not being used in the code can be selectively disabled

using the PMD module. This further reduces the power consumption.

1.1.2 Multiple Oscillator Options and Features

All of the devices in the PIC18F26/45/46Q10family offer several different oscillator options. The

PIC18F26/45/46Q10 family can be clocked from several different sources:

• HFINTOSC

– 1-64 MHz precision digitally controlled internal oscillator

• LFINTOSC

– 31 kHz internal oscillator

• EXTOSC

– External clock (EC)

– Low-power oscillator (LP)

– Medium power oscillator (XT)

– High power oscillator (HS)

• SOSC

– Secondary oscillator circuit optimized for 31 kHz clock crystals

• A Phase Lock Loop (PLL) frequency multiplier (4x) is available to the External Oscillator modes

enabling clock speeds of up to 64 MHz

PIC18F26/45/46Q10

Device Overview

• Fail-Safe Clock Monitor: This option constantly monitors the main clock source against a reference

signal provided by the LFINTOSC. If a clock failure occurs, the controller is switched to the internal

oscillator block, allowing for continued operation or a safe application shutdown.

1.2 Other Special Features

• Memory Endurance: The Flash cells for both program memory and data EEPROM are rated to last

for many thousands of erase/write cycles – up to 10K for program memory and 100K for EEPROM.

Data retention without refresh is conservatively estimated to be greater than 40 years.

• Self-programmability: These devices can write to their own program memory spaces under internal

software control. By using a boot loader routine located in the protected Boot Block at the top of

program memory, it becomes possible to create an application that can update itself in the field.

• Extended Instruction Set: The PIC18F26/45/46Q10 family includes an optional extension to the

PIC18 instruction set, which adds eight new instructions and an Indexed Addressing mode. This

extension, enabled as a device configuration option, has been specifically designed to optimize re-

entrant application code originally developed in high-level languages, such as C.

• Enhanced Peripheral Pin Select: The Peripheral Pin Select (PPS) module connects peripheral inputs

and outputs to the device I/O pins. Only digital signals are included in the selections. All analog

inputs and outputs remain fixed to their assigned pins.

• Enhanced Addressable EUSART: This serial communication module is capable of standard

RS-232 operation and provides support for the LIN bus protocol. Other enhancements include

automatic baud rate detection and a 16-bit Baud Rate Generator for improved resolution. When the

microcontroller is using the internal oscillator block, the EUSART provides stable operation for

applications that talk to the outside world without using an external crystal (or its accompanying

power requirement).

• 10-bit A/D Converter with Computation: This module incorporates programmable acquisition time,

allowing for a channel to be selected and a conversion to be initiated without waiting for a sampling

period and thus, reduce code overhead. It has a new module called ADC2 with computation features,

which provides a digital filter and threshold interrupt functions.

• Windowed Watchdog Timer (WWDT):

– Timer monitoring of overflow and underflow events

– Variable prescaler selection

– Variable window size selection

– All sources configurable in hardware or software

1.3 Details on Individual Family Members

Devices in the PIC18F26/45/46Q10 family are available in 28-pin and 40/44-pin packages. The block

diagram for this device is shown in Figure 1-1.

The devices have the following differences:

1. Program Flash Memory

2. Data Memory SRAM

3. Data Memory EEPROM

4. A/D channels

5. I/O ports

6. Enhanced USART

PIC18F26/45/46Q10

Device Overview

7. Input Voltage Range/Power Consumption

All other features for devices in this family are identical. These are summarized in the following Device

Features table.

The pinouts for all devices are listed in the pin summary tables.

Table 1-1. Device Features

Features PIC18F26Q10 PIC18F45Q10 PIC18F46Q10

Program Memory (Bytes) 65536 32768 65536

Program Memory

(Instructions) 32768 16384 32768

Data Memory (Bytes) 3615 2048 3615

Data EEPROM Memory

(Bytes) 1024 256 1024

I/O Ports A,B,C,E(1) A,B,C,D,E A,B,C,D,E

Capture/Compare/PWM

Modules (CCP) 2 2 2

10-Bit Pulse-Width

Modulator (PWM) 2 2 2

10-Bit Analog-to-Digital

Module (ADC2) with

Computation Accelerator

4 internal

24 external

4 internal

35 external

4 internal

35 external

Packages

28-pin SPDIP

28-pin SOIC

28-pin SSOP

28-pin VQFN

28-pin QFN

40-pin PDIP

40-pin QFN

44-pin TQFP

40-pin PDIP

40-pin QFN

44-pin TQFP

Timers (16-/8-bit) 4/3 4/3 4/3

Serial Communications 2 MSSP,

2 EUSART

2 MSSP,

2 EUSART

2 MSSP,

2 EUSART

Enhanced Complementary

Waveform Generator

(ECWG)

1 1 1

Zero-Cross Detect (ZCD) 1 1 1

Data Signal Modulator

(DSM) 1 1 1

Configurable Logic Cell

(CLC) 8 8 8

Peripheral Pin Select (PPS) Yes Yes Yes

PIC18F26/45/46Q10

Device Overview

...........continued

Features PIC18F26Q10 PIC18F45Q10 PIC18F46Q10

Peripheral Module Disable

(PMD) Yes Yes Yes

16-bit CRC with NVMSCAN Yes Yes Yes

Programmable High/Low-

Voltage Detect (HLVD) Yes Yes Yes

Programmable Brown-out

Reset (BOR) Yes Yes Yes

Resets (and Delays)

POR, BOR,

RESET Instruction,

Stack Overflow,

Stack Underflow

(PWRT, OST),

MCLR, WDT

POR, BOR,

RESET Instruction,

Stack Overflow,

Stack Underflow

(PWRT, OST),

MCLR, WDT

POR, BOR,

RESET Instruction,

Stack Overflow,

Stack Underflow

(PWRT, OST),

MCLR, WDT

Instruction Set

75 Instructions;

83 with Extended

Instruction Set enabled

75 Instructions;

83 with Extended

Instruction Set enabled

75 Instructions;

83 with Extended

Instruction Set

enabled

Operating Frequency DC – 64 MHz DC – 64 MHz DC – 64 MHz

Note 1: PORTE contains the single RE3 read-only bit.

PIC18F26/45/46Q10

Device Overview

Figure 1-1. PIC18F26/45/46Q10 Family Block Diagram

Instruction

Decode and

Control

Data Latch

Data Memory

Address Latch

Data Address<12>

12

Access

BSR FSR0

FSR1

FSR2

inc/dec

logic

Address

4 12 4

PCH PCL

PCLATH

8

31-Level Stack

Program Counter

PRODLPRODH

8x8 Multiply

8

BITOP

8

ALU<8>

20

8

Table Pointer<21>

inc/dec logic

21

8

Data Bus<8>

Table Latch

8

IR

12

3

ROM Latch

PCLATU

PCU

Note 1: RE3 is only available when MCLR functionality is disabled.

2: OSC1/CLKIN and OSC2/CLKOUT are only available in select oscillator modes.

EUSART1

Comparators MSSP1

10-bit

ADC

Timer2

Timer1

ZCD

Timer0

PWM3

HLVD

CCP1

BOR NVM

Controller

W

Instruction Bus <16>

STKPTR Bank

8

State machine

control signals

Decode

8

Power-up

Timer

Oscillator

Start-up Timer

Power-on

Reset

Watchdog

Timer

OSC1(2)

OSC2(2)

Brown-out

Reset

Internal

Oscillator

Fail-Safe

Clock Monitor

Precision

Reference

Band Gap

MCLR(1)

Block

LFINTOSC

Oscillator

64 MHz

Oscillator

Single-Supply

Programming

In-Circuit

Debugger

SOSCO

SOSCI

FVR

DAC

Address Latch

Program Memory

(8/16/32/64 Kbytes)

Data Latch

PORTA

RA<7:0>

PORTB

RB

<7:0>

PORTC

RC<7:0>

PORTD

RD

<7:0>

Timer4

Timer6

Timer3

Timer5

ECWG

PWM4

CCP2

C1/C2

PORTE

RE<2:0>

RE3(1)

DAC

DSM PMD

CRC-Scan

MSSP2 EUSART2

3: PORTD and PORTE<2:0> not implemented on 28-pin devices.

Rev. 30-000131B

6/14/2017

(3)

FVR

PIC18F26/45/46Q10

Device Overview

1.4 Register and Bit Naming Conventions

1.4.1 Register Names

When there are multiple instances of the same peripheral in a device, the Peripheral Control registers will

be depicted as the concatenation of a peripheral identifier, peripheral instance, and control identifier. The

control registers section will show just one instance of all the register names with an ‘x’ in the place of the

peripheral instance number. This naming convention may also be applied to peripherals when there is

only one instance of that peripheral in the device to maintain compatibility with other devices in the family

that contain more than one.

1.4.2 Bit Names

There are two variants for bit names:

• Short name: Bit function abbreviation

• Long name: Peripheral abbreviation + short name

1.4.2.1 Short Bit Names

Short bit names are an abbreviation for the bit function. For example, some peripherals are enabled with

the EN bit. The bit names shown in the registers are the short name variant.

Short bit names are useful when accessing bits in C programs. The general format for accessing bits by

the short name is RegisterNamebits.ShortName. For example, the enable bit, EN, in the CM1CON0

register can be set in C programs with the instruction CM1CON0bits.EN = 1.

Short names are generally not useful in assembly programs because the same name may be used by

different peripherals in different bit positions. When this occurs, during the include file generation, all

instances of that short bit name are appended with an underscore plus the name of the register in which

the bit resides to avoid naming contentions.

1.4.2.2 Long Bit Names

Long bit names are constructed by adding a peripheral abbreviation prefix to the short name. The prefix is

unique to the peripheral, thereby making every long bit name unique. The long bit name for the COG1

enable bit is the COG1 prefix, G1, appended with the enable bit short name, EN, resulting in the unique

bit name G1EN.

Important: The COG1 peripheral is used as an example. Not all devices have the COG

peripheral.

Long bit names are useful in both C and assembly programs. For example, in C the COG1CON0 enable

bit can be set with the G1EN = 1 instruction. In assembly, this bit can be set with the BSF

COG1CON0,G1EN instruction.

1.4.2.3 Bit Fields

Bit fields are two or more adjacent bits in the same register. Bit fields adhere only to the short bit naming

convention. For example, the three Least Significant bits of the COG1CON0 register contain the Mode

Control bits. The short name for this field is MD. There is no long bit name variant. Bit field access is only

possible in C programs. The following example demonstrates a C program instruction for setting the

COG1 to the Push-Pull mode:

COG1CON0bits.MD = 0x5;

PIC18F26/45/46Q10

Device Overview

Individual bits in a bit field can also be accessed with long and short bit names. Each bit is the field name

appended with the number of the bit position within the field. For example, the Most Significant mode bit

has the short bit name MD2 and the long bit name is G1MD2. The following two examples demonstrate

assembly program sequences for setting the COG1 to Push-Pull mode:

Example 1:

MOVLW ~(1<<G1MD1)

ANDWF COG1CON0,F

MOVLW 1<<G1MD2 | 1<<G1MD0

IORWF COG1CON0,F

Example 2:

BSF COG1CON0,G1MD2

BCF COG1CON0,G1MD1

BSF COG1CON0,G1MD0

1.4.3 Register and Bit Naming Exceptions

1.4.3.1 Status, Interrupt, and Mirror Bits

Status, interrupt enables, Interrupt flags, and Mirror bits are contained in registers that span more than

one peripheral. In these cases, the bit name shown is unique so there is no prefix or short name variant.

1.4.3.2 Legacy Peripherals

There are some peripherals that do not strictly adhere to these naming conventions. Peripherals that

have existed for many years and are present in almost every device are the exceptions. These

exceptions were necessary to limit the adverse impact of the new conventions on legacy code.

Peripherals that do adhere to the new convention will include a table in the registers section indicating the

long name prefix for each peripheral instance. Peripherals that fall into the exception category will not

have this table. These peripherals include, but are not limited to the following:

• EUSART

• MSSP

1.5 Register Legend

The table below describes the conventions for bit types and bit Reset values used in the current data

sheet.

Table 1-2. Register Legend

Value Description

RO Read-only bit

W Writable bit

U Unimplemented bit, read as ‘0’

P Programmable bit

‘1’ Bit is set

‘0’ Bit is cleared

xBit is unknown

PIC18F26/45/46Q10

Device Overview

...........continued

Value Description

uBit is unchanged

-n/n Value at POR and BOR/Value at all other Resets

qReset Value is determined by hardware

fReset Value is determined by fuse setting

gReset Value at POR for PPS re-mappable signals

PIC18F26/45/46Q10

Device Overview

2. Guidelines for Getting Started with PIC18F26/45/46Q10

Microcontrollers

2.1 Basic Connection Requirements

Getting started with the PIC18F26/45/46Q10 family of 8-bit microcontrollers requires attention to a

minimal set of device pin connections before proceeding with development.

The following pins must always be connected:

• All VDD and VSS pins (see 2.2 Power Supply Pins)

• All VDD pins must have a 0.1 uF bypass capacitor to VSS.

These pins must also be connected if they are being used in the end application:

• ICSPCLK/ICSPDAT pins used for In-Circuit Serial Programming™ (ICSP™) and debugging purposes

(see 2.4 In-Circuit Serial Programming™ (ICSP™) Pins)

• OSCI and OSCO pins when an external oscillator source is used (see 2.5 External Oscillator Pins)

• MCLR pin (see 2.3 Master Clear (MCLR) Pin) when external master clear configuration is selected.

Additionally, the following pins may be required:

• VREF+/VREF- pins are used when external voltage reference for analog modules is implemented

The minimum mandatory connections are shown in the figure below.

Figure 2-1. Recommended Minimum Connections

Filename: 10-000249C.vsd

Title: Getting Started on PIC18

Last Edit: 5/1/2018

First Used: PIC18FxxQ10

Note: Generic figure showing the MCLR, VDD and VSS pin connections.

C1

R1

Rev. 10-000249C

5/1/2018

VDD

PIC MCU

R2

MCLR

C2

VDD

Vss

Key:

C1: 0.1 F, 20V ceramic (recommended)

R1: 10 kΩ (recommended)

R2: 100Ω to 470Ω (recommended)

C2: 0.1 F, 20V ceramic (required)

2.2 Power Supply Pins

2.2.1 Decoupling Capacitors

The use of decoupling capacitors on every pair of power supply pins (VDD and VSS) is required.

Consider the following criteria when using decoupling capacitors:

PIC18F26/45/46Q10

Guidelines for Getting Started with PIC18F26/45/46...

• Value and type of capacitor: A 0.1 μF (100 nF), 10-20V capacitor is required. The capacitor should be

a low-ESR device, with a resonance frequency in the range of 200 MHz and higher. Ceramic

capacitors are recommended.

• Placement on the printed circuit board: The decoupling capacitors should be placed as close to the

pins as possible. It is recommended to place the capacitors on the same side of the board as the

device. If space is constricted, the capacitor can be placed on another layer on the PCB using a via;

however, ensure that the trace length from the pin to the capacitor is no greater than 0.25 inch (6

mm).

• Handling high-frequency noise: If the board is experiencing high-frequency noise (upward of tens of

MHz), add a second ceramic type capacitor in parallel to the above described decoupling capacitor.

The value of the second capacitor can be in the range of 0.01 μF to 0.001 μF. Place this second

capacitor next to each primary decoupling capacitor. In high-speed circuit designs, consider

implementing a decade pair of capacitances as close to the power and ground pins as possible (e.g.,

0.1 μF in parallel with 0.001 μF).

• Maximizing performance: On the board layout from the power supply circuit, run the power and return

traces to the decoupling capacitors first, and then to the device pins. This ensures that the

decoupling capacitors are first in the power chain. Equally important is to keep the trace length

between the capacitor and the power pins to a minimum, thereby reducing PCB trace inductance.

2.2.2 Tank Capacitors

On boards with power traces running longer than six inches in length, it is suggested to use a tank

capacitor for integrated circuits, including microcontrollers, to supply a local power source. The value of

the tank capacitor should be determined based on the trace resistance that connects the power supply

source to the device, and the maximum current drawn by the device in the application. In other words,

select the tank capacitor that meets the acceptable voltage sag at the device. Typical values range from

4.7 μF to 47 μF.

2.3 Master Clear (MCLR) Pin

The MCLR pin provides two specific device functions: Device Reset, and Device Programming and

Debugging. If programming and debugging are not required in the end application, a direct connection to

VDD may be all that is required. The addition of other components, to help increase the application’s

resistance to spurious Resets from voltage sags, may be beneficial. A typical configuration is shown in

Figure 2-1. Other circuit designs may be implemented, depending on the application’s requirements.

During programming and debugging, the resistance and capacitance that can be added to the pin must

be considered. Device programmers and debuggers drive the MCLR pin. Consequently, specific voltage

levels (VIH and VIL) and fast signal transitions must not be adversely affected. Therefore, specific values

of R1 and C1 will need to be adjusted based on the application and PCB requirements. For example, it is

recommended that the capacitor, C1, be isolated from the MCLR pin during programming and debugging

operations by using a jumper as shown in the following figure. The jumper is replaced for normal run-time

operations.

Any components associated with the MCLR pin should be placed within 0.25 inch (6 mm) of the pin.

PIC18F26/45/46Q10

Guidelines for Getting Started with PIC18F26/45/46...

Figure 2-2. Example of MCLR Pin Connections

Note 1: R1 10 k is recommendedPA suggested

starting value is 10 k P Ensure that the

MCLR pin VIH and VIL specifications are metP

2: R2 470 will limit any current flowing into

MCLR from the external capacitorOC1Oin the

event of MCLR pin breakdownO due to

Electrostatic Discharge DESD( or Electrical

Overstress DEOS(PEnsure that the MCLR pin

VIH and VIL specifications are metP

C1

R2

R1

VDD

JP

MCLR

Rev. 30-000058A

6/23/2017

Note:

1. R1 ≤ 10 kΩ is recommended. A suggested starting value is 10 kΩ. Ensure that the MCLR pin VIH

and VIL specifications are met.

2. R2 ≤ 470Ω will limit any current flowing into MCLR from the extended capacitor, C1, in the event of

MCLR pin breakdown, due to Electrostatic Discharge (ESD) or Electrical Overstress (EOS). Ensure

that the MCLR pin VIH and VIL specifications are met.

2.4 In-Circuit Serial Programming™ (ICSP™) Pins

The ICSPCLK and ICSPDAT pins are used for ICSP and debugging purposes. It is recommended to keep

the trace length between the ICSP connector and the ICSP pins on the device as short as possible. If the

ICSP connector is expected to experience an ESD event, a series resistor is recommended, with the

value in the range of a few tens of ohms, not to exceed 100Ω.

Pull-up resistors, series diodes and capacitors on the ICSPCLK and ICSPDAT pins are not recommended

as they can interfere with the programmer/debugger communications to the device. If such discrete

components are an application requirement, they should be removed from the circuit during programming

and debugging. Alternatively, refer to the AC/DC characteristics and timing requirements information in

the respective device Flash programming specification for information on capacitive loading limits, and

pin input voltage high (VIH) and input low (VIL) requirements.

For device emulation, ensure that the “Communication Channel Select” (i.e., ICSPCLK/ICSPDAT pins),

programmed into the device, matches the physical connections for the ICSP to the Microchip debugger/

emulator tool.

For more information on available Microchip development tools connection requirements, refer to the

“Development Support” section.

Related Links

38. Development Support

2.5 External Oscillator Pins

Many microcontrollers have options for at least two oscillators: a high-frequency primary oscillator and a

low-frequency secondary oscillator.

The oscillator circuit should be placed on the same side of the board as the device. Place the oscillator

circuit close to the respective oscillator pins with no more than 0.5 inch (12 mm) between the circuit

components and the pins. The load capacitors should be placed next to the oscillator itself, on the same

side of the board.

Use a grounded copper pour around the oscillator circuit to isolate it from surrounding circuits. The

grounded copper pour should be routed directly to the MCU ground. Do not run any signal traces or

PIC18F26/45/46Q10

Guidelines for Getting Started with PIC18F26/45/46...

power traces inside the ground pour. Also, if using a two-sided board, avoid any traces on the other side

of the board where the crystal is placed.

Layout suggestions are shown in the following figure. In-line packages may be handled with a single-

sided layout that completely encompasses the oscillator pins. With fine-pitch packages, it is not always

possible to completely surround the pins and components. A suitable solution is to tie the broken guard

sections to a mirrored ground layer. In all cases, the guard trace(s) must be returned to ground.

Figure 2-3. Suggested Placement of the Oscillator Circuit

GND

`

OSC1

OSC2

SOSCO

SOSCI

Copper Pour Primary Oscillator

Crystal

Secondary Oscillator

Crystal

DEVICE PINS

Primary

Oscillator

C1

C2

SOSC: C1 SOSC: C2

(tied to ground)

Single-Sided and In-Line Layouts:

Fine-Pitch (Dual-Sided) Layouts:

GND

OSCO

OSCI

Bottom Layer

Copper Pour

Oscillator

Crystal

Top Layer Copper Pour

C2

C1

DEVICE PINS

(tied to ground)

(SOSC)

Rev. 30-000059A

4/6/2017

In planning the application’s routing and I/O assignments, ensure that adjacent port pins, and other

signals in close proximity to the oscillator, are benign (i.e., free of high frequencies, short rise and fall

times, and other similar noise).

For additional information and design guidance on oscillator circuits, refer to these Microchip Application

Notes, available at the corporate website (www.microchip.com):

PIC18F26/45/46Q10

Guidelines for Getting Started with PIC18F26/45/46...

• AN826, “Crystal Oscillator Basics and Crystal Selection for rfPIC™ and PICmicro® Devices”

• AN849, “Basic PICmicro® Oscillator Design”

• AN943, “Practical PICmicro® Oscillator Analysis and Design”

• AN949, “Making Your Oscillator Work”

Related Links

4. Oscillator Module (with Fail-Safe Clock Monitor)

2.6 Unused I/Os

Unused I/O pins should be configured as outputs and driven to a logic low state. Alternatively, connect a 1

kΩ to 10 kΩ resistor to VSS on unused pins to drive the output to logic low.

PIC18F26/45/46Q10

Guidelines for Getting Started with PIC18F26/45/46...

3. Device Configuration

Device configuration consists of Configuration Words, Code Protection, Device ID and Rev ID.

3.1 Configuration Words

There are six Configuration Words that allow the user to select the device oscillator, reset, and memory

protection options. These are implemented as Configuration Word 1 through Configuration Word 6 at

300000h through 30000Bh.

Important: The DEBUG bit in Configuration Words is managed automatically by device

development tools including debuggers and programmers. For normal device operation, this bit

should be maintained as a ‘1’.

3.2 Code Protection

Code protection allows the device to be protected from unauthorized access. Program memory protection

and data memory protection are controlled independently. Internal access to the program memory is

unaffected by any code protection setting.

3.2.1 Program Memory Protection

The entire program memory space is protected from external reads and writes by the CP bit. When CP =

0, external reads and writes of program memory are inhibited and a read will return all ‘0’s. The CPU can

continue to read program memory, regardless of the protection bit settings. Self-writing the program

memory is dependent upon the write protection setting.

3.2.2 Data Memory Protection

The entire data EEPROM memory space is protected from external reads and writes by the CPD bit.

When CPD = 0, external reads and writes of data EEPROM memory are inhibited and a read will return

all ‘0’s. The CPU can continue to read data EEPROM memory regardless of the protection bit settings.

3.3 Write Protection

Write protection allows the device to be protected from unintended self-writes. Applications, such as boot

loader software, can be protected while allowing other regions of the program memory to be modified.

The WRT bits define the size of the program memory block that is protected.

3.4 User ID

256 bytes in the memory space (200000h-20000FFh) are designated as ID locations where the user can

store checksum or other code identification numbers. These locations are readable and writable during

normal execution. See the “User ID, Device ID and Configuration Word Access” section for more

information on accessing these memory locations. For more information on checksum calculation, see

the “PIC18F26/45/46Q10 Memory Programming Specification”, (DS40001874).

PIC18F26/45/46Q10

Device Configuration

3.5 Device ID and Revision ID

The 16-bit Device ID word is located at 0x3FFFFE and the 16-bit revision ID is located at 0x3FFFFC.

These locations are read-only and cannot be erased or modified.

Development tools, such as device programmers and debuggers, may be used to read the Device ID,

Revision ID and Configuration Words. Refer to the “Nonvolatile Memory (NVM) Control” section for

more information on accessing these locations.

Related Links

11. (NVM) Nonvolatile Memory Control

PIC18F26/45/46Q10

Device Configuration

3.6 Register Summary - Configuration Words

Address Name Bit Pos.

0x300000 CONFIG1

7:0 RSTOSC[2:0] FEXTOSC[2:0]

15:8 FCMEN CSWEN CLKOUTEN

0x300002 CONFIG2

7:0 BOREN[1:0] LPBOREN PWRTE MCLRE

15:8 XINST DEBUG STVREN PPS1WAY ZCD BORV[1:0]

0x300004 CONFIG3

7:0 WDTE[1:0] WDTCPS[4:0]

15:8 WDTCCS[2:0] WDTCWS[2:0]

0x300006 CONFIG4

7:0 WRT3 WRT2 WRT1 WRT0

15:8 LVP SCANE WRTD WRTB WRTC

0x300008 CONFIG5

7:0 CPD CP

15:8

0x30000A CONFIG6

7:0 EBTR3 EBTR2 EBTR1 EBTR0

15:8 EBTRB

3.7 Register Definitions: Configuration Words

PIC18F26/45/46Q10

Device Configuration

3.7.1 CONFIG1

Name: CONFIG1

Address: 0x300000

Configuration Word 1

Oscillators

Bit 15 14 13 12 11 10 9 8

FCMEN CSWEN CLKOUTEN

Access R/W R/W R/W

Reset 1 1 1

Bit 7 6 5 4 3 2 1 0

RSTOSC[2:0] FEXTOSC[2:0]

Access R/W R/W R/W R/W R/W R/W

Reset 1 1 1 1 1 1

Bit 13 – FCMEN Fail-Safe Clock Monitor Enable bit

Value Description

1Fail-Safe Clock Monitor enabled

0Fail-Safe Clock Monitor disabled

Bit 11 – CSWEN Clock Switch Enable bit

Value Description

1Writing to NOSC and NDIV is allowed

0The NOSC and NDIV bits cannot be changed by user software

Bit 8 – CLKOUTEN Clock Out Enable bit

If FEXTOSC = HS, XT, LP, then this bit is ignored.

Otherwise:

Value Description

1CLKOUT function is disabled; I/O function on OSC2

0CLKOUT function is enabled; FOSC/4 clock appears at OSC2

Bits 6:4 – RSTOSC[2:0] Power-up Default Value for COSC bits

This value is the Reset default value for COSC and selects the oscillator first used by user software.

Refer to COSC operation.

Value Description

111 EXTOSC operating per FEXTOSC bits (device manufacturing default)

110 HFINTOSC with HFFRQ = 4 MHz and CDIV = 4:1

101 LFINTOSC

100 SOSC

011 Reserved

010 EXTOSC with 4x PLL, with EXTOSC operating per FEXTOSC bits

001 Reserved

000 HFINTOSC with HFFRQ = 64 MHz and CDIV = 1:1. Resets COSC/NOSC to b'110'.

Bits 2:0 – FEXTOSC[2:0] FEXTOSC External Oscillator Mode Selection bits

PIC18F26/45/46Q10

Device Configuration

Value Description

111 ECH (external clock) above 16 MHz

110 ECM (external clock) for 500 kHz to 16 MHz

101 ECL (external clock) below 500 kHz

100 Oscillator not enabled

011 Reserved (do not use)

010 HS (crystal oscillator) above 4 MHz

001 XT (crystal oscillator) above 500 kHz, below 4 MHz

000 LP (crystal oscillator) optimized for 32.768 kHz

Related Links

4.6.5 OSCFRQ

4.6.2 OSCCON2

PIC18F26/45/46Q10

Device Configuration

3.7.2 CONFIG2

Name: CONFIG2

Address: 0x300002

Configuration Word 2

Supervisor

Bit 15 14 13 12 11 10 9 8

XINST DEBUG STVREN PPS1WAY ZCD BORV[1:0]

Access R/W R/W R/W R/W R/W R/W R/W

Reset 1 1 1 1 1 1 1

Bit 7 6 5 4 3 2 1 0

BOREN[1:0] LPBOREN PWRTE MCLRE

Access R/W R/W R/W R/W R/W

Reset 0 1 1 1 1

Bit 15 – XINST Extended Instruction Set Enable bit

Value Description

1Extended Instruction Set and Indexed Addressing mode disabled (Legacy mode)

0Extended Instruction Set and Indexed Addressing mode enabled

Bit 13 – DEBUG Debugger Enable bit

Value Description

1Background debugger disabled

0Background debugger enabled

Bit 12 – STVREN Stack Overflow/Underflow Reset Enable bit

Value Description

1Stack Overflow or Underflow will cause a Reset

0Stack Overflow or Underflow will not cause a Reset

Bit 11 – PPS1WAY PPSLOCKED bit One-Way Set Enable bit

Value Description

1The PPSLOCKED bit can only be set once after an unlocking sequence is executed; once

PPSLOCK is set, all future changes to PPS registers are prevented

0The PPSLOCKED bit can be set and cleared as needed (provided an unlocking sequence is

executed)

Bit 10 – ZCD ZCD Disable bit

Value Description

1ZCD disabled. ZCD can be enabled by setting the ZCDSEN bit of ZCDCON

0ZCD always enabled, PMDx[ZCDMD] bit is ignored

Bits 9:8 – BORV[1:0] Brown-out Reset Voltage Selection bit

Value Description

11 Brown-out Reset Voltage (VBOR) set to 1.90V

PIC18F26/45/46Q10

Device Configuration

...........continued

Value Description

10 Brown-out Reset Voltage (VBOR) set to 2.45V

01 Brown-out Reset Voltage (VBOR) set to 2.7V

00 Brown-out Reset Voltage (VBOR) set to 2.85V

Bits 7:6 – BOREN[1:0] Brown-out Reset Enable bits

When enabled, Brown-out Reset Voltage (VBOR) is set by BORV bit

Value Description

11 Brown-out Reset enabled, SBOREN bit is ignored

10 Brown-out Reset enabled while running, disabled in Sleep; SBOREN is ignored

01 Brown-out Reset enabled according to SBOREN

00 Brown-out Reset disabled

Bit 5 – LPBOREN Low-Power BOR Enable bit

Value Description

1Low-Power Brown-out Reset is disabled

0Low-Power Brown-out Reset is enabled

Bit 1 – PWRTE Power-up Timer Enable bit

Value Description

1PWRT disabled

0PWRT enabled

Bit 0 – MCLRE Master Clear (MCLR) Enable bit

Value Condition Description

xIf LVP = 1RE3 pin function is MCLR

1If LVP = 0MCLR pin is MCLR

0If LVP = 0MCLR pin function is port defined function

Note: BORV - The higher voltage setting is recommended for operation at or above 16 MHz.

Related Links

7.4.3 PMD2

PIC18F26/45/46Q10

Device Configuration

3.7.3 CONFIG3

Name: CONFIG3

Address: 0x300004

Configuration Word 3

Windowed Watchdog Timer

Bit 15 14 13 12 11 10 9 8

WDTCCS[2:0] WDTCWS[2:0]

Access R/W R/W R/W R/W R/W R/W

Reset 1 1 1 1 1 1

Bit 7 6 5 4 3 2 1 0

WDTE[1:0] WDTCPS[4:0]

Access R/W R/W R/W R/W R/W R/W R/W

Reset 1 1 1 1 1 1 1

Bits 13:11 – WDTCCS[2:0] WDT Input Clock Selector bits

Value Condition Description

xWDTE=00 These bits have no effect

111 WDTE≠00 Software Control

110 to

010

WDTE≠00 Reserved (Default to LFINTOSC)

001 WDTE≠00 WDT reference clock is the 31.25 kHz MFINTOSC

000 WDTE≠00 WDT reference clock is the 31.0 kHz LFINTOSC (default value)

Bits 10:8 – WDTCWS[2:0] WDT Window Select bits

WDTCWS

WDTCON1[WINDOW] at POR

Software control of

WINDOW

Keyed access

required?

Value Window delay

Percent of time

Window opening

Percent of time

111 111 n/a 100 Yes No

110 110 n/a 100

No Yes

101 101 25 75

100 100 37.5 62.5

011 011 50 50

010 010 62.5 37.5

001 001 75 25

000 000 87.5 12.5

Bits 6:5 – WDTE[1:0] WDT Operating Mode bits

Value Description

11 WDT enabled regardless of Sleep; SEN bit in WDTCON0 is ignored

10 WDT enabled while Sleep = 0, suspended when Sleep = 1; SEN bit in WDTCON0 is ignored

PIC18F26/45/46Q10

Device Configuration

Value Description

01 WDT enabled/disabled by SEN bit in WDTCON0

00 WDT disabled, SEN bit in WDTCON0 is ignored

Bits 4:0 – WDTCPS[4:0] WDT Period Select bits

WDTCPS

WDTCON0[WDTPS] at POR

Software Control of WDTPS?

Value Divider Ratio Typical Time-Out

(FIN = 31 kHz)

11111 01011 1:65536 216 2s Yes

11110

...

10011

11110

...

10011

1:32 251 ms No

10010 10010 1:8388608 223 256s

No

10001 10001 1:4194304 222 128s

10000 10000 1:2097152 221 64s

01111 01111 1:1048576 220 32s

01110 01110 1:524299 219 16s

01101 01101 1:262144 218 8s

01100 01100 1:131072 217 4s

01011 01011 1:65536 216 2s

01010 01010 1:32768 215 1s

01001 01001 1:16384 214 512 ms

01000 01000 1:8192 213 256 ms

00111 00111 1:4096 212 128 ms

00110 00110 1:2048 211 64 ms

00101 00101 1:1024 210 32 ms

00100 00100 1:512 2916 ms

00011 00011 1:256 288 ms

00010 00010 1:128 274 ms

00001 00001 1:64 262 ms

00000 00000 1:32 251 ms

PIC18F26/45/46Q10

Device Configuration

3.7.4 CONFIG4

Name: CONFIG4

Address: 0x300006

Configuration Word 4

Memory Write Protection

Bit 15 14 13 12 11 10 9 8

LVP SCANE WRTD WRTB WRTC

Access R/W R/W R/W R/W R/W

Reset 1 1 1 1 1

Bit 7 6 5 4 3 2 1 0

WRT3 WRT2 WRT1 WRT0

Access R/W R/W R/W R/W

Reset 1 1 1 1

Bit 13 – LVP Low-Voltage Programming Enable bit

The LVP bit cannot be written (to zero) while operating from the LVP programming interface. The purpose

of this rule is to prevent the user from dropping out of LVP mode while programming from LVP mode, or

accidentally eliminating LVP mode from the Configuration state.

Value Description

1Low-voltage programming enabled. MCLR/VPP pin function is MCLR. MCLRE Configuration

bit is ignored.

0HV on MCLR/VPP must be used for programming

Bit 12 – SCANE Scanner Enable bit

Value Description

1Scanner module is available for use, PMD0[SCANMD] bit enables the module

0Scanner module is NOT available for use, PMD0[SCANMD] bit is ignored

Bit 10 – WRTD Data EEPROM Write Protection bit

Value Description

1Data EEPROM NOT write-protected

0Data EEPROM write-protected

Bit 9 – WRTB Boot Block Write Protection bit

Value Description

1Boot Block NOT write-protected

0Boot Block write-protected

Bit 8 – WRTC Configuration Register Write Protection bit

Value Description

1Configuration Registers NOT write-protected

0Configuration Registers write-protected

Bits 0, 1, 2, 3 – WRTn User NVM Self-Write Protection bits

Value Description

1Corresponding Memory Block NOT write-protected

PIC18F26/45/46Q10

Device Configuration

Value Description

0Corresponding Memory Block write-protected

Related Links

10.1 Program Memory Organization

11.3.4 Operation During Code-Protect and Write-Protect

PIC18F26/45/46Q10

Device Configuration

3.7.5 CONFIG5

Name: CONFIG5

Address: 0x300008

Configuration Word 5

Code Protection

Bit 15 14 13 12 11 10 9 8

Access

Reset

Bit 7 6 5 4 3 2 1 0

CPD CP

Access RO RO

Reset 1 1

Bit 1 – CPD Data NVM (DFM) Memory Code Protection bit

Value Description

1Data NVM code protection disabled

0Data NVM code protection enabled

Bit 0 – CP User NVM Program Memory Code Protection bit

Value Description

1User NVM code protection disabled

0User NVM code protection enabled

PIC18F26/45/46Q10

Device Configuration

3.7.6 CONFIG6

Name: CONFIG6

Address: 0x30000A

Configuration Word 6

Memory Read Protection

Bit 15 14 13 12 11 10 9 8

EBTRB

Access R/W

Reset 1

Bit 7 6 5 4 3 2 1 0

EBTR3 EBTR2 EBTR1 EBTR0

Access R/W R/W R/W R/W

Reset 1 1 1 1

Bit 9 – EBTRB Table Read Protection bit

Value Description

1Memory Boot Block NOT protected from table reads executed in other blocks

0Memory Boot Block protected from table reads executed in other blocks

Bits 0, 1, 2, 3 – EBTRn Table Read Protection bits

Value Description

1Corresponding Memory Block NOT protected from table reads executed in other blocks

0Corresponding Memory Block protected from table reads executed in other blocks

Related Links

10.1 Program Memory Organization

PIC18F26/45/46Q10

Device Configuration

3.8 Register Summary - Device and Revision

Address Name Bit Pos.

0x3FFFFC REVISION ID

7:0 MJRREV[1:0] MNRREV[5:0]

15:8 1010[3:0] MJRREV[5:2]

0x3FFFFE DEVICE ID

7:0 DEV[7:0]

15:8 DEV[15:8]

3.9 Register Definitions: Device and Revision

PIC18F26/45/46Q10

Device Configuration

3.9.1 DEVICE ID

Name: DEVICE ID

Address: 0x3FFFFE

Device ID Register

Bit 15 14 13 12 11 10 9 8

DEV[15:8]

Access RO RO RO RO RO RO RO RO

Reset q q q q q q q q

Bit 7 6 5 4 3 2 1 0

DEV[7:0]

Access RO RO RO RO RO RO RO RO

Reset q q q q q q q q

Bits 15:0 – DEV[15:0]

Device ID bits

Device Device ID

PIC18F26Q10 7180h

PIC18F45Q10 7140h

PIC18F46Q10 7120h

PIC18F26/45/46Q10

Device Configuration

3.9.2 REVISION ID

Name: REVISION ID

Address: 0x3FFFFC

Revision ID Register

Bit 15 14 13 12 11 10 9 8

1010[3:0] MJRREV[5:2]

Access RO RO RO RO RO RO RO RO

Reset 1 0 1 0 q q q q

Bit 7 6 5 4 3 2 1 0

MJRREV[1:0] MNRREV[5:0]

Access RO RO RO RO RO RO RO RO

Reset q q q q q q q q

Bits 15:12 – 1010[3:0] Read as ‘1010’

These bits are fixed with value ‘1010’ for all devices in this family.

Bits 11:6 – MJRREV[5:0] Major Revision ID bits

These bits are used to identify a major revision. A major revision is indicated by an all-layer revision (A0,

B0, C0, etc.).

Revision A = b'00 0000'

Bits 5:0 – MNRREV[5:0] Minor Revision ID bits

These bits are used to identify a minor revision.

PIC18F26/45/46Q10

Device Configuration

4. Oscillator Module (with Fail-Safe Clock Monitor)

4.1 Overview

The oscillator module has multiple clock sources and selection features that allow it to be used in a wide

range of applications while maximizing performance and minimizing power consumption. Figure 4-1

illustrates a block diagram of the oscillator module.

Clock sources can be supplied from external oscillators, quartz-crystal resonators and ceramic

resonators. In addition, the system clock source can be supplied from one of two internal oscillators and

PLL circuits, with a choice of speeds selectable via software. Additional clock features include:

• Selectable system clock source between external or internal sources via software.

• Fail-Safe Clock Monitor (FSCM) designed to detect a failure of the external clock source (LP, XT, HS,

ECH, ECM, ECL) and switch automatically to the internal oscillator.

• Oscillator Start-up Timer (OST) ensures stability of crystal oscillator sources.

The RSTOSC bits of Configuration Word 1 determine the type of oscillator that will be used when the

device runs after Reset, including when it is first powered up.

If an external clock source is selected, the FEXTOSC bits of Configuration Word 1 must be used in

conjunction with the RSTOSC bits to select the External Clock mode.

The external oscillator module can be configured in one of the following clock modes, by setting the

FEXTOSC<2:0> bits of Configuration Word 1:

• ECL – External Clock Low-Power mode

(below 100 kHz)

• ECM – External Clock Medium Power mode

(100 kHz to 16 MHz)

• ECH – External Clock High-Power mode

(above 16 MHz)

• LP – 32 kHz Low-Power Crystal mode

• XT – Medium Gain Crystal or Ceramic Resonator Oscillator mode (between 500 kHz and 4 MHz)

• HS – High Gain Crystal or Ceramic Resonator mode (above 4 MHz)

The ECH, ECM, and ECL Clock modes rely on an external logic level signal as the device clock source.

The LP, XT, and HS Clock modes require an external crystal or resonator to be connected to the device.

Each mode is optimized for a different frequency range. The internal oscillator block produces low and

high-frequency clock sources, designated LFINTOSC and HFINTOSC. Multiple device clock frequencies

may be derived from these clock sources.

PIC18F26/45/46Q10

Oscillator Module (with Fail-Safe Clock Monitor)

Figure 4-1. Simplified PIC® MCU Clock Source Block Diagram

Filename: 10-000208D.vsd

Title: Simplified Clock Source Block Diagram for PIC18(L)F2x/4x/6xK40

Last Edit: 5/10/2016

First Used: PIC18(L)F2x/4x/6xK40 (MVAE,MVAF,MVAB,MVAC,MVAK)

Notes:

Rev. 10-000208D

5/10/2016

FRQ<3:0>

HFINTOSC

Secondary

Oscillator

(SOSC)

External

Oscillator

(EXTOSC)

CLKIN/OSC1

CLKOUT/OSC2

SOSCIN/SOSCI

SOSCO

31 kHz

Oscillator

4x PLL

000

110

011

001

101

100

010

111

COSC<2:0>

LFINTOSC

1,2,4,8,12,16,32,48,64

MHz

Oscillator

Post-Divider

1000

1001

0000

0011

0010

0001

0100

0101

0110

0111

512

256

128

64

32

16

8

4

2

1

CDIV<4:0>

Sleep

Idle

Sleep

SYSCMD

System Clock

Peripheral Clock

FSCM

To Peripherals

MFINTOSC

31.25 kHz and 500 kHz

Oscillator

To Peripherals

Reserved

LFINTOSC is used to

monitor system clock

Related Links

3.7.1 CONFIG1

4.2 Clock Source Types

Clock sources can be classified as external or internal.

External clock sources rely on external circuitry for the clock source to function. Examples are: oscillator

modules (ECH, ECM, ECL mode), quartz crystal resonators or ceramic resonators (LP, XT and HS

modes).

Internal clock sources are contained within the oscillator module. The internal oscillator block has two

internal oscillators that are used to generate internal system clock sources. The High-Frequency Internal

Oscillator (HFINTOSC) can produce 1, 2, 4, 8, 12, 16, 32, 48 and 64 MHz clock. The frequency can be

controlled through the OSCFRQ register. The Low-Frequency Internal Oscillator (LFINTOSC) generates a

fixed 31 kHz frequency.

A 4x PLL is provided that can be used in conjunction with the external clock.

The system clock can be selected between external or internal clock sources via the NOSC bits. The

system clock can be made available on the OSC2/CLKOUT pin for any of the modes that do not use the

OSC2 pin. The clock out functionality is governed by the CLKOUTEN bit in the CONFIG1H register. If

enabled, the clock out signal is always at a frequency of FOSC/4.

Related Links

4.6.5 OSCFRQ

4.2.1.4 4x PLL

PIC18F26/45/46Q10

Oscillator Module (with Fail-Safe Clock Monitor)

4.3 Clock Switching

4.2.1 External Clock Sources

An external clock source can be used as the device system clock by performing one of the following

actions:

• Program the RSTOSC<2:0> and FEXTOSC<2:0> bits in the Configuration Words to select an

external clock source that will be used as the default system clock upon a device Reset.

• Write the NOSC<2:0> and NDIV<3:0> bits to switch the system clock source.

Related Links

4.3 Clock Switching

4.2.1.1 EC Mode

The External Clock (EC) mode allows an externally generated logic level signal to be the system clock

source. When operating in this mode, an external clock source is connected to the OSC1 input. OSC2/

CLKOUT is available for general purpose I/O or CLKOUT. The following figure shows the pin connections

for EC mode.

EC mode has three power modes to select from through Configuration Words:

• ECH – High power, above 16 MHz

• ECM – Medium power, 100 kHz-16 MHz

• ECL – Low power, below 100 kHz

The Oscillator Start-up Timer (OST) is disabled when EC mode is selected. Therefore, there is no delay

in operation after a Power-on Reset (POR) or wake-up from Sleep. Because the PIC® MCU design is fully

static, stopping the external clock input will have the effect of halting the device while leaving all data

intact. Upon restarting the external clock, the device will resume operation as if no time had elapsed.

Figure 4-2. External Clock (EC) Mode Operation

OSC1/CLKIN

OSC2/CLKOUT

Clock from

Ext. System

PIC®MCU

FOSC/4 or I/O(1)

Rev. 30-000060A

4/6/2017

Note:

1. Output depends upon CLKOUTEN bit of the Configuration Words (CONFIG1H).

4.2.1.2 LP, XT, HS Modes

The LP, XT and HS modes support the use of quartz crystal resonators or ceramic resonators connected

to OSC1 and OSC2 (Figure 4-3). The three modes select a low, medium or high gain setting of the

internal inverter-amplifier to support various resonator types and speed.

LP Oscillator mode selects the lowest gain setting of the internal inverter-amplifier. LP mode current

consumption is the least of the three modes. This mode is designed to drive only 32.768 kHz tuning-fork

type crystals (watch crystals).

XT Oscillator mode selects the intermediate gain setting of the internal inverter-amplifier. XT mode current

consumption is the medium of the three modes. This mode is best suited to drive resonators with a

medium drive level specification (between 100 kHz - 4 MHz).

PIC18F26/45/46Q10

Oscillator Module (with Fail-Safe Clock Monitor)

HS Oscillator mode selects the highest gain setting of the internal inverter-amplifier. HS mode current

consumption is the highest of the three modes. This mode is best suited for resonators that require a high

drive setting (above 4 MHz).

Figure 4-3 and Figure 4-4 show typical circuits for quartz crystal and ceramic resonators, respectively.

Figure 4-3. Quartz Crystal Operation (LP, XT or HS Mode)

 

C1

C2

Quartz

RS(1)

OSC1/CLKIN

RF(2) Sleep

To Internal

Logic

PIC®MCU

Crystal

OSC2/CLKOUT

Rev. 30-000061A

4/6/2017

Note:

1. A series resistor (RS) may be required for quartz crystals with low drive level.

2. The value of RF varies with the Oscillator mode selected (typically between 2 MΩ to 10 MΩ).

Figure 4-4. Ceramic Resonator Operation

(XT or HS Mode)

 

C1

C2 Ceramic RS(1)

OSC1/CLKIN

RF(2) Sleep

To Internal

Logic

PIC®MCU

RP(3)

Resonator

OSC2/CLKOUT

Rev. 30-000062A

4/6/2017

Note:

1. A series resistor (RS) may be required for ceramic resonators with low drive level.

2. The value of RF varies with the Oscillator mode selected (typically between 2 MΩ to 10 MΩ).

3. An additional parallel feedback resistor (RP) may be required for proper ceramic resonator

operation.

4.2.1.3 Oscillator Start-up Timer (OST)

If the oscillator module is configured for LP, XT or HS modes, the Oscillator Start-up Timer (OST) counts

1024 oscillations from OSC1. This occurs following a Power-on Reset (POR), or a wake-up from Sleep.

The OST ensures that the oscillator circuit, using a quartz crystal resonator or ceramic resonator, has

started and is providing a stable system clock to the oscillator module.

4.2.1.4 4x PLL

The oscillator module contains a 4x PLL that can be used with the external clock sources to provide a

system clock source. The input frequency for the PLL must fall within specifications.

PIC18F26/45/46Q10

Oscillator Module (with Fail-Safe Clock Monitor)

The PLL can be enabled for use by one of two methods:

1. Program the RSTOSC bits in the Configuration Word 1 to ‘010’ (enable EXTOSC with 4x PLL).

2. Write the NOSC bits to ‘010’ (enable EXTOSC with 4x PLL).

Related Links

39.4.3 PLL Specifications

4.2.1.5 Secondary Oscillator

The secondary oscillator is a separate oscillator block that can be used as an alternate system clock

source. The secondary oscillator is optimized for 32.768 kHz, and can be used with an external crystal

oscillator connected to the SOSCI and SOSCO device pins, or an external clock source connected to the

SOSCIN pin. The secondary oscillator can be selected during run-time using clock switching.

Figure 4-5. Quartz Crystal Operation (Secondary Oscillator)

C1

C2

32.768 kHz

SOSCI

To Internal

Logic

PIC®MCU

Crystal

SOSCO

Quartz

Rev. 30-000063A

4/6/2017

Note:

1. Quartz crystal characteristics vary according to type, package and manufacturer. The user should

consult the manufacturer data sheets for specifications and recommended application.

2. Always verify oscillator performance over the VDD and temperature range that is expected for the

application.

3. For oscillator design assistance, reference the following Microchip Application Notes:

– AN826, “Crystal Oscillator Basics and Crystal Selection for PIC® and PIC® Devices” (DS00826)

– AN849, “Basic PIC® Oscillator Design” (DS00849)

– AN943, “Practical PIC® Oscillator Analysis and Design” (DS00943)

– AN949, “Making Your Oscillator Work” (DS00949)

– TB097, “Interfacing a Micro Crystal MS1V-T1K 32.768 kHz Tuning Fork Crystal to a

PIC16F690/SS” (DS91097)

– AN1288, “Design Practices for Low-Power External Oscillators” (DS01288)

Related Links

4.3 Clock Switching

4.2.2 Internal Clock Sources

The device may be configured to use the internal oscillator block as the system clock by performing one

of the following actions:

• Program the RSTOSC<2:0> bits in Configuration Words to select the INTOSC clock as the default

system clock upon a device Reset.

PIC18F26/45/46Q10

Oscillator Module (with Fail-Safe Clock Monitor)

• Write the NOSC<2:0> bits to switch the system clock source to the internal oscillator during run-time.

In INTOSC mode, OSC1/CLKIN is available for general purpose I/O. OSC2/CLKOUT is available for

general purpose I/O or CLKOUT.

The function of the OSC2/CLKOUT pin is determined by the CLKOUTEN bit in Configuration Words.

The internal oscillator block has two independent oscillators that can produce two internal system clock

sources.

1. The HFINTOSC (High-Frequency Internal Oscillator) is factory-calibrated and operates from 1 to 64

MHz. The frequency of HFINTOSC can be selected through the OSCFRQ Frequency Selection

register, and fine-tuning can be done via the OSCTUNE register.

2. The LFINTOSC (Low-Frequency Internal Oscillator) is factory-calibrated and operates at 31 kHz.

Related Links

4.3 Clock Switching

4.6.5 OSCFRQ

4.6.6 OSCTUNE

4.2.2.1 HFINTOSC

The High-Frequency Internal Oscillator (HFINTOSC) is a precision digitally-controlled internal clock

source that produces a stable clock up to 64 MHz. The HFINTOSC can be enabled through one of the

following methods:

• Programming the RSTOSC<2:0> bits in Configuration Word 1 to ‘110’ (FOSC = 1 MHz) or ‘000’ (FOSC

= 64 MHz) to set the oscillator upon device Power-up or Reset.

• Write to the NOSC<2:0> bits during run-time.

The HFINTOSC frequency can be selected by setting the HFFRQ<3:0> bits.

The NDIV<3:0> bits allow for division of the HFINTOSC output from a range between 1:1 and 1:512.

Related Links

4.3 Clock Switching

4.2.2.2 MFINTOSC

The module provides two (500 kHz and 31.25 kHz) constant clock outputs. These clocks are digital

divisors of the HFINTOSC clock. Dynamic divider logic is used to provide constant MFINTOSC clock

rates for all settings of HFINTOSC.

The MFINTOSC cannot be used to drive the system but it is used to clock certain modules such as the

Timers and WWDT.

4.2.2.3 LFINTOSC

The Low-Frequency Internal Oscillator (LFINTOSC) is a factory-calibrated 31 kHz internal clock source.

The LFINTOSC is the frequency for the Power-up Timer (PWRT), Windowed Watchdog Timer (WWDT)

and Fail-Safe Clock Monitor (FSCM).

The LFINTOSC is enabled through one of the following methods:

• Programming the RSTOSC<2:0> bits of Configuration Word 1 to enable LFINTOSC.

• Write to the NOSC<2:0> bits during run-time.

Related Links

4.3 Clock Switching

PIC18F26/45/46Q10

Oscillator Module (with Fail-Safe Clock Monitor)

4.2.2.4 ADCRC (also referred to as FRC)

The ADCRC is an oscillator dedicated to the ADC2 module. The ADCRC oscillator can be manually

enabled using the ADOEN bit. The ADCRC runs at a fixed frequency of 600 kHz. ADCRC is automatically

enabled if it is selected as the clock source for the ADC2 module.

4.2.3 Oscillator Status and Adjustments

4.2.3.1 Internal Oscillator Frequency Adjustment

The internal oscillator is factory-calibrated. This internal oscillator can be adjusted in software by writing

to the OSCTUNE register.

The default value of the OSCTUNE register is 00h. The value is a 6-bit two’s complement number. A

value of 1Fh will provide an adjustment to the maximum frequency. A value of 20h will provide an

adjustment to the minimum frequency.

When the OSCTUNE register is modified, the oscillator frequency will begin shifting to the new frequency.

Code execution continues during this shift. There is no indication that the shift has occurred.

OSCTUNE does not affect the LFINTOSC frequency. Operation of features that depend on the

LFINTOSC clock source frequency, such as the Power-up Timer (PWRT), WWDT, Fail-Safe Clock

Monitor (FSCM) and peripherals, are not affected by the change in frequency.

Related Links

4.6.6 OSCTUNE

4.2.3.2 Oscillator Status and Manual Enable

The Ready status of each oscillator (including the ADCRC oscillator) is displayed in OSCSTAT. The

oscillators (but not the PLL) may be explicitly enabled through OSCEN.

Related Links

4.6.4 OSCSTAT

4.6.7 OSCEN

4.2.3.3 HFOR and MFOR Bits

The HFOR and MFOR bits indicate that the HFINTOSC and MFINTOSC is ready. These clocks are

always valid for use at all times, but only accurate after they are ready.

When a new value is loaded into the OSCFRQ register, the HFOR and MFOR bits will clear, and set

again when the oscillator is ready. During pending OSCFRQ changes the MFINTOSC clock will stall at a

high or a low state, until the HFINTOSC resumes operation.

4.3 Clock Switching

The system clock source can be switched between external and internal clock sources via software using

the New Oscillator Source (NOSC) bits. The following clock sources can be selected using the following:

• External oscillator

• Internal Oscillator Block (INTOSC)

PIC18F26/45/46Q10

Oscillator Module (with Fail-Safe Clock Monitor)

Important: The Clock Switch Enable bit in Configuration Word 1 can be used to enable or

disable the clock switching capability. When cleared, the NOSC and NDIV bits cannot be

changed by user software. When set, writing to NOSC and NDIV is allowed and would

switch the clock frequency.

4.3.1 New Oscillator Source (NOSC) and New Divider Selection Request (NDIV) Bits

The New Oscillator Source (NOSC) and New Divider Selection Request (NDIV) bits select the system

clock source and frequency that are used for the CPU and peripherals.

When new values of NOSC and NDIV are written to OSCCON1, the current oscillator selection will

continue to operate while waiting for the new clock source to indicate that it is stable and ready. In some

cases, the newly requested source may already be in use, and is ready immediately. In the case of a

divider-only change, the new and old sources are the same, so the source will be ready immediately. The

device may enter Sleep while waiting for the switch.

When the new oscillator is ready, the New Oscillator Ready (NOSCR) bit is set and also the Clock Switch

Interrupt Flag (CSWIF) bit of PIR1 sets. If Clock Switch Interrupts are enabled (CSWIE = 1), an interrupt

will be generated at that time. The Oscillator Ready (ORDY) bit can also be polled to determine when the

oscillator is ready in lieu of an interrupt.

Important: The CSWIF interrupt will not wake the system from Sleep.

If the Clock Switch Hold (CSWHOLD) bit is clear, the oscillator switch will occur when the New Oscillator

is Ready bit (NOSCR) is set, and the interrupt (if enabled) will be serviced at the new oscillator setting.

If CSWHOLD is set, the oscillator switch is suspended, while execution continues using the current (old)

clock source. When the NOSCR bit is set, software should:

• Set CSWHOLD = 0 so the switch can complete, or

• Copy COSC into NOSC to abandon the switch.

If DOZE is in effect, the switch occurs on the next clock cycle, whether or not the CPU is operating during

that cycle.

Changing the clock post-divider without changing the clock source (i.e., changing FOSC from 1 MHz to 2

MHz) is handled in the same manner as a clock source change, as described previously. The clock

source will already be active, so the switch is relatively quick. CSWHOLD must be clear (CSWHOLD = 0)

for the switch to complete.

The current COSC and CDIV are indicated in the OSCCON2 register up to the moment when the switch

actually occurs, at which time OSCCON2 is updated and ORDY is set. NOSCR is cleared by hardware to

indicate that the switch is complete.

Related Links

4.3.3 Clock Switch and Sleep

4.3.2 PLL Input Switch

Switching between the PLL and any non-PLL source is managed as described above. The input to the

PLL is established when NOSC selects the PLL, and maintained by the COSC setting.

PIC18F26/45/46Q10

Oscillator Module (with Fail-Safe Clock Monitor)

When NOSC and COSC select the PLL with different input sources, the system continues to run using

the COSC setting, and the new source is enabled per NOSC. When the new oscillator is ready (and

CSWHOLD = 0), system operation is suspended while the PLL input is switched and the PLL acquires

lock. This provides a truly glitch-free clock switch operation.

Important: If the PLL fails to lock, the FSCM will trigger.

4.3.3 Clock Switch and Sleep

If OSCCON1 is written with a new value and the device is put to Sleep before the switch completes, the

switch will not take place and the device will enter Sleep mode.

When the device wakes from Sleep and the CSWHOLD bit is clear, the device will wake with the ‘new’

clock active, and the Clock Switch Interrupt Flag bit (CSWIF) will be set.

When the device wakes from Sleep and the CSWHOLD bit is set, the device will wake with the ‘old’ clock

active and the new clock will be requested again.

Figure 4-6. Clock Switch (CSWHOLD = 0)

Note 1: CSWIF is asserted coincident with NOSCR; interrupt is serviced at OSC#2 speed.

2: The assertion of NOSCR is hidden from the user because it appears only for the duration of the switch.

CSWHOLD

NOSCR

OSC #2

CSWIF

OSCCON1

WRITTEN

NOTE 1

USER

CLEAR

OSC #1

NOTE 2

ORDY

Rev. 30-000064A

4/7/2016

Note:

1. CSWIF is asserted coincident with NOSCR; interrupt is serviced at OSC#2 speed.

2. The assertion of NOSCR is hidden from the user because it appears only for the duration of the

switch.

PIC18F26/45/46Q10

Oscillator Module (with Fail-Safe Clock Monitor)

Figure 4-7. Clock Switch (CSWHOLD = 1)

Note 1: CSWIF is asserted coincident with NOSCR, and may be cleared before or after clearing CSWHOLD = 0.

CSWHOLD

NOSCR

OSC #1 OSC #2

CSWIF

OSCCON1

WRITTEN

NOTE 1

ORDY

USER

CLEAR

Rev. 30-000065A

4/6/2017

Note:

1. CSWIF is asserted coincident with NOSCR, and may be cleared before or after clearing

CSWHOLD = 0.

Figure 4-8. Clock Switch Abandoned

CSWHOLD

NOSCR

OSC #1

CSWIF

OSCCON1

WRITTEN

NOTE 1

OSCCON1

WRITTEN

NOTE 2

ORDY

Rev. 30-000066A

4/6/2017

Note:

1. CSWIF may be cleared before or after rewriting OSCCON1; CSWIF is not automatically cleared.

2. ORDY = 0 if OSCCON1 does not match OSCCON2; a new switch will begin.

4.4 Fail-Safe Clock Monitor

The Fail-Safe Clock Monitor (FSCM) allows the device to continue operating should the external oscillator

fail. The FSCM is enabled by setting the FCMEN bit in the Configuration Words. The FSCM is applicable

to all external Oscillator modes (LP, XT, HS, ECL/M/H and Secondary Oscillator).

PIC18F26/45/46Q10

Oscillator Module (with Fail-Safe Clock Monitor)

Figure 4-9. FSCM Block Diagram

External

LFINTOSC ÷ 64

S

R

Q

31 kHz

(~32 us)

488 Hz

(~2 ms)

Clock Monitor

Latch

Clock

Failure

Detected

Oscillator

Clock

Q

Sample Clock

Rev. 30-000067A

4/6/2017

4.4.1 Fail-Safe Detection

The FSCM module detects a failed oscillator by comparing the external oscillator to the FSCM sample

clock. The sample clock is generated by dividing the LFINTOSC by 64. See Figure 4-9. Inside the fail

detector block is a latch. The external clock sets the latch on each falling edge of the external clock. The

sample clock clears the latch on each rising edge of the sample clock. A failure is detected when an

entire half-cycle of the sample clock elapses before the external clock goes low.

4.4.2 Fail-Safe Operation

When the external clock fails, the FSCM overwrites the COSC bits to select HFINTOSC (3'b110). The

frequency of HFINTOSC would be determined by the previous state of the HFFRQ bits and the NDIV/

CDIV bits. The bit flag OSCFIF of the PIR1 register is set. Setting this flag will generate an interrupt if the

OSCFIE bit of the PIE1 register is also set. The device firmware can then take steps to mitigate the

problems that may arise from a failed clock. The system clock will continue to be sourced from the

internal clock source until the device firmware successfully restarts the external oscillator and switches

back to external operation, by writing to the NOSC and NDIV bits.

4.4.3 Fail-Safe Condition Clearing

The Fail-Safe condition is cleared after a Reset, executing a SLEEP instruction or changing the NOSC

and NDIV bits. When switching to the external oscillator or PLL, the OST is restarted. While the OST is

running, the device continues to operate from the INTOSC selected in OSCCON1. When the OST times

out, the Fail-Safe condition is cleared after successfully switching to the external clock source. The

OSCFIF bit should be cleared prior to switching to the external clock source. If the Fail-Safe condition still

exists, the OSCFIF flag will again become set by hardware.

4.4.4 Reset or Wake-up from Sleep

The FSCM is designed to detect an oscillator failure after the Oscillator Start-up Timer (OST) has expired.

The OST is used after waking up from Sleep and after any type of Reset. The OST is not used with the

EC Clock modes so that the FSCM will be active as soon as the Reset or wake-up has completed.

PIC18F26/45/46Q10

Oscillator Module (with Fail-Safe Clock Monitor)

Figure 4-10. FSCM Timing Diagram

OSCFIF

System

Clock

Output

Sample Clock

Failure

Detected

Oscillator

Failure

(Q)

Test Test Test

Clock Monitor Output

Rev. 30-000068A

4/6/2017

Note: The system clock is normally at a much higher frequency than the sample clock. The relative

frequencies in this example have been chosen for clarity.

PIC18F26/45/46Q10

Oscillator Module (with Fail-Safe Clock Monitor)

4.5 Register Summary - OSC

Address Name Bit Pos.

0x0ED3 OSCCON1 7:0 NOSC[2:0] NDIV[3:0]

0x0ED4 OSCCON2 7:0 COSC[2:0] CDIV[3:0]

0x0ED5 OSCCON3 7:0 CSWHOLD SOSCPWR ORDY NOSCR

0x0ED6 OSCSTAT 7:0 EXTOR HFOR MFOR LFOR SOR ADOR PLLR

0x0ED7 OSCEN 7:0 EXTOEN HFOEN MFOEN LFOEN SOSCEN ADOEN

0x0ED8 OSCTUNE 7:0 HFTUN[5:0]

0x0ED9 OSCFRQ 7:0 HFFRQ[3:0]

4.6 Register Definitions: Oscillator Control

PIC18F26/45/46Q10

Oscillator Module (with Fail-Safe Clock Monitor)

4.6.1 OSCCON1

Name: OSCCON1

Address: 0xED3

Oscillator Control Register1

Bit 7 6 5 4 3 2 1 0

NOSC[2:0] NDIV[3:0]

Access R/W R/W R/W R/W R/W R/W R/W

Reset f f f f f f f

Bits 6:4 – NOSC[2:0] New Oscillator Source Request bits(1,2,3)

The setting requests a source oscillator and PLL combination per Table 4-2.

Table 4-1. Default Oscillator Settings

CONFIG1[RSTOSC]

SFR Reset Values (fff ffff)

Initial FOSC Frequency

NOSC/COSC NDIV/CDIV OSCFRQ

111 111 0000

4 MHz

EXTOSC per FEXTOSC

110 110 0010 FOSC = 1 MHz (4 MHz/4)

101 101 0000 LFINTOSC

100 100 0000 SOSC

011 Reserved

010 010 0000 4 MHz EXTOSC + 4xPLL(4)

001 Reserved

000 110 0000 64 MHz FOSC = 64 MHz

Table 4-2. NOSC Bit Settings

NOSC<2:0> Clock Source

111 EXTOSC(5)

110 HFINTOSC(6)

101 LFINTOSC

100 SOSC

011 Reserved

010 EXTOSC + 4x PLL(7)

001 Reserved

000 Reserved

Bits 3:0 – NDIV[3:0] New Divider Selection Request bits(2,3)

The setting determines the new postscaler division ratio per Table 4-3.

PIC18F26/45/46Q10

Oscillator Module (with Fail-Safe Clock Monitor)

Table 4-3. NDIV Bit Settings

NDIV<3:0> Clock Divider

1111-1010 Reserved

1001 512

1000 256

0111 128

0110 64

0101 32

0100 16

0011 8

0010 4

0001 2

0000 1

Note:

1. The default value (f/f) is determined by the CONFIG1[RSTOSC] Configuration bits. See Table 4-1.

2. If NOSC is written with a reserved value (Table 4-2), the operation is ignored and NOSC is not

written.

3. When CONFIG1[CSWEN] = 0, this register is read-only and cannot be changed from the POR

value.

4. EXTOSC must meet the PLL specifications.

5. EXTOSC configured by CONFIG1[FEXTOSC].

6. HFINTOSC frequency is set with the HFFRQ bits.

7. EXTOSC must meet the PLL specifications.

Related Links

3.7.1 CONFIG1

39.4.3 PLL Specifications

PIC18F26/45/46Q10

Oscillator Module (with Fail-Safe Clock Monitor)

4.6.2 OSCCON2

Name: OSCCON2

Address: 0xED4

Oscillator Control Register 2

Bit 7 6 5 4 3 2 1 0

COSC[2:0] CDIV[3:0]

Access R R R R R R R

Reset q q q q q q q

Bits 6:4 – COSC[2:0] Current Oscillator Source Select bits (read-only)(1,2)

Indicates the current source oscillator and PLL combination as shown in the following table.

Table 4-4. COSC Bit Settings

COSC/NOSC Clock Source

111 EXTOSC(3)

110 HFINTOSC(4)

101 LFINTOSC

100 SOSC

011 Reserved

010 EXTOSC + 4x PLL(5)

001 Reserved

000 Reserved

Bits 3:0 – CDIV[3:0] Current Divider Select bits (read-only)(1,2)

Indicates the current postscaler division ratio as shown in the follwing table.

Table 4-5. CDIV Bit Settings

CDIV/NDIV Clock Divider

1111-1010 Reserved

1001 512

1000 256

0111 128

0110 64

0101 32

0100 16

0011 8

0010 4

0001 2

PIC18F26/45/46Q10

Oscillator Module (with Fail-Safe Clock Monitor)

...........continued

CDIV/NDIV Clock Divider

0000 1

Note:

1. The POR value is the value present when user code execution begins.

2. The Reset value (q/q) is the same as the NOSC/NDIV bits.

3. EXTOSC configured by the CONFIG1[FEXTOSC] bits.

4. HFINTOSC frequency is set with the HFFRQ bits.

5. EXTOSC must meet the PLL specifications.

Related Links

3.7.1 CONFIG1

39.4.3 PLL Specifications

PIC18F26/45/46Q10

Oscillator Module (with Fail-Safe Clock Monitor)

4.6.3 OSCCON3

Name: OSCCON3

Address: 0xED5

Oscillator Control Register 3

Bit 7 6 5 4 3 2 1 0

CSWHOLD SOSCPWR ORDY NOSCR

Access R/W/HC R/W RO RO

Reset 0 0 0 0

Bit 7 – CSWHOLD Clock Switch Hold bit

Value Description

1Clock switch will hold (with interrupt) when the oscillator selected by NOSC is ready

0Clock switch may proceed when the oscillator selected by NOSC is ready; when NOSCR

becomes ‘1’, the switch will occur

Bit 6 – SOSCPWR Secondary Oscillator Power Mode Select bit

Value Description

1Secondary oscillator operating in High-Power mode

0Secondary oscillator operating in Low-Power mode

Bit 4 – ORDY Oscillator Ready bit (read-only)

Value Description

1OSCCON1 = OSCCON2; the current system clock is the clock specified by NOSC

0A clock switch is in progress

Bit 3 – NOSCR New Oscillator is Ready bit (read-only)(1)

Value Description

1A clock switch is in progress and the oscillator selected by NOSC indicates a ready condition

0A clock switch is not in progress, or the NOSC-selected oscillator is not yet ready

Note:

1. If CSWHOLD = 0, the user may not see this bit set because the bit is set for less than one

instruction cycle.

PIC18F26/45/46Q10

Oscillator Module (with Fail-Safe Clock Monitor)

4.6.4 OSCSTAT

Name: OSCSTAT

Address: 0xED6

Oscillator Status Register 1

Bit 7 6 5 4 3 2 1 0

EXTOR HFOR MFOR LFOR SOR ADOR PLLR

Access RO RO RO RO RO RO RO

Reset q q q q q q q

Bit 7 – EXTOR EXTOSC (external) Oscillator Ready bit

Value Description

1The oscillator is ready to be used

0The oscillator is not enabled, or is not yet ready to be used

Bit 6 – HFOR HFINTOSC Oscillator Ready bit

Value Description

1The oscillator is ready to be used

0The oscillator is not enabled, or is not yet ready to be used

Bit 5 – MFOR MFINTOSC Oscillator Ready bit

Value Description

1The oscillator is ready to be used

0The oscillator is not enabled, or is not yet ready to be used

Bit 4 – LFOR LFINTOSC Oscillator Ready bit

Value Description

1The oscillator is ready to be used

0The oscillator is not enabled, or is not yet ready to be used

Bit 3 – SOR Secondary (Timer1) Oscillator Ready bit

Value Description

1The oscillator is ready to be used

0The oscillator is not enabled, or is not yet ready to be used

Bit 2 – ADOR ADC Oscillator Ready bit

Value Description

1The oscillator is ready to be used

0The oscillator is not enabled, or is not yet ready to be used

Bit 0 – PLLR PLL Ready bit

Value Description

1The PLL is ready to be used

0The PLL is not enabled, the required input source is not ready, or the PLL is not locked.

PIC18F26/45/46Q10

Oscillator Module (with Fail-Safe Clock Monitor)

4.6.5 OSCFRQ

Name: OSCFRQ

Address: 0xED9

HFINTOSC Frequency Selection Register

Bit 7 6 5 4 3 2 1 0

HFFRQ[3:0]

Access R/W R/W R/W R/W

Reset q q q q

Bits 3:0 – HFFRQ[3:0] HFINTOSC Frequency Selection bits

HFFRQ Nominal Freq (MHz)

1001

Reserved

1010

1111

1110

1101

1100

1011

1000(1) 64

0111 48

0110 32

0101 16

0100 12

0011 8

0010(1) 4

0001 2

0000 1

Note:

1. Refer to Table 4-1 for more information.

PIC18F26/45/46Q10

Oscillator Module (with Fail-Safe Clock Monitor)

4.6.6 OSCTUNE

Name: OSCTUNE

Address: 0xED8

HFINTOSC Tuning Register

Bit 7 6 5 4 3 2 1 0

HFTUN[5:0]

Access R/W R/W R/W R/W R/W R/W

Reset 0 0 0 0 0 0

Bits 5:0 – HFTUN[5:0] HFINTOSC Frequency Tuning bits

Value Description

01 1111 Maximum frequency

00 0000 Center frequency. Oscillator module is running at the calibrated frequency (default value).

10 0000 Minimum frequency

PIC18F26/45/46Q10

Oscillator Module (with Fail-Safe Clock Monitor)

4.6.7 OSCEN

Name: OSCEN

Address: 0xED7

Oscillator Manual Enable Register

Bit 7 6 5 4 3 2 1 0

EXTOEN HFOEN MFOEN LFOEN SOSCEN ADOEN

Access R/W R/W R/W R/W R/W R/W

Reset 0 0 0 0 0 0

Bit 7 – EXTOEN External Oscillator Manual Request Enable bit

Value Description

1EXTOSC is explicitly enabled, operating as specified by CONFIG1[FEXTOSC]

0EXTOSC is only enabled if requested by a peripheral

Bit 6 – HFOEN HFINTOSC Oscillator Manual Request Enable bit

Value Description

1HFINTOSC is explicitly enabled, operating as specified by OSCFRQ

0HFINTOSC is only enabled if requested by a peripheral

Bit 5 – MFOEN MFINTOSC (500 kHz/31.25 kHz) Oscillator Manual Request Enable bit (Derived from

HFINTOSC)

Value Description

1MFINTOSC is explicitly enabled

0MFINTOSC is only enabled if requested by a peripheral

Bit 4 – LFOEN LFINTOSC (31 kHz) Oscillator Manual Request Enable bit

Value Description

1LFINTOSC is explicitly enabled

0LFINTOSC is only enabled if requested by a peripheral

Bit 3 – SOSCEN Secondary Oscillator Manual Request Enable bit

Value Description

1Secondary Oscillator is explicitly enabled, operating as specified by SOSCPWR

0Secondary Oscillator is only enabled if requested by a peripheral

Bit 2 – ADOEN ADC Oscillator Manual Request Enable bit

Value Description

1ADC oscillator is explicitly enabled

0ADC oscillator is only enabled if requested by a peripheral

PIC18F26/45/46Q10

Oscillator Module (with Fail-Safe Clock Monitor)

5. Reference Clock Output Module

The reference clock output module provides the ability to send a clock signal to the clock reference output

pin (CLKR). The reference clock output can also be routed internally as a signal for other peripherals,

such as the Data Signal Modulator (DSM), memory scanner, and timer module.

The reference clock output module has the following features:

• Selectable Clock Source Using the CLKRCLK Register

• Programmable Clock Divider

• Selectable Duty Cycle

Figure 5-1. Clock Reference Block Diagram

Filename: 10-000261B.vsd

Title: Clock Reference Block Diagram With Selectable Clock Source

Last Edit: 5/11/2016

First Used: PIC18(L)F2x/4x/6xK40 (MVAF,MVAE,MVAB,MVAC,MVAK)

Notes:

Rev. 10-000261B

5/11/2016

000

011

010

001

100

101

110

111

128

64

32

16

8

4

2

EN

DIV

Counter Reset

Duty Cycle PPS

To Peripherals

CLKR

CLK

See

CLKRCLK

Register

EN

Reference Clock Divider

DC RxyPPS

Figure 5-2. Clock Reference Timing

Filename: 10-000264B.vsd

Title: Clock Reference Timing

Last Edit: 5/25/2016

First Used: PIC18(L)F2x/4x/6xK40 (MVAF,MVAE,MVAB,MVAC,MVAK)

Notes:

Rev. 10-000264B

5/25/2016

CLKRCLK

CLKREN

CLKRDIV<2:0> = 001

CLKRDC<1:0> = 10

CLKR Output

Duty Cycle

(50%)

CLKRDIV<2:0> = 001

CLKRDC<1:0> = 01

CLKR Output

Duty Cycle

(25%)

CLKRCLK/2

P1 P2

PIC18F26/45/46Q10

Reference Clock Output Module

5.1 Clock Source

The clock source of the reference clock peripheral is selected with the CLK bits. The available clock

sources are listed in the following table:

Table 5-1. CLKR Clock Sources

CLK Clock Source

1111 LC8_out

1110 LC7_out

1101 LC6_out

1100 LC5_out

1011 LC4_out

1010 LC3_out

1001 LC2_out

1000 LC1_out

0111-0101 0101

0100 SOSC

0011 MFINTOSC (500 kHz)

0010 LFINTOSC (31 kHz)

0001 HFINTOSC

0000 FOSC

5.1.1 Clock Synchronization

The CLKR output signal is ensured to be glitch-free when the EN bit is set to start the module and enable

the CLKR output.

When the reference clock output is disabled, the output signal will be disabled immediately.

Clock dividers and clock duty cycles can be changed while the module is enabled but doing so may

cause glitches to occur on the output. To avoid possible glitches, clock dividers and clock duty cycles

should be changed only when the EN bit is clear.

5.2 Programmable Clock Divider

The module takes the clock input and divides it based on the value of the DIV bits.

The following configurations are available:

• Base FOSC value

• FOSC divided by 2

• FOSC divided by 4

• FOSC divided by 8

• FOSC divided by 16

PIC18F26/45/46Q10

Reference Clock Output Module

• FOSC divided by 32

• FOSC divided by 64

• FOSC divided by 128

The clock divider values can be changed while the module is enabled. However, in order to prevent

glitches on the output, the DIV bits should only be changed when the module is disabled (EN = 0).

5.3 Selectable Duty Cycle

The DC bits are used to modify the duty cycle of the output clock. A duty cycle of 0%, 25%, 50%, or 75%

can be selected for all clock rates when the DIV value is not 0b000. When DIV=0b000 then the duty

cycle defaults to 50% for all values of DC except 0b00 in which case the duty cycle is 0% (constant low

output).

The duty cycle can be changed while the module is enabled. However, in order to prevent glitches on the

output, the DC bits should only be changed when the module is disabled (EN = 0).

Important: The DC value at reset is 10. This makes the default duty cycle 50% and not 0%.

5.4 Operation in Sleep Mode

The reference clock module continues to operate and provide a signal output in Sleep for all clock source

selections except FOSC (CLK=0).

PIC18F26/45/46Q10

Reference Clock Output Module

5.5 Register Summary: Reference CLK

Address Name Bit Pos.

0x0F39 CLKRCON 7:0 EN DC[1:0] DIV[2:0]

0x0F3A CLKRCLK 7:0 CLK[3:0]

5.6 Register Definitions: Reference Clock

Long bit name prefixes for the Reference Clock peripherals are shown in the following table. Refer to the

"Long Bit Names" section for more information.

Table 5-2. TABLE 5-1:

Peripheral Bit Name Prefix

CLKR CLKR

Related Links

1.4.2.2 Long Bit Names

PIC18F26/45/46Q10

Reference Clock Output Module

5.6.1 CLKRCON

Name: CLKRCON

Address: 0xF39

Reference Clock Control Register

Bit 7 6 5 4 3 2 1 0

EN DC[1:0] DIV[2:0]

Access R/W R/W R/W R/W R/W R/W

Reset 0 1 0 0 0 0

Bit 7 – EN

Reference Clock Module Enable bit

Value Description

1Reference clock module enabled

0Reference clock module is disabled

Bits 4:3 – DC[1:0]

Reference Clock Duty Cycle bits(1)

Value Description

11 Clock outputs duty cycle of 75%

10 Clock outputs duty cycle of 50%

01 Clock outputs duty cycle of 25%

00 Clock outputs duty cycle of 0%

Bits 2:0 – DIV[2:0]

Reference Clock Divider bits

Value Description

111 Base clock value divided by 128

110 Base clock value divided by 64

101 Base clock value divided by 32

100 Base clock value divided by 16

011 Base clock value divided by 8

010 Base clock value divided by 4

001 Base clock value divided by 2

000 Base clock value

Note:

1. Bits are valid for reference clock divider values of two or larger, the base clock cannot be further

divided.

PIC18F26/45/46Q10

Reference Clock Output Module

5.6.2 CLKRCLK

Name: CLKRCLK

Address: 0xF3A

Clock Reference Clock Selection MUX

Bit 7 6 5 4 3 2 1 0

CLK[3:0]

Access R/W R/W R/W R/W

Reset 0 0 0 0

Bits 3:0 – CLK[3:0] CLKR Clock Selection bits

See the Clock Sources table.

PIC18F26/45/46Q10

Reference Clock Output Module

6. Power-Saving Operation Modes

The purpose of the Power-Down modes is to reduce power consumption. There are three Power-Down

modes:

• Doze mode

• Sleep mode

• Idle mode

6.1 Doze Mode

Doze mode allows for power-saving by reducing CPU operation and program memory (PFM) access,

without affecting peripheral operation. Doze mode differs from Sleep mode because the band gap and

system oscillators continue to operate, while only the CPU and PFM are affected. The reduced execution

saves power by eliminating unnecessary operations within the CPU and memory.

When the Doze Enable bit is set (DOZEN = 1), the CPU executes only one instruction cycle out of every

N cycles as defined by the DOZE bits. For example, if DOZE = 001, the instruction cycle ratio is 1:4. The

CPU and memory execute for one instruction cycle and then lay idle for three instruction cycles. During

the unused cycles, the peripherals continue to operate at the system clock speed.

6.1.1 Doze Operation

The Doze operation is illustrated in Figure 6-1 . For this example:

• Doze enabled (DOZEN = 1)

•DOZE = 001 (1:4) ratio

• Recover-on-Interrupt enabled (ROI = 1)

As with normal operation, the PFM fetches for the next instruction cycle. The Q-clocks to the peripherals

continue throughout.

Figure 6-1. DOZE MODE OPERATION EXAMPLE (DOZE<2:0> = 001, 1:4)

Rev. 3000089A

4/11/2017

6.1.2 Interrupts During Doze

If an interrupt occurs and the Recover-On-Interrupt bit is clear (ROI = 0) at the time of the interrupt, the

Interrupt Service Routine (ISR) continues to execute at the rate selected by DOZE<2:0>. Interrupt latency

is extended by the DOZE<2:0> ratio.

If an interrupt occurs and the ROI bit is set (ROI = 1) at the time of the interrupt, the DOZEN bit is cleared

and the CPU executes at full speed. The prefetched instruction is executed and then the interrupt vector

PIC18F26/45/46Q10

Power-Saving Operation Modes

sequence is executed. In Figure 6-1, the interrupt occurs during the 2nd instruction cycle of the Doze

period, and immediately brings the CPU out of Doze. If the Doze-On-Exit (DOE) bit is set (DOE = 1) when

the RETFIE operation is executed, DOZEN is set, and the CPU executes at the reduced rate based on

the DOZE<2:0> ratio.

Figure 6-2. Doze Software Example

//Mainline operation

bool somethingToDo = FALSE:

void main()

{

initializeSystem();

// DOZE = 64:1 (for example)

// ROI = 1;

GIE = 1; // enable interrupts

while (1)

{

// If ADC completed, process data

if (somethingToDo)

{

doSomething();

DOZEN = 1; // resume low-power

}

// Data interrupt handler

void interrupt()

{

// DOZEN = 0 because ROI = 1

if (ADIF)

{

somethingToDo = TRUE;

DOE = 0; // make main() go fast

ADIF = 0;

}

// else check other interrupts...

if (TMR0IF)

{

timerTick++;

DOE = 1; // make main() go slow

TMR0IF = 0;

}

6.2 Sleep Mode

Sleep mode is entered by executing the SLEEP instruction, while the Idle Enable (IDLEN) bit of the

CPUDOZE register is clear (IDLEN = 0).

Upon entering Sleep mode, the following conditions exist:

1. WDT will be cleared but keeps running if enabled for operation during Sleep

2. The PD bit of the STATUS register is cleared

3. The TO bit of the STATUS register is set

4. The CPU clock is disabled

5. LFINTOSC, SOSC, HFINTOSC and ADCRC are unaffected and peripherals using them may

continue operation in Sleep.

6. I/O ports maintain the status they had before Sleep was executed (driving high, low, or high-

impedance)

7. Resets other than WDT are not affected by Sleep mode

Refer to individual chapters for more details on peripheral operation during Sleep.

PIC18F26/45/46Q10

Power-Saving Operation Modes

To minimize current consumption, the following conditions should be considered:

• I/O pins should not be floating

• External circuitry sinking current from I/O pins

• Internal circuitry sourcing current from I/O pins

• Current draw from pins with internal weak pull-ups

• Modules using any oscillator

I/O pins that are high-impedance inputs should be pulled to VDD or VSS externally to avoid switching

currents caused by floating inputs.

Examples of internal circuitry that might be sourcing current include modules such as the DAC and FVR

modules.

Related Links

31. (DAC) 5-Bit Digital-to-Analog Converter Module

29. (FVR) Fixed Voltage Reference

6.2.1 Wake-up from Sleep

The device can wake-up from Sleep through one of the following events:

1. External Reset input on MCLR pin, if enabled

2. BOR Reset, if enabled

3. Low-Power Brown-Out Reset (LPBOR), if enabled

4. POR Reset

5. Windowed Watchdog Timer, if enabled

6. All interrupt sources except clock switch interrupt can wake-up the part.

The first five events will cause a device Reset. The last one event is considered a continuation of

program execution. To determine whether a device Reset or wake-up event occurred, refer to the

"Determining the Cause of a Reset" section.

When the SLEEP instruction is being executed, the next instruction (PC + 2) is prefetched. For the device

to wake-up through an interrupt event, the corresponding Interrupt Enable bit must be enabled, as well as

the Peripheral Interrupt Enable bit (PEIE = 1), for every interrupt not in PIR0. Wake-up will occur

regardless of the state of the GIE bit. If the GIE bit is disabled, the device continues execution at the

instruction after the SLEEP instruction. If the GIE bit is enabled, the device executes the instruction after

the SLEEP instruction, the device will then call the Interrupt Service Routine. In cases where the

execution of the instruction following SLEEP is not desirable, the user should have a NOP after the SLEEP

instruction.

The WDT is cleared when the device wakes-up from Sleep, regardless of the source of wake-up.

Upon a wake from a Sleep event, the core will wait for a combination of three conditions before beginning

execution. The conditions are:

• PFM Ready

• COSC-Selected Oscillator Ready

• BOR Ready (unless BOR is disabled)

Related Links

8.11 Determining the Cause of a Reset

PIC18F26/45/46Q10

Power-Saving Operation Modes

6.2.2 Wake-up Using Interrupts

When global interrupts are disabled (GIE cleared) and any interrupt source, with the exception of the

clock switch interrupt, has both its interrupt enable bit and interrupt flag bit set, one of the following will

occur:

• If the interrupt occurs before the execution of a SLEEP instruction

–SLEEP instruction will execute as a NOP

– WDT and WDT prescaler will not be cleared

–TO bit of the STATUS register will not be set

– PD bit of the STATUS register will not be cleared

• If the interrupt occurs during or after the execution of a SLEEP instruction

–SLEEP instruction will be completely executed

– Device will immediately wake-up from Sleep

– WDT and WDT prescaler will be cleared

– TO bit of the STATUS register will be set

– PD bit of the STATUS register will be cleared

Even if the flag bits were checked before executing a SLEEP instruction, it may be possible for flag bits to

become set before the SLEEP instruction completes. To determine whether a SLEEP instruction executed,

test the PD bit. If the PD bit is set, the SLEEP instruction was executed as a NOP.

Figure 6-3. WAKE-UP FROM SLEEP THROUGH INTERRUPT



CLKIN(1)

CLKOUT(2)

Interrupt flag

GIE bit

(INTCON reg.)

Instruction Flow

PC

Instruction

Fetched

Instruction

Executed

PC PC + 1 PC + 2

Inst(PC) = Sleep

Inst(PC - 1)

Inst(PC + 1)

Sleep

Processor in

Sleep

Interrupt Latency(4)

Inst(PC + 2)

Inst(PC + 1)

Inst(0004h) Inst(0005h)

Inst(0004h)

Forced NOP

PC + 2 0004h 0005h

Forced NOP

TOST(3)

PC + 2

Rev. 3000090A

4/12/2017

Note:

1. External clock. High, Medium, Low mode assumed.

2. CLKOUT is shown here for timing reference.

3. TOST = 1024 TOSC. This delay does not apply to EC and INTOSC Oscillator modes.

4. GIE = 1 assumed. In this case after wake-up, the processor calls the ISR at 0004h. If GIE = 0,

execution will continue in-line.

6.2.3 Low-Power Sleep Mode

The PIC18F26/45/465Q10 device family contains an internal Low Dropout (LDO) voltage regulator, which

allows the device I/O pins to operate at voltages up to 5.5V while the internal device logic operates at a

lower voltage. The LDO and its associated reference circuitry must remain active when the device is in

Sleep mode.

PIC18F26/45/46Q10

Power-Saving Operation Modes

The PIC18F26/45/465Q10devices allows the user to optimize the operating current in Sleep, depending

on the application requirements.

Low-Power Sleep mode can be selected by setting the VREGPM bit of the VREGCON register.

6.2.3.1 Sleep Current vs. Wake-up Time

In the default operating mode, the LDO and reference circuitry remain in the normal configuration while in

Sleep. The device is able to exit Sleep mode quickly since all circuits remain active. In Low-Power Sleep

mode, when waking-up from Sleep, an extra delay time is required for these circuits to return to the

normal configuration and stabilize.

The Low-Power Sleep mode is beneficial for applications that stay in Sleep mode for long periods of time.

The Normal mode is beneficial for applications that need to wake from Sleep quickly and frequently.

6.2.3.2 Peripheral Usage in Sleep

Some peripherals that can operate in Sleep mode will not operate properly with the Low-Power Sleep

mode selected. The Low-Power Sleep mode is intended for use with these peripherals:

• Brown-out Reset (BOR)

• Windowed Watchdog Timer (WWDT)

• External interrupt pin/Interrupt-On-Change pins

• Peripherals that run off external secondary clock source

It is the responsibility of the end user to determine what is acceptable for their application when setting

the VREGPM settings in order to ensure operation in Sleep.

6.3 Idle Mode

When IDLEN is set (IDLEN = 1), the SLEEP instruction will put the device into Idle mode. In Idle mode,

the CPU and memory operations are halted, but the peripheral clocks continue to run. This mode is

similar to Doze mode, except that in IDLE both the CPU and PFM are shut off.

Important: If CLKOUTEN is enabled (CLKOUTEN = 0, Configuration Word 1H), the output will

continue operating while in Idle.

6.3.1 Idle and Interrupts

IDLE mode ends when an interrupt occurs (even if GIE = 0), but IDLEN is not changed. The device can

re-enter IDLE by executing the SLEEP instruction.

If Recover-on-Interrupt is enabled (ROI = 1), the interrupt that brings the device out of Idle also restores

full-speed CPU execution when doze is also enabled.

6.3.2 Idle and WWDT

When in Idle, the WWDT Reset is blocked and will instead wake the device. The WWDT wake-up is not

an interrupt, therefore ROI does not apply.

Important: The WWDT can bring the device out of Idle, in the same way it brings the device

out of Sleep. The DOZEN bit is not affected.

PIC18F26/45/46Q10

Power-Saving Operation Modes

6.4 Peripheral Operation in Power-Saving Modes

All selected clock sources and the peripherals running off them are active in both IDLE and DOZE mode.

Only in Sleep mode, both the FOSC and FOSC/4 clocks are unavailable. All the other clock sources are

active, if enabled manually or through peripheral clock selection before the part enters Sleep.

PIC18F26/45/46Q10

Power-Saving Operation Modes

6.5 Register Summary - Power Savings Control

Address Name Bit Pos.

0x0ED2 CPUDOZE 7:0 IDLEN DOZEN ROI DOE DOZE[2:0]

0x0ED3

...

0x0ED9

Reserved

0x0EDA VREGCON 7:0 PMSYS[1:0] VREGPM[1:0]

6.6 Register Definitions: Power Savings Control

PIC18F26/45/46Q10

Power-Saving Operation Modes

6.6.1 VREGCON

Name: VREGCON

Address: 0xEDA

Note:

1. System and peripheral inputs should not exceed 500 kHz in ULP mode.

Voltage Regulator Control Register

Bit 7 6 5 4 3 2 1 0

PMSYS[1:0] VREGPM[1:0]

Access RO RO R/W R/W

Reset g g 1 0

Bits 5:4 – PMSYS[1:0] System Power Mode Status bits

Value Description

11 Reserved

10 ULP regulator is active

01 Main regulator in LP mode is active

00 Main regulator in HP mode is active

Bits 1:0 – VREGPM[1:0] Voltage Regulator Power Mode Selection bit

Value Description

11 Reserved. Do not use.

10 ULP regulator(1)

01 Main regulator in LP mode

00 Main regulator in HP mode

PIC18F26/45/46Q10

Power-Saving Operation Modes

6.6.2 CPUDOZE

Name: CPUDOZE

Address: 0xED2

Doze and Idle Register

Bit 7 6 5 4 3 2 1 0

IDLEN DOZEN ROI DOE DOZE[2:0]

Access R/W R/W/HC/HS R/W R/W R/W R/W R/W

Reset 0 0 0 0 0 0 0

Bit 7 – IDLEN Idle Enable bit

Reset States: POR/BOR = 0

All Other Resets = u

Value Description

1A SLEEP instruction inhibits the CPU clock, but not the peripheral clock(s)

0A SLEEP instruction places the device into full Sleep mode

Bit 6 – DOZEN

Doze Enable bit(1)

Value Description

1The CPU executes instruction cycles according to DOZE setting

0The CPU executes all instruction cycles (fastest, highest power operation)

Bit 5 – ROI Recover-On-Interrupt bit

Value Description

1Entering the Interrupt Service Routine (ISR) makes DOZEN = 0, bringing the CPU to full-

speed operation

0Interrupt entry does not change DOZEN

Bit 4 – DOE Doze-On-Exit bit

Value Description

1Executing RETFIE makes DOZEN = 1, bringing the CPU to reduced speed operation

0RETFIE does not change DOZEN

Bits 2:0 – DOZE[2:0] Ratio of CPU Instruction Cycles to Peripheral Instruction Cycles

Value Description

111 1:256

110 1:128

101 1:64

100 1:32

011 1:16

010 1:8

001 1:4

000 1:2

Note:

1. When ROI = 1 or DOE = 1, DOZEN is changed by hardware interrupt entry and/or exit.

PIC18F26/45/46Q10

Power-Saving Operation Modes

7. (PMD) Peripheral Module Disable

This module provides the ability to selectively enable or disable a peripheral. Disabling a peripheral

places it in its lowest possible power state. The user can disable unused modules to reduce the overall

power consumption.

The PIC18F26/45/46Q10 devices address this requirement by allowing peripheral modules to be

selectively enabled or disabled. Disabling a peripheral places it in the lowest possible power mode.

Important: All modules are ON by default following any system Reset.

7.1 Disabling a Module

A peripheral can be disabled by setting the corresponding peripheral disable bit in the PMDx register.

Disabling a module has the following effects:

• The module is held in Reset and does not function.

• All the SFRs pertaining to that peripheral become “unimplemented”

– Writing is disabled

– Reading returns 0x00

• Module outputs are disabled

Related Links

15.1 I/O Priorities

7.2 Enabling a Module

Clearing the corresponding module disable bit in the PMDx register, re-enables the module and the SFRs

will reflect the Power-on Reset values.

Important: There should be no reads/writes to the module SFRs for at least two instruction

cycles after it has been re-enabled.

PIC18F26/45/46Q10

(PMD) Peripheral Module Disable

7.3 Register Summary - PMD

Address Name Bit Pos.

0x0EDC PMD0 7:0 SYSCMD FVRMD HLVDMD CRCMD SCANMD NVMMD CLKRMD IOCMD

0x0EDD PMD1 7:0 TMR6MD TMR5MD TMR4MD TMR3MD TMR2MD TMR1MD TMR0MD

0x0EDE PMD2 7:0 DACMD ADCMD CMP2MD CMP1MD ZCDMD

0x0EDF PMD3 7:0 CLC8MD CLC7MD CLC6MD CLC5MD PWM4MD PWM3MD CCP2MD CCP1MD

0x0EE0 PMD4 7:0 UART2MD UART1MD MSSP2MD MSSP1MD CWG1MD

0x0EE1 PMD5 7:0 CLC4MD CLC3MD CLC2MD CLC1MD DSMMD

7.4 Register Definitions: Peripheral Module Disable

PIC18F26/45/46Q10

(PMD) Peripheral Module Disable

7.4.1 PMD0

Name: PMD0

Address: 0xEDC

PMD Control Register 0

Bit 7 6 5 4 3 2 1 0

SYSCMD FVRMD HLVDMD CRCMD SCANMD NVMMD CLKRMD IOCMD

Access R/W R/W R/W R/W R/W R/W R/W R/W

Reset 0 0 0 0 0 0 0 0

Bit 7 – SYSCMD Disable Peripheral System Clock Network bit

Disables the System clock network(1)

Value Description

1System clock network disabled (FOSC)

0System clock network enabled

Bit 6 – FVRMD Disable Fixed Voltage Reference bit

Value Description

1FVR module disabled

0FVR module enabled

Bit 5 – HLVDMD Disable High-Low-Voltage Detect bit

Value Description

1HLVD module disabled

0HLVD module enabled

Bit 4 – CRCMD Disable CRC Engine bit

Value Description

1CRC module disabled

0CRC module enabled

Bit 3 – SCANMD Disable NVM Memory Scanner bit

Disables the Scanner module(2)

Value Description

1NVM Memory Scan module disabled

0NVM Memory Scan module enabled

Bit 2 – NVMMD NVM Module Disable bit

Disables the NVM module(3)

Value Description

1All Memory reading and writing is disabled; NVMCON registers cannot be written

0NVM module enabled

Bit 1 – CLKRMD Disable Clock Reference bit

Value Description

1CLKR module disabled

0CLKR module enabled

PIC18F26/45/46Q10

(PMD) Peripheral Module Disable

Bit 0 – IOCMD Disable Interrupt-on-Change bit, All Ports

Value Description

1IOC module(s) disabled

0IOC module(s) enabled

Note:

1. Clearing the SYSCMD bit disables the system clock (FOSC) to peripherals, however peripherals

clocked by FOSC/4 are not affected.

2. Subject to SCANE bit in Configuration Word 4.

3. When enabling NVM, a delay of up to 1 µs is required before accessing data.

Related Links

3.7.4 CONFIG4

PIC18F26/45/46Q10

(PMD) Peripheral Module Disable

7.4.2 PMD1

Name: PMD1

Address: 0xEDD

PMD Control Register 1

Bit 7 6 5 4 3 2 1 0

TMR6MD TMR5MD TMR4MD TMR3MD TMR2MD TMR1MD TMR0MD

Access R/W R/W R/W R/W R/W R/W R/W

Reset 0 0 0 0 0 0 0

Bits 0, 1, 2, 3, 4, 5, 6 – TMRnMD Disable Timer n bit

Value Description

1TMRn module disabled

0TMRn module enabled

PIC18F26/45/46Q10

(PMD) Peripheral Module Disable

7.4.3 PMD2

Name: PMD2

Address: 0xEDE

PMD Control Register 2

Bit 7 6 5 4 3 2 1 0

DACMD ADCMD CMP2MD CMP1MD ZCDMD

Access R/W R/W R/W R/W R/W

Reset 0 0 0 0 0

Bit 6 – DACMD Disable DAC bit

Value Description

1DAC module disabled

0DAC module enabled

Bit 5 – ADCMD Disable ADC bit

Value Description

1ADC module disabled

0ADC module enabled

Bits 1, 2 – CMPnMD Disable Comparator CMPn bit

Value Description

1CMPn module disabled

0CMPn module enabled

Bit 0 – ZCDMD Disable Zero-Cross Detect module bit(1)

Value Description

1ZCD module disabled

0ZCD module enabled

Note:

1. Subject to ZCD bit in Configuration Word 2.

Related Links

3.7.2 CONFIG2

PIC18F26/45/46Q10

(PMD) Peripheral Module Disable

7.4.4 PMD3

Name: PMD3

Address: 0xEDF

PMD Control Register 3

Bit 7 6 5 4 3 2 1 0

CLC8MD CLC7MD CLC6MD CLC5MD PWM4MD PWM3MD CCP2MD CCP1MD

Access R/W R/W R/W R/W R/W R/W R/W R/W

Reset 0 0 0 0 0 0 0 0

Bits 4, 5, 6, 7 – CLCnMD Disable CLCn bit

Value Description

1CLCn module disabled

0CLCn module enabled

Bits 2, 3 – PWMnMD Disable PWMn bit

Value Description

1PWMn module disabled

0PWMn module enabled

Bits 0, 1 – CCPnMD Disable Capture/Compare/PWMn bit

Value Description

1CCPn module disabled

0CCPn module enabled

PIC18F26/45/46Q10

(PMD) Peripheral Module Disable

7.4.5 PMD4

Name: PMD4

Address: 0xEE0

PMD Control Register 4

Bit 7 6 5 4 3 2 1 0

UART2MD UART1MD MSSP2MD MSSP1MD CWG1MD

Access R/W R/W R/W R/W R/W

Reset 0 0 0 0 0

Bits 6, 7 – UARTnMD Disable EUSARTn bit

Value Description

1EUSARTn module disabled

0EUSARTn module enabled

Bits 4, 5 – MSSPnMD Disable MSSPn bit

Value Description

1MSSPn module disabled

0MSSPn module enabled

Bit 0 – CWG1MD Disable CWG1 Module bit

Value Description

1CWG1 module disabled

0CWG1 module enabled

PIC18F26/45/46Q10

(PMD) Peripheral Module Disable

7.4.6 PMD5

Name: PMD5

Address: 0xEE1

PMD Control Register 5

Bit 7 6 5 4 3 2 1 0

CLC4MD CLC3MD CLC2MD CLC1MD DSMMD

Access R/W R/W R/W R/W R/W

Reset 0 0 0 0 0

Bits 4, 5, 6, 7 – CLCnMD Disable CLCn bit

Value Description

1CLCn module disabled

0CLCn module enabled

Bit 0 – DSMMD Disable DSM bit

Value Description

1DSM module disabled

0DSM module enabled

PIC18F26/45/46Q10

(PMD) Peripheral Module Disable

8. Resets

There are multiple ways to reset this device:

• Power-on Reset (POR)

• Brown-out Reset (BOR)

• Low-Power Brown-out Reset (LPBOR)

• MCLR Reset

• WDT Reset

•RESET instruction

• Stack Overflow

• Stack Underflow

• Programming mode exit

To allow VDD to stabilize, an optional Power-up Timer can be enabled to extend the Reset time after a

BOR or POR event.

A simplified block diagram of the On-Chip Reset Circuit is shown in the block diagram below.

Figure 8-1. Simplified Block Diagram of On-Chip Reset Circuit

Filename: 10-000006E.vsd

Title: Simplified block diagram for RESET module

Last Edit: 5/11/2016

First Used: PIC18(L)F2x/4x/6xK40 (MVAF,MVAE,MVAB,MVAC,MVAK)

Note: 1. See Table 8-1 for BOR active conditions

Device

Reset

Power-on

Reset

WWDT Time-out/

Window voilation

Brown-out

Reset(1)

LPBOR

Reset

RESET Instruction

MCLRE

PWRTE

LFINTOSC

VDD

ICSP™ Programming Mode Exit

Stack Underflow

Stack Overflow

RPower-up

Timer

Rev. 10-000006E

5/11/2016

VPP/MCLR

Note: See “BOR Operating Conditions” table for BOR active conditions.

8.1 Power-on Reset (POR)

The POR circuit holds the device in Reset until VDD has reached an acceptable level for minimum

operation. Slow rising VDD, fast operating speeds or analog performance may require greater than

minimum VDD. The PWRT, BOR or MCLR features can be used to extend the start-up period until all

device operation conditions have been met.

PIC18F26/45/46Q10

Resets

8.2 Brown-out Reset (BOR)

The BOR circuit holds the device in Reset when VDD reaches a selectable minimum level. Between the

POR and BOR, complete voltage range coverage for execution protection can be implemented.

The Brown-out Reset module has four operating modes controlled by the BOREN<1:0> bits in

Configuration Words. The four operating modes are:

• BOR is always on

• BOR is off when in Sleep

• BOR is controlled by software

• BOR is always off

Refer to “BOR Operating Conditions” table for more information.

The Brown-out Reset voltage level is selectable by configuring the BORV<1:0> bits in Configuration

Words.

A VDD noise rejection filter prevents the BOR from triggering on small events. If VDD falls below VBOR for a

duration greater than parameter TBORDC, the device will reset.

Related Links

3.7.2 CONFIG2

39.4.5 Reset, WDT, Oscillator Start-up Timer, Power-up Timer, Brown-Out Reset and Low-Power Brown-

Out Reset Specifications

8.2.1 BOR is Always On

When the BOREN bits of Configuration Words are programmed to ‘11’, the BOR is always on. The device

start-up will be delayed until the BOR is ready and VDD is higher than the BOR threshold.

BOR protection is active during Sleep. The BOR does not delay wake-up from Sleep.

8.2.2 BOR is OFF in Sleep

When the BOREN bits of Configuration Words are programmed to ‘10’, the BOR is on, except in Sleep.

The device start-up will be delayed until the BOR is ready and VDD is higher than the BOR threshold.

BOR protection is not active during Sleep. The device wake-up will be delayed until the BOR is ready.

8.2.3 BOR Controlled by Software

When the BOREN bits of Configuration Words are programmed to ‘01’, the BOR is controlled by the

SBOREN bit. The device start-up is not delayed by the BOR ready condition or the VDD level.

BOR protection begins as soon as the BOR circuit is ready. The status of the BOR circuit is reflected in

the BORRDY bit.

BOR protection is unchanged by Sleep.

Table 8-1. BOR Operating Modes

BOREN<1:0> SBOREN Device

Mode BOR Mode

Instruction Execution upon:

Release of POR Wake-up from Sleep

11 X X Active Wait for release of BOR

(BORRDY = 1)Begins immediately

PIC18F26/45/46Q10

Resets

...........continued

BOREN<1:0> SBOREN Device

Mode BOR Mode

Instruction Execution upon:

Release of POR Wake-up from Sleep

10 X

Awake Active Wait for release of BOR

(BORRDY = 1)N/A

Sleep Hibernate N/A Wait for release of

BOR (BORRDY = 1)

01

1 X Active Wait for release of BOR

(BORRDY = 1)Begins immediately

0 X Hibernate

00 X X Disabled Begins immediately

Note:

1. In this specific case, “Release of POR” and “Wake-up from Sleep”, there is no delay in start-up. The

BOR ready flag, (BORRDY = 1), will be set before the CPU is ready to execute instructions

because the BOR circuit is forced on by the BOREN<1:0> bits

Figure 8-2. Brown-out Situations

TPWRT(1)

VBOR

VDD

Internal

Reset

VBOR

VDD

Internal

Reset TPWRT(1)

< TPWRT

TPWRT(1)

VBOR

VDD

Internal

Reset

Rev. 30-000092A

4/12/2017

Note: TPWRT delay only if PWRTE bit is programmed to ‘0’.

8.2.4 BOR and Bulk Erase

BOR is forced ON during PFM Bulk Erase operations to make sure that the system code protection

cannot be compromised by reducing VDD.

During Bulk Erase, the BOR is enabled at 1.9V, even if it is configured to some other value. If VDD falls,

the erase cycle will be aborted, but the device will not be reset.

PIC18F26/45/46Q10

Resets

8.3 Low-Power Brown-out Reset (LPBOR)

The Low-Power Brown-out Reset (LPBOR) provides an additional BOR circuit for low-power operation.

Refer to the figure below to see how the BOR interacts with other modules.

The LPBOR is used to monitor the external VDD pin. When too low of a voltage is detected, the device is

held in Reset.

Figure 8-3. LPBOR, BOR, POR Relationship

Reset

POR

logic

LPBOR

To PCON

indicator bit

BOR

BOR Event

REARM POR

Event

POR Event LPBOR Event

Any Reset

Rev. 30-000091B

6/21/2017

8.3.1 Enabling LPBOR

The LPBOR is controlled by the LPBOREN bit of Configuration Word 2. When the device is erased, the

LPBOR module defaults to disabled.

Related Links

3.7.2 CONFIG2

8.3.1.1 LPBOR Module Output

The output of the LPBOR module is a signal indicating whether or not a Reset is to be asserted. This

signal is OR’d together with the Reset signal of the BOR module to provide the generic BOR signal,

which goes to the PCON0 register and to the power control block.

8.4 MCLR Reset

The MCLR is an optional external input that can reset the device. The MCLR function is controlled by the

MCLRE bit of Configuration Words and the LVP bit of Configuration Words (see table below). The

RMCLR bit in the PCON0 register will be set to ‘0’ if a MCLR has occurred.

Table 8-2. MCLR Configuration

MCLRE LVP MCLR

x 1 Enabled

PIC18F26/45/46Q10

Resets

...........continued

MCLRE LVP MCLR

1 0 Enabled

0 0 Disabled

8.4.1 MCLR Enabled

When MCLR is enabled and the pin is held low, the device is held in Reset. The MCLR pin is connected

to VDD through an internal weak pull-up.

The device has a noise filter in the MCLR Reset path. The filter will detect and ignore small pulses.

Important: An internal Reset event (RESET instruction, BOR, WWDT, POR, STKOVF,

STKUNF) does not drive the MCLR pin low.

8.4.2 MCLR Disabled

When MCLR is disabled, the MCLR becomes input-only and pin functions such as internal weak pull-ups

are under software control.

Related Links

15.1 I/O Priorities

8.5 Windowed Watchdog Timer (WWDT) Reset

The Windowed Watchdog Timer generates a Reset if the firmware does not issue a CLRWDT instruction

within the time-out period or window set. The TO and PD bits in the STATUS register and the RWDT bit

are changed to indicate a WDT Reset. The WDTWV bit indicates if the WDT Reset has occurred due to a

time-out or a window violation.

Related Links

10.8.5 STATUS

9. (WWDT) Windowed Watchdog Timer

8.6 RESET Instruction

A RESET instruction will cause a device Reset. The RI bit will be set to ‘0’. See Table 8-3 for default

conditions after a RESET instruction has occurred.

8.7 Stack Overflow/Underflow Reset

The device can reset when the Stack Overflows or Underflows. The STKOVF or STKUNF bits register

indicate the Reset condition. These Resets are enabled by setting the STVREN bit in Configuration

Words.

Related Links

3.7.2 CONFIG2

10.1.2.3 Stack Overflow and Underflow Resets

PIC18F26/45/46Q10

Resets

8.8 Programming Mode Exit

Upon exit of Programming mode, the device will behave as if a POR had just occurred.

8.9 Power-up Timer (PWRT)

The Power-up Timer provides a nominal 66 ms (2048 cycles of LFINTOSC) time-out on POR or Brown-

out Reset.

The device is held in Reset as long as PWRT is active. The PWRT delay allows additional time for the

VDD to rise to an acceptable level. The Power-up Timer is enabled by clearing the PWRTE bit in

Configuration Words.

The Power-up Timer starts after the release of the POR and BOR.

For additional information, refer to Application Note AN607, “Power-up Trouble Shooting” (DS00000607).

8.10 Start-up Sequence

Upon the release of a POR or BOR, the following must occur before the device will begin executing:

1. Power-up Timer runs to completion (if enabled).

2. Oscillator Start-up Timer runs to completion (if required for selected oscillator source).

3. MCLR must be released (if enabled).

The total time-out will vary based on oscillator configuration and Power-up Timer configuration.

The Power-up Timer and Oscillator Start-up Timer run independently of MCLR Reset. If MCLR is kept low

long enough, the Power-up Timer and Oscillator Start-up Timer will expire. Upon bringing MCLR high, the

device will begin execution after 10 FOSC cycles (see figure below). This is useful for testing purposes or

to synchronize more than one device operating in parallel.

PIC18F26/45/46Q10

Resets

Figure 8-4. Reset Start-up Sequence

TOST

TMCLR

TPWRT

VDD

Internal POR

Power-up Timer

MCLR

Internal RESET

Oscillator Modes

Oscillator Start-up Timer

Oscillator

FOSC

Internal Oscillator

Oscillator

FOSC

External Clock (EC)

CLKIN

FOSC

External Crystal

Rev. 30-000093A

4/12/2017

Related Links

4. Oscillator Module (with Fail-Safe Clock Monitor)

8.11 Determining the Cause of a Reset

Upon any Reset, multiple bits in the STATUS and PCON0 registers are updated to indicate the cause of

the Reset. The following table shows the Reset conditions of these registers.

Table 8-3. Reset Condition for Special Registers

Condition Program

Counter

STATUS

Register(2,3)

PCON0

Register

PCON1

Register

Power-on Reset 0 -110 0000 0011 110x ---- -1-1

Brown-out Reset 0 -110 0000 0011 11u0 ---- -u-u

MCLR Reset

during normal

operation

0-uuu uuuu uuuu 0uuu uuuu-u-u

MCLR Reset

during Sleep

0-10u uuuu uuuu 0uuu uuuu-u-u

PIC18F26/45/46Q10

Resets

...........continued

Condition Program

Counter

STATUS

Register(2,3)

PCON0

Register

PCON1

Register

WDT Time-out

Reset

0-0uu uuuu uuu0 uuuu uuuu-u-u

WDT Wake-up

from Sleep

PC + 2 -00u uuuu uuuu uuuu uuuu-u-u

WWDT Window

Violation Reset

0-uuu uuuu uu0u uuuu uuuu-u-u

Interrupt Wake-up

from Sleep

PC + 2(1) -10u 0uuu uuuu uuuu uuuu-u-u

RESET Instruction

Executed

0-uuu uuuu uuuu u0uu uuuu-u-u

Stack Overflow

Reset (STVREN =

1)

0-uuu uuuu 1uuu uuuu uuuu-u-u

Stack Underflow

Reset (STVREN =

1)

0-uuu uuuu u1uu uuuu uuuu-u-u

Data Protection

(Fuse Fault)

0---u uuuu uuuu uuuu ---- -u-0

VREG or ULP

Ready Fault

0---1 1000 0011 001u ---- -0-1

Legend: u = unchanged, x = unknown, — = unimplemented bit, reads as ‘0’.

Note:

1. When the wake-up is due to an interrupt and Global Interrupt Enable bit (GIE) is set, the return

address is pushed on the stack and PC is loaded with the corresponding interrupt vector

(depending on source, high or low priority) after execution of PC + 2.

2. If a Status bit is not implemented, that bit will be read as ‘0’.

3. Status bits Z, C, DC are reset by POR/BOR.

Related Links

10.8.5 STATUS

8.12 Power Control (PCON0) Register

The Power Control (PCON0) register contains flag bits to differentiate between a:

• Brown-out Reset (BOR)

• Power-on Reset (POR)

• Reset Instruction Reset (RI)

• MCLR Reset (RMCLR)

PIC18F26/45/46Q10

Resets

• Watchdog Timer Reset (RWDT)

• Watchdog Window Violation (WDTWV)

• Stack Underflow Reset (STKUNF)

• Stack Overflow Reset (STKOVF)

The Power Control register bits are shown in 8.14.2 PCON0.

Hardware will change the corresponding register bit during the Reset process; if the Reset was not

caused by the condition, the bit remains unchanged (Table 8-3).

Software should reset the bit to the Inactive state after restart (hardware will not reset the bit).

Software may also set any PCON0 bit to the Active state, so that user code may be tested, but no Reset

action will be generated.

PIC18F26/45/46Q10

Resets

8.13 Register Summary - BOR Control and Power Control

Address Name Bit Pos.

0x0EDB BORCON 7:0 SBOREN BORRDY

0x0EDC

...

0x0FD5

Reserved

0x0FD6 PCON1 7:0 RVREG RCM

0x0FD7 PCON0 7:0 STKOVF STKUNF WDTWV RWDT RMCLR RI POR BOR

8.14 Register Definitions: Power Control

PIC18F26/45/46Q10

Resets

8.14.1 BORCON

Name: BORCON

Address: 0xEDB

Brown-out Reset Control Register

Bit 7 6 5 4 3 2 1 0

SBOREN BORRDY

Access R/W R

Reset 1 q

Bit 7 – SBOREN Software Brown-out Reset Enable bit

Reset States: POR/BOR = 1

All Other Resets = u

Value Condition Description

—If BOREN≠ 01 SBOREN is read/write, but has no effect on the BOR.

1If BOREN= 01 BOR Enabled

0If BOREN= 01 BOR Disabled

Bit 0 – BORRDY Brown-out Reset Circuit Ready Status bit

Reset States: POR/BOR = q

All Other Resets = u

Value Description

1The Brown-out Reset Circuit is active and armed

0The Brown-out Reset Circuit is disabled or is warming up

Related Links

3.7.2 CONFIG2

PIC18F26/45/46Q10

Resets

8.14.2 PCON0

Name: PCON0

Address: 0xFD7

Power Control Register 0

Bit 7 6 5 4 3 2 1 0

STKOVF STKUNF WDTWV RWDT RMCLR RI POR BOR

Access R/W/HS R/W/HS R/W/HC R/W/HC R/W/HC R/W/HC R/W/HC R/W/HC

Reset 0 0 1 1 1 1 0 q

Bit 7 – STKOVF Stack Overflow Flag bit

Reset States: POR/BOR = 0

All Other Resets = q

Value Description

1A Stack Overflow occurred (more CALLs than fit on the stack)

0A Stack Overflow has not occurred or set to ‘0’ by firmware

Bit 6 – STKUNF Stack Underflow Flag bit

Reset States: POR/BOR = 0

All Other Resets = q

Value Description

1A Stack Underflow occurred (more RETURNs than CALLs)

0A Stack Underflow has not occurred or set to ‘0’ by firmware

Bit 5 – WDTWV Watchdog Window Violation Flag bit

Reset States: POR/BOR = 1

All Other Resets = q

Value Description

1A WDT window violation has not occurred or set to ‘1’ by firmware

0A CLRWDT instruction was issued when the WDT Reset window was closed (set to ‘0’ in

hardware when a WDT window violation Reset occurs)

Bit 4 – RWDT WDT Reset Flag bit

Reset States: POR/BOR = 1

All Other Resets = q

Value Description

1A WDT overflow/time-out Reset has not occurred or set to ‘1’ by firmware

0A WDT overflow/time-out Reset has occurred (set to ‘0’ in hardware when a WDT Reset

occurs)

Bit 3 – RMCLR MCLR Reset Flag bit

Reset States: POR/BOR = 1

All Other Resets = q

Value Description

1A MCLR Reset has not occurred or set to ‘1’ by firmware

0A MCLR Reset has occurred (set to ‘0’ in hardware when a MCLR Reset occurs)

PIC18F26/45/46Q10

Resets

Bit 2 – RI RESET Instruction Flag bit

Reset States: POR/BOR = 1

All Other Resets = q

Value Description

1A RESET instruction has not been executed or set to ‘1’ by firmware

0A RESET instruction has been executed (set to ‘0’ in hardware upon executing a RESET

instruction)

Bit 1 – POR Power-on Reset Status bit

Reset States: POR/BOR = 0

All Other Resets = u

Value Description

1No Power-on Reset occurred or set to ‘1’ by firmware

0A Power-on Reset occurred (set to ‘0’ in hardware when a Power-on Reset occurs)

Bit 0 – BOR Brown-out Reset Status bit

Reset States: POR/BOR = q

All Other Resets = u

Value Description

1No Brown-out Reset occurred or set to ‘1’ by firmware

0A Brown-out Reset occurred (set to ‘0’ in hardware when a Brown-out Reset occurs)

PIC18F26/45/46Q10

Resets

8.14.3 PCON1

Name: PCON1

Address: 0xFD6

Power Control Register 1

Bit 7 6 5 4 3 2 1 0

RVREG RCM

Access R/W/HC R/W/HC

Reset 1 1

Bit 2 – RVREG Main LDO Voltage Regulator Reset Flag bit

Reset States: POR/BOR = 1

All Other Resets = q

Value Description

1No LDO or ULP “ready” Reset has occured; or set to ‘1’ by firmware

0LDO or ULP “ready” Reset has occurred (VDDCORE reached its minimum spec)

Bit 0 – RCM Configuration Memory Reset Flag bit

Reset States: POR/BOR = 1

All Other Resets = q

Value Description

1A Reset occurred due to corruption of the configuration and/or calibration data latches

0The configuration and calibration latches have not been corrupted

PIC18F26/45/46Q10

Resets

9. (WWDT) Windowed Watchdog Timer

The Watchdog Timer (WDT) is a system timer that generates a Reset if the firmware does not issue a

CLRWDT instruction within the time-out period. The Watchdog Timer is typically used to recover the

system from unexpected events. The Windowed Watchdog Timer (WWDT) differs in that CLRWDT

instructions are only accepted when they are performed within a specific window during the time-out

period.

The WWDT has the following features:

• Selectable clock source

• Multiple operating modes

– WWDT is always on

– WWDT is off when in Sleep

– WWDT is controlled by software

– WWDT is always off

• Configurable time-out period is from 1 ms to 256s (nominal)

• Configurable window size from 12.5% to 100% of the time-out period

• Multiple Reset conditions

PIC18F26/45/46Q10

(WWDT) Windowed Watchdog Timer

Figure 9-1. Windowed Watchdog Timer Block Diagram

Filename: 10-000162A.vsd

Title: Windowed Watchdog Timer Timer Block Diagram

Last Edit: 1/2/2014

First Used: PIC16(L)F1613 (LECQ)

Notes:

Rev. 10-000 162A

1/2/201 4

WINDOW

CLRWDT

RESET

WDT Time-out

WDT

Window

Violation

PS

5-bit

WDT Counter

Overflow

Latch

18-bit Prescale

Counter

000

011

010

001

100

101

110

111Reserved

Reserved

SOSC

MFINTOSC/16

LFINTOSC

R

CS

WWDT

Armed

Window

Sizes Comparator

Window Closed

E

WDTE<1:0> = 01

WDTE<1:0> = 11

WDTE<1:0> = 10

SEN

Sleep

9.1 Independent Clock Source

The WWDT can derive its time base from either the 31 kHz LFINTOSC or 31.25 kHz MFINTOSC internal

oscillators, depending on the value of WDTE Configuration bits.

If WDTE = 'b1x, then the clock source will be enabled depending on the WDTCCS Configuration bits.

If WDTE = 'b01, the SEN bit should be set by software to enable WWDT, and the clock source is

enabled by the WDTCS bits.

Time intervals in this chapter are based on a minimum nominal interval of 1 ms. See “Electrical

Specifications” for LFINTOSC and MFINTOSC tolerances.

PIC18F26/45/46Q10

(WWDT) Windowed Watchdog Timer

Related Links

3.7.3 CONFIG3

39.4.2 Internal Oscillator Parameters(1)

9.2 WWDT Operating Modes

The Windowed Watchdog Timer module has four operating modes controlled by the WDTE bits in

Configuration Words. See Table 9-1.

9.2.1 WWDT Is Always On

When the WDTE bits of Configuration Words are set to ‘11’, the WWDT is always on.

WWDT protection is active during Sleep.

9.2.2 WWDT Is Off in Sleep

When the WDTE bits of Configuration Words are set to ‘10’, the WWDT is on, except in Sleep.

WWDT protection is not active during Sleep.

9.2.3 WWDT Controlled by Software

When the WDTE bits of Configuration Words are set to ‘01’, the WWDT is controlled by the SEN bit.

WWDT protection is unchanged by Sleep. See the following table for more details.

Table 9-1. WWDT Operating Modes

WDTE<1:0> SEN Device Mode WWDT Mode

11 X X Active

10 X

Awake Active

Sleep Disabled

01

1X Active

0X Disabled

00 X X Disabled

9.3 Time-out Period

If the WDTCPS Configuration bits default to 0’b11111, then the WDTPS bits set the time-out period

from 1 ms to 256 seconds (nominal). If any value other than the default value is assigned to WDTCPS

Configuration bits, then the timer period will be based on the WDTCPS bits in the CONFIG3 register. After

a Reset, the default time-out period is 2s.

Related Links

3.7.3 CONFIG3

9.4 Watchdog Window

The Windowed Watchdog Timer has an optional Windowed mode that is controlled by the WDTCWS

Configuration bits and WINDOW bits. In the Windowed mode, the CLRWDT instruction must occur within

PIC18F26/45/46Q10

(WWDT) Windowed Watchdog Timer

the allowed window of the WDT period. Any CLRWDT instruction that occurs outside of this window will

trigger a window violation and will cause a WWDT Reset, similar to a WWDT time-out. See Figure 9-2 for

an example.

The window size is controlled by the WINDOW Configuration bits, or the WINDOW bits, if WDTCWS =

111.

The five Most Significant bits of the WDTTMR register are used to determine whether the window is open,

as defined by the WINDOW bits.

In the event of a window violation, a Reset will be generated and the WDTWV bit of the PCON0 register

will be cleared. This bit is set by a POR or can be set in firmware.

Related Links

8.14.2 PCON0

9.5 Clearing the WWDT

The WWDT is cleared when any of the following conditions occur:

• Any Reset

• Valid CLRWDT instruction is executed

• Device enters Sleep

• Exit Sleep by Interrupt

• WWDT is disabled

• Oscillator Start-up Timer (OST) is running

• Any write to the WDTCON0 or 9.8.2 WDTCON1 registers

9.5.1 CLRWDT Considerations (Windowed Mode)

When in Windowed mode, the WWDT must be armed before a CLRWDT instruction will clear the timer.

This is performed by reading the WDTCON0 register. Executing a CLRWDT instruction without performing

such an arming action will trigger a window violation regardless of whether the window is open or not.

See Table 9-2 for more information.

9.6 Operation During Sleep

When the device enters Sleep, the WWDT is cleared. If the WWDT is enabled during Sleep, the WWDT

resumes counting. When the device exits Sleep, the WWDT is cleared again.

The WWDT remains clear until the Oscillator Start-up Timer (OST) completes, if enabled.

When a WWDT time-out occurs while the device is in Sleep, no Reset is generated. Instead, the device

wakes up and resumes operation. The TO and PD bits in the STATUS register are changed to indicate

the event. The RWDT bit in the PCON0 register can also be used.

PIC18F26/45/46Q10

(WWDT) Windowed Watchdog Timer

Table 9-2. WWDT Clearing Conditions

Conditions WWDT

WDTE = 00

Cleared

WDTE = 01 and SEN = 0

WDTE = 10 and enter Sleep

CLRWDT Command

Oscillator Fail Detected

Exit Sleep + System Clock = SOSC, EXTRC, INTOSC, EXTCLK

Exit Sleep + System Clock = XT, HS, LP Cleared until the end of OST

Change INTOSC divider (IRCF bits) Unaffected

Figure 9-2. Window Period and Delay

Filename: 10-000163A.vsd

Title: WDT WINDOW PERIOD AND DELAY

Last Edit: 8/15/2016

First Used: PIC16(L)F1613 (LECQ)

Notes:

Rev. 10-000163A

8/15/2016

Window Period

CLRWDT Instruction

(or other WDT Reset)

Window Delay

(window violation can occur)

Window Closed Window Open

Time-out Event

Related Links

4.2.1.3 Oscillator Start-up Timer (OST)

10.8.5 STATUS

8.14.2 PCON0

10. Memory Organization

PIC18F26/45/46Q10

(WWDT) Windowed Watchdog Timer

9.7 Register Summary - WDT Control

Address Name Bit Pos.

0x0ECD WDTCON0 7:0 WDTPS[4:0] SEN

0x0ECE WDTCON1 7:0 WDTCS[2:0] WINDOW[2:0]

0x0ECF WDTPSL 7:0 PSCNTL[7:0]

0x0ED0 WDTPSH 7:0 PSCNTH[7:0]

0x0ED1 WDTTMR 7:0 WDTTMR[4:0] STATE PSCNT[1:0]

9.8 Register Definitions: Windowed Watchdog Timer Control

PIC18F26/45/46Q10

(WWDT) Windowed Watchdog Timer

9.8.1 WDTCON0

Name: WDTCON0

Address: 0xECD

Watchdog Timer Control Register 0

Bit 7 6 5 4 3 2 1 0

WDTPS[4:0] SEN

Access R/W R/W R/W R/W R/W R/W

Reset q q q q q 0

Bits 5:1 – WDTPS[4:0] Watchdog Timer Prescale Select bits(1)

Bit Value = Prescale Rate

Value Description

11111

to

10011

Reserved. Results in minimum interval (1 ms)

10010 1:8388608 (223) (Interval 256s nominal)

10001 1:4194304 (222) (Interval 128s nominal)

10000 1:2097152 (221) (Interval 64s nominal)

01111 1:1048576 (220) (Interval 32s nominal)

01110 1:524288 (219) (Interval 16s nominal)

01101 1:262144 (218) (Interval 8s nominal)

01100 1:131072 (217) (Interval 4s nominal)

01011 1:65536 (Interval 2s nominal) (Reset value)

01010 1:32768 (Interval 1s nominal)

01001 1:16384 (Interval 512 ms nominal)

01000 1:8192 (Interval 256 ms nominal)

00111 1:4096 (Interval 128 ms nominal)

00110 1:2048 (Interval 64 ms nominal)

00101 1:1024 (Interval 32 ms nominal)

00100 1:512 (Interval 16 ms nominal)

00011 1:256 (Interval 8 ms nominal)

00010 1:128 (Interval 4 ms nominal)

00001 1:64 (Interval 2 ms nominal)

00000 1:32 (Interval 1 ms nominal)

Bit 0 – SEN Software Enable/Disable for Watchdog Timer bit

Value Condition Description

—If WDTE = 1x This bit is ignored

1If WDTE = 01 WDT is turned on

0If WDTE = 01 WDT is turned off

—If WDTE = 00 This bit is ignored

PIC18F26/45/46Q10

(WWDT) Windowed Watchdog Timer

Note:

1. Times are approximate. WDT time is based on 31 kHz LFINTOSC.

2. When WDTCPS in CONFIG3 = 11111, the Reset value (q) of WDTPS is ‘01011’. Otherwise, the

Reset value of WDTPS is equal to WDTCPS in CONFIG3.

3. When WDTCPS in CONFIG3L ≠ 11111, these bits are read-only.

PIC18F26/45/46Q10

(WWDT) Windowed Watchdog Timer

9.8.2 WDTCON1

Name: WDTCON1

Address: 0xECE

Watchdog Timer Control Register 1

Bit 7 6 5 4 3 2 1 0

WDTCS[2:0] WINDOW[2:0]

Access R/W R/W R/W R/W R/W R/W

Reset q q q q q q

Bits 6:4 – WDTCS[2:0] Watchdog Timer Clock Select bits

Value Description

111 to

010

Reserved

001 MFINTOSC 31.25 kHz

000 LFINTOSC 31 kHz

Bits 2:0 – WINDOW[2:0] Watchdog Timer Window Select bits

WINDOW Window delay Percent of time Window opening Percent of time

111 N/A 100

110 12.5 87.5

101 25 75

100 37.5 62.5

011 50 50

010 62.5 37.5

001 75 25

000 87.5 12.5

Note:

1. If WDTCCS in CONFIG3 = 111, the Reset value of WDTCS is ‘000’.

2. The Reset value (q) of WINDOW is determined by the value of WDTCWS in the CONFIG3 register.

3. If WDTCCS in CONFIG3 ≠ 111, these bits are read-only.

4. If WDTCWS in CONFIG3 ≠ 111, these bits are read-only.

PIC18F26/45/46Q10

(WWDT) Windowed Watchdog Timer

9.8.3 WDTPSH

Name: WDTPSH

Address: 0xED0

WWDT Prescale Select High Register (Read-Only)

Bit 7 6 5 4 3 2 1 0

PSCNTH[7:0]

Access RO RO RO RO RO RO RO RO

Reset 0 0 0 0 0 0 0 0

Bits 7:0 – PSCNTH[7:0] Prescale Select High Byte bits(1)

Note:

1. The 18-bit WDT prescale value, PSCNT<17:0> includes the WDTPSL, WDTPSH and the lower bits

of the WDTTMR registers. PSCNT<17:0> is intended for debug operations and should be read

during normal operation.

PIC18F26/45/46Q10

(WWDT) Windowed Watchdog Timer

9.8.4 WDTPSL

Name: WDTPSL

Address: 0xECF

WWDT Prescale Select Low Register (Read-Only)

Bit 7 6 5 4 3 2 1 0

PSCNTL[7:0]

Access RO RO RO RO RO RO RO RO

Reset 0 0 0 0 0 0 0 0

Bits 7:0 – PSCNTL[7:0] Prescale Select Low Byte bits(1)

Note:

1. The 18-bit WDT prescale value, PSCNT<17:0> includes the WDTPSL, WDTPSH and the lower bits

of the WDTTMR registers. PSCNT<17:0> is intended for debug operations and should be read

during normal operation.

PIC18F26/45/46Q10

(WWDT) Windowed Watchdog Timer

9.8.5 WDTTMR

Name: WDTTMR

Address: 0xED1

WDT Timer Register (Read-Only)

Bit 7 6 5 4 3 2 1 0

WDTTMR[4:0] STATE PSCNT[1:0]

Access RO RO RO RO RO RO RO RO

Reset 0 0 0 0 0 0 0 0

Bits 7:3 – WDTTMR[4:0] Watchdog Window Value bits

WINDOW WDT Window State Open Percent

Closed Open

111 N/A 00000-11111 100

110 00000-00011 00100-11111 87.5

101 00000-00111 01000-11111 75

100 00000-01011 01100-11111 62.5

011 00000-01111 10000-11111 50

010 00000-10011 10100-11111 37.5

001 00000-10111 11000-11111 25

000 00000-11011 11100-11111 12.5

Bit 2 – STATE WDT Armed Status bit

Value Description

1WDT is armed

0WDT is not armed

Bits 1:0 – PSCNT[1:0] Prescale Select Upper Byte bits(1)

Note:

1. The 18-bit WDT prescale value, PSCNT<17:0> includes the WDTPSL, WDTPSH and the lower bits

of the WDTTMR registers. PSCNT<17:0> is intended for debug operations and should be read

during normal operation.

PIC18F26/45/46Q10

(WWDT) Windowed Watchdog Timer

10. Memory Organization

There are three types of memory in PIC18 enhanced microcontroller devices:

• Program Memory

• Data RAM

• Data EEPROM

In Harvard architecture devices, the data and program memories use separate buses that allows for

concurrent access of the two memory spaces. The data EEPROM, for practical purposes, can be

regarded as a peripheral device, since it is addressed and accessed through a set of control registers.

Additional detailed information on the operation of the Program Flash Memory and data EEPROM

memory is provided in the Nonvolatile Memory (NVM) control section.

10.1 Program Memory Organization

PIC18 microcontrollers implement a 21-bit Program Counter, which is capable of addressing a 2 Mbyte

program memory space. Accessing a location between the upper boundary of the physically implemented

memory and the 2 Mbyte address will return all ‘0’s (a NOP instruction).

Refer to the following tables for device memory maps and code protection Configuration bits associated

with the various sections of PFM.

PIC18 devices have two interrupt vectors. The Reset vector address is at 0000h and the interrupt vector

addresses are at 0008h and 0018h.

PIC18F26/45/46Q10

Memory Organization

Figure 10-1. Program and Data Memory Map

Rev. 40-000101C

6/16/2017

PIC18F45Q10

PIC18F26Q10

PIC18F46Q10

Note 1

00 0000h

…

00 0008h

…

00 0018h

…

00 001Ah

00 7FFFh

00 8000h

00 FFFFh

01 0000h

01 FFFFh

02 0000h

1F FFFFh

20 0000h

20 00FFh

20 0100h

2F FFFFh

30 0000h

30 000Bh

30 000Ch

30 02FFh

30 0300h

30 FFFBh

31 0000h

31 00FFh

Data EEPROM

(256 Bytes)

31 0100h

31 03FFh

31 0400h

3F FFFBh

Unimplemented

3F FFFCh

3F FFFDh

3F FFFEh

3F FFFFh

Note 1: The stack is a separate SRAM panel, apart from all user memory panels.

2: The addresses do not roll over. The region is read as ‘0’.

3: Not code-protected.

4: Device/Revision IDs are hard-coded in silicon.

Interrupt Vector Low

…

User IDs (256 Words)(3)

Reserved

Configuration Words (6 Words)(3)

Not

Present(2)

Program Flash

Memory

(16 KW)

Not

Present(2)

Program Flash

Memory

(32 KW)

Address

Device

Stack (31 Levels)

Reset Vector

…

Interrupt Vector High

…

Reserved

Unimplemented

Revision ID (1 Word)(4)

Device ID (1 Word)(4)

Data EEPROM

(1 k Bytes)

Unimplemented

PIC18F26/45/46Q10

Memory Organization

Figure 10-2. Memory Map and Code Protection Control

Rev. 40-000100C

12/19/2017

PIC18F45Q10 PIC18F26Q10

PIC18F46Q10

00 0000h

to

00 07FFh

Boot Block

1 KW

CP, WRTB, EBTRB

Boot Block

1 KW

CP, WRTB, EBTRB

00 0800h

to

00 1FFFh

Block 0

3 KW

CP, WRT0, EBTR0

00 2000h

to

00 3FFFh

Block 1

4 KW

CP, WRT1, EBTR1

00 4000h

to

00 5FFFh

Block 2

4 KW

CP, WRT2, EBTR2

00 6000h

to

00 7FFFh

Block 3

4 KW

CP, WRT3, EBTR3

00 8000h

to

00 BFFFh

Block 2

8 KW

CP, WRT2, EBTR2

00 C000h

to

00 FFFFh

Block 3

8 KW

CP, WRT3, EBTR3

01 0000h

to

01 3FFFh

01 4000h

to

01 7FFFh

01 8000h

to

01 BFFFh

01 C000h

to

01 FFFFh

CONFIG 30 0000h

to

30 000Bh

31 0000h

to

31 00FFh

256 Words

CPD, WRTD

31 0100h

to

31 01FFh

Region Address

Device

PFM

Block 0

7 KW

CP, WRT0, EBTR0

Block 1

8 KW

CP, WRT1, EBTR1

Configuration Words

WRTC

Data

EEPROM

Not

Present

Not

Present

1 KW

CPD, WRTD

PIC18F26/45/46Q10

Memory Organization

10.1.1 Program Counter

The Program Counter (PC) specifies the address of the instruction to fetch for execution. The PC is 21

bits wide and is contained in three separate 8-bit registers. The low byte, known as the PCL register, is

both readable and writable. The high byte, or PCH register, contains the PC<15:8> bits; it is not directly

readable or writable. Updates to the PCH register are performed through the PCLATH register. The upper

byte is called PCU. This register contains the PC<20:16> bits; it is also not directly readable or writable.

Updates to the PCU register are performed through the PCLATU register.

The contents of PCLATH and PCLATU are transferred to the Program Counter by any operation that

writes PCL. Similarly, the upper two bytes of the Program Counter are transferred to PCLATH and

PCLATU by an operation that reads PCL. This is useful for computed offsets to the PC (see 10.1.3.1

Computed GOTO).

The PC addresses bytes in the program memory. To prevent the PC from becoming misaligned with word

instructions, the Least Significant bit of PCL is fixed to a value of ‘0’. The PC increments by two to

address sequential instructions in the program memory.

The CALL, RCALL, GOTO and program branch instructions write to the Program Counter directly. For

these instructions, the contents of PCLATH and PCLATU are not transferred to the Program Counter.

10.1.2 Return Address Stack

The return address stack allows any combination of up to 31 program calls and interrupts to occur. The

PC is pushed onto the stack when a CALL or RCALL instruction is executed or an interrupt is

Acknowledged. The PC value is pulled off the stack on a RETURN, RETLW or a RETFIE instruction.

PCLATU and PCLATH are not affected by any of the RETURN or CALL instructions.

The stack operates as a 31-word by 21-bit RAM and a 5-bit Stack Pointer, or as a 35-word by 21-bit RAM

with a 6-bit Stack Pointer in ICD mode. The stack space is not part of either program or data space. The

Stack Pointer is readable and writable and the address on the top of the stack is readable and writable

through the Top-of-Stack (TOS) Special File registers. Data can also be pushed to, or popped from the

stack, using these registers.

A CALL type instruction causes a push onto the stack; the Stack Pointer is first incremented and the

location pointed to by the Stack Pointer is written with the contents of the PC (already pointing to the

instruction following the CALL). A RETURN type instruction causes a pop from the stack; the contents of

the location pointed to by the STKPTR are transferred to the PC and then the Stack Pointer is

decremented.

The Stack Pointer is initialized to ‘0b00000’ after all Resets. There is no RAM associated with the location

corresponding to a Stack Pointer value of ‘0b00000’; this is only a Reset value. Status bits in the PCON0

register indicate if the stack is full or has overflowed or has under-flowed.

10.1.2.1 Top-of-Stack Access

Only the top of the return address stack (TOS) is readable and writable. A set of three registers,

TOSU:TOSH:TOSL, hold the contents of the stack location pointed to by the STKPTR register (see

Figure 10-3). This allows users to implement a software stack if necessary. After a CALL, RCALL or

interrupt, the software can read the pushed value by reading the TOSU:TOSH:TOSL registers. These

values can be placed on a user defined software stack. At return time, the software can return these

values to TOSU:TOSH:TOSL and do a return.

The user must disable the Global Interrupt Enable (GIE) bits while accessing the stack to prevent

inadvertent stack corruption.

PIC18F26/45/46Q10

Memory Organization

Figure 10-3. Return Address Stack and Associated Registers



00011

001A34h

11111

11110

11101

00010

00001

00000

00010

Return Address Stack <20:0>

Top-of-Stack

000D58h

TOSLTOSHTOSU

34h1Ah00h

STKPTR<4:0>

Top-of-Stack Registers Stack Pointer

Rev. 30-00094A

4/12/2017

10.1.2.2 Return Stack Pointer

The 10.8.4 STKPTR register contains the Stack Pointer value. The STKOVF (Stack Overflow) Status bit

and the STKUNF (Stack Underflow) Status bit can be accessed using the PCON0 register. The value of

the Stack Pointer can be 0 through 31. On Reset, the Stack Pointer value will be zero. The user may read

and write the Stack Pointer value. This feature can be used by a Real-Time Operating System (RTOS) for

stack maintenance. After the PC is pushed onto the stack 32 times (without popping any values off the

stack), the STKOVF bit is set. The STKOVF bit is cleared by software or by a POR. The action that takes

place when the stack becomes full depends on the state of the STVREN (Stack Overflow Reset Enable)

Configuration bit.

If STVREN is set (default), a Reset will be generated and a Stack Overflow will be indicated by the

STKOVF bit when the 32nd push is initiated. This includes CALL and CALLW instructions, as well as

stacking the return address during an interrupt response. The STKOVF bit will remain set and the Stack

Pointer will be set to zero.

If STVREN is cleared, the STKOVF bit will be set on the 32nd push and the Stack Pointer will remain at

31 but no Reset will occur. Any additional pushes will overwrite the 31st push but the STKPTR will remain

at 31.

Setting STKOVF = 1 in software will change the bit, but will not generate a Reset.

The STKUNF bit is set when a stack pop returns a value of zero. The STKUNF bit is cleared by software

or by POR. The action that takes place when the stack becomes full depends on the state of the

STVREN (Stack Overflow Reset Enable) Configuration bit.

If STVREN is set (default) and the stack has been popped enough times to unload the stack, the next pop

will return a value of zero to the PC, it will set the STKUNF bit and a Reset will be generated. This

condition can be generated by the RETURN, RETLW and RETFIE instructions.

If STVREN is cleared, the STKUNF bit will be set, but no Reset will occur.

Important: Returning a value of zero to the PC on an underflow has the effect of vectoring the

program to the Reset vector, where the stack conditions can be verified and appropriate actions

can be taken. This is not the same as a Reset, as the contents of the SFRs are not affected.

Related Links

3.7.2 CONFIG2

PIC18F26/45/46Q10

Memory Organization

10.1.2.3 Stack Overflow and Underflow Resets

Device Resets on Stack Overflow and Stack Underflow conditions are enabled by setting the STVREN

Configuration bit in Configuration. When STVREN is set, a Full or Underflow condition will set the

respective STKOVF or STKUNF bit and then cause a device Reset. When STVREN is cleared, a Full or

Underflow condition will set the respective STKOVF or STKUNF bit but not cause a device Reset. The

STKOVF or STKUNF bits are cleared by the user software or a Power-on Reset.

10.1.2.4 PUSH and POP Instructions

Since the Top-of-Stack is readable and writable, the ability to push values onto the stack and pull values

off the stack without disturbing normal program execution is a desirable feature. The PIC18 instruction set

includes two instructions, PUSH and POP, that permit the TOS to be manipulated under software control.

TOSU, TOSH and TOSL can be modified to place data or a return address on the stack.

The PUSH instruction places the current PC value onto the stack. This increments the Stack Pointer and

loads the current PC value onto the stack.

The POP instruction discards the current TOS by decrementing the Stack Pointer. The previous value

pushed onto the stack then becomes the TOS value.

10.1.2.5 Fast Register Stack

A Fast Register Stack is provided for the STATUS, WREG and BSR registers, to provide a “fast return”

option for interrupts. The Stack for each register is only one level deep and is neither readable nor

writable. It is loaded with the current value of the corresponding register when the processor vectors for

an interrupt. All interrupt sources will push values into the Fast Register Stack. The values in the registers

are then loaded back into their associated registers if the RETFIE, FAST instruction is used to return

from the interrupt.

Important: The TO and PD bits of the STATUS register are not copied over in this operation.

If both low and high-priority interrupts are enabled, the Stack registers cannot be used reliably to return

from low-priority interrupts. If a high-priority interrupt occurs while servicing a low-priority interrupt, the

Stack register values stored by the low-priority interrupt will be overwritten. In these cases, users must

save the key registers by software during a low-priority interrupt.

If interrupt priority is not used, all interrupts may use the Fast Register Stack for returns from interrupt. If

no interrupts are used, the Fast Register Stack can be used to restore the STATUS, WREG and BSR

registers at the end of a subroutine call. To use the Fast Register Stack for a subroutine call, a CALL

label, FAST instruction must be executed to save the STATUS, WREG and BSR registers to the Fast

Register Stack. A RETURN, FAST instruction is then executed to restore these registers from the Fast

Register Stack.

The following example shows a source code example that uses the Fast Register Stack during a

subroutine call and return.

Example 10-1. Fast Register Stack Code Example

CALL SUB1, FAST ;STATUS, WREG, BSR SAVED IN FAST REGISTER STACK

•

SUB1:

•

PIC18F26/45/46Q10

Memory Organization

•

RETURN, FAST ;RESTORE VALUES SAVED IN FAST REGISTER STACK

10.1.3 Look-up Tables in Program Memory

There may be programming situations that require the creation of data structures, or look-up tables, in

program memory. For PIC18 devices, look-up tables can be implemented in two ways:

• Computed GOTO

• Table Reads

10.1.3.1 Computed GOTO

A computed GOTO is accomplished by adding an offset to the Program Counter. An example is shown in

the following code example.

A look-up table can be formed with an ADDWF PCL instruction and a group of RETLW nn instructions. The

W register is loaded with an offset into the table before executing a call to that table. The first instruction

of the called routine is the ADDWF PCL instruction. The next instruction executed will be one of the RETLW

nn instructions that returns the value ‘nn’ to the calling function.

The offset value (in WREG) specifies the number of bytes that the Program Counter should advance and

must be multiples of two (LSb = 0).

In this method, only one data byte may be stored in each instruction location and room on the return

address stack is required.

Example 10-2. Computed GOTO Using an Offset Value

RLNCF OFFSET, W ; W must be an even number, Max OFFSET = 127

CALL TABLE

ORG nn00h ; 00 in LSByte ensures no addition overflow

TABLE:

ADDWF PCL ; Add OFFSET to program counter

RETLW A ; Value @ OFFSET=0

RETLW B ; Value @ OFFSET=1

RETLW C ; Value @ OFFSET=2

.

10.1.3.2 Table Reads and Table Writes

A more compact method of storing data in program memory allows two bytes of data to be stored in each

instruction location.

Look-up table data may be stored two bytes per program word by using table reads and writes. The Table

Pointer (TBLPTR) register specifies the byte address and the Table Latch (TABLAT) register contains the

data that is read from or written to program memory. Data is transferred to or from program memory one

byte at a time.

Table read and table write operations are discussed further in the Table Reads and Table Writes section.

PIC18F26/45/46Q10

Memory Organization

10.2 PIC18 Instruction Cycle

10.2.1 Clocking Scheme

The microcontroller clock input, whether from an internal or external source, is internally divided by four to

generate four non-overlapping quadrature clocks (Q1, Q2, Q3 and Q4). Internally, the Program Counter is

incremented on every Q1; the instruction is fetched from the program memory and latched into the

instruction register during Q4. The instruction is decoded and executed during the following Q1 through

Q4. The clocks and instruction execution flow are shown in the following figure.

Figure 10-4. CLOCK/INSTRUCTION CYCLE



Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

OSC1

Q1

Q2

Q3

Q4

PC

OSC2/CLKOUT

(RC mode)

PC PC + 2 PC + 4

Fetch INST (PC)

Execute INST (PC – 2)

Fetch INST (PC + 2)

Execute INST (PC)

Fetch INST (PC + 4)

Execute INST (PC + 2)

Internal

Phase

Clock

Rev. 30-000095A

4/13/2017

10.2.2 Instruction Flow/Pipelining

An “Instruction Cycle” consists of four Q cycles: Q1 through Q4. The instruction fetch and execute are

pipelined in such a manner that a fetch takes one instruction cycle, while the decode and execute take

another instruction cycle. However, due to the pipelining, each instruction effectively executes in one

cycle. If an instruction causes the Program Counter to change (e.g., GOTO), then two cycles are required

to complete the instruction as shown in the figure below.

A fetch cycle begins with the Program Counter (PC) incrementing in Q1.

In the execution cycle, the fetched instruction is latched into the Instruction Register (IR) in cycle Q1. This

instruction is then decoded and executed during the Q2, Q3 and Q4 cycles. Data memory is read during

Q2 (operand read) and written during Q4 (destination write).

Figure 10-5. Instruction Pipeline Flow

Rev. 10-000337A

9/27/2017

TCY0 TCY1TCY2 TCY3 TCY4 TCY5

1. MOVLW 55h

2. MOVWF PORTB

3. BRA Sub_1

4. BSF PORTA, BITS (Forced NOP)

5. Instruction @ address Sub_1

Fetch 1 Execute 1

Fetch 2 Execute 2

Fetch 3 Execute 3

Fetch 4 Flush (NOP)

Fetch Sub_1 Execute Sub_1

All instructions are single cycle except for any program branches. These take two cycles since the fetch instruction

is “flushed” from the pipeline while the new instruction is being fetched and then executed.

PIC18F26/45/46Q10

Memory Organization

10.2.3 Instructions in Program Memory

The program memory is addressed in bytes. Instructions are stored as either two bytes or four bytes in

program memory. The Least Significant Byte of an instruction word is always stored in a program memory

location with an even address (LSb = 0). To maintain alignment with instruction boundaries, the PC

increments in steps of two and the LSb will always read ‘0’ (see 10.1.1 Program Counter).

The Instructions in Program Memory figure below shows how instruction words are stored in the program

memory.

The CALL and GOTO instructions have the absolute program memory address embedded into the

instruction. Since instructions are always stored on word boundaries, the data contained in the instruction

is a word address. The word address is written to PC<20:1>, which accesses the desired byte address in

program memory. Instruction #2 in the example shows how the instruction GOTO 0006h is encoded in the

program memory. Program branch instructions, which encode a relative address offset, operate in the

same manner. The offset value stored in a branch instruction represents the number of single-word

instructions that the PC will be offset by. The Instruction Set Summary provides further details of the

instruction set.

Figure 10-6. Instructions in Program Memory



Word Address

LSB = 1LSB = 0

Program Memory

Byte Locations 

000000h

000002h

000004h

000006h

Instruction 1: MOVLW 055h 0Fh 55h 000008h

Instruction 2: GOTO 0006h EFh 03h 00000Ah

F0h 00h 00000Ch

Instruction 3: MOVFF 123h, 456h C1h 23h 00000Eh

F4h 56h 000010h

000012h

000014h

Rev. 30-000112A4/19/2017

Related Links

37. Instruction Set Summary

10.2.4 Two-Word Instructions

The standard PIC18 instruction set has four two-word instructions: CALL, MOVFF, GOTO and LFSR. In all

cases, the second word of the instruction always has ‘1111’ as its four Most Significant bits; the other 12

bits are literal data, usually a data memory address.

The use of ‘1111’ in the 4 MSbs of an instruction specifies a special form of NOP. If the instruction is

executed in proper sequence – immediately after the first word – the data in the second word is accessed

and used by the instruction sequence. If the first word is skipped for some reason and the second word is

executed by itself, a NOP is executed instead. This is necessary for cases when the two-word instruction

is preceded by a conditional instruction that changes the PC. The Two-Word Instructions figure below

shows how this works.

Important: See the 10.6 PIC18 Instruction Execution and the Extended Instruction Set

section for information on two-word instructions in the extended instruction set.

PIC18F26/45/46Q10

Memory Organization

Figure 10-7. Two-Word Instructions



CASE 1:

Object Code Source Code

0110 0110 0000 0000 TSTFSZ REG1 ; is RAM location 0?

1100 0001 0010 0011 MOVFF REG1, REG2 ; No, skip this word

1111 0100 0101 0110 ; Execute this word as a NOP

0010 0100 0000 0000 ADDWF REG3 ; continue code

CASE 2:

Object Code Source Code

0110 0110 0000 0000 TSTFSZ REG1 ; is RAM location 0?

1100 0001 0010 0011 MOVFF REG1, REG2 ; Yes, execute this word

1111 0100 0101 0110 ; 2nd word of instruction

0010 0100 0000 0000 ADDWF REG3 ; continue code

Rev. 30-000113A

4/19/2017

10.3 Data Memory Organization

Important: The operation of some aspects of data memory are changed when the PIC18

extended instruction set is enabled. See 10.6 PIC18 Instruction Execution and the Extended

Instruction Set for more information.

The data memory in PIC18 devices is implemented as static RAM. Each register in the data memory has

a 12-bit address, allowing up to 4096 bytes of data memory. The memory space is divided into as many

as 16 banks that contain 256 bytes each. The figure below shows the data memory organization for all

devices in the device family.

The data memory contains Special Function Registers (SFRs) and General Purpose Registers (GPRs).

The SFRs are used for control and status of the controller and peripheral functions, while GPRs are used

for data storage and scratchpad operations in the user’s application. Any read of an unimplemented

location will read as ‘0’s.

The instruction set and architecture allow operations across all banks. The entire data memory may be

accessed by Direct, Indirect or Indexed Addressing modes. Addressing modes are discussed later in this

subsection.

To ensure that commonly used registers (SFRs and select GPRs) can be accessed in a single cycle,

PIC18 devices implement an Access Bank. This is a 256-byte memory space that provides fast access to

SFRs and the lower portion of GPR Bank 0 without using the Bank Select Register (BSR). The 10.3.2

Access Bank section provides a detailed description of the Access RAM.

PIC18F26/45/46Q10

Memory Organization

Figure 10-8. Data Memory Map

Rev. 40-000102C

6/16/2017

45Q10 26Q10 46Q10

00h-5Fh

60h-FFh

1 1h 00h-FFh

2 2h 00h-FFh

3 3h 00h-FFh

4 4h 00h-FFh

5 5h 00h-FFh

6 6h 00h-FFh

7 7h 00h-FFh Virtual Access Bank

8 8h 00h-FFh

9 9h 00h-FFh 00h-5Fh

10 Ah 00h-FFh 60h-FFh

11 Bh 00h-FFh

12 Ch 00h-FFh

13 Dh 00h-FFh

00h-1Eh

1Fh-9Ah

9Bh-FFh

00h-5Fh

60h-FFh

PIC18F

Sector RAM

14 Eh

Unimplemented

GPR

SFR

Fh15

addr<7:0>

0h0

BanK BSR<3:0>

addr<11:8>

10.3.1 Bank Select Register

Large areas of data memory require an efficient addressing scheme to make rapid access to any address

possible. Ideally, this means that an entire address does not need to be provided for each read or write

operation. For PIC18 devices, this is accomplished with a RAM banking scheme. This divides the

memory space into 16 contiguous banks of 256 bytes. Depending on the instruction, each location can be

addressed directly by its full 12-bit address, or an 8-bit low-order address and a 4-bit Bank Pointer.

Most instructions in the PIC18 instruction set make use of the Bank Pointer, known as the Bank Select

Register (10.8.13 BSR). This SFR holds the four Most Significant bits of a location’s address; the

instruction itself includes the eight Least Significant bits. Only the four lower bits of the BSR are

implemented (BSR<3:0>). The upper four bits are unused; they will always read ‘0’ and cannot be written

to. The BSR can be loaded directly by using the MOVLB instruction.

The value of the BSR indicates the bank in data memory; the eight bits in the instruction show the

location in the bank and can be thought of as an offset from the bank’s lower boundary. The relationship

between the BSR’s value and the bank division in data memory is shown in the figure below.

PIC18F26/45/46Q10

Memory Organization

Since up to 16 registers may share the same low-order address, the user must always be careful to

ensure that the proper bank is selected before performing a data read or write. For example, writing what

should be program data to an 8-bit address of F9h while the BSR is 0Fh will end up resetting the Program

Counter.

While any bank can be selected, only those banks that are actually implemented can be read or written

to. Writes to unimplemented banks are ignored, while reads from unimplemented banks will return ‘0’s.

Even so, the STATUS register will still be affected as if the operation was successful. The data memory

maps in the following figure indicate which banks are implemented.

In the core PIC18 instruction set, only the MOVFF instruction fully specifies the 12-bit address of the

source and target registers. This instruction ignores the BSR completely when it executes. All other

instructions include only the low-order address as an operand and must use either the BSR or the Access

Bank to locate their target registers.

Figure 10-9. Use of the Bank Select Register (Direct Addressing)



Note 1: The Access RAM bit of the instruction can be used to force an override of the selected bank (BSR<3:0>) to

the registers of the Access Bank.

2: The MOVFF instruction embeds the entire 12-bit address in the instruction.

Data Memory

Bank Select(2)

7 0

From Opcode(2)

0 0 0 0

Bank 3

through

Bank 13

0 0 1 0 1 1 1 1 1 1 1 1

7 0

BSR(1)

000h

100h

200h

300h

F00h

E00h

FFFh

Bank 0

Bank 1

Bank 2

Bank 14

Bank 15

00h

FFh

00h

FFh

00h

FFh

00h

FFh

00h

FFh

Rev. 30-000108A

09/07/2017

10.3.2 Access Bank

While the use of the BSR with an embedded 8-bit address allows users to address the entire range of

data memory, it also means that the user must always ensure that the correct bank is selected.

Otherwise, data may be read from or written to the wrong location. This can be disastrous if a GPR is the

intended target of an operation, but an SFR is written to instead. Verifying and/or changing the BSR for

each read or write to data memory can become very inefficient.

To streamline access for the most commonly used data memory locations, the data memory is configured

with an Access Bank, which allows users to access a mapped block of memory without specifying a BSR.

The Access Bank consists of the first 96 bytes of memory (00h-5Fh) in Bank 0 and the last 160 bytes of

memory (60h-FFh) in Block 15. The lower half is known as the “Access RAM” and is composed of GPRs.

This upper half is also where the device’s SFRs are mapped. These two areas are mapped contiguously

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in the Access Bank and can be addressed in a linear fashion by an 8-bit address (see Data Memory

Map).

The Access Bank is used by core PIC18 instructions that include the Access RAM bit (the ‘a’ parameter

in the instruction). When ‘a’ is equal to ‘1’, the instruction uses the BSR and the 8-bit address included in

the opcode for the data memory address. When ‘a’ is ‘0’, however, the instruction is forced to use the

Access Bank address map; the current value of the BSR is ignored entirely.

Using this “forced” addressing allows the instruction to operate on a data address in a single cycle,

without updating the BSR first. For 8-bit addresses of 60h and above, this means that users can evaluate

and operate on SFRs more efficiently. The Access RAM below 60h is a good place for data values that

the user might need to access rapidly, such as immediate computational results or common program

variables. Access RAM also allows for faster and more code efficient context saving and switching of

variables.

The mapping of the Access Bank is slightly different when the extended instruction set is enabled (XINST

Configuration bit = 1). This is discussed in more detail in the 10.5.3 Mapping the Access Bank in Indexed

Literal Offset Mode section.

10.3.3 General Purpose Register File

PIC18 devices may have banked memory in the GPR area. This is data RAM, which is available for use

by all instructions. GPRs start at the bottom of Bank 0 (address 000h) and grow upwards towards the

bottom of the SFR area. GPRs are not initialized by a Power-on Reset and are unchanged on all other

Resets.

10.3.4 Special Function Registers

The Special Function Registers (SFRs) are registers used by the CPU and peripheral modules for

controlling the desired operation of the device. These registers are implemented as static RAM. SFRs

start at the top of data memory (FFFh) and extend downward. A list of these registers is given in the

register summary table.

The SFRs can be classified into two sets: those associated with the “core” device functionality (ALU,

Resets and interrupts) and those related to the peripheral functions. The Reset and Interrupt registers are

described in their respective chapters, while the ALU’s STATUS register is described later in this section.

Registers related to the operation of a peripheral feature are described in the chapter for that peripheral.

The SFRs are typically distributed among the peripherals whose functions they control. Unused SFR

locations are unimplemented and read as ‘0’s.

Related Links

35. Register Summary

10.3.5 Status Register

The 10.8.5 STATUS register contains the arithmetic status of the ALU. As with any other SFR, it can be

the operand for any instruction.

If the STATUS register is the destination for an instruction that affects the Z, DC, C, OV or N bits, the

results of the instruction are not written; instead, the STATUS register is updated according to the

instruction performed. Therefore, the result of an instruction with the STATUS register as its destination

may be different than intended. As an example, CLRF STATUS will set the Z bit and leave the remaining

Status bits unchanged (‘000u u1uu’).

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It is recommended that only BCF, BSF, SWAPF, MOVFF and MOVWF instructions are used to alter the

STATUS register, because these instructions do not affect the Z, C, DC, OV or N bits in the STATUS

register.

For other instructions that do not affect Status bits, see the instruction set summaries.

Important: The C and DC bits operate as the borrow and digit borrow bits, respectively, in

subtraction.

Related Links

37. Instruction Set Summary

10.4 Data Addressing Modes

Important: The execution of some instructions in the core PIC18 instruction set are changed

when the PIC18 extended instruction set is enabled. See 10.5 Data Memory and the Extended

Instruction Set for more information.

Information in the data memory space can be addressed in several ways. For most instructions, the

Addressing mode is fixed. Other instructions may use up to three modes, depending on which operands

are used and whether or not the extended instruction set is enabled.

The Addressing modes are:

• Inherent

• Literal

• Direct

• Indirect

An additional Addressing mode, Indexed Literal Offset, is available when the extended instruction set is

enabled (XINST Configuration bit = 1). Its operation is discussed in greater detail in 10.5.1 Indexed

Addressing with Literal Offset.

10.4.1 Inherent and Literal Addressing

Many PIC18 control instructions do not need any argument at all; they either perform an operation that

globally affects the device or they operate implicitly on one register. This Addressing mode is known as

Inherent Addressing. Examples include SLEEP, RESET and DAW.

Other instructions work in a similar way but require an additional explicit argument in the opcode. This is

known as Literal Addressing mode because they require some literal value as an argument. Examples

include ADDLW and MOVLW, which respectively, add or move a literal value to the W register. Other

examples include CALL and GOTO, which include a 20-bit program memory address.

10.4.2 Direct Addressing

Direct Addressing specifies all or part of the source and/or destination address of the operation within the

opcode itself. The options are specified by the arguments accompanying the instruction.

In the core PIC18 instruction set, bit-oriented and byte-oriented instructions use some version of Direct

Addressing by default. All of these instructions include some 8-bit literal address as their Least Significant

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Byte. This address specifies either a register address in one of the banks of data RAM (see 10.3.3

General Purpose Register File) or a location in the Access Bank (see 10.3.2 Access Bank) as the data

source for the instruction.

The Access RAM bit ‘a’ determines how the address is interpreted. When ‘a’ is ‘1’, the contents of the

BSR (see 10.3.1 Bank Select Register) are used with the address to determine the complete 12-bit

address of the register. When ‘a’ is ‘0’, the address is interpreted as being a register in the Access Bank.

Addressing that uses the Access RAM is sometimes also known as Direct Forced Addressing mode.

A few instructions, such as MOVFF, include the entire 12-bit address (either source or destination) in their

opcodes. In these cases, the BSR is ignored entirely.

The destination of the operation’s results is determined by the destination bit ‘d’. When ‘d’ is ‘1’, the

results are stored back in the source register, overwriting its original contents. When ‘d’ is ‘0’, the results

are stored in the W register. Instructions without the ‘d’ argument have a destination that is implicit in the

instruction; their destination is either the target register being operated on or the W register.

10.4.3 Indirect Addressing

Indirect Addressing allows the user to access a location in data memory without giving a fixed address in

the instruction. This is done by using File Select Registers (FSRs) as pointers to the locations which are

to be read or written. Since the FSRs are themselves located in RAM as Special File Registers, they can

also be directly manipulated under program control. This makes FSRs very useful in implementing data

structures, such as tables and arrays in data memory.

The registers for Indirect Addressing are also implemented with Indirect File Operands (INDFs) that

permit automatic manipulation of the pointer value with auto-incrementing, auto-decrementing or

offsetting with another value. This allows for efficient code, using loops, such as the following example of

clearing an entire RAM bank.

Example 10-3. How to Clear RAM (Bank 1) Using Indirect Addressing

LFSR FSR0,100h ; Set FSR0 to beginning of Bank1

BTFSS FSR0H,1 ; Has high FSR0 byte incremented to next bank?

BRA NEXT ; NO, clear next byte in Bank1

CONTINUE: ; YES, continue

10.4.3.1 FSR Registers and the INDF Operand

At the core of Indirect Addressing are three sets of registers: FSR0, FSR1 and FSR2. Each represents a

pair of 8-bit registers, FSRnH and FSRnL. Each FSR pair holds a 12-bit value, therefore, the four upper

bits of the FSRnH register are not used. The 12-bit FSR value can address the entire range of the data

memory in a linear fashion. The FSR register pairs, then, serve as pointers to data memory locations.

Indirect Addressing is accomplished with a set of Indirect File Operands, INDF0 through INDF2. These

can be thought of as “virtual” registers; they are mapped in the SFR space but are not physically

implemented. Reading or writing to a particular INDF register actually accesses its corresponding FSR

register pair. A read from INDF1, for example, reads the data at the address indicated by FSR1H:FSR1L.

Instructions that use the INDF registers as operands actually use the contents of their corresponding FSR

as a pointer to the instruction’s target. The INDF operand is just a convenient way of using the pointer.

Because Indirect Addressing uses a full 12-bit address, the FSR value can target any location in any

bank regardless of the BSR value. However, the Access RAM bit must be cleared to 0 to ensure that the

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INDF register in Access space is the object of the operation instead of a register in one of the other

banks. The assembler default value for the Access RAM bit is zero when targeting any of the indirect

operands.

10.4.3.2 FSR Registers and POSTINC, POSTDEC, PREINC and PLUSW

In addition to the INDF operand, each FSR register pair also has four additional indirect operands. Like

INDF, these are “virtual” registers that cannot be directly read or written. Accessing these registers

actually accesses the location to which the associated FSR register pair points, and also performs a

specific action on the FSR value. They are:

• POSTDEC: accesses the location to which the FSR points, then automatically decrements the FSR

by 1 afterwards

• POSTINC: accesses the location to which the FSR points, then automatically increments the FSR by

1 afterwards

• PREINC: automatically increments the FSR by one, then uses the location to which the FSR points in

the operation

• PLUSW: adds the signed value of the W register (range of -127 to 128) to that of the FSR and uses

the location to which the result points in the operation.

In this context, accessing an INDF register uses the value in the associated FSR register without

changing it. Similarly, accessing a PLUSW register gives the FSR value an offset by that in the W

register; however, neither W nor the FSR is actually changed in the operation. Accessing the other virtual

registers changes the value of the FSR register.

Figure 10-10. Indirect Addressing

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Operations on the FSRs with POSTDEC, POSTINC and PREINC affect the entire register pair; that is,

rollovers of the FSRnL register from FFh to 00h carry over to the FSRnH register. On the other hand,

results of these operations do not change the value of any flags in the STATUS register (e.g., Z, N, OV,

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The PLUSW register can be used to implement a form of Indexed Addressing in the data memory space.

By manipulating the value in the W register, users can reach addresses that are fixed offsets from pointer

addresses. In some applications, this can be used to implement some powerful program control structure,

such as software stacks, inside of data memory.

10.4.3.3 Operations by FSRs on FSRs

Indirect Addressing operations that target other FSRs or virtual registers represent special cases. For

example, using an FSR to point to one of the virtual registers will not result in successful operations. As a

specific case, assume that FSR0H:FSR0L contains the address of INDF1. Attempts to read the value of

the INDF1 using INDF0 as an operand will return 00h. Attempts to write to INDF1 using INDF0 as the

operand will result in a NOP.

On the other hand, using the virtual registers to write to an FSR pair may not occur as planned. In these

cases, the value will be written to the FSR pair but without any incrementing or decrementing. Thus,

writing to either the INDF2 or POSTDEC2 register will write the same value to the FSR2H:FSR2L.

Since the FSRs are physical registers mapped in the SFR space, they can be manipulated through all

direct operations. Users should proceed cautiously when working on these registers, particularly if their

code uses Indirect Addressing.

Similarly, operations by Indirect Addressing are generally permitted on all other SFRs. Users should

exercise the appropriate caution that they do not inadvertently change settings that might affect the

operation of the device.

10.5 Data Memory and the Extended Instruction Set

Enabling the PIC18 extended instruction set (XINST Configuration bit = 1) significantly changes certain

aspects of data memory and its addressing. Specifically, the use of the Access Bank for many of the core

PIC18 instructions is different; this is due to the introduction of a new Addressing mode for the data

memory space.

What does not change is just as important. The size of the data memory space is unchanged, as well as

its linear addressing. The SFR map remains the same. Core PIC18 instructions can still operate in both

Direct and Indirect Addressing mode; inherent and literal instructions do not change at all. Indirect

addressing with FSR0 and FSR1 also remain unchanged.

10.5.1 Indexed Addressing with Literal Offset

Enabling the PIC18 extended instruction set changes the behavior of Indirect Addressing using the FSR2

register pair within Access RAM. Under the proper conditions, instructions that use the Access Bank –

that is, most bit-oriented and byte-oriented instructions – can invoke a form of Indexed Addressing using

an offset specified in the instruction. This special Addressing mode is known as Indexed Addressing with

Literal Offset, or Indexed Literal Offset mode.

When using the extended instruction set, this Addressing mode requires the following:

• The use of the Access Bank is forced (‘a’ = 0) and

• The file address argument is less than or equal to 5Fh.

Under these conditions, the file address of the instruction is not interpreted as the lower byte of an

address (used with the BSR in Direct Addressing), or as an 8-bit address in the Access Bank. Instead,

the value is interpreted as an offset value to an Address Pointer, specified by FSR2. The offset and the

contents of FSR2 are added to obtain the target address of the operation.

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10.5.2 Instructions Affected by Indexed Literal Offset Mode

Any of the core PIC18 instructions that can use Direct Addressing are potentially affected by the Indexed

Literal Offset Addressing mode. This includes all byte-oriented and bit-oriented instructions, or almost

one-half of the standard PIC18 instruction set. Instructions that only use Inherent or Literal Addressing

modes are unaffected.

Additionally, byte-oriented and bit-oriented instructions are not affected if they do not use the Access

Bank (Access RAM bit is ‘1’), or include a file address of 60h or above. Instructions meeting these criteria

will continue to execute as before. A comparison of the different possible Addressing modes when the

extended instruction set is enabled is shown in the following figure.

Those who desire to use byte-oriented or bit-oriented instructions in the Indexed Literal Offset mode

should note the changes to assembler syntax for this mode. This is described in more detail in the

Extended Instruction Syntax section.

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Figure 10-11. Comparing Addressing Options for Bit-Oriented and

Byte-Oriented Instructions (Extended Instruction Set Enabled)

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Rev. 30-000110A

4/18/2017

≥

PIC18F26/45/46Q10

Memory Organization

Related Links

37.2.1 Extended Instruction Syntax

10.5.3 Mapping the Access Bank in Indexed Literal Offset Mode

The use of Indexed Literal Offset Addressing mode effectively changes how the first 96 locations of

Access RAM (00h to 5Fh) are mapped. Rather than containing just the contents of the bottom section of

Bank 0, this mode maps the contents from a user defined “window” that can be located anywhere in the

data memory space. The value of FSR2 establishes the lower boundary of the addresses mapped into

the window, while the upper boundary is defined by FSR2 plus 95 (5Fh). Addresses in the Access RAM

above 5Fh are mapped as previously described (see 10.3.2 Access Bank). An example of Access Bank

remapping in this Addressing mode is shown in the following figure.

Figure 10-12. Remapping the Access Bank with Indexed Literal Offset Addressing



Data Memory

000h

100h

200h

F60h

F00h

FFFh

Bank 1

Bank 15

Bank 2

through

Bank 14

SFRs

ADDWF f, d, a

FSR2H:FSR2L = 120h

Locations in the region

from the FSR2 pointer

(120h) to the pointer plus

05Fh (17Fh) are mapped

to the bottom of the

Access RAM (000h-05Fh).

Special File Registers at

F60h through FFFh are

mapped to 60h through

FFh, as usual.

Bank 0 addresses below

5Fh can still be addressed

by using the BSR. Access Bank

00h

60h

FFh

SFRs

Bank 1 “Window”

Bank 0

Window

Example Situation:

120h

17Fh

5Fh

Bank 1

Rev. 30-000111A

4/18/2017

Remapping of the Access Bank applies only to operations using the Indexed Literal Offset mode.

Operations that use the BSR (Access RAM bit is ‘1’) will continue to use Direct Addressing as before.

10.6 PIC18 Instruction Execution and the Extended Instruction Set

Enabling the extended instruction set adds eight additional commands to the existing PIC18 instruction

set. These instructions are executed as described in the Extended Instruction Set section.

Related Links

37.2.1 Extended Instruction Syntax

PIC18F26/45/46Q10

Memory Organization

10.7 Register Summary: Memory and Status

Address Name Bit Pos.

0x0FD8 STATUS 7:0 TO PD N OV Z DC C

0x0FD9 FSR2

7:0 FSRL[7:0]

15:8 FSRH[3:0]

0x0FDB PLUSW2 7:0 PLUSW[7:0]

0x0FDC PREINC2 7:0 PREINC[7:0]

0x0FDD POSTDEC2 7:0 POSTDEC[7:0]

0x0FDE POSTINC2 7:0 POSTINC[7:0]

0x0FDF INDF2 7:0 INDF[7:0]

0x0FE0 BSR 7:0 BSR[3:0]

0x0FE1 FSR1

7:0 FSRL[7:0]

15:8 FSRH[3:0]

0x0FE3 PLUSW1 7:0 PLUSW[7:0]

0x0FE4 PREINC1 7:0 PREINC[7:0]

0x0FE5 POSTDEC1 7:0 POSTDEC[7:0]

0x0FE6 POSTINC1 7:0 POSTINC[7:0]

0x0FE7 INDF1 7:0 INDF[7:0]

0x0FE8 WREG 7:0 WREG[7:0]

0x0FE9 FSR0

7:0 FSRL[7:0]

15:8 FSRH[3:0]

0x0FEB PLUSW0 7:0 PLUSW[7:0]

0x0FEC PREINC0 7:0 PREINC[7:0]

0x0FED POSTDEC0 7:0 POSTDEC[7:0]

0x0FEE POSTINC0 7:0 POSTINC[7:0]

0x0FEF INDF0 7:0 INDF[7:0]

0x0FF0

...

0x0FF8

Reserved

0x0FF9 PCL 7:0 PCL[7:0]

0x0FFA PCLAT

7:0 PCLATH[7:0]

15:8 PCLATU[4:0]

0x0FFC STKPTR 7:0 STKPTR[4:0]

0x0FFD TOS

7:0 TOSL[7:0]

15:8 TOSH[7:0]

23:16 TOSU[4:0]

10.8 Register Definitions: Memory and Status

PIC18F26/45/46Q10

Memory Organization

10.8.1 PCL

Name: PCL

Address: 0xFF9

Low byte of the Program Counter

Bit 7 6 5 4 3 2 1 0

PCL[7:0]

Access R/W R/W R/W R/W R/W R/W R/W R/W

Reset 0 0 0 0 0 0 0 0

Bits 7:0 – PCL[7:0]

Provides direct read and write access to the Program Counter

PIC18F26/45/46Q10

Memory Organization

10.8.2 PCLAT

Name: PCLAT

Address: 0xFFA

Program Counter Latches. Holding register for bits <21:9> of the Program Counter (PC). Reads of the

PCL register transfer the upper PC bits to the PCLAT register. Writes to PCL register transfer the PCLAT

value to the PC.

Bit 15 14 13 12 11 10 9 8

PCLATU[4:0]

Access R/W R/W R/W R/W R/W

Reset 0 0 0 0 0

Bit 7 6 5 4 3 2 1 0

PCLATH[7:0]

Access R/W R/W R/W R/W R/W R/W R/W R/W

Reset 0 0 0 0 0 0 0 0

Bits 12:8 – PCLATU[4:0] Upper PC Latch register

Holding register for Program Counter bits <21:17>

Bits 7:0 – PCLATH[7:0] High PC Latch register

Holding register for Program Counter bits <16:8>

PIC18F26/45/46Q10

Memory Organization

10.8.3 TOS

Name: TOS

Address: 0xFFD

Top-Of-Stack Registers.

Contents of the stack pointed to by the 10.8.4 STKPTR register. This is the value that will be loaded into

the Program Counter upon a RETURN or RETFIE instruction.

Bit 23 22 21 20 19 18 17 16

TOSU[4:0]

Access R/W R/W R/W R/W R/W

Reset 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8

TOSH[7:0]

Access R/W R/W R/W R/W R/W R/W R/W R/W

Reset 0 0 0 0 0 0 0 0

Bit 7 6 5 4 3 2 1 0

TOSL[7:0]

Access R/W R/W R/W R/W R/W R/W R/W R/W

Reset 0 0 0 0 0 0 0 0

Bits 20:16 – TOSU[4:0] Upper byte of TOS register

Bits <21:17> of the TOS

Bits 15:8 – TOSH[7:0] High Byte of the TOS Register

Bits <16:8> of the TOS

Bits 7:0 – TOSL[7:0] Low Byte TOS Register

Bits <7:0> of the TOS

PIC18F26/45/46Q10

Memory Organization

10.8.4 STKPTR

Name: STKPTR

Address: 0xFFC

Stack Pointer Register

Bit 7 6 5 4 3 2 1 0

STKPTR[4:0]

Access R/W R/W R/W R/W R/W

Reset 0 0 0 0 0

Bits 4:0 – STKPTR[4:0] Stack Pointer Location bits

PIC18F26/45/46Q10

Memory Organization

10.8.5 STATUS

Name: STATUS

Address: 0xFD8

Status Register

Bit 7 6 5 4 3 2 1 0

TO PD N OV Z DC C

Access R R R/W R/W R/W R/W R/W

Reset 1 1 0 0 0 0 0

Bit 6 – TO Time-Out bit

Reset States: POR/BOR = 1

All Other Resets = q

Value Description

1Set at power-up or by execution of CLRWDT or SLEEP instruction

0A WDT time-out occurred

Bit 5 – PD Power-Down bit

Reset States: POR/BOR = 1

All Other Resets = q

Value Description

1Set at power-up or by execution of CLRWDT instruction

0Cleared by execution of the SLEEP instruction

Bit 4 – N Negative bit

Used for signed arithmetic (2’s complement); indicates if the result is negative,

(ALU MSb = 1).

Reset States: POR/BOR = 0

All Other Resets = u

Value Description

1The result is negative

0The result is positive

Bit 3 – OV Overflow bit

Used for signed arithmetic (2’s complement); indicates an overflow of the 7-bit magnitude, which causes

the sign bit (bit 7) to change state.

Reset States: POR/BOR = 0

All Other Resets = u

Value Description

1Overflow occurred for current signed arithmetic operation

0No overflow occurred

Bit 2 – Z Zero bit

Reset States: POR/BOR = 0

All Other Resets = u

Value Description

1The result of an arithmetic or logic operation is zero

PIC18F26/45/46Q10

Memory Organization

Value Description

0The result of an arithmetic or logic operation is not zero

Bit 1 – DC Digit Carry/Borrow bit

ADDWF, ADDLW, SUBLW, SUBWF instructions(1)

Reset States: POR/BOR = 0

All Other Resets = u

Value Description

1A carry-out from the 4th low-order bit of the result occurred

0No carry-out from the 4th low-order bit of the result

Bit 0 – C Carry/Borrow bit

ADDWF, ADDLW, SUBLW, SUBWF instructions(1,2)

Reset States: POR/BOR = 0

All Other Resets = u

Value Description

1A carry-out from the Most Significant bit of the result occurred

0No carry-out from the Most Significant bit of the result occurred

Note:

1. For Borrow, the polarity is reversed. A subtraction is executed by adding the two’s complement of

the second operand.

2. For Rotate (RRCF, RLCF) instructions, this bit is loaded with either the high or low-order bit of the

Source register.

PIC18F26/45/46Q10

Memory Organization

10.8.6 WREG

Name: WREG

Address: 0xFE8

Shadow of Working Data Register

Bit 7 6 5 4 3 2 1 0

WREG[7:0]

Access R/W R/W R/W R/W R/W R/W R/W R/W

Reset x x x x x x x x

Bits 7:0 – WREG[7:0]

PIC18F26/45/46Q10

Memory Organization

10.8.7 INDF

Name: INDFx

Address: 0xFEF,0xFE7,0xFDF

Indirect Data Register. This is a virtual register. The GPR/SFR register addressed by the FSRx register is

the target for all operations involving the INDFx register.

Bit 7 6 5 4 3 2 1 0

INDF[7:0]

Access R/W R/W R/W R/W R/W R/W R/W R/W

Reset 0 0 0 0 0 0 0 0

Bits 7:0 – INDF[7:0]

Indirect data pointed to by the FSRx register

PIC18F26/45/46Q10

Memory Organization

10.8.8 POSTDEC

Name: POSTDECx

Address: 0xFED,0xFE5,0xFDD

Indirect Data Register with post decrement. This is a virtual register. The GPR/SFR register addressed by

the FSRx register is the target for all operations involving the POSTDECx register. FSRx is decrememted

after the read or write operation.

Bit 7 6 5 4 3 2 1 0

POSTDEC[7:0]

Access R/W R/W R/W R/W R/W R/W R/W R/W

Reset 0 0 0 0 0 0 0 0

Bits 7:0 – POSTDEC[7:0]

PIC18F26/45/46Q10

Memory Organization

10.8.9 POSTINC

Name: POSTINCx

Address: 0xFEE,0xFE6,0xFDE

Indirect Data Register with post increment. This is a virtual register. The GPR/SFR register addressed by

the FSRx register is the target for all operations involving the POSTINCx register. FSRx is incremented

after the read or write operation.

Bit 7 6 5 4 3 2 1 0

POSTINC[7:0]

Access R/W R/W R/W R/W R/W R/W R/W R/W

Reset 0 0 0 0 0 0 0 0

Bits 7:0 – POSTINC[7:0]

PIC18F26/45/46Q10

Memory Organization

10.8.10 PREINC

Name: PREINCx

Address: 0xFEC,0xFE4,0xFDC

Indirect Data Register with pre-increment. This is a virtual register. The GPR/SFR register addressed by

the FSRx register plus 1 is the target for all operations involving the PREINCx register. FSRx is

incremented before the read or write operation.

Bit 7 6 5 4 3 2 1 0

PREINC[7:0]

Access R/W R/W R/W R/W R/W R/W R/W R/W

Reset 0 0 0 0 0 0 0 0

Bits 7:0 – PREINC[7:0]

PIC18F26/45/46Q10

Memory Organization

10.8.11 PLUSW

Name: PLUSWx

Address: 0xFEB,0xFE3,0xFDB

Indirect Data Register with WREG offset. This is a virtual register. The GPR/SFR register addressed by

the sum of the FSRx register plus the signed value of the W register is the target for all operations

involving the PLUSWx register.

Bit 7 6 5 4 3 2 1 0

PLUSW[7:0]

Access R/W R/W R/W R/W R/W R/W R/W R/W

Reset 0 0 0 0 0 0 0 0

Bits 7:0 – PLUSW[7:0]

PIC18F26/45/46Q10

Memory Organization

10.8.12 FSR

Name: FSRx

Address: 0xFE9,0xFE1,0xFD9

Indirect Address Register. The FSR value is the address of the data to which the INDF register points.

Bit 15 14 13 12 11 10 9 8

FSRH[3:0]

Access R/W R/W R/W R/W

Reset 0 0 0 0

Bit 7 6 5 4 3 2 1 0

FSRL[7:0]

Access R/W R/W R/W R/W R/W R/W R/W R/W

Reset 0 0 0 0 0 0 0 0

Bits 11:8 – FSRH[3:0]

Most Significant address of INDF data

Bits 7:0 – FSRL[7:0]

Least Significant address of INDF data

PIC18F26/45/46Q10

Memory Organization

10.8.13 BSR

Name: BSR

Address: 0xFE0

Bank Select Register

The BSR indicates the data memory bank which is bits 11:8 of the GPR address.

Bit 7 6 5 4 3 2 1 0

BSR[3:0]

Access R/W R/W R/W R/W

Reset 0 0 0 0

Bits 3:0 – BSR[3:0]

Four Most Significant bits of the data memory address

PIC18F26/45/46Q10

Memory Organization

11. (NVM) Nonvolatile Memory Control

Nonvolatile memory is separated into three categories: Program Flash Memory (PFM) including User IDs,

Configuration Words, and Data Flash Memory (DFM). DFM is also referred to as EEPROM because it is

written one byte at a time and the erase before write is automatic. Although User IDs are above the PFM

section they are included in the PFM category because the read and write access is identical for both.

The write and erase times are controlled by an on-chip timer. The write and erase voltages are generated

by an on-chip charge pump rated to function over the operating voltage range of the device.

PFM and DFM can be protected in two ways: code protection and write protection. Code protection

(Configuration bits CP for PFM and CPD for DFM) disables read and write access through an external

device programmer. Code protection does not affect the self-write and erase functionality whereas write

protection does. Code protection write protection can only be reset by a Bulk Erase performed by an

external device programmer. A PFM Bulk Erase clears the program space, Configuration bits, and User

IDs. A Bulk Erase only clears DFM if the CPD = 0. When CPD = 1 then bulk erasing DFM requires setting

the Program Counter to the DFM area before the Bulk Erase command is issued, and then only the DFM

area is cleared. See the programming specification for more details. Write protection prevents writes to

NVM areas tagged for protection by the WRTn Configuration bits. Attempts to write a protected location

will set the NVMERR bit.

PFM and Configuration Words can be accessed by either the Table Pointer or NVM controls. DFM can be

accessed only by the NVM controls. The PFM access is by single byte, single word, or full sector. A

sector is 256 bytes (128 PFM words). The sector memory occupies one full bank of RAM space located in

the RAM bank following the last occupied GPR bank. Sector memory is also referred to elsewhere in this

document as the write block holding registers. The Table Pointer accesses memory by bytes. The NVM

control accesses the DFM section by bytes and the other sections by words and sectors.

The NVM controls include five independent access functions with five corresponding control bits. The

controls are as follows:

• RD – Single byte/word read

• WR – single byte/word write

• SECRD – Sector read

• SECWR – Sector write

• SECER – Sector erase

The NVMADR registers determine the address of the memory region being accessed by the NVM control.

The TBLPTR registers determine the address of the memory being accessed by the Table Pointer

functions. The following table indicates which controls operate in each region.

Table 11-1. NVM Organization Table

Region Address

Range

Table

Pointer

TBLRD

NVMCON1

RD WR SECRD SECWR SECER

PFM 00 0000h

01 FFFFh ●●●●●●

User IDs 20 0000h

20 00FFh ●●●●●●

PIC18F26/45/46Q10

(NVM) Nonvolatile Memory Control

...........continued

Region Address

Range

Table

Pointer

TBLRD

NVMCON1

RD WR SECRD SECWR SECER

CONFIG 30 0000h

30 000Bh ● ● ● ●

DFM 31 0000h

31 00FFh ● ●

11.1 Program Flash Memory

The Program Flash Memory is readable, writable, and erasable during normal operation over the entire

VDD range.

A read from program memory is executed one byte at a time. A program memory erase is executed on

blocks of n bytes at a time, also referred to as sectors. Refer to the following table for write and erase

block sizes. A Bulk Erase operation cannot be issued from user code. A write to program memory can be

executed by sectors or single words.

Table 11-2. Flash Memory Organization by Device

Device Sector Erase

Size (Words)

Holding

Registers

(Bytes)

TBLPTR LSbs

(Holding

Address)

Program Flash

Memory

(Words)

Data Flash

Memory

(Bytes)

PIC18F26Q10

128 256 8

32768 1024

PIC18F46Q10

PIC18F45Q10 16384 256

Writing or erasing program memory will cease instruction fetches until the operation is complete. The

program memory cannot be accessed during the write or erase, therefore, code cannot execute. An

internal programming timer terminates program memory writes and erases.

A value written to program memory does not need to be a valid instruction. Executing a program memory

location that forms an invalid instruction results in a NOP.

It is important to understand the PFM memory structure for erase and programming operations. Program

memory word size is 16 bits wide. PFM is arranged in sectors. A sector is the minimum size that can be

erased by user software.

After a sector has been erased, all or a portion of this sector can be programmed. Data can be written

directly into PFM one 16-bit word at a time using the NVMADR and NVMCON1 controls or as a full sector

from sector RAM, which is also referred to as the holding registers. These 8-bit registers are located in

the RAM bank following the last GPR RAM bank. The holding registers are directly accessible as any

other SFR/GPR register and also may be loaded via sequential writes using the TABLAT and 11.5.7

TBLPTR registers.

PIC18F26/45/46Q10

(NVM) Nonvolatile Memory Control

Important: To modify only a portion of a previously programmed sector the contents of the

entire sector must be read and saved in RAM prior to the sector erase. The SECRD operation is

the easiest way to do this. Then, the new data can be written into the holding registers to

reprogram the sector of PFM. However, any unprogrammed locations can be written using the

single word write operation without first erasing the sector.

11.1.1 Table Pointer Operations

In order to read and write program memory, there are two operations that allow the processor to move

bytes between the program memory space and the data RAM:

• Table Read (TBLRD*)

• Table Write (TBLWT*)

The SFR registers associated with these operations include:

•TABLAT register

•TBLPTR registers

The program memory space is 16 bits wide, while the data RAM space is eight bits wide. The TBLPTR

registers determine the address of one byte of the NVM memory. Table reads move one byte of data from

NVM space to the TABLAT register and table writes move the TABLAT data to a holding register ready for

a subsequent write to NVM space with the NVM controls.

11.1.1.1 Table Pointer Register

The Table Pointer (TBLPTR) register addresses a byte within the program memory. The TBLPTR

comprises three SFR registers: Table Pointer Upper Byte, Table Pointer High Byte and Table Pointer Low

Byte (TBLPTRU:TBLPTRH:TBLPTRL). These three registers join to form a 22-bit wide pointer (bits 0

through 21). The bits 0 through 20 allow the device to address up to 2 Mbytes of program memory space.

Bit 21 allows access to the Device ID, the User ID and the Configuration bits.

The Table Pointer register, TBLPTR, is used by the TBLRD and TBLWT instructions. These instructions

can increment and decrement the TBLPTR depending on specific appended characters as shown in the

following table. The increment and decrement operations on the TBLPTR affect only bits 0 through 20.

Table 11-3. Table Pointer Operations with TBLRD and TBLWT Instructions

Example Operation on Table Pointer

TBLRD*

TBLWT* TBLPTR is not modified

TBLRD*+

TBLWT*+ TBLPTR is incremented after the read/write

TBLRD*-

TBLWT*- TBLPTR is decremented after the read/write

TBLRD+*

TBLWT+* TBLPTR is incremented before the read/write

PIC18F26/45/46Q10

(NVM) Nonvolatile Memory Control

11.1.1.2 Table Latch Register

The Table Latch (TABLAT) is an 8-bit register mapped into the SFR space. The Table Latch register

receives one byte of NVM data resulting from a TBLRD* instruction and is the source of the 8-bit data

sent to the holding register space as a result of a TBLWT* instruction.

11.1.1.3 Table Read Operations

The table read operation retrieves one byte of data directly from program memory pointed to by the

TBLPTR registers and places it into the TABLAT register. Figure 11-1 shows the operation of a table read.

Figure 11-1. Table Read Operation



Table Pointer(1)

Table Latch (8-bit)

Program Memory

TBLPTRH TBLPTRL

TABLAT

TBLPTRU

Instruction: TBLRD*

Note 1: Table Pointer register points to a byte in program memory.

Program Memory

(TBLPTR)

Rev. 30-000002A

3/22/2017

11.1.1.4 Table Write Operations

The table write operation stores one byte of data from the TABLAT register into a sector RAM holding

register. The following figure shows the operation of a table write from the TABLAT register to the holding

register space. The procedure to write the contents of the holding registers into program memory is

detailed in the "Writing to Program Flash Memory" section.

Figure 11-2. Table Write Operation



Table Pointer(1) Table Latch (8-bit)

TBLPTRH TBLPTRL TABLAT

Program Memory

(TBLPTR<MSbs>)

TBLPTRU

Instruction: TBLWT*

Note 1: During table writes the Table Pointer points to two areas. The LSbs of TBLPRTL point to an address

within the sector RAM space. The MSbs of the Table Pointer determine where the sector will eventually

be written.

Program Memory Sector RAM

Rev. 30-000003B6/23/2017

PIC18F26/45/46Q10

(NVM) Nonvolatile Memory Control

Table operations work with byte entities. Tables containing data, rather than program instructions, are not

required to be word-aligned. Therefore, a table can start and end at any byte address. If a table write is

being used to write executable code into program memory, program instructions will need to be word-

aligned.

Related Links

11.1.4 Writing to Program Flash Memory

11.1.1.5 Table Pointer Boundaries

TBLPTR is used in reads, writes and erases of the Program Flash Memory.

When a TBLRD is executed, all 22 bits of the TBLPTR determine which byte is read from program

memory directly into the TABLAT register.

When a TBLWT is executed the byte in the TABLAT register is written, not to Flash memory, but to a

holding register in preparation for a program memory write. The holding registers constitute a write block,

which may vary depending on the device (see the "Flash Memory Organization by Device" table in the

"Program Flash Memory" section). The LSbs of the TBLPTRL register determine which specific address

within the holding register block is written to. The size of the write block determines the number of LSbs.

The MSbs of the Table Pointer have no effect during TBLWT operations.

When a PFM sector write is executed the entire holding register block is written to the Flash memory

sector at the address determined by the MSbs of the NVMADR. The LSbs are ignored during sector

writes. For more detail, see the 11.1.4 Writing to Program Flash Memory section.

The following figure illustrates the relevant boundaries of TBLPTR and NVMADR based on NVM control

operations.

Figure 11-3. Table Pointer Boundaries Based on Operation

21 16 15 8 7 0

TBLPTRL

TBLPTR<n:0>(1)

NVMADR<21:n+1>

(1)

SECTOR ERASE/WRITE

TABLE READ – TBLPTR<21:0>

TABLE WRITE

NVMADRH

NVMADRU

TBLPTRHTBLPTRU

TBLPTRL

Rev. 30-000004B

5/11/2017

Note:

1. See the "Flash Memory Organization by Device" table in the "Program Flash Memory" section for

the write holding registers block size.

Related Links

11.1 Program Flash Memory

PIC18F26/45/46Q10

(NVM) Nonvolatile Memory Control

11.1.1.6 Reading the Program Flash Memory

The TBLRD instruction retrieves data from program memory at the TBLPTR location and places it into the

TABLAT SFR register. Table reads from program memory are performed one byte at a time. In addition,

TBLPTR can be modified automatically for the next table read operation.

The CPU operation is suspended during the read, and it resumes immediately after. From the user point

of view, TABLAT is valid in the next instruction cycle.

The internal program memory is typically organized by words. The Least Significant bit of the address

selects between the high and low bytes of the word. Figure 11-4 shows the interface between the internal

program memory and the TABLAT.

Figure 11-4. Reads from Program Flash Memory



(Even Byte Address)

Program Memory

(Odd Byte Address)

TBLRD TABLAT

TBLPTR = xxxxx1

FETCH

Instruction Register

(IR) Read Register

TBLPTR = xxxxx0

Rev. 30-000006A

3/22/2017

PIC18F26/45/46Q10

(NVM) Nonvolatile Memory Control

Figure 11-5. Program Flash Memory Read Flowchart

Filename: 10-000046B.vsd

Title: FLASH PROGRAM MEMORY READ FLOWCHART

Last Edit: 8/10/2016

First Used: PIC16F1508/9

Note:

Start

Read Operation

Select Word Address

(TBLPTR registers)

Initiate Read operation

(TBLRD)

Data read now in

TABLAT register

End

Read Operation

Rev. 10-000 046B

8/10/201 6

Example 11-1. Reading a Program Flash Memory Word

MOVLW CODE_ADDR_UPPER ; Load TBLPTR with the base

MOVWF TBLPTRU ; address of the word

MOVLW CODE_ADDR_HIGH

MOVWF TBLPTRH

MOVLW CODE_ADDR_LOW

MOVWF TBLPTRL

READ_WORD:

TBLRD*+ ; read into TABLAT and increment

MOVF TABLAT, W ; get data

MOVWF WORD_EVEN

TBLRD*+ ; read into TABLAT and increment

MOVFW TABLAT, W ; get data

MOVF WORD_ODD

11.1.2 NVM Unlock Sequence

The unlock sequence is a mechanism that protects the NVM from unintended self-write programming,

sector reads, and erasing. The sequence must be executed and completed without interruption to

successfully complete any of the following operations:

• PFM sector erase

• PFM sector write from holding registers

• PFM sector read into write block holding registers

• PFM word write directly to NVM

• DFM byte write directly to NVM

• Write to Configuration Words

Each of these operations correspond to one of four unlock code sequences as shown in the following

table:

PIC18F26/45/46Q10

(NVM) Nonvolatile Memory Control

Table 11-4. NVM Unlock Codes

Operation First Unlock Byte Second Unlock Byte NVMCON1

Operation Bit

Word/Byte write 55h AAh WR

Sector write DDh 22h SECWR

Sector erase CCh 33h SECER

Sector read BBh 44h SECRD

The general unlock sequence consists of the following steps and must be completed in order:

• Write first unlock byte to NVMCON2

• Write second unlock byte to NMVCON2

• Set the operation control bit of NVMCON1

For PFM and Configuration Word operations, once the control bit is set the processor will stall internal

operations until the operation is complete and then resume with the next instruction. DFM operations do

not stall the CPU.

Since the unlock sequence must not be interrupted, global interrupts should be disabled prior to the

unlock sequence and re-enabled after the unlock sequence is completed.

Figure 11-6. NVM Unlock Sequence Flowchart



End Unlock Operation

Start Unlock Sequence

Set NVMCON1 control bit to

Initiate write or erase operation

Write first unlock byte

to NVMCON2

Write second unlock byte

to NVMCON2

Rev. 30-000005B

4/27/2017

Example 11-2. NVM Unlock Sequence for PFM word write

BCF INTCON,GIE ; Recommended so sequence is not interrupted

MOVF UpperAddr,W ; set the target address

MOVWF NVMADRU

PIC18F26/45/46Q10

(NVM) Nonvolatile Memory Control

MOVF HighAddr,W

MOVWF NVMADRH

MOVF LowAddr,W

MOVWF NVMADRL

MOVF HighByte,W ; high byte of word to be written

MOVWF NVMDATH ; store in high byte transfer register

MOVF LowByte,W ; low byte of word to be written

MOVWF NVMDATL ; store in low byte transfer register

BSF NVMCON0,NVMEN ; Enable NVM operation

MOVLW 55h ; Load first unlock byte

; –------------------ Required Sequence –-----------------------------

MOVWF NVMCON2 ; Step 1: Load first byte into NVMCON2

MOVLW AAh ; Step 2: Load W with second unlock byte

MOVWF NVMCON2 ; Step 3: Load second byte into NVMCON2

BSF NVMCON1,WR ; Step 4: Set WR bit to begin write

; –-------------------------------------------------------------------

BSF INTCON,GIE ; Re-enable interrupts

Important:

1. Sequence begins when NVMCON2 is written; steps 1-4 must occur in the cycle-accurate

order shown. If the timing of the steps 1 to 4 is corrupted by an interrupt or a debugger

halt, the action will not take place.

2. Opcodes shown are illustrative; any instruction that has the indicated effect may be used.

11.1.3 Erasing Program Flash Memory (PFM)

The minimum erase block is always one sector. Only through the use of an external programmer, or

through ICSP™ control, can larger blocks of program memory be Bulk Erased. Word erase in the Flash

array is not supported.

For example, when initiating an erase sequence from a microcontroller with sector erase size of 128

words, a block of 128 words (256 bytes) of program memory is erased. The NVMADR<21:8> bits point to

the block being erased. The NVMADR<7:0> bits are ignored.

The NVMCON0 and NVMCON1 registers command the erase operation. The NVMEN bit must be set to

enable write operations. The SECER bit is set to initiate the erase operation.

The NVM unlock sequence described in the 11.1.2 NVM Unlock Sequence section must be used, which

guards against accidental writes. This is sometimes referred to as a long write.

A long write is necessary for erasing the internal Flash. Instruction execution is halted during the long

write cycle. The long write is terminated by the internal programming timer.

11.1.3.1 PFM Erase Sequence

The sequence of events for erasing a block of internal program memory is:

1. Set NVMADR to an address within the intended sector.

2. Set the NVMEN bit to enable NVM

3. Perform the unlock sequence as described the 11.1.2 NVM Unlock Sequence section

4. Set the SECER bit

If the PFM address is write-protected, the SECER bit will be cleared and the erase operation will not take

place, NVMERR is signaled in this scenario.

The operation erases the sector indicated by masking the LSbs of the current NVMADR.

PIC18F26/45/46Q10

(NVM) Nonvolatile Memory Control

While erasing PFM, CPU operation is suspended and it resumes when the operation is complete. Upon

completion the SECER bit is cleared in hardware, the NVMIF is set and an interrupt will occur if the

NVMIE bit is also set.

The holding register data are not affected by erase operations and NVMEN will remain unchanged.

Figure 11-7. PFM Sector Erase Flowchart



Unlock Sequence

End Erase Operation

Disable Write/Erase Operation

Load NVMADR registers with

CPU stalls while Erase operation

Disable Interrupts

Enable Interrupts

Enable Write/Erase Operation

Rev/ 30-000007B

5/1/2017

address of the block being erased

Start Erase Operation

completes (10 ms typical)

Select Erase Operation

(GIE = 1)

(NVMEN =1)

(GIE = 1)

(SECER = 1)

Sector Erase

(NVMEN = 0)

Example 11-3. Erasing a Program Flash Memory block

; This sample sector erase routine assumes that the target address

; specified by CODE_ADDR_UPPER and CODE_ADDR_HIGH contain a value within

; the PFM address range of the device.

MOVLW CODE_ADDR_UPPER ; load NVMADR with the base

MOVWF NVMADRU ; address of the memory block

MOVLW CODE_ADDR_HIGH

MOVWF NVMADRH

ERASE_BLOCK:

BSF NVMCON0, NVMEN ; enable Program Flash Memory

BCF INTCON, GIE ; disable interrupts

Required MOVLW CCh ; first unlock byte for erase

PIC18F26/45/46Q10

(NVM) Nonvolatile Memory Control

Sequence MOVWF NVMCON2 ; write CCh

MOVLW 33h ; second unlock byte for erase

MOVWF NVMCON2 ; write 33h

BSF NVMCON1, SECER ; start erase (CPU stalls)

BSF INTCON, GIE ; re-enable interrupts

BCF NVMCON0, NVMEN ; disable writes to memory

Important:

1. If a write or erase operation is terminated by an unexpected event, NVMERR bit will be

set which the user can check to decide whether a rewrite of the location(s) is needed.

2. NVMERR is set if SECER is written to ‘1’ while NVMADR points to a write-protected

address.

3. NVMERR is set if SECER is written to ‘1’ while NVMADR points to an invalid address

location ( Refer to the device memory map and NVM Organization Table).

Related Links

11. (NVM) Nonvolatile Memory Control

11.1.4 Writing to Program Flash Memory

Program memory can be written either one word at a time or a sector at a time.

A single word is written by setting the NVMADR to the target address and loading NVMDAT with the

desired word. The word is then transferred to Flash memory with the WR unlock and write sequence.

A sector is written by first loading a block of holding registers and then executing a sector write sequence.

The programming write block size is specified as the holding registers, also referred to as sector RAM, in

the Flash memory organization by device table. Table writes are used to write the holding register bytes

that are then transferred to Flash memory with the SECWR unlock and write sequence. There are only as

many holding registers as there are bytes in a write block.

Since the table latch (11.5.6 TABLAT) is only a single byte, the TBLWT instruction needs to be executed

multiple times for each sector programming operation. The write protection state is ignored for table

writes. All of the table write operations will essentially be short writes because only the holding registers

are written. NVMIF is not affected while writing to the holding registers.

After all the holding registers have been written, the programming operation of that sector of memory is

started by setting NVMADR to an address within the target sector and executing a sector write unlock

sequence followed immediately by setting the SECWR bit.

If the PFM address in the NVMADR is write-protected, or if NVMADR points to an invalid location, the

SECWR bit is cleared without any effect and the NVMERR is set.

CPU operation is suspended during a long write cycle and resumes when the operation is complete. The

long write operation completes in one extended instruction cycle. When complete, the SECWR or WR bit

is cleared by hardware and NVMIF is set. An interrupt will occur if NVMIE is also set. The holding

registers are unchanged. NVMEN is not changed.

The internal programming timer controls the write time. The write/erase voltages are generated by an on-

chip charge pump, rated to operate over the voltage range of the device.

PIC18F26/45/46Q10

(NVM) Nonvolatile Memory Control

Important: The holding registers are undefined on device Resets and unchanged after write

operations. Individual bytes of program memory may be modified, provided that the modification

does not attempt to change any bit from a ‘0’ to a ‘1’. When modifying individual bytes with a

sector write operation, it is necessary to load all holding registers with either FFh or the existing

contents of memory before executing a long write operation. The fastest way to do this is by

performing a sector read operation.

Figure 11-8. Table Writes to Program Flash Memory



TABLAT

TBLPTR = xxxxYY(1)

TBLPTR = xxxx01TBLPTR = xxxx00

Write Register

TBLPTR = xxxx02

Program Memory

Holding Register Holding Register Holding Register Holding Register

88 8 8

Rev. 30-000008A

3/22/2017

Note: Refer to Flash memory organization by device table for number of holding registers (e.g. YY =

FFh for 256 holding registers).

Related Links

11.1 Program Flash Memory

11.1.4.1 PFM Sector Write Sequence

The sequence of events for programming a block of internal program memory location should be:

1. Set NVMADR with the target sector address.

2. Read the PFM sector into RAM with the SECRD operation.

3. Execute the sector erase procedure (see 11.1.3.1 PFM Erase Sequence).

4. SECER is set as the last step in the erase sequence.

5. The CPU will stall for the duration of the erase (about 10 ms using internal timer).

6. Load TBLPTR with address of first byte being updated.

7. Write the n-byte block into the holding registers with auto-increment. Refer to the Flash memory

organization by device table for the number of holding registers.

8. Disable interrupts.

9. Execute the sector write unlock sequence (see 11.1.2 NVM Unlock Sequence).

10. SECWR bit is set as last step in the unlock sequence.

11. The CPU will stall for the duration of the write (about 10 ms using internal timer).

12. Re-enable interrupts.

13. Verify the memory (table read).

This procedure will require about 20 ms to update each block of memory. See the "Memory Programming

Specifications" for more detail. An example of the required code is given below.

PIC18F26/45/46Q10

(NVM) Nonvolatile Memory Control

Important: Before setting the SECWR bit, the NVMADR value needs to be within the intended

address range of the target PFM sector.

Figure 11-9. Program Flash Memory (PFM) Write Flowchart

Start

Write Operation

End

Write Operation

CPU stalls while Write

operation completes

(10 ms typical)

No delay when writing to

PFM Latches

Determine number of

bytes to be written into

PFM. The number of

bytes cannot exceed the

number of bytes per

sector (byte_cnt)

Last byte written?

Set NVMADR to address

within target sector

Perform SECRD operation

Erase target PFM sector

with SECER operation

Load TABLAT with the

value to write

Update the byte counter

(byte_cnt--)

Disable NVM

(NVMEN = 0)

Yes

No

Rev. 10-000049D

12/15/2017

Write byte to sector RAM

with TBLWT*+

Set TBLPTR to PFM

address of first byte

Disable Interrupts

(GIE = 0)

Perform SECWR operation

Re-enable Interrupts

(GIE = 1)

CPU stalls while Erase

operation completes

(10 ms typical)

Example 11-4. Writing a Sector of Program Flash Memory

; Code sequence to modify one word in a programmed sector of PFM

; Calling routine should check WREG for the following errors:

;

; 00h = Successful modification

; 01h = Read error

; 02h = Erase error

; 03h = Write error

;

READ_BLOCK:

MOVLW CODE_ADDR_UPPER ; load NVMADR with the base

MOVWF NVMADRU ; address of the memory sector

MOVLW CODE_ADDR_HIGH

PIC18F26/45/46Q10

(NVM) Nonvolatile Memory Control

MOVWF NVMADRH

MOVLW CODE_ADDR_LOW

MOVWF NVMADRL

BCF INTCON, GIE ; disable interrupts

BSF NVMCON0, NVMEN ; enable NVM

; ----- Required Sequence -----

MOVLW 0BBh

MOVWF NVMCON2 ; first unlock byte = 0BBh

MOVLW 44h

MOVWF NVMCON2 ; second unlock byte = 44h

BSF NVMCON1, SECRD ; start sector read (CPU stall)

; ------------------------------

BTFSC NVMCON0, NVMERR ; Verify no error occurred during read

BRA NVM_RDERR ; return read error code

ERASE_BLOCK: ; NVMADR is already pointing to target

block

; ----- Required Sequence -----

MOVLW 0CCh

MOVWF NVMCON2 ; first unlock byte = 0CCh

MOVLW 33h

MOVWF NVMCON2 ; second unlock byte = 33h

BSF NVMCON1, SECER ; start sector erase (CPU stall)

; ------------------------------

BTFSC NVMCON0, NVMERR ; Verify no error occurred during erase

BRA NVM_ERERR ; return erase error code

MODIFY_WORD:

MOVLW TARGET_ADDR_UPPER ; load TBLPTR with the target address

MOVWF TBLPTRU ; of the LSByte

MOVLW TARGET_ADDR_HIGH

MOVWF TBLPTRH

MOVLW TARGET_ADDR_LOW

MOVWF TBLPTRL

MOVLW NEW_DATA_LOW ; update holding register

MOVWF TABLAT

TBLWT*+

MOVLW NEW_DATA_HIGH

MOVWF TABLAT

TBLWT*+

PROGRAM_MEMORY: ; NVMADR is already pointing to target

block

; ----- Required Sequence -----

MOVLW 0DDh

MOVWF NVMCON2 ; first unlock byte = 0DDh

MOVLW 22h

MOVWF NVMCON2 ; second unlock byte = 22h

BSF NVMCON1, SECWR ; start sector programming (CPU stall)

; ------------------------------

BTFSC NVMCON0, NVMERR ; Verify no error occurred during write

BRA NVM_WRERR ; return sector write error code

CLRF WREG,F ; return with no error

BRA NVM_EXIT

NVM_RDERR:

MOVLW 01h

BRA NVM_EXIT

NVM_ERERR:

MOVLW 02h

BRA NVM_EXIT

NVM_WRERR:

MOVLW 03h

NVM_EXIT:

BCF NVMCON0, NVMEN ; disable NVM

BSF INTCON, GIE ; re-enable interrupts

RETURN

Related Links

39.3.5 Memory Programming Specifications

11.1.4.2 PFM Word Write Sequence

The sequence of events for programming an erased single word of internal program memory location

should be:

1. Set NVMADR with the target word address.

PIC18F26/45/46Q10

(NVM) Nonvolatile Memory Control

2. Load NVMDAT with desired word.

3. Disable interrupts.

4. Execute the word/byte write unlock sequence (see 11.1.2 NVM Unlock Sequence).

5. WR bit is set as last step in the unlock sequence.

6. The CPU will stall for the duration of the write (about 50 μs using internal timer).

7. Re-enable interrupts.

8. Verify the memory (word read).

Example 11-5. Writing a Word of Program Flash Memory

; Code sequence to program one erased word of PFM

; Target address is in WORD_ADDR_UPPER:WORD_ADDR_HIGH:WORD_ADDR_LOW

; Target data is in WORD_HIGH_BYTE:WORD_LOW_BYTE

; Calling routine should check WREG for the following errors:

;

; 00h = Successful modification

; 03h = Write error

;

WORD_WRITE:

MOVF WORD_ADDR_UPPER, W ; load NVMADR with the target

MOVWF NVMADRU ; address of the word

MOVF WORD_ADDR_HIGH, W

MOVWF NVMADRH

MOVF WORD_ADDR_LOW, W

MOVWF NVMADRL

MOVF WORD_HIGH_BYTE, W ; load NVMDAT with desired

MOVWF NVMDATH ; word

MOVF WORD_LOW_BYTE, W

MOVWF NVMDATL

BCF INTCON, GIE ; disable interrupts

BSF NVMCON0, NVMEN ; enable NVM

PROGRAM_WORD:

; ----- Required Sequence -----

MOVLW 055h

MOVWF NVMCON2 ; first unlock byte = 055h

MOVLW 0AAh

MOVWF NVMCON2 ; second unlock byte = 0AAh

BSF NVMCON1, WR ; start word programming (CPU stall)

; ------------------------------

BTFSC NVMCON0, NVMERR ; Verify no error occurred during write

BRA NVM_WRERR ; return sector write error code

VERIFY_WORD:

BSF NVMCON0, RD ; Retrieve word from PFM

MOVF WORD_HIGH_BYTE, W ; Verify high byte

CPFSEQ NVMDATH

BRA NVM_RDERR ; not equal - return error code

MOVF WORD_LOW_BYTE, W ; Verify low byte

CPFSEQ NVMDATL

BRA NVM_RDERR ; not equal - return error code

CLRF WREG,F ; return with no error

BRA NVM_EXIT

NVM_RDERR:

MOVLW 01h

BRA NVM_EXIT

NVM_WRERR:

MOVLW 03h

NVM_EXIT:

BCF NVMCON0, NVMEN ; disable NVM

BSF INTCON, GIE ; re-enable interrupts

RETURN

11.1.4.3 Write Verify

Depending on the application, good programming practice may dictate that the value written to the

memory should be verified against the original value. This should be used in applications where

excessive writes can stress bits near the specification limit. Since program memory is stored as a full

PIC18F26/45/46Q10

(NVM) Nonvolatile Memory Control

page, the stored program memory contents are compared with the intended data stored in sector RAM

after the last write is complete.

Figure 11-10. Program Flash Memory Verify Flowchart

Filename: 10-000051B.vsd

Title: FLASH PROGRAM MEMORY VERIFY FLOWCHART

Last Edit: 12/4/2015

First Used: PIC18(L)F2x/4xK40

Note: 1: Refer to Figure 11-5, Program Flash Memory Read Flowchart

Start

Verify Operation

This routine assumes that the last

row of data written was from an

image saved on RAM. This image

will be used to verify the data

currently stored in PFM

Fail

Verify Operation

Last word ?

NVMDAT =

RAM image ?

Read Operation(1)

End

Verify Operation

No

Yes

Rev. 10-000051B

12/4/2015

11.1.4.4 Unexpected Termination of Write Operation

If a write is terminated by an unplanned event, such as loss of power or an unexpected Reset, the

memory location just programmed should be verified and reprogrammed if needed. If the write operation

is interrupted by a MCLR Reset or a WDT Time-out Reset during normal operation, the NVMERR bit will

be set which the user can check to decide whether a rewrite of the location(s) is needed.

11.1.4.5 Protection Against Spurious Writes

A write sequence is valid only when both the following conditions are met. This prevents spurious writes

that might lead to data corruption.

1. The WR, RD, SECWR, SECRD, and SECER bits are gated through the NVMEN bit. It is suggested

to have the NVMEN bit cleared at all times except during memory writes and reads. This prevents

memory operations if any of the control bits are set accidentally.

2. The NVM unlock sequence must be performed each time before all but the RD operation.

PIC18F26/45/46Q10

(NVM) Nonvolatile Memory Control

11.2 User ID, Device ID and Configuration Word Access

The NVMADR value determines which NVM address space is accessed. The User IDs and Configuration

Words areas allow read and write whereas Device and Revision IDs allow read-only (see NVM

organization table).

Reading and writing User ID space is identical to writing to PFM space as described in the preceding

paragraphs.

Writing to the Configuration space can only be done with the SECWR operation. A sector erase operation

on Configuration space cannot be performed with the SECER operation. When a SECWR operation is

performed on the Configuration space a sector erase is performed automatically before the sector write.

Any code protection settings that are not enabled will remain not enabled after the sector write operation

unless the new values enable them. However, any code protection settings that are enabled cannot be

disabled by a self-write of the Configuration space. The user can modify the Configuration space by the

following steps:

1. Read Configuration space with the unlock and SECRD sequence.

2. Modify the desired Configuration Word holding registers using TBLPTR address, TABLAT data, and

TBLWT* instruction.

3. Write the holding registers to Configuration space with the unlock and SECWR sequence.

Related Links

11. (NVM) Nonvolatile Memory Control

11.3 Data Flash Memory (DFM)

The data Flash memory is a nonvolatile memory array, also referred to as EEPROM. The DFM is

separate from the Program Flash Memory, which is used for long-term storage of program data. The DFM

is mapped above program memory space and is indirectly addressed through the NVM Special Function

Registers (SFRs). The DFM is readable and writable during normal operation over the entire VDD range.

Five SFRs are used to read and write to the data DFM. They are:

• NVMCON0

• NVMCON1

• NVMCON2

• NVMDAT

• NVMADR

The DFM can only be read and written one byte at a time. When interfacing to the data memory block,

NVMDATL holds the 8-bit data for read/write and the 11.5.5 NVMADR register holds the address of the

DFM location being accessed.

The DFM is rated for high erase/write cycle endurance. A byte write automatically erases the location and

writes the new data (erase-before-write). The write time is controlled by an internal programming timer; it

will vary with voltage and temperature as well as from chip-to-chip. Refer to the data EEPROM memory

parameters in the electrical specifications section for the limits.

Related Links

39.3.5 Memory Programming Specifications

PIC18F26/45/46Q10

(NVM) Nonvolatile Memory Control

11.3.1 Reading the DFM

To read a DFM location, the user must write the address to the NVMADR register, enable NVM control by

setting the NVMEN bit, and then set the RD control bit. The data is available on the very next instruction

cycle; therefore, the NVMDAT register can be read by the next instruction. NVMDAT will hold this value

until another read operation, or until it is written to by the user (during a write operation).

The basic process is shown in the following flowchart.

Figure 11-11. DFM Read Flowchart

End Read Operation

Initiate Read Operation

(RD = 1)

Data read now in

NVMDAT

Rev. 30-000009B

5/10/2017

Select Word Address

(NVMADRU:NVMADRH:NVMADRL)

Start Read Operation

Example 11-6. DFM Read

; Data Flash Memory Address to read

BSF NVMCON0, NVMEN ; Enable NVM

MOVF DFM_ADDRL, W ;

MOVWF NVMADRL ; Setup Address low byte

MOVF DFM_ADDRH, W ;

MOVWF NVMADRH ; Setup Address high byte

MOVF DFM_ADDRU, W ;

MOVWF NVMADRU ; Setup Address upper byte

BSF NVMCON1, RD ; Issue EE Read

MOVF NVMDAT, W ; W = EE_DATA

BCF NVMCON0, NVMEN ; Disable NVM

Only byte reads are supported for DFM. Reading a block of DFM with a SECRD operation is not

supported.

11.3.2 Writing to DFM

To write a DFM location, the address must first be written to the NVMADR register and the data written to

the NVMDATL register. The sequence shown in 11.1.2 NVM Unlock Sequence must be followed to

initiate the write cycle. Block writes, also referred to as sector writes, are not supported for the DFM.

The write will not begin if NVM Unlock sequence is not exactly followed for each byte. It is strongly

recommended that interrupts be disabled during this code segment.

Additionally, the NVMEN bit must be set to enable NVM control. This mechanism prevents accidental

writes to DFM due to unexpected code execution (i.e., runaway programs). The NVMEN bit should be

kept clear at all times, except when updating the DFM. The NVMEN bit is not cleared by hardware.

PIC18F26/45/46Q10

(NVM) Nonvolatile Memory Control

After a write sequence has been initiated, NVMCON1, NVMADR and NVMDAT cannot be modified. The

WR bit will be inhibited from being set unless the NVMEN bit is set.

After a write sequence has been initiated, clearing the NVMEN bit will not affect this write cycle. A single

DFM byte is written and the operation includes an implicit erase cycle for that word. CPU execution

continues in parallel and at the completion of the write cycle, the WR bit is cleared in hardware and the

NVM Interrupt Flag bit (NVMIF) is set. The user can either enable this interrupt or poll this bit. NVMIF

must be cleared by software.

Example 11-7. DFM Write

; Data Flash Memory Address to write

MOVF DFM_ADDRL, W ;

MOVWF NVMADRL ; Setup Address low byte

MOVF DFM_ADDRH, W ;

MOVWF NVMADRH ; Setup Address high byte

MOVF DFM_ADDRU, W ;

MOVWF NVMADRU ; Setup Address upper byte

; Data Memory Value to write

MOVF DMF_DATA, W ;

MOVWF NVMDATL ;

; Enable writes

BSF NVMCON0, NVMEN ; Enable NVM

; Disable interrupts

BCF INTCON, GIE ;

; –------- Required Sequence –--------

MOVLW 55h ;

MOVWF NVMCON2 ;

MOVLW AAh ;

MOVWF NVMCON2 ;

BSF NVMCON1, WR ; Set WR bit to begin write

; –------------------------------------

; Wait for write to complete

BTFSC NVMCON1, WR ; DFM writes do not stall the CPU

BRA $-2

; Enable INT

BSF INTCON, GIE ;

; Disable writes

BCF NVMCON0, NVMEN ;

11.3.3 DFM Write Verify

Depending on the application, good programming practice may dictate that the value written to the

memory should be verified against the original value. This should be used in applications where

excessive writes can stress bits near the specification limit.

11.3.4 Operation During Code-Protect and Write-Protect

DFM has its own code-protect bits in the Configuration Words. In-Circuit Serial Programming read and

write operations are disabled when code protection is enabled. However, internal reads operate normally.

Internal writes operate normally provided that write protection is not enabled.

If the DFM is write-protected or if NVMADR points at an invalid address location, the WR bit is cleared

without any effect. NVMERR is signaled in this scenario.

11.3.5 Protection Against Spurious Write

There are conditions when the user may not want to write to the DFM. To protect against spurious DFM

writes, various mechanisms have been implemented. On any Reset, the NVMEN bit is cleared. In

addition, writes to the DFM are blocked during the Power-up Timer period (TPWRT).

The unlock sequence and the NVMEN bit together help prevent an accidental write during brown-out,

power glitch or software malfunction.

PIC18F26/45/46Q10

(NVM) Nonvolatile Memory Control

11.3.6 Erasing the DFM

DFM can be erased by writing 0xFF to all locations in the memory that need to be erased.

Example 11-8. DFM Erase Routine

CLRF NVMADRL ; Clear address low byte

CLRF NVMADRH ; Clear address high byte

MOVLW 31h ; EEPROM upper address

MOVWF NVMADRU ; Set address upper byte

SETF NVMDAT ; Load 0xFF to data register

BCF INTCON, GIE ; Disable interrupts

BSF NVMCON0, NVMEN ; Enable NVM

Loop: ; Loop to refresh array

MOVLW 0x55 ; Initiate unlock sequence

MOVWF NVMCON2 ;

MOVLW 0xAA ;

MOVWF NVMCON2 ;

BSF NVMCON1, WR ; Set WR bit to begin write

BTFSC NVMCON1, WR ; Wait for write to complete

BRA $-2

INCFSZ NVMADRL, F ; Increment address low byte

BRA Loop ; Not zero, do it again

; The following 4 lines of code are not needed if EEPROM is 256 bytes or less

INCF NVMADRH, F ; Decrement address high byte

MOVLW 0x03 ; Move 0x03 to working register

CPFSGT NVMADRH ; Compare address high byte with working

register

BRA Loop ; Skip if greater than working register

; Else go back to erase loop

BCF NVMCON0, NVMEN ; Disable NVM

BSF INTCON, GIE ; Enable interrupts

PIC18F26/45/46Q10

(NVM) Nonvolatile Memory Control

11.4 Register Summary: NVM Control

Address Name Bit Pos.

0x0F79 NVMADR

7:0 NVMADRL[7:0]

15:8 NVMADRH[7:0]

23:16 NVMADRU[5:0]

0x0F7C NVMDAT

7:0 NVMDATL[7:0]

15:8 NVMDATH[7:0]

0x0F7E Reserved

0x0F7F NVMCON0 7:0 NVMEN NVMERR Reserved

0x0F80 NVMCON1 7:0 SECER SECWR WR SECRD RD

0x0F81 NVMCON2 7:0 NVMCON2[7:0]

0x0F82

...

0x0FF4

Reserved

0x0FF5 TABLAT 7:0 TABLAT[7:0]

0x0FF6 TBLPTR

7:0 TBLPTRL[7:0]

15:8 TBLPTRH[7:0]

23:16 TBLPTR21 TBLPTRU[4:0]

11.5 Register Definitions: Nonvolatile Memory

PIC18F26/45/46Q10

(NVM) Nonvolatile Memory Control

11.5.1 NVMCON0

Name: NVMCON0

Address: 0xF7F

Nonvolatile Memory Control 0 Register

Bit 7 6 5 4 3 2 1 0

NVMEN NVMERR Reserved

Access R/W R/W/HS R/W

Reset 0 x 0

Bit 7 – NVMEN NVM Enable bit

Value Description

1NVM is enabled for all operations

0NVM is disabled for all operations except single byte or word read.

Bit 4 – NVMERR

NVM Error Flag bit

Value Description

1An attempted NVM write or sector read did not complete successfully. Must be cleared by

software.

0All NVM operations have completed successfully.

Bit 3 – Reserved

Reserved - Do not use. This bit must be maintained as ‘0’.

PIC18F26/45/46Q10

(NVM) Nonvolatile Memory Control

11.5.2 NVMCON1

Name: NVMCON1

Address: 0xF80

Nonvolatile Memory Control 1 Register

Bit 7 6 5 4 3 2 1 0

SECER SECWR WR SECRD RD

Access R/S/HC R/S/HC R/S/HC R/S/HC R/S/HC

Reset 0 0 0 0 0

Bit 6 – SECER

NVM Sector Erase Enable Control bit

Value Condition Description

1NVMADR points to PFM Immediately following the sector erase unlock sequence, perform a

sector erase operation. Stays set until operation is complete.

Cannot be cleared by software.

0NVMADR points to PFM NVM sector erase operation is complete and inactive.

Bit 5 – SECWR

NVM Sector Write Enable Control bit

Value Condition Description

1NVMADR points to PFM or

CONFIG

Immediately following the sector write unlock sequence,

initiates the PFM sector write operation. Stays set until the

write is complete. Cannot be cleared by software.

0NVMADR points to PFM or

CONFIG

NVM sector write operation is complete and inactive.

Bit 4 – WR

NVM Write Control bit

Value Condition Description

1NVMADR points to

DFM

Immediately following the DFM write unlock sequence, initiates a

DFM byte erase/write sequence using data in the NVMDATL register.

Stays set until the operation is complete. Cannot be cleared by

software.

1NVMADR points to

PFM

Immediately following the PFM write unlock sequence, initiates an

NVM word write sequence using data in the NVMDATH:L register

pair. Stays set until the operation is complete. Cannot be cleared by

software.

0NVMADR points to

PFM or DFM

NVM byte/word write operation is complete and inactive.

Bit 1 – SECRD

PFM Sector Read Enable Control bit

Value Condition Description

1NVMADR points to PFM or

CONFIG

Immediately following the sector read unlock sequence, initiates

a read of one full sector from PFM into sector RAM. Stays set

until the read is complete. Cannot be cleared by software.

PIC18F26/45/46Q10

(NVM) Nonvolatile Memory Control

Value Condition Description

0NVMADR points to PFM or

CONFIG

PFM sector read operation is complete and inactive.

Bit 0 – RD

NVM Read Enable Control bit

Value Condition Description

1NVMADR points to DFM Initiates a read of one byte from DFM into the NVMDATL register.

Stays set until the read is complete. Cannot be cleared by

software.

1NVMADR points to PFM Initiates a read of one word from PFM into the NVMDATH:L

registers. Stays set until the read is complete. Cannot be cleared

by software.

0NVMADR points to PFM

or DFM

NVM read operation is complete and inactive.

PIC18F26/45/46Q10

(NVM) Nonvolatile Memory Control

11.5.3 NVMCON2

Name: NVMCON2

Address: 0xF81

Nonvolatile Memory Control 2 Register

Note: This register always reads zeros, regardless of data written.

Refer to the NVM Unlock Sequence section

Bit 7 6 5 4 3 2 1 0

NVMCON2[7:0]

Access WO WO WO WO WO WO WO WO

Reset 0 0 0 0 0 0 0 0

Bits 7:0 – NVMCON2[7:0]

PIC18F26/45/46Q10

(NVM) Nonvolatile Memory Control

11.5.4 NVMDAT

Name: NVMDAT

Address: 0xF7C

NVM Data Register

Bit 15 14 13 12 11 10 9 8

NVMDATH[7:0]

Access R/W R/W R/W R/W R/W R/W R/W R/W

Reset 0 0 0 0 0 0 0 0

Bit 7 6 5 4 3 2 1 0

NVMDATL[7:0]

Access R/W R/W R/W R/W R/W R/W R/W R/W

Reset 0 0 0 0 0 0 0 0

Bits 15:8 – NVMDATH[7:0]

NVMDAT Most Significant Byte of data written to and read from PFM.

Bits 7:0 – NVMDATL[7:0]

NVMDAT Least Significant Byte of data written to and read from PFM or DFM.

PIC18F26/45/46Q10

(NVM) Nonvolatile Memory Control

11.5.5 NVMADR

Name: NVMADR

Address: 0xF79

NVM Address Register

Bit 23 22 21 20 19 18 17 16

NVMADRU[5:0]

Access R/W R/W R/W R/W R/W R/W

Reset 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8

NVMADRH[7:0]

Access R/W R/W R/W R/W R/W R/W R/W R/W

Reset 0 0 0 0 0 0 0 0

Bit 7 6 5 4 3 2 1 0

NVMADRL[7:0]

Access R/W R/W R/W R/W R/W R/W R/W R/W

Reset 0 0 0 0 0 0 0 0

Bits 21:16 – NVMADRU[5:0]

NVM address bits <21:16> .

Bits 15:8 – NVMADRH[7:0]

High byte of NVM address.

Bits 7:0 – NVMADRL[7:0]

Low byte of NVM address.

PIC18F26/45/46Q10

(NVM) Nonvolatile Memory Control

11.5.6 TABLAT

Name: TABLAT

Address: 0xFF5

Program, Configuration, Device ID, and User ID Memory Data

Bit 7 6 5 4 3 2 1 0

TABLAT[7:0]

Access R/W R/W R/W R/W R/W R/W R/W R/W

Reset 0 0 0 0 0 0 0 0

Bits 7:0 – TABLAT[7:0] The value of the NVM memory byte returned from the address contained in

TBLPTR after a TBLRD command, or the data written to the latch by a TBLWT command.

PIC18F26/45/46Q10

(NVM) Nonvolatile Memory Control

11.5.7 TBLPTR

Name: TBLPTR

Address: 0xFF6

Program, Configuration, Device ID and User ID Memory Address

Bit 23 22 21 20 19 18 17 16

TBLPTR21 TBLPTRU[4:0]

Access R/W R/W R/W R/W R/W R/W

Reset 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8

TBLPTRH[7:0]

Access R/W R/W R/W R/W R/W R/W R/W R/W

Reset 0 0 0 0 0 0 0 0

Bit 7 6 5 4 3 2 1 0

TBLPTRL[7:0]

Access R/W R/W R/W R/W R/W R/W R/W R/W

Reset 0 0 0 0 0 0 0 0

Bit 21 – TBLPTR21 NVM Most Significant Address bit

Value Description

1Access Configuration, User ID, Device ID, and Revision ID spaces

0Access Program Flash Memory space

Bits 20:16 – TBLPTRU[4:0] NVM Upper Address bits

Bits 15:8 – TBLPTRH[7:0] High Byte of NVM Address bits

Bits 7:0 – TBLPTRL[7:0] Low Byte of NVM Address bits

PIC18F26/45/46Q10

(NVM) Nonvolatile Memory Control

12. 8x8 Hardware Multiplier

12.1 Introduction

All PIC18 devices include an 8x8 hardware multiplier as part of the ALU. The multiplier performs an

unsigned operation and yields a 16-bit result that is stored in the product register pair, PRODH:PRODL.

The multiplier’s operation does not affect any flags in the STATUS register.

Making multiplication a hardware operation allows it to be completed in a single instruction cycle. This

has the advantages of higher computational throughput and reduced code size for multiplication

algorithms and allows the PIC18 devices to be used in many applications previously reserved for digital

signal processors. A comparison of various hardware and software multiply operations, along with the

savings in memory and execution time, is shown in Table 12-1.

12.2 Operation

Example 12-1 shows the instruction sequence for an 8x8 unsigned multiplication. Only one instruction is

required when one of the arguments is already loaded in the WREG register.

Example 12-2 shows the sequence to do an 8x8 signed multiplication. To account for the sign bits of the

arguments, each argument’s Most Significant bit (MSb) is tested and the appropriate subtractions are

done.

Example 12-1. 8x8 Unsigned Multiply Routine

MOVF ARG1, W ;

MULWF ARG2 ; ARG1 * ARG2 -> PRODH:PRODL

Example 12-2. 8x8 Signed Multiply Routine

MOVF ARG1, W

MULWF ARG2 ; ARG1 * ARG2 -> PRODH:PRODL

BTFSC ARG2, SB ; Test Sign Bit

SUBWF PRODH, F ; PRODH = PRODH - ARG1

MOVF ARG2, W

BTFSC ARG1, SB ; Test Sign Bit

SUBWF PRODH, F ; PRODH = PRODH - ARG2

Table 12-1. Performance Comparison for Various Multiply Operations

Routine Multiply Method

Program

Memory

(Words)

Cycles

(Max)

Time

@ 64 MHz @ 40 MHz @ 10 MHz @ 4 MHz

8x8 unsigned

Without hardware

multiply

13 69 4.3 μs 6.9 μs 27.6 μs 69 μs

Hardware multiply 1 1 62.5 ns 100 ns 400 ns 1 μs

PIC18F26/45/46Q10

8x8 Hardware Multiplier

...........continued

Routine Multiply Method

Program

Memory

(Words)

Cycles

(Max)

Time

@ 64 MHz @ 40 MHz @ 10 MHz @ 4 MHz

8x8 signed

Without hardware

multiply

33 91 5.7 μs 9.1 μs 36.4 μs 91 μs

Hardware multiply 6 6 375 ns 600 ns 2.4 μs 6 μs

16x16 unsigned

Without hardware

multiply

21 242 15.1 μs 24.2 μs 96.8 μs 242 μs

Hardware multiply 28 28 1.8 μs 2.8 μs 11.2 μs 28 μs

16x16 signed

Without hardware

multiply

52 254 15.9 μs 25.4 μs 102.6 μs 254 μs

Hardware multiply 35 40 2.5 μs 4.0 μs 16.0 μs 40 μs

Example 12-3 shows the sequence to do a 16 x 16 unsigned multiplication. The equation below shows

the algorithm that is used. The 32-bit result is stored in four registers (RES<3:0>).

16 x 16 Unsigned Multiplication Algorithm

3:0 = 1:1•2:2=1•2• 216 +1•2• 28+

1•2• 28+1•2

Example 12-3. 16 x 16 Unsigned Multiply Routine

MOVF ARG1L, W

MULWF ARG2L ; ARG1L * ARG2L → PRODH:PRODL

MOVFF PRODH, RES1 ;

MOVFF PRODL, RES0 ;

;

MOVF ARG1H, W ;

MULWF ARG2H ; ARG1H * ARG2H → PRODH:PRODL

MOVFF PRODH, RES3 ;

MOVFF PRODL, RES2 ;

;

MOVF ARG1L, W

MULWF ARG2H ; ARG1L * ARG2H → PRODH:PRODL

MOVF PRODL, W ;

ADDWF RES1, F ; Add cross products

MOVF PRODH, W ;

ADDWFC RES2, F ;

CLRF WREG ;

ADDWFC RES3, F ;

;

MOVF ARG1H, W ;

MULWF ARG2L ; ARG1H * ARG2L → PRODH:PRODL

MOVF PRODL, W ;

ADDWF RES1, F ; Add cross products

MOVF PRODH, W ;

ADDWFC RES2, F ;

CLRF WREG ;

ADDWFC RES3, F ;

Example 12-4 shows the sequence to do a 16 x 16 signed multiply. The equation below shows the

algorithm used. The 32-bit result is stored in four registers (RES<3:0>). To account for the sign bits of the

arguments, the MSb for each argument pair is tested and the appropriate subtractions are done.

PIC18F26/45/46Q10

8x8 Hardware Multiplier

16 x 16 Signed Multiplication Algorithm

3:0 = 1:1•2:2=1•2• 216 +1•2• 28+

1•2• 28+1•2+1 • 2< 7 > • 1:1• 216 +1

•1< 7 > • 2:2• 216

Example 12-4. 16 x 16 Signed Multiply Routine

MOVF ARG1L, W

MULW ARG2L ; ARG1L * ARG2L → PRODH:PRODL

MOVF PRODH, RES1 ;

MOVFF PRODL, RES0 ;

;

MOVF ARG1H, W

MULWF ARG2H ; ARG1H * ARG2H → PRODH:PRODL

MOVFF PRODH, RES3 ;

MOVFF PRODL, RES2 ;

;

MOVF ARG1L, W

MULWF ARG2H ; ARG1L * ARG2H → PRODH:PRODL

MOVF PRODL, W ;

ADDWF RES1, F ; Add cross products

MOVF PRODH, W ;

ADDWFC RES2, F ;

CLRF WREG ;

ADDWFC RES3, F ;

;

MOVF ARG1H, W ;

MULWF ARG2L ; ARG1H * ARG2L → PRODH:PRODL

MOVF PRODL, W ;

ADDWF RES1, F ; Add cross products

MOVF PRODH, W ;

ADDWFC RES2, F ;

CLRF WREG ;

ADDWFC RES3, F ;

;

BTFSS ARG2H, 7 ; ARG2H:ARG2L neg?

BRA SIGN_ARG1 ; no, check ARG1

MOVF ARG1L, W ;

SUBWF RES2 ;

MOVF ARG1H, W ;

SUBWFB RES3

;

SIGN_ARG1:

BTFSS ARG1H, 7 ; ARG1H:ARG1L neg?

BRA CONT_CODE ; no, done

MOVF ARG2L, W ;

SUBWF RES2 ;

MOVF ARG2H, W ;

SUBWFB RES3

;

CONT_CODE:

:

PIC18F26/45/46Q10

8x8 Hardware Multiplier

12.3 Register Summary - 8x8 Hardware Multiplier

Address Name Bit Pos.

0x0FF3 PROD

7:0 PRODL[7:0]

15:8 PRODH[7:0]

12.4 Register Definitions: 8x8 Hardware Multiplier

PIC18F26/45/46Q10

8x8 Hardware Multiplier

12.4.1 PROD

Name: PROD

Address: 0xFF3

Product Register Pair

The PROD register stores the 16-bit result yielded by the unsigned operation performed by the 8x8

hardware multiplier.

Bit 15 14 13 12 11 10 9 8

PRODH[7:0]

Access R/W R/W R/W R/W R/W R/W R/W R/W

Reset x x x x x x x x

Bit 7 6 5 4 3 2 1 0

PRODL[7:0]

Access R/W R/W R/W R/W R/W R/W R/W R/W

Reset x x x x x x x x

Bits 15:8 – PRODH[7:0]

PROD Most Significant bits

Bits 7:0 – PRODL[7:0]

PROD Least Significant bits

PIC18F26/45/46Q10

8x8 Hardware Multiplier

13. (CRC) Cyclic Redundancy Check Module with Memory Scanner

The Cyclic Redundancy Check (CRC) module provides a software-configurable hardware-implemented

CRC checksum generator. This module includes the following features:

• Any standard CRC up to 16 bits can be used

• Configurable Polynomial

• Any seed value up to 16 bits can be used

• Standard and reversed bit order available

• Augmented zeros can be added automatically or by the user

• Memory scanner for fast CRC calculations on program memory user data

• Software loadable data registers for communication CRC’s

13.1 CRC Module Overview

The CRC module provides a means for calculating a check value of program memory. The CRC module

is coupled with a memory scanner for faster CRC calculations. The memory scanner can automatically

provide data to the CRC module. The CRC module can also be operated by directly writing data to SFRs,

without using a scanner.

13.2 CRC Functional Overview

The CRC module can be used to detect bit errors in the Flash memory using the built-in memory scanner

or through user input RAM memory. The CRC module can accept up to a 16-bit polynomial with up to a

16-bit seed value. A CRC calculated check value (or checksum) will then be generated into the 13.12.4

CRCACC registers for user storage. The CRC module uses an XOR shift register implementation to

perform the polynomial division required for the CRC calculation.

PIC18F26/45/46Q10

(CRC) Cyclic Redundancy Check Module with Me...

Figure 13-1. CRC Example

Filename: 10-000206A.vsd

Title: CRC EXAMPLE

Last Edit: 1/8/2014

First Used: PIC16(L)F1613

Notes:

Rev. 10-000206A

1/8/2014

CRC-16-ANSI

x16 + x15 + x2+ 1 (17 bits)

CRCXORH = 0b10000000

CRCXORL = 0b0000010- (1)

Standard 16-bit representation = 0x8005

Data Sequence:

0x55, 0x66, 0x77, 0x88

Check Value (ACCM = 1):

SHIFTM = 0: 0x32D6

CRCACCH = 0b00110010

CRCACCL = 0b11010110

SHIFTM = 1: 0x6BA2

CRCACCH = 0b01101011

CRCACCL = 0b10100010

DLEN = 0b0111

PLEN = 0b1111

Data entered into the CRC:

SHIFTM = 0:

01010101 01100110 01110111 10001000

SHIFTM = 1:

10101010 01100110 11101110 00010001

Note 1: Bit 0 is unimplemented. The LSb of any

CRC polynomial is always ‘1’ and will always

be treated as a ‘1’ by the CRC for calculating

the CRC check value. This bit will be read in

software as a ‘0’.

13.3 CRC Polynomial Implementation

Any polynomial can be used. The polynomial and accumulator sizes are determined by the PLEN bits.

For an n-bit accumulator, PLEN = n-1 and the corresponding polynomial is n+1 bits. Therefore, the

accumulator can be any size up to 16 bits with a corresponding polynomial up to 17 bits. The MSb and

LSb of the polynomial are always ‘1’ which is forced by hardware. However, the LSb of the CRCXORL

register is unimplemented and always reads as '0'.

All polynomial bits between the MSb and LSb are specified by the 13.12.6 CRCXOR registers. For

example, when using CRC16-ANSI, the polynomial is defined as X16+X15+X2+1. The X16 and X0 = 1

terms are the MSb and LSb controlled by hardware. The X15 and X2 terms are specified by setting the

corresponding CRCXOR<15:0> bits with the value of 0x8004. The actual value is 0x8005 because the

hardware sets the LSb to 1. Refer to Figure 13-1.

PIC18F26/45/46Q10

(CRC) Cyclic Redundancy Check Module with Me...

Figure 13-2. CRC LFSR Example

Filename: 10-000207A.vsd

Title: CRC LFSR EXAMPLE

Last Edit: 5/27/2014

First Used: PIC16F1613 LECQ

Notes:

Rev. 10-000207A

5/27/2014

Data in

b0b1b2b3b4b5b6b7b8b9b10b11b12b13b14b15

Linear Feedback Shift Register for CRC-16-ANSI

x16 + x15 + x2+ 1

b0b1b2b3b4b5b6b7b8b9b10b11b12b13b14b15

Data in

Augmentation Mode OFF

Augmentation Mode ON

13.4 CRC Data Sources

Data can be input to the CRC module in two ways:

• User data using the 13.12.3 CRCDAT registers

• From Flash memory using the program memory scanner

Up to 16 bits of data per word are specified with the DLEN bits. Only the number of data bits in the

CRCDATA registers specified by DLEN will be used, other data bits in CRCDATA registers will be

ignored.

Data is moved into the 13.12.5 CRCSHIFT as an intermediate to calculate the check value located in the

13.12.4 CRCACC registers.

The SHIFTM bit is used to determine the bit order of the data being shifted into the accumulator. If

SHIFTM is not set, the data will be shifted in MSb first (Big Endian). The value of DLEN will determine the

MSb. If SHIFTM bit is set, the data will be shifted into the accumulator in reversed order, LSb first (Little

Endian).

The CRC module can be seeded with an initial value by setting the CRCACC registers to the appropriate

value before beginning the CRC.

13.4.1 CRC from User Data

To use the CRC module on data input from the user, the user must write the data to the CRCDAT

registers. The data from the CRCDAT registers will be latched into the shift registers on any write to the

CRCDATL register.

13.4.2 CRC from Flash

To use the CRC module on data located in Flash memory, the user can initialize the program memory

scanner as defined in the 13.8 Program Memory Scan Configuration section.

13.5 CRC Check Value

The CRC check value will be located in the CRCACC registers after the CRC calculation has finished.

The check value will depend on the ACCM and SHIFTM mode settings.

PIC18F26/45/46Q10

(CRC) Cyclic Redundancy Check Module with Me...

When the ACCM bit is set, the CRC module augments the data with a number of zeros equal to the

length of the polynomial to align the final check value. When the ACCM bit is not set, the CRC will stop at

the end of the data. A number of zeros equal to the length of the polynomial can then be entered into

CRCDAT to find the same check value as augmented mode. Alternatively, the expected check value can

be entered at this point to make the final result equal 0.

When the CRC check value is computed with the SHIFTM bit set, selecting LSb first, and the ACCM bit is

set then the final value in the CRCACC registers will be reversed such that the LSb will be in the MSb

position and vice versa. This is the expected check value in bit reversed form. When creating a check

value to be appended to a data stream, then a bit reversal must be performed on the final value to

achieve the correct checksum. CRC can be used to do this reversal by following the steps below:

1. Save CRCACC value in user RAM space

2. Clear the CRCACC registers

3. Clear the CRCXOR registers

4. Write the saved CRCACC value to the CRCDAT input

The properly oriented check value will be in the CRCACC registers as the result.

13.6 CRC Interrupt

The CRC will generate an interrupt when the BUSY bit transitions from 1 to 0. The CRCIF Interrupt Flag

bit of the PIRx register is set every time the BUSY bit transitions, regardless of whether or not the CRC

interrupt is enabled. The CRCIF bit can only be cleared in software. The CRC interrupt enable is the

CRCIE bit of the PIEx register.

13.7 Configuring the CRC

The following steps illustrate how to properly configure the CRC.

1. Determine if the automatic program memory scan will be used with the scanner or manual

calculation through the SFR interface and perform the actions specified in 13.4 CRC Data

Sources, depending on which decision was made.

2. If desired, seed a starting CRC value into the 13.12.4 CRCACC registers.

3. Program the 13.12.6 CRCXOR registers with the desired generator polynomial.

4. Program the DLENbits with the length of the data word - 1 (refer to Figure 13-1). This determines

how many times the shifter will shift into the accumulator for each data word.

5. Program the PLEN bits with the length of the polynomial -2 (refer to Figure 13-1).

6. Determine whether shifting in trailing zeros is desired and set the ACCM bit accordingly.

7. Likewise, determine whether the MSb or LSb should be shifted first and write the SHIFTM bit

accordingly.

8. Set the GO bit to begin the shifting process.

9. If manual SFR entry is used, monitor the FULL bit. When FULL = 0, another word of data can be

written to the 13.12.3 CRCDAT registers, keeping in mind that Most Significant Byte, CRCDATH,

should be written first if the data has more than eight bits, as the shifter will begin upon the

CRCDATL register being written.

10. If the scanner is used, the scanner will automatically stuff words into the CRCDAT registers as

needed, as long as the SCANGO bit is set.

PIC18F26/45/46Q10

(CRC) Cyclic Redundancy Check Module with Me...

11. If using the Flash memory scanner, monitor the PIRx SCANIF bit (or the SCANGO bit) for the

scanner to finish pushing information into the CRCDATA registers. After the scanner is completed,

monitor the BUSY bit to determine that the CRC has been completed and the check value can be

read from the CRCACC registers. If both the interrupt flags are set (or both BUSY and SCANGO

bits are cleared), the completed CRC calculation can be read from the CRCACC registers.

12. If manual entry is used, monitor the BUSY bit to determine when the CRCACC registers hold the

valid check value.

13.8 Program Memory Scan Configuration

The program memory scan module may be used in conjunction with the CRC module to perform a CRC

calculation over a range of program memory addresses. In order to setup the scanner to work with the

CRC the following steps need to performed:

1. Set both the EN and SCANEN bits. If they get disabled, all internal states of the scanner and the

CRC are reset. However, the CRC SFR registers are unaffected.

2. Choose which memory access mode is to be used (see 13.10 Scanning Modes) and set the

MODE bits accordingly.

3. Based on the memory access mode, set the INTM bits to the appropriate Interrupt mode (see

13.10.5 Interrupt Interaction)

4. Set the 13.12.8 SCANLADR and 13.12.9 SCANHADR registers with the respective beginning and

ending locations in memory that are to be scanned.

5. The GO bit must be set before setting the SCANGO bit. Setting the SCANGO bit starts the scan.

Both the EN and GO bits must be enabled to use the scanner. When either of these bits are

disabled, the scan aborts and the INVALID bit is set. The scanner will wait for the signal from the

CRC that it is ready for the first Flash memory location, then begin loading data into the CRC. It will

continue to do so until it either hits the configured end address or an address that is unimplemented

on the device, at which point the SCANGO bit will clear, Scanner functions will cease, and the

SCANIF interrupt will be triggered. Alternately, the SCANGO bit can be cleared in software to

terminate the scan early if desired.

13.9 Scanner Interrupt

The scanner will trigger an interrupt when the SCANGO bit transitions from ‘1’ to ‘0’. The SCANIF

interrupt flag of PIRx is set when the last memory location is reached and the data is entered into the

CRCDATA registers. The SCANIF bit can only be cleared in software. The SCAN interrupt enable is the

SCANIE bit of the PIEx register.

13.10 Scanning Modes

The memory scanner can scan in four modes: Burst, Peek, Concurrent, and Triggered. These modes are

controlled by the MODE bits. The four modes are summarized in Table 13-1.

13.10.1 Burst Mode

When MODE = 01, the scanner is in Burst mode. In Burst mode, CPU operation is stalled beginning with

the operation after the one that sets the SCANGO bit, and the scan begins, using the instruction clock to

execute. The CPU is held in its current state until the scan stops. Note that because the CPU is not

executing instructions, the SCANGO bit cannot be cleared in software, so the CPU will remain stalled

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until one of the hardware end-conditions occurs. Burst mode has the highest throughput for the scanner,

but has the cost of stalling other execution while it occurs.

13.10.2 Concurrent Mode

When MODE = 00, the scanner is in Concurrent mode. Concurrent mode, like Burst mode, stalls the CPU

while performing accesses of memory. However, while Burst mode stalls until all accesses are complete,

Concurrent mode allows the CPU to execute in between access cycles.

13.10.3 Triggered mode

When MODE = 11, the scanner is in Triggered mode. Triggered mode behaves identically to Concurrent

mode, except instead of beginning the scan immediately upon the SCANGO bit being set, it waits for a

rising edge from a separate trigger source which is determined by the 13.12.10 SCANTRIG register.

13.10.4 Peek Mode

When MODE = 10, the scanner is in Peek mode. Peek mode waits for an instruction cycle in which the

CPU does not need to access the NVM (such as a branch instruction) and uses that cycle to do its own

NVM access. This results in the lowest throughput for the NVM access (and can take a much longer time

to complete a scan than the other modes), but does so without any impact on execution times, unlike the

other modes.

Table 13-1. Summary of Scanner Modes

MODE<1:0>

Description

First Scan Access CPU Operation

11 Triggered As soon as possible

following a trigger

Stalled during NVM

access

CPU resumes execution

following each access

10 Peek At the first dead cycle Timing is unaffected CPU continues execution

following each access

01 Burst

As soon as possible Stalled during NVM

access

CPU suspended until scan

completes

00 Concurrent CPU resumes execution

following each access

13.10.5 Interrupt Interaction

The INTM bit controls the scanner’s response to interrupts depending on which mode the NVM scanner is

in, as described in the following table.

Table 13-2. Scan Interrupt Modes

INTM

MODE<1:0>

MODE == Burst MODE == CONCURENT or

TRIGGERED MODE ==PEEK

1

Interrupt overrides SCANGO (to zero) to

pause the burst and the interrupt handler

executes at full speed; Scanner Burst

resumes when interrupt completes.

Scanner suspended during

interrupt response (SCANGO = 0);

interrupt executes at full speed and

scan resumes when the interrupt is

complete.

This bit is

ignored

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...........continued

INTM

MODE<1:0>

MODE == Burst MODE == CONCURENT or

TRIGGERED MODE ==PEEK

0

Interrupts do not override SCANGO, and

the scan (burst) operation will continue;

interrupt response will be delayed until

scan completes (latency will be

increased).

Scanner accesses NVM during

interrupt response.

This bit is

ignored

In general, if INTM = 0, the scanner will take precedence over the interrupt, resulting in decreased

interrupt processing speed and/or increased interrupt response latency. If INTM = 1, the interrupt will take

precedence and have a better speed, delaying the memory scan.

13.10.6 WWDT interaction

Operation of the WWDT is not affected by scanner activity. Hence, it is possible that long scans,

particularly in Burst mode, may exceed the WWDT time-out period and result in an undesired device

Reset. This should be considered when performing memory scans with an application that also utilizes

WWDT.

13.10.7 In-Circuit Debug (ICD) Interaction

The scanner freezes when an ICD halt occurs, and remains frozen until user-mode operation resumes.

The debugger may inspect the SCANCON0 and SCANLADR registers to determine the state of the scan.

The ICD interaction with each operating mode is summarized in the following table.

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Table 13-3. ICD and Scanner Interactions

ICD Halt

Scanner Operating Mode

Peek Concurrent

Triggered Burst

External

Halt

If scanner would peek

an instruction that is

not executed (because

of ICD entry), the peek

will occur after ICD

exit, when the

instruction executes.

If external halt is

asserted during a scan

cycle, the instruction

(delayed by scan) may

or may not execute

before ICD entry,

depending on external

halt timing.

If external halt is asserted during the

BSF(SCANCON.GO), ICD entry

occurs, and the burst is delayed until

ICD exit.

Otherwise, the current NVM-access

cycle will complete, and then the

scanner will be interrupted for ICD

entry.

If external halt is

asserted during the

cycle immediately prior

to the scan cycle, both

scan and instruction

execution happen after

the ICD exits.

If external halt is asserted during the

burst, the burst is suspended and will

resume with ICD exit.

PC

Breakpoint

Scan cycle occurs

before ICD entry and

instruction execution

happens after the ICD

exits.

If PCPB (or single step) is on

BSF(SCANCON.GO), the ICD is

entered before execution; execution of

the burst will occur at ICD exit, and the

burst will run to completion.

Note that the burst can be interrupted

by an external halt.

Data

Breakpoint

The instruction with the

dataBP executes and

ICD entry occurs

immediately after. If

scan is requested

during that cycle, the

scan cycle is

postponed until the ICD

exits.

Single Step

If a scan cycle is ready

after the debug

instruction is executed,

the scan will read PFM

and then the ICD is re-

entered.

SWBP and

ICDINST

If scan would stall a

SWBP, the scan cycle

occurs and the ICD is

entered.

If SWBP replaces

BSF(SCANCON.GO), the ICD will be

entered; instruction execution will occur

at ICD exit (from ICDINSTR register),

and the burst will run to completion.

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13.10.8 Peripheral Module Disable

Both the CRC and scanner module can be disabled individually by setting the CRCMD and SCANMD bits

of the PMD0 register. The SCANMD can be used to enable or disable to the scanner module only if the

SCANE bit of Configuration Word 4 is set. If the SCANE bit is cleared, then the scanner module is not

available for use and the SCANMD bit is ignored.

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13.11 Register Summary - CRC

Address Name Bit Pos.

0x0F44 SCANLADR

7:0 SCANLADRL[7:0]

15:8 SCANLADRH[7:0]

23:16 SCANLADRU[5:0]

0x0F47 SCANHADR

7:0 SCANHADRL[7:0]

15:8 SCANHADRH[7:0]

23:16 SCANHADRU[5:0]

0x0F4A SCANCON0 7:0 SCANEN SCANGO BUSY INVALID INTM MODE[1:0]

0x0F4B SCANTRIG 7:0 TSEL[4:0]

0x0F4C

...

0x0F6E

Reserved

0x0F6F CRCDAT

7:0 CRCDATL[7:0]

15:8 CRCDATH[7:0]

0x0F71 CRCACC

7:0 CRCACCL[7:0]

15:8 CRCACCH[7:0]

0x0F73 CRCSHIFT

7:0 CRCSHIFTL[7:0]

15:8 CRCSHIFTH[7:0]

0x0F75 CRCXOR

7:0 CRCXORL[6:0] CRCXORL0

15:8 CRCXORH[7:0]

0x0F77 CRCCON0 7:0 EN GO BUSY ACCM SHIFTM FULL

0x0F78 CRCCON1 7:0 DLEN[3:0] PLEN[3:0]

13.12 Register Definitions: CRC and Scanner Control

Long bit name prefixes for the CRC are shown in the table below. Refer to the "Long Bit Names Section"

for more information.

Table 13-4. CRC Long Bit Name Prefixes

Peripheral Bit Name Prefix

CRC CRC

Related Links

1.4.2.2 Long Bit Names

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13.12.1 CRCCON0

Name: CRCCON0

Address: 0xF77

Reset: 0

CRC Control Register 0

Bit 7 6 5 4 3 2 1 0

EN GO BUSY ACCM SHIFTM FULL

Access R/W R/W RO R/W R/W RO

Reset 0 0 0 0 0 0

Bit 7 – EN CRC Enable bit

Value Description

1CRC module is released from Reset

0CRC is disabled and consumes no operating current

Bit 6 – GO CRC Start bit

Value Description

1Start CRC serial shifter

0CRC serial shifter turned off

Bit 5 – BUSY CRC Busy bit

Value Description

1Shifting in progress or pending

0All valid bits in shifter have been shifted into accumulator and EMPTY = 1

Bit 4 – ACCM Accumulator Mode bit

Value Description

1Data is augmented with zeros

0Data is not augmented with zeros

Bit 1 – SHIFTM Shift Mode bit

Value Description

1Shift right (LSb)

0Shift left (MSb)

Bit 0 – FULL Data Path Full Indicator bit

Value Description

1CRCDATH/L registers are full

0CRCDATH/L registers have shifted their data into the shifter

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13.12.2 CRCCON1

Name: CRCCON1

Address: 0xF78

Reset: 0

CRC Control Register 1

Bit 7 6 5 4 3 2 1 0

DLEN[3:0] PLEN[3:0]

Access R/W R/W R/W R/W R/W R/W R/W R/W

Reset 0 0 0 0 0 0 0 0

Bits 7:4 – DLEN[3:0] Data Length bits

Denotes the length of the data word -1 (See Figure 13-1)

Bits 3:0 – PLEN[3:0] Polynomial Length bits

Denotes the length of the polynomial -1 (See Figure 13-1)

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13.12.3 CRCDAT

Name: CRCDAT

Address: 0xF6F

CRC Data Register

Bit 15 14 13 12 11 10 9 8

CRCDATH[7:0]

Access R/W R/W R/W R/W R/W R/W R/W R/W

Reset x x x x x x x x

Bit 7 6 5 4 3 2 1 0

CRCDATL[7:0]

Access R/W R/W R/W R/W R/W R/W R/W R/W

Reset x x x x x x x x

Bits 15:8 – CRCDATH[7:0] CRC Input/Output Data Most Significant Byte

Bits 7:0 – CRCDATL[7:0] CRC Input/Output Data Least Significant Byte

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13.12.4 CRCACC

Name: CRCACC

Address: 0xF71

Reset: 0

CRC Accumulator Register

Bit 15 14 13 12 11 10 9 8

CRCACCH[7:0]

Access R/W R/W R/W R/W R/W R/W R/W R/W

Reset 0 0 0 0 0 0 0 0

Bit 7 6 5 4 3 2 1 0

CRCACCL[7:0]

Access R/W R/W R/W R/W R/W R/W R/W R/W

Reset 0 0 0 0 0 0 0 0

Bits 15:8 – CRCACCH[7:0] CRC Accumulator Register most significant byte

Writing to this register writes the Most Significant Byte of the CRC accumulator register. Reading from

this register reads the Most Significant Byte of the CRC accumulator.

Bits 7:0 – CRCACCL[7:0] CRC Accumulator Register least significant byte

Writing to this register writes the Least Significant Byte of the CRC accumulator register. Reading from

this register reads the Least Significant Byte of the CRC accumulator.

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13.12.5 CRCSHIFT

Name: CRCSHIFT

Address: 0xF73

Reset: 0

CRC Shift Register

Bit 15 14 13 12 11 10 9 8

CRCSHIFTH[7:0]

Access RO RO RO RO RO RO RO RO

Reset 0 0 0 0 0 0 0 0

Bit 7 6 5 4 3 2 1 0

CRCSHIFTL[7:0]

Access RO RO RO RO RO RO RO RO

Reset 0 0 0 0 0 0 0 0

Bits 15:8 – CRCSHIFTH[7:0] CRC Shifter Register Most Significant Byte

Reading from this register reads the Most Significant Byte of the CRC Shifter.

Bits 7:0 – CRCSHIFTL[7:0] CRC Shifter Register Least Significant Byte

Reading from this register reads the Least Significant Byte of the CRC Shifter.

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13.12.6 CRCXOR

Name: CRCXOR

Address: 0xF75

CRC XOR Register

Bit 15 14 13 12 11 10 9 8

CRCXORH[7:0]

Access R/W R/W R/W R/W R/W R/W R/W R/W

Reset x x x x x x x x

Bit 7 6 5 4 3 2 1 0

CRCXORL[6:0] CRCXORL0

Access R/W R/W R/W R/W R/W R/W R/W U

Reset x x x x x x x 1

Bits 15:8 – CRCXORH[7:0] XOR of Polynomial Term XN Enable Most Significant Byte

Bits 7:1 – CRCXORL[6:0] XOR of Polynomial Term XN Enable Least Significant Byte

Bit 0 – CRCXORL0 LSbit is unimplemented. Read as 1

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13.12.7 SCANCON0

Name: SCANCON0

Address: 0xF4A

Scanner Access Control Register 0

Bit 7 6 5 4 3 2 1 0

SCANEN SCANGO BUSY INVALID INTM MODE[1:0]

Access R/W R/W/HC R R R/W R/W R/W

Reset 0 0 0 1 0 0 0

Bit 7 – SCANEN Scanner Enable bit(1)

Value Description

1Scanner is enabled

0Scanner is disabled, internal states are reset

Bit 6 – SCANGO Scanner GO bit(2, 3)

Value Description

1When the CRC sends a ready signal, NVM will be accessed according to MDx and data

passed to the client peripheral.

0Scanner operations will not occur

Bit 5 – BUSY Scanner Busy Indicator bit(4)

Value Description

1Scanner cycle is in process

0Scanner cycle is complete (or never started)

Bit 4 – INVALID Scanner Abort Signal bit

Value Description

1SCANLADRL/H/U has incremented to an invalid address(6) or the scanner was not setup

correctly(7)

0SCANLADRL/H/U points to a valid address

Bit 3 – INTM NVM Scanner Interrupt Management Mode Select bit

Value Condition Description

XMODE = 10 This bit is ignored

1MODE = 01 CPU is stalled until all data is transferred. SCANGO is overridden (to

zero) during interrupt operation; scanner resumes after returning from

interrupt

0MODE = 01 CPU is stalled until all data is transferred. SCANGO is not affected by

interrupts, the interrupt response will be affected

1MODE = 00 OR 11 SCANGO is overridden (to zero) during interrupt operation; scan

operations resume after returning from interrupt

0MODE = 00 OR 11 Interrupts do not prevent NVM access

Bits 1:0 – MODE[1:0] Memory Access Mode bits(5)

Value Description

11 Triggered mode

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Value Description

10 Peek mode

01 Burst mode

00 Concurrent mode

Note:

1. Setting SCANEN = 0 (SCANCON0 register) does not affect any other register content.

2. This bit is cleared when LADR > HADR (and a data cycle is not occurring).

3. If INTM = 1, this bit is overridden (to zero, but not cleared) during an interrupt response.

4. BUSY = 1 when the NVM is being accessed, or when the CRC sends a ready signal.

5. See Table 13-1 for more detailed information.

6. An invalid address can occur when the entire range of PFM is scanned and the value of LADR rolls

over. An invalid address can also occur if the value in the Scan Low address registers points to a

location that is not mapped in the memory map of the device.

7. CRCEN and CRCGO bits must be set before setting SCANGO bit. Refer to 13.8 Program Memory

Scan Configuration.

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13.12.8 SCANLADR

Name: SCANLADR

Address: 0xF44

Reset: 0

Scan Low Address Register

Bit 23 22 21 20 19 18 17 16

SCANLADRU[5:0]

Access R/W R/W R/W R/W R/W R/W

Reset 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8

SCANLADRH[7:0]

Access R/W R/W R/W R/W R/W R/W R/W R/W

Reset 0 0 0 0 0 0 0 0

Bit 7 6 5 4 3 2 1 0

SCANLADRL[7:0]

Access R/W R/W R/W R/W R/W R/W R/W R/W

Reset 0 0 0 0 0 0 0 0

Bits 21:16 – SCANLADRU[5:0] Scan Start/Current Address upper byte

Upper bits of the current address to be fetched from, value increments on each fetch of memory.

Bits 15:8 – SCANLADRH[7:0] Scan Start/Current Address high byte

High byte of the current address to be fetched from, value increments on each fetch of memory.

Bits 7:0 – SCANLADRL[7:0] Scan Start/Current Address low byte

Low byte of the current address to be fetched from, value increments on each fetch of memory.

Note:

1. Registers SCANLADRU/H/L form a 22-bit value, but are not guarded for atomic or asynchronous

access; registers should only be read or written while SCANGO = 0.

2. While SCANGO = 1, writing to this register is ignored.

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13.12.9 SCANHADR

Name: SCANHADR

Address: 0xF47

Reset: 0

Scan High Address Register

Bit 23 22 21 20 19 18 17 16

SCANHADRU[5:0]

Access R/W R/W R/W R/W R/W R/W

Reset 1 1 1 1 1 1

Bit 15 14 13 12 11 10 9 8

SCANHADRH[7:0]

Access R/W R/W R/W R/W R/W R/W R/W R/W

Reset 1 1 1 1 1 1 1 1

Bit 7 6 5 4 3 2 1 0

SCANHADRL[7:0]

Access R/W R/W R/W R/W R/W R/W R/W R/W

Reset 1 1 1 1 1 1 1 1

Bits 21:16 – SCANHADRU[5:0] Scan End Address bits

Upper bits of the address at the end of the designated scan

Bits 15:8 – SCANHADRH[7:0] Scan End Address bits

High byte of the address at the end of the designated scan

Bits 7:0 – SCANHADRL[7:0] Scan End Address bits

Low byte of the address at the end of the designated scan

Note:

1. Registers SCANHADRU/H/L form a 22-bit value but are not guarded for atomic or asynchronous

access; registers should only be read or written while SCANGO = 0.

2. While SCANGO = 1, writing to this register is ignored.

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13.12.10 SCANTRIG

Name: SCANTRIG

Address: 0xF4B

Reset: 0

SCAN Trigger Selection Register

Bit 7 6 5 4 3 2 1 0

TSEL[4:0]

Access R/W R/W R/W R/W R/W

Reset 0 0 0 0 0

Bits 4:0 – TSEL[4:0] Scanner Data Trigger Input Selection bits

Table 13-5. SCAN Trigger Sources

TSEL Trigger Source

11000 - 11111 Reserved

10111 CLC8_out

10110 CLC7_out

10101 CLC6_out

10100 CLC5_out

10011 CLC4_out

10010 CLC3_out

10001 CLC2_out

10000 CLC1_out

01001 - 01111 Reserved

01000 TMR6_postscaled

00111 TMR5_output

00110 TMR4_postscaled

00101 TMR3_output

00100 TMR2_postscaled

00011 TMR1_output

00010 TMR0_output

00001 CLKREF_output

00000 LFINTOSC

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14. Interrupts

The PIC18F26/45/46Q10 devices have multiple interrupt sources and an interrupt priority feature that

allows most interrupt sources to be assigned a high or low-priority level. The high-priority interrupt vector

is at 0008h and the low-priority interrupt vector is at 0018h. A high-priority interrupt event will interrupt a

low-priority interrupt that may be in progress.

The registers for controlling interrupt operation are:

• INTCON

• PIRx (Interrupt flags)

• PIEx (Interrupt enables)

• IPRx (High/Low interrupt priority)

It is recommended that the Microchip header files supplied with MPLAB® IDE be used for the symbolic bit

names in these registers. This allows the assembler/compiler to automatically take care of the placement

of these bits within the specified register.

In general, interrupt sources have three bits to control their operation. They are:

•Flag bit to indicate that an interrupt event occurred

•Enable bit that allows program execution to branch to the interrupt vector address when the flag bit

is set

•Priority bit to select high priority or low priority

14.1 Midrange Compatibility

When the IPEN bit is cleared (default state), the interrupt priority feature is disabled and interrupts are

compatible with PIC® microcontroller midrange devices. In Compatibility mode, the interrupt priority bits of

the IPRx registers have no effect. The PEIE/GIEL bit is the global interrupt enable for the peripherals. The

PEIE/GIEL bit disables only the peripheral interrupt sources and enables the peripheral interrupt sources

when the GIE/GIEH bit is also set. The GIE/GIEH bit is the global interrupt enable which enables all non-

peripheral interrupt sources and disables all interrupt sources, including the peripherals. All interrupts

branch to address 0008h in Compatibility mode.

14.2 Interrupt Priority

The interrupt priority feature is enabled by setting the IPEN bit. When interrupt priority is enabled the GIE/

GIEH and PEIE/GIEL Global Interrupt Enable bits of Compatibility mode are replaced by the GIEH high

priority, and GIEL low priority, global interrupt enables. When the IPEN bit is set, the GIEH bit enables all

interrupts which have their associated bit in the IPRx register set. When the GIEH bit is cleared, then all

interrupt sources including those selected as low priority in the IPRx register are disabled.

When both GIEH and GIEL bits are set, all interrupts selected as low priority sources are enabled.

A high-priority interrupt will vector immediately to address 00 0008h and a low-priority interrupt will vector

to address 00 0018h.

14.3 Interrupt Response

When an interrupt is responded to, the Global Interrupt Enable bit is cleared to disable further interrupts.

The GIE/GIEH bit is the Global Interrupt Enable when the IPEN bit is cleared. When the IPEN bit is set,

PIC18F26/45/46Q10

Interrupts

enabling interrupt priority levels, the GIEH bit is the high priority Global Interrupt Enable and the GIEL bit

is the low priority Global Interrupt Enable. High-priority interrupt sources can interrupt a low-priority

interrupt. Low-priority interrupts are not processed while high-priority interrupts are in progress.

The return address is pushed onto the stack and the PC is loaded with the interrupt vector address

(0008h or 0018h). Once in the Interrupt Service Routine, the source(s) of the interrupt can be determined

by polling the interrupt flag bits in the INTCONx and PIRx registers. The interrupt flag bits must be

cleared by software before re-enabling interrupts to avoid repeating the same interrupt.

The “return from interrupt” instruction, RETFIE, exits the interrupt routine and sets the GIE/GIEH bit

(GIEH or GIEL if priority levels are used), which re-enables interrupts.

For external interrupt events, such as the INT pins or the interrupt-on-change pins, the interrupt latency

will be three to four instruction cycles. The exact latency is the same for one-cycle or two-cycle

instructions. Individual interrupt flag bits are set, regardless of the status of their corresponding enable

bits or the Global Interrupt Enable bit.

Important: Do not use the MOVFF instruction to modify any of the interrupt control registers

while any interrupt is enabled. Doing so may cause erratic microcontroller behavior.

PIC18F26/45/46Q10

Interrupts

Figure 14-1. PIC18 Interrupt Logic

Filename: 10-000010B.vsd

Title: Generic Interrupt Logic for PIC18

Last Edit: 5/4/2016

First Used:

Rev. 10-000010B

5/4/2016

IPEN

GIEL/PEIE

GIEH/GIE

IPEN

GIEH/GIE

GIEL/PEIE

Interrupt to

CPU Vector at

Location 0008h

Interrupt to

CPU Vector at

Location 0018h

Wake-up if in

Idle or Sleep

modes

High Priority Interrupt Generation

Low Priority Interrupt Generation

PIR0

IPR0

PIE0

PIR0

IPR0

PIE0

PIR1

IPR1

PIE1

PIR2

IPR2

PIE2

PIRx

IPRx

PIEx

PIR1

IPR1

PIE1

PIR2

IPR2

PIE2

PIRx

IPRx

PIEx

14.4 INTCON Registers

The INTCON registers are readable and writable registers, which contain various enable and priority bits.

14.5 PIR Registers

The PIR registers contain the individual flag bits for the peripheral interrupts. Due to the number of

peripheral interrupt sources, there are 8 PIR registers.

14.6 PIE Registers

The PIE registers contain the individual enable bits for the peripheral interrupts. Due to the number of

peripheral interrupt sources, there are 8 Peripheral Interrupt Enable registers. When IPEN = 0, the PEIE/

GIEL bit must be set to enable any of these peripheral interrupts.

PIC18F26/45/46Q10

Interrupts

14.7 IPR Registers

The IPR registers contain the individual priority bits for the peripheral interrupts. Due to the number of

peripheral interrupt sources, there are 8 Peripheral Interrupt Priority registers. Using the priority bits

requires that the Interrupt Priority Enable (IPEN) bit be set.

14.8 INTn Pin Interrupts

PIC18F26/45/46Q10 devices have 3 external interrupt sources which can be assigned to any pin on

PORTA and PORTB using PPS. The external interrupt sources are edge-triggered. If the corresponding

INTxEDG bit in the 14.13.1 INTCON register is set (= 1), the interrupt is triggered by a rising edge. It the

bit is clear, the trigger is on the falling edge.

All external interrupts (INT0, INT1, INT2) can wake-up the processor from Idle or Sleep modes if bit

INTxE was set prior to going into those modes. If the Global Interrupt Enable bit (GIE/GIEH) is set, the

processor will branch to the interrupt vector following wake-up.

Interrupt priority is determined by the value contained in the corresponding interrupt priority bit (INT0P,

INT1P, INT2P) of the 14.13.18 IPR0 register.

14.9 TMR0 Interrupt

In 8-bit mode (which is the default), an overflow in the TMR0 register (FFh → 00h) will set flag bit,

TMR0IF. In 16-bit mode, an overflow in the TMR0H:TMR0L register pair (FFFFh → 0000h) will set

TMR0IF. The interrupt can be enabled/disabled by setting/clearing enable bit, TMR0IE. Interrupt priority

for Timer0 is determined by the value contained in the interrupt priority bit, TMR0IP. See “Timer0 Module”

for further details on the Timer0 module.

14.10 Interrupt-on-Change

An input change on any port pins that support IOC sets Flag bit, IOCIF. The interrupt can be enabled/

disabled by setting/clearing the enable bit, IOCIE. Pins must also be individually enabled in the IOCxP

and IOCxN register. IOCIF is a read-only bit and the flag can be cleared by clearing the corresponding

IOCxF registers. For more information, refer to chapter “Interrupt-on-Change”.

Related Links

16. Interrupt-on-Change

14.11 Context Saving During Interrupts

During interrupts, the return PC address is saved on the stack. Additionally, the WREG, STATUS and

BSR registers are saved on the fast return stack. If a fast return from interrupt is not used the user may

need to save the WREG, STATUS and BSR registers on entry to the Interrupt Service Routine.

Depending on the user’s application, other registers may also need to be saved. Saving Status, WREG

and BSR Registers in RAM saves and restores the WREG, STATUS and BSR registers during an

Interrupt Service Routine.

Example 14-1. Saving Status, WREG and BSR Registers in RAM

MOVWF W_TEMP ; W_TEMP is in virtual bank

PIC18F26/45/46Q10

Interrupts

MOVFF STATUS, STATUS_TEMP ; STATUS_TEMP located anywhere

MOVFF BSR, BSR_TEMP ; BSR_TEMP located anywhere

;

; USER ISR CODE

;

MOVFF BSR_TEMP, BSR ; Restore BSR

MOVF W_TEMP, W ; Restore WREG

MOVFF STATUS_TEMP, STATUS ; Restore STATUS

Related Links

10.1.2.5 Fast Register Stack

PIC18F26/45/46Q10

Interrupts

14.12 Register Summary - Interrupt Control

Address Name Bit Pos.

0x0EB5 IPR0 7:0 TMR0IP IOCIP INT2IP INT1IP INT0IP

0x0EB6 IPR1 7:0 OSCFIP CSWIP ADTIP ADIP

0x0EB7 IPR2 7:0 HLVDIP ZCDIP C2IP C1IP

0x0EB8 IPR3 7:0 RC2IP TX2IP RC1IP TX1IP BCL2IP SSP2IP BCL1IP SSP1IP

0x0EB9 IPR4 7:0 TMR6IP TMR5IP TMR4IP TMR3IP TMR2IP TMR1IP

0x0EBA IPR5 7:0 CLC4IP CLC3IP CLC2IP CLC1IP TMR5GIP TMR3GIP TMR1GIP

0x0EBB IPR6 7:0 CLC8IP CLC7IP CLC6IP CLC5IP CCP2IP CCP1IP

0x0EBC IPR7 7:0 SCANIP CRCIP NVMIP CWG1IP

0x0EBD PIE0 7:0 TMR0IE IOCIE INT2IE INT1IE INT0IE

0x0EBE PIE1 7:0 OSCFIE CSWIE ADTIE ADIE

0x0EBF PIE2 7:0 HLVDIE ZCDIE C2IE C1IE

0x0EC0 PIE3 7:0 RC2IE TX2IE RC1IE TX1IE BCL2IE SSP2IE BCL1IE SSP1IE

0x0EC1 PIE4 7:0 TMR6IE TMR5IE TMR4IE TMR3IE TMR2IE TMR1IE

0x0EC2 PIE5 7:0 CLC4IE CLC3IE CLC2IE CLC1IE TMR5GIE TMR3GIE TMR1GIE

0x0EC3 PIE6 7:0 CLC8IE CLC7IE CLC6IE CLC5IE CCP2IE CCP1IE

0x0EC4 PIE7 7:0 SCANIE CRCIE NVMIE CWG1IE

0x0EC5 PIR0 7:0 TMR0IF IOCIF INT2IF INT1IF INT0IF

0x0EC6 PIR1 7:0 OSCFIF CSWIF ADTIF ADIF

0x0EC7 PIR2 7:0 HLVDIF ZCDIF C2IF C1IF

0x0EC8 PIR3 7:0 RC2IF TX2IF RC1IF TX1IF BCL2IF SSP2IF BCL1IF SSP1IF

0x0EC9 PIR4 7:0 TMR6IF TMR5IF TMR4IF TMR3IF TMR2IF TMR1IF

0x0ECA PIR5 7:0 CLC4IF CLC3IF CLC2IF CLC1IF TMR5GIF TMR3GIF TMR1GIF

0x0ECB PIR6 7:0 CLC8IF CLC7IF CLC6IF CLC5IF CCP2IF CCP1IF

0x0ECC PIR7 7:0 SCANIF CRCIF NVMIF CWG1IF

0x0ECD

...

0x0FF1

Reserved

0x0FF2 INTCON 7:0 GIE/GIEH PEIE/GIEL IPEN INT2EDG INT1EDG INT0EDG

14.13 Register Definitions: Interrupt Control

PIC18F26/45/46Q10

Interrupts

14.13.1 INTCON

Name: INTCON

Address: 0xFF2

Interrupt Control Register

Bit 7 6 5 4 3 2 1 0

GIE/GIEH PEIE/GIEL IPEN INT2EDG INT1EDG INT0EDG

Access R/W R/W R/W R/W R/W R/W

Reset 0 0 0 1 1 1

Bit 7 – GIE/GIEH Global Interrupt Enable bit

Value Condition Description

1If IPEN = 1 Enables all unmasked interrupts and cleared by hardware for high-priority

interrupts only

0If IPEN = 1 Disables all interrupts

1If IPEN = 0 Enables all unmasked interrupts and cleared by hardware for all interrupts

0If IPEN = 0 Disables all interrupts

Bit 6 – PEIE/GIEL Peripheral Interrupt Enable bit

Value Condition Description

1If IPEN = 1 Enables all low-priority interrupts and cleared by hardware for low-priority

interrupts only

0If IPEN = 1 Disables all low-priority interrupts

1If IPEN = 0 Enables all unmasked peripheral interrupts

0If IPEN = 0 Disables all peripheral interrupts

Bit 5 – IPEN Interrupt Priority Enable bit

Value Description

1Enable priority levels on interrupts

0Disable priority levels on interrupts

Bits 0, 1, 2 – INTxEDG External Interrupt ‘x’ Edge Select bit

Value Description

1Interrupt on rising edge of INTx pin

0Interrupt on falling edge of INTx pin

Important: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its

corresponding enable bit or the global enable bit. User software should ensure the appropriate interrupt

flag bits are clear prior to enabling an interrupt. This feature allows for software polling.

PIC18F26/45/46Q10

Interrupts

14.13.2 PIR0

Name: PIR0

Address: 0xEC5

Peripheral Interrupt Request (Flag) Register 0

Bit 7 6 5 4 3 2 1 0

TMR0IF IOCIF INT2IF INT1IF INT0IF

Access R/W R R/W R/W R/W

Reset 0 0 0 0 0

Bit 5 – TMR0IF Timer0 Interrupt Flag bit(1)

Value Description

1TMR0 register has overflowed (must be cleared by software)

0TMR0 register has not overflowed

Bit 4 – IOCIF Interrupt-on-Change Flag bit(1,2)

Value Description

1IOC event has occurred (must be cleared by software)

0IOC event has not occurred

Bits 0, 1, 2 – INTxIF External Interrupt ‘x’ Flag bit(1,3)

Value Description

1External Interrupt ‘x’ has occurred

0External Interrupt ‘x’ has not occurred

Note:

1. Interrupts are not disabled by the PEIE bit.

2. IOCIF is a read-only bit; to clear the interrupt condition, all bits in the IOCF register must be

cleared.

3. The external interrupt GPIO pin is selected by the INTPPS register.

PIC18F26/45/46Q10

Interrupts

14.13.3 PIR1

Name: PIR1

Address: 0xEC6

Peripheral Interrupt Request (Flag) Register 1

Bit 7 6 5 4 3 2 1 0

OSCFIF CSWIF ADTIF ADIF

Access R/W R/W R/W R/W

Reset 0 0 0 0

Bit 7 – OSCFIF Oscillator Fail Interrupt Flag bit

Value Description

1Device oscillator failed, clock input has changed to HFINTOSC (must be cleared by

software)

0Device clock operating

Bit 6 – CSWIF Clock-Switch Interrupt Flag bit(1)

Value Description

1New oscillator is ready for switch (must be cleared by software)

0New oscillator is not ready for switch or has not been started

Bit 1 – ADTIF ADC Threshold Interrupt Flag bit

Value Description

1ADC Threshold interrupt has occurred (must be cleared by software)

0ADC Threshold event is not complete or has not been started

Bit 0 – ADIF ADC Interrupt Flag bit

Value Description

1An A/D conversion completed (must be cleared by software)

0The A/D conversion is not complete or has not been started

Note:

1. The CSWIF interrupt will not wake the system from Sleep. The system will Sleep until another

interrupt causes the wake-up.

Related Links

4.3.3 Clock Switch and Sleep

PIC18F26/45/46Q10

Interrupts

14.13.4 PIR2

Name: PIR2

Address: 0xEC7

Peripheral Interrupt Request (Flag) Register 2

Bit 7 6 5 4 3 2 1 0

HLVDIF ZCDIF C2IF C1IF

Access R/W R/W R/W R/W

Reset 0 0 0 0

Bit 7 – HLVDIF HLVD Interrupt Flag bit

Value Description

1HLVD interrupt event has occurred

0HLVD interrupt event has not occurred or has not been set up

Bit 6 – ZCDIF Zero-Cross Detect Interrupt Flag bit

Value Description

1ZCD Output has changed (must be cleared in software)

0ZCD Output has not changed

Bits 0, 1 – CxIF Comparator ‘x’ Interrupt Flag bit

Value Description

1Comparator Cx output has changed (must be cleared by software)

0Comparator Cx output has not changed

PIC18F26/45/46Q10

Interrupts

14.13.5 PIR3

Name: PIR3

Address: 0xEC8

Peripheral Interrupt Request (Flag) Register 3

Bit 7 6 5 4 3 2 1 0

RC2IF TX2IF RC1IF TX1IF BCL2IF SSP2IF BCL1IF SSP1IF

Access R R R R R/W R/W R/W R/W

Reset 0 0 0 0 0 0 0 0

Bits 5, 7 – RCxIF EUSARTx Receive Interrupt Flag bit

Value Description

1The EUSARTx receive buffer, RCxREG, is full (cleared by reading RCxREG)

0The EUSARTx receive buffer is empty

Bits 4, 6 – TXxIF EUSARTx Transmit Interrupt Flag bit

Value Description

1The EUSARTx transmit buffer, TXxREG, is empty (cleared by writing TXxREG)

0The EUSARTx transmit buffer is full

Bits 1, 3 – BCLxIF MSSPx Bus Collision Interrupt Flag bit

Value Description

1A bus collision has occurred while the MSSPx module configured in I2C master was

transmitting (must be cleared in software)

0No bus collision occurred

Bits 0, 2 – SSPxIF Synchronous Serial Port ‘x’ Interrupt Flag bit

Value Description

1The transmission/reception is complete (must be cleared in software)

0Waiting to transmit/receive

PIC18F26/45/46Q10

Interrupts

14.13.6 PIR4

Name: PIR4

Address: 0xEC9

Peripheral Interrupt Request (Flag) Register 4

Bit 7 6 5 4 3 2 1 0

TMR6IF TMR5IF TMR4IF TMR3IF TMR2IF TMR1IF

Access R/W R/W R/W R/W R/W R/W

Reset 0 0 0 0 0 0

Bit 5 – TMR6IF TMR6 to PR6 Match Interrupt Flag bit

Value Description

1TMR6 to PR6 match occurred (must be cleared in software)

0No TMR6 to PR6 match occurred

Bit 4 – TMR5IF TMR5 Overflow Interrupt Flag bit

Value Description

1TMR5 register overflowed (must be cleared in software)

0TMR5 register did not overflow

Bit 3 – TMR4IF TMR4 to PR4 Match Interrupt Flag bit

Value Description

1TMR4 to PR4 match occurred (must be cleared in software)

0No TMR4 to PR4 match occurred

Bit 2 – TMR3IF TMR3 Overflow Interrupt Flag bit

Value Description

1TMR3 register overflowed (must be cleared in software)

0TMR3 register did not overflow

Bit 1 – TMR2IF TMR2 to PR2 Match Interrupt Flag bit

Value Description

1TMR2 to PR2 match occurred (must be cleared in software)

0No TMR2 to PR2 match occurred

Bit 0 – TMR1IF TMR1 Overflow Interrupt Flag bit

Value Description

1TMR1 register overflowed (must be cleared in software)

0TMR1 register did not overflow

PIC18F26/45/46Q10

Interrupts

14.13.7 PIR5

Name: PIR5

Address: 0xECA

Peripheral Interrupt Request (Flag) Register 5

Bit 7 6 5 4 3 2 1 0

CLC4IF CLC3IF CLC2IF CLC1IF TMR5GIF TMR3GIF TMR1GIF

Access R/W R/W R/W R/W R/W R/W R/W

Reset 0 0 0 0 0 0 0

Bits 4, 5, 6, 7 – CLCxIF CLCx Interrupt Flag bit

Value Description

1A CLCx interrupt occurred

0No CLCx interrupt occurred

Bit 2 – TMR5GIF TMR5 Gate Interrupt Flag bit

Value Description

1TMR5 gate interrupt occurred (must be cleared in software)

0No TMR5 gate occurred

Bit 1 – TMR3GIF TMR3 Gate Interrupt Flag bit

Value Description

1TMR3 gate interrupt occurred (must be cleared in software)

0No TMR3 gate occurred

Bit 0 – TMR1GIF TMR1 Gate Interrupt Flag bit

Value Description

1TMR1 gate interrupt occurred (must be cleared in software)

0No TMR1 gate occurred

PIC18F26/45/46Q10

Interrupts

14.13.8 PIR6

Name: PIR6

Address: 0xECB

PIR6 Peripheral Interrupt Request (Flag) Register 6

Bit 7 6 5 4 3 2 1 0

CLC8IF CLC7IF CLC6IF CLC5IF CCP2IF CCP1IF

Access R/W R/W R/W R/W R/W R/W

Reset 0 0 0 0 0 0

Bits 4, 5, 6, 7 – CLCyIF CLCx Interrupt Flag bit

Value Description

1A CLCx interrupt occurred

0No CLCx interrupt occurred

Bit 1 – CCP2IF ECCP2 Interrupt Flag bit

Value Condition Description

1Capture mode A TMR register capture occurred (must be cleared in software)

0Capture mode No TMR register capture occurred

1Compare mode A TMR register compare match occurred (must be cleared in software)

0Compare mode No TMR register compare match occurred

—PWM mode Unused in PWM mode

Bit 0 – CCP1IF ECCP1 Interrupt Flag bit

Value Condition Description

1Capture mode A TMR register capture occurred (must be cleared in software)

0Capture mode No TMR register capture occurred

1Compare mode A TMR register compare match occurred (must be cleared in software)

0Compare mode No TMR register compare match occurred

—PWM mode Unused in PWM mode

PIC18F26/45/46Q10

Interrupts

14.13.9 PIR7

Name: PIR7

Address: 0xECC

Peripheral Interrupt Request (Flag) Register 7

Bit 7 6 5 4 3 2 1 0

SCANIF CRCIF NVMIF CWG1IF

Access R/W R/W R/W R/W

Reset 0 0 0 0

Bit 7 – SCANIF SCAN Interrupt Flag bit

Value Description

1SCAN interrupt has occurred (must be cleared in software)

0SCAN interrupt has not occurred or has not been started

Bit 6 – CRCIF CRC Interrupt Flag bit

Value Description

1CRC interrupt has occurred (must be cleared in software)

0CRC interrupt has not occurred or has not been started

Bit 5 – NVMIF NVM Interrupt Flag bit

Value Description

1NVM interrupt has occurred (must be cleared in software)

0NVM interrupt has not occurred or has not been started

Bit 0 – CWG1IF CWG Interrupt Flag bit

Value Description

1CWG interrupt has occurred (must be cleared in software)

0CWG interrupt has not occurred or has not been started

PIC18F26/45/46Q10

Interrupts

14.13.10 PIE0

Name: PIE0

Address: 0xEBD

Peripheral Interrupt Enable Register 0

Bit 7 6 5 4 3 2 1 0

TMR0IE IOCIE INT2IE INT1IE INT0IE

Access R/W R/W R/W R/W R/W

Reset 0 0 0 0 0

Bit 5 – TMR0IE Timer0 Interrupt Enable bit(1)

Value Description

1Enabled

0Disabled

Bit 4 – IOCIE Interrupt-on-Change Enable bit(1)

Value Description

1Enabled

0Disabled

Bits 0, 1, 2 – INTxIE External Interrupt ‘x’ Enable bit(1)

Value Description

1Enabled

0Disabled

Note:

1. PIR0 interrupts are not disabled by the PEIE bit in the INTCON register.

PIC18F26/45/46Q10

Interrupts

14.13.11 PIE1

Name: PIE1

Address: 0xEBE

Peripheral Interrupt Enable Register 1

Bit 7 6 5 4 3 2 1 0

OSCFIE CSWIE ADTIE ADIE

Access R/W R/W R/W R/W

Reset 0 0 0 0

Bit 7 – OSCFIE Oscillator Fail Interrupt Enable bit

Value Description

1Enabled

0Disabled

Bit 6 – CSWIE Clock-Switch Interrupt Enable bit

Value Description

1Enabled

0Disabled

Bit 1 – ADTIE ADC Threshold Interrupt Enable bit

Value Description

1Enabled

0Disabled

Bit 0 – ADIE ADC Interrupt Enable bit

Value Description

1Enabled

0Disabled

PIC18F26/45/46Q10

Interrupts

14.13.12 PIE2

Name: PIE2

Address: 0xEBF

Peripheral Interrupt Enable Register 2

Bit 7 6 5 4 3 2 1 0

HLVDIE ZCDIE C2IE C1IE

Access R/W R/W R/W R/W

Reset 0 0 0 0

Bit 7 – HLVDIE HLVD Interrupt Enable bit

Value Description

1Enabled

0Disabled

Bit 6 – ZCDIE Zero-Cross Detect Interrupt Enable bit

Value Description

1Enabled

0Disabled

Bits 0, 1 – CxIE Comparator ‘x’ Interrupt Enable bit

Value Description

1Enabled

0Disabled

PIC18F26/45/46Q10

Interrupts

14.13.13 PIE3

Name: PIE3

Address: 0xEC0

Peripheral Interrupt Enable Register 3

Bit 7 6 5 4 3 2 1 0

RC2IE TX2IE RC1IE TX1IE BCL2IE SSP2IE BCL1IE SSP1IE

Access R/W R/W R/W R/W R/W R/W R/W R/W

Reset 0 0 0 0 0 0 0 0

Bits 5, 7 – RCxIE EUSARTx Receive Interrupt Enable bit

Value Description

1Enabled

0Disabled

Bits 4, 6 – TXxIE EUSARTx Transmit Interrupt Enable bit

Value Description

1Enabled

0Disabled

Bits 1, 3 – BCLxIE MSSPx Bus Collision Interrupt Enable bit

Value Description

1Enabled

0Disabled

Bits 0, 2 – SSPxIE Synchronous Serial Port ‘x’ Interrupt Enable bit

Value Description

1Enabled

0Disabled

PIC18F26/45/46Q10

Interrupts

14.13.14 PIE4

Name: PIE4

Address: 0xEC1

Peripheral Interrupt Enable Register 4

Bit 7 6 5 4 3 2 1 0

TMR6IE TMR5IE TMR4IE TMR3IE TMR2IE TMR1IE

Access R/W R/W R/W R/W R/W R/W

Reset 0 0 0 0 0 0

Bit 5 – TMR6IE TMR6 to PR6 Match Interrupt Enable bit

Value Description

1Enabled

0Disabled

Bit 4 – TMR5IE TMR5 Overflow Interrupt Enable bit

Value Description

1Enabled

0Disabled

Bit 3 – TMR4IE TMR4 to PR4 Match Interrupt Enable bit

Value Description

1Enabled

0Disabled

Bit 2 – TMR3IE TMR3 Overflow Interrupt Enable bit

Value Description

1Enabled

0Disabled

Bit 1 – TMR2IE TMR2 to PR2 Match Interrupt Enable bit

Value Description

1Enabled

0Disabled

Bit 0 – TMR1IE TMR1 Overflow Interrupt Enable bit

Value Description

1Enabled

0Disabled

PIC18F26/45/46Q10

Interrupts

14.13.15 PIE5

Name: PIE5

Address: 0xEC2

Peripheral Interrupt Enable Register 5

Bit 7 6 5 4 3 2 1 0

CLC4IE CLC3IE CLC2IE CLC1IE TMR5GIE TMR3GIE TMR1GIE

Access R/W R/W R/W R/W R/W R/W R/W

Reset 0 0 0 0 0 0 0

Bits 4, 5, 6, 7 – CLCxIE CLCx Interrupt Enable bit

Value Description

1CLCx Interrupt Enabled

0CLCx Interrupt Disabled

Bit 2 – TMR5GIE TMR5 Gate Interrupt Enable bit

Value Description

1Enabled

0Disabled

Bit 1 – TMR3GIE TMR3 Gate Interrupt Enable bit

Value Description

1Enabled

0Disabled

Bit 0 – TMR1GIE TMR1 Gate Interrupt Enable bit

Value Description

1Enabled

0Disabled

PIC18F26/45/46Q10

Interrupts

14.13.16 PIE6

Name: PIE6

Address: 0xEC3

Peripheral Interrupt Enable Register 6

Bit 7 6 5 4 3 2 1 0

CLC8IE CLC7IE CLC6IE CLC5IE CCP2IE CCP1IE

Access R/W R/W R/W R/W R/W R/W

Reset 0 0 0 0 0 0

Bits 4, 5, 6, 7 – CLCyIE CLCx Interrupt Enable bit

Value Description

1CLCx Interrupts Enabled

0CLCx Interrupts Disabled

Bit 1 – CCP2IE ECCP2 Interrupt Enable bit

Value Description

1Enabled

0Disabled

Bit 0 – CCP1IE ECCP1 Interrupt Enable bit

Value Description

1Enabled

0Disabled

PIC18F26/45/46Q10

Interrupts

14.13.17 PIE7

Name: PIE7

Address: 0xEC4

Peripheral Interrupt Enable Register 7

Bit 7 6 5 4 3 2 1 0

SCANIE CRCIE NVMIE CWG1IE

Access R/W R/W R/W R/W

Reset 0 0 0 0

Bit 7 – SCANIE SCAN Interrupt Enable bit

Value Description

1Enabled

0Disabled

Bit 6 – CRCIE CRC Interrupt Enable bit

Value Description

1Enabled

0Disabled

Bit 5 – NVMIE NVM Interrupt Enable bit

Value Description

1Enabled

0Disabled

Bit 0 – CWG1IE CWG Interrupt Enable bit

Value Description

1Enabled

0Disabled

PIC18F26/45/46Q10

Interrupts

14.13.18 IPR0

Name: IPR0

Address: 0xEB5

Peripheral Interrupt Priority Register 0

Bit 7 6 5 4 3 2 1 0

TMR0IP IOCIP INT2IP INT1IP INT0IP

Access R/W R/W R/W R/W R/W

Reset 1 1 0 0 1

Bit 5 – TMR0IP Timer0 Interrupt Priority bit

Value Description

1High priority

0Low priority

Bit 4 – IOCIP Interrupt-on-Change Priority bit

Value Description

1High priority

0Low priority

Bits 0, 1, 2 – INTxIP External Interrupt ‘x’ Priority bit

Value Description

1High priority

0Low priority

PIC18F26/45/46Q10

Interrupts

14.13.19 IPR1

Name: IPR1

Address: 0xEB6

Peripheral Interrupt Priority Register 1

Bit 7 6 5 4 3 2 1 0

OSCFIP CSWIP ADTIP ADIP

Access R/W R/W R/W R/W

Reset 1 1 1 1

Bit 7 – OSCFIP Oscillator Fail Interrupt Priority bit

Value Description

1High priority

0Low priority

Bit 6 – CSWIP Clock-Switch Interrupt Priority bit

Value Description

1High priority

0Low priority

Bit 1 – ADTIP ADC Threshold Interrupt Priority bit

Value Description

1High priority

0Low priority

Bit 0 – ADIP ADC Interrupt Priority bit

Value Description

1High priority

0Low priority

PIC18F26/45/46Q10

Interrupts

14.13.20 IPR2

Name: IPR2

Address: 0xEB7

Peripheral Interrupt Priority Register 2

Bit 7 6 5 4 3 2 1 0

HLVDIP ZCDIP C2IP C1IP

Access R/W R/W R/W R/W

Reset 1 1 1 1

Bit 7 – HLVDIP HLVD Interrupt Priority bit

Value Description

1High priority

0Low priority

Bit 6 – ZCDIP Zero-Cross Detect Interrupt Priority bit

Value Description

1High priority

0Low priority

Bits 0, 1 – CxIP Comparator ‘x’ Interrupt Priority bit

Value Description

1High priority

0Low priority

PIC18F26/45/46Q10

Interrupts

14.13.21 IPR3

Name: IPR3

Address: 0xEB8

Peripheral Interrupt Priority Register 3

Bit 7 6 5 4 3 2 1 0

RC2IP TX2IP RC1IP TX1IP BCL2IP SSP2IP BCL1IP SSP1IP

Access R/W R/W R/W R/W R/W R/W R/W R/W

Reset 0 0 1 1 0 0 1 1

Bits 5, 7 – RCxIP EUSARTx Receive Interrupt Priority bit

Value Description

1High priority

0Low priority

Bits 4, 6 – TXxIP EUSARTx Transmit Interrupt Priority bit

Value Description

1High priority

0Low priority

Bits 1, 3 – BCLxIP MSSPx Bus Collision Interrupt Priority bit

Value Description

1High priority

0Low priority

Bits 0, 2 – SSPxIP Synchronous Serial Port 'x' Interrupt Priority bit

Value Description

1High priority

0Low priority

PIC18F26/45/46Q10

Interrupts

14.13.22 IPR4

Name: IPR4

Address: 0xEB9

Peripheral Interrupt Priority Register 4

Bit 7 6 5 4 3 2 1 0

TMR6IP TMR5IP TMR4IP TMR3IP TMR2IP TMR1IP

Access R/W R/W R/W R/W R/W R/W

Reset 1 1 1 1 1 1

Bit 5 – TMR6IP TMR6 to PR6 Match Interrupt Priority bit

Value Description

1High priority

0Low priority

Bit 4 – TMR5IP TMR5 Overflow Interrupt Priority bit

Value Description

1High priority

0Low priority

Bit 3 – TMR4IP TMR4 to PR4 Match Interrupt Priority bit

Value Description

1High priority

0Low priority

Bit 2 – TMR3IP TMR3 Overflow Interrupt Priority bit

Value Description

1High priority

0Low priority

Bit 1 – TMR2IP TMR2 to PR2 Match Interrupt Priority bit

Value Description

1High priority

0Low priority

Bit 0 – TMR1IP TMR1 Overflow Interrupt Priority bit

Value Description

1High priority

0Low priority

PIC18F26/45/46Q10

Interrupts

14.13.23 IPR5

Name: IPR5

Address: 0xEBA

Peripheral Interrupt Priority Register 5

Bit 7 6 5 4 3 2 1 0

CLC4IP CLC3IP CLC2IP CLC1IP TMR5GIP TMR3GIP TMR1GIP

Access R/W R/W R/W R/W R/W R/W R/W

Reset 0 0 0 0 1 1 1

Bits 4, 5, 6, 7 – CLCxIP CLCx Interrupt Priority bit

Value Description

1High priority

0Low priority

Bit 2 – TMR5GIP TMR5 Gate Interrupt Priority bit

Value Description

1High priority

0Low priority

Bit 1 – TMR3GIP TMR3 Gate Interrupt Priority bit

Value Description

1High priority

0Low priority

Bit 0 – TMR1GIP TMR1 Gate Interrupt Priority bit

Value Description

1High priority

0Low priority

PIC18F26/45/46Q10

Interrupts

14.13.24 IPR6

Name: IPR6

Address: 0xEBB

Peripheral Interrupt Priority Register

Bit 7 6 5 4 3 2 1 0

CLC8IP CLC7IP CLC6IP CLC5IP CCP2IP CCP1IP

Access R/W R/W R/W R/W R/W R/W

Reset 0 0 0 0 1 1

Bits 4, 5, 6, 7 – CLCyIP CLCx Interrupt Priority bit

Value Description

1High priority

0Low priority

Bit 1 – CCP2IP ECCP2 Interrupt Priority bit

Value Description

1High priority

0Low priority

Bit 0 – CCP1IP ECCP1 Interrupt Priority bit

Value Description

1High priority

0Low priority

PIC18F26/45/46Q10

Interrupts

14.13.25 IPR7

Name: IPR7

Address: 0xEBC

Peripheral Interrupt Priority Register

Bit 7 6 5 4 3 2 1 0

SCANIP CRCIP NVMIP CWG1IP

Access R/W R/W R/W R/W

Reset 1 1 1 1

Bit 7 – SCANIP SCAN Interrupt Priority bit

Value Description

1High priority

0Low priority

Bit 6 – CRCIP CRC Interrupt Priority bit

Value Description

1High priority

0Low priority

Bit 5 – NVMIP NVM Interrupt Priority bit

Value Description

1High priority

0Low priority

Bit 0 – CWG1IP CWG Interrupt Priority bit

Value Description

1High priority

0Low priority

PIC18F26/45/46Q10

Interrupts

15. I/O Ports

Table 15-1. Port Availability per Device

Device PORTA PORTB PORTC PORTD PORTE

PIC18F26Q10 ● ● ● ●

PIC18F45/46Q10 ● ● ● ● ●

Each port has eight registers to control the operation. These registers are:

• PORTx registers (reads the levels on the pins of the device)

• LATx registers (output latch)

• TRISx registers (data direction)

• ANSELx registers (analog select)

• WPUx registers (weak pull-up)

• INLVLx (input level control)

• SLRCONx registers (slew rate control)

• ODCONx registers (open-drain control)

Most port pins share functions with device peripherals, both analog and digital. In general, when a

peripheral is enabled on a port pin, that pin cannot be used as a general purpose output; however, the pin

can still be read.

The Data Latch (LATx registers) is useful for read-modify-write operations on the value that the I/O pins

are driving.

A write operation to the LATx register has the same effect as a write to the corresponding PORTx

register. A read of the LATx register reads of the values held in the I/O PORT latches, while a read of the

PORTx register reads the actual I/O pin value.

Ports that support analog inputs have an associated ANSELx register. When an ANSELx bit is set, the

digital input buffer associated with that bit is disabled.

Disabling the input buffer prevents analog signal levels on the pin between a logic high and low from

causing excessive current in the logic input circuitry. A simplified model of a generic I/O port, without the

interfaces to other peripherals, is shown in the following figure:

PIC18F26/45/46Q10

I/O Ports

Figure 15-1. Generic I/O Port Operation

QD

CK

Write LATx

Data Register

I/O pin

Read PORTx

Write PORTx

TRISx

Read LATx

Data Bus

To digital peripherals

ANSELx

VDD

VSS

To analog peripherals

15.1 I/O Priorities

Each pin defaults to the PORT data latch after Reset. Other functions are selected with the peripheral pin

select logic. See “Peripheral Pin Select (PPS) Module” for more information.

Analog input functions, such as ADC and comparator inputs, are not shown in the peripheral pin select

lists. These inputs are active when the I/O pin is set for Analog mode using the ANSELx register. Digital

output functions may continue to control the pin when it is in Analog mode.

Analog outputs, when enabled, take priority over digital outputs and force the digital output driver into a

high-impedance state.

The pin function priorities are as follows:

1. Configuration bits

2. Analog outputs (disable the input buffers)

3. Analog inputs

4. Port inputs and outputs from PPS

Related Links

17. (PPS) Peripheral Pin Select Module

15.2 PORTx Registers

In this section the generic names such as PORTx, LATx, TRISx, etc. can be associated with all ports. For

availability of PORTD refer to Table 15-1. The functionality of PORTE is different compared to other ports

and is explained in a separate section.

PIC18F26/45/46Q10

I/O Ports

15.2.1 Data Register

PORTx is an 8-bit wide, bidirectional port. The corresponding data direction register is TRISx. Setting a

TRISx bit (‘1’) will make the corresponding PORTA pin an input (i.e., disable the output driver). Clearing a

TRISx bit (‘0’) will make the corresponding PORTx pin an output (i.e., it enables output driver and puts

the contents of the output latch on the selected pin). Example 15-1 shows how to initialize PORTA.

Reading the PORTx register reads the status of the pins, whereas writing to it will write to the PORT

latch. All write operations are read-modify-write operations. Therefore, a write to a port implies that the

port pins are read, this value is modified and then written to the PORT data latch (LATx).

The PORT data latch LATx holds the output port data and contains the latest value of a LATx or PORTx

write.

Example 15-1. EXAMPLE-1: Initializing PORTA

; This code example illustrates initializing the PORTA register.

; The other ports are initialized in the same manner.

CLRF LATA ; Set all output bits to zero

MOVLW B'11111000' ; Set RA<7:3> as inputs and RA<2:0> as outputs

MOVWF TRISA ;

BANKSEL ANSELA

CLRF ANSELA ; All pins are digital I/O

15.2.2 Direction Control

The TRISx register controls the PORTx pin output drivers, even when they are being used as analog

inputs. The user should ensure the bits in the TRISx register are maintained set when using them as

analog inputs. I/O pins configured as analog inputs always read ‘0’.

Related Links

15.5.6 TRISA

15.5.7 TRISB

15.5.8 TRISC

15.5.9 TRISD

15.5.10 TRISE

15.2.3 Analog Control

The ANSELx register is used to configure the Input mode of an I/O pin to analog. Setting the appropriate

ANSELx bit high will cause all digital reads on the pin to be read as ‘0’ and allow analog functions on the

pin to operate correctly.

The state of the ANSELx bits has no effect on digital output functions. A pin with TRIS clear and ANSEL

set will still operate as a digital output, but the Input mode will be analog. This can cause unexpected

behavior when executing READ-MODIFY-WRITE instructions on the affected port.

Important: The ANSELx bits default to the Analog mode after Reset. To use any pins as digital

general purpose or peripheral inputs, the corresponding ANSEL bits must be initialized to ‘0’ by

user software.

Related Links

15.5.16 ANSELA

15.5.17 ANSELB

PIC18F26/45/46Q10

I/O Ports

15.5.19 ANSELD

15.5.20 ANSELE

15.2.4 Open-Drain Control

The ODCONx register controls the open-drain feature of the port. Open-drain operation is independently

selected for each pin. When an ODCONx bit is set, the corresponding port output becomes an open-drain

driver capable of sinking current only. When an ODCONx bit is cleared, the corresponding port output pin

is the standard push-pull drive capable of sourcing and sinking current.

Important: It is not necessary to set open-drain control when using the pin for I2C; the I2C

module controls the pin and makes the pin open-drain.

Related Links

15.5.26 ODCONA

15.5.27 ODCONB

15.5.28 ODCONC

15.5.29 ODCOND

15.5.30 ODCONE

15.2.5 Slew Rate Control

The SLRCONx register controls the slew rate option for each port pin. Slew rate for each port pin can be

controlled independently. When an SLRCONx bit is set, the corresponding port pin drive is slew rate

limited. When an SLRCONx bit is cleared, The corresponding port pin drive slews at the maximum rate

possible.

Related Links

15.5.31 SLRCONA

15.5.32 SLRCONB

15.5.33 SLRCONC

15.5.34 SLRCOND

15.5.35 SLRCONE

15.2.6 Input Threshold Control

The INLVLx register controls the input voltage threshold for each of the available PORTx input pins. A

selection between the Schmitt Trigger CMOS or the TTL compatible thresholds is available. The input

threshold is important in determining the value of a read of the PORTx register and also the level at which

an interrupt-on-change occurs, if that feature is enabled. See link below for more information on threshold

levels.

Important: Changing the input threshold selection should be performed while all peripheral

modules are disabled. Changing the threshold level during the time a module is active may

inadvertently generate a transition associated with an input pin, regardless of the actual voltage

level on that pin.

Related Links

15.5.36 INLVLA

PIC18F26/45/46Q10

I/O Ports

15.5.37 INLVLB

15.5.38 INLVLC

15.5.39 INLVLD

15.5.40 INLVLE

15.2.7 Weak Pull-up Control

The WPUx register controls the individual weak pull-ups for each port pin.

Related Links

15.5.21 WPUA

15.5.22 WPUB

15.5.23 WPUC

15.5.24 WPUD

15.5.25 WPUE

15.2.8 Edge Selectable Interrupt-on-Change

An interrupt can be generated by detecting a signal at the port pin that has either a rising edge or a falling

edge. Individual pins can be independently configured to generate an interrupt. The interrupt-on-change

module is present on all the pins that are common between 28-pin and 40/44-pin devices. For further

details about the IOC module, refer to "Interrupt-on-Change" chapter.

Related Links

16. Interrupt-on-Change

15.3 PORTE Registers

Depending on the device selected, PORTE is implemented in two different ways.

15.3.1 PORTE on 40/44-Pin Devices

For 40/44-pin devices, PORTE is a 4-bit wide port. Three pins (RE0, RE1 and RE2) are individually

configurable as inputs or outputs. These pins have Schmitt Trigger input buffers. When selected as an

analog input, these pins will read as ‘0’s.

The corresponding data direction register is TRISE. Setting a TRISE bit (= 1) will make the corresponding

PORTE pin an input (i.e., disable the output driver). Clearing a TRISE bit (= 0) will make the

corresponding PORTE pin an output (i.e., enable the output driver and put the contents of the output latch

on the selected pin).

TRISE controls the direction of the REx pins, even when they are being used as analog pins. The user

must make sure to keep the pins configured as inputs when using them as analog inputs. RE<2:0> bits

have other registers associated with them (i.e., ANSELE, WPUE, INLVLE, SLRCONE and ODCONE).

The functionality is similar to the other ports.

The Data Latch register (LATE) is also memory-mapped. Read-modify-write operations on the LATE

register read and write the latched output value for PORTE.

Important: On a Power-on Reset, RE<2:0> are configured as analog inputs.

PIC18F26/45/46Q10

I/O Ports

The fourth pin of PORTE (MCLR/VPP/RE3) is an input-only pin. Its operation is controlled by the MCLRE

Configuration bit. When selected as a port pin (MCLRE = 0), it functions as a digital input-only pin; as

such, it does not have TRIS or LAT bits associated with its operation. Otherwise, it functions as the

device’s Master Clear input. In either configuration, RE3 also functions as the programming voltage input

during programming.

RE3 in PORTE register is a read-only bit and will read ‘1’ when MCLRE = 1 (i.e., Master Clear enabled).

Important: On a Power-on Reset, RE3 is enabled as a digital input-only if Master Clear

functionality is disabled.

Example 15-2. EXAMPLE-2: Initializing PORTE

CLRF PORTE ; Initialize PORTE by

; clearing output

; data latches

CLRF LATE ; Alternate method

; to clear output

; data latches

CLRF ANSELE ; Configure analog pins

; for digital only

MOVLW 05h ; Value used to

; initialize data

; direction

MOVWF TRISE ; Set RE<0> as input

; RE<1> as output

; RE<2> as input

15.3.2 PORTE on 28-Pin Devices

For 28-pin devices, PORTE is only available when Master Clear functionality is disabled (MCLRE = 0). In

this case, PORTE is a single bit, input-only port comprised of RE3 only. The pin operates as previously

described. RE3 in PORTE register is a read-only bit and will read ‘1’ when MCLRE = 1 (i.e., Master Clear

enabled).

15.3.3 RE3 Weak Pull-Up

The port RE3 pin has an individually controlled weak internal pull-up. When set, the WPUE3 bit enables

the RE3 pin pull-up. When the RE3 port pin is configured as MCLR, (CONFIG2L, MCLRE = 1 and

CONFIG4H, LVP = 0), or configured for Low-Voltage Programming, (MCLRE = x and LVP = 1), the pull-

up is always enabled and the WPUE3 bit has no effect.

15.3.4 PORTE Interrupt-on-Change

The interrupt-on-change feature is available only on the RE3 pin for all devices.

Related Links

16. Interrupt-on-Change

PIC18F26/45/46Q10

I/O Ports

15.4 Register Summary - Input/Output

Address Name Bit Pos.

0x0F08 INLVLA 7:0 INLVLA7 INLVLA6 INLVLA5 INLVLA4 INLVLA3 INLVLA2 INLVLA1 INLVLA0

0x0F09 SLRCONA 7:0 SLRA7 SLRA6 SLRA5 SLRA4 SLRA3 SLRA2 SLRA1 SLRA0

0x0F0A ODCONA 7:0 ODCA7 ODCA6 ODCA5 ODCA4 ODCA3 ODCA2 ODCA1 ODCA0

0x0F0B WPUA 7:0 WPUA7 WPUA6 WPUA5 WPUA4 WPUA3 WPUA2 WPUA1 WPUA0

0x0F0C ANSELA 7:0 ANSELA7 ANSELA6 ANSELA5 ANSELA4 ANSELA3 ANSELA2 ANSELA1 ANSELA0

0x0F0D

...

0x0F0F

Reserved

0x0F10 INLVLB 7:0 INLVLB7 INLVLB6 INLVLB5 INLVLB4 INLVLB3 INLVLB2 INLVLB1 INLVLB0

0x0F11 SLRCONB 7:0 SLRB7 SLRB6 SLRB5 SLRB4 SLRB3 SLRB2 SLRB1 SLRB0

0x0F12 ODCONB 7:0 ODCB7 ODCB6 ODCB5 ODCB4 ODCB3 ODCB2 ODCB1 ODCB0

0x0F13 WPUB 7:0 WPUB7 WPUB6 WPUB5 WPUB4 WPUB3 WPUB2 WPUB1 WPUB0

0x0F14 ANSELB 7:0 ANSELB7 ANSELB6 ANSELB5 ANSELB4 ANSELB3 ANSELB2 ANSELB1 ANSELB0

0x0F15

...

0x0F17

Reserved

0x0F18 INLVLC 7:0 INLVLC7 INLVLC6 INLVLC5 INLVLC4 INLVLC3 INLVLC2 INLVLC1 INLVLC0

0x0F19 SLRCONC 7:0 SLRC7 SLRC6 SLRC5 SLRC4 SLRC3 SLRC2 SLRC1 SLRC0

0x0F1A ODCONC 7:0 ODCC7 ODCC6 ODCC5 ODCC4 ODCC3 ODCC2 ODCC1 ODCC0

0x0F1B WPUC 7:0 WPUC7 WPUC6 WPUC5 WPUC4 WPUC3 WPUC2 WPUC1 WPUC0

0x0F1C ANSELC 7:0 ANSELC7 ANSELC6 ANSELC5 ANSELC4 ANSELC3 ANSELC2 ANSELC1 ANSELC0

0x0F1D INLVLD 7:0 INLVLD7 INLVLD6 INLVLD5 INLVLD4 INLVLD3 INLVLD2 INLVLD1 INLVLD0

0x0F1E SLRCOND 7:0 SLRD7 SLRD6 SLRD5 SLRD4 SLRD3 SLRD2 SLRD1 SLRD0

0x0F1F ODCOND 7:0 ODCD7 ODCD6 ODCD5 ODCD4 ODCD3 ODCD2 ODCD1 ODCD0

0x0F20 WPUD 7:0 WPUD7 WPUD6 WPUD5 WPUD4 WPUD3 WPUD2 WPUD1 WPUD0

0x0F21 ANSELD 7:0 ANSELD7 ANSELD6 ANSELD5 ANSELD4 ANSELD3 ANSELD2 ANSELD1 ANSELD0

0x0F22

...

0x0F24

Reserved

0x0F25 INLVLE 7:0 INLVLE3 INLVLE2 INLVLE1 INLVLE0

0x0F26 SLRCONE 7:0 SLRE2 SLRE1 SLRE0

0x0F27 ODCONE 7:0 ODCE2 ODCE1 ODCE0

0x0F28 WPUE 7:0 WPUE3 WPUE2 WPUE1 WPUE0

0x0F29 ANSELE 7:0 ANSELE2 ANSELE1 ANSELE0

0x0F2A

...

0x0F81

Reserved

0x0F82 LATA 7:0 LATA7 LATA6 LATA5 LATA4 LATA3 LATA2 LATA1 LATA0

0x0F83 LATB 7:0 LATB7 LATB6 LATB5 LATB4 LATB3 LATB2 LATB1 LATB0

0x0F84 LATC 7:0 LATC7 LATC6 LATC5 LATC4 LATC3 LATC2 LATC1 LATC0

0x0F85 LATD 7:0 LATD7 LATD6 LATD5 LATD4 LATD3 LATD2 LATD1 LATD0

0x0F86 LATE 7:0 LATE2 LATE1 LATE0

0x0F87 TRISA 7:0 TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0

0x0F88 TRISB 7:0 TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0

PIC18F26/45/46Q10

I/O Ports

...........continued

Address Name Bit Pos.

0x0F89 TRISC 7:0 TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0

0x0F8A TRISD 7:0 TRISD7 TRISD6 TRISD5 TRISD4 TRISD3 TRISD2 TRISD1 TRISD0

0x0F8B TRISE 7:0 TRISE3 TRISE2 TRISE1 TRISE0

0x0F8C PORTA 7:0 RA7 RA6 RA5 RA4 RA3 RA2 RA1 RA0

0x0F8D PORTB 7:0 RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0

0x0F8E PORTC 7:0 RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0

0x0F8F PORTD 7:0 RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0

0x0F90 PORTE 7:0 RE3 RE2 RE1 RE0

15.5 Register Definitions: Port Control

PIC18F26/45/46Q10

I/O Ports

15.5.1 PORTA

Name: PORTA

Address: 0xF8C

PORTA Register

Note: Writes to PORTA are actually written to the corresponding LATA register.

Reads from PORTA register return actual I/O pin values.

Bit 7 6 5 4 3 2 1 0

RA7 RA6 RA5 RA4 RA3 RA2 RA1 RA0

Access R/W R/W R/W R/W R/W R/W R/W R/W

Reset x x x x x x x x

Bits 0, 1, 2, 3, 4, 5, 6, 7 – RAn Port I/O Value bits

Reset States: POR/BOR = xxxxxxxx

All Other Resets = uuuuuuuu

Value Description

1Port pin is ≥ VIH

0Port pin is ≤ VIL

PIC18F26/45/46Q10

I/O Ports

15.5.2 PORTB

Name: PORTB

Address: 0xF8D

PORTB Register

Bit 7 6 5 4 3 2 1 0

RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0

Access R/W R/W R/W R/W R/W R/W R/W R/W

Reset x x x x x x x x

Bits 0, 1, 2, 3, 4, 5, 6, 7 – RBn Port I/O Value bits

Note: Bits RB6 and RB7 read ‘1’ while in Debug mode.

Reset States: POR/BOR = xxxxxxxx

All Other Resets = uuuuuuuu

Value Description

1Port pin is ≥ VIH

0Port pin is ≤ VIL

Note: Writes to PORTB are actually written to the corresponding LATB register.

Reads from PORTB register return actual I/O pin values.

PIC18F26/45/46Q10

I/O Ports

15.5.3 PORTC

Name: PORTC

Address: 0xF8E

PORTC Register

Bit 7 6 5 4 3 2 1 0

RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0

Access R/W R/W R/W R/W R/W R/W R/W R/W

Reset x x x x x x x x

Bits 0, 1, 2, 3, 4, 5, 6, 7 – RCn Port I/O Value bits

Reset States: POR/BOR = xxxxxxxx

All Other Resets = uuuuuuuu

Value Description

1Port pin is ≥ VIH

0Port pin is ≤ VIL

Note: Writes to PORTC are actually written to the corresponding LATC register.

Reads from PORTC register return actual I/O pin values.

PIC18F26/45/46Q10

I/O Ports

15.5.4 PORTD

Name: PORTD

Address: 0xF8F

PORTD Register

Bit 7 6 5 4 3 2 1 0

RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0

Access R/W R/W R/W R/W R/W R/W R/W R/W

Reset x x x x x x x x

Bits 0, 1, 2, 3, 4, 5, 6, 7 – RDn Port I/O Value bits

Reset States: POR/BOR = xxxxxxxx

All Other Resets = uuuuuuuu

Value Description

1Port pin is ≥ VIH

0Port pin is ≤ VIL

Note: Writes to PORTD are actually written to the corresponding LATD register.

Reads from PORTD register return actual I/O pin values.

PIC18F26/45/46Q10

I/O Ports

15.5.5 PORTE

Name: PORTE

Address: 0xF90

PORTE Register

Note: Writes to PORTE are actually written to the corresponding LATE register.

Reads from PORTE register return actual I/O pin values.

Bit 7 6 5 4 3 2 1 0

RE3 RE2 RE1 RE0

Access R/W R/W R/W R/W

Reset x x x x

Bits 0, 1, 2, 3 – REn Port I/O Value bits

Note:

1. Bit RE3 is read-only, and will read ‘1’ when MCLRE = 1 (Master Clear enabled).

2. 28-pin package only has RE3 in this register.

Reset States: POR/BOR = xxxx

All Other Resets = uuuu

Value Description

1Port pin is ≥ VIH

0Port pin is ≤ VIL

PIC18F26/45/46Q10

I/O Ports

15.5.6 TRISA

Name: TRISA

Address: 0xF87

Tri-State Control Register

Bit 7 6 5 4 3 2 1 0

TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0

Access R/W R/W R/W R/W R/W R/W R/W R/W

Reset 1 1 1 1 1 1 1 1

Bits 0, 1, 2, 3, 4, 5, 6, 7 – TRISAn TRISA Port I/O Tri-state Control bits

Value Description

1Port output driver is disabled

0Port output driver is enabled

PIC18F26/45/46Q10

I/O Ports

15.5.7 TRISB

Name: TRISB

Address: 0xF88

Tri-State Control Register

Bit 7 6 5 4 3 2 1 0

TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0

Access R/W R/W R/W R/W R/W R/W R/W R/W

Reset 1 1 1 1 1 1 1 1

Bits 0, 1, 2, 3, 4, 5, 6, 7 – TRISBn TRISB Port I/O Tri-state Control bits

Note: Bits TRISB6 and TRISB7 read ‘1’ while in Debug mode.

Value Description

1Port output driver is disabled

0Port output driver is enabled

PIC18F26/45/46Q10

I/O Ports

15.5.8 TRISC

Name: TRISC

Address: 0xF89

Tri-State Control Register

Bit 7 6 5 4 3 2 1 0

TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0

Access R/W R/W R/W R/W R/W R/W R/W R/W

Reset 1 1 1 1 1 1 1 1

Bits 0, 1, 2, 3, 4, 5, 6, 7 – TRISCn TRISC Port I/O Tri-state Control bits

Value Description

1Port output driver is disabled

0Port output driver is enabled

PIC18F26/45/46Q10

I/O Ports

15.5.9 TRISD

Name: TRISD

Address: 0xF8A

Tri-State Control Register

Bit 7 6 5 4 3 2 1 0

TRISD7 TRISD6 TRISD5 TRISD4 TRISD3 TRISD2 TRISD1 TRISD0

Access R/W R/W R/W R/W R/W R/W R/W R/W

Reset 1 1 1 1 1 1 1 1

Bits 0, 1, 2, 3, 4, 5, 6, 7 – TRISDn TRISD Port I/O Tri-state Control bits

Value Description

1Port output driver is disabled

0Port output driver is enabled

PIC18F26/45/46Q10

I/O Ports

15.5.10 TRISE

Name: TRISE

Address: 0xF8B

Tri-State Control Register

Bit 7 6 5 4 3 2 1 0

TRISE3 TRISE2 TRISE1 TRISE0

Access R/W R/W R/W R/W

Reset 1 1 1 1

Bits 0, 1, 2, 3 – TRISEn PortE I/O Tri-state Control bits

Note:

1. Not available on 28-pin devices.

2. TRISE3 bit is read-only, and will read ‘1’.

Value Description

1Port output driver is disabled

0Port output driver is enabled

PIC18F26/45/46Q10

I/O Ports

15.5.11 LATA

Name: LATA

Address: 0xF82

Output Latch Register

Bit 7 6 5 4 3 2 1 0

LATA7 LATA6 LATA5 LATA4 LATA3 LATA2 LATA1 LATA0

Access R/W R/W R/W R/W R/W R/W R/W R/W

Reset x x x x x x x x

Bits 0, 1, 2, 3, 4, 5, 6, 7 – LATAn Output Latch A Value bits

Reset States: POR/BOR = xxxxxxxx

All Other Resets = uuuuuuuuu

Note: Writes to LATA are equivalent with writes to the corresponding PORTA register. Reads from LATA

register return register values, not I/O pin values.

PIC18F26/45/46Q10

I/O Ports

15.5.12 LATB

Name: LATB

Address: 0xF83

Output Latch Register

Bit 7 6 5 4 3 2 1 0

LATB7 LATB6 LATB5 LATB4 LATB3 LATB2 LATB1 LATB0

Access R/W R/W R/W R/W R/W R/W R/W R/W

Reset x x x x x x x x

Bits 0, 1, 2, 3, 4, 5, 6, 7 – LATBn Output Latch B Value bits

Reset States: POR/BOR = xxxxxxxx

All Other Resets = uuuuuuuuu

Note: Writes to LATB are equivalent with writes to the corresponding PORTB register. Reads from LATB

register return register values, not I/O pin values.

PIC18F26/45/46Q10

I/O Ports

15.5.13 LATC

Name: LATC

Address: 0xF84

Output Latch Register

Bit 7 6 5 4 3 2 1 0

LATC7 LATC6 LATC5 LATC4 LATC3 LATC2 LATC1 LATC0

Access R/W R/W R/W R/W R/W R/W R/W R/W

Reset x x x x x x x x

Bits 0, 1, 2, 3, 4, 5, 6, 7 – LATCn Output Latch C Value bits

Reset States: POR/BOR = xxxxxxxx

All Other Resets = uuuuuuuuu

Note: Writes to LATC are equivalent with writes to the corresponding PORTC register. Reads from LATC

register return register values, not I/O pin values.

PIC18F26/45/46Q10

I/O Ports

15.5.14 LATD

Name: LATD

Address: 0xF85

Output Latch Register

Bit 7 6 5 4 3 2 1 0

LATD7 LATD6 LATD5 LATD4 LATD3 LATD2 LATD1 LATD0

Access R/W R/W R/W R/W R/W R/W R/W R/W

Reset x x x x x x x x

Bits 0, 1, 2, 3, 4, 5, 6, 7 – LATDn Output Latch D Value bits

Reset States: POR/BOR = xxxxxxxx

All Other Resets = uuuuuuuuu

Note: Writes to LATD are equivalent with writes to the corresponding PORTD register. Reads from LATD

register return register values, not I/O pin values.

PIC18F26/45/46Q10

I/O Ports

15.5.15 LATE

Name: LATE

Address: 0xF86

Output Latch Register

Bit 7 6 5 4 3 2 1 0

LATE2 LATE1 LATE0

Access R/W R/W R/W

Reset x x x

Bits 0, 1, 2 – LATEn Output Latch E Value bits

Reset States: POR/BOR = xxx

All Other Resets = uuu

Note: Writes to LATE are equivalent with writes to the corresponding PORTE register. Reads from LATE

register return register values, not I/O pin values.

PIC18F26/45/46Q10

I/O Ports

15.5.16 ANSELA

Name: ANSELA

Address: 0xF0C

Analog Select Register

Bit 7 6 5 4 3 2 1 0

ANSELA7 ANSELA6 ANSELA5 ANSELA4 ANSELA3 ANSELA2 ANSELA1 ANSELA0

Access R/W R/W R/W R/W R/W R/W R/W R/W

Reset 1 1 1 1 1 1 1 1

Bits 0, 1, 2, 3, 4, 5, 6, 7 – ANSELAn Analog Select on Pins RA<7:0>

Value Description

1Digital Input buffers are disabled

0ST and TTL input buffers are enabled

PIC18F26/45/46Q10

I/O Ports

15.5.17 ANSELB

Name: ANSELB

Address: 0xF14

Reset: 0x00

Analog Select Register

Bit 7 6 5 4 3 2 1 0

ANSELB7 ANSELB6 ANSELB5 ANSELB4 ANSELB3 ANSELB2 ANSELB1 ANSELB0

Access R/W R/W R/W R/W R/W R/W R/W R/W

Reset 1 1 1 1 1 1 1 1

Bits 0, 1, 2, 3, 4, 5, 6, 7 – ANSELBn Analog Select on Pins RB<7:0>

Value Description

1Digital Input buffers are disabled

0ST and TTL input buffers are enabled

PIC18F26/45/46Q10

I/O Ports

15.5.18 ANSELC

Name: ANSELC

Address: 0xF1C

Analog Select Register

Bit 7 6 5 4 3 2 1 0

ANSELC7 ANSELC6 ANSELC5 ANSELC4 ANSELC3 ANSELC2 ANSELC1 ANSELC0

Access R/W R/W R/W R/W R/W R/W R/W R/W

Reset 1 1 1 1 1 1 1 1

Bits 0, 1, 2, 3, 4, 5, 6, 7 – ANSELCn Analog Select on Pins RC<7:0>

Value Description

1Digital Input buffers are disabled

0ST and TTL input buffers are enabled

PIC18F26/45/46Q10

I/O Ports

15.5.19 ANSELD

Name: ANSELD

Address: 0xF21

Analog Select Register

Bit 7 6 5 4 3 2 1 0

ANSELD7 ANSELD6 ANSELD5 ANSELD4 ANSELD3 ANSELD2 ANSELD1 ANSELD0

Access R/W R/W R/W R/W R/W R/W R/W R/W

Reset 1 1 1 1 1 1 1 1

Bits 0, 1, 2, 3, 4, 5, 6, 7 – ANSELDn Analog Select on Pins RD<7:0>

Value Description

1Digital Input buffers are disabled

0ST and TTL input buffers are enabled

PIC18F26/45/46Q10

I/O Ports

15.5.20 ANSELE

Name: ANSELE

Address: 0xF29

Analog Select Register

Bit 7 6 5 4 3 2 1 0

ANSELE2 ANSELE1 ANSELE0

Access R/W R/W R/W

Reset 1 1 1

Bits 0, 1, 2 – ANSELEn Analog Select on Pins RE<7:0>

Value Description

1Digital Input buffers are disabled

0ST and TTL input buffers are enabled

PIC18F26/45/46Q10

I/O Ports

15.5.21 WPUA

Name: WPUA

Address: 0xF0B

Weak Pull-up Register

Bit 7 6 5 4 3 2 1 0

WPUA7 WPUA6 WPUA5 WPUA4 WPUA3 WPUA2 WPUA1 WPUA0

Access R/W R/W R/W R/W R/W R/W R/W R/W

Reset 0 0 0 0 0 0 0 0

Bits 0, 1, 2, 3, 4, 5, 6, 7 – WPUAn Weak Pull-up PORTA Control bits

Value Description

1Weak Pull-up enabled

0Weak Pull-up disabled

PIC18F26/45/46Q10

I/O Ports

15.5.22 WPUB

Name: WPUB

Address: 0xF13

Weak Pull-up Register

Bit 7 6 5 4 3 2 1 0

WPUB7 WPUB6 WPUB5 WPUB4 WPUB3 WPUB2 WPUB1 WPUB0

Access R/W R/W R/W R/W R/W R/W R/W R/W

Reset 0 0 0 0 0 0 0 0

Bits 0, 1, 2, 3, 4, 5, 6, 7 – WPUBn Weak Pull-up PORTA Control bits

Value Description

1Weak Pull-up enabled

0Weak Pull-up disabled

PIC18F26/45/46Q10

I/O Ports

15.5.23 WPUC

Name: WPUC

Address: 0xF1B

Weak Pull-up Register

Bit 7 6 5 4 3 2 1 0

WPUC7 WPUC6 WPUC5 WPUC4 WPUC3 WPUC2 WPUC1 WPUC0

Access R/W R/W R/W R/W R/W R/W R/W R/W

Reset 0 0 0 0 0 0 0 0

Bits 0, 1, 2, 3, 4, 5, 6, 7 – WPUCn Weak Pull-up PORTC Control bits

Value Description

1Weak Pull-up enabled

0Weak Pull-up disabled

PIC18F26/45/46Q10

I/O Ports

15.5.24 WPUD

Name: WPUD

Address: 0xF20

Weak Pull-up Register

Bit 7 6 5 4 3 2 1 0

WPUD7 WPUD6 WPUD5 WPUD4 WPUD3 WPUD2 WPUD1 WPUD0

Access R/W R/W R/W R/W R/W R/W R/W R/W

Reset 0 0 0 0 0 0 0 0

Bits 0, 1, 2, 3, 4, 5, 6, 7 – WPUDn Weak Pull-up PORTD Control bits

Value Description

1Weak Pull-up enabled

0Weak Pull-up disabled

PIC18F26/45/46Q10

I/O Ports

15.5.25 WPUE

Name: WPUE

Address: 0xF28

Weak Pull-up Register

Bit 7 6 5 4 3 2 1 0

WPUE3 WPUE2 WPUE1 WPUE0

Access R/W R/W R/W R/W

Reset 0 0 0 0

Bits 0, 1, 2, 3 – WPUEn Weak Pull-up PORTE Control bits

Note:

1. If MCLRE = 1, the weak pull-up in RE3 is always enabled; bit WPUE3 is not affected.

2. 28-pin package only has WPUE3 bit.

Value Description

1Weak Pull-up enabled

0Weak Pull-up disabled

PIC18F26/45/46Q10

I/O Ports

15.5.26 ODCONA

Name: ODCONA

Address: 0xF0A

Open-Drain Control Register

Bit 7 6 5 4 3 2 1 0

ODCA7 ODCA6 ODCA5 ODCA4 ODCA3 ODCA2 ODCA1 ODCA0

Access R/W R/W R/W R/W R/W R/W R/W R/W

Reset 0 0 0 0 0 0 0 0

Bits 0, 1, 2, 3, 4, 5, 6, 7 – ODCAn Open-Drain Configuration on Pins Rx<7:0>

Value Description

1Output drives only low-going signals (sink current only)

0Output drives both high-going and low-going signals (source and sink current)

PIC18F26/45/46Q10

I/O Ports

15.5.27 ODCONB

Name: ODCONB

Address: 0xF12

Open-Drain Control Register

Bit 7 6 5 4 3 2 1 0

ODCB7 ODCB6 ODCB5 ODCB4 ODCB3 ODCB2 ODCB1 ODCB0

Access R/W R/W R/W R/W R/W R/W R/W R/W

Reset 0 0 0 0 0 0 0 0

Bits 0, 1, 2, 3, 4, 5, 6, 7 – ODCBn Open-Drain Configuration on Pins Rx<7:0>

Value Description

1Output drives only low-going signals (sink current only)

0Output drives both high-going and low-going signals (source and sink current)

PIC18F26/45/46Q10

I/O Ports

15.5.28 ODCONC

Name: ODCONC

Address: 0xF1A

Open-Drain Control Register

Bit 7 6 5 4 3 2 1 0

ODCC7 ODCC6 ODCC5 ODCC4 ODCC3 ODCC2 ODCC1 ODCC0

Access R/W R/W R/W R/W R/W R/W R/W R/W

Reset 0 0 0 0 0 0 0 0

Bits 0, 1, 2, 3, 4, 5, 6, 7 – ODCCn Open-Drain Configuration on Pins Rx<7:0>

Value Description

1Output drives only low-going signals (sink current only)

0Output drives both high-going and low-going signals (source and sink current)

PIC18F26/45/46Q10

I/O Ports

15.5.29 ODCOND

Name: ODCOND

Address: 0xF1F

Open-Drain Control Register

Bit 7 6 5 4 3 2 1 0

ODCD7 ODCD6 ODCD5 ODCD4 ODCD3 ODCD2 ODCD1 ODCD0

Access R/W R/W R/W R/W R/W R/W R/W R/W

Reset 0 0 0 0 0 0 0 0

Bits 0, 1, 2, 3, 4, 5, 6, 7 – ODCDn Open-Drain Configuration on Pins Rx<7:0>

Value Description

1Output drives only low-going signals (sink current only)

0Output drives both high-going and low-going signals (source and sink current)

PIC18F26/45/46Q10

I/O Ports

15.5.30 ODCONE

Name: ODCONE

Address: 0xF27

Open-Drain Control Register

Bit 7 6 5 4 3 2 1 0

ODCE2 ODCE1 ODCE0

Access R/W R/W R/W

Reset 0 0 0

Bits 0, 1, 2 – ODCEn Open-Drain Configuration on Pins Rx<7:0>

Value Description

1Output drives only low-going signals (sink current only)

0Output drives both high-going and low-going signals (source and sink current)

PIC18F26/45/46Q10

I/O Ports

15.5.31 SLRCONA

Name: SLRCONA

Address: 0xF09

Slew Rate Control Register

Bit 7 6 5 4 3 2 1 0

SLRA7 SLRA6 SLRA5 SLRA4 SLRA3 SLRA2 SLRA1 SLRA0

Access R/W R/W R/W R/W R/W R/W R/W R/W

Reset 1 1 1 1 1 1 1 1

Bits 0, 1, 2, 3, 4, 5, 6, 7 – SLRAn Slew Rate Control on Pins Rx<7:0>, respectively

Value Description

1Port pin slew rate is limited

0Port pin slews at maximum rate

PIC18F26/45/46Q10

I/O Ports

15.5.32 SLRCONB

Name: SLRCONB

Address: 0xF11

Slew Rate Control Register

Bit 7 6 5 4 3 2 1 0

SLRB7 SLRB6 SLRB5 SLRB4 SLRB3 SLRB2 SLRB1 SLRB0

Access R/W R/W R/W R/W R/W R/W R/W R/W

Reset 1 1 1 1 1 1 1 1

Bits 0, 1, 2, 3, 4, 5, 6, 7 – SLRBn Slew Rate Control on Pins Rx<7:0>, respectively

Value Description

1Port pin slew rate is limited

0Port pin slews at maximum rate

PIC18F26/45/46Q10

I/O Ports

15.5.33 SLRCONC

Name: SLRCONC

Address: 0xF19

Slew Rate Control Register

Bit 7 6 5 4 3 2 1 0

SLRC7 SLRC6 SLRC5 SLRC4 SLRC3 SLRC2 SLRC1 SLRC0

Access R/W R/W R/W R/W R/W R/W R/W R/W

Reset 1 1 1 1 1 1 1 1

Bits 0, 1, 2, 3, 4, 5, 6, 7 – SLRCn Slew Rate Control on Pins Rx<7:0>, respectively

Value Description

1Port pin slew rate is limited

0Port pin slews at maximum rate

PIC18F26/45/46Q10

I/O Ports

15.5.34 SLRCOND

Name: SLRCOND

Address: 0xF1E

Slew Rate Control Register

Bit 7 6 5 4 3 2 1 0

SLRD7 SLRD6 SLRD5 SLRD4 SLRD3 SLRD2 SLRD1 SLRD0

Access R/W R/W R/W R/W R/W R/W R/W R/W

Reset 1 1 1 1 1 1 1 1

Bits 0, 1, 2, 3, 4, 5, 6, 7 – SLRDn Slew Rate Control on Pins Rx<7:0>, respectively

Value Description

1Port pin slew rate is limited

0Port pin slews at maximum rate

PIC18F26/45/46Q10

I/O Ports

15.5.35 SLRCONE

Name: SLRCONE

Address: 0xF26

Slew Rate Control Register

Bit 7 6 5 4 3 2 1 0

SLRE2 SLRE1 SLRE0

Access R/W R/W R/W

Reset 1 1 1

Bits 0, 1, 2 – SLREn Slew Rate Control on Pins Rx<7:0>, respectively

Value Description

1Port pin slew rate is limited

0Port pin slews at maximum rate

PIC18F26/45/46Q10

I/O Ports

15.5.36 INLVLA

Name: INLVLA

Address: 0xF08

Input Level Control Register

Bit 7 6 5 4 3 2 1 0

INLVLA7 INLVLA6 INLVLA5 INLVLA4 INLVLA3 INLVLA2 INLVLA1 INLVLA0

Access R/W R/W R/W R/W R/W R/W R/W R/W

Reset 1 1 1 1 1 1 1 1

Bits 0, 1, 2, 3, 4, 5, 6, 7 – INLVLAn Input Level Select on Pins Rx<7:0>, respectively

Value Description

1ST input used for port reads and interrupt-on-change

0TTL input used for port reads and interrupt-on-change

PIC18F26/45/46Q10

I/O Ports

15.5.37 INLVLB

Name: INLVLB

Address: 0xF10

Input Level Control Register

Bit 7 6 5 4 3 2 1 0

INLVLB7 INLVLB6 INLVLB5 INLVLB4 INLVLB3 INLVLB2 INLVLB1 INLVLB0

Access R/W R/W R/W R/W R/W R/W R/W R/W

Reset 1 1 1 1 1 1 1 1

Bits 0, 1, 2, 3, 4, 5, 6, 7 – INLVLBn Input Level Select on Pins Rx<7:0>, respectively

Note: INLVLB2 / INLVLB1: Pins read the I2C ST inputs when MSSP inputs select these pins, and I2C

mode is enabled.

Value Description

1ST input used for port reads and interrupt-on-change

0TTL input used for port reads and interrupt-on-change

PIC18F26/45/46Q10

I/O Ports

15.5.38 INLVLC

Name: INLVLC

Address: 0xF18

Input Level Control Register

Bit 7 6 5 4 3 2 1 0

INLVLC7 INLVLC6 INLVLC5 INLVLC4 INLVLC3 INLVLC2 INLVLC1 INLVLC0

Access R/W R/W R/W R/W R/W R/W R/W R/W

Reset 1 1 1 1 1 1 1 1

Bits 0, 1, 2, 3, 4, 5, 6, 7 – INLVLCn Input Level Select on Pins Rx<7:0>, respectively

Note: INLVLC4 / INLVLC3: Pins read the I2C ST inputs when MSSP inputs select these pins, and I2C

mode is enabled.

Value Description

1ST input used for port reads and interrupt-on-change

0TTL input used for port reads and interrupt-on-change

PIC18F26/45/46Q10

I/O Ports

15.5.39 INLVLD

Name: INLVLD

Address: 0xF1D

Input Level Control Register

Bit 7 6 5 4 3 2 1 0

INLVLD7 INLVLD6 INLVLD5 INLVLD4 INLVLD3 INLVLD2 INLVLD1 INLVLD0

Access R/W R/W R/W R/W R/W R/W R/W R/W

Reset 1 1 1 1 1 1 1 1

Bits 0, 1, 2, 3, 4, 5, 6, 7 – INLVLDn Input Level Select on Pins Rx<7:0>, respectively

Value Description

1ST input used for port reads and interrupt-on-change

0TTL input used for port reads and interrupt-on-change

PIC18F26/45/46Q10

I/O Ports

15.5.40 INLVLE

Name: INLVLE

Address: 0xF25

Input Level Control Register

Bit 7 6 5 4 3 2 1 0

INLVLE3 INLVLE2 INLVLE1 INLVLE0

Access R/W R/W R/W R/W

Reset 1 1 1 1

Bits 0, 1, 2, 3 – INLVLEn Input Level Select on Pins Rx<3:0>, respectively

Note: 28-pin package only has INLVLE3 in this register.

Value Description

1ST input used for port reads and interrupt-on-change

0TTL input used for port reads and interrupt-on-change

PIC18F26/45/46Q10

I/O Ports

16. Interrupt-on-Change

16.1 Features

• Interrupt-on-change Enable (Master Switch)

• Individual Pin Configuration

• Rising and Falling Edge Detection

• Individual Pin Interrupt Flags

16.2 Overview

All the pins of PORTA, PORTB, PORTC, and pin RE3 of PORTE can be configured to operate as

Interrupt-on-Change (IOC) pins on PIC18F26/45/46Q10 family devices. An interrupt can be generated by

detecting a signal that has either a rising edge or a falling edge. Any individual port pin, or combination of

port pins, can be configured to generate an interrupt.

PIC18F26/45/46Q10

Interrupt-on-Change

16.3 Block Diagram

Figure 16-1. Interrupt-on-Change Block Diagram (PORTA Example)

IOCANx

IOCAPx

Q2

Q4Q1

data bus =

0 or 1

write IOCAFx

IOCIE

to data bus

IOCAFx

edge

detect

IOC interrupt

to CPU core

from all other

IOCnFx individual

pin detectors

D Q

S

D Q

R

D Q

R

RAx

Q1

Q2

Q3

Q4

Q4Q1

Q1

Q2

Q3

Q4

Q1

Q2

Q3

Q4

Q4Q1 Q4Q1Q4Q1

FOSC

Rev. 10-000 037A

6/2/201 4

16.4 Enabling the Module

To allow individual port pins to generate an interrupt, the IOCIE bit of the PIE0 register must be set. If the

IOCIE bit is disabled, the edge detection on the pin will still occur, but an interrupt will not be generated.

Related Links

14.13.10 PIE0

16.5 Individual Pin Configuration

For each port pin, a rising edge detector and a falling edge detector are present. To enable a pin to detect

a rising edge, the associated bit of the IOCxP register is set. To enable a pin to detect a falling edge, the

associated bit of the IOCxN register is set.

PIC18F26/45/46Q10

Interrupt-on-Change

A pin can be configured to detect rising and falling edges simultaneously by setting both associated bits

of the IOCxP and IOCxN registers, respectively.

16.6 Interrupt Flags

The IOCAFx, IOCBFx, IOCCFx and IOCEF3 bits located in the IOCAF, IOCBF, IOCCF and IOCEF

registers respectively, are status flags that correspond to the interrupt-on-change pins of the associated

port. If an expected edge is detected on an appropriately enabled pin, then the status flag for that pin will

be set, and an interrupt will be generated if the IOCIE bit is set. The IOCIF bit of the PIR0 register reflects

the status of all IOCAFx, IOCBFx, IOCCFx and IOCEF3 bits.

Related Links

14.13.2 PIR0

16.7 Clearing Interrupt Flags

The individual status flags, (IOCAFx, IOCBFx, IOCCFx and IOCEF3) bits, can be cleared by resetting

them to zero. If another edge is detected during this clearing operation, the associated status flag will be

set at the end of the sequence, regardless of the value actually being written.

In order to ensure that no detected edge is lost while clearing flags, only AND operations masking out

known changed bits should be performed. The following sequence is an example of what should be

performed.

Example 16-1. Clearing Interrupt Flags

(PORTA Example)

MOVLW 0xff

XORWF IOCAF, W

ANDWF IOCAF, F

16.8 Operation in Sleep

The interrupt-on-change interrupt sequence will wake the device from Sleep mode, if the IOCIE bit is set.

If an edge is detected while in Sleep mode, the IOCxF register will be updated prior to the first instruction

executed out of Sleep.

PIC18F26/45/46Q10

Interrupt-on-Change

16.9 Register Summary - Interrupt-on-Change

Address Name Bit Pos.

0x0F05 IOCAF 7:0 IOCAF7 IOCAF6 IOCAF5 IOCAF4 IOCAF3 IOCAF2 IOCAF1 IOCAF0

0x0F06 IOCAN 7:0 IOCAN7 IOCAN6 IOCAN5 IOCAN4 IOCAN3 IOCAN2 IOCAN1 IOCAN0

0x0F07 IOCAP 7:0 IOCAP7 IOCAP6 IOCAP5 IOCAP4 IOCAP3 IOCAP2 IOCAP1 IOCAP0

0x0F08

...

0x0F0C

Reserved

0x0F0D IOCBF 7:0 IOCBF7 IOCBF6 IOCBF5 IOCBF4 IOCBF3 IOCBF2 IOCBF1 IOCBF0

0x0F0E IOCBN 7:0 IOCBN7 IOCBN6 IOCBN5 IOCBN4 IOCBN3 IOCBN2 IOCBN1 IOCBN0

0x0F0F IOCBP 7:0 IOCBP7 IOCBP6 IOCBP5 IOCBP4 IOCBP3 IOCBP2 IOCBP1 IOCBP0

0x0F10

...

0x0F14

Reserved

0x0F15 IOCCF 7:0 IOCCF7 IOCCF6 IOCCF5 IOCCF4 IOCCF3 IOCCF2 IOCCF1 IOCCF0

0x0F16 IOCCN 7:0 IOCCN7 IOCCN6 IOCCN5 IOCCN4 IOCCN3 IOCCN2 IOCCN1 IOCCN0

0x0F17 IOCCP 7:0 IOCCP7 IOCCP6 IOCCP5 IOCCP4 IOCCP3 IOCCP2 IOCCP1 IOCCP0

0x0F18

...

0x0F21

Reserved

0x0F22 IOCEF 7:0 IOCEF3

0x0F23 IOCEN 7:0 IOCEN3

0x0F24 IOCEP 7:0 IOCEP3

16.10 Register Definitions: Interrupt-on-Change Control

PIC18F26/45/46Q10

Interrupt-on-Change

16.10.1 IOCAF

Name: IOCAF

Address: 0xF05

PORTA Interrupt-on-Change Flag Register Example

Bit 7 6 5 4 3 2 1 0

IOCAF7 IOCAF6 IOCAF5 IOCAF4 IOCAF3 IOCAF2 IOCAF1 IOCAF0

Access R/W/HS R/W/HS R/W/HS R/W/HS R/W/HS R/W/HS R/W/HS R/W/HS

Reset 0 0 0 0 0 0 0 0

Bits 0, 1, 2, 3, 4, 5, 6, 7 – IOCAFn Interrupt-on-Change Flag bits

Value Condition Description

1IOCAP[n]=1A positive edge was detected on the RA[n] pin

1IOCAN[n]=1A negative edge was detected on the RA[n] pin

0IOCAP[n]=x and

IOCAN[n]=x

No change was detected, or the user cleared the detected change

PIC18F26/45/46Q10

Interrupt-on-Change

16.10.2 IOCBF

Name: IOCBF

Address: 0xF0D

PORTB Interrupt-on-Change Flag Register Example

Bit 7 6 5 4 3 2 1 0

IOCBF7 IOCBF6 IOCBF5 IOCBF4 IOCBF3 IOCBF2 IOCBF1 IOCBF0

Access R/W/HS R/W/HS R/W/HS R/W/HS R/W/HS R/W/HS R/W/HS R/W/HS

Reset 0 0 0 0 0 0 0 0

Bits 0, 1, 2, 3, 4, 5, 6, 7 – IOCBFn Interrupt-on-Change Flag bits

Value Condition Description

1IOCBP[n]=1A positive edge was detected on the RB[n] pin

1IOCBN[n]=1A negative edge was detected on the RB[n] pin

0IOCBP[n]=x and

IOCBN[n]=x

No change was detected, or the user cleared the detected change

PIC18F26/45/46Q10

Interrupt-on-Change

16.10.3 IOCCF

Name: IOCCF

Address: 0xF15

PORTC Interrupt-on-Change Flag Register

Bit 7 6 5 4 3 2 1 0

IOCCF7 IOCCF6 IOCCF5 IOCCF4 IOCCF3 IOCCF2 IOCCF1 IOCCF0

Access R/W/HS R/W/HS R/W/HS R/W/HS R/W/HS R/W/HS R/W/HS R/W/HS

Reset 0 0 0 0 0 0 0 0

Bits 0, 1, 2, 3, 4, 5, 6, 7 – IOCCFn Interrupt-on-Change Flag bits

Value Condition Description

1IOCCP[n]=1A positive edge was detected on the RC[n] pin

1IOCCN[n]=1A negative edge was detected on the RC[n] pin

0IOCCP[n]=x and

IOCCN[n]=x

No change was detected, or the user cleared the detected

change

PIC18F26/45/46Q10

Interrupt-on-Change

16.10.4 IOCEF

Name: IOCEF

Address: 0xF22

PORTE Interrupt-on-Change Flag Register

Bit 7 6 5 4 3 2 1 0

IOCEF3

Access R/W/HS

Reset 0

Bit 3 – IOCEF3 PORTE Interrupt-on-Change Flag bits(1)

Value Condition Description

1IOCEP[n]=1A positive edge was detected on the RE[n] pin

1IOCEN[n]=1A negative edge was detected on the RE[n] pin

0IOCEP[n]=x and

IOCEN[n]=x

No change was detected, or the user cleared the detected change

Note:

1. If MCLRE = 1 or LVP = 1, RE3 port functionality is disabled and IOC on RE3 is not available.

PIC18F26/45/46Q10

Interrupt-on-Change

16.10.5 IOCAN

Name: IOCAN

Address: 0xF06

Interrupt-on-Change Negative Edge Register Example

Bit 7 6 5 4 3 2 1 0

IOCAN7 IOCAN6 IOCAN5 IOCAN4 IOCAN3 IOCAN2 IOCAN1 IOCAN0

Access R/W R/W R/W R/W R/W R/W R/W R/W

Reset 0 0 0 0 0 0 0 0

Bits 0, 1, 2, 3, 4, 5, 6, 7 – IOCANn Interrupt-on-Change Negative Edge Enable bits

Value Description

1Interrupt-on-Change enabled on the IOCA pin for a negative-going edge. Associated Status

bit and interrupt flag will be set upon detecting an edge.

0Interrupt-on-Change disabled for the associated pin

PIC18F26/45/46Q10

Interrupt-on-Change

16.10.6 IOCBN

Name: IOCBN

Address: 0xF0E

Interrupt-on-Change Negative Edge Register Example

Bit 7 6 5 4 3 2 1 0

IOCBN7 IOCBN6 IOCBN5 IOCBN4 IOCBN3 IOCBN2 IOCBN1 IOCBN0

Access R/W R/W R/W R/W R/W R/W R/W R/W

Reset 0 0 0 0 0 0 0 0

Bits 0, 1, 2, 3, 4, 5, 6, 7 – IOCBNn Interrupt-on-Change Negative Edge Enable bits

Value Description

1Interrupt-on-Change enabled on the IOCA pin for a negative-going edge. Associated Status

bit and interrupt flag will be set upon detecting an edge.

0Interrupt-on-Change disabled for the associated pin.

PIC18F26/45/46Q10

Interrupt-on-Change

16.10.7 IOCCN

Name: IOCCN

Address: 0xF16

Interrupt-on-Change Negative Edge Register Example

Bit 7 6 5 4 3 2 1 0

IOCCN7 IOCCN6 IOCCN5 IOCCN4 IOCCN3 IOCCN2 IOCCN1 IOCCN0

Access R/W R/W R/W R/W R/W R/W R/W R/W

Reset 0 0 0 0 0 0 0 0

Bits 0, 1, 2, 3, 4, 5, 6, 7 – IOCCNn Interrupt-on-Change Negative Edge Enable bits

Value Description

1Interrupt-on-Change enabled on the IOCA pin for a negative-going edge. Associated Status

bit and interrupt flag will be set upon detecting an edge.

0Interrupt-on-Change disabled for the associated pin.

PIC18F26/45/46Q10

Interrupt-on-Change

16.10.8 IOCEN

Name: IOCEN

Address: 0xF23

Interrupt-on-Change Negative Edge Register Example

Bit 7 6 5 4 3 2 1 0

IOCEN3

Access R/W

Reset 0

Bit 3 – IOCEN3 Interrupt-on-Change Negative Edge Enable bits(1)

Value Description

1Interrupt-on-Change enabled on the IOCA pin for a negative-going edge. Associated Status

bit and interrupt flag will be set upon detecting an edge.

0Interrupt-on-Change disabled for the associated pin

Note:

1. If MCLRE = 1 or LVP = 1, RE3 port functionality is disabled and IOC on RE3 is not available.

PIC18F26/45/46Q10

Interrupt-on-Change

16.10.9 IOCAP

Name: IOCAP

Address: 0xF07

Interrupt-on-Change Positive Edge Register

Bit 7 6 5 4 3 2 1 0

IOCAP7 IOCAP6 IOCAP5 IOCAP4 IOCAP3 IOCAP2 IOCAP1 IOCAP0

Access R/W R/W R/W R/W R/W R/W R/W R/W

Reset 0 0 0 0 0 0 0 0

Bits 0, 1, 2, 3, 4, 5, 6, 7 – IOCAPn Interrupt-on-Change Positive Edge Enable bits

Value Description

1Interrupt-on-Change enabled on the IOCA pin for a positive-going edge. Associated Status

bit and interrupt flag will be set upon detecting an edge.

0Interrupt-on-Change disabled for the associated pin.

PIC18F26/45/46Q10

Interrupt-on-Change

16.10.10 IOCBP

Name: IOCBP

Address: 0xF0F

Interrupt-on-Change Positive Edge Register

Bit 7 6 5 4 3 2 1 0

IOCBP7 IOCBP6 IOCBP5 IOCBP4 IOCBP3 IOCBP2 IOCBP1 IOCBP0

Access R/W R/W R/W R/W R/W R/W R/W R/W

Reset 0 0 0 0 0 0 0 0

Bits 0, 1, 2, 3, 4, 5, 6, 7 – IOCBPn Interrupt-on-Change Positive Edge Enable bits

Value Description

1Interrupt-on-Change enabled on the IOCB pin for a positive-going edge. Associated Status

bit and interrupt flag will be set upon detecting an edge.

0Interrupt-on-Change disabled for the associated pin.

PIC18F26/45/46Q10

Interrupt-on-Change

16.10.11 IOCCP

Name: IOCCP

Address: 0xF17

Interrupt-on-Change Positive Edge Register

Bit 7 6 5 4 3 2 1 0

IOCCP7 IOCCP6 IOCCP5 IOCCP4 IOCCP3 IOCCP2 IOCCP1 IOCCP0

Access R/W R/W R/W R/W R/W R/W R/W R/W

Reset 0 0 0 0 0 0 0 0

Bits 0, 1, 2, 3, 4, 5, 6, 7 – IOCCPn Interrupt-on-Change Positive Edge Enable bits

Value Description

1Interrupt-on-Change enabled on the IOCC pin for a positive-going edge. Associated Status

bit and interrupt flag will be set upon detecting an edge.

0Interrupt-on-Change disabled for the associated pin.

PIC18F26/45/46Q10

Interrupt-on-Change

16.10.12 IOCEP

Name: IOCEP

Address: 0xF24

Interrupt-on-Change Positive Edge Register

Bit 7 6 5 4 3 2 1 0

IOCEP3

Access R/W

Reset 0

Bit 3 – IOCEP3 Interrupt-on-Change Positive Edge Enable bit(1)

Value Description

1Interrupt-on-Change enabled on the IOCE pin for a positive-going edge. Associated Status

bit and interrupt flag will be set upon detecting an edge.

0Interrupt-on-Change disabled for the associated pin.

Note:

1. If MCLRE = 1 or LVP = 1, RE3 port functionality is disabled and IOC on RE3 is not available.

PIC18F26/45/46Q10

Interrupt-on-Change

17. (PPS) Peripheral Pin Select Module

The Peripheral Pin Select (PPS) module connects peripheral inputs and outputs to the device I/O pins.

Only digital signals are included in the selections. All analog inputs and outputs remain fixed to their

assigned pins. Input and output selections are independent as shown in the figure below.

The peripheral input is selected with the peripheral 17.9.1 xxxPPS register, and the peripheral output is

selected with the PORT 17.9.2 RxyPPS register . For example, to select PORTC<7> as the EUSART RX

input, set RXxPPS to 0x17 as shown in the input table, and to select PORTC<6> as the EUSART TX

output set RC6PPS to 0x09 as shown in the output table.

Figure 17-1. Simplified PPS Block Diagram

Rev. 10-000 262B

2/22/201 7

xyzPPS

RC7

abcPPS

RA0

Peripheral xyz

Peripheral abc

RA0PPS

RxyPPS

RC7PPS

RA0

Rxy

RC7

17.1 PPS Inputs

Each peripheral has an xxxPPS register with which the input pin to the peripheral is selected. Not all ports

are available for input as shown in the following table.

Multiple peripherals can operate from the same source simultaneously. Port reads always return the pin

level regardless of peripheral PPS selection. If a pin also has analog functions associated, the ANSEL bit

for that pin must be cleared to enable the digital input buffer.

Important: The notation “xxx” in the generic register name is a place holder for the peripheral

identifier. For example, xxx = INT for the INTPPS register.

PIC18F26/45/46Q10

(PPS) Peripheral Pin Select Module

Table 17-1. PPS Input Selection Register Details

Peripheral PPS Input

Register

Default Pin

Selection

at POR

Register

Reset

Value

at POR

PORT From Which Input Is

Available

28-Pin Devices 40-Pin Devices

Interrupt 0 INT0PPS RB0 0x08 A B — A B — —

Interrupt 1 INT1PPS RB1 0x09 A B — A B — —

Interrupt 2 INT2PPS RB2 0x0A A B — A B — —

Timer0 Clock T0CKIPPS RA4 0x04 A B — A B — —

Timer1 Clock T1CKIPPS RC0 0x10 A — C A — C —

Timer1 Gate T1GPPS RB5 0x0D — B C — B C —

Timer3 Clock T3CKIPPS RC0 0x10 — B C — B C —

Timer3 Gate T3GPPS RC0 0x10 A — C A — C —

Timer5 Clock T5CKIPPS RC2 0x12 A — C A — C —

Timer5 Gate T5GPPS RB4 0x0C — B C — B — D

Timer2 Clock T2INPPS RC3 0x13 A — C A — C —

Timer4 Clock T4INPPS RC5 0x15 — B C — B C —

Timer6 Clock T6INPPS RB7 0x0F — B C — B — D

ADC

Conversion

Trigger

ADACTPPS RB4 0x0C — B C — B — D

CCP1 CCP1PPS RC2 0x12 — B C — B C —

CCP2 CCP2PPS RC1 0x11 — B C — B C —

CWG CWG1PPS RB0 0x08 — B C — B — D

DSM Carrier

Low

MDCARLPPS RA3 0x03 A — C A — — D

DSM Carrier

High

MDCARHPPS RA4 0x04 A — C A — — D

DSM Source MDSRCPPS RA5 0x05 A — C A — — D

EUSART1

Receive

RX1PPS RC7 0x17 — B C — B C —

EUSART1

Clock

CK1PPS RC6 0x16 — B C — B C —

EUSART2

Receive

RX2PPS RB7 0x0F — B C — B — D

EUSART2

Clock

CK2PPS RB6 0x0E — B C — B — D

PIC18F26/45/46Q10

(PPS) Peripheral Pin Select Module

...........continued

Peripheral PPS Input

Register

Default Pin

Selection

at POR

Register

Reset

Value

at POR

PORT From Which Input Is

Available

28-Pin Devices 40-Pin Devices

MSSP1 Clock SSP1CLKPPS RC3 0x13 — B C — B C —

MSSP1 Data SSP1DATPPS RC4 0x14 — B C — B C —

MSSP1 Slave

Select

SSP1SSPPS RA5 0x05 A — C A — — D

MSSP2 Clock SSP2CLKPPS RB1 0x09 — B C — B — D

MSSP2 Data SSP2DATPPS RB2 0x0A — B C — B — D

MSSP2 Slave

Select

SSP2SSPPS RB0 0x08 — B C — B — D

CLCIN0 CLCIN0PPS RA0 0x00 A — C A — C —

CLCIN1 CLCIN1PPS RA1 0x01 A — C A — C —

CLCIN2 CLCIN2PPS RB6 0x0E — B C — B — D

CLCIN3 CLCIN3PPS RB7 0x0F — B C — B — D

CLCIN4 CLCIN4PPS RA0 0x00 A — C A — C —

CLCIN5 CLCIN5PPS RA1 0x01 A — C A — C —

CLCIN6 CLCIN6PPS RB6 0x0E — B C — B — D

CLCIN7 CLCIN7PPS RB7 0x0F — B C — B — D

17.2 PPS Outputs

Each I/O pin has an RxyPPS register with which the pin output source is selected. With few exceptions,

the port TRIS control associated with that pin retains control over the pin output driver. Peripherals that

control the pin output driver as part of the peripheral operation will override the TRIS control as needed.

These peripherals include:

• EUSART (synchronous operation)

• MSSP (I2C)

Although every pin has its own RxyPPS peripheral selection register, the selections are identical for every

pin as shown in the following table.

Important: The notation “Rxy” is a place holder for the pin identifier. The 'x' holds the place of

the PORT letter and the 'y' holds the place of the bit number. For example, Rxy = RA0 for the

RA0PPS register.

PIC18F26/45/46Q10

(PPS) Peripheral Pin Select Module

Table 17-2. Peripheral PPS Output Selection Codes

RxyPPS Pin Rxy Output Source

PORT To Which Output Can Be Directed

28-Pin Devices 40-Pin Devices

0x1F CLC8OUT — B C — B — D —

0x1E CLC7OUT — B C — B — D —

0x1D CLC6OUT A — C A — C — —

0x1C CLC5OUT A — C A — C — —

0x1B CLC4OUT — B C — B — D —

0x1A CLC3OUT — B C — B — D —

0x19 CLC2OUT A — C A — C — —

0x18 CLC1OUT A — C A — C — —

0x17 ADGRDB A — C A — C — —

0x16 ADGRDA A — C A — C — —

0x15 DSM A — C A — — D —

0x14 CLKR — B C — B C — —

0x13 TMR0 — B C — B C — —

0x12 MSSP2 (SDO/SDA) — B C — B — D —

0x11 MSSP2 (SCK/SCL) — B C — B — D —

0x10 MSSP1 (SDO/SDA) — B C — B C — —

0x0F MSSP1 (SCK/SCL) — B C — B C — —

0x0E CMP2 A — C A — — — E

0x0D CMP1 A — C A — — D —

0x0C EUSART2 (DT) — B C — B — D —

0x0B EUSART2 (TX/CK) — B C — B — D —

0x0A EUSART1 (DT) — B C — B C — —

0x09 EUSART1 (TX/CK) — B C — B C — —

0x08 PWM4 A — C A — C — —

0x07 PWM3 A — C A — — D —

0x06 CCP2 — B C — B C — —

0x05 CCP1 — B C — B C — —

0x04 CWG1D — B C — B — D —

0x03 CWG1C — B C — B — D —

0x02 CWG1B — B C — B — D —

PIC18F26/45/46Q10

(PPS) Peripheral Pin Select Module

...........continued

RxyPPS Pin Rxy Output Source

PORT To Which Output Can Be Directed

28-Pin Devices 40-Pin Devices

0x01 CWG1A — B C — B C — —

0x00 LATxy A B C A B C D E

17.3 Bidirectional Pins

PPS selections for peripherals with bidirectional signals on a single pin must be made so that the PPS

input and PPS output select the same pin. Peripherals that have bidirectional signals include:

• EUSART (DT/RXxPPS and TX/CKxPPS pins for synchronous operation)

• MSSP (I2C SDA/SSPxDATPPS and SCL/SSPxCLKPPS)

Important: The I2C default inputs, and a limited number of other alternate pins, are I2C and

SMBus compatible. Clock and data signals can be routed to any pin, however pins without I2C

compatibility will operate at standard TTL/ST logic levels as selected by the INLVL register. See

the INLVL register for each port to determine which pins are I2C and SMBus compatible.

17.4 PPS Lock

The PPS includes a mode in which all input and output selections can be locked to prevent inadvertent

changes. PPS selections are locked by setting the PPSLOCKED bit of the PPSLOCK register. Setting

and clearing this bit requires a special sequence as an extra precaution against inadvertent changes.

Examples of setting and clearing the PPSLOCKED bit are shown in the following examples.

Example 17-1. PPS Lock Sequence

; Disable interrupts:

BCF INTCON,GIE

; Bank to PPSLOCK register

BANKSEL PPSLOCK

MOVLW 55h

; Required sequence, next 4 instructions

MOVWF PPSLOCK

MOVLW AAh

MOVWF PPSLOCK

; Set PPSLOCKED bit to disable writes

; Only a BSF instruction will work

BSF PPSLOCK,PPSLOCKED

; Enable Interrupts

BSF INTCON,GIE

Example 17-2. PPS Unlock Sequence

; Disable interrupts:

BCF INTCON,GIE

; Bank to PPSLOCK register

BANKSEL PPSLOCK

MOVLW 55h

; Required sequence, next 4 instructions

MOVWF PPSLOCK

MOVLW AAh

PIC18F26/45/46Q10

(PPS) Peripheral Pin Select Module

MOVWF PPSLOCK

; Clear PPSLOCKED bit to enable writes

; Only a BCF instruction will work

BCF PPSLOCK,PPSLOCKED

; Enable Interrupts

BSF INTCON,GIE

17.5 PPS One-Way Lock

Using the PPS1WAY Configuration bit, the PPS settings can be locked in. When this bit is set, the

PPSLOCKED bit can only be cleared and set one time after a device Reset. This allows for clearing the

PPSLOCKED bit so that the input and output selections can be made during initialization. When the

PPSLOCKED bit is set after all selections have been made, it will remain set and cannot be cleared until

after the next device Reset event.

17.6 Operation During Sleep

PPS input and output selections are unaffected by Sleep.

17.7 Effects of a Reset

A device Power-on-Reset (POR) clears all PPS input and output selections to their default values. All

other Resets leave the selections unchanged. Default input selections are shown in the input selection

register table. The PPS one-way is also removed.

PIC18F26/45/46Q10

(PPS) Peripheral Pin Select Module

17.8 Register Summary - PPS

Address Name Bit Pos.

0x0E1F CLCIN0PPS 7:0 PORT[1:0] PIN[2:0]

0x0E20 CLCIN1PPS 7:0 PORT[1:0] PIN[2:0]

0x0E21 CLCIN2PPS 7:0 PORT[1:0] PIN[2:0]

0x0E22 CLCIN3PPS 7:0 PORT[1:0] PIN[2:0]

0x0E23 CLCIN4PPS 7:0 PORT[1:0] PIN[2:0]

0x0E24 CLCIN5PPS 7:0 PORT[1:0] PIN[2:0]

0x0E25 CLCIN6PPS 7:0 PORT[1:0] PIN[2:0]

0x0E26 CLCIN7PPS 7:0 PORT[1:0] PIN[2:0]

0x0E27

...

0x0E87

Reserved

0x0E88 RX2PPS 7:0 PORT[1:0] PIN[2:0]

0x0E89 CK2PPS 7:0 PORT[1:0] PIN[2:0]

0x0E8A SSP2CLKPPS 7:0 PORT[1:0] PIN[2:0]

0x0E8B SSP2DATPPS 7:0 PORT[1:0] PIN[2:0]

0x0E8C SSP2SSPPS 7:0 PORT[1:0] PIN[2:0]

0x0E8D

...

0x0E9A

Reserved

0x0E9B PPSLOCK 7:0 PPSLOCKED

0x0E9C INT0PPS 7:0 PORT PIN[2:0]

0x0E9D INT1PPS 7:0 PORT PIN[2:0]

0x0E9E INT2PPS 7:0 PORT PIN[2:0]

0x0E9F T0CKIPPS 7:0 PORT PIN[2:0]

0x0EA0 T1CKIPPS 7:0 PORT[1:0] PIN[2:0]

0x0EA1 T1GPPS 7:0 PORT[1:0] PIN[2:0]

0x0EA2 T3CKIPPS 7:0 PORT[1:0] PIN[2:0]

0x0EA3 T3GPPS 7:0 PORT[1:0] PIN[2:0]

0x0EA4 T5CKIPPS 7:0 PORT[1:0] PIN[2:0]

0x0EA5 T5GPPS 7:0 PORT[1:0] PIN[2:0]

0x0EA6 T2INPPS 7:0 PORT[1:0] PIN[2:0]

0x0EA7 T4INPPS 7:0 PORT[1:0] PIN[2:0]

0x0EA8 T6INPPS 7:0 PORT[1:0] PIN[2:0]

0x0EA9 ADACTPPS 7:0 PORT[1:0] PIN[2:0]

0x0EAA CCP1PPS 7:0 PORT[1:0] PIN[2:0]

0x0EAB CCP2PPS 7:0 PORT[1:0] PIN[2:0]

0x0EAC CWG1PPS 7:0 PORT[1:0] PIN[2:0]

0x0EAD MDCARLPPS 7:0 PORT[1:0] PIN[2:0]

0x0EAE MDCARHPPS 7:0 PORT[1:0] PIN[2:0]

0x0EAF MDSRCPPS 7:0 PORT[1:0] PIN[2:0]

0x0EB0 RX1PPS 7:0 PORT[1:0] PIN[2:0]

0x0EB1 CK1PPS 7:0 PORT[1:0] PIN[2:0]

0x0EB2 SSP1CLKPPS 7:0 PORT[1:0] PIN[2:0]

PIC18F26/45/46Q10

(PPS) Peripheral Pin Select Module

...........continued

Address Name Bit Pos.

0x0EB3 SSP1DATPPS 7:0 PORT[1:0] PIN[2:0]

0x0EB4 SSP1SSPPS 7:0 PORT[1:0] PIN[2:0]

0x0EB5

...

0x0EE1

Reserved

0x0EE2 RA0PPS 7:0 PPS[4:0]

0x0EE3 RA1PPS 7:0 PPS[4:0]

0x0EE4 RA2PPS 7:0 PPS[4:0]

0x0EE5 RA3PPS 7:0 PPS[4:0]

0x0EE6 RA4PPS 7:0 PPS[4:0]

0x0EE7 RA5PPS 7:0 PPS[4:0]

0x0EE8 RA6PPS 7:0 PPS[4:0]

0x0EE9 RA7PPS 7:0 PPS[4:0]

0x0EEA RB0PPS 7:0 PPS[4:0]

0x0EEB RB1PPS 7:0 PPS[4:0]

0x0EEC RB2PPS 7:0 PPS[4:0]

0x0EED RB3PPS 7:0 PPS[4:0]

0x0EEE RB4PPS 7:0 PPS[4:0]

0x0EEF RB5PPS 7:0 PPS[4:0]

0x0EF0 RB6PPS 7:0 PPS[4:0]

0x0EF1 RB7PPS 7:0 PPS[4:0]

0x0EF2 RC0PPS 7:0 PPS[4:0]

0x0EF3 RC1PPS 7:0 PPS[4:0]

0x0EF4 RC2PPS 7:0 PPS[4:0]

0x0EF5 RC3PPS 7:0 PPS[4:0]

0x0EF6 RC4PPS 7:0 PPS[4:0]

0x0EF7 RC5PPS 7:0 PPS[4:0]

0x0EF8 RC6PPS 7:0 PPS[4:0]

0x0EF9 RC7PPS 7:0 PPS[4:0]

0x0EFA RD0PPS 7:0 PPS[4:0]

0x0EFB RD1PPS 7:0 PPS[4:0]

0x0EFC RD2PPS 7:0 PPS[4:0]

0x0EFD RD3PPS 7:0 PPS[4:0]

0x0EFE RD4PPS 7:0 PPS[4:0]

0x0EFF RD5PPS 7:0 PPS[4:0]

0x0F00 RD6PPS 7:0 PPS[4:0]

0x0F01 RD7PPS 7:0 PPS[4:0]

0x0F02 RE0PPS 7:0 PPS[4:0]

0x0F03 RE1PPS 7:0 PPS[4:0]

0x0F04 RE2PPS 7:0 PPS[4:0]

17.9 Register Definitions: PPS Input and Output Selection

PIC18F26/45/46Q10

(PPS) Peripheral Pin Select Module

17.9.1 Peripheral xxx Input Selection

Name: xxxPPS

Important: The Reset value of this register is determined by the device default for each

peripheral.

Refer to the input selection table for a list of available ports and default pin locations.

Bit 7 6 5 4 3 2 1 0

PORT[1:0] PIN[2:0]

Access R/W R/W R/W R/W R/W

Reset g g g g g

Bits 4:3 – PORT[1:0] Peripheral xxx Input PORT Selection bits

See the input selection table for a list of available ports and default pin locations.

Value Description

11 PORTD

10 PORTC

01 PORTB

00 PORTA

Bits 2:0 – PIN[2:0] Peripheral xxx Input Pin Selection bits

Value Description

111 Peripheral input is from PORTx Pin 7 (Rx7)

110 Peripheral input is from PORTx Pin 6 (Rx6)

101 Peripheral input is from PORTx Pin 5 (Rx5)

100 Peripheral input is from PORTx Pin 4 (Rx4)

011 Peripheral input is from PORTx Pin 3 (Rx3)

010 Peripheral input is from PORTx Pin 2 (Rx2)

001 Peripheral input is from PORTx Pin 1 (Rx1)

000 Peripheral input is from PORTx Pin 0 (Rx0)

PIC18F26/45/46Q10

(PPS) Peripheral Pin Select Module

17.9.2 Pin Rxy Output Source Selection Register

Name: RxyPPS

Important: See 17.8 Register Summary - PPS for the address offset of each individual

register.

Bit 7 6 5 4 3 2 1 0

RxyPPS[4:0]

Access R/W R/W R/W R/W R/W

Reset 0 0 0 0 0

Bits 4:0 – RxyPPS[4:0] Pin Rxy Output Source Selection bits

See output source selection table for source codes.

PIC18F26/45/46Q10

(PPS) Peripheral Pin Select Module

17.9.3 PPS Lock Register

Name: PPSLOCK

Address: 0xE9B

Bit 7 6 5 4 3 2 1 0

PPSLOCKED

Access R/W

Reset 0

Bit 0 – PPSLOCKED PPS Locked bit

Value Description

1PPS is locked. PPS selections can not be changed.

0PPS is not locked. PPS selections can be changed.

PIC18F26/45/46Q10

(PPS) Peripheral Pin Select Module

18. Timer0 Module

Timer0 module has the following features:

• 8-Bit B\Timer with Programmable Period

• 16-Bit Timer

• Selectable Clock Sources

• Synchronous and Asynchronous Operation

• Programmable Prescaler and Postscaler

• Interrupt on Match or Overflow

• Output on I/O Pin (via PPS) or to Other Peripherals

• Operation During Sleep

Figure 18-1. Timer0 Block Diagram

Rev. 10-000017I

2/8/2018

T0CKIPPS

See T0CON1

Register

T0CS

T0CKPS

Prescaler

FOSC/4

T0ASYNCT016BIT

T0OUTPS T0IF

T0_out

Peripherals

TMR0

1

0Postscaler

TMR0L

COMPARATOR

TMR0 High

Byte

TMR0H

T0_match

Clear

Latch

Enable

8-bit TMR0 Body Diagram (T016BIT = 0)

TMR0L

TMR0H

Internal Data Bus

16-bit TMR0 Body Diagram (T016BIT = 1)

SYNC IN OUT

TMR0

body

Q

D

CK

PPS

RxyPPS

R

IN

OUT

TMR0 High

Byte

IN OUT

Read TMR0L

Write TMR0L

8

PPS

PIC18F26/45/46Q10

Timer0 Module

18.1 Timer0 Operation

Timer0 can operate as either an 8-bit or 16-bit timer. The mode is selected with the T016BIT bit.

18.1.1 8-bit Mode

In this mode Timer0 increments on the rising edge of the selected clock source. A prescaler on the clock

input gives several prescale options (see prescaler control bits, T0CKPS).

In this mode as shown in Figure 18-1, a buffered version of TMR0H is maintained. This is compared with

the value of TMR0L on each cycle of the selected clock source. When the two values match, the following

events occur:

• TMR0L is reset

• The contents of TMR0H are copied to the TMR0H buffer for next comparison

18.1.2 16-Bit Mode

In this mode Timer0 increments on the rising edge of the selected clock source. A prescaler on the clock

input gives several prescale options (see prescaler control bits, T0CKPS).

In this mode TMR0H:TMR0L form the 16-bit timer value. As shown in Figure 18-1, read and write of the

TMR0H register are buffered. TMR0H register is updated with the contents of the high byte of Timer0

during a read of TMR0L register. Similarly, a write to the high byte of Timer0 takes place through the

TMR0H buffer register. The high byte is updated with the contents of TMR0H register when a write occurs

to TMR0L register. This allows all 16 bits of Timer0 to be read and written at the same time.

Timer0 rolls over to 0x0000 on incrementing past 0xFFFF. This makes the timer free-running. TMR0L/H

registers cannot be reloaded in this mode once started.

18.2 Clock Selection

Timer0 has several options for clock source selections, option to operate synchronously/asynchronously

and a programmable prescaler.

18.2.1 Clock Source Selection

The T0CS bits are used to select the clock source for Timer0. The possible clock sources are listed in the

table below.

Table 18-1. Timer 0 Clock Source Selections

T0CS Clock Source

111 CLC1_out

110 MFINTOSC (500 kHz)

101 SOSC

100 LFINTOSC

011 HFINTOSC

010 FOSC/4

001 Pin selected by T0CKIPPS (Inverted)

000 Pin selected by T0CKIPPS (Non-inverted)

PIC18F26/45/46Q10

Timer0 Module

18.2.2 Synchronous Mode

When the T0ASYNC bit is clear, Timer0 clock is synchronized to the system clock (FOSC/4). When

operating in Synchronous mode, Timer0 clock frequency cannot exceed FOSC/4. During Sleep mode

system clock is not available and Timer0 cannot operate.

18.2.3 Asynchronous Mode

When the T0ASYNC bit is set, Timer0 increments with each rising edge of the input source (or output of

the prescaler, if used). Asynchronous mode allows Timer0 to continue operation during Sleep mode

provided the selected clock source is available.

18.2.4 Programmable Prescaler

Timer0 has 16 programmable input prescaler options ranging from 1:1 to 1:32768. The prescaler values

are selected using the T0CKPS bits.

The prescaler counter is not directly readable or writable. The prescaler counter is cleared on the

following events:

• A write to the TMR0L register

• A write to either the T0CON0 or T0CON1 registers

• Any device Reset

Related Links

8. Resets

18.3 Timer0 Output and Interrupt

18.3.1 Programmable Postscaler

Timer0 has 16 programmable output postscaler options ranging from 1:1 to 1:16. The postscaler values

are selected using the T0OUTPS bits. The postscaler divides the output of Timer0 by the selected ratio.

The postscaler counter is not directly readable or writable. The postscaler counter is cleared on the

following events:

• A write to the TMR0L register

• A write to either the T0CON0 or T0CON1 registers

• Any device Reset

18.3.2 Timer0 Output

TMR0_out is the output of the postscaler. TMR0_out toggles on every match between TMR0L and

TMR0H in 8-bit mode, or when TMR0H:TMR0L rolls over in 16-bit mode. If the output postscaler is used,

the output is scaled by the ratio selected.

The Timer0 output can be routed to an I/O pin via the RxyPPS output selection register. The Timer0

output can be monitored through software via the T0OUT output bit.

Related Links

17.2 PPS Outputs

18.3.3 Timer0 Interrupt

The Timer0 Interrupt Flag bit (TMR0IF) is set when the TMR0_out toggles. If the Timer0 interrupt is

enabled (TMR0IE), the CPU will be interrupted when the TMR0IF bit is set.

PIC18F26/45/46Q10

Timer0 Module

When the postscaler bits (T0OUTPS) are set to 1:1 operation (no division), the T0IF flag bit will be set

with every TMR0 match or rollover. In general, the TMR0IF flag bit will be set every T0OUTPS +1

matches or rollovers.

18.3.4 Timer0 Example

Timer0 Configuration:

• Timer0 mode = 16-bit

• Clock Source = FOSC/4 (250 kHz)

• Synchronous operation

• Prescaler = 1:1

• Postscaler = 1:2 (T0OUTPS = 1)

In this case the TMR0_out toggles every two rollovers of TMR0H:TMR0L. i.e.,

(0xFFFF)*2*(1/250kHz) = 524.28 ms

18.4 Operation During Sleep

When operating synchronously, Timer0 will halt when the device enters Sleep mode.

When operating asynchronously and selected clock source is active, Timer0 will continue to increment

and wake the device from Sleep mode if Timer0 interrupt is enabled.

PIC18F26/45/46Q10

Timer0 Module

18.5 Register Summary - Timer0

Address Name Bit Pos.

0x0FD2 TMR0L 7:0 TMR0L[7:0]

0x0FD3 TMR0H 7:0 TMR0H[7:0]

0x0FD4 T0CON0 7:0 T0EN T0OUT T016BIT T0OUTPS[3:0]

0x0FD5 T0CON1 7:0 T0CS[2:0] T0ASYNC T0CKPS[3:0]

18.6 Register Definitions: Timer0 Control

PIC18F26/45/46Q10

Timer0 Module

18.6.1 T0CON0

Name: T0CON0

Address: 0xFD4

Timer0 Control Register 0

Bit 7 6 5 4 3 2 1 0

T0EN T0OUT T016BIT T0OUTPS[3:0]

Access R/W R R/W R/W R/W R/W R/W

Reset 0 0 0 0 0 0 0

Bit 7 – T0EN TMR0 Enable

Value Description

1The module is enabled and operating

0The module is disabled

Bit 5 – T0OUT TMR0 Output

Bit 4 – T016BIT TMR0 Operating as 16-Bit Timer Select

Value Description

1TMR0 is a 16-bit timer

0TMR0 is an 8-bit timer

Bits 3:0 – T0OUTPS[3:0] TMR0 Output Postscaler (Divider) Select

Value Description

1111 1:16 Postscaler

1110 1:15 Postscaler

1101 1:14 Postscaler

1100 1:13 Postscaler

1011 1:12 Postscaler

1010 1:11 Postscaler

1001 1:10 Postscaler

1000 1:9 Postscaler

0111 1:8 Postscaler

0110 1:7 Postscaler

0101 1:6 Postscaler

0100 1:5 Postscaler

0011 1:4 Postscaler

0010 1:3 Postscaler

0001 1:2 Postscaler

0000 1:1 Postscaler

PIC18F26/45/46Q10

Timer0 Module

18.6.2 T0CON1

Name: T0CON1

Address: 0xFD5

Timer0 Control Register 1

Bit 7 6 5 4 3 2 1 0

T0CS[2:0] T0ASYNC T0CKPS[3:0]

Access R/W R/W R/W R/W R/W R/W R/W R/W

Reset 0 0 0 0 0 0 0 0

Bits 7:5 – T0CS[2:0] Timer0 Clock Source Select

Refer the clock source selection table

Bit 4 – T0ASYNC TMR0 Input Asynchronization Enable

Value Description

1The input to the TMR0 counter is not synchronized to system clocks

0The input to the TMR0 counter is synchronized to FOSC/4

Bits 3:0 – T0CKPS[3:0] Prescaler Rate Select

Value Description

1111 1:32768

1110 1:16384

1101 1:8192

1100 1:4096

1011 1:2048

1010 1:1024

1001 1:512

1000 1:256

0111 1:128

0110 1:64

0101 1:32

0100 1:16

0011 1:8

0010 1:4

0001 1:2

0000 1:1

PIC18F26/45/46Q10

Timer0 Module

18.6.3 TMR0H

Name: TMR0H

Address: 0xFD3

Timer0 Period/Count High Register

Bit 7 6 5 4 3 2 1 0

TMR0H[7:0]

Access R/W R/W R/W R/W R/W R/W R/W R/W

Reset 0 0 0 0 0 0 0 0

Bits 7:0 – TMR0H[7:0] TMR0 Most Significant Counter

Value Condition Description

0 to

255

T016BIT = 08-bit Timer0 Period Value. TMR0L continues counting from 0 when this value

is reached.

0 to

255

T016BIT = 116-bit Timer0 Most Significant Byte

PIC18F26/45/46Q10

Timer0 Module

18.6.4 TMR0L

Name: TMR0L

Address: 0xFD2

Timer0 Period/Count Low Register

Bit 7 6 5 4 3 2 1 0

TMR0L[7:0]

Access R/W R/W R/W R/W R/W R/W R/W R/W

Reset 0 0 0 0 0 0 0 0

Bits 7:0 – TMR0L[7:0] TMR0 Least Significant Counter

Value Condition Description

0 to

255

T016BIT = 08-bit Timer0 Counter bits

0 to

255

T016BIT = 116-bit Timer0 Least Significant Byte

PIC18F26/45/46Q10

Timer0 Module

19. Timer1 Module with Gate Control

Timer1 module is a 16-bit timer/counter with the following features:

• 16-Bit Timer/Counter Register Pair (TMRxH:TMRxL)

• Programmable Internal or External Clock Source

• 2-Bit Prescaler

• Optionally Synchronized Comparator Out

• Multiple Timer1 Gate (count enable) Sources

• Interrupt-on-Overflow

• Wake-Up on Overflow (external clock, Asynchronous mode only)

• 16-Bit Read/Write Operation

• Time Base for the Capture/Compare Function with the CCP modules

• Special Event Trigger (with CCP)

• Selectable Gate Source Polarity

• Gate Toggle mode

• Gate Single Pulse mode

• Gate Value Status

• Gate Event Interrupt

Important: References to module Timer1 apply to all the odd numbered timers on this device.

PIC18F26/45/46Q10

Timer1 Module with Gate Control

Figure 19-1. Timer1 Block Diagram

Rev. 10-000018L

6/26/2017

TxGPPS

GSS<4:0>

GPOL

0

1

Single Pulse

Acq. Control

1

0

GSPM

ON

GTM

GE

ON

DQ

EN

TMRxLTMRxH

Tx_overflow

set flag bit

TMRxIF

TMRx(2)

1

0

CS<4:0>

Prescaler

1,2,4,8

SYNC

Sleep

Input

Fosc/2

Internal

Clock

CKPS<1:0>

Synchronized Clock Input

2

det

Synchronize(3)

(1)

D

QCK

R

Q

GGO/DONE

TxCLK

D Q

set bit

TMRxGIF

GVAL

Q1

det

Interrupt

NOTE (5)

Note (4)

To Comparators (6)

00000

5

11111

PPS

TxCKIPPS

PPS

Note:

1. This signal comes from the pin seleted by TxCKIPPS.

2. TMRx register increments on rising edge.

3. Synchronize does not operate while in Sleep.

4. See TMRxCLK for clock source selections.

5. See TMRxGATE for gate source selection.

6. Synchronized comparator output should not be used in conjunction with synchronized input clock.

19.1 Timer1 Operation

The Timer1 module is a 16-bit incrementing counter that is accessed through the TMRxH:TMRxL register

pair. Writes to TMRxH or TMRxL directly update the counter.

When used with an internal clock source, the module is a timer and increments on every instruction cycle.

When used with an external clock source, the module can be used as either a timer or counter and

increments on every selected edge of the external source.

PIC18F26/45/46Q10

Timer1 Module with Gate Control

Timer1 is enabled by configuring the ON and GE bits in the TxCON and TxGCON registers, respectively.

The table below displays the Timer1 enable selections.

Table 19-1. Timer1 Enable Selections

ON GE Timer1 Operation

1 1 Count Enabled

1 0 Always On

0 1 Off

0 0 Off

19.2 Clock Source Selection

The CS bits select the clock source for Timer1. These bits allow the selection of several possible

synchronous and asynchronous clock sources. The table below lists the clock source selections.

Table 19-2. Timer Clock Sources

CS

Clock Source

Timer1 Timer3 Timer5

11000-11111 Reserved Reserved Reserved

10111 CLC8_out CLC8_out CLC8_out

10110 CLC7_out CLC7_out CLC7_out

10101 CLC6_out CLC6_out CLC6_out

10100 CLC5_out CLC5_out CLC5_out

10011 CLC4_out CLC4_out CLC4_out

10010 CLC3_out CLC3_out CLC3_out

10001 CLC2_out CLC2_out CLC2_out

10000 CLC1_out CLC1_out CLC1_out

01111-01100 Reserved Reserved Reserved

01011 TMR5 overflow TMR5 overflow Reserved

01010 TMR3 overflow Reserved TMR3 overflow

01001 Reserved TMR1 overflow TMR1 overflow

01000 TMR0 overflow TMR0 overflow TMR0 overflow

00111 CLKREF CLKREF CLKREF

00110 SOSC SOSC SOSC

00101 MFINTOSC (500 kHz) MFINTOSC (500 kHz) MFINTOSC (500 kHz)

00100 LFINTOSC LFINTOSC LFINTOSC

00011 HFINTOSC HFINTOSC HFINTOSC

PIC18F26/45/46Q10

Timer1 Module with Gate Control

...........continued

CS

Clock Source

Timer1 Timer3 Timer5

00010 FOSC FOSC FOSC

00001 FOSC/4 FOSC/4 FOSC/4

00000 T1CKIPPS T3CKIPPS T5CKIPPS

19.2.1 Internal Clock Source

When the internal clock source is selected the TMRxH:TMRxL register pair will increment on multiples of

FOSC as determined by the Timer1 prescaler.

When the FOSC internal clock source is selected, the Timer1 register value will increment by four counts

every instruction clock cycle. Due to this condition, a 2 LSB error in resolution will occur when reading the

Timer1 value. To utilize the full resolution of Timer1, an asynchronous input signal must be used to gate

the Timer1 clock input.

Important: In Counter mode, a falling edge must be registered by the counter prior to the first

incrementing rising edge after any one or more of the following conditions:

• Timer1 enabled after POR

• Write to TMRxH or TMRxL

• Timer1 is disabled

• Timer1 is disabled (TMRxON = 0) when TxCKI is high then Timer1 is enabled (TMRxON =

1) when TxCKI is low. Refer to the figure below.

Figure 19-2. Timer1 Incrementing Edge

TxCKI = 1

when TMRx

Enabled

TxCKI = 0

when TMRx

Enabled

Rev. 30-000136A

5/24/2017

Note:

1. Arrows indicate counter increments.

2. In Counter mode, a falling edge must be registered by the counter prior to the first incrementing

rising edge of the clock.

19.2.2 External Clock Source

When the external clock source is selected, the Timer1 module may work as a timer or a counter.

When enabled to count, Timer1 is incremented on the rising edge of the external clock input of the

TxCKIPPS pin. This external clock source can be synchronized to the system clock or it can run

asynchronously.

PIC18F26/45/46Q10

Timer1 Module with Gate Control

19.3 Timer1 Prescaler

Timer1 has four prescaler options allowing 1, 2, 4 or 8 divisions of the clock input. The CKPS bits control

the prescale counter. The prescale counter is not directly readable or writable; however, the prescaler

counter is cleared upon a write to TMRxH or TMRxL.

19.4 Secondary Oscillator

A secondary low-power 32.768 kHz oscillator circuit is built-in between pins SOSCI (input) and SOSCO

(amplifier output). This internal circuit is to be used in conjunction with an external 32.768 kHz crystal.

The secondary oscillator is not dedicated only to Timer1; it can also be used by other modules.

The oscillator circuit is enabled by setting the SOSCEN bit of the OSCEN register. This can be used as

one of the Timer1 clock sources selected with the CS bits. The oscillator will continue to run during Sleep.

Important: The oscillator requires a start-up and stabilization time before use. Thus, the

SOSCEN bit of the OSCEN register should be set and a suitable delay observed prior to

enabling Timer1. A software check can be performed to confirm if the secondary oscillator is

enabled and ready to use. This is done by polling the SOR bit of the OSCSTAT.

Related Links

4.2.1.5 Secondary Oscillator

19.5 Timer1 Operation in Asynchronous Counter Mode

When the SYNC control bit is set, the external clock input is not synchronized. The timer increments

asynchronously to the internal phase clocks. If external clock source is selected then the timer will

continue to run during Sleep and can generate an interrupt on overflow, which will wake-up the processor.

However, special precautions in software are needed to read/write the timer (see 19.5.1 Reading and

Writing Timer1 in Asynchronous Counter Mode).

Important: When switching from synchronous to asynchronous operation, it is possible to skip

an increment. When switching from asynchronous to synchronous operation, it is possible to

produce an additional increment.

19.5.1 Reading and Writing Timer1 in Asynchronous Counter Mode

Reading TMRxH or TMRxL while the timer is running from an external asynchronous clock will ensure a

valid read (taken care of in hardware). However, the user should keep in mind that reading the 16-bit

timer in two 8-bit values itself, poses certain problems, since the timer may overflow between the reads.

For writes, it is recommended that the user simply stop the timer and write the desired values. A write

contention may occur by writing to the timer registers, while the register is incrementing. This may

produce an unpredictable value in the TMRxH:TMRxL register pair.

19.6 Timer1 16-Bit Read/Write Mode

Timer1 can be configured to read and write all 16 bits of data, to and from, the 8-bit TMRxL and TMRxH

registers, simultaneously. The 16-bit read and write operations are enabled by setting the RD16 bit.

PIC18F26/45/46Q10

Timer1 Module with Gate Control

To accomplish this function, the TMRxH register value is mapped to a buffer register called the TMRxH

buffer register. While in 16-Bit mode, the TMRxH register is not directly readable or writable and all read

and write operations take place through the use of this TMRxH buffer register.

When a read from the TMRxL register is requested, the value of the TMRxH register is simultaneously

loaded into the TMRxH buffer register. When a read from the TMRxH register is requested, the value is

provided from the TMRxH buffer register instead. This provides the user with the ability to accurately read

all 16 bits of the Timer1 value from a single instance in time. Refer the figure below for more details.

In contrast, when not in 16-Bit mode, the user must read each register separately and determine if the

values have become invalid due to a rollover that may have occurred between the read operations.

When a write request of the TMRxL register is requested, the TMRxH buffer register is simultaneously

updated with the contents of the TMRxH register. The value of TMRxH must be preloaded into the

TMRxH buffer register prior to the write request for the TMRxL register. This provides the user with the

ability to write all 16 bits to the TMRxL:TMRxH register pair at the same time.

Any requests to write to the TMRxH directly does not clear the Timer1 prescaler value. The prescaler

value is only cleared through write requests to the TMRxL register.

Figure 19-3. Timer1 16-Bit Read/Write Mode Block Diagram

TMR1L

Internal Data Bus

8

Set

TMR1IF

on Overflow

TMR1

TMR1H

High Byte

88

8

Read TMR1L

Write TMR1L

8

From

Timer1

Circuitry

Rev. 30-000135A

5/24/2017

19.7 Timer1 Gate

Timer1 can be configured to count freely or the count can be enabled and disabled using Timer1 gate

circuitry. This is also referred to as Timer1 gate enable.

Timer1 gate can also be driven by multiple selectable sources.

19.7.1 Timer1 Gate Enable

The Timer1 Gate Enable mode is enabled by setting the GE bit. The polarity of the Timer1 Gate Enable

mode is configured using the GPOL bit.

When Timer1 Gate Enable mode is enabled, Timer1 will increment on the rising edge of the Timer1 clock

source. When Timer1 Gate signal is inactive, the timer will not increment and hold the current count.

Enable mode is disabled, no incrementing will occur and Timer1 will hold the current count. See figure

below for timing details.

PIC18F26/45/46Q10

Timer1 Module with Gate Control

Table 19-3. Timer1 Gate Enable Selections

TMRxCLK GPOL TxG Timer1 Operation

↑1 1 Counts

↑1 0 Holds Count

↑0 1 Holds Count

↑0 0 Counts

Figure 19-4. Timer1 Gate Enable Mode

TMRxGE

TxGPOL

TxG_IN

TxCKI

TxGVAL

N N + 1 N + 2 N + 3 N + 4

Timer1/3/5/7

Rev. 30-000137A

5/24/2017

19.7.2 Timer1 Gate Source Selection

The gate source for Timer1 is selected using the GSS bits. The polarity selection for the gate source is

controlled by the GPOL bit. The table below lists the gate source selections.

Table 19-4. Timer Gate Sources

GSS

Gate Source

Timer1 Timer3 Timer5

11000-11111 Reserved Reserved Reserved

10111 CLC8_out CLC8_out CLC8_out

10110 CLC7_out CLC7_out CLC7_out

10101 CLC6_out CLC6_out CLC6_out

10100 CLC5_out CLC5_out CLC5_out

10011 CLC4_out CLC4_out CLC4_out

10010 CLC3_out CLC3_out CLC3_out

PIC18F26/45/46Q10

Timer1 Module with Gate Control

...........continued

GSS

Gate Source

Timer1 Timer3 Timer5

10001 CLC2_out CLC2_out CLC2_out

10000 CLC1_out CLC1_out CLC1_out

01111 Reserved Reserved Reserved

01110 ZCDOUT ZCDOUT ZCDOUT

01101 CMP2OUT CMP2OUT CMP2OUT

01100 CMP1OUT CMP1OUT CMP1OUT

01011 PWM4OUT PWM4OUT PWM4OUT

01010 PWM3OUT PWM3OUT PWM3OUT

01001 CCP2OUT CCP2OUT CCP2OUT

01000 CCP1OUT CCP1OUT CCP1OUT

00111 TMR6OUT (post-scaled) TMR6OUT (post-scaled) TMR6OUT (post-scaled)

00110 TMR5 overflow TMR5 overflow Reserved

00101 TMR4OUT (post-scaled) TMR4OUT (post-scaled) TMR4OUT (post-scaled)

00100 TMR3 overflow Reserved TMR3 overflow

00011 TMR2OUT (post-scaled) TMR2OUT (post-scaled) TMR2OUT (post-scaled)

00010 Reserved TMR1 overflow TMR1 overflow

00001 TMR0 overflow TMR0 overflow TMR0 overflow

00000 Pin selected by T1GPPS Pin selected by T3GPPS Pin selected by T5GPPS

Any of the above mentioned signals can be used to trigger the gate. The output of the CMPx can be

synchronized to the Timer1 clock or left asynchronous. For more information refer to the Comparator

Output Synchronization section.

Related Links

33.4.1 Comparator Output Synchronization

19.7.3 Timer1 Gate Toggle Mode

When Timer1 Gate Toggle mode is enabled, it is possible to measure the full-cycle length of a Timer1

gate signal, as opposed to the duration of a single level pulse.

The Timer1 gate source is routed through a flip-flop that changes state on every incrementing edge of the

signal. See figure below for timing details.

Timer1 Gate Toggle mode is enabled by setting the GTM bit. When the GTM bit is cleared, the flip-flop is

cleared and held clear. This is necessary in order to control which edge is measured.

PIC18F26/45/46Q10

Timer1 Module with Gate Control

Important: Enabling Toggle mode at the same time as changing the gate polarity may result in

indeterminate operation.

Figure 19-5. TIMER1 GATE TOGGLE MODE

TMRxGE

TxGPOL

TxGTM

TxTxG_IN

TxCKI

TxGVAL

N N + 1 N + 2 N + 3 N + 4 N + 5 N + 6 N + 7 N + 8

TIMER1/3/5/7

Rev. 30-000138A

5/25/2017

19.7.4 Timer1 Gate Single Pulse Mode

When Timer1 Gate Single Pulse mode is enabled, it is possible to capture a single pulse gate event.

Timer1 Gate Single Pulse mode is first enabled by setting the GSPM bit. Next, the GGO/DONE must be

set. The Timer1 will be fully enabled on the next incrementing edge. On the next trailing edge of the

pulse, the GGO/DONE bit will automatically be cleared. No other gate events will be allowed to increment

Timer1 until the GGO/DONE bit is once again set in software.

Clearing the GSPM bit will also clear the GGO/DONE bit. See figure below for timing details.

Enabling the Toggle mode and the Single Pulse mode simultaneously will permit both sections to work

together. This allows the cycle times on the Timer1 gate source to be measured. See figure below for

timing details.

PIC18F26/45/46Q10

Timer1 Module with Gate Control

Figure 19-6. TIMER1 GATE SINGLE PULSE MODE

TMRxGE

TxGPOL

TxG_IN

TxCKI

TxGVAL

N N + 1 N + 2

TxGSPM

TxGGO/

DONE

Set by software

Cleared by hardware on

falling edge of TxGVAL

Set by hardware on

falling edge of TxGVAL

Cleared by software

Cleared by

software

TMRxGIF

Counting enabled on

rising edge of TxG

TIMER1/3/5/7

Rev. 30-000139A

5/25/2017

PIC18F26/45/46Q10

Timer1 Module with Gate Control

Figure 19-7. TIMER1 GATE SINGLE PULSE AND TOGGLE COMBINED MODE

TMRxGE

TxGPOL

TxG_IN

TxCKI

TxGVAL

N N + 1 N + 2

TxGSPM

TxGGO/

DONE

Set by software

Cleared by hardware on

falling edge of TxGVAL

Set by hardware on

falling edge of TxGVAL

Cleared by software

Cleared by

software

TMRxGIF

TxGTM

Counting enabled on

rising edge of TxG

N + 4

N + 3

TIMER1/3/5/7

Rev. 30-000140A

5/25/2017

19.7.5 Timer1 Gate Value Status

When Timer1 Gate Value Status is utilized, it is possible to read the most current level of the gate control

value. The value is stored in the GVAL bit in the TxGCON register. The GVAL bit is valid even when the

Timer1 gate is not enabled (GE bit is cleared).

19.7.6 Timer1 Gate Event Interrupt

When Timer1 gate event interrupt is enabled, it is possible to generate an interrupt upon the completion

of a gate event. When the falling edge of GVAL occurs, the TMRxGIF flag bit in the PIR5 register will be

set. If the TMRxGIE bit in the PIE5 register is set, then an interrupt will be recognized.

The TMRxGIF flag bit operates even when the Timer1 gate is not enabled (GE bit is cleared).

For more information on selecting high or low priority status for the Timer1 gate event interrupt see the

Interrupts chapter.

Related Links

14.2 Interrupt Priority

PIC18F26/45/46Q10

Timer1 Module with Gate Control

19.8 Timer1 Interrupt

The Timer1 register pair (TMRxH:TMRxL) increments to FFFFh and rolls over to 0000h. When Timer1

rolls over, the Timer1 interrupt flag bit of the PIRx register is set. To enable the interrupt-on-rollover, the

following bits must be set:

• TMRxON bit of the TxCON register

• TMRxIE bits of the PIEx register

• PEIE/GIEL bit of the INTCON register

• GIE/GIEH bit of the INTCON register

The interrupt is cleared by clearing the TMRxIF bit in the Interrupt Service Routine.

For more information on selecting high or low priority status for the Timer1 overflow interrupt, see the

Interrupts chapter.

Important: The TMRxH:TMRxL register pair and the TMRxIF bit should be cleared before

enabling interrupts.

Related Links

14.2 Interrupt Priority

19.9 Timer1 Operation During Sleep

Timer1 can only operate during Sleep when set up in Asynchronous Counter mode. In this mode, an

external crystal or clock source can be used to increment the counter. To set up the timer to wake the

device:

• TMRxON bit of the TxCON register must be set

• TMRxIE bit of the PIEx register must be set

• PEIE/GIEL bit of the INTCON register must be set

• TxSYNC bit of the TxCON register must be set

• Configure the TMRxCLK register for using secondary oscillator as the clock source

• Enable the SOSCEN bit of the OSCEN register

The device will wake-up on an overflow and execute the next instruction. If the GIE/GIEH bit of the

INTCON register is set, the device will call the Interrupt Service Routine.

The secondary oscillator will continue to operate in Sleep regardless of the TxSYNC bit setting.

19.10 CCP Capture/Compare Time Base

The CCP modules use the TMRxH:TMRxL register pair as the time base when operating in Capture or

Compare mode.

In Capture mode, the value in the TMRxH:TMRxL register pair is copied into the CCPRxH:CCPRxL

register pair on a configured event.

In Compare mode, an event is triggered when the value in the CCPRxH:CCPRxL register pair matches

the value in the TMRxH:TMRxL register pair. This event can be a Special Event Trigger.

PIC18F26/45/46Q10

Timer1 Module with Gate Control

For more information, see Capture/Compare/PWM Module(CCP) chapter.

Related Links

21. Capture/Compare/PWM Module

19.11 CCP Special Event Trigger

When any of the CCPs are configured to trigger a special event, the trigger will clear the TMRxH:TMRxL

register pair. This special event does not cause a Timer1 interrupt. The CCP module may still be

configured to generate a CCP interrupt.

In this mode of operation, the CCPRxH:CCPRxL register pair becomes the period register for Timer1.

Timer1 should be synchronized and FOSC/4 should be selected as the clock source in order to utilize the

Special Event Trigger. Asynchronous operation of Timer1 can cause a Special Event Trigger to be

missed.

In the event that a write to TMRxH or TMRxL coincides with a Special Event Trigger from the CCP, the

write will take precedence.

19.12 Peripheral Module Disable

When a peripheral is not used or inactive, the module can be disabled by setting the Module Disable bit in

the PMD registers. This will reduce power consumption to an absolute minimum. Setting the PMD bits

holds the module in Reset and disconnects the module’s clock source. The Module Disable bits for

Timer1 (TMR1MD) are in the PMD1 register. See Peripheral Module Disable (PMD) chapter for more

information.

Related Links

7.3 Register Summary - PMD

PIC18F26/45/46Q10

Timer1 Module with Gate Control

19.13 Register Summary - Timer1

Address Name Bit Pos.

0x0FC0 TMR5

7:0 TMRxL[7:0]

15:8 TMRxH[7:0]

0x0FC2 T5CON 7:0 CKPS[1:0] SYNC RD16 ON

0x0FC3 T5GCON 7:0 GE GPOL GTM GSPM GGO/DONE GVAL

0x0FC4 TMR5GATE 7:0 GSS[4:0]

0x0FC5 TMR5CLK 7:0 CS[4:0]

0x0FC6 TMR3

7:0 TMRxL[7:0]

15:8 TMRxH[7:0]

0x0FC8 T3CON 7:0 CKPS[1:0] SYNC RD16 ON

0x0FC9 T3GCON 7:0 GE GPOL GTM GSPM GGO/DONE GVAL

0x0FCA TMR3GATE 7:0 GSS[4:0]

0x0FCB TMR3CLK 7:0 CS[4:0]

0x0FCC TMR1

7:0 TMRxL[7:0]

15:8 TMRxH[7:0]

0x0FCE T1CON 7:0 CKPS[1:0] SYNC RD16 ON

0x0FCF T1GCON 7:0 GE GPOL GTM GSPM GGO/DONE GVAL

0x0FD0 TMR1GATE 7:0 GSS[4:0]

0x0FD1 TMR1CLK 7:0 CS[4:0]

19.14 Register Definitions: Timer1

Long bit name prefixes for the odd numbered timers is shown in the following table. Refer to the "Long Bit

Names" section for more information.

Table 19-5. Timer1 prefixes

Peripheral Bit Name Prefix

Timer1 T1

Timer3 T3

Timer5 T5

Related Links

1.4.2.2 Long Bit Names

PIC18F26/45/46Q10

Timer1 Module with Gate Control

19.14.1 TxCON

Name: TxCON

Address: 0xFCE,0xFC8,0xFC2

Timer Control Register

Bit 7 6 5 4 3 2 1 0

CKPS[1:0] SYNC RD16 ON

Access R/W R/W R/W R/W R/W

Reset 0 0 0 0 0

Bits 5:4 – CKPS[1:0] Timer Input Clock Prescale Select bits

Reset States: POR/BOR = 00

All Other Resets = uu

Value Description

11 1:8 Prescale value

10 1:4 Prescale value

01 1:2 Prescale value

00 1:1 Prescale value

Bit 2 – SYNC Timer External Clock Input Synchronization Control bit

Reset States: POR/BOR = 0

All Other Resets = u

Value Condition Description

XCS = FOSC/4 or FOSC This bit is ignored. Timer uses the incoming clock as is.

1Else Do not synchronize external clock input

0Else Synchronize external clock input with system clock

Bit 1 – RD16 16-Bit Read/Write Mode Enable bit

Reset States: POR/BOR = 0

All Other Resets = u

Value Description

1Enables register read/write of Timer in one 16-bit operation

0Enables register read/write of Timer in two 8-bit operations

Bit 0 – ON Timer On bit

Reset States: POR/BOR = 0

All Other Resets = u

Value Description

1Enables Timer

0Disables Timer

PIC18F26/45/46Q10

Timer1 Module with Gate Control

19.14.2 TxGCON

Name: TxGCON

Address: 0xFCF,0xFC9,0xFC3

Timer Gate Control Register

Bit 7 6 5 4 3 2 1 0

GE GPOL GTM GSPM GGO/DONE GVAL

Access R/W R/W R/W R/W R/W RO

Reset 0 0 0 0 0 x

Bit 7 – GE Timer Gate Enable bit

Reset States: POR/BOR = 0

All Other Resets = u

Value Condition Description

1ON = 1Timer counting is controlled by the Timer gate function

0ON = 1Timer is always counting

XON = 0This bit is ignored

Bit 6 – GPOL Timer Gate Polarity bit

Reset States: POR/BOR = 0

All Other Resets = u

Value Description

1Timer gate is active-high (Timer counts when gate is high)

0Timer gate is active-low (Timer counts when gate is low)

Bit 5 – GTM Timer Gate Toggle Mode bit

Timer Gate Flip-Flop Toggles on every rising edge when Toggle mode is enabled.

Reset States: POR/BOR = 0

All Other Resets = u

Value Description

1Timer Gate Toggle mode is enabled

0Timer Gate Toggle mode is disabled and Toggle flip-flop is cleared

Bit 4 – GSPM Timer Gate Single Pulse Mode bit

Reset States: POR/BOR = 0

All Other Resets = u

Value Description

1Timer Gate Single Pulse mode is enabled and is controlling Timer gate)

0Timer Gate Single Pulse mode is disabled

Bit 3 – GGO/DONE Timer Gate Single Pulse Acquisition Status bit

This bit is automatically cleared when TxGSPM is cleared.

Reset States: POR/BOR = 0

All Other Resets = u

Value Description

1Timer Gate Single Pulse Acquisition is ready, waiting for an edge

0Timer Gate Single Pulse Acquisition has completed or has not been started.

PIC18F26/45/46Q10

Timer1 Module with Gate Control

Bit 2 – GVAL Timer Gate Current State bit

Indicates the current state of the timer gate that could be provided to TMRxH:TMRxL

Unaffected by Timer Gate Enable (TMRxGE)

PIC18F26/45/46Q10

Timer1 Module with Gate Control

19.14.3 TMRxCLK

Name: TMRxCLK

Address: 0xFD1,0xFCB,0xFC5

Timer Clock Source Selection Register

Bit 7 6 5 4 3 2 1 0

CS[4:0]

Access R/W R/W R/W R/W R/W

Reset 0 0 0 0 0

Bits 4:0 – CS[4:0] Timer Clock Source Selection bits

Refer to the clock source selection table.

Reset States: POR/BOR = 00000

All Other Resets = uuuuu

PIC18F26/45/46Q10

Timer1 Module with Gate Control

19.14.4 TMRxGATE

Name: TMRxGATE

Address: 0xFD0,0xFCA,0xFC4

Timer Gate Source Selection Register

Bit 7 6 5 4 3 2 1 0

GSS[4:0]

Access R/W R/W R/W R/W R/W

Reset 0 0 0 0 0

Bits 4:0 – GSS[4:0] Timer Gate Source Selection bits

Refer to the gate source selection table.

Reset States: POR/BOR = 00000

All Other Resets = uuuuu

PIC18F26/45/46Q10

Timer1 Module with Gate Control

19.14.5 TMRx

Name: TMRx

Address: 0xFCC,0xFC6,0xFC0

Timer Low Byte Register

Bit 15 14 13 12 11 10 9 8

TMRxH[7:0]

Access R/W R/W R/W R/W R/W R/W R/W R/W

Reset 0 0 0 0 0 0 0 0

Bit 7 6 5 4 3 2 1 0

TMRxL[7:0]

Access R/W R/W R/W R/W R/W R/W R/W R/W

Reset 0 0 0 0 0 0 0 0

Bits 15:8 – TMRxH[7:0] Timer Most Significant Byte

Reset States: POR/BOR = 00000000

All Other Resets = uuuuuuuu

Bits 7:0 – TMRxL[7:0] Timer Least Significant Byte

Reset States: POR/BOR = 00000000

All Other Resets = uuuuuuuu

PIC18F26/45/46Q10

Timer1 Module with Gate Control

20. Timer2 Module

The Timer2 module is a 8-bit timer that incorporates the following features:

• 8-Bit Timer and Period Registers

• Readable and Writable

• Software Programmable Prescaler (1:1 to 1:128)

• Software Programmable Postscaler (1:1 to 1:16)

• Interrupt on T2TMR Match with T2PR

• One-Shot Operation

• Full Asynchronous Operation

• Includes Hardware Limit Timer (HLT)

• Alternate Clock Sources

• External Timer Reset Signal Sources

• Configurable Timer Reset Operation

See Figure 20-1 for a block diagram of Timer2. See table below for the clock source selections.

Important: References to module Timer2 apply to all the even numbered timers on this device.

(Timer2, Timer4, etc.)

PIC18F26/45/46Q10

Timer2 Module

Figure 20-1. Timer2 with Hardware Limit Timer (HLT) Block Diagram

Rev. 10-000168C

9/10/2015

MODE<3>

Clear ON

TxTMR

Comparator

TxPR

CSYNC

ON

OUTPS<3:0>

Postscaler

Set flag bit

TMRxIF

TMRx_postscaled

CPOL

4

MODE<4:0>

PSYNC

Prescaler

CKPS<2:0>

3

TMRx_clk

RSEL <4:0>

R

Sync

(2 Clocks)

Edge Detector

Level Detector

Mode Control

(2 clock Sync)

TMRx_ers

0

1

0

enable

reset

Sync

Fosc/4

D Q

CCP_pset(1)

MODE<4:1>=1011

MODE<4:3>=01

PPS

INPPS

TxIN

External

Reset

Sources

(2)

Note:

1. Signal to the CCP to trigger the PWM pulse.

2. See TxRST for external Reset sources.

Table 20-1. Clock Source Selection

CS<4:0>

Clock Source

Timer2 Timer4 Timer6

11111-11000 Reserved Reserved Reserved

10111 CLC8_out CLC8_out CLC8_out

10110 CLC7_out CLC7_out CLC7_out

10101 CLC6_out CLC6_out CLC6_out

10100 CLC5_out CLC5_out CLC5_out

10011 CLC4_out CLC4_out CLC4_out

10010 CLC3_out CLC3_out CLC3_out

10001 CLC2_out CLC2_out CLC2_out

10000 CLC1_out CLC1_out CLC1_out

PIC18F26/45/46Q10

Timer2 Module

...........continued

CS<4:0>

Clock Source

Timer2 Timer4 Timer6

01111-01001 Reserved Reserved Reserved

01000 ZCD_OUT ZCD_OUT ZCD_OUT

00111 CLKREF_OUT CLKREF_OUT CLKREF_OUT

00110 SOSC SOSC SOSC

00101 MFINTOSC (31 kHz) MFINTOSC (31 kHz) MFINTOSC (31 kHz)

00100 LFINTOSC LFINTOSC LFINTOSC

00011 HFINTOSC HFINTOSC HFINTOSC

00010 FOSC FOSC FOSC

00001 FOSC/4 FOSC/4 FOSC/4

00000 Pin selected by T2INPPS Pin selected by T4INPPS Pin selected by T6INPPS

20.1 Timer2 Operation

Timer2 operates in three major modes:

• Free Running Period

• One-shot

• Monostable

Within each mode there are several options for starting, stopping, and reset. Table 20-3 lists the options.

In all modes, the T2TMR count register is incremented on the rising edge of the clock signal from the

programmable prescaler. When T2TMR equals T2PR, a high level is output to the postscaler counter.

T2TMR is cleared on the next clock input.

An external signal from hardware can also be configured to gate the timer operation or force a T2TMR

count Reset. In Gate modes the counter stops when the gate is disabled and resumes when the gate is

enabled. In Reset modes the T2TMR count is reset on either the level or edge from the external source.

The T2TMR and T2PR registers are both directly readable and writable. The T2TMR register is cleared

and the T2PR register initializes to FFh on any device Reset. Both the prescaler and postscaler counters

are cleared on the following events:

• A write to the T2TMR register

• A write to the T2CON register

• Any device Reset

• External Reset Source event that resets the timer.

Important: T2TMR is not cleared when T2CON is written.

PIC18F26/45/46Q10

Timer2 Module

20.1.1 Free-Running Period Mode

The value of T2TMR is compared to that of the Period register, T2PR, on each clock cycle. When the two

values match, the comparator resets the value of T2TMR to 00h on the next cycle and increments the

output postscaler counter. When the postscaler count equals the value in the OUTPS bits of the T2CON

register then a one clock period wide pulse occurs on the TMR2_postscaled output, and the postscaler

count is cleared.

20.1.2 One-Shot Mode

The One-Shot mode is identical to the Free-Running Period mode except that the ON bit is cleared and

the timer is stopped when T2TMR matches T2PR and will not restart until the ON bit is cycled off and on.

Postscaler (OUTPS) values other than zero are ignored in this mode because the timer is stopped at the

first period event and the postscaler is reset when the timer is restarted.

20.1.3 Monostable Mode

Monostable modes are similar to One-Shot modes except that the ON bit is not cleared and the timer can

be restarted by an external Reset event.

20.2 Timer2 Output

The Timer2 module’s primary output is TMR2_postscaled, which pulses for a single TMR2_clk period

upon each match of the postscaler counter and the OUTPS bits of the T2CON register. The postscaler is

incremented each time the T2TMR value matches the T2PR value. This signal can be selected as an

input to several other input modules:

• The ADC module, as an auto-conversion trigger

• CWG, as an auto-shutdown source

• The CRC memory scanner, as a trigger for triggered mode

• Gate source for odd numbered timers (Timer1, Timer3, etc.)

• Alternate SPI clock

• Reset signals for other instances of even numbered timers (Timer2, Timer4, etc.)

In addition, the Timer2 is also used by the CCP module for pulse generation in PWM mode. See “PWM

Overview” and “Pulse-width Modulation” sections for more details on setting up Timer2 for use with the

CCP and PWM modules.

Related Links

21.4 PWM Overview

22. (PWM) Pulse-Width Modulation

20.3 External Reset Sources

In addition to the clock source, the Timer2 also takes in an external Reset source. This external Reset

source is selected for each timer with the corresponding TxRST register. This source can control starting

and stopping of the timer, as well as resetting the timer, depending on which mode the timer is in. Reset

source selections are shown in the following table.

PIC18F26/45/46Q10

Timer2 Module

Table 20-2. External Reset Sources

RSEL[4:0]

Reset Source

TMR2 TMR4 TMR6

11000-11111 Reserved Reserved Reserved

10111 CLC8_out CLC8_out CLC8_out

10110 CLC7_out CLC7_out CLC7_out

10101 CLC6_out CLC6_out CLC6_out

10100 CLC5_out CLC5_out CLC5_out

10011 CLC4_out CLC4_out CLC4_out

10010 CLC3_out CLC3_out CLC3_out

10001 CLC2_out CLC2_out CLC2_out

10000 CLC1_out CLC1_out CLC1_out

01111 EUSART2 TX/CK EUSART2 TX/CK EUSART2 TX/CK

01110 EUSART2 DT EUSART2 DT EUSART2 DT

01101 EUSART1 TX/CK EUSART1 TX/CK EUSART1 TX/CK

01100 EUSART1 DT EUSART1 DT EUSART1 DT

01011 Reserved Reserved Reserved

01010 ZCD_OUT ZCD_OUT ZCD_OUT

1001 CMP2OUT CMP2OUT CMP2OUT

01000 CMP1OUT CMP1OUT CMP1OUT

00111 PWM4OUT PWM4OUT PWM4OUT

00110 PWM3OUT PWM3OUT PWM3OUT

00101 CCP2OUT CCP2OUT CCP2OUT

00100 CCP1OUT CCP1OUT CCP1OUT

00011 TMR6 post-scaled TMR6 post-scaled Reserved

00010 TMR4 post-scaled Reserved TMR4 post-scaled

00001 Reserved TMR2 post-scaled TMR2 post-scaled

00000 Pin selected by T2INPPS Pin selected by T4INPPS Pin selected by T6INPPS

20.4 Timer2 Interrupt

Timer2 can also generate a device interrupt. The interrupt is generated when the postscaler counter

matches with the selected postscaler value (OUTPS bits of T2CON register). The interrupt is enabled by

setting the TMR2IE interrupt enable bit. Interrupt timing is illustrated in the figure below.

PIC18F26/45/46Q10

Timer2 Module

Figure 20-2. Timer2 Prescaler, Postscaler, and Interrupt Timing Diagram

Rev. 10-000205A

4/7/2016

TMRx_clk

PRx

TMRx

1

0

CKPS 0b010

TMRx_postscaled

OUTPS 0b0001

101010

TMRxIF (1)(1) (2)

Note:

1. Setting the interrupt flag is synchronized with the instruction clock.

2. Cleared by software.

20.5 Operating Modes

The mode of the timer is controlled by the MODE bits of the T2HLT register. Edge-Triggered modes

require six Timer clock periods between external triggers. Level-Triggered modes require the triggering

level to be at least three Timer clock periods long. External triggers are ignored while in Debug mode.

PIC18F26/45/46Q10

Timer2 Module

Table 20-3. Operating Modes Table

Mode

MODE<4:0> Output

Operation Operation

Timer Control

<4:3> <2:0> Start Reset Stop

Free-

Running

Period

00

000

Period Pulse

Software gate

(Figure 20-3)

ON = 1— ON = 0

001

Hardware

gate, active-

high

(Figure 20-4)

ON = 1 and

TMRx_ers =

1

— ON = 0 or

TMRx_ers = 0

010

Hardware

gate, active-

low

ON = 1 and

TMRx_ers =

0

— ON = 0 or

TMRx_ers = 1

011

Period

Pulse

with

Hardware

Reset

Rising or

falling edge

Reset

ON = 1

TMRx_ers

↕

ON = 0

100

Rising edge

Reset (Figure

20-5)

TMRx_ers

↑

101 Falling edge

Reset

TMRx_ers

↓

110 Low level

Reset

TMRx_ers

= 0

ON = 0 or

TMRx_ers = 0

111

High level

Reset (Figure

20-6)

TMRx_ers

= 1

ON = 0 or

TMRx_ers = 1

PIC18F26/45/46Q10

Timer2 Module

...........continued

Mode

MODE<4:0> Output

Operation Operation

Timer Control

<4:3> <2:0> Start Reset Stop

One-shot 01

000 One-shot Software start

(Figure 20-7)

ON = 1—

ON = 0

or

Next clock after

TMRx = PRx

(Note 2)

001

Edge-

Triggered

Start

(Note 1)

Rising edge

start (Figure

20-8)

ON = 1 and

TMRx_ers ↑ —

010 Falling edge

start

ON = 1 and

TMRx_ers ↓ —

011 Any edge

start

ON = 1 and

TMRx_ers ↕ —

100

Edge-

Triggered

Start

and

Hardware

Reset

(Note 1)

Rising edge

start and

Rising edge

Reset (Figure

20-9)

ON = 1 and

TMRx_ers ↑

TMRx_ers

↑

101

Falling edge

start and

Falling edge

Reset

ON = 1 and

TMRx_ers ↓

TMRx_ers

↓

110

Rising edge

start and

Low level

Reset (Figure

20-10)

ON = 1 and

TMRx_ers ↑

TMRx_ers

= 0

111

Falling edge

start and

High level

Reset

ON = 1 and

TMRx_ers ↓

TMRx_ers

= 1

PIC18F26/45/46Q10

Timer2 Module

...........continued

Mode

MODE<4:0> Output

Operation Operation

Timer Control

<4:3> <2:0> Start Reset Stop

Mono-

stable

10

000 Reserved

001 Edge-

Triggered

Start

(Note 1)

Rising edge

start

(Figure 20-11)

ON = 1 and

TMRx_ers ↑ —ON = 0

or

Next clock after

TMRx = PRx

(Note 3)

010 Falling edge

start

ON = 1 and

TMRx_ers ↓ —

011 Any edge

start

ON = 1 and

TMRx_ers ↕ —

Reserved 100 Reserved

Reserved 101 Reserved

One-shot

110

Level

Triggered

Start

and

Hardware

Reset

High level

start and

Low level

Reset (Figure

20-12)

ON = 1 and

TMRx_ers =

1

TMRx_ers

= 0ON = 0 or

Held in Reset

(Note 2)

111

Low level

start and

High level

Reset

ON = 1 and

TMRx_ers =

0

TMRx_ers

= 1

Reserved 11 xxx Reserved

Note:

1. If ON = 0 then an edge is required to restart the timer after ON = 1.

2. When T2TMR = T2PR then the next clock clears ON and stops T2TMR at 00h.

3. When T2TMR = T2PR then the next clock stops T2TMR at 00h but does not clear ON.

20.6 Operation Examples

Unless otherwise specified, the following notes apply to the following timing diagrams:

• Both the prescaler and postscaler are set to 1:1 (both the CKPS and OUTPS bits in the T2CON

register are cleared).

• The diagrams illustrate any clock except FOSC/4 and show clock-sync delays of at least two full

cycles for both ON and Timer2_ers. When using FOSC/4, the clock-sync delay is at least one

instruction period for Timer2_ers; ON applies in the next instruction period.

• ON and Timer2_ers are somewhat generalized, and clock-sync delays may produce results that are

slightly different than illustrated.

PIC18F26/45/46Q10

Timer2 Module

• The PWM Duty Cycle and PWM output are illustrated assuming that the timer is used for the PWM

function of the CCP module as described in the “PWM Overview” section. The signals are not a part

of the Timer2 module.

Related Links

21.4 PWM Overview

22. (PWM) Pulse-Width Modulation

20.6.1 Software Gate Mode

This mode corresponds to legacy Timer2 operation. The timer increments with each clock input when ON

= 1 and does not increment when ON = 0. When the TMRx count equals the PRx period count the timer

resets on the next clock and continues counting from 0. Operation with the ON bit software controlled is

illustrated in Figure 20-3. With PRx = 5, the counter advances until TMRx = 5, and goes to zero with the

next clock.

Figure 20-3. Software Gate Mode Timing Diagram (MODE = 00000)

Rev. 10-000195B

5/30/2014

TMRx_clk

Instruction(1)

ON

PRx

TMRx

TMRx_postscaled

BSF BCF BSF

5

0 1 2 3 4 5 0 1 2 2 3 4 5

MODE 0b00000

3 4 5 0 1 0 1

PWM Duty

Cycle 3

PWM Output

Note:

1. BSF and BCF represent Bit-Set File and Bit-Clear File instructions executed by the CPU to set or

clear the ON bit of TxCON. CPU execution is asynchronous to the timer clock input.

Related Links

21.4 PWM Overview

22. (PWM) Pulse-Width Modulation

20.6.2 Hardware Gate Mode

The Hardware Gate modes operate the same as the Software Gate mode except the TMRx_ers external

signal can also gate the timer. When used with the CCP, the gating extends the PWM period. If the timer

is stopped when the PWM output is high, then the duty cycle is also extended.

When MODE<4:0> = 00001 then the timer is stopped when the external signal is high. When

MODE<4:0> = 00010, then the timer is stopped when the external signal is low.

PIC18F26/45/46Q10

Timer2 Module

Figure 20-4 illustrates the Hardware Gating mode for MODE<4:0> = 00001 in which a high input level

starts the counter.

Figure 20-4. Hardware Gate Mode Timing Diagram (MODE = 00001)

Rev. 10-000 196B

5/30/201 4

TMRx_clk

TMRx_ers

PRx

TMRx

TMRx_postscaled

5

MODE 0b00001

0 1 2 3 4 5 0 1 2 3 4 5 0 1

PWM Duty

Cycle 3

PWM Output

Related Links

21.4 PWM Overview

22. (PWM) Pulse-Width Modulation

20.6.3 Edge-Triggered Hardware Limit Mode

In Hardware Limit mode, the timer can be reset by the TMRx_ers external signal before the timer reaches

the period count. Three types of Resets are possible:

• Reset on rising or falling edge (MODE<4:0>= 00011)

• Reset on rising edge (MODE<4:0> = 00100)

• Reset on falling edge (MODE<4:0> = 00101)

When the timer is used in conjunction with the CCP in PWM mode then an early Reset shortens the

period and restarts the PWM pulse after a two clock delay. Refer to Figure 20-5.

PIC18F26/45/46Q10

Timer2 Module

Figure 20-5. Edge-Triggered Hardware Limit Mode Timing Diagram

(MODE = 00100)

Rev. 10-000 197B

5/30/201 4

TMRx_clk

ON

PRx

TMRx

BSF BCF BSF

5

0 1 2 0 1 2 3 4 5 0 4 5 0

MODE 0b00100

TMRx_ers

1 2 3 1

TMRx_postscaled

PWM Duty

Cycle 3

PWM Output

Instruction(1)

Note:

1. BSF and BCF represent Bit-Set File and Bit-Clear File instructions executed by the CPU to set or

clear the ON bit of TxCON. CPU execution is asynchronous to the timer clock input.

Related Links

21.4 PWM Overview

22. (PWM) Pulse-Width Modulation

20.6.4 Level-Triggered Hardware Limit Mode

In the Level-Triggered Hardware Limit Timer modes the counter is reset by high or low levels of the

external signal TMRx_ers, as shown in Figure 20-6. Selecting MODE<4:0> = 00110 will cause the timer

to reset on a low level external signal. Selecting MODE<4:0> = 00111 will cause the timer to reset on a

high level external signal. In the example, the counter is reset while TMRx_ers = 1. ON is controlled by

BSF and BCF instructions. When ON = 0 the external signal is ignored.

When the CCP uses the timer as the PWM time base then the PWM output will be set high when the

timer starts counting and then set low only when the timer count matches the CCPRx value. The timer is

reset when either the timer count matches the PRx value or two clock periods after the external Reset

signal goes true and stays true.

The timer starts counting, and the PWM output is set high, on either the clock following the PRx match or

two clocks after the external Reset signal relinquishes the Reset. The PWM output will remain high until

the timer counts up to match the CCPRx pulse width value. If the external Reset signal goes true while

the PWM output is high then the PWM output will remain high until the Reset signal is released allowing

the timer to count up to match the CCPRx value.

PIC18F26/45/46Q10

Timer2 Module

Figure 20-6. Level-Triggered Hardware Limit Mode Timing Diagram

(MODE = 00111)

Rev. 10-000198B

5/30/2014

TMRx_clk

ON

PRx

TMRx

BSF BCF BSF

5

0 1 2 0 1 2 3 4 5 1 2 3

MODE 0b00111

TMRx_ers

00 4

TMRx_postscaled

5 0

PWM Duty

Cycle 3

PWM Output

Instruction(1)

Note:

1. BSF and BCF represent Bit-Set File and Bit-Clear File instructions executed by the CPU to set or

clear the ON bit of TxCON. CPU execution is asynchronous to the timer clock input.

Related Links

21.4 PWM Overview

22. (PWM) Pulse-Width Modulation

20.6.5 Software Start One-Shot Mode

In One-Shot mode the timer resets and the ON bit is cleared when the timer value matches the PRx

period value. The ON bit must be set by software to start another timer cycle. Setting MODE<4:0> =

01000 selects One-Shot mode which is illustrated in Figure 20-7. In the example, ON is controlled by

BSF and BCF instructions. In the first case, a BSF instruction sets ON and the counter runs to completion

and clears ON. In the second case, a BSF instruction starts the cycle, BCF/BSF instructions turn the

counter off and on during the cycle, and then it runs to completion.

When One-Shot mode is used in conjunction with the CCP PWM operation the PWM pulse drive starts

concurrent with setting the ON bit. Clearing the ON bit while the PWM drive is active will extend the PWM

drive. The PWM drive will terminate when the timer value matches the CCPRx pulse width value. The

PWM drive will remain off until software sets the ON bit to start another cycle. If software clears the ON

bit after the CCPRx match but before the PRx match then the PWM drive will be extended by the length

of time the ON bit remains cleared. Another timing cycle can only be initiated by setting the ON bit after it

has been cleared by a PRx period count match.

PIC18F26/45/46Q10

Timer2 Module

Figure 20-7. Software Start One-Shot Mode Timing Diagram (MODE = 01000)

Rev. 10-000199B

4/7/2016

TMRx_clk

ON

PRx

TMRx

BSF BSF

5

0 1 2 3 4 5 0 431

MODE 0b01000

2 5 0

TMRx_postscaled

BCF BSF

PWM Duty

Cycle 3

PWM Output

Instruction(1)

Note:

1. BSF and BCF represent Bit-Set File and Bit-Clear File instructions executed by the CPU to set or

clear the ON bit of TxCON. CPU execution is asynchronous to the timer clock input.

Related Links

21.4 PWM Overview

22. (PWM) Pulse-Width Modulation

20.6.6 Edge-Triggered One-Shot Mode

The Edge-Triggered One-Shot modes start the timer on an edge from the external signal input, after the

ON bit is set, and clear the ON bit when the timer matches the PRx period value. The following edges will

start the timer:

• Rising edge (MODE<4:0> = 01001)

• Falling edge (MODE<4:0> = 01010)

• Rising or Falling edge (MODE<4:0> = 01011)

If the timer is halted by clearing the ON bit then another TMRx_ers edge is required after the ON bit is set

to resume counting. Figure 20-8 illustrates operation in the rising edge One-Shot mode.

When Edge-Triggered One-Shot mode is used in conjunction with the CCP then the edge-trigger will

activate the PWM drive and the PWM drive will deactivate when the timer matches the CCPRx pulse

width value and stay deactivated when the timer halts at the PRx period count match.

PIC18F26/45/46Q10

Timer2 Module

Figure 20-8. Edge-Triggered One-Shot Mode Timing Diagram (MODE = 01001)

Rev. 10-000200B

5/19/2016

TMRx_clk

ON

PRx

TMRx

BSF BSF

5

0 1 2 3 4 5 0 1

MODE 0b01001

2

CCP_pset

TMRx_postscaled

BCF

TMRx_ers

PWM Duty

Cycle 3

PWM Output

Instruction(1)

Note:

1. BSF and BCF represent Bit-Set File and Bit-Clear File instructions executed by the CPU to set or

clear the ON bit of TxCON. CPU execution is asynchronous to the timer clock input.

Related Links

21.4 PWM Overview

22. (PWM) Pulse-Width Modulation

20.6.7 Edge-Triggered Hardware Limit One-Shot Mode

In Edge-Triggered Hardware Limit One-Shot modes the timer starts on the first external signal edge after

the ON bit is set and resets on all subsequent edges. Only the first edge after the ON bit is set is needed

to start the timer. The counter will resume counting automatically two clocks after all subsequent external

Reset edges. Edge triggers are as follows:

• Rising edge start and Reset (MODE<4:0> = 01100)

• Falling edge start and Reset (MODE<4:0> = 01101)

The timer resets and clears the ON bit when the timer value matches the PRx period value. External

signal edges will have no effect until after software sets the ON bit. Figure 20-9 illustrates the rising edge

hardware limit one-shot operation.

When this mode is used in conjunction with the CCP then the first starting edge trigger, and all

subsequent Reset edges, will activate the PWM drive. The PWM drive will deactivate when the timer

matches the CCPRx pulse-width value and stay deactivated until the timer halts at the PRx period match

unless an external signal edge resets the timer before the match occurs.

PIC18F26/45/46Q10

Timer2 Module

Figure 20-9. Edge-Triggered Hardware Limit One-Shot Mode Timing Diagram (MODE = 01100)

Rev. 10-000201B

4/7/2016

TMRx_clk

ON

PRx

TMRx

BSF BSF

5

0 1 2 3 4 5 0 01

MODE 0b01100

2

TMRx_postscaled

TMRx_ers

1 2 3 4 5 0

PWM Duty

Cycle 3

PWM Output

Instruction(1)

Note:

1. BSF and BCF represent Bit-Set File and Bit-Clear File instructions executed by the CPU to set or

clear the ON bit of TxCON. CPU execution is asynchronous to the timer clock input.

Related Links

21.4 PWM Overview

22. (PWM) Pulse-Width Modulation

20.6.8 Level Reset, Edge-Triggered Hardware Limit One-Shot Modes

In Level -Triggered One-Shot mode the timer count is reset on the external signal level and starts

counting on the rising/falling edge of the transition from Reset level to the active level while the ON bit is

set. Reset levels are selected as follows:

• Low Reset level (MODE<4:0> = 01110)

• High Reset level (MODE<4:0> = 01111)

When the timer count matches the PRx period count, the timer is reset and the ON bit is cleared. When

the ON bit is cleared by either a PRx match or by software control, a new external signal edge is required

after the ON bit is set to start the counter.

When Level-Triggered Reset One-Shot mode is used in conjunction with the CCP PWM operation, the

PWM drive goes active with the external signal edge that starts the timer. The PWM drive goes inactive

when the timer count equals the CCPRx pulse width count. The PWM drive does not go active when the

timer count clears at the PRx period count match.

PIC18F26/45/46Q10

Timer2 Module

Figure 20-10. Low Level Reset, Edge-Triggered Hardware Limit One-Shot Mode Timing Diagram

(MODE = 01110)

Rev. 10-000202B

4/7/2016

TMRx_clk

ON

PRx

TMRx

BSF BSF

5

0 1 2 3 4 5 0 01

MODE 0b01110

TMRx_postscaled

TMRx_ers

1 2 3 4 0

PWM Duty

Cycle 3

PWM Output

5

Instruction(1)

Note:

1. BSF and BCF represent Bit-Set File and Bit-Clear File instructions executed by the CPU to set or

clear the ON bit of TxCON. CPU execution is asynchronous to the timer clock input.

Related Links

21.4 PWM Overview

22. (PWM) Pulse-Width Modulation

20.6.9 Edge-Triggered Monostable Modes

The Edge-Triggered Monostable modes start the timer on an edge from the external Reset signal input,

after the ON bit is set, and stop incrementing the timer when the timer matches the PRx period value. The

following edges will start the timer:

• Rising edge (MODE<4:0> = 10001)

• Falling edge (MODE<4:0> = 10010)

• Rising or Falling edge (MODE<4:0> = 10011)

When an Edge-Triggered Monostable mode is used in conjunction with the CCP PWM operation, the

PWM drive goes active with the external Reset signal edge that starts the timer, but will not go active

when the timer matches the PRx value. While the timer is incrementing, additional edges on the external

Reset signal will not affect the CCP PWM.

PIC18F26/45/46Q10

Timer2 Module

Figure 20-11. Rising Edge-Triggered Monostable Mode Timing Diagram (MODE = 10001)

Rev. 10-000203A

4/7/2016

TMRx_clk

ON

PRx

TMRx

BSF BCF

5

0 1 2 3 4 5 0 1

MODE 0b10001

TMRx_postscaled

TMRx_ers

2 3 4 5 0

PWM Duty

Cycle 3

PWM Output

Instruction(1) BSF BCF BSF

1 2 3 4 5 0

Note:

1. BSF and BCF represent Bit-Set File and Bit-Clear File instructions executed by the CPU to set or

clear the ON bit of TxCON. CPU execution is asynchronous to the timer clock input.

Related Links

21.4 PWM Overview

22. (PWM) Pulse-Width Modulation

20.6.10 Level-Triggered Hardware Limit One-Shot Modes

The Level-Triggered Hardware Limit One-Shot modes hold the timer in Reset on an external Reset level

and start counting when both the ON bit is set and the external signal is not at the Reset level. If one of

either the external signal is not in Reset or the ON bit is set, then the other signal being set/made active

will start the timer. Reset levels are selected as follows:

• Low Reset level (MODE<4:0> = 10110)

• High Reset level (MODE<4:0> = 10111)

When the timer count matches the PRx period count, the timer is reset and the ON bit is cleared. When

the ON bit is cleared by either a PRx match or by software control, the timer will stay in Reset until both

the ON bit is set and the external signal is not at the Reset level.

When Level-Triggered Hardware Limit One-Shot modes are used in conjunction with the CCP PWM

operation, the PWM drive goes active with either the external signal edge or the setting of the ON bit,

whichever of the two starts the timer.

PIC18F26/45/46Q10

Timer2 Module

Figure 20-12. Level-Triggered hardware Limit one-Shot Mode Timing Diagram (MODE = 10110)

Rev. 10-000204A

4/7/2016

TMR2_clk

Instruction(1)

ON

PRx

TMRx

BSF BSF

5

0 1 2 3 4 5 0 1

MODE 0b10110

TMR2_postscaled

TMR2_ers

2 1 20

PWM Duty

Cycle ‘D3

PWM Output

3 3 4 5 0

BSFBCF

Note:

1. BSF and BCF represent Bit-Set File and Bit-Clear File instructions executed by the CPU to set or

clear the ON bit of TxCON. CPU execution is asynchronous to the timer clock input.

Related Links

21.4 PWM Overview

22. (PWM) Pulse-Width Modulation

20.7 Timer2 Operation During Sleep

When PSYNC = 1, Timer2 cannot be operated while the processor is in Sleep mode. The contents of the

T2TMR and T2PR registers will remain unchanged while processor is in Sleep mode.

When PSYNC = 0, Timer2 will operate in Sleep as long as the clock source selected is also still running.

If any internal oscillator is selected as the clock source, it will stay active during Sleep mode.

PIC18F26/45/46Q10

Timer2 Module

20.8 Register Summary - Timer2

Address Name Bit Pos.

0x0FAE T6TMR 7:0 TxTMR[7:0]

0x0FAF T6PR 7:0 TxPR[7:0]

0x0FB0 T6CON 7:0 ON CKPS[2:0] OUTPS[3:0]

0x0FB1 T6HLT 7:0 PSYNC CPOL CSYNC MODE[4:0]

0x0FB2 T6CLKCON 7:0 CS[4:0]

0x0FB3 T6RST 7:0 RSEL[4:0]

0x0FB4 T4TMR 7:0 TxTMR[7:0]

0x0FB5 T4PR 7:0 TxPR[7:0]

0x0FB6 T4CON 7:0 ON CKPS[2:0] OUTPS[3:0]

0x0FB7 T4HLT 7:0 PSYNC CPOL CSYNC MODE[4:0]

0x0FB8 T4CLKCON 7:0 CS[4:0]

0x0FB9 T4RST 7:0 RSEL[4:0]

0x0FBA T2TMR 7:0 TxTMR[7:0]

0x0FBB T2PR 7:0 TxPR[7:0]

0x0FBC T2CON 7:0 ON CKPS[2:0] OUTPS[3:0]

0x0FBD T2HLT 7:0 PSYNC CPOL CSYNC MODE[4:0]

0x0FBE T2CLKCON 7:0 CS[4:0]

0x0FBF T2RST 7:0 RSEL[4:0]

20.9 Register Definitions: Timer2 Control

Long bit name prefixes for the Timer2 peripherals are shown in table below. Refer to Section "Long Bit

Names" for more information.

Table 20-4. Timer2 long bit name prefixes

Peripheral Bit Name Prefix

Timer2 T2

Timer4 T4

Timer6 T6

Notice: References to module Timer2 apply to all the even numbered timers on this device.

(Timer2, Timer4, etc.)

Related Links

1.4.2.2 Long Bit Names

PIC18F26/45/46Q10

Timer2 Module

20.9.1 TxTMR

Name: TxTMR

Address: 0xFBA,0xFB4,0xFAE

Timer Counter Register

Bit 7 6 5 4 3 2 1 0

TxTMR[7:0]

Access R/W R/W R/W R/W R/W R/W R/W R/W

Reset 0 0 0 0 0 0 0 0

Bits 7:0 – TxTMR[7:0] Timerx Counter bits

PIC18F26/45/46Q10

Timer2 Module

20.9.2 TxPR

Name: TxPR

Address: 0xFBB,0xFB5,0xFAF

Timer Period Register

Bit 7 6 5 4 3 2 1 0

TxPR[7:0]

Access R/W R/W R/W R/W R/W R/W R/W R/W

Reset 1 1 1 1 1 1 1 1

Bits 7:0 – TxPR[7:0] Timer Period Register bits

Value Description

0 - 255 The timer restarts at ‘0’ when TxTMR reaches TxPR value

PIC18F26/45/46Q10

Timer2 Module

20.9.3 TxCON

Name: TxCON

Address: 0xFBC,0xFB6,0xFB0

Timerx Control Register

Bit 7 6 5 4 3 2 1 0

ON CKPS[2:0] OUTPS[3:0]

Access R/W/HC R/W R/W R/W R/W R/W R/W R/W

Reset 0 0 0 0 0 0 0 0

Bit 7 – ON

Timer On bit(1)

Value Description

1Timer is on

0Timer is off: all counters and state machines are reset

Bits 6:4 – CKPS[2:0] Timer Clock Prescale Select bits

Value Description

111 1:128 Prescaler

110 1:64 Prescaler

101 1:32 Prescaler

100 1:16 Prescaler

011 1:8 Prescaler

010 1:4 Prescaler

001 1:2 Prescaler

000 1:1 Prescaler

Bits 3:0 – OUTPS[3:0] Timer Output Postscaler Select bits

Value Description

1111 1:16 Postscaler

1110 1:15 Postscaler

1101 1:14 Postscaler

1100 1:13 Postscaler

1011 1:12 Postscaler

1010 1:11 Postscaler

1001 1:10 Postscaler

1000 1:9 Postscaler

0111 1:8 Postscaler

0110 1:7 Postscaler

0101 1:6 Postscaler

0100 1:5 Postscaler

0011 1:4 Postscaler

0010 1:3 Postscaler

0001 1:2 Postscaler

0000 1:1 Postscaler

PIC18F26/45/46Q10

Timer2 Module

Note:

1. In certain modes, the ON bit will be auto-cleared by hardware. See Table 20-3.

PIC18F26/45/46Q10

Timer2 Module

20.9.4 TxHLT

Name: TxHLT

Address: 0xFBD,0xFB7,0xFB1

Timer Hardware Limit Control Register

Bit 7 6 5 4 3 2 1 0

PSYNC CPOL CSYNC MODE[4:0]

Access R/W R/W R/W R/W R/W R/W R/W R/W

Reset 0 0 0 0 0 0 0 0

Bit 7 – PSYNC

Timer Prescaler Synchronization Enable bit(1, 2)

Value Description

1Timer Prescaler Output is synchronized to FOSC/4

0Timer Prescaler Output is not synchronized to FOSC/4

Bit 6 – CPOL

Timer Clock Polarity Selection bit(3)

Value Description

1Falling edge of input clock clocks timer/prescaler

0Rising edge of input clock clocks timer/prescaler

Bit 5 – CSYNC

Timer Clock Synchronization Enable bit(4, 5)

Value Description

1ON bit is synchronized to timer clock input

0ON bit is not synchronized to timer clock input

Bits 4:0 – MODE[4:0]

Timer Control Mode Selection bits(6, 7)

Value Description

00000

to

11111

See Table 20-3

Note:

1. Setting this bit ensures that reading TxTMR will return a valid data value.

2. When this bit is ‘1’, Timer cannot operate in Sleep mode.

3. CKPOL should not be changed while ON = 1.

4. Setting this bit ensures glitch-free operation when the ON is enabled or disabled.

5. When this bit is set then the timer operation will be delayed by two input clocks after the ON bit is

set.

6. Unless otherwise indicated, all modes start upon ON = 1 and stop upon ON = 0 (stops occur

without affecting the value of TxTMR).

7. When TxTMR = TxPR, the next clock clears TxTMR, regardless of the operating mode.

PIC18F26/45/46Q10

Timer2 Module

20.9.5 TxCLKCON

Name: TxCLKCON

Address: 0xFBE,0xFB8,0xFB2

Timer Clock Source Selection Register

Bit 7 6 5 4 3 2 1 0

CS[4:0]

Access R/W R/W R/W R/W R/W

Reset 0 0 0 0 0

Bits 4:0 – CS[4:0] Timer Clock Source Selection bits

Value Description

nSee Clock Source Selection table

PIC18F26/45/46Q10

Timer2 Module

20.9.6 TxRST

Name: TxRST

Address: 0xFBF,0xFB9,0xFB3

Timer External Reset Signal Selection Register

Bit 7 6 5 4 3 2 1 0

RSEL[4:0]

Access R/W R/W R/W R/W R/W

Reset 0 0 0 0 0

Bits 4:0 – RSEL[4:0]

External Reset Source Selection Bits

Value Description

nSee External Reset Sources table

PIC18F26/45/46Q10

Timer2 Module

21. Capture/Compare/PWM Module

The Capture/Compare/PWM module is a peripheral that allows the user to time and control different

events, and to generate Pulse-Width Modulation (PWM) signals. In Capture mode, the peripheral allows

the timing of the duration of an event. The Compare mode allows the user to trigger an external event

when a predetermined amount of time has expired. The PWM mode can generate Pulse-Width

Modulated signals of varying frequency and duty cycle.

This family of devices contains two standard Capture/Compare/PWM modules (CCP1 and CCP2). Each

individual CCP module can select the timer source that controls the module. Each module has an

independent timer selection which can be accessed using the CxTSEL bits in the CCPTMRS register.

The default timer selection is TMR1 when using Capture/Compare mode and T2TMR when using PWM

mode in the CCPx module.

It should be noted that the Capture/Compare mode operation is described with respect to TMR1 and the

PWM mode operation is described with respect to T2TMR in the following sections.

The Capture and Compare functions are identical for all CCP modules.

Important:

1. In devices with more than one CCP module, it is very important to pay close attention to

the register names used. A number placed after the module acronym is used to

distinguish between separate modules. For example, the CCP1CON and CCP2CON

control the same operational aspects of two completely different CCP modules.

2. Throughout this section, generic references to a CCP module in any of its operating

modes may be interpreted as being equally applicable to CCPx module. Register names,

module signals, I/O pins, and bit names may use the generic designator ‘x’ to indicate the

use of a numeral to distinguish a particular module, when required.

21.1 CCP Module Configuration

Each Capture/Compare/PWM module is associated with a control register (CCPxCON), a capture input

selection register (CCPxCAP) and a data register (CCPRx). The data register, in turn, is comprised of two

8-bit registers: CCPRxL (low byte) and CCPRxH (high byte).

21.1.1 CCP Modules and Timer Resources

The CCP modules utilize Timers 1 through 6 that vary with the selected mode. Various timers are

available to the CCP modules in Capture, Compare or PWM modes, as shown in the table below.

Table 21-1. CCP Mode - Timer Resources

CCP Mode Timer Resource

Capture

Timer1, Timer3 or Timer5

Compare

PWM Timer2, Timer4 or Timer6

PIC18F26/45/46Q10

Capture/Compare/PWM Module

The assignment of a particular timer to a module is determined by the timer to CCP enable bits in the

CCPTMRS register. All of the modules may be active at once and may share the same timer resource if

they are configured to operate in the same mode (Capture/Compare or PWM) at the same time.

21.1.2 Open-Drain Output Option

When operating in Output mode (the Compare or PWM modes), the drivers for the CCPx pins can be

optionally configured as open-drain outputs. This feature allows the voltage level on the pin to be pulled

to a higher level through an external pull-up resistor and allows the output to communicate with external

circuits without the need for additional level shifters.

21.2 Capture Mode

Capture mode makes use of the 16-bit odd numbered timer resources (Timer1, Timer3, etc.). When an

event occurs on the capture source, the 16-bit CCPRx register captures and stores the 16-bit value of the

TMRx register. An event is defined as one of the following and is configured by the MODE bits:

• Every falling edge of CCPx input

• Every rising edge of CCPx input

• Every 4th rising edge of CCPx input

• Every 16th rising edge of CCPx input

• Every edge of CCPx input (rising or falling)

When a capture is made, the Interrupt Request Flag bit CCPxIF of the PIRx register is set. The interrupt

flag must be cleared in software. If another capture occurs before the value in the CCPRx register is read,

the old captured value is overwritten by the new captured value.

Important: If an event occurs during a 2-byte read, the high and low-byte data will be from

different events. It is recommended while reading the CCPRxH:CCPRxL register pair to either

disable the module or read the register pair twice for data integrity.

The following figure shows a simplified diagram of the capture operation.

Figure 21-1. Capture Mode Operation Block Diagram

Rev. 10-000158E

6/26/2017

CCPRxH CCPRxL

TMR1H TMR1L

16

Prescaler

1,4,16

CCPx

TRIS Control

set CCPxIF

CCPx MODE <3:0>

and

Edge Detect

RxyPPS

CTS PPS

PPS

CCPxPPS

Capture Trigger Sources

See CCPxCAP register

PIC18F26/45/46Q10

Capture/Compare/PWM Module

21.2.1 Capture Sources

In Capture mode, the CCPx pin should be configured as an input by setting the associated TRIS control

bit.

Important: If the CCPx pin is configured as an output, a write to the port can cause a capture

condition.

The capture source is selected by configuring the CTS bits as shown in the following table:

Table 21-2. Capture Trigger Sources

CTS Source

1111 CLC8_out

1110 CLC7_out

1101 CLC6_out

1100 CLC5_out

1011 CLC4_out

1010 CLC3_out

1001 CLC2_out

1000 CLC1_out

0100-0111 Reserved

0011 IOC Interrupt

0010 CMP2_output

0001 CMP1_output

0000 Pin selected by CCPxPPS

21.2.2 Timer1 Mode Resource

Timer1 must be running in Timer mode or Synchronized Counter mode for the CCP module to use the

capture feature. In Asynchronous Counter mode, the capture operation may not work.

See section "Timer1 Module with Gate Control" for more information on configuring Timer1.

Related Links

19. Timer1 Module with Gate Control

21.2.3 Software Interrupt Mode

When the Capture mode is changed, a false capture interrupt may be generated. The user should keep

the CCPxIE Interrupt Priority bit of the PIEx register clear to avoid false interrupts. Additionally, the user

should clear the CCPxIF interrupt flag bit of the PIRx register following any change in Operating mode.

PIC18F26/45/46Q10

Capture/Compare/PWM Module

Important: Clocking Timer1 from the system clock (FOSC) should not be used in Capture

mode. In order for Capture mode to recognize the trigger event on the CCPx pin, Timer1 must

be clocked from the instruction clock (FOSC/4) or from an external clock source.

21.2.4 CCP Prescaler

There are four prescaler settings specified by the MODE bits. Whenever the CCP module is turned off, or

the CCP module is not in Capture mode, the prescaler counter is cleared. Any Reset will clear the

prescaler counter.

Switching from one capture prescaler to another does not clear the prescaler and may generate a false

interrupt. To avoid this unexpected operation, turn the module off by clearing the CCPxCON register

before changing the prescaler. The example below demonstrates the code to perform this function.

Example 21-1. Changing Between Capture Prescalers

BANKSEL CCP1CON ;(only needed when CCP1CON is not in ACCESS space)

CLRF CCP1CON ;Turn CCP module off

MOVLW NEW_CAPT_PS ;CCP ON and Prescaler select → W

MOVWF CCP1CON ;Load CCP1CON with this value

21.2.5 Capture During Sleep

Capture mode depends upon the Timer1 module for proper operation. There are two options for driving

the Timer1 module in Capture mode. It can be driven by the instruction clock (FOSC/4), or by an external

clock source.

When Timer1 is clocked by FOSC/4, Timer1 will not increment during Sleep. When the device wakes from

Sleep, Timer1 will continue from its previous state.

Capture mode will operate during Sleep when Timer1 is clocked by an external clock source.

21.3 Compare Mode

The Compare mode function described in this section is available and identical for all CCP modules.

Compare mode makes use of the 16-bit odd numbered Timer resources (Timer1, Timer3, etc.). The 16-bit

value of the CCPRx register is constantly compared against the 16-bit value of the TMRx register. When

a match occurs, one of the following events can occur:

• Toggle the CCPx output and clear TMRx

• Toggle the CCPx output without clearing TMRx

• Set the CCPx output

• Clear the CCPx output

• Pulse output

• Pulse output and clear TMRx

The action on the pin is based on the value of the MODE control bits. At the same time, the interrupt flag

CCPxIF bit is set, and an ADC conversion can be triggered, if selected.

All Compare modes can generate an interrupt and trigger an ADC conversion. When MODE = '0001' or

'1011', the CCP resets the TMRx register.

The following figure shows a simplified diagram of the compare operation.

PIC18F26/45/46Q10

Capture/Compare/PWM Module

Figure 21-2. Compare Mode Operation Block Diagram

CCPRxH CCPRxL

TMR1H TMR1L

Comparator

Q S

R

Output

Logic

PPS

RxyPPS

Set CCPxIF Interrupt Flag

4

TRIS

CCPx

Auto-conversion Trigger

MODE

Rev. 30-000133A

6/27/2017

21.3.1 CCPx Pin Configuration

The software must configure the CCPx pin as an output by clearing the associated TRIS bit and defining

the appropriate output pin through the RxyPPS registers. See section "Peripheral Pin Select (PPS)

Module" for more details.

The CCP output can also be used as an input for other peripherals.

Important: Clearing the CCPxCON register will force the CCPx compare output latch to the

default low level. This is not the PORT I/O data latch.

Related Links

17. (PPS) Peripheral Pin Select Module

21.3.2 Timer1 Mode Resource

In Compare mode, Timer1 must be running in either Timer mode or Synchronized Counter mode. The

compare operation may not work in Asynchronous Counter mode.

See Section "Timer1 Module with Gate Control" for more information on configuring Timer1.

Important: Clocking Timer1 from the system clock (FOSC) should not be used in Compare

mode. In order for Compare mode to generate the trigger event on the CCPx pin, Timer1 must

be clocked from the instruction clock (FOSC/4) or from an external clock source.

21.3.3 Auto-Conversion Trigger

All CCPx modes set the CCP Interrupt Flag (CCPxIF). When this flag is set and a match occurs, an auto-

conversion trigger can take place if the CCP module is selected as the conversion trigger source.

Refer to Section "Auto-Conversion Trigger" for more information.

Important: Removing the match condition by changing the contents of the CCPRxH and

CCPRxL register pair, between the clock edge that generates the Auto-conversion Trigger and

the clock edge that generates the Timer1 Reset, will preclude the Reset from occurring.

PIC18F26/45/46Q10

Capture/Compare/PWM Module

Related Links

32.2.6 Auto-Conversion Trigger

21.3.4 Compare During Sleep

Since FOSC is shut down during Sleep mode, the Compare mode will not function properly during Sleep,

unless the timer is running. The device will wake on interrupt (if enabled).

21.4 PWM Overview

Pulse-Width Modulation (PWM) is a scheme that provides power to a load by switching quickly between

fully ON and fully OFF states. The PWM signal resembles a square wave where the high portion of the

signal is considered the ON state and the low portion of the signal is considered the OFF state. The high

portion, also known as the pulse width, can vary in time and is defined in steps. A larger number of steps

applied, which lengthens the pulse width, also supplies more power to the load. Lowering the number of

steps applied, which shortens the pulse width, supplies less power. The PWM period is defined as the

duration of one complete cycle or the total amount of ON and OFF time combined.

PWM resolution defines the maximum number of steps that can be present in a single PWM period. A

higher resolution allows for more precise control of the pulse-width time and in turn the power that is

applied to the load.

The term duty cycle describes the proportion of the ON time to the OFF time and is expressed in

percentages, where 0% is fully OFF and 100% is fully ON. A lower duty cycle corresponds to less power

applied and a higher duty cycle corresponds to more power applied.

The figure below shows a typical waveform of the PWM signal.

Figure 21-3. CCP PWM Output Signal

Period

Pulse Width

TMR2 = 0

TMR2 = CCPRxH:CCPRxL

TMR2 = PR2

Rev. 30-000134A

5/9/2017

21.4.1 Standard PWM Operation

The standard PWM function described in this section is available and identical for all CCP modules.

The standard PWM mode generates a Pulse-Width Modulation (PWM) signal on the CCPx pin with up to

ten bits of resolution. The period, duty cycle, and resolution are controlled by the following registers:

• Even numbered TxPR registers (T2PR, T4PR, etc)

• Even numbered TxCON registers (T2CON, T4CON, etc)

• 16-bit CCPRx registers

• CCPxCON registers

It is required to have FOSC/4 as the clock input to TxTMR for correct PWM operation. The following figure

shows a simplified block diagram of PWM operation.

PIC18F26/45/46Q10

Capture/Compare/PWM Module

Figure 21-4. Simplified PWM Block Diagram

Rev. 10-000 157C

9/5/201 4

CCPRxH

Duty cycle registers

10-bit Latch(2)

(Not accessible by user)

Comparator

PR2

(1)

TMR2

TMR2 Module

CCPx

CCPx_out To Peripherals

R

TRIS Control

R

S

Q

CCPRxL

set CCPIF

CCPx_pset

ERS logic

PPS

RxyPPS

Note:

1. 8-bit timer is concatenated with two bits generated by FOSC or two bits of the internal prescaler to

create 10-bit time base.

2. The alignment of the 10 bits from the CCPRx register is determined by the CCPxFMT bit.

Important: The corresponding TRIS bit must be cleared to enable the PWM output on the

CCPx pin.

21.4.2 Setup for PWM Operation

The following steps should be taken when configuring the CCP module for standard PWM operation:

1. Use the desired output pin RxyPPS control to select CCPx as the source and disable the CCPx pin

output driver by setting the associated TRIS bit.

2. Load the T2PR register with the PWM period value.

3. Configure the CCP module for the PWM mode by loading the CCPxCON register with the

appropriate values.

4. Load the CCPRx register with the PWM duty cycle value and configure the FMT bit to set the

proper register alignment.

5. Configure and start Timer2:

– Clear the TMR2IF interrupt flag bit of the PIRx register. See Note below.

– Select the timer clock source to be as FOSC/4 using the TxCLKCON register. This is required

for correct operation of the PWM module.

– Configure the T2CKPS bits of the T2CON register with the timer prescale value.

– Enable the timer by setting the T2ON bit.

PIC18F26/45/46Q10

Capture/Compare/PWM Module

6. Enable PWM output pin:

– Wait until the timer overflows and the TMR2IF bit of the PIRx register is set. See Note below.

– Enable the CCPx pin output driver by clearing the associated TRIS bit.

Important: In order to send a complete duty cycle and period on the first PWM

output, the above steps must be included in the setup sequence. If it is not critical to

start with a complete PWM signal on the first output, then step 6 may be ignored.

Related Links

20.9.3 TxCON

21.4.3 Timer2 Timer Resource

The PWM standard mode makes use of the 8-bit Timer2 timer resources to specify the PWM period.

21.4.4 PWM Period

The PWM period is specified by the T2PR register of Timer2. The PWM period can be calculated using

the formula in the equation below.

Figure 21-5. PWM Period

 =2 + 1 • 4 •  •2Pr

where TOSC = 1/FOSC

When T2TMR is equal to T2PR, the following three events occur on the next increment cycle:

• T2TMR is cleared

• The CCPx pin is set. (Exception: If the PWM duty cycle = 0%, the pin will not be set.)

• The PWM duty cycle is transferred from the CCPRx register into a 10-bit buffer.

Important: The Timer postscaler (see "Timer2 Interrupt") is not used in the determination of

the PWM frequency.

Related Links

20.4 Timer2 Interrupt

21.4.5 PWM Duty Cycle

The PWM duty cycle is specified by writing a 10-bit value to the CCPRx register. The alignment of the 10-

bit value is determined by the FMT bit (see Figure 21-6). The CCPRx register can be written to at any

time. However, the duty cycle value is not latched into the 10-bit buffer until after a match between T2PR

and T2TMR.

The equations below are used to calculate the PWM pulse width and the PWM duty cycle ratio.

PIC18F26/45/46Q10

Capture/Compare/PWM Module

Figure 21-6. PWM 10-Bit Alignment

Rev. 10-000 160A

12/9/201 3

7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0

CCPRxH CCPRxL

7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0

CCPRxH CCPRxL

FMT = 0

FMT = 1

7 6 5 4 3 2 1 09 8

10-bit Duty Cycle

Figure 21-7. Pulse Width

 ℎ = :   • •2 Pr 

Figure 21-8. Duty Cycle

 =:  

42 + 1

The CCPRx register is used to double buffer the PWM duty cycle. This double buffering is essential for

glitchless PWM operation.

The 8-bit timer T2TMR register is concatenated with either the 2-bit internal system clock (FOSC), or two

bits of the prescaler, to create the 10-bit time base. The system clock is used if the Timer2 prescaler is set

to 1:1.

When the 10-bit time base matches the CCPRx register, then the CCPx pin is cleared (see Figure 21-4).

21.4.6 PWM Resolution

The resolution determines the number of available duty cycles for a given period. For example, a 10-bit

resolution will result in 1024 discrete duty cycles, whereas an 8-bit resolution will result in 256 discrete

duty cycles.

The maximum PWM resolution is ten bits when T2PR is 255. The resolution is a function of the T2PR

register value as shown below.

Figure 21-9. PWM Resolution

Re =log 4 2 + 1

log 2 

Important: If the pulse-width value is greater than the period, the assigned PWM pin(s) will

remain unchanged.

Table 21-3. Example PWM Frequencies and Resolutions (FOSC = 20 MHz)

PWM Frequency 1.22 kHz 4.88 kHz 19.53 kHz 78.12 kHz 156.3 kHz 208.3 kHz

Timer Prescale 16 4 1 1 1 1

T2PR Value 0xFF 0xFF 0xFF 0x3F 0x1F 0x17

Maximum Resolution (bits) 10 10 10 8 7 6.6

PIC18F26/45/46Q10

Capture/Compare/PWM Module

Table 21-4. Example PWM Frequencies and Resolutions (FOSC = 8 MHz)

PWM Frequency 1.22 kHz 4.90 kHz 19.61 kHz 76.92 kHz 153.85 kHz 200.0 kHz

Timer Prescale 16 4 1 1 1 1

T2PR Value 0x65 0x65 0x65 0x19 0x0C 0x09

Maximum Resolution (bits) 8 8 8 6 5 5

21.4.7 Operation in Sleep Mode

In Sleep mode, the T2TMR register will not increment and the state of the module will not change. If the

CCPx pin is driving a value, it will continue to drive that value. When the device wakes up, T2TMR will

continue from the previous state.

21.4.8 Changes in System Clock Frequency

The PWM frequency is derived from the system clock frequency. Any changes in the system clock

frequency will result in changes to the PWM frequency. See the "Oscillator Module (with Fail-Safe Clock

Monitor)" section for additional details.

Related Links

4. Oscillator Module (with Fail-Safe Clock Monitor)

21.4.9 Effects of Reset

Any Reset will force all ports to Input mode and the CCP registers to their Reset states.

PIC18F26/45/46Q10

Capture/Compare/PWM Module

21.5 Register Summary - CCP Control

Address Name Bit Pos.

0x0FA5 CCPR2

7:0 CCPRL[7:0]

15:8 CCPRH[7:0]

0x0FA7 CCP2CON 7:0 EN OUT FMT MODE[3:0]

0x0FA8 CCP2CAP 7:0 CTS[3:0]

0x0FA9 CCPR1

7:0 CCPRL[7:0]

15:8 CCPRH[7:0]

0x0FAB CCP1CON 7:0 EN OUT FMT MODE[3:0]

0x0FAC CCP1CAP 7:0 CTS[3:0]

0x0FAD CCPTMRS 7:0 P4TSEL[1:0] P3TSEL[1:0] C2TSEL[1:0] C1TSEL[1:0]

21.6 Register Definitions: CCP Control

Long bit name prefixes for the CCP peripherals are shown in the following table. Refer to the “Long Bit

Names” section for more information.

Table 21-5. CCP Long bit name prefixes

Peripheral Bit Name Prefix

CCP1 CCP1

CCP2 CCP2

Related Links

1.4.2.2 Long Bit Names

PIC18F26/45/46Q10

Capture/Compare/PWM Module

21.6.1 CCPxCON

Name: CCPxCON

Address: 0xFAB,0xFA7

CCP Control Register

Bit 7 6 5 4 3 2 1 0

EN OUT FMT MODE[3:0]

Access R/W RO R/W R/W R/W R/W R/W

Reset 0 x 0 0 0 0 0

Bit 7 – EN CCP Module Enable bit

Value Description

1CCP is enabled

0CCP is disabled

Bit 5 – OUT CCP Output Data bit (read-only)

Bit 4 – FMT CCPW (pulse-width) Value Alignment bit

Value Condition Description

xCapture mode Not used

xCompare mode Not used

1PWM mode Left-aligned format

0PWM mode Right-aligned format

Bits 3:0 – MODE[3:0] CCP Mode Select bits

Table 21-6. CCPx Mode Select Bits

MODE Operating Mode Operation Set CCPxIF

11xx PWM PWM Operation Yes

1011 Compare Pulse output; clear TMR1(2) Yes

1010 Pulse output Yes

1001 Clear output(1) Yes

1000 Set output(1) Yes

0111 Capture Every 16th rising edge of CCPx input Yes

0110 Every 4th rising edge of CCPx input Yes

0101 Every rising edge of CCPx input Yes

0100 Every falling edge of CCPx input Yes

0011 Every edge of CCPx input Yes

0010 Compare Toggle output Yes

0001 Toggle output; clear TMR1(2) Yes

0000 Disabled —

PIC18F26/45/46Q10

Capture/Compare/PWM Module

Note:

1. The set and clear operations of the Compare mode are Reset by setting MODE = '0000'.

2. When MODE = '0001' or '1011', then the timer associated with the CCP module is cleared.

TMR1 is the default selection for the CCP module, so it is used for indication purpose only.

PIC18F26/45/46Q10

Capture/Compare/PWM Module

21.6.2 CCPxCAP

Name: CCPxCAP

Address: 0xFAC,0xFA8

Capture Trigger Input Selection Register

Bit 7 6 5 4 3 2 1 0

CTS[3:0]

Access R/W R/W R/W R/W

Reset 0 0 0 0

Bits 3:0 – CTS[3:0] Capture Trigger Input Selection bits

Table 21-7. Capture Trigger Sources

CTS Source

1111 CLC8_out

1110 CLC7_out

1101 CLC6_out

1100 CLC5_out

1011 CLC4_out

1010 CLC3_out

1001 CLC2_out

1000 CLC1_out

0100-0111 Reserved

0011 IOC Interrupt

0010 CMP2_output

0001 CMP1_output

0000 Pin selected by CCPxPPS

PIC18F26/45/46Q10

Capture/Compare/PWM Module

21.6.3 CCPRx

Name: CCPRx

Address: 0xFA9,0xFA5

Capture/Compare/Pulse Width Register

Bit 15 14 13 12 11 10 9 8

CCPRH[7:0]

Access R/W R/W R/W R/W R/W R/W R/W R/W

Reset x x x x x x x x

Bit 7 6 5 4 3 2 1 0

CCPRL[7:0]

Access R/W R/W R/W R/W R/W R/W R/W R/W

Reset x x x x x x x x

Bits 15:8 – CCPRH[7:0]

Capture/Compare/Pulse Width High byte

Value Condition Description

0 to

255

MODE = Capture High byte of 16-bit captured value

0 to

255

MODE = Compare High byte of 16-bit compare value

0,1,2,3 MODE = PWM and FMT=0CCPRH<1:0>=Bits<9:8> of 10-bit Pulse width value

CCPRH<7:2> not used

0 to

255

MODE = PWM and FMT=1Bits<9:2> of 10-bit Pulse width value

Bits 7:0 – CCPRL[7:0]

Capture/Compare/Pulse Width Low byte

Value Condition Description

0 to

255

MODE = Capture Low byte of 16-bit captured value

0 to

255

MODE = Compare Low byte of 16-bit compare value

0 to

255

MODE = PWM and FMT=0Bits<7:0> of 10-bit Pulse width value

0,64,12

8,192

MODE = PWM and FMT=1CCPRL<7:6>=Bits<1:0> of 10-bit Pulse width value

CCPRL<5:0> not used

PIC18F26/45/46Q10

Capture/Compare/PWM Module

21.6.4 CCPTMRS

Name: CCPTMRS

Address: 0xFAD

CCP Timers Control Register

Bit 7 6 5 4 3 2 1 0

P4TSEL[1:0] P3TSEL[1:0] C2TSEL[1:0] C1TSEL[1:0]

Access R/W R/W R/W R/W R/W R/W R/W R/W

Reset 0 1 0 1 0 1 0 1

Bits 4:5, 6:7 – PnTSEL PWMn Timer Selection bits

Value Description

11 PWMn based on Timer6

10 PWMn based on Timer4

01 PWMn based on Timer2

00 Reserved

Bits 0:1, 2:3 – CnTSEL CCPn Timer Selection bits

Value Description

11 CCPn is based off Timer5 in Capture/Compare mode and Timer6 in PWM mode

10 CCPn is based off Timer3 in Capture/Compare mode and Timer4 in PWM mode

01 CCPn is based off Timer1 in Capture/Compare mode and Timer2 in PWM mode

00 Reserved

PIC18F26/45/46Q10

Capture/Compare/PWM Module

22. (PWM) Pulse-Width Modulation

The PWM module generates a Pulse-Width Modulated signal determined by the duty cycle, period, and

resolution that are configured by the following registers:

• TxPR

• TxCON

• PWMxDC

• PWMxCON

Important: The corresponding TRIS bit must be cleared to enable the PWM output on the

PWMx pin.

Each PWM module can select the timer source that controls the module. Each module has an

independent timer selection which can be accessed using the CCPTMRS register. Note that the PWM

mode operation is described with respect to TMR2 in the following sections.

Figure 22-1 shows a simplified block diagram of PWM operation.

Figure 22-2 shows a typical waveform of the PWM signal.

Figure 22-1. Simplified PWM Block Diagram

PWMxDCH

Comparator

TMR2

Comparator

PR2

(1)

R Q

S

Duty Cycle registers PWMxDCL<7:6>

Clear Timer,

PWMx pin and

latch Duty Cycle

PWMx

Note 1: 8-bit timer is concatenated with the two Least Significant bits of 1/FOSC adjusted by the Timer2 prescaler to

create a 10-bit time base.

Latched

(Not visible to user)

Q

Output Polarity (PWMxPOL)

TMR2 Module

0

1

PWMxOUT

to other peripherals

PPS

RxyPPS

Rev. 30-000130A

5/17/2017

PIC18F26/45/46Q10

(PWM) Pulse-Width Modulation

Figure 22-2. PWM Output

Period

Pulse Width

TMR2 = 0

TMR2 =

TMR2 = PR2

PWMxDCH<7:0>:PWMxDCL<7:6>

Rev. 30-000129A

5/17/2017

For a step-by-step procedure on how to set up this module for PWM operation, refer to 22.9 Setup for

PWM Operation using PWMx Output Pins.

22.1 Fundamental Operation

The PWM module produces a 10-bit resolution output. The PWM timer can be selected using the

PxTSEL bits in the CCPTMRS register. The default selection for PWMx is TMR2. Note that the PWM

module operation in the following sections is described with respect to TMR2. Timer2 and T2PR set the

period of the PWM. The PWMxDCL and PWMxDCH registers configure the duty cycle. The period is

common to all PWM modules, whereas the duty cycle is independently controlled.

Important: The Timer2 postscaler is not used in the determination of the PWM frequency. The

postscaler could be used to have a servo update rate at a different frequency than the PWM

output.

All PWM outputs associated with Timer2 are set when T2TMR is cleared. Each PWMx is cleared when

TxTMR is equal to the value specified in the corresponding PWMxDCH (8 MSb) and PWMxDCL<7:6> (2

LSb) registers. When the value is greater than or equal to T2PR, the PWM output is never cleared (100%

duty cycle).

Important: The PWMxDCH and PWMxDCL registers are double-buffered. The buffers are

updated when T2TMR matches T2PR. Care should be taken to update both registers before the

timer match occurs.

22.2 PWM Output Polarity

The output polarity is inverted by setting the POL bit.

22.3 PWM Period

The PWM period is specified by the TxPR register The PWM period can be calculated using the formula

of 22.3 PWM Period. It is required to have FOSC/4 as the selected clock input to the timer for correct

PWM operation.

Figure 22-3. PWM Period

 =2 + 1 • 4 •  •2 Pr

Note: TOSC = 1/FOSC

When T2TMR is equal to T2PR, the following three events occur on the next increment cycle:

PIC18F26/45/46Q10

(PWM) Pulse-Width Modulation

• T2TMR is cleared

• The PWM output is active. (Exception: When the PWM duty cycle = 0%, the PWM output will remain

inactive.)

• The PWMxDCH and PWMxDCL register values are latched into the buffers.

Important: The Timer2 postscaler has no effect on the PWM operation.

22.4 PWM Duty Cycle

The PWM duty cycle is specified by writing a 10-bit value to the PWMxDCH and PWMxDCL register pair.

The PWMxDCH register contains the eight MSbs and the PWMxDCL<7:6>, the two LSbs. The

PWMxDCH and PWMxDCL registers can be written to at any time.

The formulas below are used to calculate the PWM pulse width and the PWM duty cycle ratio.

Figure 22-4. Pulse Width

ℎ = : < 7: 6 > •  •2Pr

Note: TOSC = 1/FOSC

Figure 22-5. Duty Cycle Ratio

 =: < 7:6 >

42 + 1

The 8-bit timer T2TMR register is concatenated with the two Least Significant bits of 1/FOSC, adjusted by

the Timer2 prescaler to create the 10-bit time base. The system clock is used if the Timer2 prescaler is

set to 1:1.

22.5 PWM Resolution

The resolution determines the number of available duty cycles for a given period. For example, a 10-bit

resolution will result in 1024 discrete duty cycles, whereas an 8-bit resolution will result in 256 discrete

duty cycles.

The maximum PWM resolution is ten bits when T2PR is 255. The resolution is a function of the T2PR

register value as shown below.

Figure 22-6. PWM Resolution

Re =log 4 2 + 1

log 2 

Important: If the pulse-width value is greater than the period, the assigned PWM pin(s) will

remain unchanged.

Table 22-1. Example PWM Frequencies and Resolutions (FOSC = 20 MHz)

PWM Frequency 0.31 kHz 4.88 kHz 19.53 kHz 78.12 kHz 156.3 kHz 208.3 kHz

Timer Prescale 64 4 1 1 1 1

PIC18F26/45/46Q10

(PWM) Pulse-Width Modulation

...........continued

PWM Frequency 0.31 kHz 4.88 kHz 19.53 kHz 78.12 kHz 156.3 kHz 208.3 kHz

T2PR Value 0xFF 0xFF 0xFF 0x3F 0x1F 0x17

Maximum Resolution (bits) 10 10 10 8 7 6.6

Table 22-2. Example PWM Frequencies and Resolutions (FOSC = 8 MHz)

PWM Frequency 0.31 kHz 4.90 kHz 19.61 kHz 76.92 kHz 153.85 kHz 200.0 kHz

Timer Prescale 64 4 1 1 1 1

T2PR Value 0x65 0x65 0x65 0x19 0x0C 0x09

Maximum Resolution (bits) 8 8 8 6 5 5

22.6 Operation in Sleep Mode

In Sleep mode, the T2TMR register will not increment and the state of the module will not change. If the

PWMx pin is driving a value, it will continue to drive that value. When the device wakes up, T2TMR will

continue from its previous state.

22.7 Changes in System Clock Frequency

The PWM frequency is derived from the system clock frequency (FOSC). Any changes in the system clock

frequency will result in changes to the PWM frequency.

Related Links

4. Oscillator Module (with Fail-Safe Clock Monitor)

22.8 Effects of Reset

Any Reset will force all ports to Input mode and the PWM registers to their Reset states.

22.9 Setup for PWM Operation using PWMx Output Pins

The following steps should be taken when configuring the module for PWM operation using the PWMx

pins:

1. Disable the PWMx pin output driver(s) by setting the associated TRIS bit(s).

2. Clear the PWMxCON register.

3. Load the T2PR register with the PWM period value.

4. Load the PWMxDCH register and bits <7:6> of the PWMxDCL register with the PWM duty cycle

value.

5. Configure and start Timer2:

– Clear the TMR2IF interrupt flag bit of the PIRx register.(1)

– Select the timer clock source to be as FOSC/4 using the TxCLKCON register. This is required

for correct operation of the PWM module.

– Configure the T2CKPS bits of the T2CON register with the Timer2 prescale value.

PIC18F26/45/46Q10

(PWM) Pulse-Width Modulation

– Enable Timer2 by setting the T2ON bit of the T2CON register.

6. Enable PWM output pin and wait until Timer2 overflows, TMR2IF bit of the PIRx register is set.(2)

7. Enable the PWMx pin output driver(s) by clearing the associated TRIS bit(s) and setting the desired

pin PPS control bits.

8. Configure the PWM module by loading the PWMxCON register with the appropriate values.

Note:

1. In order to send a complete duty cycle and period on the first PWM output, the above steps must

be followed in the order given. If it is not critical to start with a complete PWM signal, then move

Step 8 to replace Step 4.

2. For operation with other peripherals only, disable PWMx pin outputs.

22.9.1 PWMx Pin Configuration

All PWM outputs are multiplexed with the PORT data latch. The user must configure the pins as outputs

by clearing the associated TRIS bits.

22.10 Setup for PWM Operation to Other Device Peripherals

The following steps should be taken when configuring the module for PWM operation to be used by other

device peripherals:

1. Disable the PWMx pin output driver(s) by setting the associated TRIS bit(s).

2. Clear the PWMxCON register.

3. Load the T2PR register with the PWM period value.

4. Load the PWMxDCH register and bits <7:6> of the PWMxDCL register with the PWM duty cycle

value.

5. Configure and start Timer2:

– Clear the TMR2IF interrupt flag bit of the PIRx register.(1)

– Select the timer clock source to be as FOSC/4 using the TxCLKCON register. This is required

for correct operation of the PWM module.

– Configure the T2CKPS bits of the T2CON register with the Timer2 prescale value.

– Enable Timer2 by setting the T2ON bit of the T2CON register.

6. Wait until Timer2 overflows, TMR2IF bit of the PIRx register is set.(1)

7. Configure the PWM module by loading the PWMxCON register with the appropriate values.

Note:

1. In order to send a complete duty cycle and period on the first PWM output, the above steps must

be included in the setup sequence. If it is not critical to start with a complete PWM signal on the first

output, then step 6 may be ignored.

PIC18F26/45/46Q10

(PWM) Pulse-Width Modulation

22.11 Register Summary - Registers Associated with PWM

Address Name Bit Pos.

0x0F9F PWM4DC

7:0 DCL[1:0]

15:8 DCH[7:0]

0x0FA1 PWM4CON 7:0 EN OUT POL

0x0FA2 PWM3DC

7:0 DCL[1:0]

15:8 DCH[7:0]

0x0FA4 PWM3CON 7:0 EN OUT POL

0x0FA5

...

0x0FAC

Reserved

0x0FAD CCPTMRS 7:0 P4TSEL[1:0] P3TSEL[1:0] C2TSEL[1:0] C1TSEL[1:0]

22.12 Register Definitions: PWM Control

Long bit name prefixes for the PWM peripherals are shown in the table below. Refer to the "Long Bit

Names Section" for more information.

Table 22-3. PWM Bit Name Prefixes

Peripheral Bit Name Prefix

PWM3 PWM3

PWM4 PWM4

Related Links

1.4.2.2 Long Bit Names

PIC18F26/45/46Q10

(PWM) Pulse-Width Modulation

22.12.1 PWMxCON

Name: PWMxCON

Address: 0xFA4,0xFA1

PWM Control Register

Bit 7 6 5 4 3 2 1 0

EN OUT POL

Access R/W RO R/W

Reset 0 0 0

Bit 7 – EN PWM Module Enable bit

Value Description

1PWM module is enabled

0PWM module is disabled

Bit 5 – OUT PWM Module Output Level When Bit is Read

Bit 4 – POL PWM Output Polarity Select bit

Value Description

1PWM output is inverted

0PWM output is normal

PIC18F26/45/46Q10

(PWM) Pulse-Width Modulation

22.12.2 CCPTMRS

Name: CCPTMRS

Address: 0xFAD

CCP Timers Control Register

Bit 7 6 5 4 3 2 1 0

P4TSEL[1:0] P3TSEL[1:0] C2TSEL[1:0] C1TSEL[1:0]

Access R/W R/W R/W R/W R/W R/W R/W R/W

Reset 0 1 0 1 0 1 0 1

Bits 7:6 – P4TSEL[1:0] PWM4 Timer Selection bits

Value Description

11 PWM4 based on TMR6

10 PWM4 based on TMR4

01 PWM4 based on TMR2

00 Reserved

Bits 5:4 – P3TSEL[1:0] PWM3 Timer Selection bits

Value Description

11 PWM3 based on TMR6

10 PWM3 based on TMR4

01 PWM3 based on TMR2

00 Reserved

Bits 3:2 – C2TSEL[1:0] CCP2 Timer Selection bits

Value Description

11 CCP2 is based off Timer5 in Capture/Compare mode and Timer6 in PWM mode

10 CCP2 is based off Timer3 in Capture/Compare mode and Timer4 in PWM mode

01 CCP2 is based off Timer1 in Capture/Compare mode and Timer2 in PWM mode

00 Reserved

Bits 1:0 – C1TSEL[1:0] CCP1 Timer Selection bits

Value Description

11 CCP1 is based off Timer5 in Capture/Compare mode and Timer6 in PWM mode

10 CCP1 is based off Timer3 in Capture/Compare mode and Timer4 in PWM mode

01 CCP1 is based off Timer1 in Capture/Compare mode and Timer2 in PWM mode

00 Reserved

PIC18F26/45/46Q10

(PWM) Pulse-Width Modulation

22.12.3 PWMxDC

Name: PWMxDC

Address: 0xFA2,0xF9F

PWM Duty Cycle Register

Bit 15 14 13 12 11 10 9 8

DCH[7:0]

Access

Reset x x x x x x x x

Bit 7 6 5 4 3 2 1 0

DCL[1:0]

Access

Reset x x

Bits 15:8 – DCH[7:0] PWM Duty Cycle Most Significant bits

These bits are the MSbs of the PWM duty cycle.

Reset States: POR/BOR = xxxxxxxx

All Other Resets = uuuuuuuu

Bits 7:6 – DCL[1:0] PWM Duty Cycle Least Significant bits

These bits are the LSbs of the PWM duty cycle.

Reset States: POR/BOR = xx

All Other Resets = uu

PIC18F26/45/46Q10

(PWM) Pulse-Width Modulation

23. (ZCD) Zero-Cross Detection Module

The ZCD module detects when an A/C signal crosses through the ground potential. The actual zero

crossing threshold is the zero crossing reference voltage, ZCPINV, which is typically 0.75V above ground.

The connection to the signal to be detected is through a series current-limiting resistor. The module

applies a current source or sink to the ZCD pin to maintain a constant voltage on the pin, thereby

preventing the pin voltage from forward biasing the ESD protection diodes. When the applied voltage is

greater than the reference voltage, the module sinks current. When the applied voltage is less than the

reference voltage, the module sources current. The current source and sink action keeps the pin voltage

constant over the full range of the applied voltage. The ZCD module is shown in the following simplified

block diagram.

Figure 23-1. Simplified ZCD Block Diagram

Filename: 10-000194B.vsd

Title: ZERO CROSS DETECT BLOCK DIAGRAM

Last Edit: 5/14/2014

First Used: PIC16(L)F1615

Notes:

Rev. 10-000194B

5/14/2014

-

+

Zcpinv

VDD

ZCDxIN

VPULLUP

External

voltage

source

RPULLDOWN

optional

RPULLUP

ZCDxPOL

D Q

ZCDx_output

ZCDxOUT bit

Q1

ZCDxINTP

ZCDxINTN

Interrupt

det

Interrupt

det

Set

ZCDIF

flag

RSERIES

The ZCD module is useful when monitoring an A/C waveform for, but not limited to, the following

purposes:

• A/C period measurement

• Accurate long term time measurement

• Dimmer phase delayed drive

PIC18F26/45/46Q10

(ZCD) Zero-Cross Detection Module

• Low EMI cycle switching

23.1 External Resistor Selection

The ZCD module requires a current-limiting resistor in series with the external voltage source. The

impedance and rating of this resistor depends on the external source peak voltage. Select a resistor

value that will drop all of the peak voltage when the current through the resistor is nominally 300 μA.

Make sure that the ZCD I/O pin internal weak pull-up is disabled so it does not interfere with the current

source and sink.

Figure 23-2. External Resistor

 =

3 × 104

Figure 23-3. External Voltage Source

VPEAK

ZCPINV

VMAXPEAK

VMINPEAK

Rev. 30-000001A

7/18/2017

23.2 ZCD Logic Output

The ZCD module includes a Status bit, which can be read to determine whether the current source or

sink is active. The OUT bit is set when the current sink is active, and cleared when the current source is

active. The OUT bit is affected by the polarity bit.

The OUT signal can also be used as input to other modules. This is controlled by the registers of the

corresponding module. OUT can be used as follows:

• Gate source for TMR1/3/5

• Clock source for TMR2/4/6

• Reset source for TMR2/4/6

23.3 ZCD Logic Polarity

The POL bit inverts the OUT bit relative to the current source and sink output. When the POL bit is set, a

OUT high indicates that the current source is active, and a low output indicates that the current sink is

active.

The POL bit affects the ZCD interrupts.

23.4 ZCD Interrupts

An interrupt will be generated upon a change in the ZCD logic output when the appropriate interrupt

enables are set. A rising edge detector and a falling edge detector are present in the ZCD for this

purpose.

PIC18F26/45/46Q10

(ZCD) Zero-Cross Detection Module

The ZCDIF bit of the PIRx register will be set when either edge detector is triggered and its associated

enable bit is set. The INTP enables rising edge interrupts and the INTN bit enables falling edge interrupts.

Priority of the interrupt can be changed if the IPEN bit of the INTCON register is set. The ZCD interrupt

can be made high or low priority by setting or clearing the ZCDIP bit of the IPRx register.

To fully enable the interrupt, the following bits must be set:

• ZCDIE bit of the PIEx register

• INTP bit for rising edge detection

• INTN bit for falling edge detection

• PEIE and GIE bits of the INTCON register

Changing the POL bit will cause an interrupt, regardless of the level of the SEN bit.

The ZCDIF bit of the PIRx register must be cleared in software as part of the interrupt service. If another

edge is detected while this flag is being cleared, the flag will still be set at the end of the sequence.

23.5 Correction for ZCPINV Offset

The actual voltage at which the ZCD switches is the reference voltage at the non-inverting input of the

ZCD op amp. For external voltage source waveforms other than square waves, this voltage offset from

zero causes the zero-cross event to occur either too early or too late.

23.5.1 Correction by AC Coupling

When the external voltage source is sinusoidal, the effects of the ZCPINV offset can be eliminated by

isolating the external voltage source from the ZCD pin with a capacitor, in addition to the voltage reducing

resistor. The capacitor will cause a phase shift resulting in the ZCD output switch in advance of the actual

zero crossing event. The phase shift will be the same for both rising and falling zero crossings, which can

be compensated for by either delaying the CPU response to the ZCD switch by a timer or other means, or

selecting a capacitor value large enough that the phase shift is negligible.

To determine the series resistor and capacitor values for this configuration, start by computing the

impedance, Z, to obtain a peak current of 300 μA. Next, arbitrarily select a suitably large non-polar

capacitor and compute its reactance, Xc, at the external voltage source frequency. Finally, compute the

series resistor, capacitor peak voltage, and phase shift by the formulas shown below.

When this technique is used and the input signal is not present, the ZCD will tend to oscillate. To avoid

this oscillation, connect the ZCD pin to VDD or GND with a high-impedance resistor such as 200K.

Figure 23-4. R-C Equations

VPEAK = external voltage source peak voltage

f = external voltage source frequency

C = series capacitor

R = series resistor

VC = Peak capacitor voltage

Φ = Capacitor induced zero crossing phase advance in radians

TΦ = Time ZC event occurs before actual zero crossing

=

3 × 104

PIC18F26/45/46Q10

(ZCD) Zero-Cross Detection Module

=1

2

=2 2

=3 × 104

Φ = tan 1



Φ=Φ

2

Figure 23-5. R-C Calcuation Example

 = 120

 = × 2 = 169.7

= 60 

= 0.1 

=

3 × 104=169.7

3 × 104= 565.7 Ω

=1

2 =1

2× 60 × 107= 26.53 Ω

=2 2= 565.1 Ω

= 560 Ω

=2+2= 560.6 Ω

 =



= 302.7 × 106

=× = 8.0 

Φ = tan 1

= 0.047

Φ=Φ

2 = 125.6

23.5.2 Correction By Offset Current

When the waveform is varying relative to VSS, then the zero cross is detected too early as the waveform

falls and too late as the waveform rises. When the waveform is varying relative to VDD, then the zero

cross is detected too late as the waveform rises and too early as the waveform falls. The actual offset

time can be determined for sinusoidal waveforms with the corresponding equations shown below.

Figure 23-6. ZCD Event Offset

When External Voltage source is relative to VSS

PIC18F26/45/46Q10

(ZCD) Zero-Cross Detection Module

 =

sin1



2

When External Voltage source is relative to VDD

 =

sin1  



2

This offset time can be compensated for by adding a pull-up or pull-down biasing resistor to the ZCD pin.

A pull-up resistor is used when the external voltage source is varying relative to VSS. A pull-down resistor

is used when the voltage is varying relative to VDD. The resistor adds a bias to the ZCD pin so that the

target external voltage source must go to zero to pull the pin voltage to the ZCPINV switching voltage. The

pull-up or pull-down value can be determined with the equations shown below.

Figure 23-7. ZCD Pull-up/Pull-down Resistor

When External Voltage source is relative to VSS

 =   



When External Voltage source is relative to VDD

 = 

  

23.6 Handling VPEAK Variations

If the peak amplitude of the external voltage is expected to vary, the series resistor must be selected to

keep the ZCD current source and sink below the design maximum range of ± 600 μA and above a

reasonable minimum range. A general rule of thumb is that the maximum peak voltage can be no more

than six times the minimum peak voltage. To ensure that the maximum current does not exceed ± 600 μA

and the minimum is at least ± 100 μA, compute the series resistance as shown in Figure 23-8. The

compensating pull-up for this series resistance can be determined with the equations shown in Figure

23-7 because the pull-up value is independent from the peak voltage.

Figure 23-8. Series R for V range

 =_ +_

7 × 104

23.7 Operation During Sleep

The ZCD current sources and interrupts are unaffected by Sleep.

PIC18F26/45/46Q10

(ZCD) Zero-Cross Detection Module

23.8 Effects of a Reset

The ZCD circuit can be configured to default to the Active or Inactive state on Power-on Reset (POR).

When the ZCD Configuration bit is cleared, the ZCD circuit will be active at POR. When the ZCD

Configuration bit is set, the SEN bit must be set to enable the ZCD module.

23.9 Disabling the ZCD Module

The ZCD module can be disabled in two ways:

1. The ZCD Configuration bit disables the ZCD module when set. When this is the case then the ZCD

module will be enabled by setting the SEN bit. When the ZCD bit is clear, the ZCD is always

enabled and the SEN bit has no effect.

2. The ZCD can also be disabled using the ZCDMD bit of the PMDx register. This is subject to the

status of the ZCD bit.

PIC18F26/45/46Q10

(ZCD) Zero-Cross Detection Module

23.10 Register Summary: ZCD Control

Address Name Bit Pos.

0x0F2D ZCDCON 7:0 SEN OUT POL INTP INTN

23.11 Register Definitions: ZCD Control

Long bit name prefixes for the ZCD peripherals are shown in the table below. Refer to the "Long Bit

Names Section" for more information.

Table 23-1. ZCD Long Bit Name Prefixes

Peripheral Bit Name Prefix

ZCD ZCD

Related Links

1.4.2.2 Long Bit Names

PIC18F26/45/46Q10

(ZCD) Zero-Cross Detection Module

23.11.1 ZCDCON

Name: ZCDCON

Address: 0xF2D

Zero-Cross Detect Control Register

Bit 7 6 5 4 3 2 1 0

SEN OUT POL INTP INTN

Access R/W RO R/W R/W R/W

Reset 0 x 0 0 0

Bit 7 – SEN Zero-Cross Detect Software Enable bit

This bit is ignored when ZCD fuse is cleared.

Value Condition Description

XZCD Config fuse = 0Zero-cross detect is always enabled. This bit is ignored.

1ZCD Config fuse = 1Zero-cross detect is enabled. ZCD pin is forced to output to source

and sink current.

0ZCD Config fuse = 1Zero-cross detect is disabled. ZCD pin operates according to PPS and

TRIS controls.

Bit 5 – OUT Zero-Cross Detect Data Output bit

Value Condition Description

1POL = 0ZCD pin is sinking current

0POL = 0ZCD pin is sourcing current

1POL = 1ZCD pin is sourcing current

0POL = 1ZCD pin is sinking current

Bit 4 – POL Zero-Cross Detect Polarity bit

Value Description

1ZCD logic output is inverted

0ZCD logic output is not inverted

Bit 1 – INTP Zero-Cross Detect Positive-Going Edge Interrupt Enable bit

Value Description

1ZCDIF bit is set on low-to-high ZCD_output transition

0ZCDIF bit is unaffected by low-to-high ZCD_output transition

Bit 0 – INTN Zero-Cross Detect Negative-Going Edge Interrupt Enable bit

Value Description

1ZCDIF bit is set on high-to-low ZCD_output transition

0ZCDIF bit is unaffected by high-to-low ZCD_output transition

PIC18F26/45/46Q10

(ZCD) Zero-Cross Detection Module

24. (CWG) Complementary Waveform Generator Module

The Complementary Waveform Generator (CWG) produces half-bridge, full-bridge, and steering of PWM

waveforms. It is backwards compatible with previous CCP functions. The PIC18F26/45/46Q10 family has

1 instance(s) of the CWG module.

The CWG has the following features:

• Six Operating modes:

– Synchronous Steering mode

– Asynchronous Steering mode

– Full-Bridge mode, Forward

– Full-Bridge mode, Reverse

– Half-Bridge mode

– Push-Pull mode

• Output Polarity Control

• Output Steering

• Independent 6-Bit Rising and Falling Event Dead-Band Timers:

– Clocked dead band

– Independent rising and falling dead-band enables

• Auto-Shutdown Control With:

– Selectable shutdown sources

– Auto-restart option

– Auto-shutdown pin override control

24.1 Fundamental Operation

The CWG generates two output waveforms from the selected input source.

The off-to-on transition of each output can be delayed from the on-to-off transition of the other output,

thereby, creating a time delay immediately where neither output is driven. This is referred to as dead time

and is covered in 24.7 Dead-Band Control.

It may be necessary to guard against the possibility of circuit faults or a feedback event arriving too late or

not at all. In this case, the active drive must be terminated before the Fault condition causes damage.

This is referred to as auto-shutdown and is covered in 24.11 Auto-Shutdown.

24.2 Operating Modes

The CWG module can operate in six different modes, as specified by the MODE bits:

• Half-Bridge mode

• Push-Pull mode

• Asynchronous Steering mode

• Synchronous Steering mode

• Full-Bridge mode, Forward

• Full-Bridge mode, Reverse

PIC18F26/45/46Q10

(CWG) Complementary Waveform Generator Modul...

All modes accept a single pulse data input, and provide up to four outputs as described in the following

sections.

All modes include auto-shutdown control as described in 24.11 Auto-Shutdown

Important: Except as noted for Full-Bridge mode (24.2.3 Full-Bridge Modes), mode changes

should only be performed while EN = 0.

24.2.1 Half-Bridge Mode

In Half-Bridge mode, two output signals are generated as true and inverted versions of the input as

illustrated in Figure 24-1. A non-overlap (dead-band) time is inserted between the two outputs to prevent

shoot-through current in various power supply applications. Dead-band control is described in 24.7

Dead-Band Control. The output steering feature cannot be used in this mode. A basic block diagram of

this mode is shown in Figure 24-2.

The unused outputs CWGxC and CWGxD drive similar signals, with polarity independently controlled by

the POLC and POLD bits, respectively.

Figure 24-1. CWG Half-Bridge Mode Operation

Rising Event D

Falling Event Dead Band

Rising Event Dead Band

Falling Event Dead Band

CWGx_clock

CWGxA

CWGxB

CWGx_data

CWGxC

CWGxD

Rev. 30-000097A

4/14/2017

Note: CWGx_rising_src = CCP1_out, CWGx_falling_src = ~CCP1_out

PIC18F26/45/46Q10

(CWG) Complementary Waveform Generator Modul...

Figure 24-2. Simplified CWG Block Diagram (Half-Bridge Mode, MODE<2:0> = 100)

Filename: 10-000209D.vsd

Title: SIMPLIFIED CWG BLOCK DIAGRAM (HALF-BRIDGE MODE)

Last Edit: 2/2/2016

First Used: PIC18(L)F6xK40

Notes:

Rev. 10-000209D

2/2/2016

1

0

1

0

1

0

1

0

00

11

10

01

00

11

10

01

00

11

10

01

00

11

10

01

LSAC<1:0>

LSBD<1:0>

LSAC<1:0>

LSBD<1:0>

CWG Clock clock

data in data out

clock

data in data out

CWG Data Input

E

DQ

REN

SHUTDOWN = 0

S

R

Q

POLA

POLB

POLC

POLD

CWG

Data

FREEZE D Q

CWG Data

CWGxD

CWGxC

CWGxB

CWGxA

‘1’

‘0’

‘1’

‘0’

High-Z

Rising Dead-Band Block

Falling Dead-Band Block

CWG Data A

CWG Data B

EN

SHUTDOWN

CWG Data

Auto-shutdown source

(CWGxAS1 register)

PIC18F26/45/46Q10

(CWG) Complementary Waveform Generator Modul...

24.2.2 Push-Pull Mode

In Push-Pull mode, two output signals are generated, alternating copies of the input as illustrated in

Figure 24-3. This alternation creates the push-pull effect required for driving some transformer-based

power supply designs. Steering modes are not used in Push-Pull mode. A basic block diagram for the

Push-Pull mode is shown in Figure 24-4.

The push-pull sequencer is reset whenever EN = 0 or if an auto-shutdown event occurs. The sequencer

is clocked by the first input pulse, and the first output appears on CWG1A.

The unused outputs CWGxC and CWGxD drive copies of CWGxA and CWGxB, respectively, but with

polarity controlled by the POLC and POLD bits of the CWGxCON1 register, respectively.

Figure 24-3. CWG Push-Pull Mode Operation

CWGx

clock

CWGxA

Input

source

CWGxB

Rev. 30-000098A

4/14/2017

PIC18F26/45/46Q10

(CWG) Complementary Waveform Generator Modul...

Figure 24-4. Simplified CWG Block Diagram (Push-Pull Mode, MODE<2:0> = 101)

Filename: 10-000210D.vsd

Title: SIMPLIFIED CWG BLOCK DIAGRAM (PUSH-PULL MODE)

Last Edit: 2/2/2016

First Used: PIC18(L)F6xK40

Notes:

Rev. 10-000210D

2/2/2016

1

0

1

0

1

0

1

0

00

11

10

01

00

11

10

01

00

11

10

01

00

11

10

01

LSAC<1:0>

LSBD<1:0>

LSAC<1:0>

LSBD<1:0>

CWG Data

CWG Data Input

E

DQ

POLA

POLB

POLC

POLD

CWG

Data

FREEZE D Q

CWG Data

CWGxD

CWGxC

CWGxB

CWGxA

‘1’

‘0’

‘1’

‘0’

High-Z

D Q

Q

CWG Data A

CWG Data B

EN

SHUTDOWN

REN

SHUTDOWN = 0

S

R

Q

Auto-shutdown source

(CWGxAS1 register)

PIC18F26/45/46Q10

(CWG) Complementary Waveform Generator Modul...

24.2.3 Full-Bridge Modes

In Forward and Reverse Full-Bridge modes, three outputs drive static values while the fourth is

modulated by the input data signal. The mode selection may be toggled between forward and reverse by

toggling the MODE<0> bit of the CWGxCON0 while keeping MODE<2:1> static, without disabling the

CWG module. When connected, as shown in Figure 24-5, the outputs are appropriate for a full-bridge

motor driver. Each CWG output signal has independent polarity control, so the circuit can be adapted to

high-active and low-active drivers. A simplified block diagram for the Full-Bridge modes is shown in

Figure 24-6.

Figure 24-5. Example of Full-Bridge Application

Filename: 10-000263A.vsd

Title: Example of Full-Bridge Application

Last Edit: 12/8/2015

First Used: PIC18(L)F2x/4xK40

Note:

Rev. 10-000263A

12/8/2015

CWGxA

CWGxB

CWGxC

CWGxD

FET

Driver

FET

Driver

FET

Driver

FET

Driver

VDD

QA QC

QB QD

LOAD

PIC18F26/45/46Q10

(CWG) Complementary Waveform Generator Modul...

Figure 24-6. Simplified CWG Block Diagram (Forward and Reverse Full-Bridge Modes)

Filename: 10-000212D.vsd

Title: SIMPLIFIED CWG BLOCK DIAGRAM (FULL-BRIDGE MODES)

Last Edit: 2/2/2016

First Used: PIC18(L)F6xK40

Notes:

Rev. 10-000212D

2/2/2016

1

0

1

0

1

0

1

0

00

11

10

01

00

11

10

01

00

11

10

01

00

11

10

01

LSAC<1:0>

LSBD<1:0>

LSAC<1:0>

LSBD<1:0>

CWG Clock clock

signal in

signal out

clock

signal insignal out

CWG Data Input

E

DQ

POLA

POLB

POLC

POLD

CWG Data

FREEZE D Q

CWG Data

CWGxD

CWGxC

CWGxB

CWGxA

‘1’

‘0’

‘1’

‘0’

High-Z

Rising Dead-Band Block

Falling Dead-Band Block

CWG Data A

CWG Data B

EN

SHUTDOWN

MODE<2:0> = 010: Forward

MODE<2:0> = 011: Reverse

CWG Clock

MODE<2:0>

CWG

Data

cwg data

CWG Data C

CWG Data D

D Q

Q

CWG

Data

REN

SHUTDOWN = 0

S

R

Q

Auto-shutdown source

(CWGxAS1 register)

PIC18F26/45/46Q10

(CWG) Complementary Waveform Generator Modul...

In Forward Full-Bridge mode (MODE = 010), CWGxA is driven to its Active state, CWGxB and CWGxC

are driven to their Inactive state, and CWGxD is modulated by the input signal, as shown in Figure 24-7.

In Reverse Full-Bridge mode (MODE = 011), CWGxC is driven to its Active state, CWGxA and CWGxD

are driven to their Inactive states, and CWGxB is modulated by the input signal, as shown in Figure 24-7.

In Full-Bridge mode, the dead-band period is used when there is a switch from forward to reverse or vice

versa. This dead-band control is described in 24.7 Dead-Band Control, with additional details in 24.8

Rising Edge and Reverse Dead Band and 24.9 Falling Edge and Forward Dead Band. Steering modes

are not used with either of the Full-Bridge modes. The mode selection may be toggled between forward

and reverse toggling the MODE<0> bit of the CWGxCON0 while keeping MODE<2:1> static, without

disabling the CWG module.

Figure 24-7. Example of Full-Bridge Output

CWGxA(2)

CWGxB(2)

CWGxC(2)

CWGxD(2)

Period

Pulse Width

(1) (1)

Forward

Mode

Pulse Width

Period

Reverse

Mode

CWGxA(2)

CWGxB(2)

CWGxC(2)

CWGxD(2)

(1) (1)

Rev. 30-000099A

4/14/2017

Note:

1. A rising CWG data input creates a rising event on the modulated output.

2. Output signals shown as active-high; all POLy bits are clear.

24.2.3.1 Direction Change in Full-Bridge Mode

In Full-Bridge mode, changing MODE controls the forward/reverse direction. Direction changes occur on

the next rising edge of the modulated input.

PIC18F26/45/46Q10

(CWG) Complementary Waveform Generator Modul...

A direction change is initiated in software by changing the MODE bits. The sequence is illustrated in

Figure 24-8.

• The associated active output CWGxA and the inactive output CWGxC are switched to drive in the

opposite direction.

• The previously modulated output CWGxD is switched to the Inactive state, and the previously

inactive output CWGxB begins to modulate.

• CWG modulation resumes after the direction-switch dead band has elapsed.

24.2.3.2 Dead-Band Delay in Full-Bridge Mode

Dead-band delay is important when either of the following conditions is true:

1. The direction of the CWG output changes when the duty cycle of the data input is at or near 100%,

or

2. The turn-off time of the power switch, including the power device and driver circuit, is greater than

the turn-on time.

The dead-band delay is inserted only when changing directions, and only the modulated output is

affected. The statically-configured outputs (CWGxA and CWGxC) are not afforded dead band, and switch

essentially simultaneously.

The following figure shows an example of the CWG outputs changing directions from forward to reverse,

at near 100% duty cycle. In this example, at time t1, the output of CWGxA and CWGxD become inactive,

while output CWGxC becomes active. Since the turn-off time of the power devices is longer than the turn-

on time, a shoot-through current will flow through power devices QC and QD for the duration of ‘t’. The

same phenomenon will occur to power devices QA and QB for the CWG direction change from reverse to

forward.

When changing the CWG direction at high duty cycle is required for an application, two possible solutions

for eliminating the shoot-through current are:

1. Reduce the CWG duty cycle for one period before changing directions.

2. Use switch drivers that can drive the switches off faster than they can drive them on.

PIC18F26/45/46Q10

(CWG) Complementary Waveform Generator Modul...

Figure 24-8. Example of PWM Direction Change at Near 100% Duty Cycle

Forward Period Reverse Period

t1

Pulse Width

T

ON

TOFF

T = TOFF - TON

CWGxA

External Switch C

External Switch D

Potential Shoot-

Through Current

CWGxB

CWGxD

CWGxC

Rev. 30-000100A

4/14/2017

24.2.4 Steering Modes

In both Synchronous and Asynchronous Steering modes, the modulated input signal can be steered to

any combination of four CWG outputs. A fixed-value will be presented on all the outputs not used for the

PWM output. Each output has independent polarity, steering, and shutdown options. Dead-band control is

not used in either steering mode.

PIC18F26/45/46Q10

(CWG) Complementary Waveform Generator Modul...

Figure 24-9. Simplified CWG Block Diagram (Output Steering Modes)

Filename: 10-000211D.vsd

Title: SIMPLIFIED CWG BLO CK DIA GR AM (OU TP UT STEERING MODES)

Last Edit: 5/30/2017

First Used: PIC18(L)F6xK40

Notes:

Rev. 10-000211D

5/30/2017

1

0

1

0

1

0

1

0

00

11

10

01

00

11

10

01

00

11

10

01

00

11

10

01

LSAC<1:0>

LSBD<1:0>

LSAC<1:0>

LSBD<1:0>

CWG Data

Input

E

DQ

POLA

POLB

POLC

POLD

CWG

Data

FREEZE DQ

CWGxD

CWGxC

CWGxB

CWGxA

‘1’

‘0’

‘1’

‘0’

High-Z

1

0

OVRD

STRD

1

0

OVRC

STRC

1

0

OVRB

STRB

1

0

OVRA

STRA

CWG Data

SHUTDOWN

CWG Data D

CWG Data C

CWG Data B

CWG Data A

EN

MODE<2:0> = 000: Asynchronous

MODE<2:0> = 001: Synchronous

REN

SHUTDOWN = 0

S

R

Q

Auto-shutdown source

(CWGxAS1 register)

PIC18F26/45/46Q10

(CWG) Complementary Waveform Generator Modul...

For example, when STRA = 0 then the corresponding pin is held at the level defined by OVRA. When

STRA = 1, then the pin is driven by the modulated input signal.

The POLy bits control the signal polarity only when STRy = 1.

The CWG auto-shutdown operation also applies in Steering modes as described in 24.11 Auto-

Shutdown”. An auto-shutdown event will only affect pins that have STRy = 1.

24.2.4.1 Synchronous Steering Mode

In Synchronous Steering mode (MODE=001), changes to steering selection registers take effect on the

next rising edge of the modulated data input (see figure below). In Synchronous Steering mode, the

output will always produce a complete waveform.

Important: Only the STRx bits are synchronized; the OVRx bits are not synchronized.

Figure 24-10. Example of Synchronous Steering (MODE = 001)

CWGx

clock

CWGxA

Input

source

CWGxB

Rev. 30-000101A

4/14/2017

24.2.4.2 Asynchronous Steering Mode

In Asynchronous mode (MODE = 000), steering takes effect at the end of the instruction cycle that writes

to STRx. In Asynchronous Steering mode, the output signal may be an incomplete waveform (see figure

below). This operation may be useful when the user firmware needs to immediately remove a signal from

the output pin.

Figure 24-11. Example of Asynchronous Steering (MODE = 000)

CWGx

INPUT

STRA

End of Instruction Cycle End of Instruction Cycle

CWGxA

CWGxA Follows CWGx data input

Rev. 30-000102A

4/14/2017

PIC18F26/45/46Q10

(CWG) Complementary Waveform Generator Modul...

24.3 Start-up Considerations

The application hardware must use the proper external pull-up and/or pull-down resistors on the CWG

output pins. This is required because all I/O pins are forced to high-impedance at Reset.

The polarity control bits (POLy) allow the user to choose whether the output signals are active-high or

active-low.

24.4 Clock Source

The clock source is used to drive the dead-band timing circuits. The CWG module allows the following

clock sources to be selected:

• FOSC (system clock)

• HFINTOSC

When the HFINTOSC is selected, the HFINTOSC will be kept running during Sleep. Therefore, CWG

modes requiring dead band can operate in Sleep, provided that the CWG data input is also active during

Sleep. The clock sources are selected using the CS bit. The system clock FOSC, is disabled in Sleep and

thus dead-band control cannot be used.

24.5 Selectable Input Sources

The CWG generates the output waveforms from the input sources which are selected with the ISM bits as

shown below.

Table 24-1. CWG Data Input Sources

ISM Data Source

1111 CLC8_out

1110 CLC7_out

1101 CLC6_out

1100 CLC5_out

1011 CLC4_out

1010 CLC3_out

1001 CLC2_out

1000 CLC1_out

0111 DSM_out

0110 CMP2_out

0101 CMP1_out

0100 PWM4_out

0011 PWM3_out

0010 CCP2_out

PIC18F26/45/46Q10

(CWG) Complementary Waveform Generator Modul...

...........continued

ISM Data Source

0001 CCP1_out

0000 Pin selected by CWGxPPS

24.6 Output Control

24.6.1 CWG Outputs

Each CWG output can be routed to a Peripheral Pin Select (PPS) output via the RxyPPS register.

Related Links

17. (PPS) Peripheral Pin Select Module

24.6.2 Polarity Control

The polarity of each CWG output can be selected independently. When the output polarity bit is set, the

corresponding output is active-high. Clearing the output polarity bit configures the corresponding output

as active-low. However, polarity does not affect the override levels. Output polarity is selected with the

POLy bits. Auto-shutdown and steering options are unaffected by polarity.

24.7 Dead-Band Control

The dead-band control provides non-overlapping PWM signals to prevent shoot-through current in PWM

switches. Dead-band operation is employed for Half-Bridge and Full-Bridge modes. The CWG contains

two 6-bit dead-band counters. One is used for the rising edge of the input source control in Half-Bridge

mode or for reverse dead-band Full-Bridge mode. The other is used for the falling edge of the input

source control in Half-Bridge mode or for forward dead band in Full-Bridge mode.

Dead band is timed by counting CWG clock periods from zero up to the value in the rising or falling dead-

band counter registers.

24.7.1 Dead-Band Functionality in Half-Bridge mode

In Half-Bridge mode, the dead-band counters dictate the delay between the falling edge of the normal

output and the rising edge of the inverted output. This can be seen in Figure 24-1.

24.7.2 Dead-Band Functionality in Full-Bridge mode

In Full-Bridge mode, the dead-band counters are used when undergoing a direction change. The

MODE<0> bit can be set or cleared while the CWG is running, allowing for changes from Forward to

Reverse mode. The CWGxA and CWGxC signals will change immediately upon the first rising input edge

following a direction change, but the modulated signals (CWGxB or CWGxD, depending on the direction

of the change) will experience a delay dictated by the dead-band counters.

24.8 Rising Edge and Reverse Dead Band

In Half-Bridge mode, the rising edge dead band delays the turn-on of the CWGxA output after the rising

edge of the CWG data input. In Full-Bridge mode, the reverse dead-band delay is only inserted when

changing directions from Forward mode to Reverse mode, and only the modulated output CWGxB is

affected.

PIC18F26/45/46Q10

(CWG) Complementary Waveform Generator Modul...

The 24.15.8 CWGxDBR register determines the duration of the dead-band interval on the rising edge of

the input source signal. This duration is from 0 to 64 periods of the CWG clock.

Dead band is always initiated on the edge of the input source signal. A count of zero indicates that no

dead band is present.

If the input source signal reverses polarity before the dead-band count is completed, then no signal will

be seen on the respective output.

The CWGxDBR register value is double-buffered. When EN = 0, the buffer is loaded when CWGxDBR is

written. When EN = 1, then the buffer will be loaded at the rising edge following the first falling edge of the

data input, after the LD bit is set. Refer to the following figure for an example.

Figure 24-12. Dead-Band Operation, CWGxDBR = 0x01, CWGxDBF = 0x02

Input Source

CWGxA

CWGxB

cwg_clock

Rev. 30-000103A

4/14/2017

24.9 Falling Edge and Forward Dead Band

In Half-Bridge mode, the falling edge dead band delays the turn-on of the CWGxB output at the falling

edge of the CWG data input. In Full-Bridge mode, the forward dead-band delay is only inserted when

changing directions from Reverse mode to Forward mode, and only the modulated output CWGxD is

affected.

The 24.15.9 CWGxDBF register determines the duration of the dead-band interval on the falling edge of

the input source signal. This duration is from zero to 64 periods of CWG clock.

Dead-band delay is always initiated on the edge of the input source signal. A count of zero indicates that

no dead band is present.

If the input source signal reverses polarity before the dead-band count is completed, then no signal will

be seen on the respective output.

The CWGxDBF register value is double-buffered. When EN = 0, the buffer is loaded when CWGxDBF is

written. When EN = 1, then the buffer will be loaded at the rising edge following the first falling edge of the

data input after the LD is set. Refer to the following figure for an example.

Figure 24-13. Dead-Band Operation, CWGxDBR = 0x03, CWGxDBF = 0x06, Source Shorter Than

Dead Band

source shorter than dead band

Input Source

CWGxA

CWGxB

cwg_clock

Rev. 30-000104A

4/14/2017

PIC18F26/45/46Q10

(CWG) Complementary Waveform Generator Modul...

24.10 Dead-Band Jitter

When the rising and falling edges of the input source are asynchronous to the CWG clock, it creates jitter

in the dead-band time delay. The maximum jitter is equal to one CWG clock period. Refer to the

equations below for more details.

Figure 24-14. Dead-Band Delay Time Calculation

  _ =1

_

• < 5:0 >  _ =1

_

• < 5: 0 > + 1

 =  _    _ =1

_

  _ =  _ +

Figure 24-15. Dead-Band Delay Example Calculation

 < 5:0 > = 00= 10

_ = 8 

 =1

8 = 125

  _ = 125 • 10 = 125

  _ = 1.25 + 0.125  = 1.37

24.11 Auto-Shutdown

Auto-shutdown is a method to immediately override the CWG output levels with specific overrides that

allow for safe shutdown of the circuit. The shutdown state can be either cleared automatically or held until

cleared by software. The auto-shutdown circuit is illustrated in the following figure.

Figure 24-16. CWG Shutdown Block Diagram

Filename: 10-000172C.vsd

Title: CWG SHUTDOWN BLOCK DIAGRAM

Last Edit: 8/7/2015

First Used: PIC16(L)F1614/5/8/9 LECW

Notes:

Rev. 10-000172C

8/7/2015

S

R

Q

Write ‘1’ to

SHUTDOWN bit

AS0E

C1OUT_sync

C2OUT_sync

TMR2_postscaled

TMR4_postscaled

TMR6_postscaled

REN

Write ‘0’ to

SHUTDOWN bit

SHUTDOWN

FREEZE D

CK

Q

S

CWG_data

CWG_shutdown

PPS

CWGxINPPS

AS4E

AS5E

AS1E

AS2E

AS3E

24.11.1 Shutdown

The shutdown state can be entered by either of the following two methods:

• Software Generated

• External Input

24.11.1.1 Software Generated Shutdown

Setting the SHUTDOWN bit will force the CWG into the shutdown state.

When the auto-restart is disabled, the shutdown state will persist as long as the SHUTDOWN bit is set.

PIC18F26/45/46Q10

(CWG) Complementary Waveform Generator Modul...

When auto-restart is enabled, the SHUTDOWN bit will clear automatically and resume operation on the

next rising edge event. The SHUTDOWN bit indicates when a shutdown condition exists. The bit may be

set or cleared in software or by hardware.

24.11.1.2 External Input Source

External shutdown inputs provide the fastest way to safely suspend CWG operation in the event of a

Fault condition. When any of the selected shutdown inputs goes active, the CWG outputs will immediately

go to the selected override levels without software delay. The override levels are selected by the LSBD

and LSAC bits. Several input sources can be selected to cause a shutdown condition. All input sources

are active-low. The shutdown input sources are individually enabled by the ASyE bits as shown in the

following table:

Table 24-2. Shutdown Sources

ASyE Source

AS7E CLC6_out (low causes shutdown)

AS6E CLC2_out (low causes shutdown)

AS5E CMP2_out (low causes shutdown)

AS4E CMP1_out (low causes shutdown)

AS3E TMR6_postscaled (high causes shutdown)

AS2E TMR4_postscaled (high causes shutdown)

AS1E TMR2_postscaled (high causes shutdown)

AS0E Pin selected by CWGxPPS (low causes shutdown)

Important: Shutdown inputs are level sensitive, not edge sensitive. The shutdown state

cannot be cleared, except by disabling auto-shutdown, as long as the shutdown input level

persists.

24.11.1.3 Pin Override Levels

The levels driven to the CWG outputs during an auto-shutdown event are controlled by the LSBD and

LSAC bits. The LSBD bits control CWGxB/D output levels, while the LSAC bits control the CWGxA/C

output levels.

24.11.1.4 Auto-Shutdown Interrupts

When an auto-shutdown event occurs, either by software or hardware setting SHUTDOWN, the CWGxIF

flag bit of the PIRx register is set.

Related Links

14.13.9 PIR7

24.11.2 Auto-Shutdown Restart

After an auto-shutdown event has occurred, there are two ways to resume operation:

• Software controlled

• Auto-restart

PIC18F26/45/46Q10

(CWG) Complementary Waveform Generator Modul...

In either case, the shutdown source must be cleared before the restart can take place. That is, either the

shutdown condition must be removed, or the corresponding ASyE bit must be cleared.

24.11.2.1 Software-Controlled Restart

When the REN bit is clear (REN = 0), the CWG module must be restarted after an auto-shutdown event

through software.

Once all auto-shutdown sources are removed, the software must clear SHUTDOWN. Once SHUTDOWN

is cleared, the CWG module will resume operation upon the first rising edge of the CWG data input.

Important: The SHUTDOWN bit cannot be cleared in software if the auto-shutdown condition

is still present.

Figure 24-17. SHUTDOWN FUNCTIONALITY, AUTO-RESTART DISABLED (REN = 0, LSAC = 01,

LSBD = 01)

Shutdown

REN Cleared by Software

Output Resumes

No Shutdown

CWG Input

SHUTDOWN

Source

Shutdown Source

Shutdown Event Ceases

Tri-State (No Pulse)

CWGxC

Rev. 30-000105A

4/14/2017

CWGxD

CWGxA

CWGxB

24.11.2.2 Auto-Restart

When the REN bit is set (REN = 1), the CWG module will restart from the shutdown state automatically.

Once all auto-shutdown conditions are removed, the hardware will automatically clear SHUTDOWN.

Once SHUTDOWN is cleared, the CWG module will resume operation upon the first rising edge of the

CWG data input.

Important: The SHUTDOWN bit cannot be cleared in software if the auto-shutdown condition

is still present.

PIC18F26/45/46Q10

(CWG) Complementary Waveform Generator Modul...

Figure 24-18. SHUTDOWN FUNCTIONALITY, AUTO-RESTART ENABLED (REN = 1, LSAC = 01,

LSBD = 01)

Shutdown

Tri-State (No Pulse)

REN auto-cleared by hardware

Output Resumes

No Shutdown

CWG Input

SHUTDOWN

Source

Shutdown Source

Shutdown Event Ceases

Tri-State (No Pulse)

Rev. 30-000106A

4/14/2017

CWGxA

CWGxB

CWGxC

CWGxD

24.12 Operation During Sleep

The CWG module operates independently from the system clock and will continue to run during Sleep,

provided that the clock and input sources selected remain active.

The HFINTOSC remains active during Sleep when all the following conditions are met:

• CWG module is enabled

• Input source is active

• HFINTOSC is selected as the clock source, regardless of the system clock source selected.

In other words, if the HFINTOSC is simultaneously selected as the system clock and the CWG clock

source, when the CWG is enabled and the input source is active, then the CPU will go idle during Sleep,

but the HFINTOSC will remain active and the CWG will continue to operate. This will have a direct effect

on the Sleep mode current.

24.13 Configuring the CWG

1. Ensure that the TRIS control bits corresponding to CWG outputs are set so that all are configured

as inputs, ensuring that the outputs are inactive during setup. External hardware should ensure that

pin levels are held to safe levels.

2. Clear the EN bit, if not already cleared.

3. Configure the MODE bits to set the output operating mode.

4. Configure the POLy bits to set the output polarities.

5. Configure the ISM bits to select the data input source.

6. If a steering mode is selected, configure the STRy bits to select the desired output on the CWG

outputs.

7. Configure the LSBD and LSAC bits to select the auto-shutdown output override states (this is

necessary even if not using auto-shutdown because start-up will be from a shutdown state).

8. If auto-restart is desired, set the REN bit.

9. If auto-shutdown is desired, configure the ASyE bits to select the shutdown source.

10. Set the desired rising and falling dead-band times with the CWGxDBR and CWGxDBF registers.

PIC18F26/45/46Q10

(CWG) Complementary Waveform Generator Modul...

11. Select the clock source with the CS bits.

12. Set the EN bit to enable the module.

13. Clear the TRIS bits that correspond to the CWG outputs to set them as outputs.

If auto-restart is to be used, set the REN bit and the SHUTDOWN bit will be cleared automatically.

Otherwise, clear the SHUTDOWN bit in software to start the CWG.

PIC18F26/45/46Q10

(CWG) Complementary Waveform Generator Modul...

24.14 Register Summary - CWG Control

Address Name Bit Pos.

0x0F3B CWG1CLK 7:0 CS

0x0F3C CWG1ISM 7:0 ISM[3:0]

0x0F3D CWG1DBR 7:0 DBR[5:0]

0x0F3E CWG1DBF 7:0 DBF[5:0]

0x0F3F CWG1CON0 7:0 EN LD MODE[2:0]

0x0F40 CWG1CON1 7:0 IN POLD POLC POLB POLA

0x0F41 CWG1AS0 7:0 SHUTDOWN REN LSBD[1:0] LSAC[1:0]

0x0F42 CWG1AS1 7:0 AS7E AS6E AS5E AS4E AS3E AS2E AS1E AS0E

0x0F43 CWG1STR 7:0 OVRD OVRC OVRB OVRA STRD STRC STRB STRA

24.15 Register Definitions: CWG Control

Long bit name prefixes for the CWG peripherals are shown in the table below. Refer to the "Long Bit

Names Section" for more information.

Table 24-3. CWG Bit Name Prefixes

Peripheral Bit Name Prefix

CWG1 CWG1

Related Links

1.4.2.2 Long Bit Names

PIC18F26/45/46Q10

(CWG) Complementary Waveform Generator Modul...

24.15.1 CWGxCON0

Name: CWGxCON0

Address: 0x0F3F

CWG Control Register 0

Bit 7 6 5 4 3 2 1 0

EN LD MODE[2:0]

Access R/W R/W/HC R/W R/W R/W

Reset 0 0 0 0 0

Bit 7 – EN CWG1 Enable bit

Value Description

1Module is enabled

0Module is disabled

Bit 6 – LD CWG1 Load Buffers bit(1)

Value Description

1Dead-band count buffers to be loaded on CWG data rising edge, following first falling edge

after this bit is set

0Buffers remain unchanged

Bits 2:0 – MODE[2:0] CWG1 Mode bits

Value Description

111 Reserved

110 Reserved

101 CWG outputs operate in Push-Pull mode

100 CWG outputs operate in Half-Bridge mode

011 CWG outputs operate in Reverse Full-Bridge mode

010 CWG outputs operate in Forward Full-Bridge mode

001 CWG outputs operate in Synchronous Steering mode

000 CWG outputs operate in Asynchronous Steering mode

Note:

1. This bit can only be set after EN = 1; it cannot be set in the same cycle when EN is set.

PIC18F26/45/46Q10

(CWG) Complementary Waveform Generator Modul...

24.15.2 CWGxCON1

Name: CWGxCON1

Address: 0x0F40

CWG Control Register 1

Bit 7 6 5 4 3 2 1 0

IN POLD POLC POLB POLA

Access RO R/W R/W R/W R/W

Reset x 0 0 0 0

Bit 5 – IN CWG Input Value bit (read-only)

Value Description

1CWG input is a logic 1

0CWG input is a logic 0

Bits 0, 1, 2, 3 – POLy CWG Output 'y' Polarity bit

Value Description

1Signal output is inverted polarity

0Signal output is normal polarity

PIC18F26/45/46Q10

(CWG) Complementary Waveform Generator Modul...

24.15.3 CWGxCLK

Name: CWGxCLK

Address: 0x0F3B

CWGx Clock Input Selection Register

Bit 7 6 5 4 3 2 1 0

CS

Access R/W

Reset 0

Bit 0 – CS Clock Source

CWG Clock Source Selection Select bits

Value Description

1HFINTOSC (remains operating during Sleep)

0FOSC

PIC18F26/45/46Q10

(CWG) Complementary Waveform Generator Modul...

24.15.4 CWGxISM

Name: CWGxISM

Address: 0x0F3C

CWGx Input Selection Register

Bit 7 6 5 4 3 2 1 0

ISM[3:0]

Access R/W R/W R/W R/W

Reset 0 0 0 0

Bits 3:0 – ISM[3:0] CWG Data Input Source Select bits

Table 24-4. CWG Data Input Sources

ISM Data Source

1111 CLC8_out

1110 CLC7_out

1101 CLC6_out

1100 CLC5_out

1011 CLC4_out

1010 CLC3_out

1001 CLC2_out

1000 CLC1_out

0111 DSM_out

0110 CMP2_out

0101 CMP1_out

0100 PWM4_out

0011 PWM3_out

0010 CCP2_out

0001 CCP1_out

0000 Pin selected by CWGxPPS

PIC18F26/45/46Q10

(CWG) Complementary Waveform Generator Modul...

24.15.5 CWGxSTR

Name: CWGxSTR

Address: 0x0F43

CWG Steering Control Register (1)

Bit 7 6 5 4 3 2 1 0

OVRD OVRC OVRB OVRA STRD STRC STRB STRA

Access R/W R/W R/W R/W R/W R/W R/W R/W

Reset 0 0 0 0 0 0 0 0

Bits 4, 5, 6, 7 – OVRy Steering Data OVR'y' bit

Value Condition Description

xSTRy = 1CWGx'y' output has the CWG data input waveform with polarity

control from POLy bit

1STRy = 0 and POLy = xCWGx'y' output is high

0STRy = 0 and POLy = xCWGx'y' output is low

Bits 0, 1, 2, 3 – STRy STR'y' Steering Enable bit(2)

Value Description

1CWGx'y' output has the CWG data input waveform with polarity control from POLy bit

0CWGx'y' output is assigned to value of OVRy bit

Note:

1. The bits in this register apply only when MODE = '00x' (24.15.1 CWGxCON0, Steering modes).

2. This bit is double-buffered when MODE = '001'.

PIC18F26/45/46Q10

(CWG) Complementary Waveform Generator Modul...

24.15.6 CWGxAS0

Name: CWGxAS0

Address: 0x0F41

CWG Auto-Shutdown Control Register 0

Bit 7 6 5 4 3 2 1 0

SHUTDOWN REN LSBD[1:0] LSAC[1:0]

Access R/W/HS/HC R/W R/W R/W R/W R/W

Reset 0 0 0 1 0 1

Bit 7 – SHUTDOWN Auto-Shutdown Event Status bit(1,2)

Value Description

1An auto-shutdown state is in effect

0No auto-shutdown event has occurred

Bit 6 – REN Auto-Restart Enable bit

Value Description

1Auto-restart is enabled

0Auto-restart is disabled

Bits 5:4 – LSBD[1:0] CWGxB and CWGxD Auto-Shutdown State Control bits

Value Description

11 A logic ‘1’ is placed on CWGxB/D when an auto-shutdown event occurs.

10 A logic ‘0’ is placed on CWGxB/D when an auto-shutdown event occurs.

01 Pin is tri-stated on CWGxB/D when an auto-shutdown event occurs.

00 The Inactive state of the pin, including polarity, is placed on CWGxB/D after the required

dead-band interval when an auto-shutdown event occurs.

Bits 3:2 – LSAC[1:0] CWGxA and CWGxC Auto-Shutdown State Control bits

Value Description

11 A logic ‘1’ is placed on CWGxA/C when an auto-shutdown event occurs.

10 A logic ‘0’ is placed on CWGxA/C when an auto-shutdown event occurs.

01 Pin is tri-stated on CWGxA/C when an auto-shutdown event occurs.

00 The Inactive state of the pin, including polarity, is placed on CWGxA/C after the required

dead-band interval when an auto-shutdown event occurs.

Note:

1. This bit may be written while EN = 0 (24.15.1 CWGxCON0), to place the outputs into the shutdown

configuration.

2. The outputs will remain in auto-shutdown state until the next rising edge of the CWG data input

after this bit is cleared.

PIC18F26/45/46Q10

(CWG) Complementary Waveform Generator Modul...

24.15.7 CWGxAS1

Name: CWGxAS1

Address: 0x0F42

CWG Auto-Shutdown Control Register 1

Bit 7 6 5 4 3 2 1 0

AS7E AS6E AS5E AS4E AS3E AS2E AS1E AS0E

Access R/W R/W R/W R/W R/W R/W R/W R/W

Reset 0 0 0 0 0 0 0 0

Bits 0, 1, 2, 3, 4, 5, 6, 7 – ASyE CWG Auto-shutdown Source ASyE Enable bit(1)

Table 24-5. Shutdown Sources

ASyE Source

AS7E CLC6_out (low causes shutdown)

AS6E CLC2_out (low causes shutdown)

AS5E CMP2_out (low causes shutdown)

AS4E CMP1_out (low causes shutdown)

AS3E TMR6_postscaled (high causes shutdown)

AS2E TMR4_postscaled (high causes shutdown)

AS1E TMR2_postscaled (high causes shutdown)

AS0E Pin selected by CWGxPPS (low causes shutdown)

Value Description

1Auto-shutdown for source ASyE is enabled

0Auto-shutdown for source ASyE is disabled

Note: This bit may be written while EN = 0 (24.15.1 CWGxCON0), to place the outputs into the

shutdown configuration.

The outputs will remain in auto-shutdown state until the next rising edge of the CWG data input after this

bit is cleared.

PIC18F26/45/46Q10

(CWG) Complementary Waveform Generator Modul...

24.15.8 CWGxDBR

Name: CWGxDBR

Address: 0x0F3D

CWG Rising Dead-Band Count Register

Bit 7 6 5 4 3 2 1 0

DBR[5:0]

Access R/W R/W R/W R/W R/W R/W

Reset x x x x x x

Bits 5:0 – DBR[5:0] CWG Rising Edge-Triggered Dead-Band Count bits

Reset States: POR/BOR = xxxxxx

All Other Resets = uuuuuu

Value Description

nDead band is active no less than n, and no more than n+1, CWG clock periods after the

rising edge

00 CWG clock periods. Dead-band generation is bypassed

PIC18F26/45/46Q10

(CWG) Complementary Waveform Generator Modul...

24.15.9 CWGxDBF

Name: CWGxDBF

Address: 0x0F3E

CWG Falling Dead-Band Count Register

Bit 7 6 5 4 3 2 1 0

DBF[5:0]

Access R/W R/W R/W R/W R/W R/W

Reset x x x x x x

Bits 5:0 – DBF[5:0] CWG Falling Edge-Triggered Dead-Band Count bits

Reset States: POR/BOR = xxxxxx

All Other Resets = uuuuuu

Value Description

nDead band is active no less than n, and no more than n+1, CWG clock periods after the

falling edge

00 CWG clock periods. Dead-band generation is bypassed

PIC18F26/45/46Q10

(CWG) Complementary Waveform Generator Modul...

25. (CLC) Configurable Logic Cell

The Configurable Logic Cell (CLCx) module provides programmable logic that operates outside the

speed limitations of software execution. The logic cell takes up to 64input signals and, through the use of

configurable gates, reduces the 64inputs to four logic lines that drive one of eight selectable single-output

logic functions.

Input sources are a combination of the following:

• I/O pins

• Internal clocks

• Peripherals

• Register bits

The output can be directed internally to peripherals and to an output pin.

Important: There are several CLC instances on this device. Throughout this section, the lower

case ‘x’ in register names is a generic reference to the CLC instance number. For example, the

first instance of the control register is CLC1CON and is generically described in this chapter as

CLCxCON.

The following figure is a simplified diagram showing signal flow through the CLC. Possible configurations

include:

• Combinatorial Logic:

– AND

– NAND

– AND-OR

– AND-OR-INVERT

– OR-XOR

– OR-XNOR

• Latches:

– S-R

– Clocked D with Set and Reset

– Transparent D with Set and Reset

– Clocked J-K with Reset

PIC18F26/45/46Q10

(CLC) Configurable Logic Cell

Figure 25-1. CLC Simplified Block Diagram

Input Data Selection Gates(1)

Logic

Function

(2)

lcxg2

lcxg1

lcxg3

lcxg4

MODE<2:0>

lcxq

EN

POL

det

Interrupt

det

Interrupt

set bit

CLCxIF

INTN

INTP

CLCx

to Peripherals

Q1

CLCx_out

OUT

CLCxOUT

D Q

PPS

LCx_in[0]

LCx_in[1]

LCx_in[2]

LCx_in[n-2]

LCx_in[n-1]

LCx_in[n]

.

Rev. 10-000025H

11/9/2016

CLCxPPS

TRIS

Note:

1. See Figure 25-2 for input data selection and gating.

2. See Figure 25-3 for programmable logic functions.

25.1 CLC Setup

Programming the CLC module is performed by configuring the four stages in the logic signal flow. The

four stages are:

• Data selection

• Data gating

• Logic function selection

• Output polarity

Each stage is setup at run time by writing to the corresponding CLC Special Function Registers. This has

the added advantage of permitting logic reconfiguration on-the-fly during program execution.

25.1.1 Data Selection

There are 64signals available as inputs to the configurable logic. Four 64-input multiplexers are used to

select the inputs to pass on to the next stage.

Data selection is through four multiplexers as indicated on the left side of the following diagram. Data

inputs in the figure are identified by a generic numbered input name.

PIC18F26/45/46Q10

(CLC) Configurable Logic Cell

Figure 25-2. Input Data Selection and Gating

lcxg1

G1POL

Data GATE 1

G 1 D1 T

lcxg2

lcxg3

lcxg4

Data GATE 2

Data GATE 3

Data GATE 4

G 1 D1 N

G 1 D2 T

G 1 D2 N

G 1 D3 T

G 1 D3 N

G 1 D4 T

G 1 D4 N

D1S<5:0>

D2S<5:0>

D3S<5:0>

D4S<5:0>

LCx_in[0]

LCx_in[n]

000000

111111

Data Selection

Note: All controls are undefined at power-up.

d1T

d1N

d2T

d2N

d3T

d3N

d4T

d4N

(Same as Data GATE 1)

LCx_in[0]

LCx_in[n]

000000

111111

LCx_in[0]

LCx_in[n]

000000

111111

LCx_in[0]

LCx_in[n]

000000

111111

Rev. 30-000149A

6/12/2017

The following table correlates the generic input name to the actual signal for each CLC module. The

column labeled ‘DyS Value’ indicates the MUX selection code for the selected data input. DyS is an

abbreviation for the MUX select input codes: D1S through D4S where 'y' is the gate number.

PIC18F26/45/46Q10

(CLC) Configurable Logic Cell

CLC Data Input Sources

DyS Value CLC Input Source DyS Value CLC Input Source

111111 [63] Reserved 011111 [31] IOC_flag

111110 [62] Reserved 011110 [30] ZCD_out

111101 [61] Reserved 011101 [29] CMP2_out

111100 [60] Reserved 011100 [28] CMP1_out

111011 [59] Reserved 011011 [27] PWM4_out

111010 58] Reserved 011010 [26] PWM3_out

111001 [57] Reserved 011001 [25] CCP2_out

111000 [56] Reserved 011000 [24] CCP1 _out

110111 [55] Reserved 010111 [23] TMR6_out

110110 [54] Reserved 010110 [22] TMR5 _overflow

110101 [53] Reserved 010101 [21] TMR4 _out

110100 [52] Reserved 010100 [20] TMR3 _overflow

110011 [51] Reserved 010011 [19] TMR2 _out

110010 [50] CWG1B_out 010010 [18] TMR1 _overflow

110001 [49] CWG1A_out 010001 [17] TMR0 _overflow

110000 [48] SCK2 010000 [16] CLKR _out

101111 [47] SDO2 001111 [15] ADCRC

101110 [46] SCK1 001110 [14] SOSC

101101 [45] SDO1 001101 [13] SFINTOSC (1MHz)

101100 [44] EUSART2_TX/CK_out 001100 [12] MFINTOSC (32 kHz)

101011 [43] EUSART2_DT_out 001011 [11] MFINTOSC (500 kHz)

101010 [42] EUSART1_TX/CK_out 001010 [10] LFINTOSC

101001 [41] EUSART1_DT_out 001001 [9] HFINTOSC

101000 [40] CLC8_out 001000 [8] FOSC

100111 [39] CLC7_out 000111 [7] CLCIN7PPS

100110 [38] CLC6_out 000110 [6] CLCIN6PPS

100101 [37] CLC5_out 000101 [5] CLCIN5PPS

100100 [36] CLC4_out 000100 [4] CLCIN4PPS

100011 [35] CLC3_out 000011 [3] CLCIN3PPS

100010 [34] CLC2_out 000010 [2] CLCIN2PPS

100001 [33] CLC1_out 000001 [1] CLCIN1PPS

PIC18F26/45/46Q10

(CLC) Configurable Logic Cell

...........continued

DyS Value CLC Input Source DyS Value CLC Input Source

100000 [32] DSM1_out 000000 [0] CLCIN0PPS

Data inputs are selected with CLCxSEL0 through CLCxSEL3 registers.

Important: Data selections are undefined at power-up.

25.1.2 Data Gating

Outputs from the input multiplexers are directed to the desired logic function input through the data gating

stage. Each data gate can direct any combination of the four selected inputs.

The gate stage is more than just signal direction. The gate can be configured to direct each input signal

as inverted or non-inverted data. Directed signals are ANDed together in each gate. The output of each

gate can be inverted before going on to the logic function stage.

The gating is in essence a 1-to-4 input AND/NAND/OR/NOR gate. When every input is inverted and the

output is inverted, the gate is an AND of all enabled data inputs. When the inputs and output are not

inverted, the gate is an OR or all enabled inputs.

The following table summarizes the basic logic that can be obtained in gate 1 by using the gate logic

select bits. The table shows the logic of four input variables, but each gate can be configured to use less

than four. If no inputs are selected, the output will be zero or one, depending on the gate output polarity

bit.

Table 25-1. Data Gating Logic

CLCxGLSy GyPOL Gate Logic

0x55 1AND

0x55 0NAND

0xAA 1NOR

0xAA 0OR

0x00 0Logic 0

0x00 1Logic 1

It is possible (but not recommended) to select both the true and negated values of an input. When this is

done, the gate output is zero, regardless of the other inputs, but may emit logic glitches (transient-

induced pulses). If the output of the channel must be zero or one, the recommended method is to set all

gate bits to zero and use the gate polarity bit to set the desired level.

Data gating is configured with the logic gate select registers as follows:

• Gate 1: CLCxGLS0

• Gate 2: CLCxGLS1

• Gate 3: CLCxGLS2

• Gate 4: CLCxGLS3

PIC18F26/45/46Q10

(CLC) Configurable Logic Cell

Register number suffixes are different than the gate numbers because other variations of this module

have multiple gate selections in the same register.

Data gating is indicated in the right side of Figure 25-2. Only one gate is shown in detail. The remaining

three gates are configured identically with the exception that the data enables correspond to the enables

for that gate.

25.1.3 Logic Function

There are eight available logic functions including:

• AND-OR

• OR-XOR

• AND

• S-R Latch

• D Flip-Flop with Set and Reset

• D Flip-Flop with Reset

• J-K Flip-Flop with Reset

• Transparent Latch with Set and Reset

Logic functions are shown in the following diagram. Each logic function has four inputs and one output.

The four inputs are the four data gate outputs of the previous stage. The output is fed to the inversion

stage and from there to other peripherals, an output pin, and back to the CLC itself.

PIC18F26/45/46Q10

(CLC) Configurable Logic Cell

Figure 25-3. Programmable Logic Functions

lcxg

1

lcxg

2

lcxg

3

lcxg

4

lcxq

AND

-

OR

-

XOR

MODE

<

2

:

0

>

=

000

MODE

<

2

:

0

>

=

001

4

-

input AND

S

-

R Latch

MODE

<

2

:

0

>

=

010

MODE

<

2

:

0

>

=

011

lcxg

1

lcxg

2

lcxg

3

lcxg

4

lcxq

S

R

Q

lcxq

lcxg

1

lcxg

2

lcxg

3

lcxg

4

lcxg

1

lcxg

2

lcxg

3

lcxg

4

lcxq

1

-

Input D Flip

-

Flop with S and R

2

-

Input D Flip

-

Flop with R

J

-

K Flip

-

Flop with R

1

-

Input Transparent Latch with S and R

MODE

<

2

:

0

>

=

100

MODE

<

2

:

0

>

=

101

MODE

<

2

:

0

>

=

110

MODE

<

2

:

0

>

=

111

D

R

Q

lcxq

lcxg

1

lcxg

2

lcxg

3

lcxg

4

D

R

Q

S

lcxg

1

lcxg

2

lcxg

3

lcxg

4

lcxq

J

R

Q

K

lcxg

1

lcxg

2

lcxg

3

lcxg

4

lcxq

D

R

Q

S

LE

lcxq

lcxg

1

lcxg

2

lcxg

3

lcxg

4

Rev. 10-000122B

9/13/2016

25.1.4 Output Polarity

The last stage in the CLC is the output polarity. Setting the POL bit inverts the output signal from the logic

stage. Changing the polarity while the interrupts are enabled will cause an interrupt for the resulting

output transition.

25.2 CLC Interrupts

An interrupt will be generated upon a change in the output value of the CLCx when the appropriate

interrupt enables are set. A rising edge detector and a falling edge detector are present in each CLC for

this purpose.

PIC18F26/45/46Q10

(CLC) Configurable Logic Cell

The CLCxIF bit of the associated PIR register will be set when either edge detector is triggered and its

associated enable bit is set. The INTP enables rising edge interrupts and the INTN bit enables falling

edge interrupts.

To fully enable the interrupt, set the following bits:

• CLCxIE bit of the respective PIE register

•INTP bit (for a rising edge detection)

•INTN bit (for a falling edge detection)

• If priority interrupts are not used

– Clear the IPEN bit of the INTCON register

– Set the GIE bit of the INTCON register

– Set the PEIE bit of the INTCON register

• If the CLC is a high-priority interrupt

– Set the IPEN bit of the INTCON register

– Set the CLCxIP bit of the respective IPR register

– Set the GIEH bit of the INTCON register

• If the CLC is a low-priority interrupt

– Set the IPEN bit of the INTCON register

– Clear the CLCxIP bit of the respective IPR register

– Set the GIEL bit of the INTCON register

The CLCxIF bit of the respective PIR register, must be cleared in software as part of the interrupt service.

If another edge is detected while this flag is being cleared, the flag will still be set at the end of the

sequence.

25.3 Output Mirror Copies

Mirror copies of all CLCxOUT bits are contained in the 25.8.11 CLCDATA register. Reading this register

reads the outputs of all CLCs simultaneously. This prevents any reading skew introduced by testing or

reading the OUT bits in the individual CLCxCON registers.

25.4 Effects of a Reset

The CLCxCON register is cleared to zero as the result of a Reset. All other selection and gating values

remain unchanged.

25.5 Operation During Sleep

The CLC module operates independently from the system clock and will continue to run during Sleep,

provided that the input sources selected remain active.

The HFINTOSC remains active during Sleep when the CLC module is enabled and the HFINTOSC is

selected as an input source, regardless of the system clock source selected.

In other words, if the HFINTOSC is simultaneously selected as the system clock and as a CLC input

source, when the CLC is enabled, the CPU will go idle during Sleep, but the CLC will continue to operate

and the HFINTOSC will remain active.

This will have a direct effect on the Sleep mode current.

PIC18F26/45/46Q10

(CLC) Configurable Logic Cell

25.6 CLC Setup Steps

The following steps should be followed when setting up the CLC:

• Disable CLC by clearing the EN bit.

• Select desired inputs using the CLCxSEL0 through CLCxSEL3 registers (See CLC Data Input Table).

• Clear any associated ANSEL bits.

• Set all TRIS bits associated with inputs.

• Enable the chosen inputs through the four gates using the CLCxGLS0 through CLCxGLS3 registers.

• Select the gate output polarities with the GyPOL bits

• Select the desired logic function with the MODE bits

• Select the desired polarity of the logic output with the POL bit. (This step may be combined with the

previous gate output polarity step).

• If driving a device pin, set the desired pin PPS control register and also clear the TRIS bit

corresponding to that output.

• Configure the interrupts (optional). See 25.2 CLC Interrupts

• Enable the CLC by setting the EN bit.

PIC18F26/45/46Q10

(CLC) Configurable Logic Cell

25.7 Register Summary - CLC Control

Address Name Bit Pos.

0x0E27 CLC1CON 7:0 EN OUT INTP INTN MODE[2:0]

0x0E28 CLC1POL 7:0 POL G4POL G3POL G2POL G1POL

0x0E29 CLC1SEL0 7:0 D1S[5:0]

0x0E2A CLC1SEL1 7:0 D2S[5:0]

0x0E2B CLC1SEL2 7:0 D3S[5:0]

0x0E2C CLC1SEL3 7:0 D4S[5:0]

0x0E2D CLC1GLS0 7:0 G1D4T G1D4N G1D3T G1D3N G1D2T G1D2N G1D1T G1D1N

0x0E2E CLC1GLS1 7:0 G2D4T G2D4N G2D3T G2D3N G2D2T G2D2N G2D1T G2D1N

0x0E2F CLC1GLS2 7:0 G3D4T G3D4N G3D3T G3D3N G3D2T G3D2N G3D1T G3D1N

0x0E30 CLC1GLS3 7:0 G4D4T G4D4N G4D3T G4D3N G4D2T G4D2N G4D1T G4D1N

0x0E31 CLC2CON 7:0 EN OUT INTP INTN MODE[2:0]

0x0E32 CLC2POL 7:0 POL G4POL G3POL G2POL G1POL

0x0E33 CLC2SEL0 7:0 D1S[5:0]

0x0E34 CLC2SEL1 7:0 D2S[5:0]

0x0E35 CLC2SEL2 7:0 D3S[5:0]

0x0E36 CLC2SEL3 7:0 D4S[5:0]

0x0E37 CLC2GLS0 7:0 G1D4T G1D4N G1D3T G1D3N G1D2T G1D2N G1D1T G1D1N

0x0E38 CLC2GLS1 7:0 G2D4T G2D4N G2D3T G2D3N G2D2T G2D2N G2D1T G2D1N

0x0E39 CLC2GLS2 7:0 G3D4T G3D4N G3D3T G3D3N G3D2T G3D2N G3D1T G3D1N

0x0E3A CLC2GLS3 7:0 G4D4T G4D4N G4D3T G4D3N G4D2T G4D2N G4D1T G4D1N

0x0E3B CLC3CON 7:0 EN OUT INTP INTN MODE[2:0]

0x0E3C CLC3POL 7:0 POL G4POL G3POL G2POL G1POL

0x0E3D CLC3SEL0 7:0 D1S[5:0]

0x0E3E CLC3SEL1 7:0 D2S[5:0]

0x0E3F CLC3SEL2 7:0 D3S[5:0]

0x0E40 CLC3SEL3 7:0 D4S[5:0]

0x0E41 CLC3GLS0 7:0 G1D4T G1D4N G1D3T G1D3N G1D2T G1D2N G1D1T G1D1N

0x0E42 CLC3GLS1 7:0 G2D4T G2D4N G2D3T G2D3N G2D2T G2D2N G2D1T G2D1N

0x0E43 CLC3GLS2 7:0 G3D4T G3D4N G3D3T G3D3N G3D2T G3D2N G3D1T G3D1N

0x0E44 CLC3GLS3 7:0 G4D4T G4D4N G4D3T G4D3N G4D2T G4D2N G4D1T G4D1N

0x0E45 CLC4CON 7:0 EN OUT INTP INTN MODE[2:0]

0x0E46 CLC4POL 7:0 POL G4POL G3POL G2POL G1POL

0x0E47 CLC4SEL0 7:0 D1S[5:0]

0x0E48 CLC4SEL1 7:0 D2S[5:0]

0x0E49 CLC4SEL2 7:0 D3S[5:0]

0x0E4A CLC4SEL3 7:0 D4S[5:0]

0x0E4B CLC4GLS0 7:0 G1D4T G1D4N G1D3T G1D3N G1D2T G1D2N G1D1T G1D1N

0x0E4C CLC4GLS1 7:0 G2D4T G2D4N G2D3T G2D3N G2D2T G2D2N G2D1T G2D1N

0x0E4D CLC4GLS2 7:0 G3D4T G3D4N G3D3T G3D3N G3D2T G3D2N G3D1T G3D1N

0x0E4E CLC4GLS3 7:0 G4D4T G4D4N G4D3T G4D3N G4D2T G4D2N G4D1T G4D1N

0x0E4F CLC5CON 7:0 EN OUT INTP INTN MODE[2:0]

0x0E50 CLC5POL 7:0 POL G4POL G3POL G2POL G1POL

0x0E51 CLC5SEL0 7:0 D1S[5:0]

PIC18F26/45/46Q10

(CLC) Configurable Logic Cell

...........continued

Address Name Bit Pos.

0x0E52 CLC5SEL1 7:0 D2S[5:0]

0x0E53 CLC5SEL2 7:0 D3S[5:0]

0x0E54 CLC5SEL3 7:0 D4S[5:0]

0x0E55 CLC5GLS0 7:0 G1D4T G1D4N G1D3T G1D3N G1D2T G1D2N G1D1T G1D1N

0x0E56 CLC5GLS1 7:0 G2D4T G2D4N G2D3T G2D3N G2D2T G2D2N G2D1T G2D1N

0x0E57 CLC5GLS2 7:0 G3D4T G3D4N G3D3T G3D3N G3D2T G3D2N G3D1T G3D1N

0x0E58 CLC5GLS3 7:0 G4D4T G4D4N G4D3T G4D3N G4D2T G4D2N G4D1T G4D1N

0x0E59 CLC6CON 7:0 EN OUT INTP INTN MODE[2:0]

0x0E5A CLC6POL 7:0 POL G4POL G3POL G2POL G1POL

0x0E5B CLC6SEL0 7:0 D1S[5:0]

0x0E5C CLC6SEL1 7:0 D2S[5:0]

0x0E5D CLC6SEL2 7:0 D3S[5:0]

0x0E5E CLC6SEL3 7:0 D4S[5:0]

0x0E5F CLC6GLS0 7:0 G1D4T G1D4N G1D3T G1D3N G1D2T G1D2N G1D1T G1D1N

0x0E60 CLC6GLS1 7:0 G2D4T G2D4N G2D3T G2D3N G2D2T G2D2N G2D1T G2D1N

0x0E61 CLC6GLS2 7:0 G3D4T G3D4N G3D3T G3D3N G3D2T G3D2N G3D1T G3D1N

0x0E62 CLC6GLS3 7:0 G4D4T G4D4N G4D3T G4D3N G4D2T G4D2N G4D1T G4D1N

0x0E63 CLC7CON 7:0 EN OUT INTP INTN MODE[2:0]

0x0E64 CLC7POL 7:0 POL G4POL G3POL G2POL G1POL

0x0E65 CLC7SEL0 7:0 D1S[5:0]

0x0E66 CLC7SEL1 7:0 D2S[5:0]

0x0E67 CLC7SEL2 7:0 D3S[5:0]

0x0E68 CLC7SEL3 7:0 D4S[5:0]

0x0E69 CLC7GLS0 7:0 G1D4T G1D4N G1D3T G1D3N G1D2T G1D2N G1D1T G1D1N

0x0E6A CLC7GLS1 7:0 G2D4T G2D4N G2D3T G2D3N G2D2T G2D2N G2D1T G2D1N

0x0E6B CLC7GLS2 7:0 G3D4T G3D4N G3D3T G3D3N G3D2T G3D2N G3D1T G3D1N

0x0E6C CLC7GLS3 7:0 G4D4T G4D4N G4D3T G4D3N G4D2T G4D2N G4D1T G4D1N

0x0E6D CLC8CON 7:0 EN OUT INTP INTN MODE[2:0]

0x0E6E CLC8POL 7:0 POL G4POL G3POL G2POL G1POL

0x0E6F CLC8SEL0 7:0 D1S[5:0]

0x0E70 CLC8SEL1 7:0 D2S[5:0]

0x0E71 CLC8SEL2 7:0 D3S[5:0]

0x0E72 CLC8SEL3 7:0 D4S[5:0]

0x0E73 CLC8GLS0 7:0 G1D4T G1D4N G1D3T G1D3N G1D2T G1D2N G1D1T G1D1N

0x0E74 CLC8GLS1 7:0 G2D4T G2D4N G2D3T G2D3N G2D2T G2D2N G2D1T G2D1N

0x0E75 CLC8GLS2 7:0 G3D4T G3D4N G3D3T G3D3N G3D2T G3D2N G3D1T G3D1N

0x0E76 CLC8GLS3 7:0 G4D4T G4D4N G4D3T G4D3N G4D2T G4D2N G4D1T G4D1N

0x0E77 CLCDATA 7:0 MLC8OUT MLC7OUT MLC6OUT MLC5OUT MLC4OUT MLC3OUT MLC2OUT MLC1OUT

25.8 Register Definitions: Configurable Logic Cell

Long bit name prefixes for the CLC peripherals are shown in the table below. Refer to the "Long Bit

Names Section" for more information.

PIC18F26/45/46Q10

(CLC) Configurable Logic Cell

Table 25-2. CLC Bit Name Prefixes

Peripheral Bit Name Prefix

CLC1 LC1

CLC2 LC2

CLC3 LC3

CLC4 LC4

CLC5 LC5

CLC6 LC6

CLC7 LC7

CLC8 LC8

Related Links

1.4.2.2 Long Bit Names

PIC18F26/45/46Q10

(CLC) Configurable Logic Cell

25.8.1 CLCxCON

Name: CLCxCON

Address: 0xE27,0xE31,0xE3B,0xE45,0xE4F,0xE59,0xE63,0xE6D

Configurable Logic Cell Control Register

Bit 7 6 5 4 3 2 1 0

EN OUT INTP INTN MODE[2:0]

Access R/W RO R/W R/W R/W R/W R/W

Reset 0 0 0 0 0 0 0

Bit 7 – EN

CLC Enable bit

Value Description

1Configurable logic cell is enabled and mixing signals

0Configurable logic cell is disabled and has logic zero output

Bit 5 – OUT

Logic cell output data, after LCPOL. Sampled from CLCxOUT

Bit 4 – INTP

Configurable Logic Cell Positive Edge Going Interrupt Enable bit

Value Description

1CLCxIF will be set when a rising edge occurs on CLCxOUT

0Rising edges on CLCxOUT have no effect on CLCxIF

Bit 3 – INTN

Configurable Logic Cell Negative Edge Going Interrupt Enable bit

Value Description

1CLCxIF will be set when a falling edge occurs on CLCxOUT

0Falling edges on CLCxOUT have no effect on CLCxIF

Bits 2:0 – MODE[2:0]

Configurable Logic Cell Functional Mode Selection bits

Value Description

111 Cell is 1-input transparent latch with Set and Reset

110 Cell is J-K flip-flop with Reset

101 Cell is 2-input D flip-flop with Reset

100 Cell is 1-input D flip-flop with Set and Reset

011 Cell is S-R latch

010 Cell is 4-input AND

001 Cell is OR-XOR

000 Cell is AND-OR

PIC18F26/45/46Q10

(CLC) Configurable Logic Cell

25.8.2 CLCxPOL

Name: CLCxPOL

Address: 0xE28,0xE32,0xE3C,0xE46,0xE50,0xE5A,0xE64,0xE6E

Signal Polarity Control Register

Bit 7 6 5 4 3 2 1 0

POL G4POL G3POL G2POL G1POL

Access R/W R/W R/W R/W R/W

Reset 0 x x x x

Bit 7 – POL

CLCxOUT Output Polarity Control bit

Value Description

1The output of the logic cell is inverted

0The output of the logic cell is not inverted

Bits 0, 1, 2, 3 – GyPOL

Gate Output Polarity Control bit

Reset States: Default = xxxx

POR/BOR = x

All Other Resets = u

Value Description

1The gate output is inverted when applied to the logic cell

0The output of the gate is not inverted

PIC18F26/45/46Q10

(CLC) Configurable Logic Cell

25.8.3 CLCxSEL0

Name: CLCxSEL0

Address: 0xE29,0xE33,0xE3D,0xE47,0xE51,0xE5B,0xE65,0xE6F

Generic CLCx Data 1 Select Register

Bit 7 6 5 4 3 2 1 0

D1S[5:0]

Access R/W R/W R/W R/W R/W R/W

Reset x x x x x x

Bits 5:0 – D1S[5:0]

CLCx Data1 Input Selection bits

Reset States: POR/BOR = xxxxxx

All Other Resets = uuuuuu

Value Description

nRefer to CLC Input Sources for input selections

PIC18F26/45/46Q10

(CLC) Configurable Logic Cell

25.8.4 CLCxSEL1

Name: CLCxSEL1

Address: 0xE2A,0xE34,0xE3E,0xE48,0xE52,0xE5C,0xE66,0xE70

Generic CLCx Data 1 Select Register

Bit 7 6 5 4 3 2 1 0

D2S[5:0]

Access R/W R/W R/W R/W R/W R/W

Reset x x x x x x

Bits 5:0 – D2S[5:0]

CLCx Data2 Input Selection bits

Reset States: POR/BOR = xxxxxx

All Other Resets = uuuuuu

Value Description

nRefer to CLC Input Sources for input selections

PIC18F26/45/46Q10

(CLC) Configurable Logic Cell

25.8.5 CLCxSEL2

Name: CLCxSEL2

Address: 0xE2B,0xE35,0xE3F,0xE49,0xE53,0xE5D,0xE67,0xE71

Generic CLCx Data 1 Select Register

Bit 7 6 5 4 3 2 1 0

D3S[5:0]

Access R/W R/W R/W R/W R/W R/W

Reset x x x x x x

Bits 5:0 – D3S[5:0]

CLCx Data3 Input Selection bits

Reset States: POR/BOR = xxxxxx

All Other Resets = uuuuuu

Value Description

nRefer to CLC Input Sources for input selections

PIC18F26/45/46Q10

(CLC) Configurable Logic Cell

25.8.6 CLCxSEL3

Name: CLCxSEL3

Address: 0xE2C,0xE36,0xE40,0xE4A,0xE54,0xE5E,0xE68,0xE72

Generic CLCx Data 4 Select Register

Bit 7 6 5 4 3 2 1 0

D4S[5:0]

Access R/W R/W R/W R/W R/W R/W

Reset x x x x x x

Bits 5:0 – D4S[5:0]

CLCx Data4 Input Selection bits

Reset States: POR/BOR = xxxxxx

All Other Resets = uuuuuu

Value Description

nRefer to CLC Input Sources for input selections

PIC18F26/45/46Q10

(CLC) Configurable Logic Cell

25.8.7 CLCxGLS0

Name: CLCxGLS0

Address: 0xE2D,0xE37,0xE41,0xE4B,0xE55,0xE5F,0xE69,0xE73

CLCx Gate1 Logic Select Register

Bit 7 6 5 4 3 2 1 0

G1D4T G1D4N G1D3T G1D3N G1D2T G1D2N G1D1T G1D1N

Access R/W R/W R/W R/W R/W R/W R/W R/W

Reset x x x x x x x x

Bits 1, 3, 5, 7 – G1DyT

dyT: Gate1 Data 'y' True (non-inverted) bit

Reset States: Default = xxxx

POR/BOR = x

All Other Resets = u

Value Description

1dyT is gated into g1

0dyT is not gated into g1

Bits 0, 2, 4, 6 – G1DyN

dyN: Gate1 Data 'y' Negated (inverted) bit

Reset States: Default = xxxx

POR/BOR = x

All Other Resets = u

Value Description

1dyN is gated into g1

0dyN is not gated into g1

PIC18F26/45/46Q10

(CLC) Configurable Logic Cell

25.8.8 CLCxGLS1

Name: CLCxGLS1

Address: 0xE2E,0xE38,0xE42,0xE4C,0xE56,0xE60,0xE6A,0xE74

CLCx Gate2 Logic Select Register

Bit 7 6 5 4 3 2 1 0

G2D4T G2D4N G2D3T G2D3N G2D2T G2D2N G2D1T G2D1N

Access R/W R/W R/W R/W R/W R/W R/W R/W

Reset x x x x x x x x

Bits 1, 3, 5, 7 – G2DyT

dyT: Gate2 Data 'y' True (non-inverted) bit

Reset States: Default = xxxx

POR/BOR = x

All Other Resets = u

Value Description

1dyT is gated into g2

0dyT is not gated into g2

Bits 0, 2, 4, 6 – G2DyN

dyN: Gate2 Data 'y' Negated (inverted) bit

Reset States: Default = xxxx

POR/BOR = x

All Other Resets = u

Value Description

1dyN is gated into g2

0dyN is not gated into g2

PIC18F26/45/46Q10

(CLC) Configurable Logic Cell

25.8.9 CLCxGLS2

Name: CLCxGLS2

Address: 0xE2F,0xE39,0xE43,0xE4D,0xE57,0xE61,0xE6B,0xE75

CLCx Gate3 Logic Select Register

Bit 7 6 5 4 3 2 1 0

G3D4T G3D4N G3D3T G3D3N G3D2T G3D2N G3D1T G3D1N

Access R/W R/W R/W R/W R/W R/W R/W R/W

Reset x x x x x x x x

Bits 1, 3, 5, 7 – G3DyT

dyT: Gate3 Data 'y' True (non-inverted) bit

Reset States: Default = xxxx

POR/BOR = x

All Other Resets = u

Value Description

1dyT is gated into g3

0dyT is not gated into g3

Bits 0, 2, 4, 6 – G3DyN

dyN: Gate3 Data 'y' Negated (inverted) bit

Reset States: Default = xxxx

POR/BOR = x

All Other Resets = u

Value Description

1dyN is gated into g3

0dyN is not gated into g3

PIC18F26/45/46Q10

(CLC) Configurable Logic Cell

25.8.10 CLCxGLS3

Name: CLCxGLS3

Address: 0xE30,0xE3A,0xE44,0xE4E,0xE58,0xE62,0xE6C,0xE76

CLCx Gate4 Logic Select Register

Bit 7 6 5 4 3 2 1 0

G4D4T G4D4N G4D3T G4D3N G4D2T G4D2N G4D1T G4D1N

Access R/W R/W R/W R/W R/W R/W R/W R/W

Reset x x x x x x x x

Bits 1, 3, 5, 7 – G4DyT

dyT: Gate4 Data 'y' True (non-inverted) bit

Reset States: Default = xxxx

POR/BOR = x

All Other Resets = u

Value Description

1dyT is gated into g4

0dyT is not gated into g4

Bits 0, 2, 4, 6 – G4DyN

dyN: Gate4 Data 'y' Negated (inverted) bit

Reset States: Default = xxxx

POR/BOR = x

All Other Resets = u

Value Description

1dyN is gated into g4

0dyN is not gated into g4

PIC18F26/45/46Q10

(CLC) Configurable Logic Cell

25.8.11 CLCDATA

Name: CLCDATA

Address: 0xE77

CLC Data Ouput Register

Mirror copy of

Bit 7 6 5 4 3 2 1 0

MLC8OUT MLC7OUT MLC6OUT MLC5OUT MLC4OUT MLC3OUT MLC2OUT MLC1OUT

Access R/W R/W R/W R/W R/W R/W R/W R/W

Reset 0 0 0 0 0 0 0 0

Bits 0, 1, 2, 3, 4, 5, 6, 7 – MLCxOUT

Mirror copy of CLCx_out bit

Value Description

1CLCx_out is 1

0CLCx_out is 0

PIC18F26/45/46Q10

(CLC) Configurable Logic Cell

26. (DSM) Data Signal Modulator Module

The Data Signal Modulator (DSM) is a peripheral that allows the user to mix a data stream, also known

as a modulator signal, with a carrier signal to produce a modulated output.

Both the carrier and the modulator signals are supplied to the DSM module either internally, from the

output of a peripheral, or externally through an input pin.

The modulated output signal is generated by performing a logical “AND” operation of both the carrier and

modulator signals and then provided to the MDOUT pin.

The carrier signal is comprised of two distinct and separate signals. A Carrier High (CARH) signal and a

Carrier Low (CARL) signal. During the time in which the modulator (MOD) signal is in a logic high state,

the DSM mixes the CARH signal with the modulator signal. When the modulator signal is in a logic low

state, the DSM mixes the CARL signal with the modulator signal.

Using this method, the DSM can generate the following types of key modulation schemes:

• Frequency-Shift Keying (FSK)

• Phase-Shift Keying (PSK)

• On-Off Keying (OOK)

Additionally, the following features are provided within the DSM module:

• Carrier Synchronization

• Carrier Source Polarity Select

• Programmable Modulator Data

• Modulated Output Polarity Select

• Peripheral Module Disable, which provides the ability to place the DSM module in the lowest power

consumption mode

The figure below shows a simplified block diagram of the data signal modulator peripheral.

PIC18F26/45/46Q10

(DSM) Data Signal Modulator Module

Figure 26-1. Simplified Block Diagram of the Data Signal Modulator

Rev. 10-000248E

8/7/2015

D

Q

D

Q

SYNC

MDOPOL

MDCHPOL

MDCLPOL

MDCLSYNC

MDCHSYNC

CARL

CARH

MOD

MDCHS<2:0>

MDCLS<2:0>

Data Signal Modulator

1

0

1

0

000

See

MDCARH

Register

111

000

See

MDCARL

Register

111

MDSRCS<3:0>

0000

See

MDSRC

Register

1111

PPS

RxyPPS

PIC18F26/45/46Q10

(DSM) Data Signal Modulator Module

26.1 DSM Operation

The DSM module can be enabled by setting the EN bit in the MDCON0 register. Clearing the EN bit,

disables the output of the module but retain the carrier and source signal selections. The module will

resume operation when the EN bit is set again. The output of the DSM module can be rerouted to several

pins using the RxyPPS register. When the EN bit is cleared the output pin is held low.

26.2 Modulator Signal Sources

The modulator signal can be supplied from the following sources selected with the SRCS bits:

Table 26-1. MDSRC Selection MUX Connections

SRCS[3:0] Connection

11000-11111 Reserved

10111 CLC8_out

10110 CLC7_out

10101 CLC6_out

10100 CLC5_out

10011 CLC4_out

10010 CLC3_out

10001 CLC2_out

10000 CLC1_out

01111 Reserved

01110 Reserved

01101 EUSART2 TX (TX/CK output)

01100 EUSART2 RX (DT output)

01011 MSSP2 - SDO

01010 MSSP1 - SDO

01001 EUSART1 TX (TX/CK output)

01000 EUSART1 RX (DT output)

00111 CMP2 OUT

00110 CMP1 OUT

00101 PWM4 OUT

00100 PWM3 OUT

00011 CCP2 OUT

00010 CCP1 OUT

00001 MDBIT

PIC18F26/45/46Q10

(DSM) Data Signal Modulator Module

...........continued

SRCS[3:0] Connection

00000 Pin selected by MDSRCPPS

26.3 Carrier Signal Sources

The carrier high signal and carrier low signal can be supplied from the following sources.

The carrier high signal is selected by configuring the CHS bits.

Table 26-2. MDCARH Source Selections

MDCARH

CHS[2:0] Connection

1111 CLC8_out

1110 CLC7_out

1101 CLC6_out

1100 CLC5_out

1011 CLC4_out

1010 CLC3_out

1001 CLC2_out

1000 CLC1_out

0111 PWM4 OUT

0110 PWM3 OUT

0101 CCP2 OUT

0100 CCP1 OUT

0011 CLKREF output

0010 HFINTOSC

0001 FOSC (system clock)

0000 Pin selected by MDCARHPPS

The carrier low signal is selected by configuring the CLS bits.

Table 26-3. MDCARL Source Selections

MDCARL

CLS[2:0] Connection

1111 CLC8_out

1110 CLC7_out

1101 CLC6_out

PIC18F26/45/46Q10

(DSM) Data Signal Modulator Module

...........continued

MDCARL

CLS[2:0] Connection

1100 CLC5_out

1011 CLC4_out

1010 CLC3_out

1001 CLC2_out

1000 CLC1_out

0111 PWM4 OUT

0110 PWM3 OUT

0101 CCP2 OUT

0100 CCP1 OUT

0011 CLKREF output

0010 HFINTOSC

0001 FOSC (system clock)

0000 Pin selected by MDCARLPPS

26.4 Carrier Synchronization

During the time when the DSM switches between carrier high and carrier low signal sources, the carrier

data in the modulated output signal can become truncated. To prevent this, the carrier signal can be

synchronized to the modulator signal. When synchronization is enabled, the carrier pulse that is being

mixed at the time of the transition is allowed to transition low before the DSM switches over to the next

carrier source.

Synchronization is enabled separately for the carrier high and carrier low signal sources. Synchronization

for the carrier high signal is enabled by setting the CHSYNC bit. Synchronization for the carrier low signal

is enabled by setting the CLSYNC bit.

The figures below show the timing diagrams of using various synchronization methods.

PIC18F26/45/46Q10

(DSM) Data Signal Modulator Module

Figure 26-2. On Off Keying (OOK) Synchronization

modulator

carrier_high

carrier_low

MDCHSYNC = 1

MDCLSYNC = 0

MDCHSYNC = 1

MDCLSYNC = 1

MDCHSYNC = 0

MDCLSYNC = 0

MDCHSYNC = 0

MDCLSYNC = 1

Rev. 30-000144A

5/26/2017

Figure 26-3. No Synchronization (MDCHSYNC = 0, MDCLSYNC = 0)

MDCHSYNC = 0

MDCLSYNC = 0

modulator

carrier_high

carrier_low

Active Carrier carrier_high carrier_low carrier_low

carrier_high

State

Rev. 30-000145A

5/26/2017

Figure 26-4. Carrier High Synchronization (MDCHSYNC = 1, MDCLSYNC = 0)

MDCHSYNC = 1

MDCLSYNC = 0

modulator

carrier_high

carrier_low

Active Carrier

carrier_high carrier_low carrier_low

carrier_high

State

both both

Rev. 30-000146A

5/26/2017

PIC18F26/45/46Q10

(DSM) Data Signal Modulator Module

Figure 26-5. Carrier Low Synchronization (MDCHSYNC = 0, MDCLSYNC = 1)

MDCHSYNC = 0

MDCLSYNC = 1

modulator

carrier_high

carrier_low

Active Carrier carrier_high carrier_low carrier_low

carrier_high

State

Rev. 30-000147A

5/26/2017

Figure 26-6. Full Synchronization (MDCHSYNC = 1, MDCLSYNC = 1)

MDCHSYNC = 1

MDCLSYNC = 1

modulator

carrier_high

carrier_low

Active Carrier carrier_high carrier_low CL

carrier_high

State

Falling edges

used to sync

Rev. 30-000148A

5/26/2017

26.5 Carrier Source Polarity Select

The signal provided from any selected input source for the carrier high and carrier low signals can be

inverted. Inverting the signal for the carrier high and low source is enabled by setting the CHPOL bit and

the CLPOL bit, respectively.

26.6 Programmable Modulator Data

The BIT control bit can be selected as the modulation source. This gives the user the ability to provide

software driven modulation.

26.7 Modulated Output Polarity

The modulated output signal provided on the DSM pin can also be inverted. Inverting the modulated

output signal is enabled by setting the OPOL bit.

26.8 Operation in Sleep Mode

The DSM can still operate during Sleep, if the carrier and modulator input sources are also still operable

during Sleep. Refer to “Power-Saving Operation Modes” for more details.

Related Links

6.4 Peripheral Operation in Power-Saving Modes

PIC18F26/45/46Q10

(DSM) Data Signal Modulator Module

26.9 Effects of a Reset

Upon any device Reset, the DSM module is disabled. The user’s firmware is responsible for initializing

the module before enabling the output. All the registers are reset to their default values.

26.10 Peripheral Module Disable

The DSM module can be completely disabled using the PMD module to achieve maximum power saving.

When the DSMMD bit of PMDx register is set, the DSM module is completely disabled. This puts the

module in its lowest power consumption state. When enabled again all the registers of the DSM module

default to POR status.

Related Links

7.4 Register Definitions: Peripheral Module Disable

PIC18F26/45/46Q10

(DSM) Data Signal Modulator Module

26.11 Register Summary - DSM

Address Name Bit Pos.

0x0F4C MDCON0 7:0 EN OUT OPOL BIT

0x0F4D MDCON1 7:0 CHPOL CHSYNC CLPOL CLSYNC

0x0F4E MDSRC 7:0 SRCS[4:0]

0x0F4F MDCARL 7:0 CLS[3:0]

0x0F50 MDCARH 7:0 CHS[3:0]

26.12 Register Definitions: Modulation Control

Long bit name prefixes for the modulation control peripherals are shown in the table below. Refer to the

"Long Bit Names Section" for more information.

Table 26-4. Modulation Control Long Bit Name Prefixes

Peripheral Bit Name Prefix

MD MD

Related Links

1.4.2.2 Long Bit Names

PIC18F26/45/46Q10

(DSM) Data Signal Modulator Module

26.12.1 MDCON0

Name: MDCON0

Address: 0xF4C

Modulation Control Register 0

Bit 7 6 5 4 3 2 1 0

EN OUT OPOL BIT

Access R/W R/W R/W R/W

Reset 0 0 0 0

Bit 7 – EN Modulator Module Enable bit

Value Description

1Modulator module is enabled and mixing input signals

0Modulator module is disabled and has no output

Bit 5 – OUT Modulator Output bit

Displays the current output value of the modulator module.

Bit 4 – OPOL Modulator Output Polarity Select bit

Value Description

1Modulator output signal is inverted; idle high output

0Modulator output signal is not inverted; idle low output

Bit 0 – BIT Modulation Source Select Input bit

Allows software to manually set modulation source input to module

Note:

1. The modulated output frequency can be greater and asynchronous from the clock that updates this

register bit, the bit value may not be valid for higher speed modulator or carrier signals.

2. MDBIT must be selected as the modulation source in the MDSRC register for this operation.

PIC18F26/45/46Q10

(DSM) Data Signal Modulator Module

26.12.2 MDCON1

Name: MDCON1

Address: 0xF4D

Modulation Control Register 1

Bit 7 6 5 4 3 2 1 0

CHPOL CHSYNC CLPOL CLSYNC

Access R/W R/W R/W R/W

Reset 0 0 0 0

Bit 5 – CHPOL Modulator High Carrier Polarity Select bit

Value Description

1Selected high carrier signal is inverted

0Selected high carrier signal is not inverted

Bit 4 – CHSYNC Modulator High Carrier Synchronization Enable bit

Value Description

1Modulator waits for a falling edge on the high time carrier signal before allowing a switch to

the low time carrier

0Modulator output is not synchronized to the high time carrier signal

Bit 1 – CLPOL Modulator Low Carrier Polarity Select bit

Value Description

1Selected low carrier signal is inverted

0Selected low carrier signal is not inverted

Bit 0 – CLSYNC Modulator Low Carrier Synchronization Enable bit

Value Description

1Modulator waits for a falling edge on the low time carrier signal before allowing a switch to

the high time carrier

0Modulator output is not synchronized to the low time carrier signal

Note:

1. Narrowed carrier pulse widths or spurs may occur in the signal stream if the carrier is not

synchronized.

PIC18F26/45/46Q10

(DSM) Data Signal Modulator Module

26.12.3 MDCARH

Name: MDCARH

Address: 0xF50

Modulation High Carrier Control Register

Bit 7 6 5 4 3 2 1 0

CHS[3:0]

Access R/W R/W R/W R/W

Reset 0 0 0 0

Bits 3:0 – CHS[3:0] Modulator Carrier High Selection bits

Table 26-5. MDCARH Source Selections

MDCARH

CHS[2:0] Connection

1111 CLC8_out

1110 CLC7_out

1101 CLC6_out

1100 CLC5_out

1011 CLC4_out

1010 CLC3_out

1001 CLC2_out

1000 CLC1_out

0111 PWM4 OUT

0110 PWM3 OUT

0101 CCP2 OUT

0100 CCP1 OUT

0011 CLKREF output

0010 HFINTOSC

0001 FOSC (system clock)

0000 Pin selected by MDCARHPPS

PIC18F26/45/46Q10

(DSM) Data Signal Modulator Module

26.12.4 MDCARL

Name: MDCARL

Address: 0xF4F

Modulation Low Carrier Control Register

Bit 7 6 5 4 3 2 1 0

CLS[3:0]

Access R/W R/W R/W R/W

Reset 0 0 0 0

Bits 3:0 – CLS[3:0] Modulator Carrier Low Input Selection bits

Table 26-6. MDCARL Source Selections

MDCARL

CLS[2:0] Connection

1111 CLC8_out

1110 CLC7_out

1101 CLC6_out

1100 CLC5_out

1011 CLC4_out

1010 CLC3_out

1001 CLC2_out

1000 CLC1_out

0111 PWM4 OUT

0110 PWM3 OUT

0101 CCP2 OUT

0100 CCP1 OUT

0011 CLKREF output

0010 HFINTOSC

0001 FOSC (system clock)

0000 Pin selected by MDCARLPPS

PIC18F26/45/46Q10

(DSM) Data Signal Modulator Module

26.12.5 MDSRC

Name: MDSRC

Address: 0xF4E

Modulation Source Control Register

Bit 7 6 5 4 3 2 1 0

SRCS[4:0]

Access R/W R/W R/W R/W R/W

Reset 0 0 0 0 0

Bits 4:0 – SRCS[4:0] Modulator Source Selection bits

Table 26-7. MDSRC Selection MUX Connections

SRCS[3:0] Connection

11000-11111 Reserved

10111 CLC8_out

10110 CLC7_out

10101 CLC6_out

10100 CLC5_out

10011 CLC4_out

10010 CLC3_out

10001 CLC2_out

10000 CLC1_out

01111 Reserved

01110 Reserved

01101 EUSART2 TX (TX/CK output)

01100 EUSART2 RX (DT output)

01011 MSSP2 - SDO

01010 MSSP1 - SDO

01001 EUSART1 TX (TX/CK output)

01000 EUSART1 RX (DT output)

00111 CMP2 OUT

00110 CMP1 OUT

00101 PWM4 OUT

00100 PWM3 OUT

00011 CCP2 OUT

PIC18F26/45/46Q10

(DSM) Data Signal Modulator Module

...........continued

SRCS[3:0] Connection

00010 CCP1 OUT

00001 MDBIT

00000 Pin selected by MDSRCPPS

PIC18F26/45/46Q10

(DSM) Data Signal Modulator Module

27. (MSSP) Master Synchronous Serial Port Module

The Master Synchronous Serial Port (MSSP) module is a serial interface useful for communicating with

other peripheral or microcontroller devices. These peripheral devices may be serial EEPROMs, Shift

registers, display drivers, A/D converters, etc. The MSSP module can operate in one of two modes:

• Serial Peripheral Interface (SPI)

• Inter-Integrated Circuit (I2C)

The SPI interface supports the following modes and features:

• Master mode

• Slave mode

• Clock Parity

• Slave Select Synchronization (Slave mode only)

• Daisy-chain connection of slave devices

The I2C interface supports the following modes and features:

• Master mode

• Slave mode

• Byte NACKing (Slave mode)

• Limited multi-master support

• 7-bit and 10-bit addressing

• Start and Stop interrupts

• Interrupt masking

• Clock stretching

• Bus collision detection

• General call address matching

• Address masking

• Address Hold and Data Hold modes

• Selectable SDA hold times

27.1 SPI Mode Overview

The Serial Peripheral Interface (SPI) bus is a synchronous serial data communication bus that operates

in Full-Duplex mode. Devices communicate in a master/slave environment where the master device

initiates the communication. A slave device is controlled through a Chip Select known as Slave Select.

The SPI bus specifies four signal connections:

• Serial Clock (SCK)

• Serial Data Out (SDO)

• Serial Data In (SDI)

• Slave Select (SS)

The following figure shows the block diagram of the MSSP module when operating in SPI mode.

PIC18F26/45/46Q10

(MSSP) Master Synchronous Serial Port Module

Figure 27-1. MSSP Block Diagram (SPI mode)



( )

Read Write

Data Bus

SSPSR Reg

SSPM<3:0>

bit 0 Shift

Clock

SS Control

Enable

Edge

Select

Clock Select

T2_match

2

Edge

Select

2 (CKP, CKE)

4

TRIS bit

SDO

SSPxBUF Reg

SDI

SS

SCK

TOSC

Prescaler

4, 16, 64

Baud Rate

Generator

(SSPxADD)

PPS

SSPxDATPPS

RxyPPS

SSPxCLKPPS(2)

PPS

RxyPPS(1)

SSPxSSPPS

Note 1: Output selection for master mode

2: Input selection for slave and master mode

Rev. 30-000011A

3/31/2017

The SPI bus operates with a single master device and one or more slave devices. When multiple slave

devices are used, an independent Slave Select connection is required from the master device to each

slave device.

The figure below shows a typical connection between a master device and multiple slave devices.

The master selects only one slave at a time. Most slave devices have tri-state outputs so their output

signal appears disconnected from the bus when they are not selected.

PIC18F26/45/46Q10

(MSSP) Master Synchronous Serial Port Module

Figure 27-2. SPI Master and Multiple Slave Connection



SPI Master SCK

SDO

SDI

General I/O

SCK

SDI

SDO

SS

SPI Slave

#1

SCK

SDI

SDO

SS

SPI Slave

#2

SCK

SDI

SDO

SS

SPI Slave

#3

Rev. 30-000012A

3/31/2017

27.1.1 SPI Mode Registers

The MSSP module has five registers for SPI mode operation. These are:

• MSSP STATUS register (SSPxSTAT)

• MSSP Control register 1 (SSPxCON1)

• MSSP Control register 3 (SSPxCON3)

• MSSP Data Buffer register (SSPxBUF)

• MSSP Address register (SSPxADD)

• MSSP Shift register (SSPSR)

(Not directly accessible)

SSPxCON1 and SSPxSTAT are the control and STATUS registers for SPI mode operation. The

SSPxCON1 register is readable and writable. The lower six bits of the SSPxSTAT are read-only. The

upper two bits of the SSPxSTAT are read/write.

One of the five SPI Master modes uses the SSPxADD value to determine the Baud Rate Generator clock

frequency. More information on the Baud Rate Generator is available in 27.7 Baud Rate Generator.

SSPSR is the Shift register used for shifting data in and out. SSPxBUF provides indirect access to the

SSPSR register. SSPxBUF is the Buffer register to which data bytes are written, and from which data

bytes are read.

In receive operations, SSPSR and SSPxBUF together create a buffered receiver. When SSPSR receives

a complete byte, it is transferred to SSPxBUF and the SSPxIF interrupt is set.

During transmission, the SSPxBUF is not buffered. A write to SSPxBUF will write to both SSPxBUF and

SSPSR.

27.2 SPI Mode Operation

Transmissions involve two Shift registers, eight bits in size, one in the master and one in the slave. With

either the master or the slave device, data is always shifted out one bit at a time, with the Most Significant

PIC18F26/45/46Q10

(MSSP) Master Synchronous Serial Port Module

bit (MSb) shifted out first. At the same time, a new Least Significant bit (LSb) is shifted into the same

register.

The following figure shows a typical connection between two processors configured as master and slave

devices.

Figure 27-3. SPI Master/Slave Connection



Serial Input Buffer

(BUF)

Shift Register

(SSPSR)

MSb LSb

SDO

SDI

Processor 1

SCK

SPI Master SSPM<3:0> = 00xx

Serial Input Buffer

(SSPxBUF)

Shift Register

Processor 2

SCK

SPI Slave SSPM<3:0> = 010x

Serial Clock

SS

Slave Select

General I/O (optional)

=1010

(SSPSR)

LSb

MSb

SDI

SDO

Rev/ 30-000013A

3/31/2017

Data is shifted out of both Shift registers on the programmed clock edge and latched on the opposite

edge of the clock.

The master device transmits information out on its SDO output pin, which is connected to and received by

the slave’s SDI input pin. The slave device transmits information out on its SDO output pin, which is

connected to and received by the master’s SDI input pin.

To begin communication the master device first sends out the clock signal. Both the master and the slave

devices should be configured for the same clock polarity.

The master device starts a transmission by sending out the MSb from its Shift register. The slave device

reads this bit from that same line and saves it into the LSb position of its Shift register.

During each SPI clock cycle, a full-duplex data transmission occurs. This means that while the master

device is sending out the MSb from its Shift register (on its SDO pin) and the slave device is reading this

bit and saving it as the LSb of its Shift register, the slave device is also sending out the MSb from its Shift

register (on its SDO pin) and the master device is reading this bit and saving it as the LSb of its Shift

register.

After eight bits have been shifted out, the master and slave have exchanged register values.

If there is more data to exchange, the Shift registers are loaded with new data and the process repeats

itself.

Whether the data is meaningful or not (dummy data), depends on the application software. This leads to

three scenarios for data transmission:

• Master sends useful data and slave sends dummy data.

• Master sends useful data and slave sends useful data.

PIC18F26/45/46Q10

(MSSP) Master Synchronous Serial Port Module

• Master sends dummy data and slave sends useful data.

Transmissions may involve any number of clock cycles. When there is no more data to be transmitted,

the master stops sending the clock signal and it deselects the slave.

Every slave device connected to the bus that has not been selected through its slave select line must

disregard the clock and transmission signals and must not transmit out any data of its own.

When initializing the SPI several options need to be specified. This is done by programming the

appropriate control bits (SSPxCON1<5:0> and SSPxSTAT<7:6>). These control bits allow the following to

be specified:

• Master mode (SCK is the clock output)

• Slave mode (SCK is the clock input)

• Clock Polarity (Idle state of SCK)

• Data Input Sample Phase (middle or end of data output time)

• Clock Edge (output data on rising/falling edge of SCK)

• Clock Rate (Master mode only)

• Slave Select mode (Slave mode only)

To enable the serial port the SSP Enable bit, SSPEN, must be set. To reset or reconfigure SPI mode,

clear the SSPEN bit, re-initialize the SSPxCONx registers and then set the SSPEN bit. The SDI, SDO,

SCK and SS serial port pins are selected with the PPS controls. For the pins to behave as the serial port

function, some must have their data direction bits (in the TRIS register) appropriately programmed as

follows:

• SDI must have corresponding TRIS bit set

• SDO must have corresponding TRIS bit cleared

• SCK (Master mode) must have corresponding TRIS bit cleared

• SCK (Slave mode) must have corresponding TRIS bit set

• The RxyPPS and SSPxCLKPPS controls must select the same pin

• SS must have corresponding TRIS bit set

Any serial port function that is not desired may be overridden by programming the corresponding data

direction (TRIS) register to the opposite value.

The MSSP consists of a transmit/receive shift register (SSPSR) and a buffer register (SSPxBUF). The

SSPSR shifts the data in and out of the device, MSb first. The SSPxBUF holds the data that was written

to the SSPSR until the received data is ready. Once the eight bits of data have been received, that byte is

moved to the SSPxBUF register. Then, the Buffer Full Detect bit, BF, and the Interrupt Flag bit, SSPxIF,

are set. This double-buffering of the received data (SSPxBUF) allows the next byte to start reception

before reading the data that was just received. Any write to the SSPxBUF register during transmission/

reception of data will be ignored and the write collision detect bit, WCOL, will be set. User software must

clear the WCOL bit to allow the following write(s) to the SSPxBUF register to complete successfully.

When the application software is expecting to receive valid data, the SSPxBUF should be read before the

next byte of data to transfer is written to the SSPxBUF. The Buffer Full bit, BF, indicates when SSPxBUF

has been loaded with the received data (transmission is complete). When the SSPxBUF is read, the BF

bit is cleared. This data may be irrelevant if the SPI is only a transmitter. Generally, the MSSP interrupt is

used to determine when the transmission/reception has completed. If the interrupt method is not going to

be used, then software polling can be done to ensure that a write collision does not occur.

PIC18F26/45/46Q10

(MSSP) Master Synchronous Serial Port Module

The SSPSR is not directly readable or writable and can only be accessed by addressing the SSPxBUF

register. Additionally, the SSPxSTAT register indicates the various Status conditions.

27.2.1 SPI Master Mode

The master can initiate the data transfer at any time because it controls the SCK line. The master

determines when the slave (Processor 2, Figure 27-3) is to broadcast data by the software protocol.

In Master mode, the data is transmitted/received as soon as the SSPxBUF register is written to. If the SPI

is only going to receive, the SDO output could be disabled (programmed as an input). The SSPSR

register will continue to shift in the signal present on the SDI pin at the programmed clock rate. As each

byte is received, it will be loaded into the SSPxBUF register as if a normal received byte (interrupts and

Status bits appropriately set).

The clock polarity is selected by appropriately programming the CKP bit and the CKE bit. This then,

would give waveforms for SPI communication as shown in Figure 27-4, Figure 27-6, Figure 27-7 and

Figure 27-8, where the MSB is transmitted first. In Master mode, the SPI clock rate (bit rate) is user

programmable to be one of the following:

• FOSC/4 (or TCY)

• FOSC/16 (or 4 * TCY)

• FOSC/64 (or 16 * TCY)

• Timer2 output/2

• FOSC/(4 * (SSPxADD + 1))

Figure 27-4 shows the waveforms for Master mode.

When the CKE bit is set, the SDO data is valid before there is a clock edge on SCK. The change of the

input sample is shown based on the state of the SMP bit. The time when the SSPxBUF is loaded with the

received data is shown.

Important: In Master mode the clock signal output to the SCK pin is also the clock signal input

to the peripheral. The pin selected for output with the RxyPPS register must also be selected as

the peripheral input with the SSPxCLKPPS register. The pin that is selected using the

SSPxCLKPPS register should also be made a digital I/O. This is done by clearing the

corresponding ANSEL bit.

PIC18F26/45/46Q10

(MSSP) Master Synchronous Serial Port Module

Figure 27-4. SPI Mode Waveform (Master Mode)



SCK

(CKP = 0

SCK

(CKP = 1

SCK

(CKP = 0

SCK

(CKP = 1

4 Clock

Modes

Input

Sample

Input

Sample

SDI

bit 7 bit 0

SDO bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0

bit 7

SDI

SSPxIF

(SMP = 1)

(SMP = 0)

(SMP = 1)

CKE = 1)

CKE = 0)

CKE = 1)

CKE = 0)

(SMP = 0)

Write to

SSPxBUF

SSPSR to

SSPxBUF

SDO bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0

(CKE = 0)

(CKE = 1)

bit 0

Rev. 30-000014A

3/13/2017

27.2.2 SPI Slave Mode

In Slave mode, the data is transmitted and received as external clock pulses appear on SCK. When the

last bit is latched, the SSPxIF Interrupt Flag bit is set.

Before enabling the module in SPI Slave mode, the clock line must match the proper Idle state. The clock

line can be observed by reading the SCK pin. The Idle state is determined by the CKP bit.

While in Slave mode, the external clock is supplied by the external clock source on the SCK pin. This

external clock must meet the minimum high and low times as specified in the electrical specifications.

While in Sleep mode, the slave can transmit/receive data. The Shift register is clocked from the SCK pin

input and when a byte is received, the device will generate an interrupt. If enabled, the device will wake-

up from Sleep.

27.2.3 Daisy-Chain Configuration

The SPI bus can sometimes be connected in a daisy-chain configuration. The first slave output is

connected to the second slave input, the second slave output is connected to the third slave input, and so

on. The final slave output is connected to the master input. Each slave sends out, during a second group

of clock pulses, an exact copy of what was received during the first group of clock pulses. The whole

PIC18F26/45/46Q10

(MSSP) Master Synchronous Serial Port Module

chain acts as one large communication shift register. The daisy-chain feature only requires a single Slave

Select line from the master device.

The following figure shows the block diagram of a typical daisy-chain connection when operating in SPI

mode.

Figure 27-5. SPI Daisy-Chain Connection



SPI Master SCK

SDO

SDI

General I/O

SCK

SDI

SDO

SS

SPI Slave

#1

SCK

SDI

SDO

SS

SPI Slave

#2

SCK

SDI

SDO

SS

SPI Slave

#3

Rev. 30-000015A

3/31/2017

In a daisy-chain configuration, only the most recent byte on the bus is required by the slave. Setting the

BOEN bit will enable writes to the SSPxBUF register, even if the previous byte has not been read. This

allows the software to ignore data that may not apply to it.

27.2.4 Slave Select Synchronization

The Slave Select can also be used to synchronize communication. The Slave Select line is held high until

the master device is ready to communicate. When the Slave Select line is pulled low, the slave knows

that a new transmission is starting.

If the slave fails to receive the communication properly, it will be reset at the end of the transmission,

when the Slave Select line returns to a high state. The slave is then ready to receive a new transmission

when the Slave Select line is pulled low again. If the Slave Select line is not used, there is a risk that the

slave will eventually become out of sync with the master. If the slave misses a bit, it will always be one bit

off in future transmissions. Use of the Slave Select line allows the slave and master to align themselves at

the beginning of each transmission.

The SS pin allows a Synchronous Slave mode. The SPI must be in Slave mode with SS pin control

enabled (SSPM = 0100).

When the SS pin is low, transmission and reception are enabled and the SDO pin is driven.

When the SS pin goes high, the SDO pin is no longer driven, even if in the middle of a transmitted byte

and becomes a floating output. External pull-up/pull-down resistors may be desirable depending on the

application.

PIC18F26/45/46Q10

(MSSP) Master Synchronous Serial Port Module

Note:

1. When the SPI is in Slave mode with SS pin control enabled (SSPM = 0100), the SPI module will

reset if the SS pin is set to VDD.

2. When the SPI is used in Slave mode with CKE set; the user must enable SS pin control.

3. While operated in SPI Slave mode the SMP bit must remain clear.

When the SPI module resets, the bit counter is forced to ‘0’. This can be done by either forcing the SS pin

to a high level or clearing the SSPEN bit.

Figure 27-6. Slave Select Synchronous Waveform



SCK

(CKP = 1

SCK

(CKP = 0

Input

Sample

SDI

bit 7

SDO bit 7 bit 6 bit 7

SSPxIF

Interrupt

CKE = 0)

Write to

SSPxBUF

SSPSR to

SSPxBUF

SS

Flag

bit 0

bit 7

bit 0

bit 6

SSPxBUF to

SSPSR

Shift register SSPSR

and bit count are reset

Rev. 30-000016A

4/10/2017

PIC18F26/45/46Q10

(MSSP) Master Synchronous Serial Port Module

Figure 27-7. SPI Mode Waveform (Slave Mode with CKE = 0)

SCK

(CKP = 1

SCK

(CKP = 0

Input

Sample

SDI

bit 7

SDO bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0

SSPxIF

Interrupt

CKE = 0)

Write to

SSPxBUF

SSPSR to

SSPxBUF

SS

Flag

Optional

bit 0

detection active

Write Collision

Valid

Rev. 30-000017A

4/3/2017

Figure 27-8. SPI Mode Waveform (Slave Mode with CKE = 1)

SCK

(CKP = 1

SCK

(CKP = 0

Input

Sample

SDI

bit 7 bit 0

SDO bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0

SSPxIF

Interrupt

CKE = 1)

Write to

SSPxBUF

SSPSR to

SSPxBUF

SS

Flag

Not Optional

Write Collision

detection active

Valid

Rev. 30-000018A

4/1/2017

PIC18F26/45/46Q10

(MSSP) Master Synchronous Serial Port Module

27.2.5 SPI Operation in Sleep Mode

In SPI Master mode, module clocks may be operating at a different speed than when in Full-Power mode;

in the case of the Sleep mode, all clocks are halted.

Special care must be taken by the user when the MSSP clock is much faster than the system clock.

In Slave mode, when MSSP interrupts are enabled, after the master completes sending data, an MSSP

interrupt will wake the controller from Sleep.

If an exit from Sleep mode is not desired, MSSP interrupts should be disabled.

In SPI Master mode, when the Sleep mode is selected, all module clocks are halted and the

transmission/reception will remain in that state until the device wakes. After the device returns to Run

mode, the module will resume transmitting and receiving data.

In SPI Slave mode, the SPI Transmit/Receive Shift register operates asynchronously to the device. This

allows the device to be placed in Sleep mode and data to be shifted into the SPI Transmit/Receive Shift

register. When all eight bits have been received, the MSSP interrupt flag bit will be set and if enabled, will

wake the device.

27.3 I2C Mode Overview

The Inter-Integrated Circuit (I2C) bus is a multi-master serial data communication bus. Devices

communicate in a master/slave environment where the master devices initiate the communication. A

slave device is controlled through addressing. The following two diagrams show block diagrams of the I2C

Master and Slave modes, respectively.

PIC18F26/45/46Q10

(MSSP) Master Synchronous Serial Port Module

Figure 27-9. MSSP Block Diagram (I2C Master mode)

Read Write

SSPSR

Start bit, Stop bit,

Start bit detect,

SSPxBUF

Internal

data bus

Set/Reset: S, P, SSPxSTAT, WCOL, SSPOV

Shift

Clock

MSb LSb

SDA

Acknowledge

Generate (SSPxCON2)

Stop bit detect

Write collision detect

Clock arbitration

State counter for

end of XMIT/RCV

SCL

SCL in

Bus Collision

SDA in

Receive Enable (RCEN)

Clock Cntl

Clock arbitrate/BCOL detect

(Hold off clock source)

[SSPM<3:0>]

Baud Rate

Reset SEN, PEN (SSPxCON2)

Generator

(SSPxADD)

Address Match detect

Set SSP1IF, BCL1IF

PPS

SSPxDATPPS(1)

PPS

Note 1: SDA pin selections must be the same for input and output

2: SCL pin selections must be the same for input and output

PPS

RxyPPS(1)

PPS

SSPxCLKPPS(2)

RxyPPS(1)

RxyPPS(2)

Rev. 30-000019A

4/3/2017

PIC18F26/45/46Q10

(MSSP) Master Synchronous Serial Port Module

Figure 27-10. MSSP Block Diagram (I2C Slave mode)

Read Write

SSPSR Reg

Match Detect

SSPxADD Reg

Start and

Stop bit Detect

SSPxBUF Reg

Internal

Data Bus

Addr Match

Set, Reset

S, P bits

(SSPxSTAT Reg)

SCL

Shift

Clock

MSb LSb

SSPxMSK Reg

PPS

SSPxCLKPPS(2)

RxyPPS(2)

Clock

Stretching

SDA

PPS

SSPxDATPPS(1)

RxyPPS(1)

Note 1: SDA pin selections must be the same for input and output

2: SCL pin selections must be the same for input and output

Rev. 30-000020A

4/3/2017

The I2C bus specifies two signal connections:

• Serial Clock (SCL)

• Serial Data (SDA)

Both the SCL and SDA connections are bidirectional open-drain lines, each requiring pull-up resistors for

the supply voltage. Pulling the line to ground is considered a logical zero and letting the line float is

considered a logical one.

The following diagram shows a typical connection between two processors configured as master and

slave devices.

Figure 27-11. I2C Master/

Slave Connection

Master

SCL

SDA

SCL

SDA

Slave

VDD

Rev. 30-000021A

4/3/2017

The I2C bus can operate with one or more master devices and one or more slave devices.

There are four potential modes of operation for a given device:

• Master Transmit mode

(master is transmitting data to a slave)

PIC18F26/45/46Q10

(MSSP) Master Synchronous Serial Port Module

• Master Receive mode

(master is receiving data from a slave)

• Slave Transmit mode

(slave is transmitting data to a master)

• Slave Receive mode

(slave is receiving data from the master)

To begin communication, a master device starts out in Master Transmit mode. The master device sends

out a Start bit followed by the address byte of the slave it intends to communicate with. This is followed by

a single Read/Write bit, which determines whether the master intends to transmit to or receive data from

the slave device.

If the requested slave exists on the bus, it will respond with an Acknowledge bit, otherwise known as an

ACK. The master then continues in either Transmit mode or Receive mode and the slave continues in the

complement, either in Receive mode or Transmit mode, respectively.

A Start bit is indicated by a high-to-low transition of the SDA line while the SCL line is held high. Address

and data bytes are sent out, Most Significant bit (MSb) first. The Read/Write bit is sent out as a logical

one when the master intends to read data from the slave, and is sent out as a logical zero when it intends

to write data to the slave.

The Acknowledge bit (ACK) is an active-low signal, which holds the SDA line low to indicate to the

transmitter that the slave device has received the transmitted data and is ready to receive more.

The transition of a data bit is always performed while the SCL line is held low. Transitions that occur while

the SCL line is held high are used to indicate Start and Stop bits.

If the master intends to write to the slave, then it repeatedly sends out a byte of data, with the slave

responding after each byte with an ACK bit. In this example, the master device is in Master Transmit

mode and the slave is in Slave Receive mode.

If the master intends to read from the slave, then it repeatedly receives a byte of data from the slave, and

responds after each byte with an ACK bit. In this example, the master device is in Master Receive mode

and the slave is Slave Transmit mode.

On the last byte of data communicated, the master device may end the transmission by sending a Stop

bit. If the master device is in Receive mode, it sends the Stop bit in place of the last ACK bit. A Stop bit is

indicated by a low-to-high transition of the SDA line while the SCL line is held high.

In some cases, the master may want to maintain control of the bus and re-initiate another transmission. If

so, the master device may send another Start bit in place of the Stop bit or last ACK bit when it is in

Receive mode.

The I2C bus specifies three message protocols:

• Single message where a master writes data to a slave.

• Single message where a master reads data from a slave.

• Combined message where a master initiates a minimum of two writes, or two reads, or a combination

of writes and reads, to one or more slaves.

When one device is transmitting a logical one, or letting the line float, and a second device is transmitting

a logical zero, or holding the line low, the first device can detect that the line is not a logical one. This

detection, when used on the SCL line, is called clock stretching. Clock stretching gives slave devices a

mechanism to control the flow of data. When this detection is used on the SDA line, it is called arbitration.

Arbitration ensures that there is only one master device communicating at any single time.

PIC18F26/45/46Q10

(MSSP) Master Synchronous Serial Port Module

27.3.1 Register Definitions: I2C Mode

The MSSPx module has seven registers for I2C operation.

These are:

• MSSP Status register (SSPxSTAT)

• MSSP Control register 1 (SSPxCON1)

• MSSP Control register 2 (SSPxCON2)

• MSSP Control register 3 (SSPxCON3)

• Serial Receive/Transmit Buffer register (SSPxBUF)

• MSSP Address register (SSPxADD)

• I2C Slave Address Mask register (SSPxMSK)

• MSSP Shift register (SSPSR) – not directly accessible

SSPxCON1, SSPxCON2, SSPxCON3 and SSPxSTAT are the Control and STATUS registers in I2C mode

operation. The SSPxCON1, SSPxCON2, and SSPxCON3 registers are readable and writable. The lower

six bits of the SSPxSTAT are read-only. The upper two bits of the SSPxSTAT are read/write. SSPSR is

the Shift register used for shifting data in or out. SSPxBUF is the buffer register to which data bytes are

written to or read from. SSPxADD contains the slave device address when the MSSP is configured in I2C

Slave mode. When the MSSP is configured in Master mode, the lower seven bits of SSPxADD act as the

Baud Rate Generator reload value.

SSPxMSK holds the slave address mask value when the module is configured for 7-Bit Address Masking

mode. While it is a separate register, it shares the same SFR address as SSPxADD; it is only accessible

when the SSPM<3:0> bits are specifically set to permit access. In receive operations, SSPSR and

SSPxBUF together, create a double-buffered receiver. When SSPSR receives a complete byte, it is

transferred to SSPxBUF and the SSPxIF interrupt is set. During transmission, the SSPxBUF is not

double-buffered. A write to SSPxBUF will write to both SSPxBUF and SSPSR.

27.4 I2C Mode Operation

All MSSP I2C communication is byte oriented and shifted out MSb first. Six SFR registers and two

interrupt flags interface the module with the PIC® microcontroller and user software. Two pins, SDA and

SCL, are exercised by the module to communicate with other external I2C devices.

27.4.1 Clock Stretching

When a slave device has not completed processing data, it can delay the transfer of more data through

the process of clock stretching. An addressed slave device may hold the SCL clock line low after

receiving or sending a bit, indicating that it is not yet ready to continue. The master that is communicating

with the slave will attempt to raise the SCL line in order to transfer the next bit, but will detect that the

clock line has not yet been released. Because the SCL connection is open-drain, the slave has the ability

to hold that line low until it is ready to continue communicating.

Clock stretching allows receivers that cannot keep up with a transmitter to control the flow of incoming

data.

27.4.2 Arbitration

Each master device must monitor the bus for Start and Stop bits. If the device detects that the bus is

busy, it cannot begin a new message until the bus returns to an Idle state.

However, two master devices may try to initiate a transmission on or about the same time. When this

occurs, the process of arbitration begins. Each transmitter checks the level of the SDA data line and

PIC18F26/45/46Q10

(MSSP) Master Synchronous Serial Port Module

compares it to the level that it expects to find. The first transmitter to observe that the two levels do not

match, loses arbitration, and must stop transmitting on the SDA line.

For example, if one transmitter holds the SDA line to a logical one (lets it float) and a second transmitter

holds it to a logical zero (pulls it low), the result is that the SDA line will be low. The first transmitter then

observes that the level of the line is different than expected and concludes that another transmitter is

communicating.

The first transmitter to notice this difference is the one that loses arbitration and must stop driving the

SDA line. If this transmitter is also a master device, it also must stop driving the SCL line. It then can

monitor the lines for a Stop condition before trying to reissue its transmission. In the meantime, the other

device that has not noticed any difference between the expected and actual levels on the SDA line

continues with its original transmission. It can do so without any complications, because so far, the

transmission appears exactly as expected with no other transmitter disturbing the message.

Slave Transmit mode can also be arbitrated, when a master addresses multiple slaves, but this is less

common.

If two master devices are sending a message to two different slave devices at the address stage, the

master sending the lower slave address always wins arbitration. When two master devices send

messages to the same slave address, and addresses can sometimes refer to multiple slaves, the

arbitration process must continue into the data stage.

Arbitration usually occurs very rarely, but it is a necessary process for proper multi-master support.

27.4.3 Byte Format

All communication in I2C is done in 9-bit segments. A byte is sent from a master to a slave or vice versa,

followed by an Acknowledge bit sent back. After the eighth falling edge of the SCL line, the device

outputting data on the SDA changes that pin to an input and reads in an acknowledge value on the next

clock pulse.

The clock signal, SCL, is provided by the master. Data is valid to change while the SCL signal is low, and

sampled on the rising edge of the clock. Changes on the SDA line while the SCL line is high define

special conditions on the bus, explained below.

27.4.4 Definition of I2C Terminology

There is language and terminology in the description of I2C communication that have definitions specific

to I2C. That word usage is defined below and may be used in the rest of this document without

explanation. This table was adapted from the Philips I2C specification.

TERM Description

Transmitter The device that shifts data out onto the bus.

Receiver The device that shifts data in from the bus.

Master The device that initiates a transfer, generates clock signals and terminates a

transfer.

Slave The device addressed by the master.

Multi-master A bus with more than one device that can initiate data transfers.

Arbitration Procedure to ensure that only one master at a time controls the bus. Winning

arbitration ensures that the message is not corrupted.

PIC18F26/45/46Q10

(MSSP) Master Synchronous Serial Port Module

...........continued

TERM Description

Synchronization Procedure to synchronize the clocks of two or more devices on the bus.

Idle No master is controlling the bus, and both SDA and SCL lines are high.

Active Any time one or more master devices are controlling the bus.

Addressed Slave Slave device that has received a matching address and is actively being clocked by

a master.

Matching Address Address byte that is clocked into a slave that matches the value stored in SSPxADD.

Write Request Slave receives a matching address with R/W bit clear, and is ready to clock in data.

Read Request Master sends an address byte with the R/W bit set, indicating that it wishes to clock

data out of the Slave. This data is the next and all following bytes until a Restart or

Stop.

Clock Stretching When a device on the bus hold SCL low to stall communication.

Bus Collision Any time the SDA line is sampled low by the module while it is outputting and

expected high state.

27.4.5 SDA and SCL Pins

Selection of any I2C mode with the SSPEN bit set, forces the SCL and SDA pins to be open-drain. These

pins should be set by the user to inputs by setting the appropriate TRIS bits.

Note:

1. SDA is tied to output zero when an I2C mode is enabled.

2. Any device pin can be selected for SDA and SCL functions with the PPS peripheral. These

functions are bidirectional. The SDA input is selected with the SSPxDATPPS registers. The SCL

input is selected with the SSPxCLKPPS registers. Outputs are selected with the RxyPPS registers.

It is the user’s responsibility to make the selections so that both the input and the output for each

function is on the same pin.

27.4.6 SDA Hold Time

The hold time of the SDA pin is selected by the SDAHT bit. Hold time is the time SDA is held valid after

the falling edge of SCL. Setting the SDAHT bit selects a longer 300 ns minimum hold time and may help

on buses with large capacitance.

I2C Bus Terms

27.4.7 Start Condition

The I2C specification defines a Start condition as a transition of SDA from a high to a low state while SCL

line is high. A Start condition is always generated by the master and signifies the transition of the bus

from an Idle to an Active state. Figure 27-12 shows wave forms for Start and Stop conditions.

A bus collision can occur on a Start condition if the module samples the SDA line low before asserting it

low. This does not conform to the I2C Specification that states no bus collision can occur on a Start.

27.4.8 Stop Condition

A Stop condition is a transition of the SDA line from low-to-high state while the SCL line is high.

PIC18F26/45/46Q10

(MSSP) Master Synchronous Serial Port Module

Important: At least one SCL low time must appear before a Stop is valid, therefore, if the SDA

line goes low then high again while the SCL line stays high, only the Start condition is detected.

Figure 27-12. I2C Start and Stop Conditions



SDA

SCL

P

Stop

Condition

S

Start

Condition

Change of

Data Allowed

Change of

Data Allowed

Rev. 30-000022A

4/3/2017

27.4.9 Restart Condition

A Restart is valid any time that a Stop would be valid. A master can issue a Restart if it wishes to hold the

bus after terminating the current transfer. A Restart has the same effect on the slave that a Start would,

resetting all slave logic and preparing it to clock in an address. The master may want to address the

same or another slave. Figure 27-13 shows the wave form for a Restart condition.

In 10-bit Addressing Slave mode a Restart is required for the master to clock data out of the addressed

slave. Once a slave has been fully addressed, matching both high and low address bytes, the master can

issue a Restart and the high address byte with the R/W bit set. The slave logic will then hold the clock

and prepare to clock out data.

After a full match with R/W clear in 10-bit mode, a prior match flag is set and maintained until a Stop

condition, a high address with R/W clear, or high address match fails.

Figure 27-13. I2C Restart Condition



Restart

Condition

Sr

Change of

Data Allowed

Change of

Data Allowed

Rev. 30-000023A

4/3/2017

27.4.10 Start/Stop Condition Interrupt Masking

The SCIE and PCIE bits can enable the generation of an interrupt in Slave modes that do not typically

support this function. These bits will have no effect in Slave modes where interrupt on Start and Stop

detect are already enabled.

PIC18F26/45/46Q10

(MSSP) Master Synchronous Serial Port Module

27.4.11 Acknowledge Sequence

The ninth SCL pulse for any transferred byte in I2C is dedicated as an Acknowledge. It allows receiving

devices to respond back to the transmitter by pulling the SDA line low. The transmitter must release

control of the line during this time to shift in the response. The Acknowledge (ACK) is an active-low

signal, pulling the SDA line low indicates to the transmitter that the device has received the transmitted

data and is ready to receive more.

The result of an ACK is placed in the ACKSTAT bit.

Slave software, when the AHEN and DHEN bits are set, allow the user to set the ACK value sent back to

the transmitter. The ACKDT bit is set/cleared to determine the response.

Slave hardware will generate an ACK response if both the AHEN and DHEN bits are clear. However, tf

the BF bit or the SSPOV bit are set when a byte is received then the ACK will not be sent by the slave.

When the module is addressed, after the eighth falling edge of SCL on the bus, the ACKTIM bit is set.

The ACKTIM bit indicates the acknowledge time of the active bus. The ACKTIM Status bit is only active

when either the AHEN bit or DHEN bit is enabled.

27.5 I2C Slave Mode Operation

The MSSP Slave mode operates in one of four modes selected by the SSPM bits. The modes can be

divided into 7-bit and 10-bit Addressing mode. 10-bit Addressing modes operate the same as 7-bit with

some additional overhead for handling the larger addresses.

Modes with Start and Stop bit interrupts operate the same as the other modes with SSPxIF additionally

getting set upon detection of a Start, Restart, or Stop condition.

27.5.1 Slave Mode Addresses

The SSPxADD register contains the Slave mode address. The first byte received after a Start or Restart

condition is compared against the value stored in this register. If the byte matches, the value is loaded

into the SSPxBUF register and an interrupt is generated. If the value does not match, the module goes

idle and no indication is given to the software that anything happened.

The SSPxMSK register affects the address matching process. See 27.5.9 SSP Mask Register for more

information.

27.5.1.1 I2C Slave 7-bit Addressing Mode

In 7-bit Addressing mode, the LSb of the received data byte is ignored when determining if there is an

address match.

27.5.1.2 I2C Slave 10-bit Addressing Mode

In 10-bit Addressing mode, the first received byte is compared to the binary value of ‘1 1 1 1 0 A9 A8 0’.

A9 and A8 are the two MSb’s of the 10-bit address and stored in bits 2 and 1 of the SSPxADD register.

After the acknowledge of the high byte the UA bit is set and SCL is held low until the user updates

SSPxADD with the low address. The low address byte is clocked in and all eight bits are compared to the

low address value in SSPxADD. Even if there is not an address match; SSPxIF and UA are set, and SCL

is held low until SSPxADD is updated to receive a high byte again. When SSPxADD is updated the UA bit

is cleared. This ensures the module is ready to receive the high address byte on the next communication.

A high and low address match as a write request is required at the start of all 10-bit addressing

communication. A transmission can be initiated by issuing a Restart once the slave is addressed, and

clocking in the high address with the R/W bit set. The slave hardware will then acknowledge the read

PIC18F26/45/46Q10

(MSSP) Master Synchronous Serial Port Module

request and prepare to clock out data. This is only valid for a slave after it has received a complete high

and low address byte match.

27.5.2 Slave Reception

When the R/W bit of a matching received address byte is clear, the R/W bit is cleared. The received

address is loaded into the SSPxBUF register and acknowledged.

When the overflow condition exists for a received address, then Not Acknowledge (NACK) is given. An

overflow condition is defined as either bit BF is set, or bit SSPOV is set. The BOEN bit modifies this

operation. For more information see SSPxCON3.

An MSSP interrupt is generated for each transferred data byte. Flag bit, SSPxIF, must be cleared by

software.

When the SEN bit is set, SCL will be held low (clock stretch) following each received byte. The clock must

be released by setting the CKP bit, except sometimes in 10-bit mode. See 27.5.6.2 10-bit Addressing

Mode for more detail.

27.5.2.1 7-bit Addressing Reception

This section describes a standard sequence of events for the MSSP module configured as an I2C slave in

7-bit Addressing mode. Figure 27-14 and Figure 27-15 is used as a visual reference for this description.

This is a step by step process of what typically must be done to accomplish I2C communication.

1. Start bit detected.

2. S bit is set; SSPxIF is set if interrupt on Start detect is enabled.

3. Matching address with R/W bit clear is received.

4. The slave pulls SDA low sending an ACK to the master, and sets SSPxIF bit.

5. Software clears the SSPxIF bit.

6. Software reads received address from SSPxBUF clearing the BF flag.

7. If SEN = 1; Slave software sets CKP bit to release the SCL line.

8. The master clocks out a data byte.

9. Slave drives SDA low sending an ACK to the master, and sets SSPxIF bit.

10. Software clears SSPxIF.

11. Software reads the received byte from SSPxBUF clearing BF.

12. Steps 8-12 are repeated for all received bytes from the master.

13. Master sends Stop condition, setting P bit, and the bus goes idle.

27.5.2.2 7-bit Reception with AHEN and DHEN

Slave device reception with AHEN and DHEN set operate the same as without these options with extra

interrupts and clock stretching added after the eighth falling edge of SCL. These additional interrupts

allow the slave software to decide whether it wants to ACK the receive address or data byte, rather than

the hardware. This functionality adds support for PMBus™ that was not present on previous versions of

this module.

This list describes the steps that need to be taken by slave software to use these options for I2C

communication. Figure 27-16 displays a module using both address and data holding. Figure 27-17

includes the operation with the SEN bit of the SSPxCON2 register set.

1. S bit is set; SSPxIF is set if interrupt on Start detect is enabled.

2. Matching address with R/W bit clear is clocked in. SSPxIF is set and CKP cleared after the eighth

falling edge of SCL.

PIC18F26/45/46Q10

(MSSP) Master Synchronous Serial Port Module

3. Slave clears the SSPxIF.

4. Slave can look at the ACKTIM bit to determine if the SSPxIF was after or before the ACK.

5. Slave reads the address value from SSPxBUF, clearing the BF flag.

6. Slave sets ACK value clocked out to the master by setting ACKDT.

7. Slave releases the clock by setting CKP.

8. SSPxIF is set after an ACK, not after a NACK.

9. If SEN = 1, the slave hardware will stretch the clock after the ACK.

10. Slave clears SSPxIF.

Important: SSPxIF is still set after the ninth falling edge of SCL even if there is no clock

stretching and BF has been cleared. Only if NACK is sent to master is SSPxIF not set

11. SSPxIF set and CKP cleared after eighth falling edge of SCL for a received data byte.

12. Slave looks at ACKTIM bit to determine the source of the interrupt.

13. Slave reads the received data from SSPxBUF clearing BF.

14. Steps 7-14 are the same for each received data byte.

15. Communication is ended by either the slave sending an ACK = 1, or the master sending a Stop

condition. If a Stop is sent and Interrupt on Stop Detect is disabled, the slave will only know by

polling the P bit.

PIC18F26/45/46Q10

(MSSP) Master Synchronous Serial Port Module

Figure 27-14. I2C Slave, 7-bit Address, Reception (SEN = 0, AHEN = 0, DHEN = 0)rotatethispage90

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Rev. 30-000024A

4/10/2017

of data is

available

in SSPxBUF

PIC18F26/45/46Q10

(MSSP) Master Synchronous Serial Port Module

Figure 27-15. I2C Slave, 7-bit Address, Reception (SEN = 1, AHEN = 0, DHEN = 0)rotatethispage90



SEN SEN

A7 A6 A5 A4 A3 A2 A1 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0SDA

SCL 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 P

SSPxIF set on 9th

SCL is not held

CKP is written to ‘1’ in software,

ACK

low because

falling edge of SCL

releasing SCL

ACK is not sent.

Bus Master sends

CKP

SSPOV

BF

SSPxIF

SSPOV set because

SSPxBUF is still full.

Cleared by software

First byte

of dat a is

avai labl e

in SSPx BUF

ACK=1

Cleared by software

SSPxBUF is read

Clock is held low until CKP is set to ‘1’

releasing SCL

Stop condition

S

ACK

Receive Address Receive Data Receive Data

R/W=0

Rev. 30-000025A

4/3/2017

PIC18F26/45/46Q10

(MSSP) Master Synchronous Serial Port Module

Figure 27-16. I2C Slave, 7-bit Address, Reception (SEN = 0, AHEN = 1, DHEN = 1)rotatethispage90



Receiving Address Receiving Data Received Data

P

A7 A6 A5 A4 A3 A2 A1 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0

SDA

SCL

BF

CKP

S

P

1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8

Master sends

Stop condition

S

Data is read from SSPxBUF

Cleared by software

SSPxIF is set on

9th falling edge of

SCL, after ACK

CKP set by software,

SCL is released

Slave software

9

ACKTIM cleared by

hardware in 9th

rising edge of SCL

sets ACKDT to

not ACK

When DHEN=1:

CKP is cleared by

hardware on 8th falling

edge of SCL

Slave software

clears ACKDT to

ACK the received

byte

ACKTIM set by hardware

on 8th falling edge of SCL

When AHEN=1:

CKP is cleared by hardware

and SCL is stretched

Address is

read from

SSBUF

ACKTIM set by hardware

on 8th falling edge of SCL

ACK

Master Releases SDA

to slave for ACK sequence

No interrupt

after not ACK

from Slave

ACK=1

ACK

ACKDT

ACKTIM

SSPxIF

If AHEN = 1:

SSPxIF is set

Rev. 30-000026A

4/3/2017

PIC18F26/45/46Q10

(MSSP) Master Synchronous Serial Port Module

Figure 27-17. I2C Slave, 7-bit Address, Reception (SEN = 1, AHEN = 1, DHEN = 1)rotatethispage90



Receiving Address Receive Data Receive Data

A7 A6 A5 A4 A3 A2 A1 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0

SDA

SCL

SSPxIF

BF

ACKDT

CKP

S

P

ACK

S1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9

ACK

Cleared by software

ACKTIM is cleared by hardware

SSPxBUF can be

Set by software,

read any time before

next byte is loaded

release SCL

on 9th rising edge of SCL

Received

address is loaded into

SSPxBUF

Slave software clears

ACKDT to ACK

R/W = 0Master releases

SDA to slave for ACK sequence

the received byte

When AHEN = 1;

on the 8th falling edge

of SCL of an address

byte, CKP is cleared

ACKTIM is set by hardware

on 8th falling edge of SCL

When DHEN = 1;

on the 8th falling edge

of SCL of a received

data byte, CKP is cleared

Received data is

available on SSPxBUF

Slave sends

not ACK

CKP is not cleared

if not ACK

P

Master sends

Stop condition

No interrupt after

if not ACK

from Slave

ACKTIM

Rev. 30-000027A

4/3/2017

PIC18F26/45/46Q10

(MSSP) Master Synchronous Serial Port Module

27.5.3 Slave Transmission

When the R/W bit of the incoming address byte is set and an address match occurs, the R/W bit is set.

The received address is loaded into the SSPxBUF register, and an ACK pulse is sent by the slave on the

ninth bit.

Following the ACK, slave hardware clears the CKP bit and the SCL pin is held low (see 27.5.6 Clock

Stretchingfor more detail). By stretching the clock, the master will be unable to assert another clock pulse

until the slave is done preparing the transmit data.

The transmit data must be loaded into the SSPxBUF register, which also loads the SSPSR register. Then

the SCL pin should be released by setting the CKP bit. The eight data bits are shifted out on the falling

edge of the SCL input. This ensures that the SDA signal is valid during the SCL high time.

The ACK pulse from the master receiver is latched on the rising edge of the ninth SCL input pulse. This

ACK value is copied to the ACKSTAT bit. If ACKSTAT is set (not ACK), then the data transfer is complete.

In this case, when the not ACK is latched by the slave, the slave goes idle and waits for another

occurrence of the Start bit. If the SDA line was low (ACK), the next transmit data must be loaded into the

SSPxBUF register. Again, the SCL pin must be released by setting bit CKP.

An MSSP interrupt is generated for each data transfer byte. The SSPxIF bit must be cleared by software

and the SSPxSTAT register is used to determine the status of the byte. The SSPxIF bit is set on the

falling edge of the ninth clock pulse.

27.5.3.1 Slave Mode Bus Collision

A slave receives a read request and begins shifting data out on the SDA line. If a bus collision is detected

and the SBCDE bit is set, the BCLxIF bit of the PIRx register is set. Once a bus collision is detected, the

slave goes idle and waits to be addressed again. User software can use the BCLxIF bit to handle a slave

bus collision.

27.5.3.2 7-bit Transmission

A master device can transmit a read request to a slave, and then clock data out of the slave. The list

below outlines what software for a slave will need to do to accomplish a standard transmission. Figure

27-18 can be used as a reference to this list.

1. Master sends a Start condition on SDA and SCL.

2. S bit is set; SSPxIF is set if interrupt on Start detect is enabled.

3. Matching address with R/W bit set is received by the Slave setting SSPxIF bit.

4. Slave hardware generates an ACK and sets SSPxIF.

5. SSPxIF bit is cleared by user.

6. Software reads the received address from SSPxBUF, clearing BF.

7. R/W is set so CKP was automatically cleared after the ACK.

8. The slave software loads the transmit data into SSPxBUF.

9. CKP bit is set releasing SCL, allowing the master to clock the data out of the slave.

10. SSPxIF is set after the ACK response from the master is loaded into the ACKSTAT register.

11. SSPxIF bit is cleared.

12. The slave software checks the ACKSTAT bit to see if the master wants to clock out more data.

PIC18F26/45/46Q10

(MSSP) Master Synchronous Serial Port Module

Important:

1. If the master ACKs then the clock will be stretched.

2. ACKSTAT is the only bit updated on the rising edge of the ninth SCL clock

instead of the falling edge.

13. Steps 9-13 are repeated for each transmitted byte.

14. If the master sends a not ACK; the clock is not held, but SSPxIF is still set.

15. The master sends a Restart condition or a Stop.

16. The slave is no longer addressed.

PIC18F26/45/46Q10

(MSSP) Master Synchronous Serial Port Module

Figure 27-18. I2C Slave, 7-bit Address, Transmission (AHEN = 0)rotatethispage90



Receiving Address Automatic Transmitting Data Automatic Transmitting Data

A7 A6 A5 A4 A3 A2 A1 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0

1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9

SDA

SCL

SSPxIF

BF

CKP

ACKSTAT

R/W

D/A

S

P

Received address

When R/W is set

R/W is copied from the

Indicates an address

is read from SSPxBUF

SCL is always

held low after 9th SCL

falling edge

matching address byte

has been received

Masters not ACK

is copied to

ACKSTAT

CKP is not

held for not

ACK

BF is automatically

cleared after 8th falling

edge of SCL

Data to transmit is

loaded into SSPxBUF

Set by software

Cleared by software

ACK

R/W = 1

SP

Master sends

Stop condition

Rev. 30-000028A

4/3/2017

PIC18F26/45/46Q10

(MSSP) Master Synchronous Serial Port Module

27.5.3.3 7-bit Transmission with Address Hold Enabled

Setting the AHEN bit enables additional clock stretching and interrupt generation after the eighth falling

edge of a received matching address. Once a matching address has been clocked in, CKP is cleared and

the SSPxIF interrupt is set.

Figure 27-19 displays a standard waveform of a 7-bit address slave transmission with AHEN enabled.

1. Bus starts Idle.

2. Master sends Start condition; the S bit is set; SSPxIF is set if interrupt on Start detect is enabled.

3. Master sends matching address with R/W bit set. After the eighth falling edge of the SCL line the

CKP bit is cleared and SSPxIF interrupt is generated.

4. Slave software clears SSPxIF.

5. Slave software reads the ACKTIM, R/W and D/A bits to determine the source of the interrupt.

6. Slave reads the address value from the SSPxBUF register clearing the BF bit.

7. Slave software decides from this information if it wishes to ACK or not ACK and sets the ACKDT bit

accordingly.

8. Slave sets the CKP bit releasing SCL.

9. Master clocks in the ACK value from the slave.

10. Slave hardware automatically clears the CKP bit and sets SSPxIF after the ACK if the R/W bit is

set.

11. Slave software clears SSPxIF.

12. Slave loads value to transmit to the master into SSPxBUF setting the BF bit.

Important: SSPxBUF cannot be loaded until after the ACK.

13. Slave sets the CKP bit releasing the clock.

14. Master clocks out the data from the slave and sends an ACK value on the ninth SCL pulse.

15. Slave hardware copies the ACK value into the ACKSTAT bit.

16. Steps 10-15 are repeated for each byte transmitted to the master from the slave.

17. If the master sends a not ACK the slave releases the bus allowing the master to send a Stop and

end the communication.

Important: Master must send a not ACK on the last byte to ensure that the slave

releases the SCL line to receive a Stop.

PIC18F26/45/46Q10

(MSSP) Master Synchronous Serial Port Module

Figure 27-19. I2C Slave, 7-bit Address, Transmission (AHEN = 1)rotatethispage90



Receiving Address Automatic Transmitting Data Automatic Transmitting Data

A7 A6 A5 A4 A3 A2 A1 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0

1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9

SDA

SCL

SSPxIF

BF

ACKDT

ACKSTAT

CKP

R/W

D/A

Received address

is read from SSPxBUF

BF is automatically

cleared after 8th falling

edge of SCL

Data to transmit is

loaded into SSPxBUF

Cleared by software

Slave clears

ACKDT to ACK

address

Master’s ACK

response is copied

to SSPxSTAT

CKP not cleared

after not ACK

Set by software,

releases SCL

ACKTIM is cleared

on 9th rising edge of SCL

ACKTIM is set on 8th falling

edge of SCL

When AHEN = 1;

CKP is cleared by hardware

after receiving matching

address.

When R/W = 1;

CKP is always

cleared after ACK

SP

Master sends

Stop condition

ACK

R/W = 1

Master releases SDA

to slave for ACK sequence

ACK

ACKTIM

Rev. 30-00029A

4/10/2017

PIC18F26/45/46Q10

(MSSP) Master Synchronous Serial Port Module

27.5.4 Slave Mode 10-bit Address Reception

This section describes a standard sequence of events for the MSSP module configured as an I2C slave in

10-bit Addressing mode.

Figure 27-20 is used as a visual reference for this description.

This is a step-by-step process of what must be done by the slave software to accomplish I2C

communication.

1. Bus starts Idle.

2. Master sends Start condition; S bit is set; SSPxIF is set if interrupt on Start detect is enabled.

3. Master sends matching high address with R/W bit clear; UA bit is set.

4. Slave sends ACK and SSPxIF is set.

5. Software clears the SSPxIF bit.

6. Software reads received address from SSPxBUF clearing the BF flag.

7. Slave loads low address into SSPxADD, releasing SCL.

8. Master sends matching low address byte to the slave; UA bit is set.

Important: Updates to the SSPxADD register are not allowed until after the ACK

sequence.

9. Slave sends ACK and SSPxIF is set.

Important: If the low address does not match, SSPxIF and UA are still set so that the

slave software can set SSPxADD back to the high address. BF is not set because there is

no match. CKP is unaffected.

10. Slave clears SSPxIF.

11. Slave reads the received matching address from SSPxBUF clearing BF.

12. Slave loads high address into SSPxADD.

13. Master clocks a data byte to the slave and clocks out the slaves ACK on the ninth SCL pulse;

SSPxIF is set.

14. If SEN bit is set, CKP is cleared by hardware and the clock is stretched.

15. Slave clears SSPxIF.

16. Slave reads the received byte from SSPxBUF clearing BF.

17. If SEN is set the slave sets CKP to release the SCL.

18. Steps 13-17 repeat for each received byte.

19. Master sends Stop to end the transmission.

27.5.5 10-bit Addressing with Address or Data Hold

Reception using 10-bit addressing with AHEN or DHEN set is the same as with 7-bit modes. The only

difference is the need to update the SSPxADD register using the UA bit. All functionality, specifically when

the CKP bit is cleared and SCL line is held low are the same. Figure 27-21 can be used as a reference of

a slave in 10-bit addressing with AHEN set.

Figure 27-22 shows a standard waveform for a slave transmitter in 10-bit Addressing mode.

PIC18F26/45/46Q10

(MSSP) Master Synchronous Serial Port Module

Figure 27-20. I2C Slave, 10-bit Address, Reception (SEN = 1, AHEN = 0, DHEN = 0)rotatethispage90

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Rev. 30-000030A

4/3/2017

PIC18F26/45/46Q10

(MSSP) Master Synchronous Serial Port Module

Figure 27-21. I2C Slave, 10-bit Address, Reception (SEN = 0, AHEN = 1, DHEN = 0)rotatethispage90

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Rev. 30-000031A

4/3/2017

is read from

PIC18F26/45/46Q10

(MSSP) Master Synchronous Serial Port Module

Figure 27-22. I2C Slave, 10-bit Address, Transmission (SEN = 0, AHEN = 0, DHEN = 0)rotatethispage90



Receiving Address

ACK

Receiving Second Address Byte

Sr

Receive First Address Byte

ACK

Transmitting Data Byte

1 1 1 1 0

A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

1 1 1 1 0

A9 A8 D7 D6 D5 D4 D3 D2 D1 D0

SDA

SCL

SSPxIF

BF

UA

CKP

R/W

D/A

1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9

ACK =1

P

Master sends

Stop condition

Master sends

not ACK

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Restart event

ACK

R/W = 0

S

Cleared by software

After SSPxADD is

updated, UA is cleared

and SCL is released

High address is loaded

Received address is Data to transmit is

Set by software

Indicates an address

When R/W = 1;

R/W is copied from the

Set by hardware

UA indicates SSPxADD

SSPxBUF loaded

with received address

must be updated

has been received

loaded into SSPxBUF

releases SCL

Masters not ACK

is copied

matching address byte

CKP is cleared on

9th falling edge of SCL

read from SSPxBUF

back into SSPxADD

ACKSTAT

Set by hardware

Rev. 30-000032A

4/3/2017

PIC18F26/45/46Q10

(MSSP) Master Synchronous Serial Port Module

27.5.6 Clock Stretching

Clock stretching occurs when a device on the bus holds the SCL line low, effectively pausing

communication. The slave may stretch the clock to allow more time to handle data or prepare a response

for the master device. A master device is not concerned with stretching as anytime it is active on the bus

and not transferring data it is stretching. Any stretching done by a slave is invisible to the master software

and handled by the hardware that generates SCL.

The CKP bit is used to control stretching in software. Any time the CKP bit is cleared, the module will wait

for the SCL line to go low and then hold it. Setting CKP will release SCL and allow more communication.

27.5.6.1 Normal Clock Stretching

Following an ACK if the R/W bit is set, a read request, the slave hardware will clear CKP. This allows the

slave time to update SSPxBUF with data to transfer to the master. If the SEN bit is set, the slave

hardware will always stretch the clock after the ACK sequence. Once the slave is ready; CKP is set by

software and communication resumes.

Important:

1. The BF bit has no effect on whether or not the clock will be stretched. This is different

than previous versions of the module that would not stretch the clock, clear CKP, if

SSPxBUF was read before the ninth falling edge of SCL.

2. Previous versions of the module did not stretch the clock for a transmission if SSPxBUF

was loaded before the ninth falling edge of SCL. It is now always cleared for read

requests.

27.5.6.2 10-bit Addressing Mode

In 10-bit Addressing mode, when the UA bit is set, the clock is always stretched. This is the only time the

SCL is stretched without CKP being cleared. SCL is released immediately after a write to SSPxADD.

Important: Previous versions of the module did not stretch the clock if the second address

byte did not match.

27.5.6.3 Byte NACKing

When the AHEN bit is set, CKP is cleared by hardware after the eighth falling edge of SCL for a received

matching address byte. When the DHEN bit is set, CKP is cleared after the eighth falling edge of SCL for

received data.

Stretching after the eighth falling edge of SCL allows the slave to look at the received address or data

and decide if it wants to ACK the received data.

27.5.7 Clock Synchronization and the CKP bit

Any time the CKP bit is cleared, the module will wait for the SCL line to go low and then hold it. However,

clearing the CKP bit will not assert the SCL output low until the SCL output is already sampled low.

Therefore, the CKP bit will not assert the SCL line until an external I2C master device has already

asserted the SCL line. The SCL output will remain low until the CKP bit is set and all other devices on the

I2C bus have released SCL. This ensures that a write to the CKP bit will not violate the minimum high

time requirement for SCL (see the following figure).

PIC18F26/45/46Q10

(MSSP) Master Synchronous Serial Port Module

Figure 27-23. Clock Synchronization Timing



SDA

SCL

DX ‚ –1DX

WR

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

SSPxCON1

CKP

Master device

releases clock

Master device

asserts clock

Rev. 30-000033A

4/3/2017

27.5.8 General Call Address Support

The addressing procedure for the I2C bus is such that the first byte after the Start condition usually

determines which device will be the slave addressed by the master device. The exception is the general

call address that can address all devices. When this address is used, all devices should, in theory,

respond with an acknowledge.

The general call address is a reserved address in the I2C protocol, defined as address 0x00. When the

GCEN bit is set, the slave module will automatically ACK the reception of this address regardless of the

value stored in SSPxADD. After the slave clocks in an address of all zeros with the R/W bit clear, an

interrupt is generated and slave software can read SSPxBUF and respond. The following figure shows a

general call reception sequence.

Figure 27-24. Slave Mode General Call Address Sequence



SDA

SCL

S

SSPxIF

BF (SSPxSTAT<0>)

Cleared by software

SSPxBUF is read

R/W =0

ACK

General Call Address

Address is compared to General Call Address

Receiving Data ACK

1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9

D7 D6 D5 D4 D3 D2 D1 D0

after ACK, set interrupt

GCEN (SSPxCON2<7>)

’1’

Rev. 30-000034A

4/3/2017

In 10-bit Address mode, the UA bit will not be set on the reception of the general call address. The slave

will prepare to receive the second byte as data, just as it would in 7-bit mode.

PIC18F26/45/46Q10

(MSSP) Master Synchronous Serial Port Module

If the AHEN bit is set, just as with any other address reception, the slave hardware will stretch the clock

after the eighth falling edge of SCL. The slave must then set its ACKEN value and release the clock with

communication progressing as it would normally.

27.5.9 SSP Mask Register

An SSP Mask register (SSPxMSK) is available in I2C Slave mode as a mask for the value held in the

SSPSR register during an address comparison operation. A zero (‘0’) bit in the SSPxMSK register has

the effect of making the corresponding bit of the received address a “don’t care”.

This register is reset to all ‘1’s upon any Reset condition and, therefore, has no effect on standard SSP

operation until written with a mask value.

The SSP Mask register is active during:

• 7-bit Address mode: address compare of A<7:1>.

• 10-bit Address mode: address compare of A<7:0> only. The SSP mask has no effect during the

reception of the first (high) byte of the address.

27.6 I2C Master Mode

Master mode is enabled by setting and clearing the appropriate SSPM bits and setting the SSPEN bit. In

Master mode, the SDA and SCK pins must be configured as inputs. The MSSP peripheral hardware will

override the output driver TRIS controls when necessary to drive the pins low.

Master mode of operation is supported by interrupt generation on the detection of the Start and Stop

conditions. The Stop (P) and Start (S) bits are cleared from a Reset or when the MSSP module is

disabled. Control of the I2C bus may be taken when the P bit is set, or the bus is Idle.

In Firmware Controlled Master mode, user code conducts all I2C bus operations based on Start and Stop

bit condition detection. Start and Stop condition detection is the only active circuitry in this mode. All other

communication is done by the user software directly manipulating the SDA and SCL lines.

The following events will cause the SSP Interrupt Flag bit, SSPxIF, to be set (SSP interrupt, if enabled):

• Start condition detected

• Stop condition detected

• Data transfer byte transmitted/received

• Acknowledge transmitted/received

• Repeated Start generated

Important:

1. The MSSP module, when configured in I2C Master mode, does not allow queuing of

events. For instance, the user is not allowed to initiate a Start condition and immediately

write the SSPxBUF register to initiate transmission before the Start condition is complete.

In this case, the SSPxBUF will not be written to and the WCOL bit will be set, indicating

that a write to the SSPxBUF did not occur.

2. Master mode suspends Start/Stop detection when sending the Start/Stop condition by

means of the SEN/PEN control bits. The SSPxIF bit is set at the end of the Start/Stop

generation when hardware clears the control bit.

PIC18F26/45/46Q10

(MSSP) Master Synchronous Serial Port Module

27.6.1 I2C Master Mode Operation

The master device generates all of the serial clock pulses and the Start and Stop conditions. A transfer is

ended with a Stop condition or with a Repeated Start condition. Since the Repeated Start condition is

also the beginning of the next serial transfer, the I2C bus will not be released.

In Master Transmitter mode, serial data is output through SDA, while SCL outputs the serial clock. The

first byte transmitted contains the slave address of the receiving device (7 bits) and the R/W bit. In this

case, the R/W bit will be logic ‘0’. Serial data is transmitted eight bits at a time. After each byte is

transmitted, an Acknowledge bit is received. Start and Stop conditions are output to indicate the

beginning and the end of a serial transfer.

In Master Receive mode, the first byte transmitted contains the slave address of the transmitting device

(7 bits) and the R/W bit. In this case, the R/W bit will be logic ‘1’. Thus, the first byte transmitted is a 7-bit

slave address followed by a ‘1’ to indicate the receive bit. Serial data is received via SDA, while SCL

outputs the serial clock. Serial data is received eight bits at a time. After each byte is received, an

Acknowledge bit is transmitted. Start and Stop conditions indicate the beginning and end of transmission.

A Baud Rate Generator is used to set the clock frequency output on SCL. See 27.7 Baud Rate

Generator for more detail.

27.6.2 Clock Arbitration

Clock arbitration occurs when the master, during any receive, transmit or Repeated Start/Stop condition,

releases the SCL pin (SCL allowed to float high). When the SCL pin is allowed to float high, the Baud

Rate Generator (BRG) is suspended from counting until the SCL pin is actually sampled high. When the

SCL pin is sampled high, the Baud Rate Generator is reloaded with the contents of 27.9.6 SSPxADD

and begins counting. This ensures that the SCL high time will always be at least one BRG rollover count

in the event that the clock is held low by an external device as shown in the following figure.

Figure 27-25. Baud Rate Generator Timing with Clock Arbitration



SDA

SCL

SCL deasserted but slave holds

DX ‚ –1DX

BRG

SCL is sampled high, reload takes

place and BRG starts its count

03h 02h 01h 00h (hold off) 03h 02h

Reload

BRG

Value

SCL low (clock arbitration)

SCL allowed to transition high

BRG decrements on

Q2 and Q4 cycles

Rev. 30-000035A

4/3/2017

27.6.3 WCOL Status Flag

If the user writes the SSPxBUF when a Start, Restart, Stop, Receive or Transmit sequence is in progress,

the WCOL bit is set and the contents of the buffer are unchanged (the write does not occur). Any time the

WCOL bit is set it indicates that an action on SSPxBUF was attempted while the module was not idle.

PIC18F26/45/46Q10

(MSSP) Master Synchronous Serial Port Module

Important: Because queuing of events is not allowed, writing to the lower five bits of

SSPxCON2 is disabled until the Start condition is complete.

27.6.4 I2C Master Mode Start Condition Timing

To initiate a Start condition (Figure 27-26), the user sets the SEN Start Enable bit. If the SDA and SCL

pins are sampled high, the Baud Rate Generator is reloaded with the contents of SSPxADD and starts its

count. If SCL and SDA are both sampled high when the Baud Rate Generator times out (TBRG), the SDA

pin is driven low. The action of the SDA being driven low while SCL is high is the Start condition and

causes the S bit to be set. Following this, the Baud Rate Generator is reloaded with the contents of

SSPxADD and resumes its count. When the Baud Rate Generator times out (TBRG), the SEN bit will be

automatically cleared by hardware; the Baud Rate Generator is suspended, leaving the SDA line held low

and the Start condition is complete.

Important:

1. If at the beginning of the Start condition, the SDA and SCL pins are already sampled low,

or if during the Start condition, the SCL line is sampled low before the SDA line is driven

low, a bus collision occurs, the Bus Collision Interrupt Flag, BCLxIF, is set, the Start

condition is aborted and the I2C module is reset into its Idle state.

2. The Philips I2C specification states that a bus collision cannot occur on a Start.

Figure 27-26. First Start Bit Timing



SDA

SCL

S

TBRG

1st bit 2nd bit

TBRG

SDA = 1, At completion of Start bit,

SCL = 1

Write to SSPxBUF occurs here

TBRG

hardware clears SEN bit

TBRG

Write to SEN bit occurs here Set S bit (SSPxSTAT<3>)

a nd set s SSPx I F bi t

Rev. 30-000036A

4/3/2017

27.6.5 I2C Master Mode Repeated Start Condition Timing

A Repeated Start condition (Figure 27-27) occurs when the RSEN bit is programmed high and the master

state machine is no longer active. When the RSEN bit is set, the SCL pin is asserted low. When the SCL

pin is sampled low, the Baud Rate Generator is loaded and begins counting. The SDA pin is released

(brought high) for one Baud Rate Generator count (TBRG). When the Baud Rate Generator times out, if

SDA is sampled high, the SCL pin will be deasserted (brought high). When SCL is sampled high, the

Baud Rate Generator is reloaded and begins counting. SDA and SCL must be sampled high for one

TBRG. This action is then followed by assertion of the SDA pin (SDA = 0) for one TBRG while SCL is high.

SCL is asserted low. Following this, the RSEN bit will be automatically cleared and the Baud Rate

Generator will not be reloaded, leaving the SDA pin held low. As soon as a Start condition is detected on

PIC18F26/45/46Q10

(MSSP) Master Synchronous Serial Port Module

the SDA and SCL pins, the S bit will be set. The SSPxIF bit will not be set until the Baud Rate Generator

has timed out.

Important:

1. If RSEN is programmed while any other event is in progress, it will not take effect.

2. A bus collision during the Repeated Start condition occurs if:

– SDA is sampled low when SCL goes from low-to-high.

– SCL goes low before SDA is asserted low. This may indicate that another master is

attempting to transmit a data ‘1’.

Figure 27-27. Repeated Start Condition Waveform



SDA

SCL

Repeated Start

Write to SSPxCON2

Write to SSPxBUF occurs here

At completion of Start bit,

hardware clears the RSEN bit

1st bit

S bit set by hardware

TBRG

SDA = 1, SDA = 1,

SCL (no change) SCL = 1

occurs here

TBRG TBRG TBRG

and sets SSPxIF

Sr

Rev. 30-000037A

4/10/2017

27.6.6 I2C Master Mode Transmission

Transmission of a data byte, a 7-bit address or the other half of a 10-bit address is accomplished by

simply writing a value to the SSPxBUF register. This action will set the Buffer Full flag bit, BF, and allow

the Baud Rate Generator to begin counting and start the next transmission. Each bit of address/data will

be shifted out onto the SDA pin after the falling edge of SCL is asserted. SCL is held low for one Baud

Rate Generator rollover count (TBRG). Data should be valid before SCL is released high. When the SCL

pin is released high, it is held that way for TBRG. The data on the SDA pin must remain stable for that

duration and some hold time after the next falling edge of SCL. After the eighth bit is shifted out (the

falling edge of the eighth clock), the BF flag is cleared and the master releases SDA. This allows the

slave device being addressed to respond with an ACK bit during the ninth bit time if an address match

occurred, or if data was received properly. The status of ACK is written into the ACKSTAT bit on the rising

edge of the ninth clock. If the master receives an Acknowledge, the Acknowledge Status bit, ACKSTAT, is

cleared. If not, the bit is set. After the ninth clock, the SSPxIF bit is set and the master clock (Baud Rate

Generator) is suspended until the next data byte is loaded into the SSPxBUF, leaving SCL low and SDA

unchanged (Figure 27-28).

After the write to the SSPxBUF, each bit of the address will be shifted out on the falling edge of SCL until

all seven address bits and the R/W bit are completed. On the falling edge of the eighth clock, the master

will release the SDA pin, allowing the slave to respond with an Acknowledge. On the falling edge of the

ninth clock, the master will sample the SDA pin to see if the address was recognized by a slave. The

status of the ACK bit is loaded into the ACKSTAT Status bit of the SSPxCON2 register. Following the

falling edge of the ninth clock transmission of the address, the SSPxIF is set, the BF flag is cleared and

PIC18F26/45/46Q10

(MSSP) Master Synchronous Serial Port Module

the Baud Rate Generator is turned off until another write to the SSPxBUF takes place, holding SCL low

and allowing SDA to float.

27.6.6.1 BF Status Flag

In Transmit mode, the BF bit is set when the CPU writes to SSPxBUF and is cleared when all eight bits

are shifted out.

27.6.6.2 WCOL Status Flag

If the user writes the SSPxBUF when a transmit is already in progress (i.e., SSPSR is still shifting out a

data byte), the WCOL bit is set and the contents of the buffer are unchanged (the write does not occur).

The WCOL bit must be cleared by software before the next transmission.

27.6.6.3 ACKSTAT Status Flag

In Transmit mode, the ACKSTAT bit is cleared when the slave has sent an Acknowledge (ACK = 0) and is

set when the slave does not Acknowledge (ACK = 1). A slave sends an Acknowledge when it has

recognized its address (including a general call), or when the slave has properly received its data.

27.6.6.4 Typical transmit sequence:

1. The user generates a Start condition by setting the SEN bit.

2. SSPxIF is set by hardware on completion of the Start.

3. SSPxIF is cleared by software.

4. The MSSP module will wait the required start time before any other operation takes place.

5. The user loads the SSPxBUF with the slave address to transmit.

6. Address is shifted out the SDA pin until all eight bits are transmitted. Transmission begins as soon

as SSPxBUF is written to.

7. The MSSP module shifts in the ACK bit from the slave device and writes its value into the

ACKSTAT bit.

8. The MSSP module generates an interrupt at the end of the ninth clock cycle by setting the SSPxIF

bit.

9. The user loads the SSPxBUF with eight bits of data.

10. Data is shifted out the SDA pin until all eight bits are transmitted.

11. The MSSP module shifts in the ACK bit from the slave device and writes its value into the

ACKSTAT bit.

12. Steps 8-11 are repeated for all transmitted data bytes.

13. The user generates a Stop or Restart condition by setting the PEN or RSEN bits. Interrupt is

generated once the Stop/Restart condition is complete.

PIC18F26/45/46Q10

(MSSP) Master Synchronous Serial Port Module

Figure 27-28. I2C Master Mode Waveform (Transmission, 7 or 10-bit Address)



SDA

SCL

SSPxIF

BF (SSPxSTAT<0>)

SEN

A7 A6 A5 A4 A3 A2 A1 ACK =0D7 D6 D5 D4 D3 D2 D1 D0

ACK

Transmitting Data or Second Half

R/W = 0

Transmit Address to Slave

1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 P

Cleared by software service routine

SSPxBUF is written by software

from SSP interrupt

After Start condition, SEN cleared by hardware

S

SSPxBUF written with 7-bit address and R/W

start transmit

SCL held low

while CPU

responds to SSPxIF

SEN = 0

of 10-bit Address

Write SSPxCON2<0> SEN = 1

Start condition begins From slave, clear ACKSTAT bit SSPxCON2<6>

ACKSTAT in

SSPxCON2 = 1

Cleared by software

SSPxBUF written

PEN

R/W

Cleared by software

Rev. 30-000038A

4/3/2017

27.6.7 I2C Master Mode Reception

Master mode reception (Figure 27-29) is enabled by programming the RCEN Receive Enable bit.

Important: The MSSP module must be in an Idle state before the RCEN bit is set or the

RCEN bit will be disregarded.

The Baud Rate Generator begins counting and on each rollover, the state of the SCL pin changes (high-

to-low/low-to-high) and data is shifted into the SSPSR. After the falling edge of the eighth clock all the

following events occur:

• The receive enable flag is automatically cleared

• The contents of the SSPSR are loaded into the SSPxBUF

• The BF flag bit is set

• The SSPxIF flag bit is set

• The Baud Rate Generator is suspended from counting

• The SCL pin is held low

The MSSP is now in Idle state awaiting the next command. When the buffer is read by the CPU, the BF

flag bit is automatically cleared. The user can then send an Acknowledge bit at the end of reception by

setting the Acknowledge Sequence Enable, ACKEN bit.

27.6.7.1 BF Status Flag

In receive operation, the BF bit is set when an address or data byte is loaded into SSPxBUF from

SSPSR. It is cleared when the SSPxBUF register is read.

PIC18F26/45/46Q10

(MSSP) Master Synchronous Serial Port Module

27.6.7.2 SSPOV Status Flag

In receive operation, the SSPOV bit is set when eight bits are received into the SSPSR while the BF flag

bit is already set from a previous reception.

27.6.7.3 WCOL Status Flag

If the user writes the SSPxBUF when a receive is already in progress (i.e., SSPSR is still shifting in a data

byte), the WCOL bit is set and the contents of the buffer are unchanged (the write does not occur).

27.6.7.4 Typical Receive Sequence:

1. The user generates a Start condition by setting the SEN bit.

2. SSPxIF is set by hardware on completion of the Start.

3. SSPxIF is cleared by software.

4. User writes SSPxBUF with the slave address to transmit and the R/W bit set.

5. Address is shifted out the SDA pin until all eight bits are transmitted. Transmission begins as soon

as SSPxBUF is written to.

6. The MSSP module shifts in the ACK bit from the slave device and writes its value into the

ACKSTAT bit.

7. The MSSP module generates an interrupt at the end of the ninth clock cycle by setting the SSPxIF

bit.

8. User sets the RCEN bit and the master clocks in a byte from the slave.

9. After the eighth falling edge of SCL, SSPxIF and BF are set.

10. Master clears SSPxIF and reads the received byte from SSPUF which clears BF.

11. Master sets the ACK value to be sent to slave in the ACKDT bit and initiates the ACK by setting the

ACKEN bit.

12. Master’s ACK is clocked out to the slave and SSPxIF is set.

13. User clears SSPxIF.

14. Steps 8-13 are repeated for each received byte from the slave.

15. Master sends a not ACK or Stop to end communication.

PIC18F26/45/46Q10

(MSSP) Master Synchronous Serial Port Module

Figure 27-29. I2C Master Mode Waveform (Reception, 7-bit Address)rotatethispage90



P

9

87

6

5

D0

D1

D2

D3D4

D5

D6D7

S

A7 A6 A5 A4 A3 A2 A1

SDA

SCL 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4

Bus master

terminates

transfer

ACK

Receiving Data from Slave

D0

D1

D2

D3D4

D5

D6D7

ACK

R/W

Transmit Address to Slave

SSPxIF

BF

ACK is not sent

Write to SSPxCON2<0>(SEN = 1),

Write to SSPxBUF occurs here, ACK from Slave

Master configured as a receiver

by programming SSPxCON2<3> (RCEN = 1)

PEN bit = 1

written here

Data shifted in on falling edge of CLK

Cleared by software

start XMIT

SEN = 0

SSPOV

SDA = 0, SCL = 1

while CPU

(SSPxSTAT<0>)

ACK

Cleared by software

Set SSPxIF interrupt

at end of receive

Set P bit

(SSPxSTAT<4>)

and SSPxIF

Cleared in

software

ACK from Master

Set SSPxIF at end

Set SSPxIF interrupt

at end of Acknowledge

sequence

Set SSPxIF interrupt

at end of Acknow-

ledge sequence

of receive

Set ACKEN, start Acknowledge sequence

SSPOV is set because

SSPxBUF is still full

SDA = ACKDT = 1

RCEN cleared

automatically

RCEN = 1, start

next receive

Write to SSPxCON2<4>

to start Acknowledge sequence

SDA = ACKDT (SSPxCON2<5>) = 0

RCEN cleared

automatically

responds to SSPxIF

ACKEN

begin Start condition

Cleared by software

SDA = ACKDT = 0

Last bit is shifted into SSPSR and

contents are unloaded into SSPxBUF

RCEN

Master configured as a receiver

by programming SSPxCON2<3> (RCEN = 1)

RCEN cleared

automatically

ACK from Master

SDA = ACKDT = 0RCEN cleared

automatically

Rev. 30-000039A

4/3/2017

PIC18F26/45/46Q10

(MSSP) Master Synchronous Serial Port Module

27.6.8 Acknowledge Sequence Timing

An Acknowledge sequence is enabled by setting the Acknowledge Sequence Enable ACKEN bit. When

this bit is set, the SCL pin is pulled low and the contents of the Acknowledge data bit are presented on

the SDA pin. If the user wishes to generate an Acknowledge, then the ACKDT bit should be cleared. If

not, the user should set the ACKDT bit before starting an Acknowledge sequence. The Baud Rate

Generator then counts for one rollover period (TBRG) and the SCL pin is deasserted (pulled high). When

the SCL pin is sampled high (clock arbitration), the Baud Rate Generator counts for TBRG. The SCL pin is

then pulled low. Following this, the ACKEN bit is automatically cleared, the Baud Rate Generator is

turned off and the MSSP module then goes into Idle mode.

Figure 27-30. Acknowledge Sequence Waveform



Note: TBRG = one Baud Rate Generator period.

SDA

SCL

SSPxIF set at

Acknowledge sequence starts here,

write to SSPxCON2 ACKEN automatically cleared

Cleared in

TBRG TBRG

the end of receive

8

ACKEN = 1, ACKDT = 0

D0

9

SSPxIF

software SSPxIF set at the end

of Acknowledge sequence

Cleared in

software

ACK

Rev. 30-000040A

4/3/2017

27.6.8.1 Acknowledge Write Collision

If the user writes the SSPxBUF when an Acknowledge sequence is in progress, then the WCOL bit is set

and the contents of the buffer are unchanged (the write does not occur).

27.6.9 Stop Condition Timing

A Stop bit is asserted on the SDA pin at the end of a receive/transmit by setting the Stop Sequence

Enable PEN bit. At the end of a receive/transmit, the SCL line is held low after the falling edge of the ninth

clock. When the PEN bit is set, the master will assert the SDA line low. When the SDA line is sampled

low, the Baud Rate Generator is reloaded and counts down to ‘0’. When the Baud Rate Generator times

out, the SCL pin will be brought high and one TBRG (Baud Rate Generator rollover count) later, the SDA

pin will be deasserted. When the SDA pin is sampled high while SCL is high, the P bit is set. One TBRG

later, the PEN bit is cleared and the SSPxIF bit is set.

PIC18F26/45/46Q10

(MSSP) Master Synchronous Serial Port Module

Figure 27-31. Stop Condition in Receive or Transmit Mode



SCL

SDA

SDA asserted low before rising edge of clock

Write to SSPxCON2,

set PEN

Falling edge of

SCL = 1for TBRG, followed by SDA = 1for TBRG

9th clock

SCL brought high after TBRG

Note: TBRG = one Baud Rate Generator period.

TBRG TBRG

after SDA sampled high. P bit (SSPxSTAT<4>) is set.

TBRG

to setup Stop condition

ACK

P

TBRG

PEN bit (SSPxCON2<2>) is cleared by

hardware and the SSPxIF bit is set

Rev. 30-000041A

4/3/2017

27.6.9.1 Write Collision on Stop

If the user writes the SSPxBUF when a Stop sequence is in progress, then the WCOL bit is set and the

contents of the buffer are unchanged (the write does not occur).

27.6.10 Sleep Operation

While in Sleep mode, the I2C slave module can receive addresses or data and when an address match or

complete byte transfer occurs, wake the processor from Sleep (if the MSSP interrupt is enabled).

27.6.11 Effects of a Reset

A Reset disables the MSSP module and terminates the current transfer.

27.6.12 Multi-Master Mode

In Multi-Master mode, the interrupt generation on the detection of the Start and Stop conditions allows the

determination of when the bus is free. The Stop (P) and Start (S) bits are cleared from a Reset or when

the MSSP module is disabled. Control of the I2C bus may be taken when the P bit is set, or the bus is

Idle, with both the S and P bits clear. When the bus is busy, enabling the SSP interrupt will generate the

interrupt when the Stop condition occurs.

In multi-master operation, the SDA line must be monitored for arbitration to see if the signal level is the

expected output level. This check is performed by hardware with the result placed in the BCLxIF bit.

The states where arbitration can be lost are:

• Address Transfer

• Data Transfer

• A Start Condition

• A Repeated Start Condition

• An Acknowledge Condition

27.6.13 Multi-Master Communication, Bus Collision and Bus Arbitration

Multi-Master mode support is achieved by bus arbitration. When the master outputs address/data bits

onto the SDA pin, arbitration takes place when the master outputs a ‘1’ on SDA, by letting SDA float high

and another master asserts a ‘0’. When the SCL pin floats high, data should be stable. If the expected

data on SDA is a ‘1’ and the data sampled on the SDA pin is ‘0’, then a bus collision has taken place. The

master will set the Bus Collision Interrupt Flag, BCLxIF and reset the I2C port to its Idle state (Figure

27-32).

PIC18F26/45/46Q10

(MSSP) Master Synchronous Serial Port Module

If a transmit was in progress when the bus collision occurred, the transmission is halted, the BF flag is

cleared, the SDA and SCL lines are deasserted and the SSPxBUF can be written to. When the user

services the bus collision Interrupt Service Routine and if the I2C bus is free, the user can resume

communication by asserting a Start condition.

If a Start, Repeated Start, Stop or Acknowledge condition was in progress when the bus collision

occurred, the condition is aborted, the SDA and SCL lines are deasserted and the respective control bits

in the SSPxCON2 register are cleared. When the user services the bus collision Interrupt Service Routine

and if the I2C bus is free, the user can resume communication by asserting a Start condition.

The master will continue to monitor the SDA and SCL pins. If a Stop condition occurs, the SSPxIF bit will

be set.

A write to the SSPxBUF will start the transmission of data at the first data bit, regardless of where the

transmitter left off when the bus collision occurred.

In Multi-Master mode, the interrupt generation on the detection of Start and Stop conditions allows the

determination of when the bus is free. Control of the I2C bus can be taken when the P bit is set, or the

bus is Idle and the S and P bits are cleared.

Figure 27-32. Bus Collision Timing for Transmit and Acknowledge



SDA

SCL

BCLxIF

SDA released

SDA line pulled low

by another source

Sample SDA. While SCL is high,

data does not match what is driven

Bus collision has occurred.

Set bus collision

interrupt (BCLxIF)

by the master.

by master

Data changes

while SCL = 0

Rev. 30-000042A

4/3/2017

27.6.13.1 Bus Collision During a Start Condition

During a Start condition, a bus collision occurs if:

1. SDA or SCL are sampled low at the beginning of the Start condition (Figure 27-33).

2. SCL is sampled low before SDA is asserted low (Figure 27-34).

During a Start condition, both the SDA and the SCL pins are monitored.

If the SDA pin is already low, or the SCL pin is already low, then all of the following occur:

• the Start condition is aborted,

• the BCLxIF flag is set and

• the MSSP module is reset to its Idle state (Figure 27-33).

PIC18F26/45/46Q10

(MSSP) Master Synchronous Serial Port Module

Figure 27-33. Bus Collision During Start Condition (SDA Only)



SDA

SCL

SEN

SDA sampled low before

SDA goes low before the SEN bit is set.

S bit and SSPxIF set because

SSPx module reset into Idle state.

SEN cleared automatically because of bus collision.

S bit and SSPxIF set because

Set SEN, enable Start

condition if SDA = 1, SCL = 1

SDA = 0, SCL = 1.

BCLxIF

S

SSPxIF

SDA = 0, SCL = 1.

SSPxIF and BCLxIF are

cleared by software

SSPxIF and BCLxIF are

cleared by software

Set BCLxIF,

Start condition. Set BCLxIF.

Rev. 30-000043A

4/3/2017

The Start condition begins with the SDA and SCL pins deasserted. When the SDA pin is sampled high,

the Baud Rate Generator is loaded and counts down. If the SCL pin is sampled low while SDA is high, a

bus collision occurs because it is assumed that another master is attempting to drive a data ‘1’ during the

Start condition.

Figure 27-34. Bus Collision During Start Condition (SCL = 0)



SDA

SCL

SEN bus collision occurs. Set BCLxIF.

SCL = 0before SDA = 0,

Set SEN, enable Start

sequence if SDA = 1, SCL = 1

TBRG TBRG

SDA = 0, SCL = 1

BCLxIF

S

SSPxIF

Interrupt cleared

by software

bus collision occurs. Set BCLxIF.

SCL = 0before BRG time-out,

’0’ ’0’

’0’’0’

Rev. 30-000044A

4/3/2017

PIC18F26/45/46Q10

(MSSP) Master Synchronous Serial Port Module

If the SDA pin is sampled low during this count, the BRG is reset and the SDA line is asserted early

(Figure 27-35). If, however, a ‘1’ is sampled on the SDA pin, the SDA pin is asserted low at the end of the

BRG count. The Baud Rate Generator is then reloaded and counts down to zero; if the SCL pin is

sampled as ‘0’ during this time, a bus collision does not occur. At the end of the BRG count, the SCL pin

is asserted low.

Figure 27-35. BRG Reset Due to SDA Arbitration During Start Condition



SDA

SCL

SEN

Set S

Less than TBRG TBRG

SDA = 0, SCL = 1

BCLxIF

S

SSPxIF

S

Interrupts cleared

by software

set SSPxIF

SDA = 0, SCL = 1,

SCL pulled low after BRG

time out

Set SSPxIF

’0’

SDA pulled low by other master.

Reset BRG and assert SDA.

Set SEN, enable Start

sequence if SDA = 1, SCL = 1

Rev. 30-000045A

4/10/2017

-

Important: The reason that bus collision is not a factor during a Start condition is that no two

bus masters can assert a Start condition at the exact same time. Therefore, one master will

always assert SDA before the other. This condition does not cause a bus collision because the

two masters must be allowed to arbitrate the first address following the Start condition. If the

address is the same, arbitration must be allowed to continue into the data portion, Repeated

Start or Stop conditions.

27.6.13.2 Bus Collision During a Repeated Start Condition

During a Repeated Start condition, a bus collision occurs if:

1. A low level is sampled on SDA when SCL goes from low level to high level (Case 1).

2. SCL goes low before SDA is asserted low, indicating that another master is attempting to transmit a

data ‘1’ (Case 2).

When the user releases SDA and the pin is allowed to float high, the BRG is loaded with SSPxADD and

counts down to zero. The SCL pin is then deasserted and when sampled high, the SDA pin is sampled.

If SDA is low, a bus collision has occurred (i.e., another master is attempting to transmit a data ‘0’, Figure

27-36). If SDA is sampled high, the BRG is reloaded and begins counting. If SDA goes from high-to-low

before the BRG times out, no bus collision occurs because no two masters can assert SDA at exactly the

same time.

PIC18F26/45/46Q10

(MSSP) Master Synchronous Serial Port Module

Figure 27-36. Bus Collision During a Repeated Start Condition (Case 1)



SDA

SCL

RSEN

BCLxIF

S

SSPxIF

Sample SDA when SCL goes high.

If SDA = 0, set BCLxIF and release SDA and SCL.

Cleared by software

’0’

Rev. 30-000046A

4/3/2017

If SCL goes from high-to-low before the BRG times out and SDA has not already been asserted, a bus

collision occurs. In this case, another master is attempting to transmit a data ‘1’ during the Repeated Start

condition, see Figure 27-37.

If, at the end of the BRG time-out, both SCL and SDA are still high, the SDA pin is driven low and the

BRG is reloaded and begins counting. At the end of the count, regardless of the status of the SCL pin, the

SCL pin is driven low and the Repeated Start condition is complete.

Figure 27-37. Bus Collision During Repeated Start Condition (Case 2)



SDA

SCL

BCLxIF

RSEN

S

SSPxIF

Interrupt cleared

by software

SCL goes low before SDA,

set BCLxIF. Release SDA and SCL.

TBRG TBRG

’0’

Rev. 30-000047A

4/3/2017

27.6.13.3 Bus Collision During a Stop Condition

Bus collision occurs during a Stop condition if:

1. After the SDA pin has been deasserted and allowed to float high, SDA is sampled low after the

BRG has timed out (Case 1).

2. After the SCL pin is deasserted, SCL is sampled low before SDA goes high (Case 2).

The Stop condition begins with SDA asserted low. When SDA is sampled low, the SCL pin is allowed to

float. When the pin is sampled high (clock arbitration), the Baud Rate Generator is loaded with SSPxADD

PIC18F26/45/46Q10

(MSSP) Master Synchronous Serial Port Module

and counts down to zero. After the BRG times out, SDA is sampled. If SDA is sampled low, a bus

collision has occurred. This is due to another master attempting to drive a data ‘0’ (Figure 27-38). If the

SCL pin is sampled low before SDA is allowed to float high, a bus collision occurs. This is another case of

another master attempting to drive a data ‘0’ (Figure 27-39).

Figure 27-38. Bus Collision During a Stop Condition (Case 1)



SDA

SCL

BCLxIF

PEN

P

SSPxIF

TBRG TBRG TBRG

SDA asserted low

SDA sampled

low after TBRG,

set BCLxIF

’0’

Rev. 30-000048A

4/3/2017

Figure 27-39. Bus Collision During a Stop Condition (Case 2)



SDA

SCL

BCLxIF

PEN

P

SSPxIF

TBRG TBRG TBRG

Assert SDA SCL goes low before SDA goes high,

set BCLxIF

’0’

Rev. 30-000049A

4/3/2017

27.7 Baud Rate Generator

The MSSP module has a Baud Rate Generator available for clock generation in both I2C and SPI Master

modes. The Baud Rate Generator (BRG) reload value is placed in the SSPxADD register. When a write

occurs to SSPxBUF, the Baud Rate Generator will automatically begin counting down.

Once the given operation is complete, the internal clock will automatically stop counting and the clock pin

will remain in its last state.

An internal signal “Reload” shown in Figure 27-40 triggers the value from SSPxADD to be loaded into the

BRG counter. This occurs twice for each oscillation of the module clock line. The logic dictating when the

reload signal is asserted depends on the mode in which the MSSP is being operated.

PIC18F26/45/46Q10

(MSSP) Master Synchronous Serial Port Module

Table 27-1 illustrates clock rates based on instruction cycles and the BRG value loaded into SSPxADD.

Example 27-1. MSSP Baud Rate Generator Frequency Equation

 =

4 ×  + 1`

Figure 27-40. Baud Rate Generator Block Diagram



SSPM<3:0>

BRG Down Counter

SSPCLK FOSC/2

SSPxADD<7:0>

SSPM<3:0>

SCL

Reload

Control

Reload

Rev. 30-000050A

4/3/2017

Important: Values of 0x00, 0x01 and 0x02 are not valid for SSPxADD when used as a Baud

Rate Generator for I2C. This is an implementation limitation.

Table 27-1. MSSP Clock Rate w/BRG

FOSC FCY BRG Value Fclock

(2 Rollovers of BRG)

32 MHz 8 MHz 13h 400 kHz

32 MHz 8 MHz 19h 308 kHz

32 MHz 8 MHz 4Fh 100 kHz

16 MHz 4 MHz 09h 400 kHz

16 MHz 4 MHz 0Ch 308 kHz

16 MHz 4 MHz 27h 100 kHz

4 MHz 1 MHz 09h 100 kHz

Note: Refer to the I/O port electrical specifications in the "Electrical Specifications" section, Internal

Oscillator Parameters, to ensure the system is designed to support Iol requirements.

PIC18F26/45/46Q10

(MSSP) Master Synchronous Serial Port Module

27.8 Register Summary: MSSP Control

Address Name Bit Pos.

0x0E8D SSP2BUF 7:0 BUF[7:0]

0x0E8E SSP2ADD 7:0 ADD[7:0]

0x0E8F SSP2MSK 7:0 MSK[6:0] MSK0

0x0E90 SSP2STAT 7:0 SMP CKE D/A P S R/W UA BF

0x0E91 SSP2CON1 7:0 WCOL SSPOV SSPEN CKP SSPM[3:0]

0x0E92 SSP2CON2 7:0 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN

0x0E93 SSP2CON3 7:0 ACKTIM PCIE SCIE BOEN SDAHT SBCDE AHEN DHEN

0x0E94

...

0x0F90

Reserved

0x0F91 SSP1BUF 7:0 BUF[7:0]

0x0F92 SSP1ADD 7:0 ADD[7:0]

0x0F93 SSP1MSK 7:0 MSK[6:0] MSK0

0x0F94 SSP1STAT 7:0 SMP CKE D/A P S R/W UA BF

0x0F95 SSP1CON1 7:0 WCOL SSPOV SSPEN CKP SSPM[3:0]

0x0F96 SSP1CON2 7:0 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN

0x0F97 SSP1CON3 7:0 ACKTIM PCIE SCIE BOEN SDAHT SBCDE AHEN DHEN

27.9 Register Definitions: MSSP Control

PIC18F26/45/46Q10

(MSSP) Master Synchronous Serial Port Module

27.9.1 SSPxSTAT

Name: SSPxSTAT

Address: 0xF94,0xE90

MSSP Status Register

Bit 7 6 5 4 3 2 1 0

SMP CKE D/A P S R/W UA BF

Access R/W R/W RO RO RO RO RO RO

Reset 0 0 0 0 0 0 0 0

Bit 7 – SMP Slew Rate Control bit

Value Mode Description

1SPI Master Input data is sampled at the end of data output time

0SPI Master Input data is sampled at the middle of data output time

0SPI Slave Keep this bit cleared in SPI Slave mode

1I2C Slew rate control is disabled for Standard Speed mode (100 kHz and 1 MHz)

0I2C Slew rate control is enabled for High-Speed mode (400 kHz)

Bit 6 – CKE

SPI: Clock select bit(4) I2C: SMBus Select bit

Value Mode Description

1SPI Transmit occurs on the transition from active to Idle clock state

0SPI Transmit occurs on the transition from Idle to active clock state

1I2C Enables SMBus-specific inputs

0I2C Disables SMBus-specific inputs

Bit 5 – D/A

Data/Address bit

Value Mode Description

xSPI or I2C Master Reserved

1I2C Slave Indicates that the last byte received or transmitted was data

0I2C Slave Indicates that the last byte received or transmitted was address

Bit 4 – P

Stop bit(1)

Value Mode Description

xSPI Reserved

1I2C Stop bit was detected last

0I2C Stop bit was not detected last

Bit 3 – S

Start bit(1)

Value Mode Description

xSPI Reserved

1I2C Start bit was detected last

0I2C Start bit was not detected last

PIC18F26/45/46Q10

(MSSP) Master Synchronous Serial Port Module

Bit 2 – R/W

Read/Write Information bit(2,3)

Value Mode Description

xSPI Reserved

1I2C Slave Read

0I2C Slave Write

1I2C Master Transmit is in progress

0I2C Master Transmit is not in progress

Bit 1 – UA Update Address bit (10-Bit Slave mode only)

Value Mode Description

xAll other modes Reserved

1I2C 10-bit Slave Indicates that the user needs to update the address in the SSPxADD

register

0I2C 10-bit Slave Address does not need to be updated

Bit 0 – BF

Buffer Full Status bit(5)

Value Mode Description

1I2C Transmit Character written to SSPxBUF has not been sent

0I2C Transmit SSPxBUF is ready for next character

1SPI and I2C Receive Received character in SSPxBUF has not been read

0SPI and I2C Receive Received character in SSPxBUF has been read

Note:

1. This bit is cleared on Reset and when SSPEN is cleared.

2. In I2C Slave mode this bit holds the R/W bit information following the last address match. This bit is

only valid from the address match to the next Start bit, Stop bit or not ACK bit.

3. ORing this bit with SEN, RSEN, PEN, RCEN or ACKEN will indicate if the MSSP is in Active mode.

4. Polarity of clock state is set by the CKP bit.

5. I2C receive status does not include ACK and Stop bits.

PIC18F26/45/46Q10

(MSSP) Master Synchronous Serial Port Module

27.9.2 SSPxCON1

Name: SSPxCON1

Address: 0xF95,0xE91

MSSP Control Register 1

Bit 7 6 5 4 3 2 1 0

WCOL SSPOV SSPEN CKP SSPM[3:0]

Access R/W/HS R/W/HS R/W R/W R/W R/W R/W R/W

Reset 0 0 0 0 0 0 0 0

Bit 7 – WCOL

Write Collision Detect bit

Value Mode Description

1SPI A write to the SSPxBUF register was attempted while the previous

byte was still transmitting (must be cleared by software)

1I2C Master transmit A write to the SSPxBUF register was attempted while the I2C

conditions were not valid for a transmission to be started (must be

cleared by software)

1I2C Slave transmit The SSPxBUF register is written while it is still transmitting the

previous word (must be cleared in software)

0SPI or I2C Master or

Slave transmit

No collision

xMaster or Slave

receive

Don't care

Bit 6 – SSPOV

Receive Overflow Indicator bit(1)

Value Mode Description

1SPI Slave A byte is received while the SSPxBUF register is still holding the

previous byte. The user must read SSPxBUF, even if only

transmitting data, to avoid setting overflow. (must be cleared in

software)

1I2C Receive A byte is received while the SSPxBUF register is still holding the

previous byte (must be cleared in software)

0SPI Slave or I2C

Receive

No overflow

xSPI Master or I2C

Master transmit

Don't care

Bit 5 – SSPEN

Master Synchronous Serial Port Enable bit.(2)

Value Mode Description

1SPI Enables the serial port. The SCKx, SDOx, SDIx, and SSx pin selections must be

made with the PPS controls. Each signal must be configured with the corresponding

TRIS control to the direction appropriate for the mode selected.

PIC18F26/45/46Q10

(MSSP) Master Synchronous Serial Port Module

Value Mode Description

1I2C Enables the serial port. The SDAx and SCLx pin selections must be made with the

PPS controls. Since both signals are bidirectional the PPS input pin and PPS output

pin selections must be made that specify the same pin. Both pins must be configured

as inputs with the corresponding TRIS controls.

0All Disables serial port and configures these pins as I/O port pins

Bit 4 – CKP

SCK Release Control bit

Value Mode Description

1SPI Idle state for the clock is a high level

0SPI Idle state for the clock is a low level

1I2C Slave Releases clock

0I2C Slave Holds clock low (clock stretch), used to ensure data setup time

xI2C Master Unused in this mode

Bits 3:0 – SSPM[3:0]

Master Synchronous Serial Port Mode Select bits(4)

Value Description

1111 I2C Slave mode: 10-bit address with Start and Stop bit interrupts enabled

1110 I2C Slave mode: 7-bit address with Start and Stop bit interrupts enabled

1101 Reserved - do not use

1100 Reserved - do not use

1011 I2C Firmware Controlled Master mode (slave Idle)

1010 SPI Master mode: Clock = FOSC/(4*(SSPxADD+1)). SSPxADD must be greater than 0.(3)

1001 Reserved - do not use

1000 I2C Master mode: Clock = FOSC/(4 * (SSPxADD + 1))

0111 I2C Slave mode: 10-bit address

0110 I2C Slave mode: 7-bit address

0101 SPI Slave mode: Clock = SCKx pin. SSx pin control is disabled

0100 SPI Slave mode: Clock = SCKx pin. SSx pin control is enabled

0011 SPI Master mode: Clock = TMR2 output/2

0010 SPI Master mode: Clock = Fosc/64

0001 SPI Master mode: Clock = Fosc/16

0000 SPI Master mode: Clock = Fosc/4

Note:

1. In Master mode, the overflow bit is not set since each new reception (and transmission) is initiated

by writing to the SSPxBUF register.

2. When enabled, these pins must be properly configured as inputs or outputs.

3. SSPxADD = 0 is not supported.

4. Bit combinations not specifically listed here are either reserved or implemented in I2C mode only.

PIC18F26/45/46Q10

(MSSP) Master Synchronous Serial Port Module

27.9.3 SSPxCON2

Name: SSPxCON2

Address: 0xF96,0xE92

Control Register for I2C Operation Only

MSSP Control Register 2

Bit 7 6 5 4 3 2 1 0

GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN

Access R/W R/W/HC R/W R/W R/W R/W R/W R/W

Reset 0 0 0 0 0 0 0 0

Bit 7 – GCEN

General Call Enable bit (Slave mode only)

Value Mode Description

xMaster mode Don't care

1Slave mode General call is enabled

0Slave mode General call is not enabled

Bit 6 – ACKSTAT Acknowledge Status bit (Master Transmit mode only)

Value Description

1Acknowledge was not received from slave

0Acknowledge was received from slave

Bit 5 – ACKDT

Acknowledge Data bit (Master Receive mode only)(1)

Value Description

1Not Acknowledge

0Acknowledge

Bit 4 – ACKEN

Acknowledge Sequence Enable bit(2)

Value Description

1Initiates Acknowledge sequence on SDAx and SCLx pins and transmits ACKDT data bit;

automatically cleared by hardware

0Acknowledge sequence is Idle

Bit 3 – RCEN

Receive Enable bit (Master Receive mode only)(2)

Value Description

1Enables Receive mode for I2C

0Receive is Idle

Bit 2 – PEN

Stop Condition Enable bit (Master mode only)(2)

Value Description

1Initiates Stop condition on SDAx and SCLx pins; automatically cleared by hardware

0Stop condition is Idle

PIC18F26/45/46Q10

(MSSP) Master Synchronous Serial Port Module

Bit 1 – RSEN

Repeated Start Condition Enable bit (Master mode only)(2)

Value Description

1Initiates Repeated Start condition on SDAx and SCLx pins; automatically cleared by

hardware

0Repeated Start condition is Idle

Bit 0 – SEN

Start Condition Enable bit (Master mode only)(2)

Value Description

1Initiates Start condition on SDAx and SCLx pins; automatically cleared by hardware

0Start condition is Idle

Note:

1. The value that will be transmitted when the user initiates an Acknowledge sequence at the end of a

receive.

2. If the I2C module is active, these bits may not be set (no spooling) and the SSPxBUF may not be

written (or writes to the SSPxBUF are disabled).

PIC18F26/45/46Q10

(MSSP) Master Synchronous Serial Port Module

27.9.4 SSPxCON3

Name: SSPxCON3

Address: 0xF97,0xE93

MSSP Control Register 3

Bit 7 6 5 4 3 2 1 0

ACKTIM PCIE SCIE BOEN SDAHT SBCDE AHEN DHEN

Access R/HS/HC R/W R/W R/W R/W R/W R/W R/W

Reset 0 0 0 0 0 0 0 0

Bit 7 – ACKTIM Acknowledge Time Status bit

Unused in Master mode.

Value Mode Description

xSPI or I2C Master This bit is not used

1I2C Slave and AHEN = 1 or

DHEN = 1

Eighth falling edge of SCL has occurred and the ACK/

NACK state is active

0I2C Slave ACK/NACK state is not active. Transitions low on ninth

rising edge of SCL.

Bit 6 – PCIE

Stop Condition Interrupt Enable bit(1)

Value Mode Description

xSPI or SSPM = 1111 or 0111 Don't care

1SSPM ≠ 1111 and SSPM ≠ 0111 Enable interrupt on detection of Stop condition

0SSPM ≠ 1111 and SSPM ≠ 0111 Stop detection interrupts are disabled

Bit 5 – SCIE Start Condition Interrupt Enable bit

Value Mode Description

xSPI or SSPM = 1111 or 0111 Don't care

1SSPM ≠ 1111 and SSPM ≠ 0111 Enable interrupt on detection of Start condition

0SSPM ≠ 1111 and SSPM ≠ 0111 Start detection interrupts are disabled

Bit 4 – BOEN

Buffer Overwrite Enable bit(2)

Value Mode Description

1SPI SSPxBUF is updated every time a new data byte is available, ignoring the BF bit

0SPI If a new byte is receive with BF set then SSPOV is set and SSPxBUF is not updated

1I2C SSPxBUF is updated every time a new data byte is available, ignoring the SSPOV

effect on updating the buffer

0I2C SSPxBUF is only updated when SSPOV is clear

Bit 3 – SDAHT SDA Hold Time Selection bit

Value Mode Description

xSPI Not used in SPI mode

1I2C Minimum of 300ns hold time on SDA after the falling edge of SCL

0I2C Minimum of 100ns hold time on SDA after the falling edge of SCL

PIC18F26/45/46Q10

(MSSP) Master Synchronous Serial Port Module

Bit 2 – SBCDE Slave Mode Bus Collision Detect Enable bit

Unused in Master mode.

Value Mode Description

xSPI or I2C Master Don't care

1I2C Slave Collision detection is enabled

0I2C Slave Collision detection is not enabled

Bit 1 – AHEN Address Hold Enable bit

Value Mode Description

xSPI or I2C Master Don't care

1I2C Slave Address hold is enabled. As a result CKP is cleared after the eighth

falling SCL edge of an address byte reception. Software must set the

CKP bit to resume operation.

0I2C Slave Address hold is not enabled

Bit 0 – DHEN Data Hold Enable bit

Value Mode Description

xSPI or I2C Master Don't care

1I2C Slave Data hold is enabled. As a result CKP is cleared after the eighth falling

SCL edge of a data byte reception. Software must set the CKP bit to

resume operation.

0I2C Slave Data hold is not enabled

Note:

1. This bit has no effect in Slave modes that Start and Stop condition detection is explicitly listed as

enabled.

2. For daisy-chained SPI operation; allows the user to ignore all but the last received byte. SSPOV is

still set when a new byte is received and BF = 1, but hardware continues to write the most recent

byte to SSPxBUF.

PIC18F26/45/46Q10

(MSSP) Master Synchronous Serial Port Module

27.9.5 SSPxBUF

Name: SSPxBUF

Address: 0xF91,0xE8D

MSSP Data Buffer Register

Bit 7 6 5 4 3 2 1 0

BUF[7:0]

Access R/W R/W R/W R/W R/W R/W R/W R/W

Reset x x x x x x x x

Bits 7:0 – BUF[7:0] MSSP Input and Output Data Buffer bits

PIC18F26/45/46Q10

(MSSP) Master Synchronous Serial Port Module

27.9.6 SSPxADD

Name: SSPxADD

Address: 0xF92,0xE8E

MSSP Baud Rate Divider and Address Register

Bit 7 6 5 4 3 2 1 0

ADD[7:0]

Access R/W R/W R/W R/W R/W R/W R/W R/W

Reset 0 0 0 0 0 0 0 0

Bits 7:0 – ADD[7:0]

• SPI and I2C Master: Baud rate divider

• I2C Slave: Address bits

Value Mode Description

3 to

255

SPI and I2C Master Baud rate divider. SCK/SCL pin clock period = ((n + 1) *4)/FOSC.

Values less than 3 are not valid.

2,4,6,8 I2C 10-bit Slave MS

Address

Bits 7-3 and Bit 0 are not used and are don't care. Bits 2:1 are bits

9:8 of the 10-bit Slave Most Significant Address

nI2C 10-bit Slave LS

Address

Bits 7:0 of 10-Bit Slave Least Significant Address

2*(1 to

127)

I2C 7-bit Slave Bit 0 is not used and is don't care. Bits 7:1 are the 7-bit Slave

Address

PIC18F26/45/46Q10

(MSSP) Master Synchronous Serial Port Module

27.9.7 SSPxMSK

Name: SSPxMSK

Address: 0xF93,0xE8F

MSSP Address Mask Register

Bit 7 6 5 4 3 2 1 0

MSK[6:0] MSK0

Access R/W R/W R/W R/W R/W R/W R/W R/W

Reset 1 1 1 1 1 1 1 1

Bits 7:1 – MSK[6:0] Mask bits

Value Mode Description

1I2C Slave The received address bit n is compared to SSPxADD bit n to detect I2C address

match

0I2C Slave The received address bit n is not used to detect I2C address match

Bit 0 – MSK0

Mask bit for I2C 10-bit Slave mode

Value Mode Description

1I2C 10-bit Slave The received address bit 0 is compared to SSPxADD bit 0 to detect I2C

address match

0I2C 10-bit Slave The received address bit 0 is not used to detect I2C address match

xSPI or I2C 7-bit Don't care

PIC18F26/45/46Q10

(MSSP) Master Synchronous Serial Port Module

28. (EUSART) Enhanced Universal Synchronous Asynchronous Receiver

Transmitter

The Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART) module is a serial

I/O communications peripheral. It contains all the clock generators, shift registers and data buffers

necessary to perform an input or output serial data transfer independent of device program execution.

The EUSART, also known as a Serial Communications Interface (SCI), can be configured as a full-duplex

asynchronous system or half-duplex synchronous system. Full-Duplex mode is useful for communications

with peripheral systems, such as CRT terminals and personal computers. Half-Duplex Synchronous

mode is intended for communications with peripheral devices, such as A/D or D/A integrated circuits,

serial EEPROMs or other microcontrollers. These devices typically do not have internal clocks for baud

rate generation and require the external clock signal provided by a master synchronous device.

The EUSART module includes the following capabilities:

• Full-duplex asynchronous transmit and receive

• Two-character input buffer

• One-character output buffer

• Programmable 8-bit or 9-bit character length

• Address detection in 9-bit mode

• Input buffer overrun error detection

• Received character framing error detection

• Half-duplex synchronous master

• Half-duplex synchronous slave

• Programmable clock polarity in Synchronous modes

• Sleep operation

The EUSART module implements the following additional features, making it ideally suited for use in

Local Interconnect Network (LIN) bus systems:

• Automatic detection and calibration of the baud rate

• Wake-up on Break reception

• 13-bit Break character transmit

Block diagrams of the EUSART transmitter and receiver are shown in Figure 28-1 and Figure 28-2.

The operation of the EUSART module consists of six registers:

• Transmit Status and Control (28.6.2 TXxSTA)

• Receive Status and Control (28.6.1 RCxSTA)

• Baud Rate Control (28.6.3 BAUDxCON)

• Baud Rate Value (28.6.4 SPxBRG)

• Receive Data Register (28.6.5 RCxREG)

• Transmit Data Register (28.6.6 TXxREG)

The RXx/DTx and TXx/CKx input pins are selected with the RXxPPS and TXxPPS registers, respectively.

TXx, CKx, and DTx output pins are selected with each pin’s RxyPPS register. Since the RX input is

coupled with the DT output in Synchronous mode, it is the user’s responsibility to select the same pin for

both of these functions when operating in Synchronous mode. The EUSART control logic will control the

data direction drivers automatically.

PIC18F26/45/46Q10

(EUSART) Enhanced Universal Synchronous Asyn...

Figure 28-1. EUSART Transmit Block Diagram

TXREG register

8

Pin Buffer

and Control

TXIF

TRMT

TX9D

Data bus

8TXIE

Inte rrupt

RXx/DTx Pin

TX_out

TX9

TXEN

Transmit Shift Register (TSR)

(8) 0

MSb LSb

÷ n

Multiplier x4

SYNC

BRGH

BRG16

x16 x64

1

x

x 0

0

n

+ 1

SPBRG H SPBRGL

Baud Rate Generator FOSC

BRG16

Rev. 10-000 113C

2/15/201 7

PPS

RxyPPS(1)

0

1

0

SYNC

CSRC

PPS

CKx Pin

CKPPS(2)

PPS

RxyPPS(2)

SYNC

CSRC

TXx/CKx Pi n

Not e 1: In Synchronous mod e, the DT output and RX input PPS

selections should enable the same pin.

2: In Master Syn chronous mode the TX output and CK inpu t

PPS selections shou ld enable the sa me pin.

PIC18F26/45/46Q10

(EUSART) Enhanced Universal Synchronous Asyn...

Figure 28-2. EUSART Receive Block Diagram

÷ n

Multiplier x4

SYNC

BRGH

BRG16

x16 x64

1

x

x 0

0

n

+ 1

SPBRG H SPBRGL

Baud Rate Generator FOSC

BRG16

SPEN

CRE N OERR RCIDL

Pin Buffer

and Control

Data

Recovery

RXx/DTx pin

Stop (8) 7 Start01

MSb LSb

RSR Register

RX9

FERR RX9D RCREG Register

FIFO

8

Data B us

RCxIE

RCxIF Inte rrupt

Rev. 10-000 114B

2/15/201 7

PPS

RXPPS(1)

Not e 1: In S ynchronous mod e, the DT output and RX input PPS

selectio ns should en able the same pin.

2: In Master S ynchr onous mode the TX output and CK input

PPS selections shou ld enable the sa me pin.

1

0

SYNC

CSRC

PPS

CKx Pin

CKPPS(2)

28.1 EUSART Asynchronous Mode

The EUSART transmits and receives data using the standard non-return-to-zero (NRZ) format. NRZ is

implemented with two levels: a VOH Mark state which represents a ‘1’ data bit, and a VOL Space state

which represents a ‘0’ data bit. NRZ refers to the fact that consecutively transmitted data bits of the same

value stay at the output level of that bit without returning to a neutral level between each bit transmission.

An NRZ transmission port idles in the Mark state. Each character transmission consists of one Start bit

followed by eight or nine data bits and is always terminated by one or more Stop bits. The Start bit is

always a space and the Stop bits are always marks. The most common data format is eight bits. Each

transmitted bit persists for a period of 1/(Baud Rate). An on-chip dedicated 8-bit/16-bit Baud Rate

Generator is used to derive standard baud rate frequencies from the system oscillator. See Table 28-2 for

examples of baud rate configurations.

The EUSART transmits and receives the LSb first. The EUSART’s transmitter and receiver are

functionally independent, but share the same data format and baud rate. Parity is not supported by the

hardware, but can be implemented in software and stored as the ninth data bit.

28.1.1 EUSART Asynchronous Transmitter

The Figure 28-1 is a simplified representation of the transmitter. The heart of the transmitter is the serial

Transmit Shift Register (TSR), which is not directly accessible by software. The TSR obtains its data from

the transmit buffer, which is the TXxREG register.

28.1.1.1 Enabling the Transmitter

The EUSART transmitter is enabled for asynchronous operations by configuring the following three

control bits:

PIC18F26/45/46Q10

(EUSART) Enhanced Universal Synchronous Asyn...

• TXEN = 1 (enables the transmitter circuitry of the EUSART)

• SYNC = 0 (configures the EUSART for asynchronous operation)

• SPEN = 1 (enables the EUSART and automatically enables the output drivers for the RxyPPS

selected as the TXx/CKx output)

All other EUSART control bits are assumed to be in their default state.

If the TXx/CKx pin is shared with an analog peripheral, the analog I/O function must be disabled by

clearing the corresponding ANSEL bit.

Important: The TXxIF Transmitter Interrupt flag is set when the TXEN enable bit is set and the

TSR is idle.

28.1.1.2 Transmitting Data

A transmission is initiated by writing a character to the TXxREG register. If this is the first character, or the

previous character has been completely flushed from the TSR, the data in the TXxREG is immediately

transferred to the TSR register. If the TSR still contains all or part of a previous character, the new

character data is held in the TXxREG until the Stop bit of the previous character has been transmitted.

The pending character in the TXxREG is then transferred to the TSR in one TCY immediately following the

Stop bit transmission. The transmission of the Start bit, data bits and Stop bit sequence commences

immediately following the transfer of the data to the TSR from the TXxREG.

28.1.1.3 Transmit Data Polarity

The polarity of the transmit data can be controlled with the SCKP bit of the BAUDxCON register. The

default state of this bit is ‘0’ which selects high true transmit idle and data bits. Setting the SCKP bit to ‘1’

will invert the transmit data resulting in low true idle and data bits. The SCKP bit controls transmit data

polarity in Asynchronous mode only. In Synchronous mode, the SCKP bit has a different function. See the

28.3.1.2 Clock Polarity section for more detail.

28.1.1.4 Transmit Interrupt Flag

The TXxIF interrupt flag bit of the PIRx register is set whenever the EUSART transmitter is enabled and

no character is being held for transmission in the TXxREG. In other words, the TXxIF bit is only clear

when the TSR is busy with a character and a new character has been queued for transmission in the

TXxREG. The TXxIF flag bit is not cleared immediately upon writing TXxREG. TXxIF becomes valid in the

second instruction cycle following the write execution. Polling TXxIF immediately following the TXxREG

write will return invalid results. The TXxIF bit is read-only, it cannot be set or cleared by software.

The TXxIF interrupt can be enabled by setting the TXxIE interrupt enable bit of the PIEx register.

However, the TXxIF flag bit will be set whenever the TXxREG is empty, regardless of the state of TXxIE

enable bit.

To use interrupts when transmitting data, set the TXxIE bit only when there is more data to send. Clear

the TXxIE interrupt enable bit upon writing the last character of the transmission to the TXxREG.

28.1.1.5 TSR Status

The TRMT bit of the TXxSTA register indicates the status of the TSR register. This is a read-only bit. The

TRMT bit is set when the TSR register is empty and is cleared when a character is transferred to the TSR

register from the TXxREG. The TRMT bit remains clear until all bits have been shifted out of the TSR

register. No interrupt logic is tied to this bit, so the user needs to poll this bit to determine the TSR status.

PIC18F26/45/46Q10

(EUSART) Enhanced Universal Synchronous Asyn...

Important: The TSR register is not mapped in data memory, so it is not available to the user.

28.1.1.6 Transmitting 9-Bit Characters

The EUSART supports 9-bit character transmissions. When the TX9 bit of the TXxSTA register is set, the

EUSART will shift nine bits out for each character transmitted. The TX9D bit of the TXxSTA register is the

ninth, and Most Significant data bit. When transmitting 9-bit data, the TX9D data bit must be written

before writing the eight Least Significant bits into the TXxREG. All nine bits of data will be transferred to

the TSR shift register immediately after the TXxREG is written.

A special 9-bit Address mode is available for use with multiple receivers. See the 28.1.2.7 Address

Detection section for more information on the Address mode.

28.1.1.7 Asynchronous Transmission Setup

1. Initialize the SPxBRGH, SPxBRGL register pair and the BRGH and BRG16 bits to achieve the

desired baud rate (see 28.2 EUSART Baud Rate Generator (BRG)).

2. Select the transmit output pin by writing the appropriate value to the RxyPPS register.

3. Enable the asynchronous serial port by clearing the SYNC bit and setting the SPEN bit.

4. If 9-bit transmission is desired, set the TX9 control bit. A set ninth data bit will indicate that the eight

Least Significant data bits are an address when the receiver is set for address detection.

5. Set SCKP bit if inverted transmit is desired.

6. Enable the transmission by setting the TXEN control bit. This will cause the TXxIF interrupt bit to be

set.

7. If interrupts are desired, set the TXxIE interrupt enable bit of the PIEx register

8. An interrupt will occur immediately provided that the GIE and PEIE bits of the INTCON register are

also set.

9. If 9-bit transmission is selected, the ninth bit should be loaded into the TX9D data bit.

10. Load 8-bit data into the TXxREG register. This will start the transmission.

Figure 28-3. Asynchronous Transmission

Rev. 10-000 115A

2/7/201 7

Write to TXxREG

BRG Output

(Shift Clock)

TXx/CKx pin

TXxIF bit

(Transmit Buffer

Reg Empty Flag)

TRMT bit

(Transmit Shift

Reg Empty Flag)

Start bit bit 0 bit 1 bit 7/8 Stop bit

1 TCY

Word 1

PIC18F26/45/46Q10

(EUSART) Enhanced Universal Synchronous Asyn...

Figure 28-4. Asynchronous Transmission (Back-to-Back)

Rev. 10-000 116A

2/7/201 7

Write to TXxREG

BRG Output

(Shift Clock)

TXx/CKx pin

TXxIF bit

(Transmit Buffer

Reg Empty Flag)

TRMT bit

(Transmit Shift

Reg Empty Flag)

Start bit bit 0 bit 1 bit 7/8 Stop bit

1 TCY

Word 1

Start bit bit 0

Word 2

Word 1 Word 2

28.1.2 EUSART Asynchronous Receiver

The Asynchronous mode is typically used in RS-232 systems. A simplified representation of the receiver

is shown in the Figure 28-2. The data is received on the RXx/DTx pin and drives the data recovery block.

The data recovery block is actually a high-speed shifter operating at 16 times the baud rate, whereas the

serial Receive Shift Register (RSR) operates at the bit rate. When all eight or nine bits of the character

have been shifted in, they are immediately transferred to a two character First-In-First-Out (FIFO)

memory. The FIFO buffering allows reception of two complete characters and the start of a third character

before software must start servicing the EUSART receiver. The FIFO and RSR registers are not directly

accessible by software. Access to the received data is via the RCxREG register.

28.1.2.1 Enabling the Receiver

The EUSART receiver is enabled for asynchronous operation by configuring the following three control

bits:

• CREN = 1 (enables the receiver circuitry of the EUSART)

• SYNC = 0 (configures the EUSART for asynchronous operation)

• SPEN = 1 (enables the EUSART)

All other EUSART control bits are assumed to be in their default state.

The user must set the RXxPPS register to select the RXx/DTx I/O pin and set the corresponding TRIS bit

to configure the pin as an input.

Important: If the RX/DT function is on an analog pin, the corresponding ANSEL bit must be

cleared for the receiver to function.

28.1.2.2 Receiving Data

The receiver data recovery circuit initiates character reception on the falling edge of the first bit. The first

bit, also known as the Start bit, is always a zero. The data recovery circuit counts one-half bit time to the

center of the Start bit and verifies that the bit is still a zero. If it is not a zero then the data recovery circuit

aborts character reception, without generating an error, and resumes looking for the falling edge of the

Start bit. If the Start bit zero verification succeeds then the data recovery circuit counts a full bit time to

the center of the next bit. The bit is then sampled by a majority detect circuit and the resulting ‘0’ or ‘1’ is

shifted into the RSR. This repeats until all data bits have been sampled and shifted into the RSR. One

final bit time is measured and the level sampled. This is the Stop bit, which is always a ‘1’. If the data

PIC18F26/45/46Q10

(EUSART) Enhanced Universal Synchronous Asyn...

recovery circuit samples a ‘0’ in the Stop bit position then a framing error is set for this character,

otherwise the framing error is cleared for this character. See the 28.1.2.4 Receive Framing Error section

for more information on framing errors.

Immediately after all data bits and the Stop bit have been received, the character in the RSR is

transferred to the EUSART receive FIFO and the RCxIF interrupt flag bit of the PIRx register is set. The

top character in the FIFO is transferred out of the FIFO by reading the RCxREG register.

Important: If the receive FIFO is overrun, no additional characters will be received until the

overrun condition is cleared. See the 28.1.2.5 Receive Overrun Error section for more

information.

28.1.2.3 Receive Interrupts

The RCxIF interrupt flag bit of the PIRx register is set whenever the EUSART receiver is enabled and

there is an unread character in the receive FIFO. The RCxIF interrupt flag bit is read-only, it cannot be set

or cleared by software.

RCxIF interrupts are enabled by setting all of the following bits:

• RCxIE, Interrupt Enable bit of the PIEx register

• PEIE, Peripheral Interrupt Enable bit of the INTCON register

• GIE, Global Interrupt Enable bit of the INTCON register

The RCxIF interrupt flag bit will be set when there is an unread character in the FIFO, regardless of the

state of interrupt enable bits.

28.1.2.4 Receive Framing Error

Each character in the receive FIFO buffer has a corresponding framing error Status bit. A framing error

indicates that a Stop bit was not seen at the expected time. The framing error status is accessed via the

FERR bit of the RCxSTA register. The FERR bit represents the status of the top unread character in the

receive FIFO. Therefore, the FERR bit must be read before reading the RCxREG.

The FERR bit is read-only and only applies to the top unread character in the receive FIFO. A framing

error (FERR = 1) does not preclude reception of additional characters. It is not necessary to clear the

FERR bit. Reading the next character from the FIFO buffer will advance the FIFO to the next character

and the next corresponding framing error.

The FERR bit can be forced clear by clearing the SPEN bit of the RCxSTA register which resets the

EUSART. Clearing the CREN bit of the RCxSTA register does not affect the FERR bit. A framing error by

itself does not generate an interrupt.

Important: If all receive characters in the receive FIFO have framing errors, repeated reads of

the RCxREG will not clear the FERR bit.

28.1.2.5 Receive Overrun Error

The receive FIFO buffer can hold two characters. An overrun error will be generated if a third character, in

its entirety, is received before the FIFO is accessed. When this happens the OERR bit of the RCxSTA

register is set. The characters already in the FIFO buffer can be read but no additional characters will be

received until the error is cleared. The error must be cleared by either clearing the CREN bit of the

RCxSTA register or by resetting the EUSART by clearing the SPEN bit of the RCxSTA register.

PIC18F26/45/46Q10

(EUSART) Enhanced Universal Synchronous Asyn...

28.1.2.6 Receiving 9-Bit Characters

The EUSART supports 9-bit character reception. When the RX9 bit of the RCxSTA register is set the

EUSART will shift nine bits into the RSR for each character received. The RX9D bit of the RCxSTA

register is the ninth and Most Significant data bit of the top unread character in the receive FIFO. When

reading 9-bit data from the receive FIFO buffer, the RX9D data bit must be read before reading the eight

Least Significant bits from the RCxREG.

28.1.2.7 Address Detection

A special Address Detection mode is available for use when multiple receivers share the same

transmission line, such as in RS-485 systems. Address detection is enabled by setting the ADDEN bit of

the RCxSTA register.

Address detection requires 9-bit character reception. When address detection is enabled, only characters

with the ninth data bit set will be transferred to the receive FIFO buffer, thereby setting the RCxIF interrupt

bit. All other characters will be ignored.

Upon receiving an address character, user software determines if the address matches its own. Upon

address match, user software must disable address detection by clearing the ADDEN bit before the next

Stop bit occurs. When user software detects the end of the message, determined by the message

protocol used, software places the receiver back into the Address Detection mode by setting the ADDEN

bit.

28.1.2.8 Asynchronous Reception Setup

1. Initialize the SPxBRGH:SPxBRGL register pair and the BRGH and BRG16 bits to achieve the

desired baud rate (see the 28.2 EUSART Baud Rate Generator (BRG) section).

2. Set the RXxPPS register to select the RXx/DTx input pin.

3. Clear the ANSEL bit for the RXx pin (if applicable).

4. Enable the serial port by setting the SPEN bit. The SYNC bit must be clear for asynchronous

operation.

5. If interrupts are desired, set the RCxIE bit of the PIEx register and the GIE and PEIE bits of the

INTCON register.

6. If 9-bit reception is desired, set the RX9 bit.

7. Enable reception by setting the CREN bit.

8. The RCxIF interrupt flag bit will be set when a character is transferred from the RSR to the receive

buffer. An interrupt will be generated if the RCxIE interrupt enable bit was also set.

9. Read the RCxSTA register to get the error flags and, if 9-bit data reception is enabled, the ninth

data bit.

10. Get the received eight Least Significant data bits from the receive buffer by reading the RCxREG

register.

11. If an overrun occurred, clear the OERR flag by clearing the CREN receiver enable bit.

28.1.2.9 9-Bit Address Detection Mode Setup

This mode would typically be used in RS-485 systems. To set up an Asynchronous Reception with

Address Detect Enable follow these steps:

1. Initialize the SPxBRGH:SPxBRGL register pair and the BRGH and BRG16 bits to achieve the

desired baud rate (see the 28.2 EUSART Baud Rate Generator (BRG) section).

2. Set the RXxPPS register to select the RXx input pin.

3. Clear the ANSEL bit for the RXx pin (if applicable).

4. Enable the serial port by setting the SPEN bit. The SYNC bit must be clear for asynchronous

operation.

PIC18F26/45/46Q10

(EUSART) Enhanced Universal Synchronous Asyn...

5. If interrupts are desired, set the RCxIE bit of the PIEx register and the GIE and PEIE bits of the

INTCON register.

6. Enable 9-bit reception by setting the RX9 bit.

7. Enable address detection by setting the ADDEN bit.

8. Enable reception by setting the CREN bit.

9. The RCxIF interrupt flag bit will be set when a character with the ninth bit set is transferred from the

RSR to the receive buffer. An interrupt will be generated if the RCxIE Interrupt Enable bit is also

set.

10. Read the RCxSTA register to get the error flags. The ninth data bit will always be set.

11. Get the received eight Least Significant data bits from the receive buffer by reading the RCxREG

register. Software determines if this is the device’s address.

12. If an overrun occurred, clear the OERR flag by clearing the CREN receiver enable bit.

13. If the device has been addressed, clear the ADDEN bit to allow all received data into the receive

buffer and generate interrupts.

Figure 28-5. Asynchronous Reception

Rev. 10-000 117A

2/8/201 7

RXx/DTx

Start

bit bit 0

Word 1

bit 7/8 Stop

bit

Start

bit bit 0 bit 7/8 Stop

bit

Start

bit bit 0 bit 7/8 Stop

bit

Word 3Word 2

Rcv Shift Reg

Rcv Buffer Reg

Word 1

RCxREG

Word 2

RCxREG

RCIDL

Read

RCxREG

OERR Flag

CREN

(software clear)

RCxIF

(Interrupt flag)

Note: This timing diagram shows three bytes appearing on the RXx input. The OERR flag is set because the

RCxREG is not read before the third word is received.

28.1.3 Clock Accuracy with Asynchronous Operation

The factory calibrates the internal oscillator block output (INTOSC). However, the INTOSC frequency may

drift as VDD or temperature changes, and this directly affects the asynchronous baud rate. Two methods

may be used to adjust the baud rate clock, but both require a reference clock source of some kind.

The first (preferred) method uses the OSCTUNE register to adjust the INTOSC output. Adjusting the

value in the OSCTUNE register allows for fine resolution changes to the system clock source.

The other method adjusts the value in the Baud Rate Generator. This can be done automatically with the

Auto-Baud Detect feature (see 28.2.1 Auto-Baud Detect). There may not be fine enough resolution when

adjusting the Baud Rate Generator to compensate for a gradual change in the peripheral clock frequency.

PIC18F26/45/46Q10

(EUSART) Enhanced Universal Synchronous Asyn...

28.2 EUSART Baud Rate Generator (BRG)

The Baud Rate Generator (BRG) is an 8-bit or 16-bit timer that is dedicated to the support of both the

asynchronous and synchronous EUSART operation. By default, the BRG operates in 8-bit mode. Setting

the BRG16 bit of the BAUDxCON register selects 16-bit mode.

The SPxBRGH, SPxBRGL register pair determines the period of the free-running baud rate timer. In

Asynchronous mode the multiplier of the baud rate period is determined by both the BRGH bit of the

TXxSTA register and the BRG16 bit of the BAUDxCON register. In Synchronous mode, the BRGH bit is

ignored.

Table 28-1 contains the formulas for determining the baud rate. Figure 28-6 provides a sample calculation

for determining the baud rate and baud rate error.

Typical baud rates and error values for various asynchronous modes have been computed and are

shown in Table 28-2. It may be advantageous to use the high baud rate (BRGH = 1), or the 16-bit BRG

(BRG16 = 1) to reduce the baud rate error. The 16-bit BRG mode is used to achieve slow baud rates for

fast oscillator frequencies. The BRGH bit is used to achieve very high baud rates.

Writing a new value to the SPxBRGH, SPxBRGL register pair causes the BRG timer to be reset (or

cleared). This ensures that the BRG does not wait for a timer overflow before outputting the new baud

rate.

If the system clock is changed during an active receive operation, a receive error or data loss may result.

To avoid this problem, check the status of the RCIDL bit to make sure that the receive operation is idle

before changing the system clock.

Figure 28-6. Calculating Baud Rate Error

For a device with Fosc of 16 MHz, desired baud rate of 9600, Asynchronous mode, 8-bit BRG:

 =

64× + 1

Solving for SPxBRG:

 =

64× 1

 =16000000

64 × 9600 1

 = 25.042 25

 =16000000

64 × 25 + 1

 = 9615

 =  



 =9615 9600

9600

 = 0.16 %

PIC18F26/45/46Q10

(EUSART) Enhanced Universal Synchronous Asyn...

Table 28-1. Baud Rate Formulas

Configuration Bits

BRG/EUSART Mode Baud Rate Formula

SYNC BRG16 BRGH

0 0 0 8-bit/Asynchronous FOSC/[64 (n+1)]

0 0 1 8-bit/Asynchronous

FOSC/[16 (n+1)]

0 1 0 16-bit/Asynchronous

0 1 1 16-bit/Asynchronous

FOSC/[4 (n+1)]

1 0 x 8-bit/Synchronous

1 1 x 16-bit/Synchronous

Note: x = Don’t care, n = value of SPxBRGH:SPxBRGL register pair.

Table 28-2. Sample Baud Rates for Asynchronous Modes

BAUD

RATE

SYNC = 0, BRGH = 0, BRG16 = 0

FOSC = 32.000 MHz FOSC = 20.000 MHz FOSC = 18.432 MHz FOSC = 11.0592 MHz

Actual

Rate

%

Error

SPBRG

value

(decimal)

Actual

Rate

%

Error

SPBRG

value

(decimal)

Actual

Rate

%

Error

SPBRG

value

(decimal)

Actual

Rate

%

Error

SPBRG

value

(decimal)

300 — — — — — — — — — — — —

1200 — — — 1221 1.73 255 1200 0.00 239 1200 0.00 143

2400 2404 0.16 207 2404 0.16 129 2400 0.00 119 2400 0.00 71

9600 9615 0.16 51 9470 -1.36 32 9600 0.00 29 9600 0.00 17

10417 10417 0.00 47 10417 0.00 29 10286 -1.26 27 10165 -2.42 16

19.2k 19.23k 0.16 25 19.53k 1.73 15 19.20k 0.00 14 19.20k 0.00 8

57.6k 55.55k -3.55 3 — — — 57.60k 0.00 7 57.60k 0.00 2

115.2k — — — — — — — — — — — —

BAUD

RATE

SYNC = 0, BRGH = 0, BRG16 = 0

Fosc = 8.000 MHz Fosc = 4.000 MHz Fosc = 3.6864 MHz Fosc = 1.000 MHz

Actual

Rate

%

Error

SPBRG

value

(decimal)

Actual

Rate

%

Error

SPBRG

value

(decimal)

Actual

Rate

%

Error

SPBRG

value

(decimal)

Actual

Rate

%

Error

SPBRG

value

(decimal)

300 — — — 300 0.16 207 300 0.00 191 300 0.16 51

1200 1202 0.16 103 1202 0.16 51 1200 0.00 47 1202 0.16 12

2400 2404 0.16 51 2404 0.16 25 2400 0.00 23 — — —

9600 9615 0.16 12 — — — 9600 0.00 5 — — —

PIC18F26/45/46Q10

(EUSART) Enhanced Universal Synchronous Asyn...

10417 10417 0.00 11 10417 0.00 5 — — — — — —

19.2k — — — — — — 19.20k 0.00 2 — — —

57.6k — — — — — — 57.60k 0.00 0 — — —

115.2k — — — — — — — — — — — —

BAUD

RATE

SYNC = 0, BRGH = 1, BRG16 = 0

Fosc = 32.000 MHz Fosc = 20.000 MHz Fosc = 18.432 MHz Fosc = 11.0592 MHz

Actual

Rate

%

Error

SPBRG

value

(decimal)

Actual

Rate

%

Error

SPBRG

value

(decimal)

Actual

Rate

%

Error

SPBRG

value

(decimal)

Actual

Rate

%

Error

SPBRG

value

(decimal)

300 — — — — — — — — — — — —

1200 — — — — — — — — — — — —

2400 — — — — — — — — — — — —

9600 9615 0.16 207 9615 0.16 129 9600 0.00 119 9600 0.00 71

10417 10417 0.00 191 10417 0.00 119 10378 -0.37 110 10473 0.53 65

19.2k 19.23k 0.16 103 19.23k 0.16 64 19.20k 0.00 59 19.20k 0.00 35

57.6k 57.14k -0.79 34 56.82k -1.36 21 57.60k 0.00 19 57.60k 0.00 11

115.2k 117.64k 2.12 16 113.64k -1.36 10 115.2k 0.00 9 115.2k 0.00 5

BAUD

RATE

SYNC = 0, BRGH = 1, BRG16 = 0

Fosc = 8.000 MHz Fosc = 4.000 MHz Fosc = 3.6864 MHz Fosc = 1.000 MHz

Actual

Rate

%

Error

SPBRG

value

(decimal)

Actual

Rate

%

Error

SPBRG

value

(decimal)

Actual

Rate

%

Error

SPBRG

value

(decimal)

Actual

Rate

%

Error

SPBRG

value

(decimal)

300 — — — — — — — — — 300 0.16 207

1200 — — — 1202 0.16 207 1200 0.00 191 1202 0.16 51

2400 2404 0.16 207 2404 0.16 103 2400 0.00 95 2404 0.16 25

9600 9615 0.16 51 9615 0.16 25 9600 0.00 23 — — —

10417 10417 0.00 47 10417 0.00 23 10473 0.53 21 10417 0.00 5

19.2k 19231 0.16 25 19.23k 0.16 12 19.2k 0.00 11 — — —

57.6k 55556 -3.55 8 — — — 57.60k 0.00 3 — — —

115.2k — — — — — — 115.2k 0.00 1 — — —

PIC18F26/45/46Q10

(EUSART) Enhanced Universal Synchronous Asyn...

BAUD

RATE

SYNC = 0, BRGH = 0, BRG16 = 1

Fosc = 32.000 MHz Fosc = 20.000 MHz Fosc = 18.432 MHz Fosc = 11.0592 MHz

Actual

Rate

%

Error

SPBRG

value

(decimal)

Actual

Rate

%

Error

SPBRG

value

(decimal)

Actual

Rate

%

Error

SPBRG

value

(decimal)

Actual

Rate

%

Error

SPBRG

value

(decimal)

300 300.0 0.00 6666 300.0 -0.01 4166 300.0 0.00 3839 300.0 0.00 2303

1200 1200 -0.02 3332 1200 -0.03 1041 1200 0.00 959 1200 0.00 575

2400 2401 -0.04 832 2399 -0.03 520 2400 0.00 479 2400 0.00 287

9600 9615 0.16 207 9615 0.16 129 9600 0.00 119 9600 0.00 71

10417 10417 0.00 191 10417 0.00 119 10378 -0.37 110 10473 0.53 65

19.2k 19.23k 0.16 103 19.23k 0.16 64 19.20k 0.00 59 19.20k 0.00 35

57.6k 57.14k -0.79 34 56.818 -1.36 21 57.60k 0.00 19 57.60k 0.00 11

115.2k 117.6k 2.12 16 113.636 -1.36 10 115.2k 0.00 9 115.2k 0.00 5

BAUD

RATE

SYNC = 0, BRGH = 0, BRG16 = 1

Fosc = 8.000 MHz Fosc = 4.000 MHz Fosc = 3.6864 MHz Fosc = 1.000 MHz

Actual

Rate

%

Error

SPBRG

value

(decimal)

Actual

Rate

%

Error

SPBRG

value

(decimal)

Actual

Rate

%

Error

SPBRG

value

(decimal)

Actual

Rate

%

Error

SPBRG

value

(decimal)

300 299.9 -0.02 1666 300.1 0.04 832 300.0 0.00 767 300.5 0.16 207

1200 1199 -0.08 416 1202 0.16 207 1200 0.00 191 1202 0.16 51

2400 2404 0.16 207 2404 0.16 103 2400 0.00 95 2404 0.16 25

9600 9615 0.16 51 9615 0.16 25 9600 0.00 23 — — —

10417 10417 0.00 47 10417 0.00 23 10473 0.53 21 10417 0.00 5

19.2k 19.23k 0.16 25 19.23k 0.16 12 19.20k 0.00 11 — — —

57.6k 55556 -3.55 8 — — — 57.60k 0.00 3 — — —

115.2k — — — — — — 115.2k 0.00 1 — — —

BAUD

RATE

SYNC = 0, BRGH = 1, BRG16 = 1 or SYNC = 1, BRG16 = 1

Fosc = 32.000 MHz Fosc = 20.000 MHz Fosc = 18.432 MHz Fosc = 11.0592 MHz

Actual

Rate

%

Error

SPBRG

value

(decimal)

Actual

Rate

%

Error

SPBRG

value

(decimal)

Actual

Rate

%

Error

SPBRG

value

(decimal)

Actual

Rate

%

Error

SPBRG

value

(decimal)

300 300.0 0.00 26666 300.0 0.00 16665 300.0 0.00 15359 300.0 0.00 9215

1200 1200 0.00 6666 1200 -0.01 4166 1200 0.00 3839 1200 0.00 2303

PIC18F26/45/46Q10

(EUSART) Enhanced Universal Synchronous Asyn...

2400 2400 0.01 3332 2400 0.02 2082 2400 0.00 1919 2400 0.00 1151

9600 9604 0.04 832 9597 -0.03 520 9600 0.00 479 9600 0.00 287

10417 10417 0.00 767 10417 0.00 479 10425 0.08 441 10433 0.16 264

19.2k 19.18k -0.08 416 19.23k 0.16 259 19.20k 0.00 239 19.20k 0.00 143

57.6k 57.55k -0.08 138 57.47k -0.22 86 57.60k 0.00 79 57.60k 0.00 47

115.2k 115.9k 0.64 68 116.3k 0.94 42 115.2k 0.00 39 115.2k 0.00 23

BAUD

RATE

SYNC = 0, BRGH = 1, BRG16 = 1 or SYNC = 1, BRG16 = 1

Fosc = 8.000 MHz Fosc = 4.000 MHz Fosc = 3.6864 MHz Fosc = 1.000 MHz

Actual

Rate

%

Error

SPBRG

value

(decimal)

Actual

Rate

%

Error

SPBRG

value

(decimal)

Actual

Rate

%

Error

SPBRG

value

(decimal)

Actual

Rate

%

Error

SPBRG

value

(decimal)

300 300.0 0.00 6666 300.0 0.01 3332 300.0 0.00 3071 300.1 0.04 832

1200 1200 -0.02 1666 1200 0.04 832 1200 0.00 767 1202 0.16 207

2400 2401 0.04 832 2398 0.08 416 2400 0.00 383 2404 0.16 103

9600 9615 0.16 207 9615 0.16 103 9600 0.00 95 9615 0.16 25

10417 10417 0 191 10417 0.00 95 10473 0.53 87 10417 0.00 23

19.2k 19.23k 0.16 103 19.23k 0.16 51 19.20k 0.00 47 19.23k 0.16 12

57.6k 57.14k -0.79 34 58.82k 2.12 16 57.60k 0.00 15 — — —

115.2k 117.6k 2.12 16 111.1k -3.55 8 115.2k 0.00 7 — — —

28.2.1 Auto-Baud Detect

The EUSART module supports automatic detection and calibration of the baud rate.

In the Auto-Baud Detect (ABD) mode, the clock to the BRG is reversed. Rather than the BRG clocking

the incoming RX signal, the RX signal is timing the BRG. The Baud Rate Generator is used to time the

period of a received 55h (ASCII “U”) which is the Sync character for the LIN bus. The unique feature of

this character is that it has five rising edges including the Stop bit edge.

Setting the ABDEN bit of the BAUDxCON register starts the auto-baud calibration sequence. While the

ABD sequence takes place, the EUSART state machine is held in Idle. On the first rising edge of the

receive line, after the Start bit, the SPxBRG begins counting up using the BRG counter clock as shown in

Figure 28-7. The fifth rising edge will occur on the RXx pin at the end of the eighth bit period. At that time,

an accumulated value totaling the proper BRG period is left in the SPxBRGH, SPxBRGL register pair, the

ABDEN bit is automatically cleared and the RCxIF interrupt flag is set. The value in the RCxREG needs

to be read to clear the RCxIF interrupt. RCxREG content should be discarded. When calibrating for

modes that do not use the SPxBRGH register the user can verify that the SPxBRGL register did not

overflow by checking for 00h in the SPxBRGH register.

The BRG auto-baud clock is determined by the BRG16 and BRGH bits as shown in Table 28-3. During

ABD, both the SPxBRGH and SPxBRGL registers are used as a 16-bit counter, independent of the

BRG16 bit setting. While calibrating the baud rate period, the SPxBRGH and SPxBRGL registers are

PIC18F26/45/46Q10

(EUSART) Enhanced Universal Synchronous Asyn...

clocked at 1/8th the BRG base clock rate. The resulting byte measurement is the average bit time when

clocked at full speed.

Note:

1. If the WUE bit is set with the ABDEN bit, auto-baud detection will occur on the byte following the

Break character (see 28.2.3 Auto-Wake-up on Break).

2. It is up to the user to determine that the incoming character baud rate is within the range of the

selected BRG clock source. Some combinations of oscillator frequency and EUSART baud rates

are not possible.

3. During the auto-baud process, the auto-baud counter starts counting at one. Upon completion of

the auto-baud sequence, to achieve maximum accuracy, subtract 1 from the SPxBRGH:SPxBRGL

register pair.

Table 28-3. BRG Counter Clock Rates

BRG16 BRGH BRG Base Clock BRG ABD Clock

1 1 FOSC/4 FOSC/32

1 0 FOSC/16 FOSC/128

0 1 FOSC/16 FOSC/128

0 0 FOSC/64 FOSC/512

Note: During the ABD sequence, SPxBRGL and SPxBRGH registers are both used as a 16-bit

counter, independent of the BRG16 setting.

Figure 28-7. Automatic Baud Rate Calibration

Rev. 10-000 120A

2/13/201 7

BRG Value

RXx/DTx pin

RCxIF bit

(Interrupt Flag)

Read

RCxREG

Edge #1

BRG Clock

SPxBRGH:L

Auto cleared

XXXXh 0000h 001Ch

ABDEN

start bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7

Edge #2 Edge #3 Edge #4 Edge #5

Set by user

001Ch

XXXXh

28.2.2 Auto-Baud Overflow

During the course of automatic baud detection, the ABDOVF bit of the BAUDxCON register will be set if

the baud rate counter overflows before the fifth rising edge is detected on the RXx pin. The ABDOVF bit

indicates that the counter has exceeded the maximum count that can fit in the 16 bits of the

SPxBRGH:SPxBRGL register pair. After the ABDOVF bit has been set, the counter continues to count

until the fifth rising edge is detected on the RXx pin. Upon detecting the fifth RX edge, the hardware will

set the RCxIF interrupt flag and clear the ABDEN bit of the BAUDxCON register. The RCxIF flag can be

PIC18F26/45/46Q10

(EUSART) Enhanced Universal Synchronous Asyn...

subsequently cleared by reading the RCxREG register. The ABDOVF flag of the BAUDxCON register can

be cleared by software directly.

To terminate the auto-baud process before the RCxIF flag is set, clear the ABDEN bit then clear the

ABDOVF bit of the BAUDxCON register. The ABDOVF bit will remain set if the ABDEN bit is not cleared

first.

28.2.3 Auto-Wake-up on Break

During Sleep mode, all clocks to the EUSART are suspended. Because of this, the Baud Rate Generator

is inactive and a proper character reception cannot be performed. The Auto-Wake-up feature allows the

controller to wake-up due to activity on the RX/DT line. This feature is available only in Asynchronous

mode.

The Auto-Wake-up feature is enabled by setting the WUE bit of the BAUDxCON register. Once set, the

normal receive sequence on RX/DT is disabled, and the EUSART remains in an Idle state, monitoring for

a wake-up event independent of the CPU mode. A wake-up event consists of a high-to-low transition on

the RX/DT line. (This coincides with the start of a Sync Break or a wake-up signal character for the LIN

protocol.)

The EUSART module generates an RCxIF interrupt coincident with the wake-up event. The interrupt is

generated synchronously to the Q clocks in normal CPU operating modes as shown in Figure 28-8, and

asynchronously if the device is in Sleep mode as shown in Figure 28-9. The interrupt condition is cleared

by reading the RCxREG register.

The WUE bit is automatically cleared by the low-to-high transition on the RX line at the end of the Break.

This signals to the user that the Break event is over. At this point, the EUSART module is in Idle mode

waiting to receive the next character.

28.2.3.1 Special Considerations

Break Character

To avoid character errors or character fragments during a wake-up event, the wake-up character must be

all zeros.

When the wake-up is enabled the function works independent of the low time on the data stream. If the

WUE bit is set and a valid non-zero character is received, the low time from the Start bit to the first rising

edge will be interpreted as the wake-up event. The remaining bits in the character will be received as a

fragmented character and subsequent characters can result in framing or overrun errors.

Therefore, the initial character in the transmission must be all ‘0’s. This must be ten or more bit times, 13-

bit times recommended for LIN bus, or any number of bit times for standard RS-232 devices.

Oscillator Start-up Time

Oscillator start-up time must be considered, especially in applications using oscillators with longer start-up

intervals (i.e., LP, XT or HS/PLL mode). The Sync Break (or wake-up signal) character must be of

sufficient length, and be followed by a sufficient interval, to allow enough time for the selected oscillator to

start and provide proper initialization of the EUSART.

WUE Bit

The wake-up event causes a receive interrupt by setting the RCxIF bit. The WUE bit is cleared in

hardware by a rising edge on RX/DT. The interrupt condition is then cleared in software by reading the

RCxREG register and discarding its contents.

PIC18F26/45/46Q10

(EUSART) Enhanced Universal Synchronous Asyn...

To ensure that no actual data is lost, check the RCIDL bit to verify that a receive operation is not in

process before setting the WUE bit. If a receive operation is not occurring, the WUE bit may then be set

just prior to entering the Sleep mode.

Figure 28-8. Auto-Wake-up Bit (WUE) Timing During Normal Operation

Rev. 10-000 326A

2/13/201 7

FOSC

q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q2 q3 q4

q1 q2 q3 q4q1

WUE bit

RXx/DTx

line

RCxIF

Bit set by user

Cleared due to user read of RCxREG

Auto cleared

Note 1: The EUSART remains in idle while the WUE bit is set.

Figure 28-9. Auto-Wake-up Bit (WUE) Timings During Sleep

Rev. 10-000 327A

2/13/201 7

FOSC

q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q2 q3 q4

q1 q2 q3 q4q1

WUE bit

RXx/DTx

line

RCxIF

Bit set by user

Cleared due to user read of RCxREG

Auto cleared

Note 1: The EUSART remains in idle while the WUE bit is set.

Sleep command executed Sleep ends

28.2.4 Break Character Sequence

The EUSART module has the capability of sending the special Break character sequences that are

required by the LIN bus standard. A Break character consists of a Start bit, followed by 12 ‘0’ bits and a

Stop bit.

To send a Break character, set the SENDB and TXEN bits of the TXxSTA register. The Break character

transmission is then initiated by a write to the TXxREG. The value of data written to TXxREG will be

ignored and all ‘0’s will be transmitted.

The SENDB bit is automatically reset by hardware after the corresponding Stop bit is sent. This allows

the user to preload the transmit FIFO with the next transmit byte following the Break character (typically,

the Sync character in the LIN specification).

The TRMT bit of the TXxSTA register indicates when the transmit operation is active or idle, just as it

does during normal transmission. See Figure 28-10 for more detail.

28.2.4.1 Break and Sync Transmit Sequence

The following sequence will start a message frame header made up of a Break, followed by an auto-baud

Sync byte. This sequence is typical of a LIN bus master.

PIC18F26/45/46Q10

(EUSART) Enhanced Universal Synchronous Asyn...

1. Configure the EUSART for the desired mode.

2. Set the TXEN and SENDB bits to enable the Break sequence.

3. Load the TXxREG with a dummy character to initiate transmission (the value is ignored).

4. Write ‘55h’ to TXxREG to load the Sync character into the transmit FIFO buffer.

5. After the Break has been sent, the SENDB bit is reset by hardware and the Sync character is then

transmitted.

When the TXxREG becomes empty, as indicated by the TXxIF, the next data byte can be written to

TXxREG.

28.2.5 Receiving a Break Character

The EUSART module can receive a Break character in two ways.

The first method to detect a Break character uses the FERR bit of the RCxSTA register and the received

data as indicated by RCxREG. The Baud Rate Generator is assumed to have been initialized to the

expected baud rate.

A Break character has been received when all three of the following conditions are true:

• RCxIF bit is set

• FERR bit is set

• RCxREG = 00h

The second method uses the Auto-Wake-up feature described in 28.2.3 Auto-Wake-up on Break. By

enabling this feature, the EUSART will sample the next two transitions on RX/DT, cause an RCxIF

interrupt, and receive the next data byte followed by another interrupt.

Note that following a Break character, the user will typically want to enable the Auto-Baud Detect feature.

For both methods, the user can set the ABDEN bit of the BAUDxCON register before placing the

EUSART in Sleep mode.

Figure 28-10. Send Break Character Sequence

Rev. 10-000 118A

2/13/201 7

Write to TXxREG

BRG Output

(Shift Clock)

TXx/CKx pin

TXxIF bit

(Transmit Buffer

Reg Empty Flag)

TRMT bit

(Transmit Shift

Reg Empty Flag)

Start bit bit 0 bit 1 bit 11 Stop bit

Break

Dummy

Write

SENDB

(send break

control bit)

SENDB sampled here Auto cleared

28.3 EUSART Synchronous Mode

Synchronous serial communications are typically used in systems with a single master and one or more

slaves. The master device contains the necessary circuitry for baud rate generation and supplies the

PIC18F26/45/46Q10

(EUSART) Enhanced Universal Synchronous Asyn...

clock for all devices in the system. Slave devices can take advantage of the master clock by eliminating

the internal clock generation circuitry.

There are two signal lines in Synchronous mode: a bidirectional data line and a clock line. Slaves use the

external clock supplied by the master to shift the serial data into and out of their respective receive and

transmit shift registers. Since the data line is bidirectional, synchronous operation is half-duplex only. Half-

duplex refers to the fact that master and slave devices can receive and transmit data but not both

simultaneously. The EUSART can operate as either a master or slave device.

Start and Stop bits are not used in synchronous transmissions.

28.3.1 Synchronous Master Mode

The following bits are used to configure the EUSART for synchronous master operation:

• SYNC = 1 (configures the EUSART for synchronous operation)

• CSRC = 1 (configures the EUSART as the master)

• SREN = 0 (for transmit); SREN = 1 (recommended setting to receive 1 byte)

• CREN = 0 (for transmit); CREN = 1 (to receive continuously)

• SPEN = 1 (enables the EUSART)

Important: Clearing the SREN and CREN bits of the RCxSTA register ensures that the device

is in the Transmit mode, otherwise the device will be configured to receive.

28.3.1.1 Master Clock

Synchronous data transfers use a separate clock line, which is synchronous with the data. A device

configured as a master transmits the clock on the TX/CK line. The TXx/CKx pin output driver is

automatically enabled when the EUSART is configured for synchronous transmit or receive operation.

Serial data bits change on the leading edge to ensure they are valid at the trailing edge of each clock.

One clock cycle is generated for each data bit. Only as many clock cycles are generated as there are

data bits.

28.3.1.2 Clock Polarity

A clock polarity option is provided for Microwire compatibility. Clock polarity is selected with the SCKP bit

of the BAUDxCON register. Setting the SCKP bit sets the clock Idle state as high. When the SCKP bit is

set, the data changes on the falling edge of each clock. Clearing the SCKP bit sets the Idle state as low.

When the SCKP bit is cleared, the data changes on the rising edge of each clock.

28.3.1.3 Synchronous Master Transmission

Data is transferred out of the device on the RXx/DTx pin. The RXx/DTx and TXx/CKx pin output drivers

are automatically enabled when the EUSART is configured for synchronous master transmit operation.

A transmission is initiated by writing a character to the TXxREG register. If the TSR still contains all or

part of a previous character the new character data is held in the TXxREG until the last bit of the previous

character has been transmitted. If this is the first character, or the previous character has been

completely flushed from the TSR, the data in the TXxREG is immediately transferred to the TSR. The

transmission of the character commences immediately following the transfer of the data to the TSR from

the TXxREG.

Each data bit changes on the leading edge of the master clock and remains valid until the subsequent

leading clock edge.

PIC18F26/45/46Q10

(EUSART) Enhanced Universal Synchronous Asyn...

Note: The TSR register is not mapped in data memory, so it is not available to the user.

28.3.1.4 Synchronous Master Transmission Setup

1. Initialize the SPxBRGH, SPxBRGL register pair and the BRG16 bit to achieve the desired baud rate

(see 28.2 EUSART Baud Rate Generator (BRG)).

2. Select the transmit output pin by writing the appropriate values to the RxyPPS register and

RXxPPS register. Both selections should enable the same pin.

3. Select the clock output pin by writing the appropriate values to the RxyPPS register and CKxPPS

register. Both selections should enable the same pin.

4. Enable the synchronous master serial port by setting bits SYNC, SPEN and CSRC.

5. Disable Receive mode by clearing bits SREN and CREN.

6. Enable Transmit mode by setting the TXEN bit.

7. If 9-bit transmission is desired, set the TX9 bit.

8. If interrupts are desired, set the TXxIE bit of the PIEx register and the GIE and PEIE bits of the

INTCON register.

9. If 9-bit transmission is selected, the ninth bit should be loaded in the TX9D bit.

10. Start transmission by loading data to the TXxREG register.

Figure 28-11. Synchronous Transmission

Rev. 10-000 115A

2/7/201 7

Write to TXxREG

BRG Output

(Shift Clock)

TXx/CKx pin

TXxIF bit

(Transmit Buffer

Reg Empty Flag)

TRMT bit

(Transmit Shift

Reg Empty Flag)

Start bit bit 0 bit 1 bit 7/8 Stop bit

1 TCY

Word 1

28.3.1.5 Synchronous Master Reception

Data is received at the RXx/DTx pin. The RXx/DTx pin output driver is automatically disabled when the

EUSART is configured for synchronous master receive operation.

In Synchronous mode, reception is enabled by setting either the Single Receive Enable bit (SREN of the

RCxSTA register) or the Continuous Receive Enable bit (CREN of the RCxSTA register).

When SREN is set and CREN is clear, only as many clock cycles are generated as there are data bits in

a single character. The SREN bit is automatically cleared at the completion of one character. When

CREN is set, clocks are continuously generated until CREN is cleared. If CREN is cleared in the middle of

a character the CK clock stops immediately and the partial character is discarded. If SREN and CREN

are both set, then SREN is cleared at the completion of the first character and CREN takes precedence.

To initiate reception, set either SREN or CREN. Data is sampled at the RXx/DTx pin on the trailing edge

of the TX/CK clock pin and is shifted into the Receive Shift Register (RSR). When a complete character is

received into the RSR, the RCxIF bit is set and the character is automatically transferred to the two

character receive FIFO. The Least Significant eight bits of the top character in the receive FIFO are

available in RCxREG. The RCxIF bit remains set as long as there are unread characters in the receive

FIFO.

PIC18F26/45/46Q10

(EUSART) Enhanced Universal Synchronous Asyn...

Note: If the RX/DT function is on an analog pin, the corresponding ANSEL bit must be cleared for the

receiver to function.

28.3.1.6 Receive Overrun Error

The receive FIFO buffer can hold two characters. An overrun error will be generated if a third character, in

its entirety, is received before RCxREG is read to access the FIFO. When this happens the OERR bit of

the RCxSTA register is set. Previous data in the FIFO will not be overwritten. The two characters in the

FIFO buffer can be read, however, no additional characters will be received until the error is cleared. The

OERR bit can only be cleared by clearing the overrun condition. If the overrun error occurred when the

SREN bit is set and CREN is clear then the error is cleared by reading RCxREG. If the overrun occurred

when the CREN bit is set then the error condition is cleared by either clearing the CREN bit of the

RCxSTA register or by clearing the SPEN bit which resets the EUSART.

28.3.1.7 Receiving 9-Bit Characters

The EUSART supports 9-bit character reception. When the RX9 bit of the RCxSTA register is set the

EUSART will shift nine bits into the RSR for each character received. The RX9D bit of the RCxSTA

register is the ninth, and Most Significant, data bit of the top unread character in the receive FIFO. When

reading 9-bit data from the receive FIFO buffer, the RX9D data bit must be read before reading the eight

Least Significant bits from the RCxREG.

28.3.1.8 Synchronous Master Reception Setup

1. Initialize the SPxBRGH:SPxBRGL register pair and set or clear the BRG16 bit, as required, to

achieve the desired baud rate.

2. Select the receive input pin by writing the appropriate values to the RxyPPS register and RXxPPS

register. Both selections should enable the same pin.

3. Select the clock output pin by writing the appropriate values to the RxyPPS register and CKxPPS

register. Both selections should enable the same pin.

4. Clear the ANSEL bit for the RXx pin (if applicable).

5. Enable the synchronous master serial port by setting bits SYNC, SPEN and CSRC.

6. Ensure bits CREN and SREN are clear.

7. If interrupts are desired, set the RCxIE bit of the PIEx register and the GIE and PEIE bits of the

INTCON register.

8. If 9-bit reception is desired, set bit RX9.

9. Start reception by setting the SREN bit or for continuous reception, set the CREN bit.

10. Interrupt flag bit RCxIF will be set when reception of a character is complete. An interrupt will be

generated if the enable bit RCxIE was set.

11. Read the RCxSTA register to get the ninth bit (if enabled) and determine if any error occurred

during reception.

12. Read the 8-bit received data by reading the RCxREG register.

13. If an overrun error occurs, clear the error by either clearing the CREN bit of the RCxSTA register or

by clearing the SPEN bit which resets the EUSART.

PIC18F26/45/46Q10

(EUSART) Enhanced Universal Synchronous Asyn...

Figure 28-12. Synchronous Reception (Master Mode, SREN)

Rev. 10-000 121A

2/13/201 7

RXx/DTx pin bit 0

TXx/CKx pin

SCKP = 0

TXx/CKx pin

SCKP = 1

bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7

Write to SREN

SREN bit

CREN bit ‘0’ ‘0’

RCxIF

(Interrupt)

Read

RCxREG

28.3.2 Synchronous Slave Mode

The following bits are used to configure the EUSART for synchronous slave operation:

• SYNC = 1 (configures the EUSART for synchronous operation.)

• CSRC = 0 (configures the EUSART as a slave)

• SREN = 0 (for transmit); SREN = 1 (for single byte receive)

• CREN = 0 (for transmit); CREN = 1 (recommended setting for continuous receive)

• SPEN = 1 (enables the EUSART)

Important: Clearing the SREN and CREN bits of the RCxSTA register ensures that the device

is in the Transmit mode, otherwise the device will be configured to receive.

28.3.2.1 Slave Clock

Synchronous data transfers use a separate clock line, which is synchronous with the data. A device

configured as a slave receives the clock on the TX/CK line. The TXx/CKx pin output driver is

automatically disabled when the device is configured for synchronous slave transmit or receive operation.

Serial data bits change on the leading edge to ensure they are valid at the trailing edge of each clock.

One data bit is transferred for each clock cycle. Only as many clock cycles should be received as there

are data bits.

Important: If the device is configured as a slave and the TX/CK function is on an analog pin,

the corresponding ANSEL bit must be cleared.

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28.3.2.2 EUSART Synchronous Slave Transmit

The operation of the Synchronous Master and Slave modes are identical (see 28.3.1.3 Synchronous

Master Transmission), except in the case of the Sleep mode.

If two words are written to the TXxREG and then the SLEEP instruction is executed, the following will

occur:

1. The first character will immediately transfer to the TSR register and transmit.

2. The second word will remain in the TXxREG register.

3. The TXxIF bit will not be set.

4. After the first character has been shifted out of TSR, the TXxREG register will transfer the second

character to the TSR and the TXxIF bit will now be set.

5. If the PEIE and TXxIE bits are set, the interrupt will wake the device from Sleep and execute the

next instruction. If the GIE bit is also set, the program will call the Interrupt Service Routine.

28.3.2.3 Synchronous Slave Transmission Setup

1. Set the SYNC and SPEN bits and clear the CSRC bit.

2. Select the transmit output pin by writing the appropriate values to the RxyPPS register and

RXxPPS register. Both selections should enable the same pin.

3. Select the clock input pin by writing the appropriate value to the CKxPPS register.

4. Clear the ANSEL bit for the CKx pin (if applicable).

5. Clear the CREN and SREN bits.

6. If interrupts are desired, set the TXxIE bit of the PIEx register and the GIE and PEIE bits of the

INTCON register.

7. If 9-bit transmission is desired, set the TX9 bit.

8. Enable transmission by setting the TXEN bit.

9. If 9-bit transmission is selected, insert the Most Significant bit into the TX9D bit.

10. Prepare for transmission by writing the Least Significant eight bits to the TXxREG register. The

word will be transmitted in response to the Master clocks at the CKx pin.

28.3.2.4 EUSART Synchronous Slave Reception

The operation of the Synchronous Master and Slave modes is identical (see 28.3.1.5 Synchronous

Master Reception), with the following exceptions:

• Sleep

• CREN bit is always set, therefore the receiver is never idle

• SREN bit, which is a “don’t care” in Slave mode

A character may be received while in Sleep mode by setting the CREN bit prior to entering Sleep. Once

the word is received, the RSR register will transfer the data to the RCxREG register. If the RCxIE enable

bit is set, the interrupt generated will wake the device from Sleep and execute the next instruction. If the

GIE bit is also set, the program will branch to the interrupt vector.

28.3.2.5 Synchronous Slave Reception Setup:

1. Set the SYNC and SPEN bits and clear the CSRC bit.

2. Select the receive input pin by writing the appropriate value to the RXxPPS register.

3. Select the clock input pin by writing the appropriate values to the CKxPPS register.

4. Clear the ANSEL bit for both the TXx/CKx and RXx/DTx pins (if applicable).

5. If interrupts are desired, set the RCxIE bit of the PIEx register and the GIE and PEIE bits of the

INTCON register.

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6. If 9-bit reception is desired, set the RX9 bit.

7. Set the CREN bit to enable reception.

8. The RCxIF bit will be set when reception is complete. An interrupt will be generated if the RCxIE bit

was set.

9. If 9-bit mode is enabled, retrieve the Most Significant bit from the RX9D bit of the RCxSTA register.

10. Retrieve the eight Least Significant bits from the receive FIFO by reading the RCxREG register.

11. If an overrun error occurs, clear the error by either clearing the CREN bit of the RCxSTA register or

by clearing the SPEN bit which resets the EUSART.

28.4 EUSART Operation During Sleep

The EUSART will remain active during Sleep only in the Synchronous Slave mode. All other modes

require the system clock and therefore cannot generate the necessary signals to run the Transmit or

Receive Shift registers during Sleep.

Synchronous Slave mode uses an externally generated clock to run the Transmit and Receive Shift

registers.

28.4.1 Synchronous Receive During Sleep

To receive during Sleep, all the following conditions must be met before entering Sleep mode:

• RCxSTA and TXxSTA Control registers must be configured for Synchronous Slave Reception (see

28.3.2.5 Synchronous Slave Reception Setup:).

• If interrupts are desired, set the RCxIE bit of the PIEx register and the GIE and PEIE bits of the

INTCON register.

• The RCxIF interrupt flag must be cleared by reading RCxREG to unload any pending characters in

the receive buffer.

Upon entering Sleep mode, the device will be ready to accept data and clocks on the RXx/DTx and

TXx/CKx pins, respectively. When the data word has been completely clocked in by the external device,

the RCxIF interrupt flag bit of the PIRx register will be set. Thereby, waking the processor from Sleep.

Upon waking from Sleep, the instruction following the SLEEP instruction will be executed. If the Global

Interrupt Enable (GIE) bit of the INTCON register is also set, then the Interrupt Service Routine at

address 004h will be called.

28.4.2 Synchronous Transmit During Sleep

To transmit during Sleep, all the following conditions must be met before entering Sleep mode:

• The RCxSTA and TXxSTA Control registers must be configured for synchronous slave transmission

(see 28.3.2.3 Synchronous Slave Transmission Setup).

• The TXxIF interrupt flag must be cleared by writing the output data to the TXxREG, thereby filling the

TSR and transmit buffer.

• Interrupt enable bits TXxIE of the PIEx register and PEIE of the INTCON register must set.

• If interrupts are desired, set the GIEx bit of the INTCON register.

Upon entering Sleep mode, the device will be ready to accept clocks on the TXx/CKx pin and transmit

data on the RXx/DTx pin. When the data word in the TSR has been completely clocked out by the

external device, the pending byte in the TXxREG will transfer to the TSR and the TXxIF flag will be set.

Thereby, waking the processor from Sleep. At this point, the TXxREG is available to accept another

character for transmission. Writing TXxREG will clear the TXxIF flag.

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Upon waking from Sleep, the instruction following the SLEEP instruction will be executed. If the Global

Interrupt Enable (GIE) bit is also set then the Interrupt Service Routine at address 0004h will be called.

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28.5 Register Summary - EUSART

Address Name Bit Pos.

0x0E94 RC2REG 7:0 RCREG[7:0]

0x0E95 TX2REG 7:0 TXREG[7:0]

0x0E96 SP2BRG

7:0 SPBRGL[7:0]

15:8 SPBRGH[7:0]

0x0E98 RC2STA 7:0 SPEN RX9 SREN CREN ADDEN FERR OERR RX9D

0x0E99 TX2STA 7:0 CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D

0x0E9A BAUD2CON 7:0 ABDOVF RCIDL SCKP BRG16 WUE ABDEN

0x0E9B

...

0x0F97

Reserved

0x0F98 RC1REG 7:0 RCREG[7:0]

0x0F99 TX1REG 7:0 TXREG[7:0]

0x0F9A SP1BRG

7:0 SPBRGL[7:0]

15:8 SPBRGH[7:0]

0x0F9C RC1STA 7:0 SPEN RX9 SREN CREN ADDEN FERR OERR RX9D

0x0F9D TX1STA 7:0 CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D

0x0F9E BAUD1CON 7:0 ABDOVF RCIDL SCKP BRG16 WUE ABDEN

28.6 Register Definitions: EUSART Control

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28.6.1 RCxSTA

Name: RCxSTA

Address: 0xF9C,0xE98

Receive Status and Control Register

Bit 7 6 5 4 3 2 1 0

SPEN RX9 SREN CREN ADDEN FERR OERR RX9D

Access R/W R/W R/W R/W R/W RO R/HC R/HC

Reset 0 0 0 0 0 0 0 0

Bit 7 – SPEN Serial Port Enable bit

Value Description

1Serial port enabled

0Serial port disabled (held in Reset)

Bit 6 – RX9 9-Bit Receive Enable bit

Value Description

1Selects 9-bit reception

0Selects 8-bit reception

Bit 5 – SREN Single Receive Enable bit

Controls reception. This bit is cleared by hardware when reception is complete

Value Condition Description

1SYNC = 1 AND CSRC = 1Start single receive

0SYNC = 1 AND CSRC = 1Single receive is complete

XSYNC = 0 OR CSRC = 0Don't care

Bit 4 – CREN Continuous Receive Enable bit

Value Condition Description

1SYNC = 1Enables continuous receive until enable bit CREN is cleared (CREN overrides

SREN)

0SYNC = 1Disables continuous receive

1SYNC = 0Enables receiver

0SYNC = 0Disables receiver

Bit 3 – ADDEN Address Detect Enable bit

Value Condition Description

1SYNC = 0 AND RX9 = 1The receive buffer is loaded and the interrupt occurs only when the

ninth received bit is set

0SYNC = 0 AND RX9 = 1All bytes are received and interrupt always occurs. Ninth bit can be

used as parity bit

XRX9 = 0 OR SYNC = 1Don't care

Bit 2 – FERR Framing Error bit

Value Description

1Unread byte in 28.6.5 RCxREG has a framing error

0Unread byte in 28.6.5 RCxREG does not have a framing error

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Bit 1 – OERR Overrun Error bit

Value Description

1Overrun error (can be cleared by clearing either SPEN or CREN bit)

0No overrun error

Bit 0 – RX9D Ninth bit of Received Data

This can be address/data bit or a parity bit which is determined by user firmware.

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28.6.2 TXxSTA

Name: TXxSTA

Address: 0xF9D,0xE99

Transmit Status and Control Register

Bit 7 6 5 4 3 2 1 0

CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D

Access R/W R/W R/W R/W R/W R/W RO R/W

Reset 0 0 0 0 0 0 1 0

Bit 7 – CSRC Clock Source Select bit

Value Condition Description

1SYNC= 1Master mode (clock generated internally from BRG)

0SYNC= 1Slave mode (clock from external source)

XSYNC= 0Don't care

Bit 6 – TX9 9-bit Transmit Enable bit

Value Description

1Selects 9-bit transmission

0Selects 8-bit transmission

Bit 5 – TXEN Transmit Enable bit

Enables transmitter(1)

Value Description

1Transmit enabled

0Transmit disabled

Bit 4 – SYNC EUSART Mode Select bit

Value Description

1Synchronous mode

0Asynchronous mode

Bit 3 – SENDB Send Break Character bit

Value Condition Description

1SYNC= 0Send Sync Break on next transmission (cleared by hardware upon completion)

0SYNC= 0Sync Break transmission disabled or completed

XSYNC= 1Don't care

Bit 2 – BRGH High Baud Rate Select bit

Value Condition Description

1SYNC= 0High speed, if BRG16 = 1, baud rate is baudclk/4; else baudclk/16

0SYNC= 0Low speed

XSYNC= 1Don't care

Bit 1 – TRMT Transmit Shift Register (TSR) Status bit

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Value Description

1TSR is empty

0TSR is not empty

Bit 0 – TX9D Ninth bit of Transmit Data

Can be address/data bit or a parity bit.

Note:

1. SREN and CREN bits override TXEN in Sync mode.

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28.6.3 BAUDxCON

Name: BAUDxCON

Address: 0xF9E,0xE9A

Baud Rate Control Register

Bit 7 6 5 4 3 2 1 0

ABDOVF RCIDL SCKP BRG16 WUE ABDEN

Access RO RO RW RW RW RW

Reset 0 0 0 0 0 0

Bit 7 – ABDOVF Auto-Baud Detect Overflow bit

Value Condition Description

1SYNC= 0Auto-baud timer overflowed

0SYNC= 0Auto-baud timer did not overflow

XSYNC= 1Don't care

Bit 6 – RCIDL Receive Idle Flag bit

Value Condition Description

1SYNC= 0Receiver is Idle

0SYNC= 0Start bit has been received and the receiver is receiving

XSYNC= 1Don't care

Bit 4 – SCKP Synchronous Clock Polarity Select bit

Value Condition Description

1SYNC= 0Idle state for transmit (TX) is a low level (transmit data inverted)

0SYNC= 0Idle state for transmit (TX) is a high level (transmit data is non-inverted)

1SYNC= 1Data is clocked on rising edge of the clock

0SYNC= 1Data is clocked on falling edge of the clock

Bit 3 – BRG16 16-bit Baud Rate Generator Select bit

Value Description

116-bit Baud Rate Generator is used

08-bit Baud Rate Generator is used

Bit 1 – WUE Wake-up Enable bit

Value Condition Description

1SYNC= 0Receiver is waiting for a falling edge. Upon falling edge no character will be

received and flag RCxIF will be set. WUE will automatically clear after RCxIF is

set.

0SYNC= 0Receiver is operating normally

XSYNC= 1Don't care

Bit 0 – ABDEN Auto-Baud Detect Enable bit

Value Condition Description

1SYNC= 0Auto-Baud Detect mode is enabled (clears when auto-baud is complete)

0SYNC= 0Auto-Baud Detect is complete or mode is disabled

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Value Condition Description

XSYNC= 1Don't care

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28.6.4 SPxBRG

Name: SPxBRG

Address: 0xF9A,0xE96

Baud Rate Determination Register

Bit 15 14 13 12 11 10 9 8

SPBRGH[7:0]

Access R/W R/W R/W R/W R/W R/W R/W R/W

Reset 0 0 0 0 0 0 0 0

Bit 7 6 5 4 3 2 1 0

SPBRGL[7:0]

Access R/W R/W R/W R/W R/W R/W R/W R/W

Reset 0 0 0 0 0 0 0 0

Bits 15:8 – SPBRGH[7:0] Baud Rate High Byte Register

Bits 7:0 – SPBRGL[7:0] Baud Rate Low Byte Register

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28.6.5 RCxREG

Name: RCxREG

Address: 0xF98,0xE94

Receive Data Register

Bit 7 6 5 4 3 2 1 0

RCREG[7:0]

Access RO RO RO RO RO RO RO RO

Reset 0 0 0 0 0 0 0 0

Bits 7:0 – RCREG[7:0] Receive data

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28.6.6 TXxREG

Name: TXxREG

Address: 0xF99,0xE95

Transmit Data Register

Bit 7 6 5 4 3 2 1 0

TXREG[7:0]

Access R/W R/W R/W R/W R/W R/W R/W R/W

Reset 0 0 0 0 0 0 0 0

Bits 7:0 – TXREG[7:0] Transmit Data

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29. (FVR) Fixed Voltage Reference

The Fixed Voltage Reference (FVR) is a stable voltage reference, independent of VDD, with the following

selectable output levels:

• 1.024V

• 2.048V

• 4.096V

The output of the FVR can be configured to supply a reference voltage to the following:

• ADC input channel

• ADC positive reference

• Comparator input

• Digital-to-Analog Converter (DAC)

The FVR can be enabled by setting the FVREN bit of the FVRCON register.

Important: Fixed Voltage Reference output cannot exceed VDD.

29.1 Independent Gain Amplifiers

The output of the FVR, which is connected to the ADC, Comparators, and DAC, is routed through two

independent programmable gain amplifiers. Each amplifier can be programmed for a gain of 1x, 2x or 4x,

to produce the three possible voltage levels.

The ADFVR<1:0> bits of the FVRCON register are used to enable and configure the gain amplifier

settings for the reference supplied to the ADC module. Reference the ADC chapter for additional

information.

The CDAFVR<1:0> bits of the FVRCON register are used to enable and configure the gain amplifier

settings for the reference supplied to the DAC and comparator module.

Related Links

32. (ADC2) Analog-to-Digital Converter with Computation Module

33. (CMP) Comparator Module

31. (DAC) 5-Bit Digital-to-Analog Converter Module

29.2 FVR Stabilization Period

When the Fixed Voltage Reference module is enabled, it requires time for the reference and amplifier

circuits to stabilize. Once the circuits stabilize and are ready for use, the FVRRDY bit of the FVRCON

register will be set.

PIC18F26/45/46Q10

(FVR) Fixed Voltage Reference

Figure 29-1. Voltage Reference Block Diagram

Filename: 10-000053C.vsd

Title: VOLTAGE REFERENCE BLOCK DIAGRAM (ADC, Comp and DAC)

Last Edit: 12/9/2013

First Used: PIC16F1613 (LECQ)

Note: Any peripheral requiring the Fixed Reference (See Table 13-1)

1x

2x

4x

1x

2x

4x

ADFVR<1:0>

CDAFVR<1:0>

FVR_buffer1

(To ADC Module)

FVR_buffer2

(To Comparators

and DAC)

+

_

FVREN FVRRDY

Note 1

2

Rev. 10-000 053C

12/9/201 3

Note:

1. Any peripheral requiring the FVR

PIC18F26/45/46Q10

(FVR) Fixed Voltage Reference

29.3 Register Summary - FVR

Address Name Bit Pos.

0x0F2C FVRCON 7:0 FVREN FVRRDY TSEN TSRNG CDAFVR[1:0] ADFVR[1:0]

29.4 Register Definitions: FVR Control

PIC18F26/45/46Q10

(FVR) Fixed Voltage Reference

29.4.1 FVRCON

Name: FVRCON

Address: 0xF2C

Fixed Voltage Reference Control Register

Bit 7 6 5 4 3 2 1 0

FVREN FVRRDY TSEN TSRNG CDAFVR[1:0] ADFVR[1:0]

Access R/W R R/W R/W R/W R/W R/W R/W

Reset 0 q 0 0 0 0 0 0

Bit 7 – FVREN Fixed Voltage Reference Enable bit

Value Description

1Fixed Voltage Reference is enabled

0Fixed Voltage Reference is disabled

Bit 6 – FVRRDY Fixed Voltage Reference Ready Flag bit

Value Description

1Fixed Voltage Reference output is ready for use

0Fixed Voltage Reference output is not ready or not enabled

Bit 5 – TSEN

Temperature Indicator Enable bit(2)

Value Description

1Temperature Indicator is enabled

0Temperature Indicator is disabled

Bit 4 – TSRNG

Temperature Indicator Range Selection bit(2)

Value Description

1VOUT = VDD - 4Vt (High Range)

0VOUT = VDD - 2Vt (Low Range)

Bits 3:2 – CDAFVR[1:0] Comparator FVR Buffer Gain Selection bits

Value Description

11 Comparator FVR Buffer Gain is 4x, (4.096V)(1)

10 Comparator FVR Buffer Gain is 2x, (2.048V)(1)

01 Comparator FVR Buffer Gain is 1x, (1.024V)

00 Comparator FVR Buffer is off

Bits 1:0 – ADFVR[1:0] ADC FVR Buffer Gain Selection bit

Value Description

11 ADC FVR Buffer Gain is 4x, (4.096V)(1)

10 ADC FVR Buffer Gain is 2x, (2.048V)(1)

01 ADC FVR Buffer Gain is 1x, (1.024V)

00 ADC FVR Buffer is off

PIC18F26/45/46Q10

(FVR) Fixed Voltage Reference

Note:

1. Fixed Voltage Reference output cannot exceed VDD.

2. See Temperature Indicator Module section for additional information.

Related Links

30. Temperature Indicator Module

PIC18F26/45/46Q10

(FVR) Fixed Voltage Reference

30. Temperature Indicator Module

This family of devices is equipped with a temperature circuit designed to measure the operating

temperature of the silicon die. The circuit’s range of operating temperature falls between -40°C and

+85°C. The output is a voltage that is proportional to the device temperature. The output of the

temperature indicator is internally connected to the device ADC.

The circuit may be used as a temperature threshold detector or a more accurate temperature indicator,

depending on the level of calibration performed. A one-point calibration allows the circuit to indicate a

temperature closely surrounding that point. A two-point calibration allows the circuit to sense the entire

range of temperature more accurately. Refer to Application Note AN1333, “Use and Calibration of the

Internal Temperature Indicator” (DS00001333) for more details regarding the calibration process.

30.1 Circuit Operation

Figure 30-2 shows a simplified block diagram of the temperature circuit. The proportional voltage output

is achieved by measuring the forward voltage drop across multiple silicon junctions.

The following equation describes the output characteristics of the temperature indicator.

Figure 30-1. VOUT Ranges

ℎ: = 4 : = 2

The temperature sense circuit is integrated with the Fixed Voltage Reference (FVR) module. See “Fixed

Voltage Reference (FVR)” chapter for more information.

The circuit is enabled by setting the TSEN bit of the FVRCON register. When disabled, the circuit draws

no current.

The circuit operates in either high or low range. The high range, selected by setting the TSRNG bit of the

FVRCON register, provides a wider output voltage. This provides more resolution over the temperature

range, but may be less consistent from part to part. This range requires a higher bias voltage to operate

and thus, a higher VDD is needed.

The low range is selected by clearing the TSRNG bit of the FVRCON register. The low range generates a

lower voltage drop and thus, a lower bias voltage is needed to operate the circuit. The low range is

provided for low voltage operation.

PIC18F26/45/46Q10

Temperature Indicator Module

Figure 30-2. Temperature Circuit Diagram

VOUT

Temp. Indicator To ADC

TSRNG

TSEN

Rev. 10-000069A

7/31/2013

VDD

Related Links

29. (FVR) Fixed Voltage Reference

30.2 Minimum Operating VDD

When the temperature circuit is operated in low range, the device may be operated at any operating

voltage that is within specifications.

When the temperature circuit is operated in high range, the device operating voltage, VDD, must be high

enough to ensure that the temperature circuit is correctly biased.

Table 30-1 shows the recommended minimum VDD vs. range setting.

Table 30-1. Recommended VDD vs. Range

Min. VDD, TSRNG = 1Min. VDD, TSRNG = 0

3.6V 1.8V

30.3 Temperature Output

The output of the circuit is measured using the internal Analog-to-Digital Converter. A channel is reserved

for the temperature circuit output. Refer to “Analog-to-Digital Converter with Computation (ADC2) Module”

chapter for detailed information.

Related Links

32. (ADC2) Analog-to-Digital Converter with Computation Module

PIC18F26/45/46Q10

Temperature Indicator Module

30.4 ADC Acquisition Time

To ensure accurate temperature measurements, the user must wait at least 200 μs after the ADC input

multiplexer is connected to the temperature indicator output before the conversion is performed. In

addition, the user must wait 200 μs between consecutive conversions of the temperature indicator output.

PIC18F26/45/46Q10

Temperature Indicator Module

31. (DAC) 5-Bit Digital-to-Analog Converter Module

The Digital-to-Analog Converter supplies a variable voltage reference, ratiometric with the input source,

with 32 selectable output levels.

The positive input source (VSOURCE+) of the DAC can be connected to:

• FVR Buffer

• External VREF+ pin

• VDD supply voltage

The negative input source (VSOURCE-) of the DAC can be connected to:

• External VREF- pin

• VSS

The output of the DAC (DACx_output) can be selected as a reference voltage to the following:

• Comparator positive input

• ADC input channel

• DACxOUT1 pin

• DACxOUT2 pin

The Digital-to-Analog Converter (DAC) can be enabled by setting the EN bit.

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Figure 31-1. Digital-to-Analog Converter Block Diagram

Filename: 10-000026F.vsd

Title: 5bit_DAC Block Diagram

Last Edit: 8/7/2015

First Used: PIC16(L)F1508/9 (LECD)

Note 1: The unbuffered DACx_output is provided on the DACxOUT pin(s).

VREF+

AVDD

DACPSS

VSOURCE+

VSOURCE-

AVSS

R

32

Steps

R

32-to-1 MUX

To Peripherals

DACxOUT1(1)

DACOE1

DACx_output

DACEN

DACR<4:0>

5

DACxOUT2(1)

DACOE2

Rev. 10-000026F

8/7/2015

00

11

10

01

FVR Buffer

Reserved

1

0

VREF-

DACNSS

Note:

1. The unbuffered DACx_output is provided on the DACxOUT pin(s).

31.1 Output Voltage Selection

The DAC has 32 voltage level ranges. The 32 levels are set with the DAC1R bits.

The DAC output voltage can be determined by using the following equation.

Figure 31-2. DAC Output Voltage

When EN = 1:

_ = +    4: 0

25+ 

Note: See the DAC1CON0 register for the available VSOURCE+ and VSOURCE- selections.

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31.2 Ratiometric Output Level

The DAC output value is derived using a resistor ladder with each end of the ladder tied to a positive and

negative voltage reference input source. If the voltage of either input source fluctuates, a similar

fluctuation will result in the DAC output value.

The value of the individual resistors within the ladder can be found in the “5-Bit DAC Specifications” table

from the “Electrical Specifications” chapter.

Related Links

39.4.10 5-Bit DAC Specifications

31.3 DAC Voltage Reference Output

The unbuffered DAC voltage can be output to the DACxOUTn pin(s) by setting the respective OEn bit(s).

Selecting the DAC reference voltage for output on either DACxOUTn pin automatically overrides the

digital output buffer, the weak pull-up and digital input threshold detector functions of that pin.

Reading the DACxOUTn pin when it has been configured for DAC reference voltage output will always

return a ‘0’.

Important: The unbuffered DAC output (DACxOUTn) is not intended to drive an external load.

31.4 Operation During Sleep

When the device wakes up from Sleep through an interrupt or a Windowed Watchdog Timer Time-out, the

contents of the DACxCON0 register are not affected. To minimize current consumption in Sleep mode,

the voltage reference should be disabled.

31.5 Effects of a Reset

A device Reset affects the following:

• DACx is disabled.

• DACx output voltage is removed from the DACxOUTn pin(s).

• The DAC1R range select bits are cleared.

PIC18F26/45/46Q10

(DAC) 5-Bit Digital-to-Analog Converter Modu...

31.6 Register Summary - DAC Control

Address Name Bit Pos.

0x0F2E DAC1CON0 7:0 EN OE1 OE2 PSS[1:0] NSS

0x0F2F DAC1CON1 7:0 DAC1R[4:0]

31.7 Register Definitions: DAC Control

Long bit name prefixes for the DAC are shown in the table below. Refer to the "Long Bit Names Section"

for more information.

Table 31-1. DAC Long Bit Name Prefixes

Peripheral Bit Name Prefix

DAC DAC

Related Links

1.4.2.2 Long Bit Names

PIC18F26/45/46Q10

(DAC) 5-Bit Digital-to-Analog Converter Modu...

31.7.1 DAC1CON0

Name: DAC1CON0

Address: 0xF2E

DAC Control Register

Bit 7 6 5 4 3 2 1 0

EN OE1 OE2 PSS[1:0] NSS

Access R/W R/W R/W R/W R/W R/W

Reset 0 0 0 0 0 0

Bit 7 – EN DAC Enable bit

Value Description

1DAC is enabled

0DAC is disabled

Bit 5 – OE1 DAC Voltage Output Enable bit

Value Description

1DAC voltage level is output on the DAC1OUT1 pin

0DAC voltage level is disconnected from the DAC1OUT1 pin

Bit 4 – OE2 DAC Voltage Output Enable bit

Value Description

1DAC voltage level is output on the DAC1OUT2 pin

0DAC voltage level is disconnected from the DAC1OUT2 pin

Bits 3:2 – PSS[1:0] DAC Positive Source Select bit

Value Description

11 Reserved

10 FVR buffer

01 VREF+

00 AVDD

Bit 0 – NSS DAC Negative Source Select bit

Value Description

1VREF-

0AVSS

PIC18F26/45/46Q10

(DAC) 5-Bit Digital-to-Analog Converter Modu...

31.7.2 DAC1CON1

Name: DAC1CON1

Address: 0xF2F

DAC Data Register

Bit 7 6 5 4 3 2 1 0

DAC1R[4:0]

Access R/W R/W R/W R/W R/W

Reset 0 0 0 0 0

Bits 4:0 – DAC1R[4:0] Data Input Register for DAC bits

PIC18F26/45/46Q10

(DAC) 5-Bit Digital-to-Analog Converter Modu...

32. (ADC2) Analog-to-Digital Converter with Computation Module

The Analog-to-Digital Converter with Computation (ADC2) allows conversion of an analog input signal to

a 10-bit binary representation of that signal. This device uses analog inputs that are multiplexed into a

single Sample-and-Hold circuit. The output of the Sample-and-Hold is connected to the input of the

converter. The converter generates a 10-bit binary result via successive approximation and stores the

conversion result into the ADC result registers (32.7.15 ADRES).

Additionally, the following features are provided within the ADC module:

• 8-bit Acquisition Timer

• Hardware Capacitive Voltage Divider (CVD) support:

– 8-bit precharge timer

– Adjustable Sample-and-Hold capacitor array

– Guard ring digital output drive

• Automatic Repeat and Sequencing:

– Automated double sample conversion for CVD

– Two sets of Result registers (Result and Previous Result)

– Auto-conversion trigger

– Internal retrigger

• Computation Features:

– Averaging and low-pass filter functions

– Reference comparison

– 2-level threshold comparison

– Selectable interrupts

Figure 32-1 shows the block diagram of the ADC.

The ADC voltage reference is software selectable to be either internally generated or externally supplied.

The ADC can generate an interrupt upon completion of a conversion and upon threshold comparison.

These interrupts can be used to wake-up the device from Sleep.

PIC18F26/45/46Q10

(ADC2) Analog-to-Digital Converter with Comp...

Figure 32-1. ADC2 Block Diagram

Filename: 10-000034C.vsd

Title: 10-Bit ADC Block Diagram

Last Edit: 5/10/2016

First Used: PIC16(L)F188X5 (MFAF)

Vref+Vref-

Enable

DACx_output

FVR_buffer1

Temp Indicator

CHS<x:0>

External

Channel

Inputs

GO/DONE

complete

start

ADC

Sample Circuit

Write to bit

GO/DONE

VSS

VDD

VREF+ pin

ADPREF<1:0>

10-bit Result

ADRESH ADRESL

16

ADFM

10

Internal

Channel

Inputs

.

AN0

ANa

ANz

set bit ADIF

VSS

ADON

sampled

input

Q1

Q2

Q4

Fosc

Divider FOSC

FOSC/n

FRC

ADC

Clock

Select

ADC_clk

ADCS<2:0>

FRC

ADC CLOCK SOURCE

Trigger Select

Trigger Sources

. . .

TRIGSEL<x:0>

AUTO CONVERSION

TRIGGER

Rev. 10-000034C

5/10/2016

Positive

Reference

Select

00

11

10

01Reserved

FVR_buffer1

1

0

ADNREF

VREF- pin

VSS

To Computation

module

32.1 ADC Configuration

When configuring and using the ADC the following functions must be considered:

• Port Configuration

• Channel Selection

• ADC Voltage Reference Selection

• ADC Conversion Clock Source

• Interrupt Control

• Result Formatting

• Conversion Trigger Selection

• ADC Acquisition Time

PIC18F26/45/46Q10

(ADC2) Analog-to-Digital Converter with Comp...

• ADC Precharge Time

• Additional Sample-and-Hold Capacitor

• Single/Double Sample Conversion

• Guard Ring Outputs

32.1.1 Port Configuration

The ADC can be used to convert both analog and digital signals. When converting analog signals, the I/O

pin should be configured for analog by setting the associated TRIS and ANSEL bits. Refer to the "I/O

Ports" section for more information.

Important: Analog voltages on any pin that is defined as a digital input may cause the input

buffer to conduct excess current.

Related Links

15. I/O Ports

32.1.2 Channel Selection

The 32.7.8 ADPCH register determines which channel is connected to the Sample-and-Hold circuit.

There are several channel selections available as shown in the following selection table:

Table 32-1. ADC Positive Input Channel Selections

ADPCH ADC Positive Channel Input

111111 Fixed Voltage Reference (FVR)(2)

111110 DAC1 output(1)

111101 Temperature Indicator(3)

111100 AVSS (Analog Ground)

100011-111011 Reserved. No channel connected.

100010 RE2/ANE2(1)

100001 RE1/ANE1(1)

100000 RE0/ANE0(1)

011111 RD7/AND7(1)

011110 RD6/AND6(1)

011101 RD5/AND5(1)

011100 RD4/AND4(1)

011011 RD3/AND3(1)

011010 RD2/AND2(1)

011001 RD1/AND1(1)

011000 RD0/AND0(1)

PIC18F26/45/46Q10

(ADC2) Analog-to-Digital Converter with Comp...

...........continued

ADPCH ADC Positive Channel Input

010111 RC7/ANC7

010110 RC6/ANC6

010101 RC5/ ANC5

010100 RC4/ ANC4

010011 RC3/ANC3

010010 RC2/ANC2

010001 RC1/ ANC1

010000 RC0/ANC0

001111 RB7/ANB7

001110 RB6/ANB6

001101 RB5/ANB5

001100 RB4/ ANB4

001011 RB3/ANB3

001010 RB2/ ANB2

001001 RB1/ ANB1

001000 RB0/ANB0

000111 RA7/ANA7

000110 RA6/ANA6

000101 RA5/ANA5

000100 RA4/ ANA4

000011 RA3/ ANA3

000010 RA2/ ANA2

000001 RA1/ ANA1

000000 RA0/ANA0

Note:

1. 40/44-pin devices only.

When changing channels, a delay is required before starting the next conversion.

Refer to Section “ADC Operation” for more information.

PIC18F26/45/46Q10

(ADC2) Analog-to-Digital Converter with Comp...

Important: It is recommended to discharge the Sample-and-Hold capacitor when switching

between ADC channels by starting a conversion on a channel connected to VSS and terminating

the conversion after the acquisition time has elapsed. If the ADC does not have a dedicated VSS

input channel, the VSS selection (DAC1R<4:0> = b'00000') through the DAC output channel can

be used. If the DAC is in use, a free input channel can be connected to VSS, and can be used in

place of the DAC.

32.1.3 ADC Voltage Reference

The ADPREF bits provide control of the positive voltage reference. The positive voltage reference can be:

• VREF+ pin

• VDD

• FVR 1.024V

• FVR 2.048V

• FVR 4.096V

The ADNREF bit provides control of the negative voltage reference. The negative voltage reference can

be:

• VREF- pin

• VSS

32.1.4 Conversion Clock

The conversion clock source is software selected with the ADCS bit. When ADCS = 1 the ADC clock

source is an internal fixed-frequency clock referred to as FRC. When ADCS = 0 the ADC clock

frequencies are derived from FOSC. The 32.7.6 ADCLK register selects one of 64 possible clock options

from FOSC/2 to FOSC/128:

• FOSC/2

• FOSC/4

• FOSC/6

• FOSC/8

• FOSC/10

• ...

• FOSC/128

The time to complete one bit conversion is defined as the TAD. One full 10-bit conversion requires 11.5

TAD periods as shown in Figure 32-2.

For correct conversion, the appropriate TAD specification must be met. Refer to the "ADC Timing

Specifications" for more information. The "ADC Clock Period" table below gives examples of appropriate

ADC clock selections.

PIC18F26/45/46Q10

(ADC2) Analog-to-Digital Converter with Comp...

Important:

1. Except for the FRC clock source, any changes in the system clock frequency will change

the ADC clock frequency, which may adversely affect the ADC result.

2. The internal control logic of the ADC runs off of the clock selected by ADCS. When the

ADCS is set to ‘1’ (ADC runs on FRC), there may be unexpected delays in operation

when setting ADC control bits.

Table 32-2. ADC Clock Period (TAD) Vs. Device Operating Frequencies(1,4)

ADC Clock Period

(TAD)Device Frequency (FOSC)

ADC

Clock

Source

ADCLK 64 MHz 32 MHz 20 MHz 16 MHz 8 MHz 4 MHz 1 MHz

FOSC/2 000000 31.25

ns(2)

62.5 ns(2) 100 ns(2) 125 ns(2) 250 ns(2) 500 ns(2) 2.0 μs

FOSC/4 000001 62.5 ns(2) 125 ns(2) 200 ns(2) 250 ns(2) 500 ns(2) 1.0 μs 4.0 μs

FOSC/6 000010 125 ns(2) 187.5

ns(2)

300 ns(2) 375 ns(2) 750 ns(2) 1.5 μs 6.0 μs

FOSC/8 000011 187.5

ns(2)

250 ns(2) 400 ns(2) 500 ns(2) 1.0 μs 2.0 μs 8.0 μs(3)

... ... ... ... ... ... ... ... ...

FOSC/16 000111 250 ns(2) 500 ns(2) 800 ns(2) 1.0 μs 2.0 μs 4.0 μs 16.0 μs(3)

... ... ... ... ... ... ... ... ...

FOSC/128 111111 2.0 μs 4.0 μs 6.4 μs 8.0 μs 16.0 μs(3) 32.0 μs(2) 128.0

μs(2)

FRC ADCS=11.0-6.0

μs

1.0-6.0

μs

1.0-6.0

μs

1.0-6.0

μs

1.0-6.0

μs

1.0-6.0

μs

1.0-6.0

μs

Note:

1. See TAD parameter in the "Electrical Specifications" section for FRC source typical TAD value.

2. These values violate the required TAD time.

3. Outside the recommended TAD time.

4. The ADC clock period (TAD) and total ADC conversion time can be minimized when the ADC

clock is derived from the system clock FOSC. However, the FRC oscillator source must be used

when conversions are to be performed with the device in Sleep mode.

PIC18F26/45/46Q10

(ADC2) Analog-to-Digital Converter with Comp...

Figure 32-2. Analog-to-Digital Conversion TAD Cycles

On the following cycle:

ADRESH:ADRESL is loaded,

GO bit is cleared,

ADIF bit is set,

Rev. 10-000035B

11/3/2016

Set GO bit

External and Internal

Channels are

charged/discharged

If ADPRE ≠0If ADACQ ≠0

External and Internal

Channels share

charge

If ADPRE = 0

If ADACQ = 0

(Traditional Operation Start)

TAD1

TCY TCY-TAD TAD2TAD3TAD4TAD5TAD6TAD7TAD8TAD9TAD10TAD11

Holding capacitor CHOLD is disconnected from analog input (typically 100ns)

2 TCY

Conversion starts

b9 b8 b7 b6 b5 b4 b3 b2 b1 b0

Precharge

Time

1-255 TCY

(TPRE)

Acquisition/

Sharing Time

1-255 TCY

(TACQ)

Conversion Time

(Traditional Timing of ADC Conversion)

Related Links

39.4.8 Analog-to-Digital Converter (ADC) Conversion Timing Specifications

32.1.5 Interrupts

The ADC module allows for the ability to generate an interrupt upon completion of an Analog-to-Digital

Conversion. The ADC Interrupt Flag is the ADIF bit in the PIRx register. The ADC Interrupt Enable is the

ADIE bit in the PIEx register. The ADIF bit must be cleared in software.

Important:

1. The ADIF bit is set at the completion of every conversion, regardless of whether or not the

ADC interrupt is enabled.

2. The ADC operates during Sleep only when the FRC oscillator is selected.

This interrupt can be generated while the device is operating or while in Sleep. If the device is in Sleep,

the interrupt will wake-up the device. Upon waking from Sleep, the next instruction following the SLEEP

instruction is always executed. If the user is attempting to wake-up from Sleep and resume in-line code

execution, the ADIE bit and the PEIE bit of the INTCON register must both be set and the GIE bit of the

INTCON register must be cleared. If all three of these bits are set, the execution will switch to the

Interrupt Service Routine.

32.1.6 Result Formatting

The 10-bit ADC conversion result can be supplied in two formats, left justified or right justified. The ADFM

bit controls the output format as shown in the following figure.

PIC18F26/45/46Q10

(ADC2) Analog-to-Digital Converter with Comp...

Figure 32-3. 10-Bit ADC Conversion Result Format

ADRESH ADRESL

(ADFM = 0) MSB LSB

bit 7 bit 0 bit 7 bit 0

10-bit ADC Result Unimplemented: Read as ‘0’

(ADFM = 1)MSB LSB

bit 7 bit 0 bit 7 bit 0

Unimplemented: Read as ‘0’ 10-bit ADC Result

Rev. 30-000116A

5/16/2017

32.2 ADC Operation

32.2.1 Starting a Conversion

To enable the ADC module, the ADON must be set to a ‘1’. A conversion may be started by any of the

following:

• Software setting the ADGO bit to '1'

• An external trigger (source selected by 32.7.22 ADACT)

• A continuous-mode retrigger (see section 32.5.8 Continuous Sampling Mode)

.

Important: The ADGO bit should not be set in the same instruction that turns on the ADC.

Refer to 32.2.7 ADC Conversion Procedure (Basic Mode).

32.2.2 Completion of a Conversion

When any individual conversion is complete, the value already in 32.7.15 ADRES is written into 32.7.16

ADPREV (if ADPSIS = 0) and the new conversion results appear in ADRES. When the conversion

completes, the ADC module will:

• Clear the ADGO bit (unless the ADCONT bit is set)

• Set the ADIF Interrupt Flag bit

• Set the ADMATH bit

• Update 32.7.17 ADACC

After every conversion when ADDSEN = 0, or after every other conversion when ADDSEN = 1, the

following events occur:

•32.7.19 ADERR is calculated

• ADTIF interrupt is set if ADERR calculation meets threshold comparison

PIC18F26/45/46Q10

(ADC2) Analog-to-Digital Converter with Comp...

Important: Filter and threshold computations occur after the conversion itself is complete. As

such, interrupt handlers responding to ADIF should check ADTIF before reading filter and

threshold results.

32.2.3 Terminating a Conversion

If a conversion must be terminated before completion, the ADGO bit can be cleared in software. The

partial conversion results will be discarded and the ADRES registers will retain the value from the

previous conversion.

Important: A device Reset forces all registers to their Reset state. Thus, the ADC module is

turned off and any pending conversion is terminated.

32.2.4 ADC Operation During Sleep

The ADC module can operate during Sleep. This requires the ADC clock source to be set to the FRC

option. When the FRC oscillator source is selected, the ADC waits one additional instruction before

starting the conversion. This allows the SLEEP instruction to be executed, which can reduce system noise

during the conversion. If the ADC interrupt is enabled, the device will wake-up from Sleep when the

conversion completes. If the ADC interrupt is disabled, the ADC module is turned off after the conversion

completes, although the ADON bit remains set.

32.2.5 External Trigger During Sleep

If the external trigger is received during Sleep while the ADC clock source is set to the FRC, the ADC

module will perform the conversion and set the ADIF bit upon completion.

If an external trigger is received when the ADC clock source is something other than FRC, the trigger will

be recorded, but the conversion will not begin until the device exits Sleep.

32.2.6 Auto-Conversion Trigger

The auto-conversion trigger allows periodic ADC measurements without software intervention. When a

rising edge of the selected source occurs, the ADGO bit is set by hardware.

The auto-conversion trigger source is selected with the ADACT bits.

Using the auto-conversion trigger does not assure proper ADC timing. It is the user’s responsibility to

ensure that the ADC timing requirements are met. See the following table for auto-conversion sources.

Table 32-3. ADC Auto-Conversion Trigger Sources

ADACT Auto-conversioin Trigger Source

11111 Software write to ADPCH

11110 Reserved, do not use

11101 Software read of ADRESH

11100 Software read of ADERRH

11000 to 11011 Reserved, do not use

PIC18F26/45/46Q10

(ADC2) Analog-to-Digital Converter with Comp...

...........continued

ADACT Auto-conversioin Trigger Source

10111 CLC8_out

10110 CLC7_out

10101 CLC6_out

10100 CLC5_out

10011 CLC4_out

10010 CLC3_out

10001 CLC2_out

10000 CLC1_out

01111 Interrupt-on-change Interrupt Flag

01110 C2_out

01101 C1_out

01100 PWM4_out

01011 PWM3_out

01010 CCP2_trigger

01001 CCP1_trigger

01000 TMR6_postscaled

00111 TMR5_overflow

00110 TMR4_postscaled

00101 TMR3_overflow

00100 TMR2_postscaled

00011 TMR1_overflow

00010 TMR0_overflow

00001 Pin selected by ADACTPPS

00000 External Trigger Disabled

32.2.7 ADC Conversion Procedure (Basic Mode)

This is an example procedure for using the ADC to perform an Analog-to-Digital Conversion:

1. Configure Port:

1.1. Disable pin output driver (Refer to the TRISx register)

1.2. Configure pin as analog (Refer to the ANSELx register)

2. Configure the ADC module:

2.1. Select ADC conversion clock

2.2. Configure voltage reference

2.3. Select ADC input channel (precharge+acquisition)

PIC18F26/45/46Q10

(ADC2) Analog-to-Digital Converter with Comp...

2.4. Turn on ADC module

3. Configure ADC interrupt (optional):

3.1. Clear ADC interrupt flag

3.2. Enable ADC interrupt

3.3. Enable peripheral interrupt (PEIE bit)

3.4. Enable global interrupt (GIE bit)(1)

4. If ADACQ = 0, software must wait the required acquisition time(2).

5. Start conversion by setting the ADGO bit.

6. Wait for ADC conversion to complete by one of the following:

6.1. Polling the ADGO bit

6.2. Waiting for the ADC interrupt (interrupts enabled)

7. Read ADC Result.

8. Clear the ADC interrupt flag (required if interrupt is enabled).

Important:

1. With global interrupts disabled, the device will wake from Sleep but will not enter an

Interrupt Service Routine.

2. Refer to 32.3 ADC Acquisition Requirements.

Example 32-1. ADC Conversion (assembly)

; This code block configures the ADC for polling, Vdd and Vss references,

; FRC oscillator, and AN0 input.

; Conversion start & polling for completion are included.

BANKSEL ADCON1

clrf ADCON1 ;

clrf ADCON2 ; Legacy mode, no filtering, ADRES->ADPREV

clrf ADCON3 ; no math functions

clrf ADREF ; Vref = Vdd & Vss

clrf ADPCH ; select RA0/AN0

clrf ADACQ ; software controlled acquisition time

clrf ADCAP ; default S&H capacitance

clrf ADRPT ; no repeat measurements

clrf ADACT ; auto-conversion disabled

movlw B'10010100' ; ADC On, right-justified, FRC clock

movwf ADCON0

BANKSEL TRISA ;

bsf TRISA,0 ; Set RA0 to input

BANKSEL ANSEL ;

bsf ANSEL,0 ; Set RA0 to analog

call SampleTime ; Acquisiton delay

BANKSEL ADCON0

bsf ADCON0,ADGO ; Start conversion

btfsc ADCON0,ADGO ; Is conversion done?

goto $-2 ; No, test again

BANKSEL ADRESH ;

movf ADRESH,W ; Read upper 2 bits

movwf RESULTHI ; store in GPR space

movf ADRESL,W ; Read lower 8 bits

movwf RESULTLO ; Store in GPR space

Example 32-2. ADC Conversion (C)

/*This code block configures the ADC

PIC18F26/45/46Q10

(ADC2) Analog-to-Digital Converter with Comp...

for polling, VDD and VSS references, ADCRC

oscillator and AN0 input.

Conversion start & polling for completion

are included.

*/

void main() {

//System Initialize

initializeSystem();

//Setup ADC

ADCON0bits.FM = 1; //right justify

ADCON0bits.CS = 1; //FRC Clock

ADPCH = 0x00; //RA0 is Analog channel

TRISAbits.TRISA0 = 1; //Set RA0 to input

ANSELAbits.ANSELA0 = 1; //Set RA0 to analog

ADCON0bits.ON = 1; //Turn ADC On

while (1) {

ADCON0bits.GO = 1; //Start conversion

while (ADCON0bits.GO); //Wait for conversion done

resultHigh = ADRESH; //Read result

resultLow = ADRESL; //Read result

}

32.3 ADC Acquisition Requirements

For the ADC to meet its specified accuracy, the charge holding capacitor (CHOLD) must be allowed to fully

charge to the input channel voltage level. The analog input model is shown in Figure 32-5. The source

impedance (RS) and the internal sampling switch (RSS) impedance directly affect the time required to

charge the capacitor CHOLD. The sampling switch (RSS) impedance varies over the device voltage (VDD),

refer to Figure 32-5. The maximum recommended impedance for analog sources is 10 kΩ. As the source

impedance is decreased, the acquisition time may be decreased. After the analog input channel is

selected (or changed), an ADC acquisition must be completed before the conversion can be started. To

calculate the minimum acquisition time, Figure 32-4 may be used. This equation assumes that 1/2 LSb

error is used (1024 steps for the ADC). The 1/2 LSb error is the maximum error allowed for the ADC to

meet its specified resolution.

Figure 32-4. Acquisition Time Example

Assumptions: Temperature = 50°C; External impedance = 10kΩ; VDD = 5.0V

TACQ = Amplifier Settling Time + Hold Capacitor Charging Time + Temperature Coefficient

 = ++

 = 2 ++  25°0.05/°

The value for TC can be approximated with the following equations:

 11

2+ 1 1= ; [1] VCHOLD charged to within ½ lsb

 1 



 = ; [2] VCHOLD charge response to VAPPLIED

 1 



 = 11

2+ 1 1 ; Combining [1] and [2]

Note: Where n = ADC resolution in bits

PIC18F26/45/46Q10

(ADC2) Analog-to-Digital Converter with Comp...

Solving for TC:

=   + + 1/2047

=10 1Ω + 7Ω + 10Ω 0.0004885

= 1.37

Therefore:

 = 2 + 892 + 50°  25°0.05/°

 = 4.62 

Note:

1. The reference voltage (VREF) has no effect on the equation, since it cancels itself out.

2. The charge holding capacitor (CHOLD) is not discharged after each conversion.

3. The maximum recommended impedance for analog sources is 10 kΩ. This is required to meet the

pin leakage specification.

Figure 32-5. Analog Input Model

CPIN

VA

Rs

Analog

5 pF

V

DD

VT0.6V

V

T0.6V ILEAKAGE(1)

RIC 1k

Sampling

Switch

SS Rss

C

HOLD = 10 pF

Ref-

6V

Sampling Switch

5V

4V

3V

2V

5 6 7 8 9 10 11

(k)

VDD

Legend:

CPIN

VT

ILEAKAGE

RIC

SS

C

HOLD

= Input Capacitance

= Threshold Voltage

= Leakage current at the pin due to

= Interconnect Resistance

= Sampling Switch

= Sample/Hold Capacitance

various junctions

RSS

SS = Resistance of Sampling Switch

Input

Rev. 30-000114A

5/16/2017

R

PIC18F26/45/46Q10

(ADC2) Analog-to-Digital Converter with Comp...

Figure 32-6. ADC Transfer Function

3FFh

3FEh

ADC Output Code

3FDh

3FCh

03h

02h

01h

00h

Full-Scale

3FBh

0.5 LSB

REF- Zero-Scale

Transition REF+

Transition

1.5 LSB

Full-Scale Range

Analog Input Voltage

Rev. 30-000115A

5/16/2017

32.4 Capacitive Voltage Divider (CVD) Features

The ADC module contains several features that allow the user to perform a relative capacitance

measurement on any ADC channel using the internal ADC Sample-and-Hold capacitance as a reference.

This relative capacitance measurement can be used to implement capacitive touch or proximity sensing

applications. The following figure shows the basic block diagram of the CVD portion of the ADC module.

PIC18F26/45/46Q10

(ADC2) Analog-to-Digital Converter with Comp...

Figure 32-7. Hardware Capacitive Voltage Divider Block Diagram

Rev. 10-000322B

10/4/2017

ANx

Multiplexer

Additional

Sample

Capacitors

ADPPOL & Precharge

VDD

ADC

ADCAP

ADPPOL & Precharge

Precharge

VDD

32.4.1 CVD Operation

A CVD operation begins with the ADC’s internal Sample-and-Hold capacitor (CHOLD) being disconnected

from the path which connects it to the external capacitive sensor node. While disconnected, CHOLD is

precharged to VDD or VSS the sensor node is also charged to VSS or VDD, respectively to the level

opposite that of CHOLD. When the precharge phase is complete, the VDD/VSS bias paths for the two nodes

are shut off and the paths between CHOLD and the external sensor node is reconnected, at which time the

acquisition phase of the CVD operation begins. During acquisition, a capacitive voltage divider is formed

between the precharged CHOLD and sensor nodes, which results in a final voltage level setting on CHOLD

which is determined by the capacitances and precharge levels of the two nodes. After acquisition, the

ADC converts the voltage level on CHOLD. This process is then repeated with the selected precharge

levels inverted for both the CHOLD and the sensor nodes. The waveform for two CVD measurements,

which is known as differential CVD measurement, is shown in the following figure.

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Figure 32-8. Differential CVD Measurement Waveform

Rev. 10-000335A

10/2/2017

Precharge Acquire Convert Precharge Acquire Convert

First Sample Second Sample

External Capacitive Sensor

VDD

VSS

Time

Voltage

ADC Sample-and-Hold Capacitor

32.4.2 Precharge Control

The Precharge stage is an optional period of time that brings the external channel and internal Sample-

and-Hold capacitor to known voltage levels. Precharge is enabled by writing a nonzero value to the

ADPRE register. This stage is initiated when an ADC conversion begins, either from setting the ADGO

bit, a Special Event Trigger, or a conversion restart from the computation functionality. If the ADPRE

register is cleared when an ADC conversion begins, this stage is skipped.

During the precharge time, CHOLD is disconnected from the outer portion of the sample path that leads to

the external capacitive sensor and is connected to either VDD or VSS, depending on the value of the

ADPPOL bit. At the same time, the port pin logic of the selected analog channel is overridden to drive a

digital high or low out, in order to precharge the outer portion of the ADC’s sample path, which includes

the external sensor. The output polarity of this override is also determined by the ADPPOL bit such that

the external sensor cap is charged opposite that of the internal CHOLD cap. The amount of time that this

charging needs is controlled by the ADPRE register.

Important: The external charging overrides the TRIS setting of the respective I/O pin. If there

is a device attached to this pin, precharge should not be used.

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32.4.3 Acquisition Control for CVD (ADPRE > 0)

The Acquisition stage allows time for the voltage on the internal Sample-and-Hold capacitor to charge or

discharge from the selected analog channel. This acquisition time is controlled by the ADACQ register.

When ADPRE = 0, acquisition starts at the beginning of conversion. When ADPRE > 0, the acquisition

stage begins when precharge ends.

At the start of the acquisition stage, the port pin logic of the selected analog channel is overridden to turn

off the digital high/low output drivers so they do not affect the final result of the charge averaging. Also,

the selected ADC channel is connected to CHOLD. This allows charge averaging to proceed between the

precharged channel and the CHOLD capacitor.

Important: When ADPRE > 0 setting ADACQ to ‘0’ will set a maximum acquisition time (256

ADC clock cycles). When precharge is disabled, setting ADACQ to ‘0’ will disable hardware

acquisition time control.

32.4.4 Guard Ring Outputs

Figure 32-9 shows a typical guard ring circuit. CGUARD represents the capacitance of the guard ring trace

placed on the PCB board. The user selects values for RA and RB that will create a voltage profile on

CGUARD, which will match the selected acquisition channel.

The purpose of the guard ring is to generate a signal in phase with the CVD sensing signal to minimize

the effects of the parasitic capacitance on sensing electrodes. It also can be used as a mutual drive for

mutual capacitive sensing. For more information about active guard and mutual drive, see Application

Note AN1478, “mTouchTM Sensing Solution Acquisition Methods Capacitive Voltage Divider”.

The ADC has two guard ring drive outputs, ADGRDA and ADGRDB. These outputs can be routed

through PPS controls to I/O pins (see “Peripheral Pin Select (PPS) Module” for details). The polarity of

these outputs are controlled by the ADGPOL and ADIPEN bits.

At the start of the first precharge stage, both outputs are set to match the ADGPOL bit. Once the

acquisition stage begins, ADGRDA changes polarity, while ADGRDB remains unchanged. When

performing a double sample conversion, setting the ADIPEN bit causes both guard ring outputs to

transition to the opposite polarity of ADGPOL at the start of the second precharge stage, and ADGRDA

toggles again for the second acquisition. For more information on the timing of the guard ring output, refer

to Figure 32-9 and Figure 32-10.

Figure 32-9. Guard Ring Circuit

CGUARD

RA

RB

ADGRDA

ADGRDB

Rev. 30-000120A

5/16/2017

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Figure 32-10. Differential CVD with Guard Ring Output Waveform

Rev. 10-000336A

10/2/2017

Precharge Acquire Convert Precharge Acquire Convert

First Sample Second Sample

External Capacitive Sensor

VDD

VSS

Time

Voltage

ADGRDA

ADGRDB

Guard Ring Capacitance

Figure 32-11. Hardware CVD Sequence Timing Diagram

T

AD

1T

AD

2T

AD

3 T

AD

4 T

AD

5T

AD

6 T

AD

7T

AD

8 T

AD

11

Set GO/DONE bit

Holding capacitor C

HOLD

is disconnected from analog input (typically 100 ns)

T

AD

9 T

AD

10

T

CY

- T

AD

AADRES0H:AADRES0L is loaded,

ADIF bit is set,

Conversion starts

b0

b9 b6 b5 b4 b3 b2 b1

b8 b7

On the following cycle:

1-255 T

INST

1-255 T

INST

Precharge Acquisition/

Sharing Time

Time Conversion Time

If ADPRE

0

If ADACQ

0

If ADPRE =

0

If ADACQ =

0

GO/DONE bit is cleared

(Traditional Timing of ADC Conversion)

External and Internal

Channels are

charged/discharged

External and Internal

Channels share

charge

(Traditional Operation Start)

(T

PRE

) (T

ACQ

)T

AD

1T

AD

2T

AD

3 T

AD

4 T

AD

5T

AD

6 T

AD

7T

AD

8 T

AD

11

Set GO/DONE bit

Holding capacitor C

HOLD

is disconnected from analog input (typically 100 ns)

T

AD

9 T

AD

10

T

CY

- T

AD

AADRES0H:AADRES0L is loaded,

ADIF bit is set,

Conversion starts

b0

b9 b6 b5 b4 b3 b2 b1

b8 b7

On the following cycle:

1-255 T

INST

1-255 T

INST

Precharge Acquisition/

Sharing Time

Time Conversion Time

If ADPRE

0

If ADACQ

0

If ADPRE =

0

If ADACQ =

0

GO/DONE bit is cleared

(Traditional Timing of ADC Conversion)

External and Internal

Channels are

charged/discharged

External and Internal

Channels share

charge

(Traditional Operation Start)

(T

PRE

) (T

ACQ

)

Rev. 30-000122A

5/16/2017

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32.4.5 Additional Sample-and-Hold Capacitance

Additional capacitance can be added in parallel with the internal Sample-and-Hold capacitor (CHOLD) by

using the ADCAP register. This register selects a digitally programmable capacitance that is added to the

ADC conversion bus, increasing the effective internal capacitance of the Sample-and-Hold capacitor in

the ADC module. This is used to improve the match between internal and external capacitance for a

better sensing performance. The additional capacitance does not affect analog performance of the ADC

because it is not connected during conversion. See Figure 32-12.

32.5 Computation Operation

The ADC module hardware is equipped with post conversion computation features. These features

provide data post-processing functions that can be operated on the ADC conversion result, including

digital filtering/averaging and threshold comparison functions.

Figure 32-12. Computational Features Simplified Block Diagram

Rev. 10-000260B

8/4/2015

ADRES

Average/

Filter 1

0

ADPREV

Error

Calculation

ADSTPT

ADFILT

Threshold

Logic

ADPSIS

ADCALC<2:0>

ADMD<2:0>

ADUTHR ADLTHR

Set

Interrupt

Flag

ADERR

The operation of the ADC computational features is controlled by the ADMD bits.

The module can be operated in one of five modes:

• Basic: This is a legacy mode. In this mode, ADC conversion occurs on single (ADDSEN = 0) or

double (ADDSEN = 1) samples. ADIF is set after each conversion is complete.

• Accumulate: With each trigger, the ADC conversion result is added to the accumulator and ADCNT

increments. ADIF is set after each conversion. ADTIF is set according to the calculation mode.

• Average: With each trigger, the ADC conversion result is added to the accumulator. When the

ADRPT number of samples have been accumulated, a threshold test is performed. Upon the next

trigger, the accumulator is cleared. For the subsequent tests, additional ADRPT samples are required

to be accumulated.

• Burst Average: At the trigger, the accumulator is cleared. The ADC conversion results are then

collected repetitively until ADRPT samples are accumulated and finally the threshold is tested.

• Low-Pass Filter (LPF): With each trigger, the ADC conversion result is sent through a filter. When

ADRPT samples have occurred, a threshold test is performed. Every trigger after that the ADC

conversion result is sent through the filter and another threshold test is performed.

The five modes are summarized in the following table.

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Table 32-4. Computation Modes

rotatethispage90 Register Clear

Event

Value after Cycle(2)

Completion

Threshold Operations Value at ADTIF Interrupt

Mode ADMD ADACC and

ADCNT

ADACC(1) ADCNT Retrigger Threshold Test Interrupt ADAOV ADFLTR ADCNT

Basic 0 ADACLR = 1Unchanged Unchanged No Every Sample If

threshold=true

N/A N/A count

Accumulate 1 ADACLR = 1S1 + ADACC

or

(S2-S1) +

ADACC

If (ADCNT=FF):

ADCNT,

otherwise:

ADCNT+1

No Every Sample If

threshold=true

ADACC

Overflow

ADACC/

2ADCRS

count

Average 2 ADACLR = 1 or

ADCNT>=ADRPT

at ADGO or

retrigger

S1 + ADACC

or

(S2-S1) +

ADACC

If (ADCNT=FF):

ADCNT,

otherwise:

ADCNT+1

No If

ADCNT>=ADRPT

If

threshold=true

ADACC

Overflow

ADACC/

2ADCRS

count

Burst

Average

3 ADACLR = 1 or

ADGO set or

retrigger

Each

repetition:

same as

Average

End with

sum of all

samples

Each repetition:

same as

Average

End with

ADCNT=ADRPT

Repeat while

ADCNT<ADRPT

If

ADCNT>=ADRPT

If

threshold=true

ADACC

Overflow

ADACC/

2ADCRS

ADRPT

Low-pass

Filter

4 ADACLR = 1S1+ADACC-

ADACC/

2ADCRS

or

(S2-

S1)+ADACC-

ADACC/

2ADCRS

If (ADCNT=FF):

ADCNT,

otherwise:

ADCNT+1

No If

ADCNT>=ADRPT

If

threshold=true

ADACC

Overflow

Filtered

Value

count

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...........continued

rotatethispage90 Register Clear

Event

Value after Cycle(2)

Completion

Threshold Operations Value at ADTIF Interrupt

Mode ADMD ADACC and

ADCNT

ADACC(1) ADCNT Retrigger Threshold Test Interrupt ADAOV ADFLTR ADCNT

Note:

1. S1 and S2 are abbreviations for Sample 1 and Sample 2, respectively. When ADDSEN = 0, S1 = ADRES; When ADDSEN = 1, S1 =

ADPREV and S2 = ADRES.

2. When ADDSEN = 0 then Cycle means one conversion. When ADDSEN = 1 then Cycle means two conversions.

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32.5.1 Digital Filter/Average

The digital filter/average module consists of an accumulator with data feedback options, and control logic

to determine when threshold tests need to be applied. The accumulator is a 16-bit wide register that can

be accessed through the 32.7.17 ADACC registers.

Upon each trigger event (the ADGO bit set or external event trigger), the ADC conversion result is added

to the accumulator. If the accumulated value exceeds 2(accumulator_width)-1 = 216 = 65535, the ADAOV

overflow bit is set.

The number of samples to be accumulated is determined by the ADRPT (A/D Repeat Setting) register.

Each time a sample is added to the accumulator, the ADCNT register is incremented. Once ADRPT

samples are accumulated (ADCNT = ADRPT), an accumulator clear command can be issued by the

software by setting the ADACLR bit. Setting the ADACLR bit will also clear the ADAOV (Accumulator

overflow) bit, as well as the ADCNT register. The ADACLR bit is cleared by the hardware when

accumulator clearing action is complete.

Important: When ADC is operating from FRC, five FRC clock cycles are required to execute

the ADACC clearing operation.

The ADCRS bits control the data shift on the accumulator result, which effectively divides the value in

accumulator (32.7.17 ADACC) registers. For the Accumulate mode of the digital filter, the shift provides a

simple scaling operation. For the Average/Burst Average mode, the shift bits are used to determine

number of samples for averaging. For the Low-pass Filter mode, the shift is an integral part of the filter,

and determines the cutoff frequency of the filter. Table 32-5 shows the -3 dB cutoff frequency in ωT

(radians) and the highest signal attenuation obtained by this filter at nyquist frequency (ωT = π).

Table 32-5. Low-pass Filter -3 dB Cutoff Frequency

ADCRS ωT (radians) @ -3 dB Frequency dB @ Fnyquist=1/(2T)

1 0.72 -9.5

2 0.284 -16.9

3 0.134 -23.5

4 0.065 -29.8

5 0.032 -36.0

6 0.016 -42.0

32.5.2 Basic Mode

Basic mode (ADMD = 000) disables all additional computation features. In this mode, no accumulation

occurs but threshold error comparison is performed. Double sampling, Continuous mode, and all CVD

features are still available, but no features involving the digital filter/average features are used.

32.5.3 Accumulate Mode

In Accumulate mode (ADMD = 001), after every conversion, the ADC result is added to the ADACC

register. The ADACC register is right-shifted by the value of the ADCRS bits. This right-shifted value is

copied in to the ADFLT register. The Formatting mode does not affect the right-justification of the ADACC

value. Upon each sample, ADCNT is also incremented, incrementing the number of samples

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accumulated. After each sample and accumulation, the ADACC value has a threshold comparison

performed on it (see 32.5.7 Threshold Comparison) and the ADTIF interrupt may trigger.

32.5.4 Average Mode

In Average Mode (ADMD = 010), the ADACC registers accumulate with each ADC sample, much as in

Accumulate mode, and the ADCNT register increments with each sample. The ADFLT register is also

updated with the right-shifted value of the ADACC register. The value of the ADCRS bits governs the

number of right shifts. However, in Average mode, the threshold comparison is performed upon ADCNT

being greater than or equal to a user-defined ADRPT value. In this mode when ADRPT = 2^ADCNT, then

the final accumulated value will be divided by number of samples, allowing for a threshold comparison

operation on the average of all gathered samples.

32.5.5 Burst Average Mode

The Burst Average mode (ADMD = 011) acts the same as the Average mode in most respects. The one

way it differs is that it continuously retriggers ADC sampling until the ADCNT value is greater than or

equal to ADRPT, even if Continuous Sampling mode (see 32.5.8 Continuous Sampling Mode) is not

enabled. This allows for a threshold comparison on the average of a short burst of ADC samples.

32.5.6 Low-pass Filter Mode

The Low-pass Filter mode (ADMD = 100) acts similarly to the Average mode in how it handles samples

(accumulates samples until ADCNT value greater than or equal to ADRPT, then triggers threshold

comparison), but instead of a simple average, it performs a low-pass filter operation on all of the samples,

reducing the effect of high-frequency noise on the average, then performs a threshold comparison on the

results. (see 32.5 Computation Operation for a more detailed description of the mathematical operation).

In this mode, the ADCRS bits determine the cutoff frequency of the low-pass filter (as demonstrated by

32.5.1 Digital Filter/Average).

32.5.7 Threshold Comparison

At the end of each computation:

• The conversion results are latched and held stable at the end-of-conversion.

• The error (32.7.19 ADERR) is calculated based on a difference calculation which is selected by the

ADCALC bits. The value can be one of the following calculations (see Table 32-6 for more details):

– The first derivative of single measurements

– The CVD result when double-sampling is enabled

– The current result vs. a setpoint

– The current result vs. the filtered/average result

– The first derivative of the filtered/average value

– Filtered/average value vs. a setpoint

• The result of the calculation (ADERR) is compared to the upper and lower thresholds, 32.7.21

ADUTH and 32.7.20 ADLTH registers, to set the ADUTHR and ADLTHR flag bits. The threshold

logic is selected by ADTMD bits. The threshold trigger option can be one of the following:

– Never interrupt

– Error is less than lower threshold

– Error is greater than or equal to lower threshold

– Error is between thresholds (inclusive)

– Error is outside of thresholds

– Error is less than or equal to upper threshold

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– Error is greater than upper threshold

– Always interrupt regardless of threshold test results

– If the threshold condition is met, the threshold interrupt flag ADTIF is set.

Note:

1. The threshold tests are signed operations.

2. If ADAOV is set, a threshold interrupt is signaled. It is good practice for threshold interrupt handlers

to verify the validity of the threshold by checking ADAOV.

Table 32-6. ADC Error Calculation Mode

ADCALC

ADERR

Application

ADDSEN = 0 Single-

Sample Mode

ADDSEN = 1 CVD

Double-Sample Mode(1)

111 ADFLTR ADFLTR Filtered results above or below the

threshold.

110 ADRES ADRES Measurement above or below the

threshold

101 ADLFTR-ADSTPT ADFLTR-ADSTPT Average/filtered value vs. setpoint

100 ADPREV-ADFLTR ADPREV-ADFLTR First derivative of filtered value(3)

(negative)

011 Reserved Reserved Reserved

010 ADRES-ADFLTR (ADRES-ADPREV)-

ADFLTR

Actual result vs. averaged/filtered

value

001 ADRES-ADSTPT (ADRES-ADPREV)-

ADSTPT

Actual result vs.setpoint

000 ADRES-ADPREV ADRES-ADPREV First derivative of single

measurement(2)

Actual CVD result(1,2)

Note:

1. When ADDSEN=1, ADERR is computed only after every second sample.

2. When ADPSIS = 0.

3. When ADPSIS = 1.

32.5.8 Continuous Sampling Mode

Setting the ADCONT bit register automatically retriggers a new conversion cycle after updating the

ADACC register. That means the ADGO bit is set to generate automatic retriggering, until the device

Reset occurs or the ADSOI A/D Stop-on-interrupt bit is set (correct logic).

32.5.9 Double Sample Conversion

Double sampling is enabled by setting the ADDSEN bit. When this bit is set, two conversions are required

before the module will calculate threshold error. Each conversion must still be triggered separately when

ADCONT = 0. The first conversion will set the ADMATH bit and update ADACC, but will not calculate

ADERR or trigger ADTIF. When the second conversion completes, the first value is transferred to

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ADPREV (depending on the setting of ADPSIS) and the value of the second conversion is placed into

ADRES. Only upon the completion of the second conversion is ADERR calculated and ADTIF triggered

(depending on the value of ADCALC).

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32.6 Register Summary - ADC Control

Address Name Bit Pos.

0x0F51 ADACT 7:0 ADACT[4:0]

0x0F52 ADCLK 7:0 ADCS[5:0]

0x0F53 ADREF 7:0 ADNREF ADPREF[1:0]

0x0F54 ADCON1 7:0 ADPPOL ADIPEN ADGPOL ADDSEN

0x0F55 ADCON2 7:0 ADPSIS ADCRS[2:0] ADACLR ADMD[2:0]

0x0F56 ADCON3 7:0 ADCALC[2:0] ADSOI ADTMD[2:0]

0x0F57 ADACQ 7:0 ADACQ[7:0]

0x0F58 ADCAP 7:0 ADCAP[4:0]

0x0F59 ADPRE 7:0 ADPRE[7:0]

0x0F5A ADPCH 7:0 ADPCH[5:0]

0x0F5B ADCON0 7:0 ADON ADCONT ADCS ADFM ADGO

0x0F5C ADPREV

7:0 ADPREVL[7:0]

15:8 ADPREVH[7:0]

0x0F5E ADRES

7:0 ADRESL[7:0]

15:8 ADRESH[7:0]

0x0F60 ADSTAT 7:0 ADAOV ADUTHR ADLTHR ADMATH ADSTAT[2:0]

0x0F61 ADRPT 7:0 ADRPT[7:0]

0x0F62 ADCNT 7:0 ADCNT[7:0]

0x0F63 ADSTPT

7:0 ADSTPTL[7:0]

15:8 ADSTPTH[7:0]

0x0F65 ADLTH

7:0 ADLTHL[7:0]

15:8 ADLTHH[7:0]

0x0F67 ADUTH

7:0 ADUTHL[7:0]

15:8 ADUTHH[7:0]

0x0F69 ADERR

7:0 ADERRL[7:0]

15:8 ADERRH[7:0]

0x0F6B ADACC

7:0 ADACCL[7:0]

15:8 ADACCH[7:0]

0x0F6D ADFLTR

7:0 ADFLTRL[7:0]

15:8 ADFLTRH[7:0]

32.7 Register Definitions: ADC Control

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32.7.1 ADCON0

Name: ADCON0

Address: 0xF5B

ADC Control Register 0

Bit 7 6 5 4 3 2 1 0

ADON ADCONT ADCS ADFM ADGO

Access R/W R/W R/W R/W R/W/HC

Reset 0 0 0 0 0

Bit 7 – ADON ADC Enable bit

Value Description

1ADC is enabled

0ADC is disabled

Bit 6 – ADCONT ADC Continuous Operation Enable bit

Value Description

1ADGO is retriggered upon completion of each conversion trigger until ADTIF is set (if ADSOI

is set) or until ADGO is cleared (regardless of the value of ADSOI)

0ADC is cleared upon completion of each conversion trigger

Bit 4 – ADCS ADC Clock Selection bit

Value Description

1Clock supplied from FRC dedicated oscillator

0Clock supplied by Fosc, divided according to ADCLK register

Bit 2 – ADFM ADC results Format/alignment Selection

Value Description

1ADRES and ADPREV data are right justified

0ADRES and ADPREV data are left justified, zero-filled

Bit 0 – ADGO ADC Conversion Status bit

Value Description

1ADC conversion cycle in progress. Setting this bit starts an ADC conversion cycle. The bit is

cleared by hardware as determined by the ADCONT bit

0ADC conversion completed/not in progress

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32.7.2 ADCON1

Name: ADCON1

Address: 0xF54

ADC Control Register 1

Bit 7 6 5 4 3 2 1 0

ADPPOL ADIPEN ADGPOL ADDSEN

Access R/W R/W R/W R/W

Reset 0 0 0 0

Bit 7 – ADPPOL Precharge Polarity bit

Action During 1st Precharge Stage

Value Condition Description

xADPRE=0 Bit has no effect

1ADPRE>0 and ADC input is I/O pin Pin shorted to AVDD

0ADPRE>0 and ADC input is I/O pin Pin shorted to VSS

1ADPRE>0 and ADC input is internal CHOLD Shorted to AVDD

0ADPRE>0 and ADC input is internal CHOLD Shorted to VSS

Bit 6 – ADIPEN A/D Inverted Precharge Enable bit

Value Condition Description

xADDSEN = 0 Bit has no effect

1ADDSEN = 1 The precharge and guard signals in the second conversion cycle are the

opposite polarity of the first cycle

0ADDSEN = 1 Both Conversion cycles use the precharge and guards specified by ADPPOL

and ADGPOL

Bit 5 – ADGPOL Guard Ring Polarity Selection bit

Value Description

1ADC guard Ring outputs start as digital high during Precharge stage

0ADC guard Ring outputs start as digital low during Precharge stage

Bit 0 – ADDSEN Double-Sample Enable bit

Value Description

1Two conversions are processed as a pair. The selected computation is performed after every

second conversion.

0Selected computation is performed after every conversion

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32.7.3 ADCON2

Name: ADCON2

Address: 0xF55

ADC Control Register 2

Bit 7 6 5 4 3 2 1 0

ADPSIS ADCRS[2:0] ADACLR ADMD[2:0]

Access R/W R/W R/W R/W R/W/HC R/W R/W R/W

Reset 0 0 0 0 0 0 0 0

Bit 7 – ADPSIS ADC Previous Sample Input Select bits

Value Description

1ADFLTR is transferred to ADPREV at start-of-conversion

0ADRES is transferred to ADPREV at start-of-conversion

Bits 6:4 – ADCRS[2:0] ADC Accumulated Calculation Right Shift Select bits

Value Condition Description

1 to 6 ADMD = 'b100 Low-pass filter time constant is 2ADCRS, filter gain is 1:1(2)

1 to 6 ADMD =' b011 to 'b001 The accumulated value is right-shifted by ADCRS (divided by

2ADCRS)(1,2)

xADMD ='b000 These bits are ignored

Bit 3 – ADACLR A/D Accumulator Clear Command bit(3)

Value Description

1ADACC, ADAOV and ADCNT registers are cleared

0Clearing action is complete (or not started)

Bits 2:0 – ADMD[2:0] ADC Operating Mode Selection bits(4)

Value Description

111-101 Reserved

100 Low-pass Filter mode

011 Burst Average mode

010 Average mode

001 Accumulate mode

000 Basic (Legacy) mode

Note:

1. To correctly calculate an average, the number of samples (set in ADRPT) must be 2ADCRS.

2. ADCRS = 'b111 and 'b000 are reserved.

3. This bit is cleared by hardware when the accumulator operation is complete; depending on

oscillator selections, the delay may be many instructions.

4. See Table 32-4 for Full mode descriptions.

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32.7.4 ADCON3

Name: ADCON3

Address: 0xF56

ADC Control Register 3

Bit 7 6 5 4 3 2 1 0

ADCALC[2:0] ADSOI ADTMD[2:0]

Access R/W R/W R/W R/W/HC R/W R/W R/W

Reset 0 0 0 0 0 0 0

Bits 6:4 – ADCALC[2:0] ADC Error Calculation Mode Select bits

See Table 32-6 table for selection details.

Bit 3 – ADSOI ADC Stop-on-Interrupt bit

Value Condition Description

1ADCONT = 1ADGO is cleared when the threshold conditions are met, otherwise the

conversion is retriggered

0ADCONT = 1ADGO is not cleared by hardware, must be cleared by software to stop

retriggers

xADCONT = 0This bit is not used

Bits 2:0 – ADTMD[2:0] Threshold Interrupt Mode Select bits

Value Description

111 Interrupt regardless of threshold test results

110 Interrupt if ADERR>ADUTH

101 Interrupt if ADERR≤ADUTH

100 Interrupt if ADERR<ADLTH or ADERR>ADUTH

011 Interrupt if ADERR>ADLTH and ADERR<ADUTH

010 Interrupt if ADERR≥ADLTH

001 Interrupt if ADERR<ADLTH

000 Never interrupt

PIC18F26/45/46Q10

(ADC2) Analog-to-Digital Converter with Comp...

32.7.5 ADSTAT

Name: ADSTAT

Address: 0xF60

ADC Status Register

Bit 7 6 5 4 3 2 1 0

ADAOV ADUTHR ADLTHR ADMATH ADSTAT[2:0]

Access R/C/HS/HC RO RO R/C/HS/HC RO RO RO

Reset 0 0 0 0 0 0 0

Bit 7 – ADAOV ADC Accumulator Overflow bit

Value Description

1ADC accumulator or ADERR calculation have overflowed

0ADC accumulator and ADERR calculation have not overflowed

Bit 6 – ADUTHR ADC Module Greater-than Upper Threshold Flag bit

Value Description

1ADERR >ADUTH

0ADERR≤ADUTH

Bit 5 – ADLTHR ADC Module Less-than Lower Threshold Flag bit

Value Description

1ADERR<ADLTH

0ADERR≥ADLTH

Bit 4 – ADMATH ADC Module Computation Status bit

Value Description

1Registers ADACC, ADFLTR, ADUTH, ADLTH and the ADAOV bit are updating or have

already updated

0Associated registers/bits have not changed since this bit was last cleared

Bits 2:0 – ADSTAT[2:0]

ADC Module Cycle Multi-Stage Status bits(1)

Value Description

111 ADC module is in 2nd conversion stage

110 ADC module is in 2nd acquisition stage

101 ADC module is in 2nd precharge stage

100 Not used

011 ADC module is in 1st conversion stage

010 ADC module is in 1st acquisition stage

001 ADC module is in 1st precharge stage

000 ADC module is not converting

Note:

1. If ADCS = 1, and FOSC<FRC, the indicated status may not be valid.

PIC18F26/45/46Q10

(ADC2) Analog-to-Digital Converter with Comp...

32.7.6 ADCLK

Name: ADCLK

Address: 0xF52

ADC Clock Selection Register

Bit 7 6 5 4 3 2 1 0

ADCS[5:0]

Access R/W R/W R/W R/W R/W R/W

Reset 0 0 0 0 0 0

Bits 5:0 – ADCS[5:0] ADC Conversion Clock Select bits

Value Description

nADC Clock frequency = FOSC/(2*(n+1))

PIC18F26/45/46Q10

(ADC2) Analog-to-Digital Converter with Comp...

32.7.7 ADREF

Name: ADREF

Address: 0xF53

ADC Reference Selection Register

Bit 7 6 5 4 3 2 1 0

ADNREF ADPREF[1:0]

Access R/W R/W R/W

Reset 0 0 0

Bit 4 – ADNREF ADC Negative Voltage Reference Selection bit

Value Description

1VREF- is connected to external VREF-

0VREF- is connected to AVSS

Bits 1:0 – ADPREF[1:0] ADC Positive Voltage Reference Selection bits

Value Description

11 VREF+ is connected to internal Fixed Voltage Reference (FVR) module

10 VREF+ is connected to external VREF+

01 Reserved

00 VREF+ is connected to VDD

PIC18F26/45/46Q10

(ADC2) Analog-to-Digital Converter with Comp...

32.7.8 ADPCH

Name: ADPCH

Address: 0xF5A

ADC Positive Channel Selection Register

Bit 7 6 5 4 3 2 1 0

ADPCH[5:0]

Access R/W R/W R/W R/W R/W R/W

Reset 0 0 0 0 0 0

Bits 5:0 – ADPCH[5:0] ADC Positive Input Channel Selection bits

See Channel Selection Table for input selection details.

PIC18F26/45/46Q10

(ADC2) Analog-to-Digital Converter with Comp...

32.7.9 ADPRE

Name: ADPRE

Address: 0xF59

ADC Precharge Time Control Register

Bit 7 6 5 4 3 2 1 0

ADPRE[7:0]

Access R/W R/W R/W R/W R/W R/W R/W R/W

Reset 0 0 0 0 0 0 0 0

Bits 7:0 – ADPRE[7:0] Precharge Time Select bits

Value Description

1 to

255

Number of ADC clocks in the precharge time.

0Precharge time is not included in the data conversion cycle

PIC18F26/45/46Q10

(ADC2) Analog-to-Digital Converter with Comp...

32.7.10 ADACQ

Name: ADACQ

Address: 0xF57

ADC Acquisition Time Control Register

Bit 7 6 5 4 3 2 1 0

ADACQ[7:0]

Access R/W R/W R/W R/W R/W R/W R/W R/W

Reset 0 0 0 0 0 0 0 0

Bits 7:0 – ADACQ[7:0] Acquisition (charge share time) Select bits

Value Description

0x01 to

0xFF

Number of ADC clock periods in the acquisition time

0x00 Acquisition time is not included in the data conversion cycle

PIC18F26/45/46Q10

(ADC2) Analog-to-Digital Converter with Comp...

32.7.11 ADCAP

Name: ADCAP

Address: 0xF58

ADC Additional Sample Capacitor Selection Register

Bit 7 6 5 4 3 2 1 0

ADCAP[4:0]

Access R/W R/W R/W R/W R/W

Reset 0 0 0 0 0

Bits 4:0 – ADCAP[4:0] ADC Additional Sample Capacitor Selection bits

Value Description

1 to 31 Number of pF in the additional capacitance

0No additional capacitance

PIC18F26/45/46Q10

(ADC2) Analog-to-Digital Converter with Comp...

32.7.12 ADRPT

Name: ADRPT

Address: 0xF61

ADC Repeat Setting Register

Bit 7 6 5 4 3 2 1 0

ADRPT[7:0]

Access R/W R/W R/W R/W R/W R/W R/W R/W

Reset 0 0 0 0 0 0 0 0

Bits 7:0 – ADRPT[7:0] ADC Repeat Threshold bits

Determines the number of times that the ADC is triggered for a threshold check. When ADCNT reaches

this value the error threshold is checked. Used when the computation mode is Low-pass Filter, Burst

Average, or Average. See Table 32-4 for more details.

PIC18F26/45/46Q10

(ADC2) Analog-to-Digital Converter with Comp...

32.7.13 ADCNT

Name: ADCNT

Address: 0xF62

ADC Repeat Counter Register

Bit 7 6 5 4 3 2 1 0

ADCNT[7:0]

Access R/W R/W R/W R/W R/W R/W R/W R/W

Reset 0 0 0 0 0 0 0 0

Bits 7:0 – ADCNT[7:0] ADC Repeat Count bits

Counts the number of times that the ADC is triggered before the threshold is checked. When this value

reaches ADPRT then the threshold is checked. Used when the computation mode is Low-pass Filter,

Burst Average, or Average. See Table 32-4 for more details.

PIC18F26/45/46Q10

(ADC2) Analog-to-Digital Converter with Comp...

32.7.14 ADFLTR

Name: ADFLTR

Address: 0xF6D

ADC Filter Register. In Accumulate, Average, and Burst Average mode, this is equal to ADACC right

shifted by the ADCRS bits of ADCON2. In LPF mode, this is the output of the low-pass filter.

Bit 15 14 13 12 11 10 9 8

ADFLTRH[7:0]

Access RO RO RO RO RO RO RO RO

Reset x x x x x x x x

Bit 7 6 5 4 3 2 1 0

ADFLTRL[7:0]

Access RO RO RO RO RO RO RO RO

Reset x x x x x x x x

Bits 15:8 – ADFLTRH[7:0] ADC Filter Output Most Significant bits

Bits 7:0 – ADFLTRL[7:0] ADC Filter Output Least Significant bits

PIC18F26/45/46Q10

(ADC2) Analog-to-Digital Converter with Comp...

32.7.15 ADRES

Name: ADRES

Address: 0xF5E

ADC Result Register

Bit 15 14 13 12 11 10 9 8

ADRESH[7:0]

Access R/W R/W R/W R/W R/W R/W R/W R/W

Reset 0 0 0 0 0 0 0 0

Bit 7 6 5 4 3 2 1 0

ADRESL[7:0]

Access R/W R/W R/W R/W R/W R/W R/W R/W

Reset 0 0 0 0 0 0 0 0

Bits 15:8 – ADRESH[7:0] ADC Result Register bits. High bits

Value Condition Description

0x00,0x

01,0x02

,0x03

ADFM=1Upper 2 bits of result

0 to

0xFF

ADFM=0Upper 8 bits of result

Bits 7:0 – ADRESL[7:0] ADC Result Register bits. Lower bits

Value Condition Description

0 to

0xFF

ADFM=1Lower 8 bits of result

0x00,0x

40,0x80

,0xC0

ADFM=0Lower 2 bits of result

PIC18F26/45/46Q10

(ADC2) Analog-to-Digital Converter with Comp...

32.7.16 ADPREV

Name: ADPREV

Address: 0xF5C

ADC Previous Result Register

Bit 15 14 13 12 11 10 9 8

ADPREVH[7:0]

Access RO RO RO RO RO RO RO RO

Reset 0 0 0 0 0 0 0 0

Bit 7 6 5 4 3 2 1 0

ADPREVL[7:0]

Access RO RO RO RO RO RO RO RO

Reset 0 0 0 0 0 0 0 0

Bits 15:8 – ADPREVH[7:0] Previous ADC Result Most Significant bits

Value Condition Description

0 to

0xFF

ADPSIS=1Upper byte of ADFLTR at the start of current ADC conversion

varies ADPSIS=0Upper bits of ADRES at the start of current ADC conversion(1)

Bits 7:0 – ADPREVL[7:0] Previous ADC Result Least Significant bits

Value Condition Description

0 to

0xFF

ADPSIS=1Lower byte of ADFLTR at the start of current ADC conversion

varies ADPSIS=0Lower bits of ADRES at the start of current ADC conversion(1)

Note: If ADPSIS = 0, ADPREVH and ADPREVL are formatted the same way as ADRES is, depending

on the ADFM bit.

PIC18F26/45/46Q10

(ADC2) Analog-to-Digital Converter with Comp...

32.7.17 ADACC

Name: ADACC

Address: 0xF6B

ADC Accumulator Register

See Table 32-4 for more details.

Bit 15 14 13 12 11 10 9 8

ADACCH[7:0]

Access R/W R/W R/W R/W R/W R/W R/W R/W

Reset x x x x x x x x

Bit 7 6 5 4 3 2 1 0

ADACCL[7:0]

Access R/W R/W R/W R/W R/W R/W R/W R/W

Reset x x x x x x x x

Bits 15:8 – ADACCH[7:0]

ADC Accumulator Most Significant Byte.

Reset States: POR/BOR = xxxxxxxx

All Other Resets = uuuuuuuu

Bits 7:0 – ADACCL[7:0]

ADC Accumulator Least Significant Byte.

Reset States: POR/BOR = xxxxxxxx

All Other Resets = uuuuuuuu

PIC18F26/45/46Q10

(ADC2) Analog-to-Digital Converter with Comp...

32.7.18 ADSTPT

Name: ADSTPT

Address: 0xF63

ADC Threshold Setpoint Register

Depending on ADCALC, may be used to determine ADERR. See Table 32-6 for more details.

Bit 15 14 13 12 11 10 9 8

ADSTPTH[7:0]

Access R/W R/W R/W R/W R/W R/W R/W R/W

Reset 0 0 0 0 0 0 0 0

Bit 7 6 5 4 3 2 1 0

ADSTPTL[7:0]

Access R/W R/W R/W R/W R/W R/W R/W R/W

Reset 0 0 0 0 0 0 0 0

Bits 15:8 – ADSTPTH[7:0]

ADC Threshold Setpoint Most Significant Byte.

Bits 7:0 – ADSTPTL[7:0]

ADC Threshold Setpoint Least Significant Byte.

PIC18F26/45/46Q10

(ADC2) Analog-to-Digital Converter with Comp...

32.7.19 ADERR

Name: ADERR

Address: 0xF69

ADC Setpoint Error Register. ADC Setpoint Error calculation is determined by the ADCALC bits.

Bit 15 14 13 12 11 10 9 8

ADERRH[7:0]

Access RO RO RO RO RO RO RO RO

Reset 0 0 0 0 0 0 0 0

Bit 7 6 5 4 3 2 1 0

ADERRL[7:0]

Access RO RO RO RO RO RO RO RO

Reset 0 0 0 0 0 0 0 0

Bits 15:8 – ADERRH[7:0]

ADC Setpoint Error MSB

Bits 7:0 – ADERRL[7:0]

ADC Setpoint Error LSB

PIC18F26/45/46Q10

(ADC2) Analog-to-Digital Converter with Comp...

32.7.20 ADLTH

Name: ADLTH

Address: 0xF65

ADC Lower Threshold Register

ADLTH and ADUTH are compared with ADERR to set the ADUTHR and ADLTHR bits of ADSTAT.

Depending on the setting of ADTMD, an interrupt may be triggered by the results of this comparison.

Bit 15 14 13 12 11 10 9 8

ADLTHH[7:0]

Access R/W R/W R/W R/W R/W R/W R/W R/W

Reset 0 0 0 0 0 0 0 0

Bit 7 6 5 4 3 2 1 0

ADLTHL[7:0]

Access R/W R/W R/W R/W R/W R/W R/W R/W

Reset 0 0 0 0 0 0 0 0

Bits 15:8 – ADLTHH[7:0] ADC Lower Threshold MSB

Bits 7:0 – ADLTHL[7:0] ADC Lower Threshold LSB

PIC18F26/45/46Q10

(ADC2) Analog-to-Digital Converter with Comp...

32.7.21 ADUTH

Name: ADUTH

Address: 0xF67

ADC Upper Threshold Register

ADLTH and ADUTH are compared with ADERR to set the ADUTHR and ADLTHR bits of ADSTAT.

Depending on the setting of ADTMD, an interrupt may be triggered by the results of this comparison.

Bit 15 14 13 12 11 10 9 8

ADUTHH[7:0]

Access R/W R/W R/W R/W R/W R/W R/W R/W

Reset 0 0 0 0 0 0 0 0

Bit 7 6 5 4 3 2 1 0

ADUTHL[7:0]

Access R/W R/W R/W R/W R/W R/W R/W R/W

Reset 0 0 0 0 0 0 0 0

Bits 15:8 – ADUTHH[7:0] ADC Upper Threshold MSB

Bits 7:0 – ADUTHL[7:0] ADC Upper Threshold LSB

PIC18F26/45/46Q10

(ADC2) Analog-to-Digital Converter with Comp...

32.7.22 ADACT

Name: ADACT

Address: 0xF51

ADC AUTO Conversion Trigger Source Selection Register

Bit 7 6 5 4 3 2 1 0

ADACT[4:0]

Access R/W R/W R/W R/W R/W

Reset 0 0 0 0 0

Bits 4:0 – ADACT[4:0] Auto-Conversion Trigger Select Bits

Value Description

00000

to

11111

See Auto-Conversion Trigger Sources table.

PIC18F26/45/46Q10

(ADC2) Analog-to-Digital Converter with Comp...

33. (CMP) Comparator Module

Comparators are used to interface analog circuits to a digital circuit by comparing two analog voltages

and providing a digital indication of their relative magnitudes. Comparators are very useful mixed-signal

building blocks because they provide analog functionality independent of program execution. The

PIC18F26/45/46Q10 devices have two comparators (C1/C2).

The analog comparator module includes the following features:

• Programmable Input Selection

• Programmable Output Polarity

• Rising/Falling Output Edge Interrupts

• Wake-up from Sleep

• CWG Auto-shutdown Source

• Selectable Voltage Reference

• ADC Auto-Trigger

• Odd Numbered Timers (Timer1, Timer3, etc.) Gate

• Even Numbered Timers (Timer2, Timer4, etc.) Reset

• CCP Capture Mode Input

• DSM Modulator Source

• Input and Window Signal-to-Signal Measurement Timer

33.1 Comparator Overview

A single comparator is shown in Figure 33-1 along with the relationship between the analog input levels

and the digital output. When the analog voltage at VIN+ is less than the analog voltage at VIN-, the output

of the comparator is a digital low level. When the analog voltage at VIN+ is greater than the analog

voltage at VIN-, the output of the comparator is a digital high level.

Figure 33-1. Single Comparator

–

+

VIN+

VIN- Output

Output

VIN+

VIN-

Rev. 30-000125A

5/17/2017

Note:

1. The black areas of the output of the comparator represent the uncertainty due to input offsets and

response time.

PIC18F26/45/46Q10

(CMP) Comparator Module

Figure 33-2. Comparator Module Simplified Block Diagram

Rev. 10-000027R

7/19/2017

+

PCH

NCH

EN(1)

HYS

Interrupt

Rising

Edge

D Q

Q1

INTP

INTN

Cx_out

CMxCON0.OUT

CMOUT.MCxOUT

D Q

0

1

SYNC

set bit

CxIF

TRIS bit

CxOUT

CxOUT_sync

-

Interrupt

Falling

Edge

POL

Cx

(From Timer1 Module) T1CLK

To Other

Peripherals

Note 1: When EN = 0, all multiplexer inputs are disconnected and the Comparator will produce a ‘0’ at the output.

PPS

RxyPPS

CxVP

CxVN

See CMxNCH

Register

See CMxPCH

Register

Related Links

33.15.3 CMxNCH

33.15.4 CMxPCH

33.2 Comparator Control

Each comparator has two control registers: CMxCON0 and CMxCON1.

The CMxCON0 register contains Control and Status bits for the following:

• Enable

• Output

• Output Polarity

• Hysteresis Enable

• Timer1 Output Synchronization

The CMxCON1 register contains Control bits for the following:

• Interrupt on Positive/Negative Edge Enables

• Positive Input Channel Selection

• Negative Input Channel Selection

33.2.1 Comparator Enable

Setting the EN bit enables the comparator for operation. Clearing the CxEN bit disables the comparator,

resulting in minimum current consumption.

PIC18F26/45/46Q10

(CMP) Comparator Module

33.2.2 Comparator Output

The output of the comparator can be monitored by reading either the CxOUT bit or the MCxOUT bit.

The comparator output can also be routed to an external pin through the RxyPPS register. The

corresponding TRIS bit must be clear to enable the pin as an output.

Note:

1. The internal output of the comparator is latched with each instruction cycle. Unless otherwise

specified, external outputs are not latched.

Related Links

17.9.2 RxyPPS

33.2.3 Comparator Output Polarity

Inverting the output of the comparator is functionally equivalent to swapping the comparator inputs. The

polarity of the comparator output can be inverted by setting the CxPOL bit. Clearing the CxPOL bit results

in a non-inverted output.

Table 33-1 shows the output state versus input conditions, including polarity control.

Table 33-1. Comparator Output State vs. Input Conditions

Input Condition CxPOL CxOUT

CxVn > CxVp 0 0

CxVn < CxVp 0 1

CxVn > CxVp 1 1

CxVn < CxVp 1 0

33.3 Comparator Hysteresis

A selectable amount of separation voltage can be added to the input pins of each comparator to provide a

hysteresis function to the overall operation. Hysteresis is enabled by setting the CxHYS bit.

See Comparator Specifications for more information.

Related Links

39.4.9 Comparator Specifications

33.4 Operation With Timer1 Gate

The output resulting from a comparator operation can be used as a source for gate control of the odd

numbered timers (Timer1, Timer3, etc.). See the timer gate section for more information. This feature is

useful for timing the duration or interval of an analog event.

It is recommended that the comparator output be synchronized to the timer by setting the SYNC bit. This

ensures that the timer does not increment while a change in the comparator is occurring. However,

synchronization is only possible with the Timer1 clock source. Synchronization with the other odd

numbered timers is only possible when they use the same clock source as Timer1.

Related Links

19.7 Timer1 Gate

PIC18F26/45/46Q10

(CMP) Comparator Module

33.4.1 Comparator Output Synchronization

The output from a comparator can be synchronized with Timer1 by setting the SYNC bit.

Once enabled, the comparator output is latched on the falling edge of the Timer1 source clock. If a

prescaler is used with Timer1, the comparator output is latched after the prescaling function. To prevent a

race condition, the comparator output is latched on the falling edge of the Timer1 clock source and

Timer1 increments on the rising edge of its clock source. See the Figure 33-2 Comparator Block Diagram

and the Timer1 Block Diagram for more information.

Related Links

19. Timer1 Module with Gate Control

33.5 Comparator Interrupt

An interrupt can be generated upon a change in the output value of the comparator for each comparator;

a rising edge detector and a falling edge detector are present.

When either edge detector is triggered and its associated enable bit is set (CxINTP and/or CxINTN bits),

the Corresponding Interrupt Flag bit (CxIF bit of the PIR2 register) will be set.

To enable the interrupt, the following bits must be set:

•EN and POL bits

• CxIE bit of the PIE2 register

•INTP bit (for a rising edge detection)

•INTN bit (for a falling edge detection)

• PEIE and GIE bits of the INTCON register

The associated interrupt flag bit, CxIF bit of the PIR2 register, must be cleared in software. If another

edge is detected while this flag is being cleared, the flag will still be set at the end of the sequence.

Important: Although a comparator is disabled, an interrupt can be generated by changing the

output polarity with the CxPOL bit, or by switching the comparator on or off with the CxEN bit.

33.6 Comparator Positive Input Selection

Configuring the PCH bits direct an internal voltage reference or an analog pin to the non-inverting input of

the comparator:

PCH Positive Input Source

111 AVSS

110 FVR_Buffer2

101 DAC_Output

100 CxPCH not connected

011 CxPCH not connected

010 CxPCH not connected

PIC18F26/45/46Q10

(CMP) Comparator Module

...........continued

PCH Positive Input Source

001 CxIN1+

000 CxIN0+

Important: To use CxINy+ pins as analog input, the appropriate bits must be set in the ANSEL

register and the corresponding TRIS bits must also be set to disable the output drivers.

See Fixed Voltage Reference (FVR) for more information on the Fixed Voltage Reference module.

See 5-Bit Digital-to-Analog Converter (DAC) module for more information on the DAC input signal.

Any time the comparator is disabled (CxEN = 0), all comparator inputs are disabled.

Related Links

29. (FVR) Fixed Voltage Reference

31. (DAC) 5-Bit Digital-to-Analog Converter Module

33.7 Comparator Negative Input Selection

The NCH bits direct an analog input pin and internal reference voltage or analog ground to the inverting

input of the comparator:

NCH Negative Input Sources

111 AVSS

110 FVR_Buffer2

101 CxNCH not connected

100 CxNCH not connected

011 CxIN3-

010 CxIN2-

001 CxIN1-

000 CxIN0-

Important: To use CxINy- pins as analog input, the appropriate bits must be set in the ANSEL

register and the corresponding TRIS bits must also be set to disable the output drivers.

33.8 Comparator Response Time

The comparator output is indeterminate for a period of time after the change of an input source or the

selection of a new reference voltage. This period is referred to as the response time. The response time

of the comparator differs from the settling time of the voltage reference. Therefore, both of these times

PIC18F26/45/46Q10

(CMP) Comparator Module

must be considered when determining the total response time to a comparator input change. See the

Comparator and Voltage Reference Specifications in Comparator Specifications and Fixed Voltage

Reference (FVR) Specifications for more details.

Related Links

39.4.9 Comparator Specifications

39.4.11 Fixed Voltage Reference (FVR) Specifications

33.9 Analog Input Connection Considerations

A simplified circuit for an analog input is shown in Figure 33-3. Since the analog input pins share their

connection with a digital input, they have reverse biased ESD protection diodes to VDD and VSS. The

analog input, therefore, must be between VSS and VDD. If the input voltage deviates from this range by

more than 0.6V in either direction, one of the diodes is forward biased and a latch-up may occur.

A maximum source impedance of 10 kΩ is recommended for the analog sources. Also, any external

component connected to an analog input pin, such as a capacitor or a Zener diode, should have very little

leakage current to minimize inaccuracies introduced.

Note:

1. When reading a PORT register, all pins configured as analog inputs will read as a ‘0’. Pins

configured as digital inputs will convert as an analog input, according to the input specification.

2. Analog levels on any pin defined as a digital input, may cause the input buffer to consume more

current than is specified.

Figure 33-3. Analog Input Model

VA

RS< 10K

VDD

Analog

Input pin

CPIN

5pF VT≈0.6V

VT≈0.6V

ILEAKAGE(1)

VSS

RIC

To Comparator

Legend: CPIN = Input Capacitance

ILEAKAGE = Leakage Current at the pin due to various junctions

RIC = Interconnect Resistance

RS= Source Impedance

VA= Analog Voltage

VT= Threshold Voltage

Rev. 10-000071A

8/2/2013

Note: See Electrical Specifications chapter.

Related Links

39. Electrical Specifications

PIC18F26/45/46Q10

(CMP) Comparator Module

33.10 CWG1 Auto-Shutdown Source

The output of the comparator module can be used as an auto-shutdown source for the CWG1 module.

When the output of the comparator is active and the corresponding WGASxE is enabled, the CWG

operation will be suspended immediately.

Related Links

24.11.1.2 External Input Source

33.11 ADC Auto-Trigger Source

The output of the comparator module can be used to trigger an ADC conversion. When the ADACT

register is set to trigger on a comparator output, an ADC conversion will trigger when the comparator

output goes high.

33.12 Even Numbered Timers Reset

The output of the comparator module can be used to reset the even numbered timers (Timer2, Timer4,

etc.). When the TxERS register is appropriately set, the timer will reset when the comparator output goes

high.

33.13 Operation in Sleep Mode

The comparator module can operate during Sleep. The comparator clock source is based on the Timer1

clock source. If the Timer1 clock source is either the system clock (FOSC) or the instruction clock (FOSC/4),

Timer1 will not operate during Sleep, and synchronized comparator outputs will not operate.

A comparator interrupt will wake the device from Sleep. The CxIE bits of the PIEx register must be set to

enable comparator interrupts.

PIC18F26/45/46Q10

(CMP) Comparator Module

33.14 Register Summary - Comparator

Address Name Bit Pos.

0x0F30 CM2CON0 7:0 EN OUT POL HYS SYNC

0x0F31 CM2CON1 7:0 INTP INTN

0x0F32 CM2NCH 7:0 NCH[2:0]

0x0F33 CM2PCH 7:0 PCH[2:0]

0x0F34 CM1CON0 7:0 EN OUT POL HYS SYNC

0x0F35 CM1CON1 7:0 INTP INTN

0x0F36 CM1NCH 7:0 NCH[2:0]

0x0F37 CM1PCH 7:0 PCH[2:0]

0x0F38 CMOUT 7:0 MC2OUT MC1OUT

33.15 Register Definitions: Comparator Control

Long bit name prefixes for the comparator peripherals are shown in the table below. Refer to the "Long

Bit Names Section" for more information.

Table 33-2. Comparator Bit Name Prefixes

Peripheral Bit Name Prefix

C1 C1

C2 C2

Related Links

1.4.2.2 Long Bit Names

PIC18F26/45/46Q10

(CMP) Comparator Module

33.15.1 CMxCON0

Name: CMxCON0

Address: 0xF34,0xF30

Comparator x Control Register 0

Bit 7 6 5 4 3 2 1 0

EN OUT POL HYS SYNC

Access R/W RO R/W R/W R/W

Reset 0 0 0 0 0

Bit 7 – EN Comparator Enable bit

Value Description

1Comparator is enabled

0Comparator is disabled and consumes no active power

Bit 6 – OUT Comparator Output bit

Value Condition Description

1If POL = 0 (non-inverted polarity): CxVP > CxVN

0If POL = 0 (non-inverted polarity): CxVP < CxVN

1If POL = 1 (inverted polarity): CxVP < CxVN

0If POL = 1 (inverted polarity): CxVP > CxVN

Bit 4 – POL Comparator Output Polarity Select bit

Value Description

1Comparator output is inverted

0Comparator output is not inverted

Bit 1 – HYS Comparator Hysteresis Enable bit

Value Description

1Comparator hysteresis enabled

0Comparator hysteresis disabled

Bit 0 – SYNC Comparator Output Synchronous Mode bit

Output updated on the falling edge of prescaled Timer1 clock.

Value Description

1Comparator output to Timer1 and I/O pin is synchronous to changes on the prescaled

Timer1 clock.

0Comparator output to Timer1 and I/O pin is asynchronous

PIC18F26/45/46Q10

(CMP) Comparator Module

33.15.2 CMxCON1

Name: CMxCON1

Address: 0xF35,0xF31

Comparator x Control Register 1

Bit 7 6 5 4 3 2 1 0

INTP INTN

Access R/W R/W

Reset 0 0

Bit 1 – INTP Comparator Interrupt on Positive-Going Edge Enable bit

Value Description

1The CxIF interrupt flag will be set upon a positive-going edge of the CxOUT bit

0No interrupt flag will be set on a positive-going edge of the CxOUT bit

Bit 0 – INTN Comparator Interrupt on Negative-Going Edge Enable bit

Value Description

1The CxIF interrupt flag will be set upon a negative-going edge of the CxOUT bit

0No interrupt flag will be set on a negative-going edge of the CxOUT bit

PIC18F26/45/46Q10

(CMP) Comparator Module

33.15.3 CMxNCH

Name: CMxNCH

Address: 0xF36,0xF32

Comparator x Inverting Channel Select Register

Bit 7 6 5 4 3 2 1 0

NCH[2:0]

Access R/W R/W R/W

Reset 0 0 0

Bits 2:0 – NCH[2:0] Comparator Inverting Input Channel Select bits

NCH Negative Input Sources

111 AVSS

110 FVR_Buffer2

101 CxNCH not connected

100 CxNCH not connected

011 CxIN3-

010 CxIN2-

001 CxIN1-

000 CxIN0-

PIC18F26/45/46Q10

(CMP) Comparator Module

33.15.4 CMxPCH

Name: CMxPCH

Address: 0xF37,0xF33

Comparator x Non-Inverting Channel Select Register

PCH Positive Input Source

111 AVSS

110 FVR_Buffer2

101 DAC_Output

100 CxPCH not connected

011 CxPCH not connected

010 CxPCH not connected

001 CxIN1+

000 CxIN0+

Bit 7 6 5 4 3 2 1 0

PCH[2:0]

Access R/W R/W R/W

Reset 0 0 0

Bits 2:0 – PCH[2:0] Comparator Non-Inverting Input Channel Select bits

PIC18F26/45/46Q10

(CMP) Comparator Module

33.15.5 CMOUT

Name: CMOUT

Address: 0xF38

Comparator Output Register

Bit 7 6 5 4 3 2 1 0

MC2OUT MC1OUT

Access RO RO

Reset 0 0

Bits 0, 1 – MCxOUT Mirror copy of CxOUT bit

PIC18F26/45/46Q10

(CMP) Comparator Module

34. (HLVD) High/Low-Voltage Detect

The HLVD module can be configured to monitor the device voltage. This is useful in battery monitoring

applications.

Complete control of the HLVD module is provided through the HLVDCON0 and HLVDCON1 registers.

The module’s block diagram is shown in the figure below.

Figure 34-1. HLVD Module Block Diagram

Filename: 10-000256A.vsd

Title: HLVD MODULE BLOCK DIAGRAM (WITHOUT EXTERNAL INPUT)

Last Edit: 8/8/2018

First Used: 18(L)F2x/4xK40 (MFAE)

Notes:

Rev. 10-000256A

8/8/2018

HLVDSEL<3:0>

4

+

-

16-to-1 MUX

VDD

HLVDEN

Band gap

Reference

Volatge

Trigger/

Interrupt

Generation

HLVDINTH HLVDINTL

HLVDIF

HLVDRDY

HLVDOUT

Since the HLVD can be software enabled through the HLVDEN bit, setting and clearing the enable bit

does not produce a false HLVD event glitch. Each time the HLVD module is enabled, the RDY bit can be

used to detect when the module is stable and ready to use.

The INTH and INTL bits determine the overall operation of the module. When INTH is set, the module

monitors for rises in VDD above the trip point set by the bits. When INTL is set, the module monitors for

drops in VDD below the trip point set by the SEL bits. When both the INTH and INTL bits are set, any

changes above or below the trip point set by the SEL bits can be monitored.

The OUT bit can be read to determine if the voltage is greater than or less than the selected trip point.

34.1 Operation

When the HLVD module is enabled, a comparator uses an internally generated voltage reference as the

set point. The set point is compared with the trip point, where each node in the resistor divider represents

a trip point voltage. The “trip point” voltage is the voltage level at which the device detects a high or low-

voltage event, depending on the configuration of the module.

When the supply voltage is equal to the trip point, the voltage tapped off of the resistor array is equal to

the internal reference voltage generated by the voltage reference module. The comparator then

generates an interrupt signal by setting the HLVDIF bit.

PIC18F26/45/46Q10

(HLVD) High/Low-Voltage Detect

The trip point voltage is software programmable to any of 16 values. The trip point is selected by

programming the SEL bits.

34.2 Setup

To set up the HLVD module:

1. Select the desired HLVD trip point by writing the value to the SEL bits of the HLVDCON1 register.

2. Depending on the application to detect high-voltage peaks or low-voltage drops or both, set the

INTH or INTL bit appropriately.

3. Enable the HLVD module by setting the EN bit.

4. Clear the HLVD interrupt flag (HLVDIF), which may have been set from a previous interrupt.

5. If interrupts are desired, enable the HLVD interrupt by setting the HLVDIE and GIE bits.

An interrupt will not be generated until the RDY bit is set.

Important: Before changing any module settings (interrupts and tripping point), first

disable the module (EN = 0), make the changes and re-enable the module. This prevents

the generation of false HLVD events.

Related Links

14.13.4 PIR2

14.13.13 PIE3

34.3 Current Consumption

When the module is enabled, the HLVD comparator and voltage divider are enabled and consume static

current. The total current consumption, when enabled, is specified in electrical specification Parameter

D206.

Depending on the application, the HLVD module does not need to operate constantly. To reduce current

consumption, the module can be enabled for short periods where the voltage is checked. After such a

check, the module could be disabled.

Related Links

39.3.3 Power-Down Current (IPD)(1,2)

34.4 HLVD Start-up Time

If the HLVD or other circuits using the internal voltage reference are disabled to lower the device’s current

consumption, the reference voltage circuit will require time to become stable before a low or high-voltage

condition can be reliably detected. This start-up time, TFVRST, is an interval that is independent of device

clock speed. It is specified in electrical specification.

The HLVD interrupt flag is not enabled until TFVRST has expired and a stable reference voltage is reached.

For this reason, brief excursions beyond the set point may not be detected during this interval (see the

figures below).

PIC18F26/45/46Q10

(HLVD) High/Low-Voltage Detect

Figure 34-2. Low-Voltage Detect Operation (INTL = 1)

VHLVD

VDD

HLVDIF

VHLVD

VDD

Enable HLVD

TFVRST

HLVDIF may not be Set

Enable HLVD

HLVDIF

HLVDIF Cleared in Software

HLVDIF Cleared in Software,

CASE 1:

CASE 2:

HLVDIF Remains Set since HLVD Condition still Exists

TFVRST

Band Gap Reference Voltage is Stable

HLVDRDY

Rev. 30-000141A

5/26/2017

PIC18F26/45/46Q10

(HLVD) High/Low-Voltage Detect

Figure 34-3. High-Voltage Detect Operation (INTH = 1)

VHLVD

VDD

HLVDIF

VHLVD

VDD

Enable HLVD

TIRVST

HLVDIF may not be Set

Enable HLVD

HLVDIF

HLVDIF Cleared in Software

HLVDIF Cleared in Software,

CASE 1:

CASE 2:

HLVDIF Remains Set since HLVD Condition still Exists

TIRVST

HLVDRDY

Band Gap Reference Voltage is Stable

HLVDRDY

Rev. 30-000142A

5/26/2017

34.5 Applications

In many applications, it is desirable to detect a drop below, or rise above, a particular voltage threshold.

For example, the HLVD module could be periodically enabled to detect Universal Serial Bus (USB) attach

or detach. This assumes the device is powered by a lower voltage source than the USB when detached.

An attach would indicate a High-Voltage Detect from, for example, 3.3V to 5V (the voltage on USB) and

vice versa for a detach. This feature could save a design a few extra components and an attach signal

(input pin).

For general battery applications, the figure below shows a possible voltage curve. Over time, the device

voltage decreases. When the device voltage reaches voltage, Va, the HLVD logic generates an interrupt

at time, Ta. The interrupt could cause the execution of an Interrupt Service Routine (ISR), which would

allow the application to perform “housekeeping tasks” and a controlled shutdown before the device

voltage exits the valid operating range at TB. This would give the application a time window, represented

by the difference between TA and TB, to safely exit.

PIC18F26/45/46Q10

(HLVD) High/Low-Voltage Detect

Figure 34-4. Typical Low-Voltage Detect Application

Time

Voltage

VA

VB

TATB

VA= HLVD trip point

VB= Minimum valid device

o per at ing vol tage

Legend:

Rev. 30-000143A

5/26/2017

34.6 Operation During Sleep

When enabled, the HLVD circuitry continues to operate during Sleep. If the device voltage crosses the trip

point, the HLVDIF bit will be set and the device will wake-up from Sleep. Device execution will continue

from the interrupt vector address if interrupts have been globally enabled.

34.7 Operation During Idle and Doze Modes

In both Idle and Doze modes, the module is active and events are generated if peripheral is enabled.

34.8 Effects of a Reset

A device Reset forces all registers to their Reset state. This forces the HLVD module to be turned off.

PIC18F26/45/46Q10

(HLVD) High/Low-Voltage Detect

34.9 Register Summary - HLVD

Address Name Bit Pos.

0x0F2A HLVDCON0 7:0 EN OUT RDY INTH INTL

0x0F2B HLVDCON1 7:0 SEL[3:0]

34.10 Register Definitions: HLVD Control

Long bit name prefixes for the HLVD peripheral is shown in the following table. Refer to the "Long Bit

Names" section for more information.

Table 34-1. HLVD Long Bit Name Prefixes

Peripheral Bit Name Prefix

HLVD HLVD

Related Links

1.4.2.2 Long Bit Names

PIC18F26/45/46Q10

(HLVD) High/Low-Voltage Detect

34.10.1 HLVDCON0

Name: HLVDCON0

Address: 0xF2A

High/Low-Voltage Detect Control Register 0

Bit 7 6 5 4 3 2 1 0

EN OUT RDY INTH INTL

Access R/W RO RO R/W R/W

Reset 0 x x 0 0

Bit 7 – EN High/Low-voltage Detect Power Enable bit

Value Description

1Enables the HLVD module

0Disables the HLVD module

Bit 5 – OUT HLVD Comparator Output bit

Value Description

1Voltage ≤ selected detection limit (SEL)

0Voltage ≥ selected detection limit (SEL)

Bit 4 – RDY Band Gap Reference Voltages Stable Status Flag bit

Value Description

1Indicates HLVD Module is ready and output is stable

0Indicates HLVD Module is not ready

Bit 1 – INTH HLVD Positive going (High Voltage) Interrupt Enable

Value Description

1HLVDIF will be set when voltage ≥ selected detection limit (SEL)

0HLVDIF will not be set

Bit 0 – INTL HLVD Negative going (Low Voltage) Interrupt Enable

Value Description

1HLVDIF will be set when voltage ≤ selected detection limit (SEL)

0HLVDIF will not be set

PIC18F26/45/46Q10

(HLVD) High/Low-Voltage Detect

34.10.2 HLVDCON1

Name: HLVDCON1

Address: 0xF2B

Low-Voltage Detect Control Register 1

Bit 7 6 5 4 3 2 1 0

SEL[3:0]

Access R/W R/W R/W R/W

Reset 0 0 0 0

Bits 3:0 – SEL[3:0] High/Low-Voltage Detection Limit Selection bits

Table 34-2. HLVD Detection Limits

SEL Detection Limit

1111 Reserved

1110 to 0000 See High/Low-voltage detect characteristics

Reset States: POR/BOR = 0000

All other resets = uuuu

Related Links

39.4.6 High/Low-Voltage Detect Characteristics

PIC18F26/45/46Q10

(HLVD) High/Low-Voltage Detect

35. Register Summary

Address Name Bit Pos.

0x0E1F CLCIN0PPS 7:0 PORT[1:0] PIN[2:0]

0x0E20 CLCIN1PPS 7:0 PORT[1:0] PIN[2:0]

0x0E21 CLCIN2PPS 7:0 PORT[1:0] PIN[2:0]

0x0E22 CLCIN3PPS 7:0 PORT[1:0] PIN[2:0]

0x0E23 CLCIN4PPS 7:0 PORT[1:0] PIN[2:0]

0x0E24 CLCIN5PPS 7:0 PORT[1:0] PIN[2:0]

0x0E25 CLCIN6PPS 7:0 PORT[1:0] PIN[2:0]

0x0E26 CLCIN7PPS 7:0 PORT[1:0] PIN[2:0]

0x0E27 CLC1CON 7:0 EN OUT INTP INTN MODE[2:0]

0x0E28 CLC1POL 7:0 POL G4POL G3POL G2POL G1POL

0x0E29 CLC1SEL0 7:0 D1S[5:0]

0x0E2A CLC1SEL1 7:0 D2S[5:0]

0x0E2B CLC1SEL2 7:0 D3S[5:0]

0x0E2C CLC1SEL3 7:0 D4S[5:0]

0x0E2D CLC1GLS0 7:0 G1D4T G1D4N G1D3T G1D3N G1D2T G1D2N G1D1T G1D1N

0x0E2E CLC1GLS1 7:0 G2D4T G2D4N G2D3T G2D3N G2D2T G2D2N G2D1T G2D1N

0x0E2F CLC1GLS2 7:0 G3D4T G3D4N G3D3T G3D3N G3D2T G3D2N G3D1T G3D1N

0x0E30 CLC1GLS3 7:0 G4D4T G4D4N G4D3T G4D3N G4D2T G4D2N G4D1T G4D1N

0x0E31 CLC2CON 7:0 EN OUT INTP INTN MODE[2:0]

0x0E32 CLC2POL 7:0 POL G4POL G3POL G2POL G1POL

0x0E33 CLC2SEL0 7:0 D1S[5:0]

0x0E34 CLC2SEL1 7:0 D2S[5:0]

0x0E35 CLC2SEL2 7:0 D3S[5:0]

0x0E36 CLC2SEL3 7:0 D4S[5:0]

0x0E37 CLC2GLS0 7:0 G1D4T G1D4N G1D3T G1D3N G1D2T G1D2N G1D1T G1D1N

0x0E38 CLC2GLS1 7:0 G2D4T G2D4N G2D3T G2D3N G2D2T G2D2N G2D1T G2D1N

0x0E39 CLC2GLS2 7:0 G3D4T G3D4N G3D3T G3D3N G3D2T G3D2N G3D1T G3D1N

0x0E3A CLC2GLS3 7:0 G4D4T G4D4N G4D3T G4D3N G4D2T G4D2N G4D1T G4D1N

0x0E3B CLC3CON 7:0 EN OUT INTP INTN MODE[2:0]

0x0E3C CLC3POL 7:0 POL G4POL G3POL G2POL G1POL

0x0E3D CLC3SEL0 7:0 D1S[5:0]

0x0E3E CLC3SEL1 7:0 D2S[5:0]

0x0E3F CLC3SEL2 7:0 D3S[5:0]

0x0E40 CLC3SEL3 7:0 D4S[5:0]

0x0E41 CLC3GLS0 7:0 G1D4T G1D4N G1D3T G1D3N G1D2T G1D2N G1D1T G1D1N

0x0E42 CLC3GLS1 7:0 G2D4T G2D4N G2D3T G2D3N G2D2T G2D2N G2D1T G2D1N

0x0E43 CLC3GLS2 7:0 G3D4T G3D4N G3D3T G3D3N G3D2T G3D2N G3D1T G3D1N

0x0E44 CLC3GLS3 7:0 G4D4T G4D4N G4D3T G4D3N G4D2T G4D2N G4D1T G4D1N

0x0E45 CLC4CON 7:0 EN OUT INTP INTN MODE[2:0]

0x0E46 CLC4POL 7:0 POL G4POL G3POL G2POL G1POL

0x0E47 CLC4SEL0 7:0 D1S[5:0]

0x0E48 CLC4SEL1 7:0 D2S[5:0]

0x0E49 CLC4SEL2 7:0 D3S[5:0]

PIC18F26/45/46Q10

Register Summary

...........continued

Address Name Bit Pos.

0x0E4A CLC4SEL3 7:0 D4S[5:0]

0x0E4B CLC4GLS0 7:0 G1D4T G1D4N G1D3T G1D3N G1D2T G1D2N G1D1T G1D1N

0x0E4C CLC4GLS1 7:0 G2D4T G2D4N G2D3T G2D3N G2D2T G2D2N G2D1T G2D1N

0x0E4D CLC4GLS2 7:0 G3D4T G3D4N G3D3T G3D3N G3D2T G3D2N G3D1T G3D1N

0x0E4E CLC4GLS3 7:0 G4D4T G4D4N G4D3T G4D3N G4D2T G4D2N G4D1T G4D1N

0x0E4F CLC5CON 7:0 EN OUT INTP INTN MODE[2:0]

0x0E50 CLC5POL 7:0 POL G4POL G3POL G2POL G1POL

0x0E51 CLC5SEL0 7:0 D1S[5:0]

0x0E52 CLC5SEL1 7:0 D2S[5:0]

0x0E53 CLC5SEL2 7:0 D3S[5:0]

0x0E54 CLC5SEL3 7:0 D4S[5:0]

0x0E55 CLC5GLS0 7:0 G1D4T G1D4N G1D3T G1D3N G1D2T G1D2N G1D1T G1D1N

0x0E56 CLC5GLS1 7:0 G2D4T G2D4N G2D3T G2D3N G2D2T G2D2N G2D1T G2D1N

0x0E57 CLC5GLS2 7:0 G3D4T G3D4N G3D3T G3D3N G3D2T G3D2N G3D1T G3D1N

0x0E58 CLC5GLS3 7:0 G4D4T G4D4N G4D3T G4D3N G4D2T G4D2N G4D1T G4D1N

0x0E59 CLC6CON 7:0 EN OUT INTP INTN MODE[2:0]

0x0E5A CLC6POL 7:0 POL G4POL G3POL G2POL G1POL

0x0E5B CLC6SEL0 7:0 D1S[5:0]

0x0E5C CLC6SEL1 7:0 D2S[5:0]

0x0E5D CLC6SEL2 7:0 D3S[5:0]

0x0E5E CLC6SEL3 7:0 D4S[5:0]

0x0E5F CLC6GLS0 7:0 G1D4T G1D4N G1D3T G1D3N G1D2T G1D2N G1D1T G1D1N

0x0E60 CLC6GLS1 7:0 G2D4T G2D4N G2D3T G2D3N G2D2T G2D2N G2D1T G2D1N

0x0E61 CLC6GLS2 7:0 G3D4T G3D4N G3D3T G3D3N G3D2T G3D2N G3D1T G3D1N

0x0E62 CLC6GLS3 7:0 G4D4T G4D4N G4D3T G4D3N G4D2T G4D2N G4D1T G4D1N

0x0E63 CLC7CON 7:0 EN OUT INTP INTN MODE[2:0]

0x0E64 CLC7POL 7:0 POL G4POL G3POL G2POL G1POL

0x0E65 CLC7SEL0 7:0 D1S[5:0]

0x0E66 CLC7SEL1 7:0 D2S[5:0]

0x0E67 CLC7SEL2 7:0 D3S[5:0]

0x0E68 CLC7SEL3 7:0 D4S[5:0]

0x0E69 CLC7GLS0 7:0 G1D4T G1D4N G1D3T G1D3N G1D2T G1D2N G1D1T G1D1N

0x0E6A CLC7GLS1 7:0 G2D4T G2D4N G2D3T G2D3N G2D2T G2D2N G2D1T G2D1N

0x0E6B CLC7GLS2 7:0 G3D4T G3D4N G3D3T G3D3N G3D2T G3D2N G3D1T G3D1N

0x0E6C CLC7GLS3 7:0 G4D4T G4D4N G4D3T G4D3N G4D2T G4D2N G4D1T G4D1N

0x0E6D CLC8CON 7:0 EN OUT INTP INTN MODE[2:0]

0x0E6E CLC8POL 7:0 POL G4POL G3POL G2POL G1POL

0x0E6F CLC8SEL0 7:0 D1S[5:0]

0x0E70 CLC8SEL1 7:0 D2S[5:0]

0x0E71 CLC8SEL2 7:0 D3S[5:0]

0x0E72 CLC8SEL3 7:0 D4S[5:0]

0x0E73 CLC8GLS0 7:0 G1D4T G1D4N G1D3T G1D3N G1D2T G1D2N G1D1T G1D1N

0x0E74 CLC8GLS1 7:0 G2D4T G2D4N G2D3T G2D3N G2D2T G2D2N G2D1T G2D1N

0x0E75 CLC8GLS2 7:0 G3D4T G3D4N G3D3T G3D3N G3D2T G3D2N G3D1T G3D1N

0x0E76 CLC8GLS3 7:0 G4D4T G4D4N G4D3T G4D3N G4D2T G4D2N G4D1T G4D1N

PIC18F26/45/46Q10

Register Summary

...........continued

Address Name Bit Pos.

0x0E77 CLCDATA 7:0 MLC8OUT MLC7OUT MLC6OUT MLC5OUT MLC4OUT MLC3OUT MLC2OUT MLC1OUT

0x0E78