1
Motorola Small–Signal Transistors, FETs and Diodes Device Data
 
N–Channel — Enhancement
MAXIMUM RATINGS
Rating Symbol Value Unit
DrainSource Voltage VDS 60 Vdc
Gate–Source Voltage
— Continuous
— Non–repetitive (tp 50 µs) VGS
VGSM ±20
±40 Vdc
Vpk
Drain Current – Continuous(1)
– Pulsed(2) ID
IDM 0.5
1.0 Adc
Total Device Dissipation @ TA = 25°C
Derate above 25°C MPF910 PD1.0
8.0 Watts
mW/°C
Total Device Dissipation @ TC = 25°C
Derate above 25°C MFE910 PD6.25
50 Watts
mW/°C
Operating and Storage Junction
Temperature Range TJ, Tstg 65 to +150 °C
ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise noted)
Characteristic Symbol Min Typ Max Unit
OFF CHARACTERISTICS
Zero–Gate–Voltage Drain Current
(VDS = 40 V, VGS = 0) IDSS 0.1 10 µAdc
Gate Reverse Current
(VGS = 10 V, VDS = 0) IGSS 0.01 10 nAdc
Drain–Source Breakdown Voltage
(VGS = 0, ID = 100 µA) V(BR)DSS 60 90 Vdc
ON CHARACTERISTICS
Gate Threshold Voltage
(VDS = VGS, ID = 1.0 mA) VGS(th) 0.3 1.5 2.5 Vdc
Drain–Source On–V oltage
(VGS = 10 V, ID = 500 mA) VDS(on) 2.5 Vdc
On–State Drain Current
(VDS = 25 V, VGS = 10 V) ID(on) 500 mA
Forward T ransconductance
(VDS = 15 V, ID = 500 mA) gfs 100 mmhos
1. The Power Dissipation of the package may result in a lower continuous drain current.
2. Pulse Test: Pulse Width
v
300 µs, Duty Cycle
v
2.0%.
TMOS is a registered trademark of Motorola, Inc.
Order this document
by MPF910/D

SEMICONDUCTOR TECHNICAL DATA

CASE 29–05, STYLE 22
TO–92 (TO–226AE)
123
Motorola, Inc. 1997
3 DRAIN
1 SOURCE
2
GATE
REV 1
MPF910
2 Motorola Small–Signal Transistors, FETs and Diodes Device Data
Figure 1. Switching Test Circuit
20 dB
50
Attenuator
Pulse Generator
+25 V
Vin40 pF
1.0 M
50
23
50
Vout
To Sampling Scope
50
Input
Output V out
Inverted
Input Vin Pulse
Width
10%
90%
50%
50%
10%
90% 90%
10 v
toff
ton
Figure 2. Switching Waveforms
RESISTIVE SWITCHING
Figure 3. VGS(th) Normalized versus Temperature Figure 4. On–Region Characteristics
VDS = VGS
ID = 1.0 mA
2.0
1.6
1.2
0.8
0.4
0
, THRESHOLD VOLTAGE
–50 150 (
°
C)
050
100
TJ, JUNCTION TEMPERATURE
VGS(th)
VDS, DRAINSOURCE VOL TAGE (VOLTS)
, DRAIN CURRENT (AMPS)
D(on)
I
0.8
0.4
1.2
2.0
1.6
1.0 2.0 3.0 4.0
0
4.0 V
5.0 V
6.0 V
7.0 V
8.0 V
9.0 V
VGS = 10 V
MPF910
3
Motorola Small–Signal Transistors, FETs and Diodes Device Data
Figure 5. Output Characteristics Figure 6. Capacitance versus
Drain–to–Source Voltage
VDS, DRAINSOURCE VOL TAGE (VOLTS)
, DRAIN CURRENT (AMPS)
D(on)
I
0.8
0.4
1.2
1.6
2.0
010
20 30 VDS, DRAINSOURCE VOL TAGE (VOLTS)
C, CAPACITANCE (pF)
010 20 30 40 50
60
40
20
80
100
VGS = 10 V
5.0 V
4.0 V
6.0 V
7.0 V
8.0 V
9.0 V
40
VGS = 10 V
Ciss
Coss
Crss
60
Figure 7. On Voltage versus Temperature
VGS = 10 V ID = 1.5 A
1.0 A
10
5.0
1.0
0.5
0.2
0.1
, DRAIN–SOURCE VOLT AGE (VOLTS)
–50 –10 30 70 110 150
–30 10 50 90 130
TJ, JUNCTION TEMPERATURE
VDS
0.3
0.4
0.5 A
MPF910
4 Motorola Small–Signal Transistors, FETs and Diodes Device Data
PACKAGE DIMENSIONS
CASE 029–05
(TO–226AE)
ISSUE AD
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. CONTOUR OF PACKAGE BEYOND DIMENSION R
IS UNCONTROLLED.
4. DIMENSION F APPLIES BETWEEN P AND L.
DIMENSIONS D AND J APPLY BETWEEN L AND K
MIMIMUM. LEAD DIMENSION IS UNCONTROLLED
IN P AND BEYOND DIMENSION K MINIMUM.
R
A
PL
F
B
K
G
H
C
V
N
N
XX
SEATING
PLANE
1
J
SECTION X–X
D
DIM MIN MAX MIN MAX
MILLIMETERSINCHES
A0.175 0.205 4.44 5.21
B0.290 0.310 7.37 7.87
C0.125 0.165 3.18 4.19
D0.018 0.022 0.46 0.56
F0.016 0.019 0.41 0.48
G0.045 0.055 1.15 1.39
H0.095 0.105 2.42 2.66
J0.018 0.024 0.46 0.61
K0.500 ––– 12.70 –––
L0.250 ––– 6.35 –––
N0.080 0.105 2.04 2.66
P––– 0.100 ––– 2.54
R0.135 ––– 3.43 –––
V0.135 ––– 3.43 –––
23
STYLE 22:
PIN 1. SOURCE
2. GATE
3. DRAIN
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MPF910/D