512Mb LPDDR SDRAM
NT6DM32M16AD / NT6DM16M32AC
32
REV 1.4
12/ 2012 Nanya Technology, Inc., reserves the right to change products or
specifications without notices. 2012 NTC. All rights reserve
Burst Length, Type, and Order
Accesses within a given burst may be programmed to sequential or interleaved order. The burst type is selected via bit A3 as above
figure. The ordering of access within a burst is determined by the burst length, burst type, and the starting column address. The burst
length determines the maximum number of column locations that can be accessed for a given READ or WRITE command. The burst
length is defined by bits A0-A2. Burst length options include 2, 4, 8 or 16 for both the sequential and the interleaved burst types.
When a READ or WRITE command is issued, a block of columns equal to the BL is effectively selected. All accesses for that burst
take place within this block, meaning that the burst will wrap when a boundary is reached. The block is uniquely selected by A1–Ai
when BL = 2, by A2–Ai when BL = 4, by A3–Ai when BL = 8, and by A4–Ai when BL = 16, where Ai is the most significant column
address bit for a given configuration. The remaining (least significant) address bits are used to specify the starting location within the
block. The programmed BL applies to both READ and WRITE bursts. Accesses within a given burst may be programmed to be either
sequential or interleaved via the standard mode register.
Burst Type and Burst Order
Starting Column Address
(A3, A2,A1,A0)
Burst type = Sequential
A3 = 0
Burst type = Interleaved
A3 = 1
0000 0,1,2,3,4,5,6,7 0,1,2,3,4,5,6,7
0001 1,2,3,4,5,6,7,0 1,0,3,2,5,4,7,6
0010 2,3,4,5,6,7,0,1 2,3,0,1,6,7,4,5
0011 3,4,5,6,7,0,1,2 3,2,1,0,7,6,5,4
0100 4,5,6,7,0,1,2,3 4,5,6,7,0,1,2,3
0101 5,6,7,0,1,2,3,4 5,4,7,6,1,0,3,2
0110 6,7,0,1,2,3,4,5 6,7,4,5,2,3,0,1
0111 7,0,1,2,3,4,5,6 7,6,5,4,3,2,1,0
0000 0,1,2,3,4,5,6,7,8,9,A,B,C,D,E,F 0,1,2,3,4,5,6,7,8,9,A,B,C,D,E,F
0001 1,2,3,4,5,6,7,8,9,A,B,C,D,E,F,0 1,0,3,2,5,4,7,6,9,8,B,A,D,C,F,E
0010 2,3,4,5,6,7,8,9,A,B,C,D,E,F,0,1 2,3,0,1,6,7,4,5,A,B,8,9,E,F,C,D
0011 3,4,5,6,7,8,9,A,B,C,D,E,F,0,1,2 3,2,1,0,7,6,5,4,B,A,9,8,F,E,D,C
0100 4,5,6,7,8,9,A,B,C,D,E,F,0,1,2,3 4,5,6,7,0,1,2,3,C,D,E,F,8,9,A,B
0101 5,6,7,8,9,A,B,C,D,E,F,0,1,2,3,4 5,4,7,6,1,0,3,2,D,C,F,E,9,8,B,A
0110 6,7,8,9,A,B,C,D,E,F,0,1,2,3,4,5 6,7,4,5,2,3,0,1,E,F,C,D,A,B,8,9
0111 7,8,9,A,B,C,D,E,F,0,1,2,3,4,5,6 7,6,5,4,3,2,1,0,F,E,D,C,B,A,9,8
1000 8,9,A,B,C,D,E,F,0,1,2,3,4,5,6,7 8,9,A,B,C,D,E,F,0,1,2,3,4,5,6,7
1001 9,A,B,C,D,E,F,0,1,2,3,4,5,6,7,8 9,8,B,A,D,C,F,E,1,0,3,2,5,4,7,6
1010 A,B,C,D,E,F,0,1,2,3,4,5,6,7,8,9 A,B,8,9,E,F,C,D,2,3,0,1,6,7,4,5
1011 B,C,D,E,F,0,1,2,3,4,5,6,7,8,9,A B,A,9,8,F,E,D,C,3,2,1,0,7,6,5,4
1100 C,D,E,F,0,1,2,3,4,5,6,7,8,9,A,B C,D,E,F,8,9,A,B,4,5,6,7,0,1,2,3
1101 D,E,F,0,1,2,3,4,5,6,7,8,9,A,B,C D,C,F,E,,9,8,B,A,5,4,7,6,1,0,3,2
1110 E,F,0,1,2,3,4,5,6,7,8,9,A,B,C,D E,F,C,D,A,B,8,9,6,7,4,5,2,3,0,1
1111 F,0,1,2,3,4,5,6,7,8,9,A,B,C,D,E F,E,D,C,B,A,9,8,7,6,5,4,3,2,1,0
CAS Latency (CL)
The CAS Latency, or READ latency is the delay, in clock cycles, between the registration of a Read command and the availability of
the first bit of output data. CAS Latency is defined by bit A6~A4 in the standard mode register. If a READ command is registered at a
clock edge n, and the CAS latency is 3 clocks, the first data element will be valid at (n + 2tCK + tAC). If a READ command is
registered at a clock edge n, and the CAS latency is 2 clocks, the first data element will be valid at (n + 1tCK + tAC).