M58BW016FB7T3T - Micron Technology Inc.

July 2011 Rev 18 1/70

M58BW016DB M58BW016DT

M58BW016FT M58BW016FB

16 Mbit (512 Kbit x 32, bo ot block, burst)

3 V supply Flash memories

Features



Supply voltage

–V

= 2.7 V to 3.6 V for program, erase

and read

–V

DDQ

= V

DDQIN

= 2.4 V to 3.6 V for I/O

buffers

–V

= 12 V for fast program (optional)



High pe rf ormance

– Access times: 70, 80 ns

– 5 6 M Hz effect ive zer o wait-state burst re ad

– Synchronous burst read

– Asynchronous page read



Hardware block protection

–WP

pin for write protect of the 2 outermost

parameter blocks and all main blocks

–RP

pin for write protect of all blocks



Optimi z ed for FDI dr i v er s

– Fast program / erase suspend latency

time < 6 µs

– Com mon Flash interf ace



Memory blocks

– 8 parame t ers b locks (top or bottom)

– 31 main blocks



Low power con sumption

– 5 µ A typical deep power-down

– 60 µ A typical standby for M58BW0 16DT/B

150 µ A typical standb y for M58 B W016FT/B

– Aut om atic standb y aft er asynchrono us

read



Electronic signature

– Manufacturer code: 20h

– Top device code: 8836h

– Bottom device code: 8835h



100 K writ e/erase cycling + 20 years da ta

retention (minimum)



High reliability level with over 1 M write/e r ase

cycling sustained



RoHS packages av ailable

PQF P80 (T)

LBGA80 10 × 12 mm

LBGA

www.numonyx.com

Content s M58BW016DT, M58BW01 6D B, M58B W01 6FT, M58BW016 FB
2/70   
Contents
1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1.1 Block protection  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
2 Signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.1 Address inputs (A0-A18)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  14
2.2 Data inputs/outputs (DQ0-DQ31) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  14
2.3 Chip Enable (E)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  14
2.4 Output Enable (G)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  14
2.5 Output Disable (GD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.6 Write Enable (W)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  15
2.7 Reset/Power-down (RP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  15
2.8 Latch Enable (L) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  15
2.9 Burst Clock (K) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  16
2.10 Burst Address Advance (B)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  16
2.11 Valid Data Ready (R )  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  16
2.12 Write Protect (WP)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  16
2.13 Supply voltage (V
DD) . . . . . . . . . .  . . . . . . . . . .  . . . . . . . . . . .  . . . . . . . . . . .  . . . . . . . . . . 16
2.14 Output supply voltage (V
DDQ
)   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  17
2.15 Input supply voltage (V
DDQIN
)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.16 Program/erase supply voltage (V
PP
)  . . . . . . . . . . . . . . . . . . . . . . . . . . . .  17
2.17 Ground (V
SS
 and V
SSQ
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  17
2.18 Don’t use (DU)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  17
2.19 Not connected (NC)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  17
3 Bus operations  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.1 Asynchronous bus operations  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  18
3.1.1 Asynchronous bus read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.1.2 Asynchronous latch controlled bus read  . . . . . . . . . . . . . . . . . . . . . . . . 18
3.1.3 Asynchronous page read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.1.4 Asynchronous bus write  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.1.5 Asynchronous latch controlled bus write  . . . . . . . . . . . . . . . . . . . . . . . . 19
3.1.6 Output Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

M58BW016DT, M58BW016DB, M58BW016FT, M58BW016FB Contents
 3/70
1.7 Standby mode  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
1.8 Automatic low power mode  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
1.9 Power-down mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
1.10 Electronic signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2 Synchronous bus operations  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  21
2.1 Synchronous burst read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
2.2 Synchronous burst read suspend  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3 Burst configuration register   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  23
3.1 Read select bit (M15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.2 X-Latency bits (M14-M11)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.3 Y-Latency bit (M9)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.4 Valid data ready bit (M8)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.5 Burst type bit (M7)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.6 Valid clock edge bit (M6)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.7 Wrap burst bit (M3)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.8 Burst length bit (M2-M0)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Command interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
1 Read Memory Array command   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  28
2 Read Electronic Signature command . . . . . . . . . . . . . . . . . . . . . . . . . . . .  28
3 Read Query command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  28
4 Read Status Register command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  29
5 Clear Status Register command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  29
6 Block Erase command  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  30
7 Program command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  30
8 Program/Erase Suspend command . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  31
9 Program/Erase Resume command  . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  31
10 Set Burst Configuration Register command . . . . . . . . . . . . . . . . . . . . . . .  32
Status register  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
1 Program/erase controller status (bit 7) . . . . . . . . . . . . . . . . . . . . . . . . . . .  34
2 Erase suspend status (bit 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  34
3 Erase status (bit 5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  35
4 Program status (bit 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  35
5 V
PP
 status (bit 3)   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  35

Content s M58BW016DT, M58BW01 6D B, M58B W01 6FT, M58BW016 FB

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5.6 Program suspend status (bit 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

5.7 Block protection status (bit 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

6 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

7 DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

8 Package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

9 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Appendix A Common Flash interface (CFI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Appendix B Flowcharts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

10 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

M58BW016DT, M58BW016DB, M58BW016FT, M58BW016FB List of tables
 5/70
List of tables
Table 1. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Table 2. M58BW016DT and M58BW016FT top boot block addresses . . . . . . . . . . . . . . . . . . . . . . 12
Table 3. M58BW016DB and M58BW016FB bottom boot block addresses  . . . . . . . . . . . . . . . . . . . 13
Table 4. Asynchronous bus operations  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 5. Asynchronous read electronic signature operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 6. Synchronous burst read bus operations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 7. Burst configuration register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 8. Burst type definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 9. C om mands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 10. Program, erase  times and program, erase endurance cycl es . . . . . . . . . . . . . . . . . . . . . . 33
Table 11. Status register bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 12. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Table 13. Operating and AC measurement conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Table 14. Device capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Table 15. DC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Table 16. Asynchronous bus read AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Table  17. Asynchronous latc h controll ed bus read AC characteristics. . . . . . . . . . . . . . . . . . . . . . . . 42
Table 18. Asynchronous page read AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Table 19. Asynchronous write and latch controlled write AC characteristics . . . . . . . . . . . . . . . . . . . 46
Table 20. Synchronous burst read AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Table 21. Power supply AC and DC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Table 22. Reset, power-down and power-up AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Table 23. PQFP80 - 80 lead plastic quad flat pack, package mechanical data . . . . . . . . . . . . . . . . . 53
Table  24. LBGA80 10 × 1 2 mm - 8 × 10  active ball  array, 1 mm pit ch, package  m echanical data  . . 5 4
Table 25. Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Table 26. Query structure overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  56
Table 27. CFI - query address and data output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Table 28. CFI - device voltage and timing specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Table 29. Device geometry definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Table 30. Extended query information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Table 31. Document revision history  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

List of figures M58BW016DT, M58BW016DB, M58BW016FT, M58BW016FB
6/70   
List of figures
Figure 1. Logic diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 2. PQFP connections (top view through package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 3. LBGA connections (top view through package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 4. Example burst configuration X-1-1-1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 5. Example burst configuration X-2-2-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 6. AC measurement input/output waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Figure 7. AC measurement load circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Figure 8. Asynchronous bus re ad AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Figure 9. Asynch ronous latc h controlled bus read AC waveform s. . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Figure 10. Asynchronous page read AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Figure 11. Asynchronous write AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Figure 12. Asynchronous latch controlled write AC waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Figure 13. Synchronous burst read (data valid from ‘n’ clock rising edge) . . . . . . . . . . . . . . . . . . . . . 47
Figure 14. Synchronous burst read (data valid from ‘n’ clock rising edge) . . . . . . . . . . . . . . . . . . . . . 48
Figure 15. Synchronou s  burst read - continuous - valid data ready output . . . . . . . . . . . . . . . . . . . . . 49
Figure 16. Synchronous burst read - burst address advance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Figure 17. Reset, power-down and power-up AC waveforms - control pins low . . . . . . . . . . . . . . . . . 50
Figure 18. Reset, power-down and power-up AC waveforms - control pins toggling  . . . . . . . . . . . . . 50
Figure 19. Power supply slope specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Figure 20. PQFP80 - 80 lead plastic quad flat pack, package outline. . . . . . . . . . . . . . . . . . . . . . . . . 52
Figure 21. LBGA80 10 × 12 mm  - 8 × 10 active ball array, 1 mm pitch, package outline . . . . . . . . . . 54
Figure 22. Program flowchart and pseudocode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Figure  23. Program su spend & resum e flowchart and ps eudocode . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Figure 24. Block erase flowchart and pseudocode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Figure 25. Erase suspend & resume flowchart and pseudocode  . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Figure  26. Po wer-up sequence fo llowed by synchronous burst read  . . . . . . . . . . . . . . . . . . . . . . . . . 63
Figure 27. Command interface and program/erase controller flowchart (a). . . . . . . . . . . . . . . . . . . . . 64
Figure 28. Command interface and program/erase controller flowchart (b). . . . . . . . . . . . . . . . . . . . . 65
Figure 29. Command interface and program/erase controller flowchart (c). . . . . . . . . . . . . . . . . . . . . 66
Figure 30. Command interface and program/erase controller flowchart (d). . . . . . . . . . . . . . . . . . . . . 67

Important Notes and Warnings

Micron Technology, Inc. ("Micron") reserves the right to make changes to information published in this

document, including without limitation specifications and product descriptions. This document

supersedes and replaces all information supplied prior to the publication hereof. You may not rely on any

information set forth in this document if you obtain the product described herein from any unauthorized

distributor or other source not authorized by Micron.

Automotive Applications. Products are not designed or intended for use in automotive applications

unless specifically designated by Micron as automotive-grade by their respective data sheets. Distributor

and customer/distributor shall assume the sole risk and liability for and shall indemnify and hold Micron

harmless against all claims, costs, damages, and expenses and reasonable attorneys' fees arising out of,

directly or indirectly, any claim of product liability, personal injury, death, or property damage resulting

directly or indirectly from any use of nonautomotive-grade products in automotive applications.

Customer/distributor shall ensure that the terms and conditions of sale between customer/distributor and

any customer of distributor/customer (1) state that Micron products are not designed or intended for use

in automotive applications unless specifically designated by Micron as automotive-grade by their

respective data sheets and (2) require such customer of distributor/customer to indemnify and hold

Micron harmless against all claims, costs, damages, and expenses and reasonable attorneys' fees

arising out of, directly or indirectly, any claim of product liability, personal injury, death, or property

damage resulting from any use of non-automotive-grade products in automotive applications.

Critical Applications. Products are not authorized for use in applications in which failure of the Micron

component could result, directly or indirectly in death, personal injury, or severe property or

environmental damage ("Critical Applications"). Customer must protect against death, personal injury,

and severe property and environmental damage by incorporating safety design measures into

customer's applications to ensure that failure of the Micron component will not result in such harms.

Should customer or distributor purchase, use, or sell any Micron component for any critical application,

customer and distributor shall indemnify and hold harmless Micron and its subsidiaries, subcontractors,

and affiliates and the directors, officers, and employees of each against all claims, costs, damages, and

expenses and reasonable attorneys' fees arising out of, directly or indirectly, any claim of product liability,

personal injury, or death arising in any way out of such critical application, whether or not Micron or its

subsidiaries, subcontractors, or affiliates were negligent in the design, manufacture, or warning of the

Micron product.

Customer Responsibility. Customers are responsible for the design, manufacture, and operation of

their systems, applications, and products using Micron products. ALL SEMICONDUCTOR PRODUCTS

HAVE INHERENT FAILURE RATES AND LIMITED USEFUL LIVES. IT IS THE CUSTOMER'S SOLE

RESPONSIBILITY TO DETERMINE WHETHER THE MICRON PRODUCT IS SUITABLE AND FIT FOR

THE CUSTOMER'S SYSTEM, APPLICATION, OR PRODUCT. Customers must ensure that adequate

design, manufacturing, and operating safeguards are included in customer's applications and products to

eliminate the risk that personal injury, death, or severe property or environmental damages will result

from failure of any semiconductor component.

Limited Warranty. In no event shall Micron be liable for any indirect, incidental, punitive, special or

consequential damages (including without limitation lost profits, lost savings, business interruption, costs

related to the removal or replacement of any products or rework charges) whether or not such damages

are based on tort, warranty, breach of contract or other legal theory, unless explicitly stated in a written

agreement executed by Micron's duly authorized representative.

M58BW016DT, M58BW016DB, M58BW016FT, M58BW016FB Description

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1 Description

The M 58BW016DT, M58BW016 DB, M58BW01 6FT and M58BW016FB are 16-Mbit non-

volatile Flash memories that can be era s ed electrically at the block level and programmed

in-system on a double-word basis using a 2.7 V to 3.6 V V

supply for the circuit and a

DDQ

supply down to 2.4 V for the i np ut and output buffers. Option ally a 12 V V

supply

can be used to provide fast program and erase for a limited time and number of

program/erase cycles.

The de vices support asynchronous (latch cont rolled an d page read) and synchronous b us

operations. The synchronous burst read interface allows a high data transfer rate controlled

by the burst clock, K, signal. It is capable of bursting fixed or unlimited lengths of data. The

burst type, latency and length can be configured and can be easily adapted to a large

variety of system clock frequencies and micro pro cessors. All writ es are asynchronous. On

power-up the memory defaults to read mode with an asynchronous bus.

The de vices have a boot bloc k architectu re with an array of 8 parameter b locks of 64 Kbits

each and 3 1 ma in blocks of 512 K bits each. In the M58BW016DT and M58 BW 01 6FT the

parameter blocks are located at the top of the address space whereas in the M58BW016DB

and M58BW016FB, they are located at the bottom.

Program and erase commands are written to the command interface of the memory. An on-

chip p rogra m/er a se cont roll er s impli fi es th e pr ocess of pr ogr ammi ng or era sing th e mem or y

by taking care of all of the special operations that are required to update the memory

conten ts . The end of a prog ram or erase op erati on can be detec ted and any er ror condi tions

identi fie d in the status register. The command set required to control the memory is

consistent with JEDEC standards.

Erase can be suspended in order to perform either read or program in any other block and

then resum ed. Progr a m ca n be suspend ed to re a d data in any other bl oc k and then

resumed . Each block can be programmed and erased over 10 0,000 cycles.

All blocks are protected during power-up.

The M58BW0 16DT, M58BW01 6DB, M58BW0 16FT and M58BW01 6FB feature tw o dif ferent

levels of block protection to avoid unwanted program/erase operations:



The WP pin offers an hardware protection on two of the parameter blocks and all of the

main blocks



All program or erase operatio ns are bloc ked when Reset, R P, is held Low. A

reset/power-down mode is entered when the RP input is Low. In this mode the power

consu m ption is lower than in the norm al standby m ode, the device is w r it e protec ted

and both the status and the burst configuration registers are cleared. A recovery time is

requir ed when the R P input goes High.

The memory is offered in a PQ FP80 (14 x 20 mm) and L BGA80 (10 × 12 m m ) package.

The m emories are supplied with all the bits erased (set to ’1’).

In th e present document, M58BW01 6DT, M58BW016DB, M58BW01 6F T and

M58 B W016FB will be referred to as M 58BW016 unless otherwise specified.

Description M58BW016DT, M58B W01 6D B, M58BW016FT , M58BW0 16 FB

8/70

Figure 1. Logic diagram

AI11201b

A0-A18

DQ0-DQ31

VDD

M58BW016DT

M58BW016DB

M58BW016FT

M58BW016FB

VSS

VDDQ

VPP

VSSQ

VDDQIN

M58BW016DT, M58BW016DB, M58BW016FT, M58BW016FB Description

9/70

Table 1. Signal names

Signal Description Direction

A0-A18 Address inputs Inputs

DQ0-DQ7 Data input/output, command input I /O

DQ8-DQ15 Data input/output, Burst Configuration Register I/O

DQ16-DQ31 Data input/output I/O

BBurst Address Advance Input

EChip Enable Input

GOutput Enable Input

K Burst Clock Input

LLatch Enable Input

R Valid Data R eady (open drain output) Output

RP Reset/Power-down Input

WWrite Enable Input

GD Output Disable Input

WP Write Protect Input

Supply voltage Supply

DDQ

Power supply for output buffers Supply

DDQIN

Power supply for input buffers only Supply

Optional supply voltage for fast program and fast

erase operations Supply

Ground –

SSQ

Input/output ground –

NC Not connected internally –

DU Don’t use as internally connected –

Description M58BW016DT, M58B W01 6D B, M58BW016FT , M58BW0 16 FB

10/70

Figure 2. PQFP co nn ections (top view through packag e)

AI11202b

VDDQ

DQ24

DQ25

DQ18

DQ17

DQ16

DQ19

DQ20

DQ21

DQ22

DQ23

VDDQ

DQ29

DQ26

DQ30

DQ31

DQ28

DQ27

A11

VSS

A12

A13

A14

A10

VSS

VDDQ

DQ7

DQ6

DQ13

DQ14

DQ15

DQ12

DQ11

DQ10

DQ9

VSSQ

DQ8

DQ2

DQ5

DQ0

A18

A16

A17

DQ3

DQ4

VSSQ

VPP

VDD

A15

DQ1

VDDQ

VSSQ

VDD

VDDQI

M58BW016DT

M58BW016DB

M58BW016FT

M58BW016FB

M58BW016DT, M58BW016DB, M58BW016FT, M58BW016FB Description

11/70

Figure 3. LBGA connections (top view through package)

1.1 Block protection

The M58BW016 featu re two different levels of bl ock protec t ion.



Write protect pin, WP - When WP is Low, V

all the lockable parameter blocks (two

upper ( to p) or lower (bott om)) and al l th e m ain blocks ar e protected. When WP is High

) all the lockable parameter blocks and all the main blocks are unp r otected



Reset/power-down pin, RP - If the device is held in reset mode (RP at V

), no

prog ram or eras e operat ions can be per f or m e d on any block.

Afte r a devi ce rese t the fir st tw o kinds of bl ock pr ot ection (W P, RP) can be co mbine d to give

a flexible block protection.

AI04151C

DQ24DQ7VSSQ

VDDQ

DQ26DQ4VDDQ

DQ29

VSS

DQ0DQ3D

NCA7A11A18A17C

A4A5A8

A13A16B

A3A6

VDD

VPP

VDD

A14A

87654321

DQ20DQ18DQ19DQ17DQ11DQ12DQ13

VDDQ

DQ23DQ8VDDQ

GDW

VDDQIN

DQ16RGLDQ14DQ15

A15 VSS

A12 A9

A10 NC

NC NC DQ31 DQ30

DQ2 DQ28

DQ6 DQ25 VSSQ

DQ10 DQ9 DQ21

DQ1 DQ27

DQ5 NC

DQ22

Description M58BW016DT, M58B W01 6D B, M58BW016FT , M58BW0 16 FB

12/70

Table 2. M58BW016DT and M58BW016FT top boot block addresses

# Size (Kbit) Address range

38 64 7F800h-7FFFFh

37 64 7F000h-7F7FFh

36 64 7E800h-7EFFFh

35 64 7E000h-7E7FFh

34 64 7D800h-7DFFFh

33 64 7D000h-7D7FFh

32 64 7C800h-7CFFFh

31 64 7C000h-7C7FFh

30 512 78000h-7BFFFh

29 512 74000h-77FFFh

28 512 70000h-73FFFh

27 512 6C000h-6FFFFh

26 512 68000h-6BFFFh

25 512 64000h-67FFFh

24 512 60000h-63FFFh

23 512 5C000h-5FFFFh

22 512 58000h-5BFFFh

21 512 54000h-57FFFh

20 512 50000h-53FFFh

19 512 4C000h-4FFFFh

18 512 48000h-4BFFFh

17 512 44000h-47FFFh

16 512 40000h-43FFFh

15 512 3C000h-3FFFFh

14 512 38000h-3BFFFh

13 512 34000h-37FFFh

12 512 30000h-33FFFh

11 512 2C000h-2FFFFh

10 512 28000h-2BFFFh

9 512 24000h-27FFFh

8 512 20000h-23FFFh

7 512 1C000h-1FFFFh

6 512 18000h-1BFFFh

5 512 14000h-17FFFh

4 512 10000h-13FFFh

3 512 0C000h-0FFFFh

2 512 08000h-0BFFFh

1 512 04000h-07FFFh

0 512 00000h-03FFFh

M58BW016DT, M58BW016DB, M58BW016FT, M58BW016FB Description

13/70

Table 3. M58BW016DB and M58BW016FB bottom boot block addresses

# Size (Kbit) Address range

38 512 7C000h-7FFFFh

37 512 78000h-7BFFFh

36 512 74000h-77FFFh

35 512 70000h-73FFFh

34 512 6C000h-6FFFFh

33 512 68000h-6BFFFh

32 512 64000h-67FFFh

31 512 60000h-63FFFh

30 512 5C000h-5FFFFh

29 512 58000h-5BFFFh

28 512 54000h-57FFFh

27 512 50000h-53FFFh

26 512 4C000h-4FFFFh

25 512 48000h-4BFFFh

24 512 44000h-47FFFh

23 512 40000h-43FFFh

22 512 3C000h-3FFFFh

21 512 38000h-3BFFFh

20 512 34000h-37FFFh

19 512 30000h-33FFFh

18 512 2C000h-2FFFFh

17 512 28000h-2BFFFh

16 512 24000h-27FFFh

15 512 20000h-23FFFh

14 512 1C000h-1FFFFh

13 512 18000h-1BFFFh

12 512 14000h-17FFFh

11 512 10000h-13FFFh

10 512 0C000h-0FFFFh

9 512 08000h-0BFFFh

8 512 04000h-07FFFh

7 64 03800h-03FFFh

6 64 03000h-037FFh

5 64 02800h-02FFFh

4 64 02000h-027FFh

3 64 01800h-01FFFh

2 64 01000h-017FFh

1 64 00800h-00FFFh

0 64 00000h-007FFh

Signal desc rip t ions M58BW016D T, M5 8B W01 6D B, M58B W01 6FT, M58BW016 FB

14/70

2 Signal descriptions

See Figure 1: Logic diagram, and Table 1: Signal names for a brief overview of the signals

connected to this device.

2.1 Address inputs (A0-A18)

The address inputs are used to select the cells to access in th e me mory array durin g b us

operations either to read or to program data . During bus write operations they control the

commands sent to the comm and interf ace of the progra m/erase cont roller. Chip Enable

must be Low when selecting the addresses.

The address inputs are latched on the rising edge of Latch Enable L or Burst Clock K,

which ever oc curs f irst, in a read op erat ion.The address inputs are latched on the rising edge

of Chip Enable, Write Enable or Latch Enable, whichever occurs first in a write operation.

The address latch is transparent when Latch Enable is Low, V

. The address is internally

latched in an erase or program operation.

2.2 Data inputs/outputs (DQ0-DQ31)

The data inputs/outputs output the data stored at the se lected address du ring a bus read

operation, or are used to input the data during a program operation. During bus write

operations they represent the commands sent to the command in terface of the

program/erase controller. When used to input data or write commands th ey are latched on

the risi ng edge of Write Enable or Chip Enable, whichever occurs first.

When Chip Enable and Output Enable are both Low, V

, and Output Disable is at V

IH,

the

data bus outputs data from the memory array, the electronic signature, the CFI info rmation

or th e contents of t he status register. Th e data bus is h igh impe dance when the device is

deselected with Chip Enable at V

, Output Enable at V

, Output Disable at V

Reset/Power-down at V

. The status register content is output on DQ0-DQ7 and DQ8-

DQ31 are at V

2.3 Chip Enable (E)

The Chip Enable, E, input act ivates the m em ory contro l logic, inp ut buffers, decoders and

sens e amplifiers. Chip Enable, E, at V

deselects the memory and reduces the power

consumption to the standby level.

2.4 Output Enable (G)

The O utput Ena ble, G, gates the outputs through the data output buffers during a read

operation, when Outp ut Disable GD is at V

. When Output Enable G is at V

, the outputs

are high impedance independently of Output Disable.

M58BW016DT, M58BW016DB, M58BW016FT, M58BW016FB Signal descriptions

15/70

2.5 Output Disable (GD)

The O utput Di sable, GD, deactivates the data output buffers. When Output Disable, GD, is

at V

, the outputs are driven by the Output Enable. When Output Disable, GD, is at V

, the

outputs are high impedance independently of Output Enable. The Output Disable pin must

be connected to an external pull-up resistor as there is no in ternal pu ll-up resis to r t o drive

the pin.

2.6 Write Enable (W)

The Write Enable, W, input controls writing to the command interface, Address inputs and

Data lat c hes. Both addresses and data can be latc hed on the rising edge of Write Enable

(also see Latc h Enable , L).

2.7 Reset/Power-down (RP)

The Reset/Power-down, RP, is used to apply a hardware reset to the memory. A hardware

reset is achieved by ho lding Reset/Power-down Low, V

, for at least t

PLPH

. Writing is

inhibited to protect data, the command interface and the program/erase controller are reset.

The status register information is cleared and power cons um ption is re duced to de ep

power-down level. The device acts as deselected , th at is the data ou t puts are high

impedance.

After Reset/Power-down goes High, V

, the memory will be ready for bus read operations

after a delay of t

PHEL

or bus write operations after t

PHWL

If Reset/Power-down goes Low, V

, during a Block Erase, or a Program the operation is

aborted, in a time of t

PLRH

maximum, and data is altered and may be corrupted.

During power-up power should be applied simultaneously to V

and V

DDQ(IN)

with RP held

at V

. When the supp lies are stab le RP is taken to V

. Output Enable, G, Chip Enable, E,

and Write Enable, W, should be held at V

during pow er-u p.

In an application, it is recommended to associate reset/power-down pin, RP, with the reset

signal of the microprocessor. Otherwise, if a reset operation occurs while the memory is

performing an erase or program operation, the memory may output the status register

information instead of being in itializ ed to the d efault as ynchronous random read.

See Table 22: Reset, power-down and power-up AC characteristics and Figure 17: Reset,

power-down and power-up AC waveforms - control pins low, for more details.

2.8 Latch Enable (L)

The bus interface can be configured t o latch the address inputs on th e rising edge of Lat ch

Enabl e, L, for asynchronous latch enable controlled read or write or synchronous burst read

opera tions. In s y nchronous bu r s t re ad oper ati on s the address is la tc he d on the activ e edge

of the Cloc k wh en Latch Enable is Low, V

. Once la tched, the addresses may change

without affecting the address used by the memory. When Latch Enable is Low , V

, the la tch

is transparent. Latch Enable, L, can remain at V

for asynch ronous rand om read an d writ e

operations.

Signal desc rip t ions M58BW016D T, M5 8B W01 6D B, M58B W01 6FT, M58BW016 FB

16/70

2.9 Burst Clock (K)

The Bu rst Clock, K, is used to synchronize the memory with the external bus during

synchronous burst read operations. Bus signals are latched on the active edge of the Clock.

The Clock can be configu red to have an acti ve rising or fa lling edge. In synch r onous burst

read mode the address is latched on the first active clock edge when Latch Enable is Low,

, or on the rising edge of Latch Enable, whiche ver occurs first.

During asynchronous bus operations the Clock is not used.

2.10 Burst Address Advance (B)

The Burst Address Advance, B, controls the adv a nc ing of the addre s s by t he in ter n al

address counter during synchronous burst read operations.

Burst Address Advance, B, is only sa m pled on the active clock edge of the C lock when the

X-latency time has expired. If Burst Address Advance is Low, V

, the int ernal addre ss

counter advances. If Burst Address Advance is High, V

, the internal address counter does

not ch ange; the same data re m ains on the data inputs/outp uts and Burst A ddress Advance

is not sampled until the Y-latency expires.

The Burst Address Advance, B, may be tied to V

2.11 Valid Data Ready (R)

The Va lid Data Ready output, R, is an open drain output that can be used, during

synch r onous burst read operations, t o identify if the memory is ready to output data or not.

The Valid Data Ready output can be configured to be active on the clock edge of the invalid

data read cycle or one cycle before. Valid Data Ready, at V

, indicates that new data is or

wil l be availa ble. When Valid Data Ready is Low, V

, the previous data out puts remain

active.

In all asynchronous operations, Valid Data Ready is high impedance. It may be tied to other

compo nents w ith the sam e V ali d Dat a Ready si gnal to c reate a uni que syst em Ready si gnal.

The Valid Data Ready output has an internal pull-up resistor of around 1 MΩ powere d from

DDQ

, designers should use an external pull-up resist or of t he correct val ue to meet th e

external timing requirements for Va lid Data Read y going to V

2.12 Write Protect (WP)

The Write Protect, WP, provides protection against program or erase operations. When

Write Protect, WP, is at V

the first two (in the bottom configuration) or last two (in the top

configur ation) parameter blocks and all main blocks are locked. When Write Prote ct WP is

at V

all the blo cks can be programmed or erased, if no other protection is use d.

2.13 Supply voltage (V

)

The supply voltag e, V

, is the core po wer supply. All internal circuits draw their cu rrent

from the V

pin, including the program/erase controller.

M58BW016DT, M58BW016DB, M58BW016FT, M58BW016FB Signal descriptions

17/70

2.14 Output supply voltage (V

DDQ

)

The output s upp ly vol tage, V

DDQ

, is the output buffer power supply for all operations (read,

program and erase) us ed for DQ0- DQ31 when used as ou tpu ts.

2.15 Input supply voltage (V

DDQIN

)

The input su pply voltage, V

DDIN

, is the power supply for all input signal. Input signals are: K, B,

L, W, GD, G, E , A0-A18 and D Q0-DQ31 , when used as inputs.

2.16 Program/erase supply voltage (V

)

The program/erase supply voltage, V

, is used for program and erase operations. The

memory norma lly execut es program and e rase operations at V

PP1

volt age level s. In a

manufacturing environment, programming may be speeded up by applying a higher voltage

level, V

PPH

, to the V

pin.

The voltage level V

PPH

may be applied for a total of 80 hours over a maximum of 1000

cycles. Stressing the device beyond these limits co uld damage the device.

2.17 Ground (V

and V

SSQ

)

The gro und V

is the r efere nce for the intern al supp ly vol tage V

. The gr ound V

SSQ

is the

referen c e fo r th e output an d input s up pl ies V

DDQ,

and V

DDQIN

. It is esse nti al to con nec t V

and V

SSQ

together.

Note: A 0.1 µF capacitor should be connected between the supply voltages, V

, V

DDQ

and V

DDIN

and the grounds, V

and V

SSQ

to decouple the current surges from the power supply. The

PCB track widt hs must be sufficient to carry the currents required during all operations of the

parts, see Table 15: DC characteristics, for maximum current supply req ui r ements.

2.18 Don’t use (DU)

This pin should not be used as it is internal ly connec ted. Its voltage level can be betwe en

and V

DDQ

or lea v e it unconnected.

2.19 Not connected (NC)

This pin is not physically connected to the device.

Bus oper at ion s M58BW016DT, M58B W01 6D B, M58BW016F T, M58BW0 16FB

18/70

3 Bus operations

Each bus operation that controls the memory is described in this section, see Table 4,

Table 5 and Table 6 Bus operations, for a summary. The bus operation is selected through

the burst configuration register; the bits in this register are described at the end of this

section.

On power-up or after a hardware reset the memory defaults to asynchronous bus read and

asynchronous bus write, no other bus operation can be performed until the burst control

The electronic signature, CFI or status register will be read in asynchronous mode

regard less of the burst control register settings.

Typically glitches of less than 5 ns on C hip Enable or Write Enable are ignored by the

memory and do not affect bus operations.

3.1 Asynchronous bus operations

For asynchronous bus operations refer to Table 4 together with the followi ng text.

3.1.1 Asynchronous bus read

Asynchronous bus read operation s read from th e m emory cells, or specific registers

(electronic signature, status register, CFI and burst configuration register) in the command

interface. A valid bus operation involves setting the desired address on the address inputs,

applying a Low signal, V

, to Chip Enable and Output Enable and keeping Write Enable

and Output Disable High, V

. The data inputs/outputs will output the value, see Figure 8:

Asynchronous bus read AC waveforms, and Table 16: Asynchronous b us read AC

characteristics, for details of when the output becomes valid.

Asynch ronous read is the default read mode which the device enters on power-up or on

return from res et/po we r-down.

3.1.2 Asynchronous latch controlled bus read

Asynch ronous latc h controll ed bus read operations read from t he memory ce lls or specific

regist ers in the command in terf ace. The add r ess is latched in the m em ory before the value

is output on the data bus, allowing the address to change during the cycle without affecting

the ad dress that the m emory uses .

A valid bus operat ion involves setting t he desired address on t he address inputs, setting

Chip Enable and Latch Enable Low, V

and ke eping Write Enable High, V

; the address i s

latched on the rising edge of Latch Enable. Once latched, the address inputs can change.

Set Output Enable Low, V

, to read the data on the data inputs/outputs; see Figure 9:

Asynchronous lat ch controll ed bus read AC waveforms, and Table 1 7: Asynchronous latch

contr olled bus read AC char acteristi c s , for details on when the output becomes valid.

Note that, sinc e the La tch Ena ble in put is tr ans pa ren t when set Lo w, V

, asynchronous bus

read operations can be perf ormed when t he memory is configured for asynchronous latc h

enable bus operations by holding Latch Enable Low, V

throughout the bus operation.

M58BW016DT, M58BW016DB, M58BW016FT, M58BW016FB Bus operations

19/70

3.1.3 Asynchronous page read

Asynchronous page re ad operat ions are used to read fr om several add r esses withi n t he

same m emory page. Each m emory page is 4 do uble-wor ds and is addressed b y the

address inputs A0 and A1.

Data is read intern ally and s to r ed in the page buffer. Valid bus operat ions are the same as

asynchronous bus read operations b ut with different timings. Th e first read operation within

the page has identical tim ings, subse quent rea d s within the same page ha ve much shorter

access times. If the page changes then the normal, longer timings apply again. Page read

does not support latched controlled read.

See Figure 10: Asy nchro nous p age r ead AC wav efor ms, an d Table 18: Asynchronous page

read AC ch aracteristics, for details on when the outputs become valid.

3.1.4 Asynchronous bus write

Asynch ronous bus write operatio ns write to the com m and inte rf ace to send com m ands to

the memory or to latc h addresse s and input data to progra m . Bus write operations are

asynchronous, the clock, K, is don’t care duri ng bus write operation s.

A valid asynchronous bus write operation begins by setting the desired address on the

address inputs, and setting Chip Enable, Write Enable and Latch Enable Low, V

, and

Output Enable High, V

, or Outp ut D isable Low, V

. The address inputs a r e l atched by th e

command interface on the rising edge of Chip Enable or Write Enable, whichever occurs

first. Commands and input da ta are latched on th e rising edge of Chip Enable, E, or Write

Enabl e, W, whichever occurs first. Output Enable must remain High, and Output Disable

Low, during the whole asynchronous bus write operatio n.

See Figure 11: Asynchronou s wri te AC waveforms, and Table 19: Asynchron ou s wr ite and

latch controlled write AC characteristics, for details of the ti ming requirements.

3.1.5 Asynchronous latch controlled bus write

Asynch ronous lat c h controll ed bus write operati ons write to the command interface to se nd

commands to the mem ory or to la tc h add r ess es and inp ut data to program. Bu s wr i t e

operations are asynchronous, the clock, K, is don’t care during bus write operations.

A valid asynchronous latch controlled bus write operation begins by setting the desired

addr ess on the address inputs and pulsing Latch Enable Low, V

. The address inputs are

latched by the command interface on the rising edge of Latch Enable, Write Enable or Chip

Enable, whichever occurs first. Command s and input data are latched on the rising edge of

Chip Enable, E, or W r ite Enab le, W, whichever occurs first. Output Enable must remain

High, and Output Disab le Low, during t he whole asy nchronous bus wri te operation.

See Figure 12: Asynchronous latch c ontrolled write AC wavef orms, and Table 19:

Asynchronous writ e and latch controlled write AC charact eristics, for deta ils of the timing

requirements.

3.1.6 Output Disable

The data outputs are hig h impedance when the Output Enable , G, is at V

or Output

Disable, GD, is at V

Bus oper at ion s M58BW016DT, M58B W01 6D B, M58BW016F T, M58BW0 16FB

20/70

3.1.7 Standby mode

When Chip Enable is High, V

, an d the Progra m/Eras e cont rolle r is i dle, th e memo ry ente rs

Standby mode, the power consumption is reduced to the standby level and the Data

inputs/outputs pins are placed in the high impedance state regardless of Output Enable,

Write Enable or Output Di sable in puts.

3.1.8 Automatic low power mode

If there is no change in the state of the bus for a short period of time during asynchronous

bus read operations the memory enters auto low power mode where the internal supply

current is reduced to the auto-standby supply current. The data inputs/outputs will still

output data if a bus read operation is in progress.

Automatic low power is only available in asynchronous read modes.

3.1.9 Power-down mode

The m emory is in power-down when Res et/Power-down, RP, is at V

. The power

consumption is reduced to the power-down level and the outputs are high impedance,

indepe ndent of the Chip Ena bl e, E, Output Enable, G, Output Disable, GD, or W ri te En able ,

W, inputs.

3.1.10 Electronic signature

Two codes identifying the manufacturer and the device can be read from the memory

allowing programming equipment or applications to automatically match their interface to

the characteristics of the memory. The electronic signature is output by giving the Read

Electronic Signature command. The manufacturer code is output when all the address

input s are at V

. The device code is output when A1 is at V

and all the other address pins

are at V

(see Table 5: Asynchronous read electronic signature operation). Issue a Read

Memory Array command to return to read mo de .

Table 4. Asynchronous bus operations

(1)

1. X = don’t care.

Bus operation Step E GGD WRP LA0-A18 DQ0-DQ31

Asynchronous bus read V

Address Data output

Asynchronous latch

controlled bus read Address Latch V

Address High-Z

Read V

X Data output

Asynchronous page read V

X Address Data output

Asynchronous bus write V

Address Data input

Asynchronous latch

controlled bus write Address Latch V

Address High-Z

Write V

X Data input

Output Enable, G V

X X High-Z

Output Disable, GD V

X X High-Z

Standby V

XXXV

X X High-Z

Reset/power-down X X X X V

X X High-Z

M58BW016DT, M58BW016DB, M58BW016FT, M58BW016FB Bus operations

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3.2 Synchronous bus operations

For synchronous bus operations refer to Table 6 together with the following text.

3.2.1 Synchronous burst read

Synchronous burst read operations are used to read from the memory at specific times

synchr onized to an e x t ernal reference clock.

In th e M 58BW016FT and M 58BW0 16FB only, once the m emory is configured in burst

mode, it is mandatory to have an active clock signal since the switching of the output buffer

data bus is synchronized to the active edge of the clock. In t he absenc e of clock, no data is

output.

Caution: The M58BW016DT and M58BW016DB are not concerned by the paragraph above.

The burst type, len gt h and la tency can be configured. The differ ent configurations for

synchronous burst read operations are described in Section 3.3: Burst configuration

In continuous burst read, on e burst read operation can access the entire memory

sequentially by keeping the Burst Address Advance B at V

for the appropriate number of

clock cycles. At the end of the memory address space the burst read restarts from the

beginning at address 000000h.

A valid synchronous burst read operation begins when the Burst Clock is active and Chip

Enable and Latch Enable are Low, V

. The burst start address is latched and loaded into

the internal burst address counter on the valid Burst Clock K edge (rising or falling

depending on the value of M6) or on the rising edge of Latch Enable, whichever occurs first.

After an initial memory latency time, the memory outputs data each clock cycle (or two clock

cycle s depending on the value of M9 ). The Burst Ad dress Advan ce B input controls the

memory burst output. The second burst output is on the next clock valid edge after the Burst

Address Ad vance B has been pulled Low.

Valid Data Ready, R, monitors if the memory burst boundary is exceeded and the burst

controller of the microprocessor needs to insert wait states. When Valid Data Ready is Low

on the active clock edge, no new data is available and the memory does not increment the

internal addr ess counter at the a ct iv e clock ed ge even if B urs t A dd r es s Ad v an ce , B, is Lo w.

Table 5. Asynchronous read electronic signature operation

Code Device E GGD WA18-A0 DQ31-DQ0

Manufacturer All V

00000h 00000020h

Device

M58BW016DT

M58BW016FT V

00001h 00008836h

M58BW016DB

M58BW016FB V

00001h 00008835h

Burst configuration

00005h BCR

(1)

1. BCR = Burst configuration register.

Bus oper at ion s M58BW016DT, M58B W01 6D B, M58BW016F T, M58BW0 16FB

22/70

Valid Data Ready may be configured (by bit M8 of burst configuration register) to be valid

immedi ately at the valid clock edge or one data cycle before the valid clock edge.

Synchr onous burst read will be suspended i f Bu rst Address Advance, B, goes High, V

If Output Enable is at V

and Output Disable is at V

, the last data is st ill vali d.

If Output Enable , G, is at V

or Output Disable, GD, is at V

, but the Burst Address

Advance, B, is at V

the inter nal Bur s t Addres s c ounter is increme nted at each Burst Clock

K valid edge.

The synchronous burst read timing diagrams and AC characteristics are de scribed in the

AC and DC parameters section. See Figure 13, Figure 14, Figure 15 and Figure 16, and

Table 20.

3.2.2 Synchronous burst read suspend

During a synchronous burst read operation it is possible to suspend the operation, freeing

the data bus for other higher priority devices.

A valid synchronous burst read operation is suspended when both Output Enable and Burst

Address Advance are High, V

. The Burst Address Adva nce goin g High, V

, stops the

burst counter and the Output Enable going High, V

, inhibits the data outputs. The

synch ronous burst rea d operatio n can be resumed by setting Ou tput Enab le Low.

Table 6. Synchronous burst read bus operations

(1)(2)

1. X = don't care, V

or V

2. M15 = 0, bit M15 is in the burst configuration register.

Bus operation Step E GGD RP K

(3)

3. T = transit ion, see M6 in the burst conf iguration register for details on the active edge of K.

L B A0-A18

DQ0-DQ31

Synchronous

burst read

Address Latch V

X Address input

Read V

Data output

Read Suspend V

High-Z

Read Resume V

Data output

Burst Address

Advance V

High-Z

Read Abort, E V

XXV

XXX High-Z

Read Abort, RP XXXV

XXX High-Z

M58BW016DT, M58BW016DB, M58BW016FT, M58BW016FB Bus operations

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3.3 Burst configuration register

The bur st con fi gurati on regi st er i s us ed to conf ig ure the typ e of bus ac ce ss t hat the m emor y

will pe rf orm .

The burst configuration register is set through the command interface and will retain its

information until it is re-configured, the device is reset, or the device goes into reset/pow er-

down mode. The burst configuratio n register bits are described in Table 7. They sp ecify the

select ion of the burst length, burst ty pe, burst X and Y latencies and t he read operation.

Refer to Figure 4 and Figure 5 for examples of syn chronous burst config urations.

3.3.1 Read select bit (M15)

The re ad select bi t, M15, is used to swi tch between asynchronous and synchronous bus

read operations. When the read select bit is set to ’1’, bus read operations are

asynchro nous; when the read select bit is set to ’0’, bus read operations are synchronous.

On reset or po wer-up the read select b i t is set to’1’ for asynchronous accesses.

3.3.2 X-Latency bits (M14-M11)

The X-Latency bits are used during synchronous bus read operations to set the number of

clock cycles betw een the address being latched and the first data becoming available. For

correct operation the X-Latency bits can only assume the values in Table 7: Burst

confi guration re gister. The X-Latency bits should also be selected in conjunction with

Table 8: Burst type definition to ensure vali d settings.

3.3.3 Y-Latency bit (M9)

The Y-Latency bit is used d uri ng synchronous bus read op erations to set the num ber of

cloc k cy c l es between consecutive reads. The Y-Latency value depends on both the X-

Latency value and the setting in M9.

When the Y-Latency is ‘1’ the d ata changes each clock c ycle; when the Y-Latency is ‘2’ t he

data changes every second clock cycle. See Table 7: Burst configuration register, and

Ta ble 8: Burst type definition for va lid comb i nations of the Y-Latency, the X-Latenc y an d the

clo c k fr equency.

3.3.4 Valid data ready bit (M8)

The valid data ready b it controls the tim ing of the valid d ata ready outpu t pin, R. When the

valid data ready bit is ’0’ the valid data ready output pin is driven Low for the active clock

edge when invalid data is output on the bus. When the valid data ready bit is ’1’ the valid

data ready ou tput pin is driven Low one clock cycle prior to invalid data bein g output on the

bus.

3.3.5 Burst type bit (M7)

The burst type bit is used to configure the sequence of addresses read as sequential or

interleaved. When the burst type bit is ’0’ the memory outputs from interleaved addresses;

when the burst type bit is ’1’ the memory outputs from sequential addresses. See Table 8:

Burst type definition, for the sequence of addresses output from a given starting address in

each mode.

Bus oper at ion s M58BW016DT, M58B W01 6D B, M58BW016F T, M58BW0 16FB

24/70

3.3.6 Valid clock edge bit (M6)

The valid clock edge bit, M6, is used to configure the active edge of the Clock, K, durin g

synch r onous burst read operations. When th e valid clock edge bit is ’0’ the falli ng edge of

the clo ck is the ac tive e dge; when the vali d cloc k edge bit is ’1’ the ris ing edg e of the cloc k is

active.

3.3.7 Wrap burst bit (M3)

The burst reads can be confined inside the 4 or 8 double-word boundary (wrap) or

overco me the bound ary (no wra p). The wr ap burst bit is us ed to sel ect between wr ap and no

wrap. When the wr ap burst bit i s set to ‘0’ t he burst read wrap s; when i t is set to ‘1 ’ the burst

read does not wrap.

3.3.8 Burst length bit (M2-M0)

The burst length bits set the maximum number of double-words that can be output during a

synchronous burst read operation before the address wraps. Burst lengths of 4 or 8 are

available for both the sequential and interleaved burst types, and a continuous burst is

available for the sequential type.

Table 7: Burs t config urati on regis ter gives the valid combinations of the burst length bits that

the memory accepts; Table 8: Burst type de finition, gives the sequence of addresses output

from a given starting address for each length.

If either a conti nuous or a no wrap bu rst read has been initiated the devi ce will output data

synchronously . Depending on the starting address, the device activates the valid data ready

outp ut to indicate that a delay is nece ssary before the data is output. If the starting address

is aligned to an 8 double-word boundary, the continuous burs t mode will run without

activating the valid data ready output. If the starting address is not aligned to an 8 double-

word boundary, valid data ready is activated to indicate that the device needs an internal

delay to read the successive words in the array.

M10, M5 and M4 are reserved for future use.

M58BW016DT, M58BW016DB, M58BW016FT, M58BW016FB Bus operations

25/70

Table 7. Burst configuration register

Bit Description Value Description

M15 Read select 0 Synchronous burst read

1 Asynchronous rea d (default at power-on)

M14 0 Reserved (defau lt value)

M13-M11 X-Latency

(1)

1. X latencies can be calculated as: (t

AVQV

– t

LLKH

+ t

QVKH

) + t

SYSTEM MARGIN

< (X -1) t

is an integer

number from 4 to 8, t

is the clock peri od and t

SYSTEM MARGIN

is the time margin required for the

calculation).

000 R ese rved (d efault value)

001 Reserved

010 4, 4-1-1-1

(2)

2. This feature i s available for th e M58BW016F version up to the full operative freq uency of 56 MHz, and for

the M58BW016D version only if the operative frequency is below 45 MHz.

011 5

(3)

, 5-1-1-1, 5-2-2-2

3. The M58BW016F version has a maximum operative frequency of 66 MHz, fully factory tested.

100 6

(3)

, 6-1-1-1, 6-2-2-2

101 7

(3)

, 7-1-1-1, 7-2-2-2

110 8

(3)

, 8-1-1-1, 8-2-2-2

111 Reserved

M10 0 Reserved (defau lt value)

M9 Y-Latency

(4)

4. Y latencies can be calculated as: t

KHQV

+ t

SYSTEM MARGIN

+ t

QVKH

< Y t

0 One burst clock cycle (de fault value)

1 Two bur st clock cycles

M8 Valid data ready 0R valid Low during valid burst clock edge (default

value)

1 R valid Low 1 data cycle before valid burst clock edge

M7 Burst type 0 Interleaved (default value)

1 Sequential

M6 Valid clock edge 0 Falling burst clock edge (default value)

1 Rising burst clock edge

M5-M4

00 R eserved (default value)

01 Reserved

10 Reserved

11 Reserved

M3 Wrapping 0 Wrap (default value)

1 No wrap

M2-M0 Bur st length

000 R ese rved (defa ult value)

001 4 double-words

010 8 double-words

011 Reserved

100 Reserved

101 Reserved

110 Reserved

111 Continuous

Bus oper at ion s M58BW016DT, M58B W01 6D B, M58BW016F T, M58BW0 16FB

26/70

Table 8. Burst type definition

M 3 Starting

address x4

sequential x4

interleaved x8

sequential x8

interleaved Continuous

0 0 0-1-2-3 0-1-2-3 0-1-2-3-4-5-6-7 0-1-2-3-4-5-6-7 0-1-2-3-4-5-6-7-8-9-10..

0 1 1-2-3-0 1-0-3-2 1-2-3-4-5-6-7-0 1-0-3-2-5-4-7-6 1-2-3-4-5-6-7-8-9-10-11..

0 2 2-3-0-1 2-3-0-1 2-3-4-5-6-7-0-1 2-3-0-1-6-7-4-5 2-3-4-5-6-7-8-9-10-11-12..

0 3 3-0-1-2 3-2-1-0 3-4-5-6-7-0-1-2 3-2-1-0-7-6-5-4 3-4-5-6-7-8-9-10-11-12-13..

0 4 – – 4-5-6-7-0-1-2-3 4-5-6-7-0-1-2-3 4-5-6-7-8-9-10-11-2-13-14..

0 5 – – 5-6-7-0-1-2-3-4 5-4-7-6-1-0-3-2 5-6-7-8-9-10-11-12-13-14..

0 6 – – 6-7-0-1-2-3-4-5 6-7-4-5-2-3-0-1 6-7-8-9-10-11-12-13-14-15..

0 7 – – 7-0-1-2-3-4-5-6 7-6-5-4-3-2-1-0 7-8-9-10-11-12-13-14-15-16..

0 8 – – – – 8-9-10-11-12-13-14-15-16-17..

1 0 0-1-2-3 – 0-1-2-3-4-5-6-7 – 0-1-2-3-4-5-6-7-8-9-10..

1 1 1-2-3-4 – 1-2-3-4-5-6-7-8 – 1-2-3-4-5-6-7-8-9-10-11..

1 2 2-3-4-5 – 2-3-4-5-6-7-8-9 – 2-3-4-5-6-7-8-9-10-11-12..

1 3 3-4-5-6 – 3-4-5-6-7-8-9-10 – 3-4-5-6-7-8-9-10-11-12-13..

1 4 4-5-6-7 – 4-5-6-7-8-9-10-11 – 4-5-6-7-8-9-10-11-12-13-14..

1 5 5-6-7-8 – 5-6-7-8-9-10-11-12 – 5-6-7-8-9-10-11-12-13-14..

1 6 6-7-8-9 – 6-7-8-9-10-11-12-13 – 6-7-8-9-10-11-12-13-14-15..

1 7 7-8-9-10 – 7-8-9-10-11-12-13-14 – 7-8-9-10-11-12-13-14-15-16..

1 8 8-9-10-11 – 8-9-10-11-12-13-14-15 – 8-9-10-11-12-13-14-15-16-17..

M58BW016DT, M58BW016DB, M58BW016FT, M58BW016FB Bus operations

27/70

Figure 4. Example burst configuration X-1-1-1

Figure 5. Example burst configuration X-2-2-2

AI03841

ADD VALID

4-1-1-1

5-1-1-1

6-1-1-1

7-1-1-1

8-1-1-1

0123456789

VALIDVALIDVALIDVALID

VALID

VALIDVALIDVALID

VALID

VALIDVALID

VALID

AI04406b

ADD

DQ VALID

5-2-2-2

6-2-2-2

7-2-2-2

8-2-2-2

0123456789

VALID

VALID VALID

VALID

NV NV

NVNV

NV=NOT VALID

Command i nt er f ace M58BW0 16D T, M58BW016DB, M58BW016F T, M58BW0 16FB

28/70

4 Command interface

All bus wri te opera tions to the memo ry ar e interpr ete d by the co m ma nd interface .

Com m ands consist of one or m ore sequential bus write operation s . Th e commands are

summarized in Table 9: Comma nds. Refer to Table 9 in conjunction with the text

descriptions below.

4.1 Read Memory Array command

The Read Memory Array command returns the memory to read mode. One bus write cycle is

required to issue the Read Memory Array command and return the memory to read mode.

Subsequent read operations will output the addressed memory array data. Once the

command is issued the memory remains in read mode until another command is issued.

From read mode bus read commands will access the memory array.

4.2 Read Electronic Signature command

The Read Electronic Signature command is used to read the manufacturer code, the device

code or the burst con figu ration register. One bus write cycle is required to issue the Read

Electronic Signature command. Once the command is issued subsequent bus read

oper ations, depending on the addr ess spec if ied, read the manufacturer code, the device

code or the burst configuration register until another command is issued; see Table 5:

Asynch ronous read electronic signat ure operation.

4.3 Read Query command

The Re ad Query c ommand i s used to read data from the common Flash interf ace (CFI)

memory area. One bus write cycle is required to issue the Read Query command. Once the

command is issued subsequent bus read operations, depending on the address specified,

read from the com m on Flash interface m emory area. See Appendix A: Common Flash

interface (CFI), Table 26, Table 27, Table 28, Table 29 and Table 30 for details on the

information contained in the com m on Flash interface (CFI) memory area.

M58BW016DT, M58BW016DB, M58BW016FT, M58BW016FB Command interface

29/70

4.4 Read Status Register command

The Read Status Register command is used to read the status register. One bus write cycle

is required to issue the Read Status Register command. Once the command is issued

subsequent bus read operations read the status register until another command is issued.

The stat us register i nf ormatio n is present on the output data bus (DQ1-DQ7) when Chip

Enabl e E and Outp ut Enable G are at V

and Output Disable is at V

An interactive update of the status register bits is possible by toggling Output Enable or

Output Disable. It is also possible during a program or erase operation, by deactivating the

device with Chip Enable at V

and then r e ac ti v ating it with Chip E na bl e a nd Output Enable

at V

and Out put Disab le at V

The content of the status register may also be read at the completion of a program, erase or

suspend operation. During a Block Erase or Program command, DQ7 indicates the

program/erase controller status. It is valid until the operation is completed or suspended.

See th e se ct ion on th e st atu s r egist er and Table 11 for detai ls on the def init ions of the status

regist er bits.

4.5 Clear Status Register command

The Clear Status Regist er comma nd can be used to reset bits 1, 3, 4 an d 5 in the status

the co m m an d is issued the memo ry ret urns to its previou s m ode, subse quent bus read

opera tions conti n ue to ou tput the same data.

The bits in the status register are sticky and do not automatically return to ‘0’ when a new

Program or Erase command is issued. If any error occurs the n i t is essential t o clear any

error bits in the status regist er by issuing the Cl ear Status Regis te r command before

attempting a new Pr ogram, Era se or Resume command.

Command i nt er f ace M58BW0 16D T, M58BW016DB, M58BW016F T, M58BW0 16FB

30/70

4.6 Block Erase command

The Block Erase command can be used to erase a block. It sets all of the bit s in the block to

‘1’. All previo us dat a in the bl ock is lo st. If the bl ock is pro tect ed then the er ase oper ation wi ll

abort, the data in the block will not be changed and the status register will output the error.

T wo bus write operations are required to issue the command; the first write cycle sets up the

Block Er ase command, the second write cycle confirms the Bl ock Erase command and

latches the block address in the program/erase controller and starts it. The sequence is

aborted if the Confirm command is not given and the device will output the status register

data with bits 4 and 5 set to '1'.

Once the command is issued subsequent bus read operations read the status register. See

the se ction on th e status registe r fo r details on the definitions of the status regi st er bits.

Durin g the e rase ope rat ion th e me mory will on ly a ccept the Read St atus Regi ster co mmand

and the Program/Erase Suspend command. All other commands will be ignored. The

command can be executed using either V

(for a norma l eras e ope ratio n) or V

(for a fast

erase operation). If V

is in the V

PPH

range when the command is issued then a fast erase

opera t io n will be ex ecuted, oth er wi s e the operat io n will us e V

. If V

goes b el ow the V

lockout voltage, V

PPLK

, during a fast erase the operation aborts, the status register V

status bi t is set to ‘1 ’ and the command m ust be re-issued.

Typical erase times are given in Table 10.

See Appendix B: Flowcharts, Figure 24: Block erase flowchart and pseudocode, for a

suggested flowchart on using the Block Erase command.

4.7 Program command

The Progra m com man d is use d t o pr ogra m th e memo ry arr ay. Two bus wr ite op era ti ons a re

required to issue the command; the first write cycle sets up the Program command, the

second write cycle latches the address and data to be programmed in the program/erase

controller and starts it. A program operation can be aborted by writing FFFFFFFFh to any

addre ss after the progr am se t- up command has been given.

Once the command is issued subsequent bus read operations read the status register. See

the se ction on th e stat us register for details on the definitions of the status register bits.

During the program operation the memory will only accept the Read Status Register

command and the Program/Erase Suspend command. All other commands will be ignored.

If Reset/Power-down, RP, fa lls to V

during programming the operation will be aborted.

The command can be executed using either V

(for a normal program operation) or V

(for a fa st progr am operati on). If V

is in the V

PPH

rang e when th e comman d is iss ued t hen

a fast pr ogr am oper at ion will be ex ecut ed , otherw ise the oper atio n wi ll u se V

. If V

goes

below the V

lock o ut voltag e, V

PPLK

, during a fast program the operatio n aborts and the

status register V

status bit is set to ‘1’. As data integrity cannot be guaranteed when the

program operation is aborted, the memory block must be erased and reprogrammed.

See Appendix B: Flowcharts on page 59, Figur e 22: Pro gram flowch art and p seudocode, f or

a suggested flowchart on using the Program command.

M58BW016DT, M58BW016DB, M58BW016FT, M58BW016FB Command interface

31/70

4.8 Program/Erase Suspend command

The Program/Erase Suspend comman d is used to p ause a prog ram or era se opera tion. T he

command will only be accepted during a program or erase operation. It can be issued at any

time during a program or erase operation. The command is ignored if the device is already

in suspend mode.

One bus write cycle is req uired to issue the Program/Erase Suspend command and pause

the program/erase controller. Once the command is issued it is necessary to poll th e

program/erase controller status bit (bit 7) to find out when the program/erase controller has

paus ed; no other commands wi ll be acc epted until the pr ogram/eras e control ler has p aused.

After the program/erase controller has paused, the memory will continue to output the status

During the polling period between issuing the Program/Erase Susp end command and t he

program/erase cont roller pausing it is possible f or t he operation to complete. Once the

program/erase controlle r status bit (bit 7) indicates that the pr ogram/erase controller is no

longer active, the program suspend statu s bit (bit 2) or the erase suspend status bit (bit 6)

can be us ed to d etermine if the operation has c om pl eted or is su sp ended. For tim ing on the

delay between issuing the Program/Erase Suspend command and th e program/erase

contro ller pausing see Table 10.

During Program/Erase Suspend the Read Memory Array, Read Status Register, Read

Elect ron ic S ign atu re, Rea d Q uery and Pr ogr am/E rase Re sum e co mmand s wi ll be a cce pted

by the command interface. Additionally, if the suspended operation was erase then the

Prog ram and the Program Su spend comm ands will al so be accepted. When a program

operation is completed inside a Block Erase Suspend the Read Memory Array command

must b e i ssued to reset the devic e i n r e ad mode, then t he Eras e R es um e command c an be

issued to complete the whole sequence. Only the blocks not being erased may be read or

programmed correctly.

See Appendix B: Flowcharts, Figure 23: Pr ogram suspend & resume f lowchart and

pseudocode, and Figure 2 5: Erase suspe nd & resume flowchar t and pseudo code, for

suggested flowcharts on using the Program/Erase Suspend command.

4.9 Program/Erase Resume command

Th e Pro gram/Er ase Resu m e comm an d can be used to re start the progra m / er a s e c ontr oller

after a program/erase suspend operation has pa used it. One bus write cycle is required to

issue the Program/Erase Resume command.

See Appendix B: Flowcharts, Figure 23: Pr ogram suspend & resume f lowchart and

pseudocode, and Figure 2 5: Erase suspe nd & resume flowchar t and pseudo code, for

suggested flowcharts on using the Program/Erase Resume command.

Command i nt er f ace M58BW0 16D T, M58BW016DB, M58BW016F T, M58BW0 16FB

32/70

4.10 Set Burst Configuration Register command

The Set Burst Co nf iguration Register command is used to write a new valu e to the bu rst

confi guration control re gister which defines the bur s t length, t y pe, X and Y la t encies,

synchr onous/asynchronous read m od e and the valid clock edge con f iguration.

Two bus write cycles are req ui red to issue the Set Bu rst Co nfiguration Register command .

The first cycle wr ites the setup command and the address corre sponding to the se t burs t

confi guration re gister content. The se cond cycle writes the burst configuration register data

and the confi rm com mand. Once the com m and is issued the memory return s to read mode

as if a Re ad Memory Array comma nd had been issued.

The valu e for the b ur s t configuration r egister is al wa ys pr es ented on A0-A 15. M0 is on A0,

M1 on A1, etc.; th e other address bi ts are ignored.

Table 9. Commands

(1)

1. X = Don’t care; RA = Read Address, RD = Read Data, ID = Devic e Code, SRD = Stat us Register Data, PA

= Program Addres s; PD = Pro gram Data, QA = Query Address , QD = Query Data, BA = Any address in t he

Block, BCR = Burst Con fi guration Register value.

Command

Cycles

Bus operations

1st cycle 2nd cycle

Op. Addr. Data Op. Addr. Data

Read Memor y Array ≥ 2 Write X FFh Read RA RD

Read Electronic Signature

(manufacturer code) ≥ 2 Write X 90h Read 00000h 20h

Read Electronic Signature

(device code) ≥ 2 Write X 90h Read 00001h IDh

Read Electronic Signature

(burst configuration register) ≥ 2 Write X 90h Read 00005h BCRh

Read Status Regis ter 2 Write X 70h Read X SRDh

Read Query ≥ 2 Write X 98h Read QAh QDh

Clear Status Reg ister 1 Write X 50h

Block Erase 2 Write X 20h Write BAh D0h

Program 2 Write X 40h

10h Write PA PD

Program/Erase Suspend 1 Write X B0h

Program/Erase Resume 1 Write X D0h

Set Burst Configuration Register 2 Write X 60h W r ite BCRh 03h

M58BW016DT, M58BW016DB, M58BW016FT, M58BW016FB Command interface

33/70

Table 10. Program, erase times and program, erase endurance cycles

(1)

1. T

= –40 to 125 ° C, V

= 2.7 V to 3.6 V, V

DDQ

= 2.4 V to V

Parameters

M58BW016

Unit

Min Typ Max

=12V V

=12V

Param et e r B l o ck (64 Kbi ts)

Program 0.030 0.016 0.060 0.032 s

Main Block (512 Kbits)

Program 0.23 0.13 0.46 0.26 s

Parameter Block Erase 0.8 0.64 1.8 1.5 s

Main Block Erase 1.5 0.9 3 1.8 s

Program Suspend Latency

time 310µs

Erase Suspend Latency tim e 10 30 µs

Program/Erase cycles (pe r

block) 100,000 cycles

Status regis t er M58BW016DT, M58BW01 6D B, M58B W01 6FT, M58BW016FB

34/70

5 Status register

The Status register provides information on the current or previous program or erase

operat ion. The various bits in the status register co nvey information an d errors on th e

operation. They are output on DQ7-DQ0.

To read the status register t he Read Status Register command can be issued. The status

The status register can be read fro m any address.

The cont en t s of th e st at us r egi ste r ca n be upd at ed dur ing an era se or pro gra m ope rati on by

toggling the Output Enable or Output Disable pins or by deactivating (Chip Enable, V

) and

then reactivating (Chip Enable and Output Enable, V

, and

Output Disable, V

.) the device.

The status register bits are summarized in Table 11: S t at us r egi st er bit s. Refer to Table 11 in

conjunction w ith the following text descript ions.

5.1 Program/erase controller status (bit 7)

The Program/erase controller status bit indicates whether the program/erase controller is

active or inactive. When the program/erase controller status bit is set to ‘0’, the

program/erase controller is active; when bit7 is set to ‘1’, the program/erase controller is

inactive.

The program/erase cont roller status is set to ‘0’ imm ediate ly after a Program/Erase

Suspend comma nd is issued un til the program / erase controller pauses. After the

program/erase controller pauses the bit is set to ‘1’.

During program and erase operatio ns the program/erase controller status bit can be polled

to find the end of th e oper ation. The o ther b its in the st atus reg ist er shou ld not b e test ed unti l

the program/erase controller comple tes the operation and the bit is set to ‘1’.

After the progr am/era s e c ontr o ller complet es its operation the erase sta t us (bit5), program

status bits should be tested for errors.

5.2 Erase suspend status (bit 6)

The erase susp end status bit indica tes that an erase operat ion has been suspe nded and is

wait ing to be res umed . The er ase susp end s t atus shou ld only be con sid ere d val id whe n the

program/erase controller status bit is set to ‘1’ (program/erase controller inactive); after a

Program/Erase Suspend command is issued the memory may still complete the operation

rather than entering the suspend mode.

When the erase suspend status bit is set to ‘0’, the program/erase controller is active or has

comp leted its operation; when the bit is set to ‘1’, a Program/Erase Suspend command has

been issued and the memory is waiting for a Program/Erase Resume command.

When a Pr ogram /Eras e Resume command i s issu ed the erase s uspen d st atus bit re turns to

‘0’.

M58BW016DT, M58BW016DB, M58BW016FT, M58BW016FB Status register

35/70

5.3 Erase status (bit 5)

The erase status bit c an be used to ident ify if the m emory ha s failed to verify th at the block

has er ase d corr ect ly. The eras e st a tus bit s hou ld be re ad on ce the pro gram/e r ase cont rol le r

status bit is High (program/erase controller inactive).

When the erase status bit is set to ‘0’, the memory has succe ssfully verified that the bl ock

has e rased corr ectly. When th e era se st atus bi t is s et t o ‘1’, the pr ogra m/eras e cont rol ler h as

applied the maximum number of pulses to the block and still failed to verify that the block

has erased correctly.

Once set to ‘1’, the e r ase status bit can only be reset to ‘0’ by a Clear Status Register

comman d or a hardw are res et. If set to ‘1 ’ it s hou ld be res et be fore a n ew Pro gra m or Eras e

command is issued, otherwise the new command will appear to fail.

5.4 Program status (bit 4)

The program status bit is used to identify a program failure. Bit4 should be read once the

program/erase controller status bit is High (program/erase controller inactive).

When bit4 is set to ‘0’ the memory has successfully verified that the device has programmed

correctly. When bit4 is set to ‘1’ the device has failed to verify that the data has been

programmed correctly.

Once set to 1’, the program status bit can only be reset to ‘0’ by a Clear Status Register

comman d or a hardw are res et. If set to ‘1 ’ it s hou ld be res et be fore a n ew Pro gra m or Eras e

command is issued, otherwise the new command will appear to fail.

5.5 V

status (bit 3)

The V

status bit can be used to identify an invalid voltage on the V

pin during fast

program and erase operations. The V

pin is only sampled at the beginn ing of a program

or erase operation. Indeterminate results can occur if V

becomes invalid during a fast

progr am or er as e op er ation.

Wh en the V

status bit is set to ‘0’, the voltage on the V

pin was sampled at a valid

voltage; when th e V

status bit is set to ‘1’, the V

pin has a v oltag e that is below the V

lockout voltage, V

PPLK

Once set to ‘1’, the V

status bit can only be reset to ‘0’ by a Clear Status Register

comman d or a hardw are res et. If set to ‘1 ’ it s hou ld be res et be fore a n ew Pro gra m or Eras e

command is issued, otherwise the new command will appear to fail.

Status regis t er M58BW016DT, M58BW01 6D B, M58B W01 6FT, M58BW016FB

36/70

5.6 Program suspend status (bit 2)

The program su spend status bit indi cates that a program operati on has been suspended

and is waiting to be resumed. The program suspend status should only be considered valid

when the program/erase controller status bit is set to ‘1’ (program/erase controller inactive);

after a Program/Erase Suspend command is issued the m emory may still complete the

operation rather than entering the suspend mode.

When the pr ogram suspend status bit is set to ‘0’, the p r ogram/er ase control ler is active or

has completed its operation; when the bit is set to ‘1’, a Program/Erase Suspend command

has been issued and the memory is waiting for a Program/Erase Resume command.

When a Program/Erase Resume command is issued the program suspend status bit returns

to ‘0’.

5.7 Block protection status (bit 1)

The bl ock protec tion status bit can be used t o identify if a progra m or erase opera ti on has

tried to modify the contents of a protected block.

When the block protection status bit is set to ‘0’, no program or erase operations have been

attempted to protected blocks since the last Clear Status Regis ter command or hardware

reset; when the block protection status bit is set to ‘1’, a program or erase operation has

been attempted on a protected block.

Once set to ‘1’, th e block protec t ion statu s bit can only be reset Low b y a Clear Status

Regis ter c omma nd or a hardw are res et. If s et t o ‘1’ it sh ould be re set befo re a new P rogra m

or Erase command is issued, otherwise the new command will appear to fail.

All others bits are reserved.

Table 11. Status register bits

Bit Name Logic level Definition

7Program/erase controller

status ’1’ Ready

’0’ Busy

6 Eras e suspend status ’1’ Suspended

’0’ In progress or completed

5 Eras e status ’1’ Erase error

’0’ Erase success

4 Program status, ’1’ Program error

’0’ Program success

status ’1’ V

invalid, abort

’0’ V

2 Progr am suspend status ’1’ Suspended

’0’ In progress or completed

1Erase/program in a protected

block ’1’ Program/erase on protected block, abort

’0’ No operations to protected sectors

Other bits reserved

M58BW016DT, M58BW016DB, M58BW016FT, M58BW016FB Maximum ratings

37/70

6 Maximum ratings

Stressing the device above th e ratings listed in Tabl e 1 2: Absolut e m aximum ratings, may

caus e permanent damage to the device. These are stress rating s only and operation of the

device at these or any other conditions above those indicated in the operating sections of

this specification is not implied. Exposure to absolute maximum rating conditions for

extended periods may affect device reliability. Refer also to the Numonyx SURE Program

and other relevant quality documents.

Table 12. Absolute maximum ratings

Symbol Parameter Value Unit

Min Max

BIAS

Temperature under bias –40 125 °C

STG

Storage temperature –55 155 °C

Input or output voltage –0.6 V

DDQ

+0.6

DDQIN

+0.6 V

, V

DDQ,

DDQIN

Supply voltage –0.6 4.2 V

Program voltage –0 .6 13.5

(1)

1. Cumulative time at a high voltage level of 13.5 V should not exceed 80 hours on V

pin.

DC and AC parameters M58BW016DT, M58BW016DB, M58BW016FT, M58BW016FB

38/70

7 DC and AC parameters

This section summarizes the operating a nd measurement conditions, and the DC and AC

characteristics of the device. The parameters in the DC and AC characteristics tables that

follow, are derived from tests performed under the measurement conditions summarized in

Table 13: Operating and AC measurement conditions. Designers shou ld check that the

operating conditions in their circuit match the measurement conditions when relying on the

quoted p aramete r s .

Figure 6. AC measurement input/output waveform

1. V

= V

DDQ

Table 13. Operating and AC measurement conditions

Parameter Value Units

Min Max

Supply voltage (V

)2.7 3.6V

Input/output supply voltage (V

DDQ

)2.4 V

Ambient temperatu re (T

)Grade 6 –40 90 °C

Grade 3 –40 125 °C

Load capacitance (C

)30pF

Clock rise and fall times 4 ns

Input rise and fall times 4 ns

Input pulses voltages 0 to V

DDQ

Input and output timing ref. voltages V

DDQ

/2 V

AI04153

VDDQ

VDDQIN

0 V

VDDQ/2

VDDQIN/2

M58BW016DT, M58BW016DB, M58BW016FT, M58BW016FB DC and AC parameters

39/70

Figure 7. AC measurement load circuit

Table 14 . Device capaci tance

(1)(2)

1. T

= 25 °C, f = 1 MHz.

2. Sampled only, not 100% tested.

Symbol Parameter Test condition Typ Max Uni t

Input capacitance V

= 0 V 6 8 pF

OUT

Output capacitance V

OUT

= 0 V 8 12 pF

AI04154

1.3 V

OUT

CL includes JIG capacitance

3.3 kΩ

1N914

DEVICE

UNDER

TEST

DC and AC parameters M58BW016DT, M58BW016DB, M58BW016FT, M58BW016FB

40/70

Table 15. DC characteristics

Symbol Parameter Test condition Min Max Unit

Input Leakage current 0 V≤ V

≤ V

DDQ

±1 µA

Output Leakage current 0 V

≤

OUT

≤V

DDQ

±5 µA

Supply current (Random R ead) E=V

, G =V

add

=6MHz M58BW016DT/B 20 mA

M58BW016FT/B 25

DDP-UP(1)

Supply current (Power-up) E =V

applies only to

M58BW016FT/B 20 mA

DDB

Supply current (Burst Read)

E=V

, G =V

clock

=40MHz M58BW016DT/B 30 mA

M58BW016FT/B

E=V

, G =V

clock

=56MHz M58BW016DT/B 30 mA

M58BW016FT/B 40 mA

DD1

Supply current (Standby) E=RP=V

0.2 V M58BW016DT/B 60 µA

M58BW016FT/B 150 µA

Supply current (Auto Low-Power ) E=V

±0.2V,

RP =V

±0.2V 60 µA

DD2

Supply current (Reset/Pow er-down) RP =V

±0.2V 60 µA

DD3

Supply current (Program or Erase,

Set Lock bit, Erase Lock bit) Program, Block Erase in progress 30 mA

DD4

Supply current

(Erase/Program Suspend) E=V

M58BW016DT/B 40 µA

M58BW016FT/B 150 µA

Program current (Read or St andby) V

≥ V

PP1

± 30 µA

PP1

Program current (Read or St andby) V

≤ V

PP1

± 30 µA

PP2

Program current (Power-down) RP =V

± 5 µA

PP3

Program current (Program)

Program in progress V

PP1

200 µA

PPH

20 mA

PP4

Program current (Erase) Erase in

progress V

PP1

200 µA

PPH

20 mA

Input Low voltage –0.5 0.2V

DDQIN

Input High voltage (for DQ lines) 0.8V

DDQIN

DDQ

+0.3 V

Input High voltage (for input only

lines) 0.8V

DDQIN

3.6 V

Output Low voltage I

= 100 µA 0.1 V

Output High voltage CMOS I

= –100 µA V

DDQ

–0.1 V

PP1

Program voltage

(program or erase operations) 2.7 3.6 V

PPH

Program voltage

(p rogram or erase operations ) 11.4 12.6 V

LKO

supply voltage (erase and

program lockout) 2.2 V

PPLK

supply voltage (erase and

program lockout) 11.4 V

1. I

DDP-UP

is defin ed only during the power-up phase of th e M58BW016FT/B, fro m the moment current is appli ed with RP Low

to the moment when the sup ply voltage has become stable and RP is brought to High.

M58BW016DT, M58BW016DB, M58BW016FT, M58BW016FB DC and AC parameters

41/70

Figure 8. Asynchronous bus read AC waveforms

Table 16. Asynchronous bus read AC characteristics

Symbol Parameter Test condition M58BW016 Unit

70 80

AVAV

Address Valid to Address Valid E =V

, G =V

Min 70 80 ns

AVQV

Address Valid to Output Valid E =V

, G =V

Max 70 80 ns

AXQX

Address Transition to Output Transition E = V

, G = V

Min 0 0 ns

EHLX

Chip Enable High to Latch Enable Transition Min 0 0 ns

EHQX

Chip Enable High to Output Trans ition G =V

Min 0 0 ns

EHQZ

Chip Enable High to Output Hi-Z G =V

Max 20 20 ns

ELQV(1)

1. Output Enable G may be dela yed up to t

ELQV

- t

GLQV

after the falling edge of Chip Enable E without

increasing t

ELQV

Chip Enable Low to Output Valid G =V

Max 70 80 ns

ELQX

Chip Enable Low to Output Transition G =V

Min 0 0 ns

GHQX

Output Enable High to Output Transition E =V

Min 0 0 ns

GHQZ

Output Enable High to Output Hi-Z E =V

Max 15 15 ns

GLQV

Output Enable Low to Output Valid E =V

Max 25 25 ns

GLQX

Output Enable to Output Tra nsition E =V

Min 0 0 ns

LLEL

Latch Enable Low to Chip Enable Low Min 0 0 ns

AI04407C

A0-A18

DQ0-DQ31

VALID

tLLEL

tAXQX

tELQX

tELQV

tAVQV

tGLQX

tGLQV tEHQX

tEHQZ

tGHQX

tGHQZ

See also Page Read

OUTPUT

M58BW016DT, M58BW016DB, M58BW016FT, M58BW016FB DC and AC parameters

43/70

Figure 10. Asynchronous page read AC waveforms

Table 18. Asynchronous page read AC characteristics

(1)

1. For other timings see Table 16: Asynchronous bus read AC characteristics.

Symbol Parameter Test condition M58BW016 Unit

70 80

AVQV1

Address Valid to Output Valid E =V

, G =V

Max 25 25 ns

AXQX

Address Transition to Output Transit ion E =V

, G =V

Min 6 6 ns

AI03646

A0-A1

DQ0-DQ31

A0 and/or A1

tAVQV1

OUTPUT

tAXQX

OUTPUT + 1

DC and AC parameters M58BW016DT, M58BW016DB, M58BW016FT, M58BW016FB

44/70

Figure 11. Asynchronous write AC waveforms

AI03651

DQ0-DQ31

A0-A18

E = L

INPUT

VALID VALID

tWHEH

VALID

tAVWH

tWLWH

tELWL

INPUT VALID SR

VPP

tWHAX

tWHWL

tWHDX

tDVWH

tWHGL

tWHQV

tVPHWH tQVVPL

tQVPL

tPHWH

RP = V

Read Status RegisterWrite CycleWrite Cycle

tAVLL

M58BW016DT, M58BW016DB, M58BW016FT, M58BW016FB DC and AC parameters

45/70

Figure 12. Asynchronous latch controlled write AC waveforms

AI03652

DQ0-DQ31

A0-A18

INPUT

VALID VALID VALID

tAVLH

INPUT VALID SR

VPP

tLHAX

Read Status RegisterWrite CycleWrite Cycle

tLLLH

tLLWH

tWHAX

tELWL

tWLWH

tWHEH

tWHWL tWHGL

tWHQV

tDVWH

tWHDX tVPHWH tQVVPL

tQVPL

RP = V

tAVWH

tELLL

tAVLL

DC and AC parameters M58BW016DT, M58BW016DB, M58BW016FT, M58BW016FB

46/70

Table 19. Asynchronous write and latch controlled write AC characteristics

Symbol Parameter Test condition M58BW016 Unit

70 80

AVLL

Address Valid to Latch Enable Low Min 0 0 ns

AVWH

Address Valid to Write Enable High E =V

Min 50 50 ns

DVWH

Data Input Valid to Write Enable High E =V

Min 50 50 ns

ELLL

Chip Enable Low to Latch Enable Low Min 0 0 ns

ELWL

Chip Enable Low to Write Enable Low Min 0 0 ns

LHAX

Latch Enable High to Address Tr ansition Min 5 5 ns

LLLH

Latch Enable Low to Latch Enable High Min 10 10 ns

LLWH

latch Enable Low to Write Enable High E =V

Min 50 50 ns

QVVPL

Output Valid to V

Low Min 0 0 ns

VPHWH

High to Write Enable High Mi n 0 0 ns

WHAX

Write Enable High to Address Transition E =V

Min 0 0 ns

WHDX

Write Enable High to Input Transition E =V

Min 0 0 ns

WHEH

Write Enable High to Chip Enable High Min 0 0 ns

WHGL

Write Enable High to Output Enable Low Min 150 150 ns

WHQV

Write Enable High to Output Valid Min 175 175 ns

WHWL

Write Enable High to Write Enable Low Min 20 20 ns

WLWH

Write Enable Low to Write Enable High E =V

Min 60 60 ns

QVPL

Output Va lid to Reset/Power -do wn Low Min 0 0 ns

M58BW016DT, M58BW016DB, M58BW016FT, M58BW016FB DC and AC parameters

47/70

Figure 13. Synchronous burst read (data valid from ‘n’ clock rising edge)

1. The M58BW016F first dat a output is synchronized wi th the clock ’s active edge, while the M58BW016D fi rst

data output is not synchron ized with the cloc k’s active edge.

2. In the M58BW016F devices the right access time depends on the clock frequency.

3. For further details, please refer to the section 3.2 Clo ck signal in burst mode in the application note

AN2461.

AI04409

DQ0-DQ31

A0-A18

VALID

tKHAX

n+2

n+1n

tKHLL

tLLKH

tELLL

tAVLL

tKHLX

tEHQX

tEHQZ

tGHQX

tGHQZ

tGLQV

Setup

OUTPUT

tKHQV tQVKH

tAVQV

Note: n depends on Burst X-Latency.

DC and AC parameters M58BW016DT, M58BW016DB, M58BW016FT, M58BW016FB

48/70

Figure 14. Synchronous burst read (data valid from ‘n’ clock rising edge)

1. For set up signals and timings see synchronous burst read.

Table 20. Syn chrono us bur st read AC characterist ics

(1)

1. For other timings see Table 16: Asynchronous bus read AC characteristics.

Symbol Parameter Test condition M58BW016 Unit

70 80

AVLL

Address Valid to Latch Enable Low E =V

Min 0 0 ns

BHKH

Burst Address Advance High to Valid

Clock Edge E=V

, G =V

, L =V

Min 8 8 ns

BLKH

Burst Address Advance Low to Valid

Clock Edge E=V

, G =V

, L =V

Min 8 8 ns

ELLL

Chip Enable Low to Latch Enable Low Min 0 0 ns

GLQV

Output Enable Low to Output Valid E =V

, L =V

Min 25 25 ns

KHAX

Valid Clock Edge to Address

Transition E=V

Min 5 5 ns

KHLL

Valid Clock Edge to Latch Enable Low E =V

Min 0 0 ns

KHLX

Valid Clock Edge to Latch Enable

Transition E=V

Min 0 0 ns

KHQX

Valid Clock Edge to Output Transit ion E=V

G=V

L=V

M58BW016DT/B Min 3 3 ns

M58BW016FT/B Min 3 3 ns

LLKH

Latch Enable Low to Valid Clock Edge E =V

M58BW016DT/B Min 6 6 ns

M58BW016FT/B Min 5 5 ns

QVKH(2)

2. Data output sho uld be read on the valid clock edge.

Output Valid to Valid Clock Edge E =V

, G =V

, L =V

Min 6 6 ns

RLKH

Valid Data Ready Low to Valid Clock

Edge E=V

, G =V

, L =V

Min 6 6 ns

KHQV

Valid Clock Edge to Output Valid E =V

, G =V

, L =V

Max 11 11 ns

AI04408b

n+5

n+4

n+3

n+2

n+1

DQ0-DQ31

tQVKH

tKHQX

Q0 Q1 Q2 Q3 Q4 Q5

SETUP Burst Read

Q0 to Q3

tKHQV

Note: n depends on Burst X-Latency

M58BW016DT, M58BW016DB, M58BW016FT, M58BW016FB DC and AC parameters

49/70

Figure 15. Synchronous burst read - continuous - valid data ready output

1. Valid Data Ready = Valid Low during valid clock edge.

2. V= Valid ou tput.

3. R is an open drain output wi th an inte rnal pul l up resi sto r of 1 MΩ

The internal timing of R follows DQ. An extern al resi stor,

typically 300 kΩ

for a single memory on the R bus, should be used to give the data v alid set up time required to recognize

that valid data is available on the next v alid clock edge.

Figure 16. Synchronous burst read - burst address advance

AI03649

Output (1) VVVV

tRLKH

(2)

AI03650

ADD Q0 Q1

ADD VALID

tGLQV

tBLKH tBHKH

DC and AC parameters M58BW016DT, M58BW016DB, M58BW016FT, M58BW016FB

50/70

Figure 17. Reset, power-down and power-up AC waveforms - control pins low

Figure 18. Reset, power-down and power-up AC waveforms - control pins toggling

AI14240

tPHWL

tPHEL

tPHGL

G, E

VDD, VDDQ

tVDHPH

tPHWL

tPHEL

tPHGL

tPLPH

tPLRZ

Power-up Reset

LtPHLL

Hi-Z Hi-Z

tPHRH

AI14241

tPHWL

tPHEL

tPHGL

G, E

VDD, VDDQ

tVDHPH tPLPH

tPLRZ

Power-up Reset

LtPHLL

Hi-Z Hi-Z

tPHRH tPHRH

tGLRH

tELRH

tLLRH

tWLRH

M58BW016DT, M58BW016DB, M58BW016FT, M58BW016FB DC and AC parameters

51/70

Figure 19. Power supply slope specification

1. Please refer to the applicati on note AN2601.

Table 21. Power supply AC and DC characteristics

Symbol Description Min Max Unit

Minimum value of power supply 2.7 V

DHH

Maximum value of power supply 3.6 V

VDH

Time required from power supply to reach the V

value 50 50000 µs

Table 22. Reset, power-down and power-up AC characteristics

Symbol Parameter Min Max Unit

PHEL

Reset/Power-down High to Chip Enable Low 50 n s

PHLL

Reset/Power-down High to Latch Enable Low 50 ns

PHQV(1)

1. This time is t

PHEL

+ t

AVQV

or t

PHEL

+ t

ELQV

Reset/Power-down High to Output Valid 95 n s

PHWL

Reset/Power-down High to Write Enable Low 50 ns

PHGL

Reset/Power-down High to Output Enable Low 50 n s

PLPH

Reset/Power-down Low to Reset/Powe r-dow n High 100 n s

PHRH(1)

Reset/Power-down High to Valid Data Ready High 95

VDHPH

Supply voltages High to Reset/Power-down High M58BW016DT/B 10 µs

M58BW016FT/B 50 µs

PLRZ

Reset/Power-down Low to Data Ready High Impedan ce 80 ns

WLRH

Write Enable Low to Data Ready High Impedance 80 ns

GLRH

Output Enable Low to Data Ready High Impedance 80 ns

ELRH

Chip Enable Low to Data Ready High Impedance 80 n s

LLRH

Latch Enable Low to Data Ready High Impedance 80 ns

PLRH

Reset/PowerDown Low to Flash Ready 30 µs

AI14230b

VDH

VDHH

Voltage

Time

tVDH

Packag e mech anical M58BW0 16D T, M5 8B W016DB, M58BW01 6FT, M58BW016 FB

52/70

8 Package mechanical

In order to meet environm ental require m ents, Numonyx offers thes e devices in RoHS

packages, which are lead-free. The category of second level interconnect is marked on the

package and on the inner box label, in compliance with JEDEC Standard JESD97. The

maximum ratings related to soldering conditions are also marked on the inner box label.

Figure 20. PQFP80 - 80 lead plastic quad flat pack, package outline

1. Drawing is not to scal e.

QFP-B

LA1 α

M58BW016DT, M58BW016DB, M58BW016FT, M58BW016FB Package mechanical

53/70

Table 23. PQFP80 - 80 lead plastic quad flat pack, package mechanical data

Symbol millimeters inches

Typ Min Max Typ Min Max

A 3.40 0.134

A1 0.25 0.010

A2 2.80 2.55 3.05 0.110 0.100 0.120

b 0.30 0.45 0.012 0.018

c 0.13 0.23 0.005 0.009

D 23.20 22.95 23.45 0.913 0.903 0.923

D1 20.00 19.90 20.10 0.787 0.783 0.791

D2 18.40 – – 0.724 – –

e0.80– –0.031– –

E 17.20 16.95 17.45 0.677 0.667 0.687

E1 14.00 13.90 14.10 0.551 0.547 0.555

E2 12.00 – – 0.472 – –

L 0.80 0.65 0.95 0.031 0.026 0.037

L1 1.60 – – 0.063 – –

a0°7°0°7°

N80 80

Nd 24 24

Ne 16 16

Packag e mech anical M58BW0 16D T, M5 8B W016DB, M58BW01 6FT, M58BW016 FB

54/70

Figure 21. LBGA80 10 × 12 mm - 8 × 10 active ball array, 1 mm pitch, package

outline

1. Drawing is not to scal e.

Table 24 . LBGA80 10 × 12 mm - 8 × 10 active ball array, 1 mm pitch, packa ge

mechanical data

Symbol millimeters inches

Typ Min Max Typ Min Max

A 1.60 0.063

A1 0.40 0.016

A2 1.05 0.041

b 0.60 0.024

D 10.00 – – 0.394 – –

D1 7.00 – – 0.276 – –

ddd 0.15 0.006

E 12.00 – – 0.472 – –

E1 9.00 – – 0.354 – –

e 1.00 0.039

FD 1.50 – – 0.059 – –

FE 1.50 – – 0.059 – –

SD 0.50 0.020

SE 0.50 0.020

E1E

JE_ME

ddd

FE SD

BALL "A1"

M58BW016DT, M58BW016DB, M58BW016FT, M58BW016FB Ordering information

55/70

9 Ordering information

Note: Devices are shipped from the factory with the memory content bits erased to ’1’.

For a l is t of availab le options (spee d, pack ag e, e t c .) or for fu rther infor mat i on on an y as pect

of th is device, please co ntact the Numonyx Sales Office nearest to you.

Table 25. Ordering information scheme

Example: M58BW016D T 8 T 3 F T

Device type

M58

Architecture

B = Burst mode

Operating voltage

W = V

= 2.7 V to 3.6 V; V

DDQ

= V

DDQIN

= 2.4 to V

Device function

016D = 16-Mbit (x 32), boot block, burst, 0.15 µm

016F = 16-Mbit (x 32), boot block, burst, 0.11 µ m

Array matrix

T = Top boo t

B = Bottom boot

Speed

7 = 70 ns

8 = 80 ns (only available in the M58BW016D devices)

Package

T = PQFP80

ZA = LBGA 10 × 12 mm

Temperature range

3 = automotive grade certified

(1)

, –40 to 125 °C

1. Qualified & characteriz ed accordin g to AEC Q100 & Q00 3 or equivalen t, advanced s creening accordi ng to

AEC Q001 & Q002 or equivalent.

Version

F = silicon version F (only available in the M58BW016D devices)

Option

T = Tape and reel packing

F = RoHS package, tape and reel packing

Common Flash interface (C FI) M58BW0 16D T, M58BW016DB, M58B W016FT, M58BW0 16 FB

56/70

Appendix A Common Flash interface (CFI)

The common Flash interface is a JEDEC approved, standardized data structure that can be

read from the Fl ash memory device. It allows a system software to query the dev ice to

determine various electrical and timing parameters, density information and functions

supporte d by the memory. The system can interface easily with the device, enabling the

software to upgrade itself when necessary.

When the CFI Query c o m m an d ( RC FI) i s i s su ed the device enters CFI quer y mode and the

dat a struc ture is read f rom the m emory. Table 26, Table 27, Table 28, Table 29 and Table 30

show the addresses used to retrieve the data.

Table 26. Query st r uct ure overvi ew

Offset Sub-section name Description

00h Manufacturer code

01h Device code

10h C FI Query identificatio n string Command set ID and algorithm data offset

1Bh System interface information Device timing and voltage information

27h D evice geom et ry definition Flash memory layout

P(h)

(1)

1. Offset 15h defines P which points to the primary algorithm extended query address table.

Primary algorithm-specific extended query

table Additional information specific to the primary

algorithm (optional)

A(h)

(2)

2. Offset 19h defines A which points to the alternate algorithm extended query address table.

Alternate algorithm-specific extended query

table Additional information specific to the

alternate algorithm (optional)

Table 27. CFI - query address and data output

(1)(2)

1. The x 8 or byte address and the x 16 or word address mode are not available.

2. Query data are always presented on DQ7-DQ0. DQ31-DQ8 are set to '0'.

Address

A0-A18 Data Instruction

10h 51h "Q" 51h ; ‘Q’

Query ASCII String 52h; ‘R’

59h; ‘Y’

11h 52h "R"

12h 59h "Y"

13h 03h Primary vendor:

Command set and control interface ID code

14h 00h

15h 35h Primary algorithm extended quer y addre ss table:

P(h)

16h 00h

17h 00h Alternate vendor:

Command Set and Control interface ID code

18h 00h

19h 00h Alternate algorithm extended query address table

1Ah 00h

M58BW016DT, M58BW016DB, M58BW016FT, M58BW016FB Common Flash interface (CFI)

57/70

Table 28 . CFI - dev i ce voltage and timing sp ecifica t ion

Address

A0-A18 Data Description

1Bh 27h

(1)

1. Bits are coded in bi nary code deci m al, bit7 to bit4 are scaled in Vol ts and bit3 to bit0 in mV.

min, 2.7 V

1Ch 36h

(1)

max, 3 . 6 V

1Dh B4h

(2)

2. Bit7 to bit 4 are coded in hexadeci mal and scaled in Volts while bit3 to bit0 are in binary code deci ma l and

scaled in 100 mV.

min

1Eh C6h

(2)

max

1Fh 04h 2

ms typical time-out for Word, DWord prog – not available

20h 00h 2

ms, typical time-out for max buffer write – not available

21h 0Ah 2

ms, typical time-out for Erase Block

22h 00h 2

ms, typical time-out for chip erase – not avail able

23h-24h Reserved

25h 04h 2

x typical for individual block erase time-out maxim um

26h 00h 2

x typical for chip erase max time-out – not available

Table 29. Device geometry definition

Address

A0-A18 Data Description

27h 15h 2

number of bytes memory size

28h 03h Device interface sync./as y nc.

29h 00h Organization sync./async.

2Ah 00h Page size in bytes, 2

2Bh 00h

2Ch 02h Bit7-0 = number of erase block regions in device

2Dh 1Eh Number (n-1) of blocks of identical size; n=31

2Eh 00h

2Fh 00h Erase block region information x 256 bytes per erase block

(64 Kbytes)

30h 01h

31h 07h Number (n-1) of blocks of identical size; n=8

32h 00h

33h 20h Erase block region information x 256 bytes per erase block

(8 Kbytes)

34h 00h

Common Flash interface (C FI) M58BW0 16D T, M58BW016DB, M58B W016FT, M58BW0 16 FB

58/70

Table 30. Extended query information

Address

offset Address

A18-A0 Data (Hex) Description

(P)h 35h 50h "P"

Query ASCII string - extended table(P+1)h 36h 52h "R"

(P+2)h 37h 49h "Y"

(P+3)h 38h 31h Major version number

(P+4)h 39h 31h Minor version number

(P+5)h 3Ah 86h

Optional feature: (1=yes, 0=no)

bit0, Chip Erase supported (0=no)

bit1, Suspend Erase supported (1=yes)

bit2, Suspend Program supported (1=yes)

bit3, Lock/Unlock supported (1=yes)

bit4, Queue Erase supported (0=no)

bit 3 1 -5 reserve d for future u se

(P+6)h 3Bh 01h

Optional features: synchrono us read supp orted(P+7)h 3Ch 00h

(P+8)h 3Dh 00h

(P+9)h 3Eh 01h Function allowed after suspend:

Program allowed after Erase Suspend (1=yes)

Bit 7-1 reserved for future use

(P+A)h 3Fh Reserved

M58BW016DT, M58BW016DB, M58BW016FT, M58BW016FB Flowcharts

59/70

Appendix B Flowcharts

Figure 22. Program flowchart and pseudocode

1. If an error is found, the st atus register must be cleared before further program/erase operations.

Write 40h

AI03850b

Start

Write Address

& Data

Read Status

YES

b7 = 1

YES

b3 = 0

b4 = 0

VPP Invalid

Error (1)

Program

Error (1)

Program Command:

– write 40h

– write Address & Data

(memory enters read status

state after the Program command)

do:

– read status register

(E or G must be toggled)

while b7 = 0

If b3 = 1, VPP invalid error:

– error handler

If b4 = 1, Program error:

– error handler

YES

End

b1 = 0 Program to Protect

Block Error If b1 = 1, Program to Protected Block Error:

– error handler

YES

Flowchart s M58BW016DT, M58BW016D B, M58BW016FT, M58 BW0 16 FB

60/70

Figure 23. Program suspend & resume flowchart and pseudocode

Write 70h

AI00612b

Read Status

YES

b7 = 1

YES

b2 = 1

Program Continues

Write FFh

Program/Erase Suspend Command:

– write B0h

– write 70h

do:

– read status register

while b7 = 0

If b2 = 0, Program completed

Read Memory Array Command:

– write FFh

– one or more data reads

from other blocks

Write D0h Program Erase Resume Command:

– write D0h

to resume erasure

– if the program operation completed

then this is not necessary. The device

returns to Read Array as normal

(as if the Program/Erase Suspend

command was not issued).

Read data from

another block

Start

Write B0h

Program Complete

Write FFh

Read Data

M58BW016DT, M58BW016DB, M58BW016FT, M58BW016FB Flowcharts

61/70

Figure 24. Block erase flowchart and pseudocode

1. If an error is found, the st atus register must be cleared before further program/ erase operations.

Write 20h

AI03851b

Start

Write Block Address

& D0h

Read Status

YES

b7 = 1

YES

b3 = 0

YES

b4 and b5

= 1

VPP Invalid

Error (1)

Command

Sequence Error

Erase Command:

– write 20h

– write Block Address

(A11-A18) & D0h

(memory enters read status

state after the Erase command)

do:

– read status register

(E or G must be toggled)

if Erase command given execute

suspend erase loop

while b7 = 0

If b3 = 1, VPP invalid error:

– error handler

If b4, b5 = 1, Command Sequence error:

– error handler

b5 = 0 Erase

Error (1)

YES

Suspend

Loop

If b5 = 1, Erase error:

– error handler

YES

End

YES

b1 = 0 Erase to Protected

Block Error If b1 = 1, Erase to Protected Block Error:

– error handler

Flowchart s M58BW016DT, M58BW016D B, M58BW016FT, M58 BW0 16 FB

62/70

Figure 25. Erase suspend & resu m e flowchart and pseudocode

Write 70h

AI00615b

Read Status

YES

b7 = 1

YES

b6 = 1

Erase Continues

Write FFh

Program/Erase Suspend Command:

– write B0h

– write 70h

do:

– read status register

while b7 = 0

If b6 = 0, Erase completed

Read Memory Array command:

– write FFh

– one or more data reads

from other blocks

Write D0h

Read data from

another block

or Program

Start

Write B0h

Erase Complete

Write FFh

Read Data

Program/Erase Resume command:

– write D0h to resume the Erase

operation

– if the Erase operation completed

then this is not necessary. The device

returns to Read mode as normal

(as if the Program/Erase suspend

was not issued).

M58BW016DT, M58BW016DB, M58BW016FT, M58BW016FB Flowcharts

63/70

Figure 26. Power-up sequence followed by synchronous burst read

AI03834b

Power-up

or Reset

Asynchronous Read

Write 60h command

Write 03h with A15-A0

BCR inputs

Synchronous Read

BCR bit 15 = '1'

Set Burst Configuration Register Command:

– write 60h

– write 03h

and BCR on A15-A0

BCR bit 15 = '0'

Flowchart s M58BW016DT, M58BW016D B, M58BW016FT, M58 BW0 16 FB

64/70

Figure 27. Comma nd interface and program/erase controller flowc har t (a)

AI03835

READ ELEC.

SIGNATURE

YES

90h

READ

STATUS

YES

70h NO

ERASE

SET-UP

YES

20h NO

PROGRAM

SET-UP

YES

40h NO

CLEAR

STATUS

YES

50h NO

WAIT FOR

COMMAND

WRITE

READ

STATUS

READ

ARRAY

YES

READ CFI

YES

98h NO

NO D0h

ERASE

COMMAND

ERROR E

M58BW016DT, M58BW016DB, M58BW016FT, M58BW016FB Flowcharts

65/70

Figure 28. Command interface and program/erase controller flowchart (b)

AI03836b

SET BCR

SET_UP

YES

60h NO

FFh

03h

YES

Flowchart s M58BW016DT, M58BW016D B, M58BW016FT, M58 BW0 16 FB

66/70

Figure 29. Command interface and program/erase controller flowchart (c)

READ

STATUS

70h

ERASE

READY

B0h NO READ

STATUS

YES READY

ERASE

SUSPEND

YES

READ

ARRAY

YES

ERASE

SUSPENDED

READ

STATUS YES

40h

D0h

PROGRAM

SET_UP

AI03837

YES

NO YES READ

STATUS

M58BW016DT, M58BW016DB, M58BW016FT, M58BW016FB Flowcharts

67/70

Figure 30. Command interface and program/erase controller flowchart (d)

READ

STATUS

70h

PROGRAM

READY

B0h NO READ

STATUS

YES READY

PROGRAM

SUSPEND

READ

ARRAY

YES

PROGRAM

SUSPENDED

READ

STATUS YES

D0h

AI03838

YES

NO YES READ

STATUS

YES

Revi sion  hist ory M58BW016DT, M58BW01 6D B, M58B W01 6FT, M58BW016FB
68/70   
10 Revision history
          
Table 31. Document revision history
Date Version Changes
January-2001 01 First Issue.
05-Jun-2001 02 Major rewrite and restructure.
15-Jun-2001 03 Nd and Ne values changed in PQFP80 package mechanical table.
17-Jul-2001 0 4 PQFP8 0 package outline draw ing and mechanical data table updated.
17-Dec-2001 05
t
LEAD
 removed from absolute maximum rati ngs (Table 12).
80, 90 and 100 ns speed classes defined (Table 16, Table 17, Table 18, 
Table 19 and Table 20 clarified accordingly).
Figure 13, Figure 14, Figure 15 and Figure 16 clarified.
Tem pera ture range 3 and 6 added.
Table 13, Table 14, Table 15, Table 22 and CFI Table 27, Table 28, 
Table 29, Table 30 clarified.
Document status changed from Product Preview to Preliminary Data.
17-Jan-2002 06 DC characteristics I
PP
, I
PP1
 and I
DD1
 clarified.
AC Bus Read characteristics  timing t
GHQZ
 clarified.
30-Aug-2002 6.1
Revision numbering modified: a minor revision will be indicated by 
incrementing the tenths digit, and a major revision, by incrementing the 
units digit  of t he previous version (e.g. revision version 06 becomes 6.0).
References of V
PP
 pin used for block protection purposes removed. 
Figure 8 modified.
4-Sep-2002 7.0 Datasheet status changed from Preliminary Data to full Datasheet.
t
WLWH 
parameter modified in Table 19: Asynchronous write and latch 
controlled write AC characteristics.
13-May-2003 7.1 Revision history moved to end of document. V
PP
 clarified in Program 
and Block Erase commands and Status Register, V
PP
 Status bit. V
PPLK 
added to DC characte ristics table. Timing t
KHQV
 modified.
16-Oct-2003 7.2 Silicon Version added to Ordering Information Scheme.
03-Mar-2005 8
Tuning block protection feature removed from the who le docu men t and 
root part numbers M58BW016BT/B have been  remo ved.
Figure 22, Figure 23, Figure 24, Figure 25, Figure 26 and Figure 28 
updated.
LBGA80 package (ZA) removed. Lead-free option added.
90 and 100 ns access times removed and 70 ns added.
Tem pera ture rage 6 removed from Table 25: Ordering information 
scheme.
06-Sep-2005 9 Load capacitance updated in Table 13: Operating and AC measurement 
conditions.
3-Mar-2006 10 Updated Table 25: Ordering information scheme on page 55 and 
Disclaimer information. Converted document to new template.
16-Jun-2006 11 M58BW016FT and M58BW016FB part numbers added. Small text 
changes.

M58BW016DT, M58BW016DB, M58BW016FT, M58BW016FB Revision history
 69/70
09-Nov-2006 12
LBGA80 package added (see Figure 21 and Table 24).
M58BW016FT and M58BW016FB behavior in Burst mode specified 
under Section 3.2.1: Synchronous burst read.
I
DDB
, I
DD1
 and I
DD4
 current values specified for M58BW016FT and 
M58BW016FB in Table 15: DC characteristics, I
DD5
 added.
t
VDHPH
 specified for M58BW016FT and M58BW016FB in Table 22: 
Reset, power-down and power-up AC characteristics.
t
KHQX
 specified for M58BW016FT and M58BW016FB in Table 20: 
Synchronous burst read AC characteristics .
23h-24h reserved in Table 28: CFI - device voltage and timing 
specification. 3Fh reserved in Table 30: Extended query information.
24-Nov-2006 13 I
DD
 current specified for M58BW016DT/B and M58BW016FT/B in 
Table 15: DC characteristics.
05-Oct-2007 14
Table 7: Burst configuration register and Table 22: Reset, power-down 
and power-up AC characteristics updated.
Mo dified values for t
LLKH
 in Table 20: Synchronous burst read AC 
characteristics.
Figure 17: Reset, power-down and power-up AC waveforms - control 
pins low updated and Figure 18: Reset, power-down and power-up AC 
waveforms - control pins toggling added.
Small text changes.
16-Jan-2008 15
Added: Figure 19: Power supply slope specification and Table 21: Power 
supply AC and DC characteristics.
Changed mechanical data of the LBGA package and the description for 
the 010 value of M13 M11 bits in Table 7: Burst configuration register.
Minor text changes.
12-Mar-2008 16
Added: information on data retention and reliability level on page 1, not e 
3 below Table 7: Burst configuration register, and note 1, 2, 3 below 
Figure 13: Synchronous burst read (dat a valid from ‘n’ clock rising edge).
Modified: note 2 below Table 7: Burst configuration register and 
Table 25: Ordering information scheme .
Minor text changes.
26-Mar-2008 1 7 Applied Num onyx branding.
8-July-2011 18
On cover page, revised from “WP pin for write protect of the 4 outermost 
parameter blocks and all main blocks” to “WP pin for write protect of the 
2 outermost parameter blocks and all main blocks”
In Table 20.: Synchronous burst read AC characteristics, revised tKHQX 
(M58BW016FT/B) values from 2 to 3.
In Table 21.: Power supply AC and DC characteristics, revised tVDH 
value from 300 to 50
In Table 22.: Reset, power-down and power-up AC characteristics, 
added tPLRH.
Table 31. Document revision history (continued)
Date Version Changes

M58BW016DT, M58BW01 6D B, M58B W01 6FT, M58BW016 FB

70/70

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