YA20 2.5 Gb/s 1:16 Demultiplexer Data Sheet Features Data and clock inputs accept differential CML signals at up to 2.5 Gb/s Internally generated divide-by-16 clock and deserialized data delivered via PECL 100 k outputs Fully differential internal logic for improved noise performance The Nortel Networks YA20 1:16 Demultiplexer assembles a 2.5 Gb/s input datastream into 16-bit wide 155 Mb/s parallel data. For maximum flexibility it is configured to interface with an external clock and data recovery device such as the Nortel Networks YA18. The CML inputs of the YA20 are configured to interface directly with the YA18 Clock and Data Recovery device. The YA20 provides for power and chipcount savings that translate into better utilization of board real-estate and ultimately cost savings to the designer of fibre-based datacom or telecom solutions. The device is fabricated using a high yield, silicon bipolar process. Each product is available in an industry-standard package. Typical power dissipation 960 mW Single 3.3 V supply for simplified system integration Industry standard LQFP package YA19 Tightly controlled output propagation delays across the 16 outputs SONET/SDH-based transmission systems, test equipment and modules WDM for 2.5 Gb/s SONET applications ATM over SONET/SDH Section repeaters, muxes, terminators, broadband cross-connects 155 Mb/s 155 MHz Laser Diode Driver 2 16:1 Mux & Clk Gen Laser Diode 2.5 Gb/s Clk YA20 YA18 16 155 Mb/s Data 1:16 Demux Clk Figure 1: System Block Diagram AC10 Data 2.5 Gb/s 2 2 155 MHz 2 Clock & Data Recovery 2 AGC Post Amplifier AB89 2 Tz AMP OC-48 fibre optic modules and line termination Data Overhead Processor Applications YA08 16 PIN Clk 2.5GHz Receiver Module Functional Description The YA20 demultiplexes a single serial input stream, at up to 2.5 Gb/s, to parallel data on a 16-bit output bus at up to 155 Mb/s. The device is designed to be used with an external clock and data recovery function. The input is captured on the rising edge of the 2.5 GHz clock at the front end of a demultiplexer tree, from where it is progressively converted to 16 bit parallel data at 155 Mb/s. Output changes occur following the falling edge of a 155 MHz clock which is obtained by division from the 2.5 GHz input clock. This 155 MHz clock is also delivered differentially to output pins. Apart from standard decoupling capacitors, the only external components required are the PECL output termination resistors. The device operates from a single +3.3 V (5%) power supply. 2 YA20 2.5 Gb/s 1:16 Demultiplexer System Inputs System Outputs The clock and multiplexed data inputs CK2G5_INP/N and RXD_INP/N, which accept signals from a clock and data recovery device, are differential CML. They are terminated on-chip with 50 (nominal) resistors. Data output from the Nortel Networks YA18 Clock and Data Recovery Circuit will be changing on the falling edge of the 2.5 GHz clock and are read into the demultiplexer on the rising edge of CK2G5_INP. The 16-bit demultiplexed data is output to pins RXD_OUT0 to RXD_OUT15, which are single ended, unterminated, 100 k PECL outputs. The associated 155MHz clock on pins CK155_OUTP/N is of differential PECL type, again unterminated. Data transfer to the output bus is timed from the falling edge of CK155_OUTP as shown in the timing diagram, Figure 3. All PECL outputs are designed to be terminated externally with 50 resistors connected to a VCC-2 Volt supply. The serial data stream is mapped on to the output bus in conventional order, i.e.bit0 precedes bit1, etc. Since framing information is not extracted at this stage, the actual data bytes might be split across consecutive output words from the demultiplexer. The actual split is indeterminate, but will not change until loss-of-signal or loss-of-lock occurs in the receive path. The device is designed for frame coding to be recovered and utilized in a processor that follows the demultiplexing function. RX D _O UT0 R X D _IN P D E M U LT IP L E X E R TREE R X D _ IN N RX D _O UT15 C K 2 G 5_ IN P C K 1 55 _O U T P D IV ID E R C K 2G 5 _I N N C K 1 55 _O U T N Figure 2: Functional Block Diagram Absolute Maximum Ratings These are stress ratings only. Exposure to stresses beyond these maximum ratings may cause permanent damage to, or affect the reliability of, the device. Avoid operating the device outside the recommended operating conditions defined below. Symbol Parameter Min Max Unit VCC Supply voltage - any VCC pin -0.7 6.0 V VIcml CML input voltage - single ended wrt GND 0 VCC+0.5 V IOPECL Output current - PECL outputs -50 mA Tstg Storage temperature -65 135 C Recommended Operating Conditions Symbol Parameter Min Typ Max Unit VCC Supply voltage - any VCC pin 3.13 3.3 3.47 V VIDcml CML differential input voltage (peak) 60 350 750 mV VIcml CML input voltage, recommended overall range 2.15 VCC V Tamb Operating ambient temperature -40 85 C YA20 2.5 Gb/s 1:16 Demultiplexer 3 DC Electrical Characteristics Over recommended operating conditions. Outputs terminated in 50 to (VCC-2) Volts Symbol Parameter Min VOHpecl LVPECL output HIGH voltage VOLpecl LVPECL output LOW voltage RINdiff Differential input resistance 85 RINeff Effective signal input resistance 42 Icc Pd Typ Max Unit VCC-1.085 VCC-0.88 V VCC-1.83 VCC-1.555 V 100 115 50 58 Supply current 291 390 mA Device power dissipation 0.96 1.35 W Max Unit AC Characteristics Over recommended operating conditions. Outputs terminated in 50 to (VCC-2) Volts 4 Symbol Parameter TSUdi Data input SETUP time wrt CK2G5_INP rising edge 100 ps THdi Data input HOLD time wrt CK2G5_INP rising edge 100 ps TRpecl PECL output rise time 0.5 1.5 ns TFpecl PECL output fall time 0.5 1.5 ns CKmsr CK155_OUTP/N mark to space ratio 45 55 % Tpd Propagation delay from falling edge of CK155_OUT to RXD_OUTn 0.8 1.6 ns YA20 2.5 Gb/s 1:16 Demultiplexer Min Typ Design Procedure and Applications Information Timing Information Data inputs as delivered from the YA18 Clock and Data Recovery Circuit will be changing on the falling edge of the 2.5 GHz clock, hence they are read into the demultiplexer on the rising edge of CK2G5_INP, as shown in Figure 3 below. TSUdi THdi CK2G5_INP RXD_INP CK2G5_INP RXD_INP 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 CK155_OUTP RXD_OUTn TPD Figure 3: Signal Timing Diagram YA20 2.5 Gb/s 1:16 Demultiplexer 5 Input Interfacing As with other members of the OC-48/STM-16 2.5 Gb/s optical networking ICs family, the high speed (2.5 Gbps/2.5 GHz) inputs of the YA20 are configured as fully differential CML signal pairs as shown in Figure 4. The inputs are internally terminated with a 100 resistor between the differential inputs and require a typical differential peak voltage of 350 mV. However, the inputs to the YA20 will continue to operate correctly with a peak differential input voltage as low as 60 mV, see Figure 5. Although the YA20 is specifically designed CML OUTPUT ( YA18) to interface with the Nortel Networks YA18 Clock and Data Recovery device, it is possible to drive the inputs from a range of alternative differential signal sources with voltage levels of between 60 mV and 750 mV peak differential. CML INPUT ( YA20) VCC VCC OP 60 mV(min) 750 mV(max) 50 R 50 OPB R OP OPB 120 mVp-p(min) IP OP-OPB 1500 m Vp-p(m ax) 100 IPB R R Figure 5: CML Output Differential Voltage Levels GND Figure 4: CML Input and Output Configurations 6 YA20 2.5 Gb/s 1:16 Demultiplexer GND Pin Assignments Pin No Symbol Type Description Function 1, 8,25, 45 VCC_CORE P Positive supply pins for digital core 2,12,36 GND_CORE P Supply ground for digital core 3, 6, 9, 10, 14, 16 VCC_OUT1 P Positive supply pins for PECL outputs (CK155_OUTP/N and RXD_OUT0,1,2,3) 4 CK155_OUTN O PECL 100 K 155 MHz Clock differential negative output 5 CK155_OUTP O PECL 100 K 155 MHz Clock differential positive output 7 RXD_OUT0 O PECL 100 K Parallel data output, bit 0 (MSB) 11 RXD_OUT1 O PECL 100 K Parallel data output, bit1 13 RXD_OUT2 O PECL 100 K Parallel data output, bit2 15 RXD_OUT3 O PECL 100 K Parallel data output, bit3 17 RXD_OUT4 O PECL 100 K Parallel data output, bit4 18, 20, 22, 23, 27, 29 VCC_OUT2 P 19 RXD_OUT5 O PECL 100 K Parallel data output, bit5 21 RXD_OUT6 O PECL 100 K Parallel data output, bit6 24 RXD_OUT7 O PECL 100 K Parallel data output, bit7 Positive supply pins for PECL outputs (RXD_OUT4,5,6,7,8,9) YA20 2.5 Gb/s 1:16 Demultiplexer 7 Pin Assignments (continued) 8 Pin No Symbol Type Description Function 26 RXD_OUT8 O PECL 100 K Parallel data output, bit8 28 RXD_OUT9 O PECL 100 K Parallel data output, bit9 30 RXD_OUT10 O PECL 100 K Parallel data output, bit10 31, 33, 35, 38, 40, 42 VCC_OUT3 P 32 RXD_OUT11 O PECL 100 K Parallel data output, bit11 34 RXD_OUT12 O PECL 100 K Parallel data output, bit12 37 RXD_OUT13 O PECL 100 K Parallel data output, bit13 39 RXD_OUT14 O PECL 100 K Parallel data output, bit14 41 RXD_OUT15 O PECL 100 K Parallel data output, bit15 (LSB) 43 RXD_INN I CML Serial data negative differential input 44 RXD_INP I CML Serial data positive differential input 46 CK2G5_INN I CML 2.5 GHz clock negative differential input 47 CK2G5_INP I CML 2.5 GHz clock positive differential input YA20 2.5 Gb/s 1:16 Demultiplexer Positive supply pins for PECL outputs (RXD_OUT10,11,12,13,14,15) Package Pin Configuration N/C CK2G5_INP CK2G5_INN VCC_CORE RXD_INP RXD_INN VCC_OUT3 RXD_OUT15 VCC_OUT3 RXD_OUT14 VCC_OUT3 RXD_OUT13 48 47 46 45 44 43 42 41 40 39 38 37 The device is packaged in a 48-lead plastic low-profile quad flat pack (LQFP). To achieve the required thermal resistance, the package contains a heat slug which must be soldered directly to the circuit board. VCC_CORE 1 36 GND_CORE 28 RXD_OUT9 10 27 VCC_OUT2 RXD_OUT1 11 26 RXD_OUT8 GND_CORE 12 25 VCC_CORE 24 9 VCC_OUT1 RXD_OUT7 VCC_OUT1 VCC_OUT2 VCC_OUT2 23 29 22 8 VCC_OUT2 VCC_CORE 21 RXD_OUT10 RXD_OUT6 30 20 TOP VIEW VCC_OUT2 7 19 RXD_OUT0 RXD_OUT5 VCC_OUT3 VCC_OUT2 31 18 6 YA20 RXD_OUT11 VCC_OUT1 RXD_OUT4 VCC_OUT3 32 17 33 5 16 4 CK155_OUTP VCC_OUT1 RXD_OUT12 15 34 RXD_OUT3 3 CK155_OUTN 14 VCC_OUT3 VCC_OUT1 35 13 2 RXD_OUT2 GND_CORE VCC_OUT1 Figure 6: 48-lead LQFP YA20 2.5 Gb/s 1:16 Demultiplexer 9 Package Outline Drawing and Dimensions D D1 A A2 C Exposed Heatsink: 4.32 mm +/- 0.12 mm diam Intrusion: 0.0127 mm max On underside of package. B E A1 Figure 7: Package Outline Dimension Min (mm) Lead pitch (E) Nom (mm) 0.50 Body size (D1) 6.90 7.00 7.10 Component tip-to-tip (D) 8.80 9.00 9.20 Component height (A) 10 Max (mm) 1.60 Component standoff (A1) 0.05 Body thickness (A2) 1.35 1.40 1.45 Lead width, plated (B) 0.17 0.22 0.27 Lead thickness, plated (C) 0.09 YA20 2.5 Gb/s 1:16 Demultiplexer 0.15 0.20 Notes: Ordering information Please quote the Product Code from Table 1 below when ordering as this is the identification that appears on the part when shipped. Table 1: Product ordering information Product Code Product Name A0742187 (QMV1052-1AF5) YA20 1:16 Demultiplexer For additional information on Nortel Networks products and services offered, please contact your local representative. Nortel Networks High Performance Optical Component Solutions attn: Marketing Department 2745 Iris Street 6th Floor Ottawa, Ontario Canada K2C 3V5 Copyright 2001 Nortel Networks Corporation. All rights reserved. Nortel, Nortel Networks, the Nortel Networks corporate logo, and the globemark design are trademarks of Nortel Networks Corporation. Any third-party trademarks are the property of their respective owners. The information contained in this document is considered to be accurate as of the date of publication. No liability is assumed by Nortel Networks for use of any information contained in this document, or for infringement of any patent rights or any other proprietary rights of third parties which may result from such use. No license is granted by implication or otherwise under any patent right or any other proprietary right of Nortel Networks. Tel: 1-800-4 NORTEL Fax: 1-613-763-8416 Email: opticalcomponents@nortelnetworks.com www.nortelnetworks.com/hpocs Publication # 84005.37/03-01 Issue 3 Issued: 5 March 2001