The YA20 provides for power and chip-
count savings that translate into better
utilization of board real-estate and
ultimately cost savings to the designer of
fibre-based datacom or telecom solutions.
The device is fabricated using a high yield,
silicon bipolar process. Each product is
available in an industry-standard package.
Data Sheet
Features
Data and clock inputs accept
differential CML signals at up to
2.5Gb/s
Internally generated divide-by-16
clock and deserialized data
delivered via PECL 100 k outputs
Fully differential internal logic for
improved noise performance
Typical power dissipation 960 mW
Single 3.3V supply for simplified
system integration
Industry standard LQFP package
Tightly controlled output
propagation delays across
the 16 outputs
Applications
SONET/SDH-based transmission
systems, test equipment and
modules
OC-48 fibre optic modules and
line termination
WDM for 2.5 Gb/s SONET
applications
ATM over SONET/SDH
Section repeaters,muxes,
terminators, broadband
cross-connects
The Nortel Networks YA20 1:16
Demultiplexer assembles a 2.5 Gb/s input
datastream into 16-bit wide 155 Mb/s
parallel data. For maximum flexibility it is
configured to interface with an external
clock and data recovery device such as the
Nortel Networks YA18. The CML inputs
of the YA20 are configured to interface
directly with the YA18 Clock and Data
Recovery device.
YA202.5 Gb/s
1:16 Demultiplexer
Overhead Processor
AB89
Tz AMP
Laser Diode
Driver
Clk
2.5GHz
16
Clk
Clk
YA18
YA19
1:16
Demux
YA20
PIN
Receiver Module
YA08
155 Mb/s 2
2
2
155 MHz
Data
Data Data
Clock & Data
Recovery
AC10
AGC Post
Amplifier
22
16:1 Mux
& Clk Gen Laser
Diode
16
155 Mb/s
155 MHz
2.5 Gb/s
2.5 Gb/s
2
Figure 1: System Block Diagram
System Inputs
The clock and multiplexed data inputs
CK2G5_INP/N and RXD_INP/N,
which accept signals from a clock and
data recovery device, are differential
CML. They are terminated on-chip with
50 Ω(nominal) resistors. Data output
from the Nortel Networks YA18 Clock
and Data Recovery Circuit will be
changing on the falling edge of the 2.5
GHz clock and are read into the
demultiplexer on the rising edge of
CK2G5_INP.
System Outputs
The 16-bit demultiplexed data is output
to pins RXD_OUT0 to RXD_OUT15,
which are single ended, unterminated,
100 k PECL outputs. The associated
155MHz clock on pins
CK155_OUTP/N is of differential PECL
type, again unterminated. Data transfer
to the output bus is timed from the
falling edge of CK155_OUTP as shown
in the timing diagram, Figure 3. All
PECL outputs are designed to be
terminated externally with 50 Ωresistors
connected to a VCC-2 Volt supply.
The serial data stream is mapped on to
the output bus in conventional order,
i.e.bit0 precedes bit1, etc. Since framing
information is not extracted at this stage,
the actual data bytes might be split across
consecutive output words from the
demultiplexer. The actual split is
indeterminate, but will not change until
loss-of-signal or loss-of-lock occurs in the
receive path. The device is designed for
frame coding to be recovered and utilized
in a processor that follows the
demultiplexing function.
YA20 2.5 Gb/s 1:16 Demultiplexer
2
Functional Description
The YA20 demultiplexes a single serial
input stream, at up to 2.5 Gb/s, to
parallel data on a 16-bit output bus at up
to 155 Mb/s. The device is designed to be
used with an external clock and data
recovery function. The input is captured
on the rising edge of the 2.5 GHz clock
at the front end of a demultiplexer tree,
from where it is progressively converted
to 16 bit parallel data at 155 Mb/s.
Output changes occur following the
falling edge of a 155 MHz clock which is
obtained by division from the 2.5 GHz
input clock. This 155 MHz clock is also
delivered differentially to output pins.
Apart from standard decoupling
capacitors, the only external components
required are the PECL output
termination resistors.
The device operates from a single +3.3 V
(±5%) power supply.
YA20 2.5 Gb/s 1:16 Demultiplexer 3
Absolute Maximum Ratings
These are stress ratings only. Exposure to stresses beyond these maximum ratings may cause permanent damage to, or affect the reliability
of, the device. Avoid operating the device outside the recommended operating conditions defined below.
Symbol Parameter Min Max Unit
VCC Supply voltage – any VCC pin -0.76.0V
VIcml CML input voltage – single 0VCC+0.5V
ended wrt GND
IOPECL Output current – PECL outputs -50 mA
Tstg Storage temperature -65 135 ˚C
Recommended Operating Conditions
Symbol Parameter Min Typ Max Unit
VCC Supply voltage – any VCC pin 3.13 3.33.47 V
VIDcml CML differential input voltage (peak) 60 350 750 mV
VIcml CML input voltage, 2.15 VCC V
recommended overall range
Tamb Operating ambient temperature -40 85 ˚C
RXD_INN
RXD_INP
DEMULTIPLEXER
TREE
CK2G5_INN
CK2G5_INP DIVIDER
RXD_OUT15
CK155_OUTP
CK155_OUTN
RXD_OUT0
Figure 2: Functional Block Diagram
YA20 2.5 Gb/s 1:16 Demultiplexer
4
DC Electrical Characteristics
Over recommended operating conditions. Outputs terminated in 50 Ωto (VCC-2) Volts
Symbol Parameter Min Typ Max Unit
VOHpecl LVPECL output HIGH voltage VCC-1.085 VCC-0.88 V
VOLpecl LVPECL output LOW voltage VCC-1.83 VCC-1.555 V
RINdiff Differential input resistance 85 100 115 Ω
RINeff Effective signal input resistance 42 50 58 Ω
Icc Supply current 291 390 mA
Pd Device power dissipation 0.96 1.35 W
AC Characteristics
Over recommended operating conditions. Outputs terminated in 50 Ωto (VCC-2) Volts
Symbol Parameter Min Typ Max Unit
TSUdi Data input SETUP time wrt 100 ps
CK2G5_INP rising edge
THdi Data input HOLD time wrt 100 ps
CK2G5_INP rising edge
TRpecl PECL output rise time 0.51.5ns
TFpecl PECL output fall time 0.51.5ns
CKmsr CK155_OUTP/N mark to space ratio 45 55 %
Tpd Propagation delay from falling edge 0.8 1.6 ns
of CK155_OUT to RXD_OUTn
YA20 2.5 Gb/s 1:16 Demultiplexer 5
Design Procedure and Applications Information
Timing Information
Data inputs as delivered from the YA18 Clock and Data Recovery Circuit will be changing on the falling edge of the 2.5 GHz clock,
hence they are read into the demultiplexer on the rising edge of CK2G5_INP, as shown in Figure 3 below.
CK2G5_INP
RXD_INP
RXD_OUTn
CK155_OUTP
CK2G5_INP
RXD_INP
TPD
TSUdi THdi
1213141501234567891011121314
Figure 3: Signal Timing Diagram
YA20 2.5 Gb/s 1:16 Demultiplexer6
Input Interfacing
As with other members of the
OC-48/STM-16 2.5 Gb/s optical
networking ICs family, the high speed
(2.5 Gbps/2.5 GHz) inputs of the YA20
are configured as fully differential CML
signal pairs as shown in Figure 4. The
inputs are internally terminated with
a 100 Ωresistor between the differential
inputs and require a typical differential
peak voltage of 350 mV. However, the
inputs to the YA20 will continue to operate
correctly with a peak differential input
voltage as low as 60 mV, see Figure 5.
Although the YA20 is specifically designed
to interface with the Nortel Networks
YA18 Clock and Data Recovery device, it is
possible to drive the inputs from a range of
alternative differential signal sources with
voltage levels of between 60 mV and
750 mV peak differential.
GND
R
RR
R
100
IP
IPB
VCC
CML OUTPUT ( YA18)
VCC
50
OPB
OP
50
CML INPUT ( YA20)
GND
OP
OPB
OP-OPB
60 mV(min)
750 m V (m ax)
120 mVp-p(min)
1500 mVp-p(max)
Figure 4: CML Input and Output Configurations
Figure 5: CML Output Differential Voltage Levels
Pin Assignments
Pin No Symbol Type Description Function
1,8,25,45 VCC_CORE P Positive supply pins for digital core
2,12,36 GND_CORE P Supply ground for digital core
3,6,9,10,14,16 VCC_OUT1P Positive supply pins for PECL outputs
(CK155_OUTP/N and RXD_OUT0,1,2,3)
4CK155_OUTN O PECL 100 K155 MHz Clock differential negative output
5CK155_OUTP O PECL 100 K155 MHz Clock differential positive output
7RXD_OUT0O PECL 100 K Parallel data output, bit 0(MSB)
11 RXD_OUT1O PECL 100 K Parallel data output, bit1
13 RXD_OUT2O PECL 100 K Parallel data output, bit2
15 RXD_OUT3O PECL 100 K Parallel data output, bit3
17 RXD_OUT4O PECL 100 K Parallel data output, bit4
18,20,22,23,27,29 VCC_OUT2P Positive supply pins for PECL outputs (RXD_OUT4,5,6,7,8,9)
19 RXD_OUT5O PECL 100 K Parallel data output, bit5
21 RXD_OUT6O PECL 100 K Parallel data output, bit6
24 RXD_OUT7O PECL 100 K Parallel data output, bit7
YA20 2.5 Gb/s 1:16 Demultiplexer 7
YA20 2.5 Gb/s 1:16 Demultiplexer8
Pin Assignments (continued)
Pin No Symbol Type Description Function
26 RXD_OUT8O PECL 100 K Parallel data output, bit8
28 RXD_OUT9O PECL 100 K Parallel data output, bit9
30 RXD_OUT10 O PECL 100 K Parallel data output, bit10
31,33,35,38,40,42 VCC_OUT3P Positive supply pins for PECL outputs
(RXD_OUT10,11,12,13,14,15)
32 RXD_OUT11 O PECL 100 K Parallel data output, bit11
34 RXD_OUT12 O PECL 100 K Parallel data output, bit12
37 RXD_OUT13 O PECL 100 K Parallel data output, bit13
39 RXD_OUT14 O PECL 100 K Parallel data output, bit14
41 RXD_OUT15 O PECL 100 K Parallel data output, bit15 (LSB)
43 RXD_INN I CML Serial data negative differential input
44 RXD_INP I CML Serial data positive differential input
46 CK2G5_INN I CML 2.5GHz clock negative differential input
47 CK2G5_INP I CML 2.5GHz clock positive differential input
YA20 2.5 Gb/s 1:16 Demultiplexer 9
Package Pin Configuration
The device is packaged in a 48-lead plastic low-profile quad flat pack (LQFP). To achieve the required thermal resistance,
the package contains a heat slug which must be soldered directly to the circuit board.
YA20
TOP VIEW
1
2
3
4
5
6
7
8
9
10
11
12
36
35
34
33
32
31
30
29
28
27
26
25
GND_CORE
RXD_OUT12
RXD_OUT11
RXD_OUT10
RXD_OUT9
RXD_OUT8
VCC_CORE
GND_CORE
VCC_OUT1
CK155_OUTN
CK155_OUTP
RXD_OUT0
VCC_CORE
RXD_OUT1
GND_CORE
RXD_OUT2
RXD_OUT3
RXD_OUT4
RXD_OUT5
RXD_OUT6
RXD_OUT7
N/C
CK2G5_INP
CK2G5_INN
VCC_CORE
RXD_INP
RXD_INN
RXD_OUT15
RXD_OUT14
RXD_OUT13
VCC_OUT1
VCC_OUT1
VCC_OUT1
VCC_OUT3
VCC_OUT2
VCC_OUT2
VCC_OUT
3
VCC_OUT
3
VCC_OUT
3
VCC_OUT
2
VCC_OUT
2
VCC_OUT
2
VCC_OUT
2
VCC_OUT1
VCC_OUT1
VCC_OUT3
VCC_CORE
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
VCC_OUT3
Figure 6:48-lead LQFP
YA20 2.5 Gb/s 1:16 Demultiplexer10
Package Outline Drawing and Dimensions
Dimension Min (mm) Nom (mm) Max (mm)
Lead pitch (E) 0.50
Body size (D1)6.90 7.00 7.10
Component tip-to-tip (D) 8.80 9.00 9.20
Component height (A) 1.60
Component standoff (A1)0.05 0.15
Body thickness (A2)1.35 1.40 1.45
Lead width, plated (B) 0.17 0.22 0.27
Lead thickness, plated (C) 0.09 0.20
E
B
D
D1A
A2
C
A1
Exposed Heatsink:
4.32 mm +/- 0.12 mm diam
Intrusion: 0.0127 mm max
On underside of package.
Figure 7: Package Outline
Notes:
Table 1: Product ordering information
Product Code Product Name
A0742187 (QMV1052-1AF5) YA20 1:16 Demultiplexer
Ordering information
Please quote the Product Code from Table 1 below when
ordering as this is the identification that appears on the
part when shipped.
For additional information on Nortel Networks products and services
offered, please contact your local representative.
Nortel Networks
High Performance Optical Component Solutions
attn: Marketing Department
2745 Iris Street
6th Floor
Ottawa, Ontario
Canada K2C 3V5
Tel: 1-800-4 NORTEL
Fax: 1-613-763-8416
Email: opticalcomponents@nortelnetworks.com
www.nortelnetworks.com/hpocs
Copyright 2001 Nortel Networks Corporation. All rights reserved.
Nortel, Nortel Networks, the Nortel Networks corporate logo, and the globemark
design are trademarks of Nortel Networks Corporation. Any third-party trademarks
are the property of their respective owners.
The information contained in this document is considered to be accurate as of
the date of publication. No liability is assumed by Nortel Networks for use of any
information contained in this document, or for infringement of any patent rights
or any other proprietary rights of third parties which may result from such use.
No license is granted by implication or otherwise under any patent right or any
other proprietary right of Nortel Networks.
Publication # 84005.37/03-01 Issue 3Issued: 5 March 2001
