A DY A EPC1064/EPC1064V en Configuration EPROMs | December 1993, ver. 1 Data Sheet Supplement | This data sheet supplement must be used together with the Configuration EPROMs for FLEX 8000 Devices Data Sheet in the Altera 1993 Data Book. This supplement provides specifications for the 3.3-V EPC1064V device, and the dimensions for the 32-pin thin quad flat pack (TQFP) package available for EPC1064 and EPC1064V devices. Features (4 Serial EPROMs designed to configure FLEX 8000 devices Q 3.3-V operation provided by EPC1064V Q Available in the following one-time programmable (OTP) packages: - 32-pin thin quad flat pack (TQFP) (see Figure 1) - 8-pin plastic dual in-line (PDIP) - 20-pin plastic J-lead chip carrier (PLCC) QM Simple 4-wire interface to FLEX 8000 devices for ease of use 4 Low current during configuration (10 mA) and near-zero standby current (100 HA) 1 Software design support with Alteras MAX+PLUS II development system for IBM PC-AT, PS/2, and compatible computers, as well as for Sun SPARCstation, HP 9000 Series 700, and DEC Alpha AXP workstations 1 Programming support with Alteras Master Programming Unit (MPU) and programming hardware from other manufacturers, including Data I/O Figure 1. EPC1064/EPC1064V 32-Pin TQFP Package Pin-Out Diagram Package outline < Ook 6 Oo G6 oo not drawn to scale. Szeegegges ff fe Dj Cj iz ni 27 N.C. 1 2410 N.C. DCLK 2 230 VCC N.C. 3 22D NC. N.C. 210 NC. N.C 200 NC N.C is9AANC oE C7 EPC1064V 18 ONC. N.C. 8 417 ONC 9 6 11 #12 13 14 UJ a UJ L] 0 U U GRBGEBGS5Q SO 22282222 Oo 2 32-Pin TQFP Altera Corporation Page 1 A-DSS-EPC1064V-01EPC1064/EPC1064V Configuration EPROMs EPC1064V Absolute Maximum Ratings Data Sheet Supplement See Operating Requirements for Altera Devices in the 1993 Data Book. Symbol Parameter Conditions Min Max | Unit Voc Supply voitage With respect to GND -2.0 7.0 Vv vi DC input voltage Note (1) -2.0 7.0 v Imax DC Vcc or GND current 20 mA lout DC output current, per pin -25 25 mA Pp Power dissipation 100 mw Tst Storage temperature No bias -65 150 C Tame Ambient temperature Under bias ~65 135 c Ty Junction temperature Under bias 150 C EPC1064V Recommended Operating Conditions Symbol Parameter Conditions Min Max | Unit Veco Supply voltage With respect to GND 3.0 3.6 Vv Vv) Input vollage Note (1) 0 Voc Vv Vo Output voltage 0 Voc Vv Ta Operating temperature For commercial use 0 70 C Ta Operating temperature For industrial use 40 85 c To Case temperature For military use 55 125 C tr Input rise time 20 ns te tnput fail time 20 ns EPC1064V DC Operating Conditions _Notes (2), (3) Symbol Parameter Conditions Min Max | Unit Vin High-level input voltage 2.0 Veco + 0.3) V Vin Low-level input voltage -0.3 0.8 Vv Vou High-level output voltage lon = -0.1 mA DC Voc 0.2 Vv Voi Low-level output voltage lop = 4mA DC 0.45 v ', Input leakage current V, =Vec or GND -10 10 pA loz Tri-state output off-state current Vo =Vcc or GND 10 10 HA EPC1064V Supply Current Symbol Parameter Conditions Min Typ Max | Unit loco Vcc supply current (standby) 100 BA loc Voc supply current DCL = 8 MHz 10 mA (during configuration) Page 2 Altera Corporation| Data Sheet Supplement EPC1064V Capacitance Note (4) EPC1064/EPC1064V Configuration EPROMs Symbol Parameter Conditions Min Max | Unit Cin Input capacitance Vin = OV,f = 1.0 MHz 10 pF Court | Output capacitance Vout = OV,f = 1.0 MHz 10 pF EPC1064V Timing Parameters Symbol Parameter Conditions Min Max | Unit toezx = | C= high to DATA output enabled 75 ns teszx | .C Slow toDATA output enabled 75 ns tesxz | ncshigh te DATA output disabled 75 ns tess ncs low setup time to first DCLK rising edge 250 ns tesy ncs low hold time after DcLK rising edge 0 ns tosu Data setup time before rising edge on DcLK 75 ns ton Data hold time after rising edge on CLK 0 ns tco DCLK to DATA out delay, Note (5) 100 ns tex Clock period 240 ns fox Clock frequency 4 MHz tet DCLK low time 120 ns ton DCLK high time 120 ns txz OF low orncs high to DATA output disabled 75 ns toew OE pulse width to guarantee counter reset 150 ns tease | Last DcLK + 1 toncasclow delay 90 ns texxz | Last DCLX + 1 topaTA tri-state delay 75 ns teeout | ocshigh toncasc high delay 150 ns Notes to tables: (1) Minimum DC input is -0.3 V. During transitions, the inputs may undershoot to ~2.0 V or overshoot to 7.0 V for periods shorter than 20 ns under no-load conditions. (2) Typical values are for T, = 25 Cand Vcc = 3.3 V. (3) Operating conditions: Voc = 3.3 V + 10%, T, = 0 C to 70 C for commercial use. (4) Capacitance is sample-tested only. (5) Eight Clock cycles are required after the tegg setup time has been met to clock out the first eight bits. These bits are all high and are used to synchronize the configuration process. The ninth Clock cycle presents the first configuration data bit. Product Product Grade Availability Availability Commercial Temp. (0 C to 70 C) EPC1064V Industrial Temp. (40 C to 85 C) Consult factory Military Temp. (-55 C to 125 C) Consult factory Altera Corporation Page 3| EPC1064/EPC1064V Configuration EPROMs Data Sheet Supplement | Package Outlines Figure 2 shows the package outlines for the 32-pin TQFP package. For dimensions of the 8-pin PDIP and 20-pin PLCC packages, see the Alfera Device Package Outlines Data Sheet in the 1993 Data Book. Figure 2. 32-Pin Thin Plastic Quad Flat Pack (TQFP) For an explanation of the package outline dimensions, refer to Introduction in the Altera Device Package Outlines Data Sheet in the 1993 Data Book. Controlling measurement is in millimeters. 0.002 (0.05) 0.006 (0.15) 0.05 (1.27) 0.012 (0.30) 0.078 (0.48) PS as ee Detail a A t 0.031 an 0.005 (0.135) )) (0.80) 0.007 (0.180) he 0-7" f + i+ ee p/) 4 0.018 (0.45) 0.029 (0.75) 0.396 Ret. (1.00) LI Detail A NTETRN 2610 Orchard Parkway San Jose, CA 95134-2020 (408) 894-7000 Applications Hotline: (800) 800-EPLD Marketing Information: (408) 894-7000 Altera, MAX+PLUS, and MAX are registered trademarks of Altera Corporation. The following are trademarks of Altera Corporation: MAX+PLUS II, FLEX, FLEX 8000, EPC1064, and EPC1064V. Altera acknowledges the trademarks of other organizations for their respective products or services mentioned in this document, specifically: Data I/O is a registered trademark of Data 1/O Corporation. HP is a registered trademark and HP 9000 Series 700 is a trademark of Hewlett-Packard Company. IBM and AT are registered trademarks, and IBM PC-AT and PS/2 are trademarks of International Business Machines Corporation. SPARCstation is a trademark of SPARC International, Inc. and is licensed exclusively to Sun Microsystems, Inc. DEC and Alpha AXP are trademarks of Digital Equipment Corporation. Sun Workstation is a registered trademark, and Sun is a trademark of Sun Microsystems, Inc. Altera products marketed under trademarks are protected under numerous U.S. and foreign patents and pending applications, maskwork rights, and copyrights. Altera warrants performance of its semiconductor products to current specifications in accordance with Alteras standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera Corporation. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services. U.S. and European patents pending Copyright 1993 Altera Corporation | Page 4 Altera Corporation