®
ADC0801S040
Single 8 bits ADC, up to 40 MHz
Rev. 03 — 2 July 2012 Product data sheet
1. General description
The ADC0801S040 is an 8-bit universal analog-to-digital converter (ADC) for video and
general purpose applications. It converts the analog input signal from 2.7 V to 5.5 V into
8-bit binary-coded digital words at a maximum sampling rate of 40 MHz. All digital inputs
and outputs are CMOS/Transistor-Transistor Logic (TTL) compatible. A sleep mode
allows reduction of the device power consumption to 4 mW.
2. Features
8-bit resolution
Operation between 2.7 V and 5.5 V
Sampling rate up to 40 MHz
DC sampling allowed
High signal-to-noise ratio over a large analog input frequency range (7.3 effective bits
at 4.43 MHz full-scale input at fclk = 40 MHz)
CMOS/TTL compatible digital inputs and outputs
External reference voltage regulator
Power dissipation only 30 mW (typical value)
Low analog input capacitance, no buffer amplifier required
Sleep mode (4 mW)
No sample-and-hold circuit required
3. Applications
Video data digitizing
Camera
Camcorder
Radio communication
Car alarm system
3ADC0801S040_3 © IDT 2012. All rights reserved.
Product data sheet Rev. 03 — 2 July 2012 2 of 18
Integrated Device Technology
ADC0801S040
Single 8 bits ADC, up to 40 MHz
4. Quick reference data
Table 1. Quick reference data
VDDA = V5 to V6 = 3.3 V; VDDD = V3 to V4 = 3.3 V; VDDO = V20 to V11 = 3.3 V; VSSA, VSSD and VSSO
shorted together; Vi(a)(p-p) = 1.84 V; CL = 20 pF; Tamb = 0
C to 70
C; typical values measured at
Tamb = 25
C unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Unit
VDDA analog supply
voltage
2.7 3.3 5.5 V
VDDD digital supply
voltage
2.7 3.3 5.5 V
VDDO output supply
voltage
2.5 3.3 5.5 V
VDD supply voltage
difference
VDDA VDDD 0.2 -+0.2 V
VDDD VDDO 0.2 -+2.25 V
IDDA analog supply
current
- 46mA
IDDD digital supply
current
- 58mA
IDDO output supply
current
fclk = 40 MHz; ramp input;
CL = 20 pF
- 12mA
INL integral
non-linearity
ramp input; see Figure 6 - 0.5 0.75 LSB
DNL differential
non-linearity
ramp input; see Figure 7 - 0.25 0.5 LSB
fclk(max) maximum
clock
frequency
40 --MHz
Ptot total power
dissipation
VDDA = VDDD = VDDO = 3.3 V -30 53 mW
5. Ordering information
Table 2. Ordering information
Type number Package
Name Description Version
ADC0801S040TS SSOP20 plastic shrink small outline package; 20 leads; body width 4.4 mm SOT266-1
3ADC0801S040_3 © IDT 2012. All rights reserved.
Product data sheet Rev. 03 — 2 July 2012 3 of 18
Integrated Device Technology
ADC0801S040
Single 8 bits ADC, up to 40 MHz
6. Block diagram
7
9
Rlad
8
10
RB
RM
RT
VI
3
VDDD
5
VDDA
2
CMOS
OUTPUTS
LATCHES
CLOCK DRIVER
014aaa495
1
CLK
SLEEP
ADC0801S040
20 VDDO
6
VSSA
analog ground digital ground
4
VSSD
11
VSSO
output ground
analog
voltage input data outputs
LSB
MSB
19 D7
18 D6
17 D5
16 D4
15 D3
14 D2
13 D1
12 D0
ANALOG - TO - DIGITAL
CONVERTER
Fig 1. Block diagram
3ADC0801S040_3 © IDT 2012. All rights reserved.
Product data sheet Rev. 03 — 2 July 2012 4 of 18
Integrated Device Technology
ADC0801S040
Single 8 bits ADC, up to 40 MHz
7. Pinning information
7.1 Pinning
ADC0801S
040TS
CLK V
DDO
SLEEP D7
V
DDD
D6
V
SSD
D5
V
DDA
D4
V
SSA
D3
RB D2
RM D1
VI D0
RT V
SSO
014aaa494
1
2
3
4
5
6
7
8
9
10
12
11
14
13
16
15
18
17
20
19
Fig 2. Pin configuration
7.2 Pin description
Table 3. Pin description
Symbol Pin Description
CLK 1clock input
SLEEP 2sleep mode input
VDDD 3digital supply voltage (2.7 V to 5.5 V)
VSSD 4digital ground
VDDA 5analog supply voltage (2.7 V to 5.5 V)
VSSA 6analog ground
RB 7reference voltage BOTTOM input
RM 8reference voltage MIDDLE
VI 9analog input voltage
RT 10 reference voltage TOP input
VSSO 11 output stage ground
D0 12 data output; bit 0 (Least Significant Bit (LSB))
D1 13 data output; bit 1
D2 14 data output; bit 2
D3 15 data output; bit 3
D4 16 data output; bit 4
D5 17 data output; bit 5
3ADC0801S040_3 © IDT 2012. All rights reserved.
Product data sheet Rev. 03 — 2 July 2012 5 of 18
Integrated Device Technology
ADC0801S040
Single 8 bits ADC, up to 40 MHz
8. Limiting values
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter Conditions Min Max Unit
VDDA analog supply voltage [1] 0.3 +7.0 V
VDDD digital supply voltage [1] 0.3 +7.0 V
VDDO output supply voltage [1] 0.3 +7.0 V
VDD supply voltage difference VDDA VDDD;
VDDD VDDO;
VDDA VDDO
0.1 +4.0 V
VIinput voltage referenced to
VSSA
0.3 +7.0 V
Vi(clk)(p-p) peak-to-peak clock input voltage referenced to
VSSD
- VDDD V
IOoutput current -10 mA
Tstg storage temperature 55 +150 C
Tamb ambient temperature 20 +75 C
Tjjunction temperature -150 C
[1] The supply voltages VDDA, VDDD and VDDO may have any value between 0.3 V and +7.0 V provided that
the supply voltage VDD remains as indicated.
9. Thermal characteristics
Table 5. Thermal characteristics
Symbol Parameter Condition Value Unit
Rth(j-a) thermal resistance from junction to
ambient
in free air 120 K/W
10. Characteristics
D6 18 data output; bit 6
D7 19 data output; bit 7 (Most Significant Bit (MSB))
VDDO 20 positive supply voltage for output stage (2.7 V to 5.5 V)
Table 3. Pin description …continued
Symbol Pin Description
Table 6. Characteristics
VDDA = V5 to V6 = 3.3 V; VDDD = V3 to V4 = 3.3 V; VDDO = V20 to V11 = 3.3 V; VSSA, VSSD and VSSO shorted together; Vi(a)(p-p)
= 1.84 V; CL = 20 pF; Tamb = 0
C to 70
C; typical values measured at Tamb = 25
C unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Unit
Supplies
VDDA analog supply voltage 2.7 3.3 5.5 V
VDDD digital supply voltage 2.7 3.3 5.5 V
VDDO output supply voltage 2.5 3.3 5.5
3ADC0801S040_3 © IDT 2012. All rights reserved.
Product data sheet Rev. 03 — 2 July 2012 6 of 18
Integrated Device Technology
ADC0801S040
Single 8 bits ADC, up to 40 MHz
VDD supply voltage difference VDDA VDDD 0.2 -+0.2 V
VDDD VDDO 0.2 -+2.25 V
IDDA analog supply current - 4 6 mA
IDDD digital supply current - 5 8 mA
IDDO output supply current fclk = 40 MHz; ramp input;
CL = 20 pF
- 1 2 mA
Ptot total power dissipation VDDA = VDDD = VDDO = 3.3 V -30 53 mW
Inputs
Clock input CLK (Referenced to VSSD)[1]
VIL LOW-level input voltage 0 - 0.3 VDDD V
VIH HIGH-level input voltage VDDD 3.6 V 0.6 VDDD - VDDD V
VDDD > 3.6 V 0.7 VDDD - VDDD V
IIL LOW-level input current Vclk = 0.3 VDDD 1 0 +1 A
IIH HIGH-level input current Vclk = 0.7 VDDD - - 5 A
Ziinput impedance fclk = 40 MHz - 4 - k
Ciinput capacitance fclk = 40 MHz -3-pF
Input SLEEP (Referenced to VSSD); see Table 8
VIL LOW-level input voltage 0 - 0.3 VDDD V
VIH HIGH-level input voltage VDDD 3.6 V 0.6 VDDD - VDDD V
VDDD > 3.6 V 0.7 VDDD - VDDD V
IIL LOW-level input current VIL = 0.3 VDDD 1 - - A
IIH HIGH-level input current VIH = 0.7 VDDD - - +1 A
Analog input VI (Referenced to VSSA)
IIL LOW-level input current VI = VRB -0-A
IIH HIGH-level input current VI = VRT -9-A
Ziinput impedance fi = 1 MHz -20 - k
Ciinput capacitance fi = 1 MHz -2-pF
Reference voltages for the resistor ladder; see Table 7
VRB voltage on pin RB 1.1 1.2 - V
VRT voltage on pin RT VRT VDDA 2.7 3.3 VDDA V
Vref(dif) differential reference
voltage
VRT VRB 1.5 2.1 2.7 V
Iref reference current -0.95 -mA
Rlad ladder resistance -2.2 - k
TCRlad ladder resistor
temperature coefficient
-4092 - m/K
Voffset offset voltage BOTTOM [2] -170 -mV
TOP [2] -170 -mV
Vi(a)(p-p) peak-to-peak analog
input voltage
[3] 1.4 1.76 2.4 V
Table 6. Characteristics …continued
VDDA = V5 to V6 = 3.3 V; VDDD = V3 to V4 = 3.3 V; VDDO = V20 to V11 = 3.3 V; VSSA, VSSD and VSSO shorted together; Vi(a)(p-p)
= 1.84 V; CL = 20 pF; Tamb = 0
C to 70
C; typical values measured at Tamb = 25
C unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Unit
3ADC0801S040_3 © IDT 2012. All rights reserved.
Product data sheet Rev. 03 — 2 July 2012 7 of 18
Integrated Device Technology
ADC0801S040
Single 8 bits ADC, up to 40 MHz
Digital outputs D7 to D0 and IR (Referenced to VSSD)
VOL LOW-level output
voltage
IO = 1 mA 0 - 0.5 V
VOH HIGH-level output
voltage
IO = 1 mA VDDO 0.5 - VDDO V
IOZ OFF-state output current 0.4 V < VO < VDDO 20 -+20 A
Clock input CLK; see Figure 4[1]
fclk(max) maximum clock
frequency
40 - - MHz
tw(clk)H HIGH clock pulse width 9 - - ns
tw(clk)L LOW clock pulse width 9 - - ns
Analog signal processing (fclk = 40 MHz)
Linearity
INL integral non-linearity ramp input; see Figure 6 - 0.5 0.75 LSB
DNL differential non-linearity ramp input; see Figure 7 - 0.25 0.5 LSB
Bandwidth
Bbandwidth full-scale sine wave [4] -10 MHz
75 % full-scale sine wave -13 MHz
50 % full-scale sine wave -20 MHz
small signal at mid scale;
Vi = 10 LSB at code 128
-350 MHz
Input set response; see Figure 8[5]
ts(LH) LOW to HIGH settling
time
full-scale square wave - 3 5 ns
ts(HL) HIGH to LOW settling
time
full-scale square wave - 3 5 ns
Harmonics; see Figure 9[6]
THD total harmonic distortion fi = 4.43 MHz -50 -dB
Signal-to-Noise ratio; see Figure 9[6]
S/N signal-to-noise ratio without harmonics;
fi= 4.43 MHz
-47 -dB
Effective bits; see Figure 9[6]
ENOB effective number of bits fi = 300 MHz -7.8 -bits
fi = 4.43 MHz -7.3 -bits
Differential gain[7]
Gdif differential gain PAL modulated ramp -1.5 - %
Table 6. Characteristics …continued
VDDA = V5 to V6 = 3.3 V; VDDD = V3 to V4 = 3.3 V; VDDO = V20 to V11 = 3.3 V; VSSA, VSSD and VSSO shorted together; Vi(a)(p-p)
= 1.84 V; CL = 20 pF; Tamb = 0
C to 70
C; typical values measured at Tamb = 25
C unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Unit
3ADC0801S040_3 © IDT 2012. All rights reserved.
Product data sheet Rev. 03 — 2 July 2012 8 of 18
Integrated Device Technology
ADC0801S040
Single 8 bits ADC, up to 40 MHz
[1] In addition to a good layout of the digital and analog ground, it is recommended that the rise and fall times of the clock must not be less
than 1 ns.
[2] Analog input voltages producing code 0 up to and including code 255:
a) Voffset BOTTOM is the difference between the analog input which produces data equal to 00 and the reference voltage on pin RB
(VRB) at Tamb = 25 C.
b) Voffset TOP is the difference between the reference voltage on pin RT (VRT) and the analog input which produces data outputs equal
to code 255 at Tamb = 25 C.
[3] To ensure the optimum linearity performance of such a converter architecture the lower and upper extremities of the converter reference
resistor ladder are connected to pins RB and RT via offset resistors ROB and ROT as shown in Figure 3.
a) The current flowing into the resistor ladder is
I
VRT VRB
–
ROB RLROT
++
---------------------------------------
=
and the full-scale input range at the converter, to cover code 0
to 255 is
VIRLIL
RL
ROB RLROT
++
--------------------------------------- VRT VRB
+0.838 VRT VRB
–== =
b) Since RL, ROB and ROT have similar behavior with respect to process and temperature variation, the ratio
RL
ROB RLROT
++
---------------------------------------
will be kept reasonably constant from device to device. Consequently variation of the output codes at a given input voltage depends
mainly on the difference VRT VRB and its variation with temperature and supply voltage. When several ADCs are connected in
parallel and fed with the same reference source, the matching between each of them is optimized.
[4] The analog bandwidth is defined as the maximum input sine wave frequency which can be applied to the device. No glitches greater
than 2 LSB, nor any significant attenuation is observed in the reconstructed signal.
[5] The analog input settling time is the minimum time required for the input signal to be stabilized after a sharp full-scale input (square
wave signal) in order to sample the signal and obtain correct output data.
[6] Effective bits are obtained via a Fast Fourier Transform (FFT) treatment taking 8000 acquisition points per equivalent fundamental
period. The calculation takes into account all harmonics and noise up to half of the clock frequency (Nyquist frequency). Conversion to
signal-to-noise ratio: S/N = ENOB 6.02 + 1.76 dB.
[7] Measurement carried out using video analyzer VM700A, where video analog signal is reconstructed through a DAC.
[8] Output data acquisition: the output data is available after the maximum delay time of td(o).
Differential phase[7]
dif differential phase PAL modulated ramp -0.25 -deg
Timing (fclk = 40 MHz; CL = 20 pF); see Figure 4[8]
td(s) sampling delay time - - 5 ns
th(o) output hold time 5 - -ns
td(o) output delay time VDDO = 4.75 V 812 15 ns
VDDO = 3.15 V 817 20 ns
VDDO = 2.7 V 818 21 ns
3-state output delay times; see Figure 5
tdHZ active HIGH to float
delay time
-14 18 ns
tdZL float to active LOW
delay time
-16 20 ns
tdZH float to active HIGH
delay time
-16 20 ns
tdLZ active LOW to float
delay time
-14 18 ns
Table 6. Characteristics …continued
VDDA = V5 to V6 = 3.3 V; VDDD = V3 to V4 = 3.3 V; VDDO = V20 to V11 = 3.3 V; VSSA, VSSD and VSSO shorted together; Vi(a)(p-p)
= 1.84 V; CL = 20 pF; Tamb = 0
C to 70
C; typical values measured at Tamb = 25
C unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Unit
3ADC0801S040_3 © IDT 2012. All rights reserved.
Product data sheet Rev. 03 — 2 July 2012 9 of 18
Integrated Device Technology
ADC0801S040
Single 8 bits ADC, up to 40 MHz
014aaa504
RT
RB
RM
Rlad
ROT
RL
RL
RL
RL
IL
ROB
code 255
code 0
9
7
6
Fig 3. Explanation of Table 6 Table note 3
11. Additional information relating to Table 6
Table 7. Output coding and input voltage (typical values; referenced to VSSA)
Code Vi(a)(p-p) (V) Binary outputs D7 to D0
Underflow < 1.37 00 0000 00
01.37 00 0000 00
1 - 00 0000 01
-
254 -11 11 11 10
255 3.13 11 11 11 11
Overflow > 3.13 11 11 11 11
Table 8. Mode selection
SLEEP D7 to D0 IDDA + IDDD (typ)
1high impedance 1.2 mA
0active 9 mA
3ADC0801S040_3 © IDT 2012. All rights reserved.
Product data sheet Rev. 03 — 2 July 2012 10 of 18
Integrated Device Technology
ADC0801S040
Single 8 bits ADC, up to 40 MHz
sample N + 1sample N
CLK
014aaa508
sample N + 2
sample N + 1sample N sample N + 2
50 %
VI
DATA
D0 to D7
VDDO
0 V
50 %
DATA
N + 1
DATA
N
DATA
N − 1
DATA
N − 2
td(o)
tw(clk)H
tw(clk)L
td(s) th(o)
Fig 4. Timing diagram
3ADC0801S040_3 © IDT 2012. All rights reserved.
Product data sheet Rev. 03 — 2 July 2012 11 of 18
Integrated Device Technology
ADC0801S040
Single 8 bits ADC, up to 40 MHz
LOW
HIGH
HIGH
LOW
ADC0801S040
VDDD
VDDD
S1
SLEEP
SLEEP
output
data
output
data
10 %
50 %
50 %
90 %
50 %
tdLZ tdZL
tdHZ tdZH
20 pF
3.3 kΩ
S1
TEST
VDDD
tdLZ
VDDD
tdZL
GND
tdZH
tdHZ GND
014aaa496
frequency on pin SLEEP = 100 kHz.
Fig 5. Timing diagram and test conditions of 3-state output delay time
Fig 6. Typical Integral Non-Linearity (INL) performance
3ADC0801S040_3 © IDT 2012. All rights reserved.
Product data sheet Rev. 03 — 2 July 2012 12 of 18
Integrated Device Technology
ADC0801S040
Single 8 bits ADC, up to 40 MHz
Fig 7. Typical Differential Non-Linearity (DNL) performance
014aaa497
code 255
code 0
50 % 50 %
CLK
VI
t
s(LH)
t
s(HL)
50 % 50 %
5 ns 5 ns
2 ns 2 ns
Fig 8. Analog input settling-time diagram
3ADC0801S040_3 © IDT 2012. All rights reserved.
Product data sheet Rev. 03 — 2 July 2012 13 of 18
Integrated Device Technology
ADC0801S040
Single 8 bits ADC, up to 40 MHz
f (MHz)
0 20.015.05.0 10.0
014aaa503
−80
−40
0
A
(dB)
−120
Effective bits: 7.32; THD = 51.08 dB.
Harmonic levels (dB): 2nd = 68.99; 3rd = 51.62; 4th = 66.05; 5th = 63.23; 6th = 72.79.
Fig 9. Typical fast Fourier transform (fclk = 40 MHz; fi = 4.43 MHz)
014aaa498
V
DDO
D7 to D0
V
SSO
V
DDA
VI
V
SSA
014aaa505
Fig 10. CMOS data outputs Fig 11. VI analog input
014aaa499
V
DDO
V
SSO
SLEEP
VDDA
RT
RM
RB
VSSA 014aaa506
RL
RL
RL
RL
Fig 12. SLEEP 3-state input Fig 13. RB, RM and RT inputs
3ADC0801S040_3 © IDT 2012. All rights reserved.
Product data sheet Rev. 03 — 2 July 2012 14 of 18
Integrated Device Technology
ADC0801S040
Single 8 bits ADC, up to 40 MHz
VDDD
CLK 1/2 VDDD
VSSD
014aaa507
Fig 14. CLK input
3ADC0801S040_3 © IDT 2012. All rights reserved.
Product data sheet Rev. 03 — 2 July 2012 15 of 18
Integrated Device Technology
ADC0801S040
Single 8 bits ADC, up to 40 MHz
12. Application information
12.1 Application diagrams
100 nF
100 nF
100 nF
CLK
SLEEP
V
DDD
V
SSD
V
DDA
V
SSA
V
SSA
V
SSA
V
SSA
RB(1)
RM(1)
VI
RT(1)
V
DDO
D7
D6
D5
D4
D3
D2
D1
D0
V
SSO
1
2
3
4
5
6
7
8
9
10 11
12
20
19
18
17
16
15
14
13
ADC0801S040
014aaa500
The analog and digital supplies should be separated and decoupled.
The external voltage reference generator must be built in such a way that a good supply voltage
ripple rejection is achieved with respect to the LSB value. Eventually, the reference ladder voltages
can be derived from a well regulated VDDA supply through a resistor bridge and a decoupling
capacitor.
(1) RB, RM, RT are decoupled to VSSA.
Fig 15. Application diagram
3ADC0801S040_3 © IDT 2012. All rights reserved.
Product data sheet Rev. 03 — 2 July 2012 16 of 18
Integrated Device Technology
ADC0801S040
Single 8 bits ADC, up to 40 MHz
13. Package outline
UNIT A1A2A3bpcD
(1) E(1) (1)
eH
ELL
pQZywv θ
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm 0.15
01.4
1.2 0.32
0.20 0.20
0.13 6.6
6.4 4.5
4.3 0.65 1 0.2
6.6
6.2 0.65
0.45 0.48
0.18 10
0
o
o
0.13 0.1
DIMENSIONS (mm are the original dimensions)
Note
1. Plastic or metal protrusions of 0.20 mm maximum per side are not included.
0.75
0.45
SOT266-1 MO-152 99-12-27
03-02-19
wM
θ
A
A1
A2
bp
D
HE
Lp
Q
detail X
E
Z
e
c
L
vMA
X
(A )
3
A
y
0.25
110
20 11
pin 1 index
0 2.5 5 mm
scale
SSOP20: plastic shrink small outline package; 20 leads; body width 4.4 mm SOT266-1
A
max.
1.5
Fig 16. Package outline SOT266-1 (SSOP20)
3ADC0801S040_3 © IDT 2012. All rights reserved.
Product data sheet Rev. 03 — 2 July 2012 17 of 18
Integrated Device Technology
ADC0801S040
Single 8 bits ADC, up to 40 MHz
14. Revision history
Table 9. Revision history
Document ID Release date Data sheet status Change notice Supersedes
ADC0801S040_3 20120702 Product data sheet -ADC0801S040_2
ADC0801S040_2 20080818 Product data sheet -ADC0801S040_1
Modifications: Corrections made to table notes in Figure
• 1.
Corrections made to Table
• 3.
Corrections made to symbol in Table
• 4.
Corrections made to Table
• 6.
Corrections made to Figure
• 13
ADC0801S040_1 20080612 Product data sheet - -
15. Contact information
For more information or sales office addresses, please visit: http://www.idt.com
3ADC0801S040_3 © IDT 2012. All rights reserved.
Product data sheet Rev. 03 — 2 July 2012 18 of 18
Integrated Device Technology
ADC0801S040
Single 8 bits ADC, up to 40 MHz
16. Contents
1 General description . . . . . . . . . . . . . . . . . . . . . . 1
2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
4 Quick reference data . . . . . . . . . . . . . . . . . . . . . 2
5 Ordering information . . . . . . . . . . . . . . . . . . . . . 2
6 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3
7 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4
7.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
7.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4
8 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5
9 Thermal characteristics . . . . . . . . . . . . . . . . . . 5
10 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 5
11 Additional information relating to Table 6 . . . 9
12 Application information . . . . . . . . . . . . . . . . . 15
12.1 Application diagrams . . . . . . . . . . . . . . . . . . . 15
13 Package outline. . . . . . . . . . . . . . . . . . . . . . . . 16
14 Revision history . . . . . . . . . . . . . . . . . . . . . . . 17
15 Contact information . . . . . . . . . . . . . . . . . . . . 17
16 Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18