Revision 2.4
April 2002
1
A4
A3
A2
A1
A0
CE
DQ0
DQ1
DQ2
DQ3
VCC
GND
DQ4
DQ5
DQ6
DQ7
WE
A17
A16
A15
A14
A13
A5
A6
A7
OE
UB
LB
DQ15
DQ14
DQ13
DQ12
GND
VCC
DQ11
DQ10
DQ9
DQ8
NC
A8
A9
A10
A11
A12
1
2
3
4
5
7
14
16
18
20
22
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38
31
29
27
25
23
6
8
9
10
11
12
36
35
34
33
BS616LV4011EC
BS616LV4011EI
13
15
17
19
21
44
42
41
40
39
37
32
30
28
26
24
R0201-BS616LV4011
Very Low Power/Voltage CMOS SRAM
256K X 16 bit
• Very low operation voltage : 2.4 ~ 5.5V
• Very low power consumption :
Vcc = 3.0V C-grade: 20mA (Max.) operating current
I-grade: 25mA (Max.) operating current
0.25uA (Typ.) CMOS standby current
Vcc = 5.0V C-grade: 45mA (Max.) operating current
I-grade: 50mA (Max.) operating current
1.5uA (Typ.) CMOS standby current
• High speed access time :
-70 70ns (Max.) at Vcc = 3.0V
-10 100ns (Max.) at Vcc = 3.0V
• Automatic power down when chip is deselected
• Three state outputs and TTL compatible
• Fully static operation
• Data retention supply voltage as low as 1.5V
• Easy expansion with CE and OE options
• I/O Configuration x8/x16 selectable by LB and UB pin
The BS616LV4011 is a high performance, very low power CMOS Static
Random Access Memory organized as 262,144 words by 16 bits and
operates from a wide range of 2.4V to 5.5V supply voltage.
Advanced CMOS technology and circuit techniques provide both high
speed and low power features with a typical CMOS standby current
of 0.25uA and maximum access time of 70/100ns in 3V operation.
Easy memory expansion is provided by active LOW chip
enable(CE), active LOW output enable(OE) and three-state output
drivers.
The BS616LV4011 has an automatic power down feature, reducing the
power consumption significantly when chip is deselected.
The BS616LV4011 is available in DICE form, JEDEC standard 44-pin
TSOP Type II package and 48-pin BGA package.
DESCRIPTION
FEATURES
Row
Decoder
Memory Array
2048 x 2048
Column I/O
Write Driver
Sense Amp
Column Decoder
Data
Buffer
Output
A9 A8 A7
Data
Input
Buffer
Control
Gnd
Vcc
OE
DQ0
A15
A1
16
16
16
16
WE
CE
DQ15
A0
A13
A14
A2
14
128
2048
BLOCK DIAGRAM
2048
22
A17
A16
A10
A12
A6
A11
A3
Address
Input
Buffer
A5
Address Input Buffer
.
.
.
.
UB
.
.
.
.
LB
PRODUCT FAMILY
PIN CONFIGURATIONS
Brilliance Semiconductor Inc.reserves the right to modify document contents without notice.
BS616LV4011
A4
BSI
POWER DISSIPATION
SPEED
( ns ) STANDBY
( ICCSB1, Max ) Operating
( ICC, Max )
PRODUCT
FAMILY
OPERATING
TEMPERATURE
Vcc
RANGE Vcc=
3.0V Vcc=
3.0V Vcc=
5.0V Vcc=
3.0V Vcc=
5.0V
PKG TYPE
BS616LV4011DC DICE
BS616LV4011EC TSOP2-44
BS616LV4011BC BGA-48-0810
BS616LV4011AC
+0 OC to +70 OC 2.4V ~ 5.5V 70/100 45mA
BGA-48-0608
1.5uA 15uA 20mA
BS616LV4011DI DICE
BS616LV4011EI TSOP2-44
BS616LV4011BI BGA-48-0810
BS616LV4011AI
-40 OC to +85 OC 2.4V ~ 5.5V 70/100 50mA3uA 50uA 25mA
BGA-48-0608
Revision 2.4
April 2002
2
R0201-BS616LV4011
Name Function
A0-A17 Address Input These 18 address inputs select one of the 262,144 x 16-bit words in the RAM.
CE Chip Enable Input CE is active LOW. Chip enables must be active to read from or write to the device. if
chip enable is not active, the device is deselected and is in a standby power mode.
The DQ pins will be in the high impedance state when the device is deselected.
WE Write Enable Input The write enable input is active LOW and controls read and write operations. With the
chip selected, when WE is HIGH and OE is LOW, output data will be present on the
DQ pins; when WE is LOW, the data present on the DQ pins will be written into the
selected memory location.
OE Output Enable Input The output enable input is active LOW. If the output enable is active while the chip is
selected and the write enable is inactive, data will be present on the DQ pins and they
will be enabled. The DQ pins will be in the high impedance state when OE is inactive.
LB and UB Data Byte Control Input Lower byte and upper byte data input/output control pins.
DQ0 - DQ15 Data Input/Output These 16 bi-directional ports are used to read data from or write data into the RAM.
Ports
Vcc Power Supply
Gnd Ground
TRUTH TABLE
PIN DESCRIPTIONS
BSI BS616LV4011
MODE CE WE OE LB UB DQ0~DQ7 DQ8~DQ15 Vcc CURRENT
Not selected
(Power Down) H X X X X High Z High Z ICCSB, ICCSB1
Output Disabled L H H X X High Z High Z ICC
L L Dout Dout ICC
H L High Z Dout ICC
Read L H L
L H Dout High Z ICC
L L Din Din ICC
H L X Din ICC
Write L L X
L H Din X ICC
Revision 2.4
April 2002
3
PARAMETER
NAME PARAMETER TEST CONDITIONS MIN. TYP. (1) MAX. UNITS
Vcc=3.0V
VIL Guaranteed Input Low
Voltage(2) Vcc=5.0V -0.5 -- 0.8 V
Vcc=3.0V 2.0
VIH Guaranteed Input High
Voltage(2) Vcc=5.0V 2.2 -- Vcc+0.
2V
IIL Input Leakage Current Vcc = Max, VIN = 0V to Vcc -- -- 1uA
IOL Output Leakage Current Vcc = Max, CE = V
V = 0V to Vcc
IH ,or OE = V
IH ,
I/O -- -- 1uA
Vcc=3.0V
VOL Output Low Voltage Vcc = Max, IOL = 2mA V
Vcc=5.0V -- -- 0.4
Vcc=3.0V
VOH Output High Voltage Vcc = Min, IOH = -1mA V
Vcc=5.0V 2.4 -- --
Vcc=3.0V -- -- 20
ICC Operating Power Supply
Current CE = VIL ,IDQ = 0mA,F = Fmax(3)
Vcc=5.0V -- -- 45 mA
Vcc=3.0V -- -- 1
ICCSB Standby Current -TTL IH ,I DQ = 0mACE = V Vcc=5.0V -- -- 2mA
Vcc=3.0V -- 0.25 1.5
ICCSB1 IN ЊVcc - 0.2V or VINЉ0.2V Vcc=5.0V --
Stand Њ
by Current-CMOS CE
V
Vcc -0.2V,
1.5 15 uA
R0201-BS616LV4011
SYMBOL PARAMETER TEST CONDITIONS MIN. TYP. (1) MAX. UNITS
VDR Vcc for Data Retention CE Њ Vcc - 0.2V
VIN Њ Vcc - 0.2V or VIN Љ 0.2V 1.5 -- -- V
ICCDR Data Retention Current CE Њ Vcc - 0.2V
VIN Њ Vcc - 0.2V or VIN Љ 0.2V -- 0.1 1 uA
tCDR
Chip Deselect to Data
Retention Time 0 -- -- ns
tROperation Recovery Time
See Retention Waveform
TRC
(2) -- -- ns
CIN Input
Capacitance VIN=0V 6 pF
CDQ Input/Output
Capacitance VI/O=0V 8 pF
RANGE AMBIENT
TEMPERATURE Vcc
Commercial 0 OC to +70OC2.4V ~ 5.5V
Industrial -40 OC to +85OC 2.4V ~5.5V
1. Typical characteristics are at TA = 25oC.
2. These are absolute values with respect to device ground and all overshoots due to system or tester notice are included.
3. Fmax = 1/tRC .
DATA RETENTION CHARACTERISTICS ( TA = 0 to + 70oC )
1. Vcc = 1.5V, TA= + 25OC
2. tRC = Read Cycle Time
ABSOLUTE MAXIMUM RATINGS(1) OPERATING RANGE
CAPACITANCE (1) (TA = 25oC, f = 1.0 MHz)
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these
or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
reliability.
1. This parameter is guaranteed and not tested.
DC ELECTRICAL CHARACTERISTICS ( TA = 0 to + 70oC )
SYMBOL PARAMETER RATING UNITS
VTERM Terminal Voltage with
Respect to GND
-0.5 to
Vcc+0.5 V
TBIAS Temperature Under Bias -40 to +125 OC
TSTG Storage Temperature -60 to +150 OC
PTPower Dissipation 1.0 W
IOUT DC Output Current mA20
BSI BS616LV4011
SYMBOL PARAMETER CONDITIONS MAX. UNIT
Revision 2.4
April 2002
4
R0201-BS616LV4011
JEDEC
PARAMETER
NAME
PARAMETER
NAME DESCRIPTION BS616LV4011-70
MIN. TYP. MAX.
BS616LV4011-10
MIN. TYP. MAX. UNIT
tAVAX tRC Read Cycle Time 70 -- -- 100 -- -- ns
tAVQV tAA Address Access Time -- -- 70 -- -- 100 ns
tELQV tACS Chip Select Access Time (CE) -- -- 70 -- -- 100 ns
tBA tBA Data Byte Control Access Time (LB,UB) -- -- 35 -- -- 50 ns
tGLQV tOE Output Enable to Output Valid -- -- 35 -- -- 50 ns
tELQX tCLZ Chip Select to Output Low Z (CE) 10 -- -- 15 -- -- ns
tBE tBE Data Byte Control to Output Low Z (LB,UB) 10 -- -- 15 -- -- ns
tGLQX tOLZ Output Enable to Output in Low Z 10 -- -- 15 -- -- ns
tEHQZ tCHZ Chip Deselect to Output in High Z (CE) 0 -- 35 0 -- 40 ns
tBDO tBDO Data Byte Control to Output High Z (LB,UB) 0 -- 35 0 -- 40 ns
tGHQZ tOHZ Output Disable to Output in High Z 0--300--35ns
tAXOX tOH Output Disable to Address Change 10 -- -- 15 -- -- ns
Input Pulse Levels
Input Rise and Fall Times
Input and Output
Timing Reference Level
Vcc/0V
5ns
0.5Vcc
AC ELECTRICAL CHARACTERISTICS ( TA = 0 to + 70oC , Vcc = 3.0V )
READ CYCLE
AC TEST CONDITIONS
AC TEST LOADS AND WAVEFORMS
KEY TO SWITCHING WAVEFORMS
WAVEFORM INPUTS OUTPUTS
MUST BE
STEADY
MAY CHANGE
FROM H TO L
DON T CAR
ANY CHANG
PERMITTED
E: CHANGE :
E STATE
DOES NOT
APPLY
MUST BE
STEADY
WILL BE
CHANGE
FROM H TO L
UNKNOWN
CENTER
LINE IS HIGH
IMPEDANCE
”OFF ”STATE
MAY CHANGE
FROM L TO H
WILL BE
CHANGE
FROM L TO H
,
LOW VCC DATA RETENTION WAVEFORM ( CE Controlled )
CE
Data Retention Mode
Vcc
tCDR
Vcc
tR
VIHVIH
Vcc VDR 1.5V
≥
CE Vcc - 0.2V
≥
BSI BS616LV4011
Ω667
THEVENIN EQUIVALENT
ALL INPUT PULSES
→
10% 90%
←
Vcc
GND
→←5ns
90% 10%
1.73V
OUTPUT
FIGURE 2
3.3V
OUTPUT
INCLUDING
JIG AND
SCOPE
Ω
1269
Ω
1404
5PF
FIGURE 1B
3.3V
OUTPUT
INCLUDING
JIG AND
SCOPE
Ω
1269
Ω
100PF
FIGURE 1A
1404
(1)
1. tBA is 35ns/50ns (@speed=70ns/100ns) with address toggle. ; tBA is 70ns/100ns (@speed=70ns/100ns) without address toggle.
NOTE :
Revision 2.4
April 2002
5
R0201-BS616LV4011
NOTES:
1. WE is high in read Cycle.
2. Device is continuously selected when CE = VIL.
3. Address valid prior to or coincident with CE transition low.
4. OE = VIL .
5. Transition is measured 500mV from steady state with CL= 5pF as shown in Figure 1B.
The parameter is guaranteed but not 100% tested.
±
BSI BS616LV4011
SWITCHING WAVEFORMS (READ CYCLE)
READ CYCLE1 (1,2,4)
tRC
tOH
tAA
DOUT
ADDRESS
tOH
tOH
READ CYCLE3 (1,4)
tRC
tOE
DOUT
LB,UB
CE
OE
ADDRESS
tCLZ
(5) tACS
tCHZ
(1,5)
tOHZ (5)
tOLZ
tAA
READ CYCLE2 (1,3,4)
tCLZ
tCHZ
(5)
DOUT
LB,UB
CE
(5)
tBA
tACS
tBE tBDO
tBDO
tBA
tBE
Revision 2.4
April 2002
6
JEDEC
PARAMETER
NAME
PARAMETER
NAME DESCRIPTION BS616LV4011-70
MIN. TYP. MAX.
BS616LV4011-10
MIN. TYP. MAX. UNIT
tAVAX Write Cycle TimetWC 70 -- -- 100 -- -- ns
tE1LWH tCW Chip Select to End of Write 70 -- -- 100 -- -- ns
tAVWL tAS Address Setup Time 0 -- -- 0 -- -- ns
tAVWH tAW Address Valid to End of Write 70 -- -- 100 -- -- ns
tWLWH tWP Write Pulse Width 35 -- -- 50 -- -- ns
tWHAX tWR1 Write recovery Time (CE,WE) 0 -- -- 0 -- -- ns
tBW tBW Date Byte Control to End of Write (LB,U ) 3B 0 -- -- 40 -- -- ns
tWLQZ tWHZ Write to Output in High Z 0--300--40ns
tDVWH tDW Data to Write Time Overlap 30 -- -- 40 -- -- ns
tWHDX tDH Data Hold from Write Time 0 -- -- 0 -- -- ns
tGHQZ tOHZ Output Disable to Output in High Z 0--300--40ns
tWHOX tOW End of Write to Output Active 5----10---- ns
R0201-BS616LV4011
AC ELECTRICAL CHARACTERISTICS ( TA = 0 to + 70oC , Vcc = 3.0V )
WRITE CYCLE
BSI BS616LV4011
SWITCHING WAVEFORMS (WRITE CYCLE)
tWR
WRITE CYCLE1 (1)
tWC
(3)
tCW
(11)
tBW
(2)
tWP
tAW
tOHZ
(4,10)
tAS
(3)
tDH
tDW
DIN
DOUT
WE
LB,UB
CE
OE
ADDRESS
(5)
1. tBW is 30ns/40ns (@speed=70ns/100ns) with address toggle. ; tBW is 70ns/100ns (@speed=70ns/100ns) without address toggle.
NOTE :
(1)
Revision 2.4
April 2002
7
R0201-BS616LV4011
BSI BS616LV4011
WRITE CYCLE2 (1,6)
tWC
tCW
(11)
(2)
tWP
tAW
tWHZ
(4,10)
tAS
tWR
(3)
tDH
tDW
DIN
DOUT
WE
CE
ADDRESS
(5)
tDH
(7) (8)
(8,9)
tBW
LB,UB
NOTES:
1. WE must be high during address transitions.
2. The internal write time of the memory is defined by the overlap of CE and WE low. All signals
must be active to initiate a write and any one signal can terminate a write by going inactive.
The data input setup and hold timing should be referenced to the second transition edge of
the signal that terminates the write.
3. TWR is measured from the earlier of CE or WE going high at the end of write cycle.
4. During this period, DQ pins are in the output state so that the input signals of opposite phase
to the outputs must not be applied.
5. If the CE low transition occurs simultaneously with the WE low transitions or after the WE
transition, output remain in a high impedance state.
6. OE is continuously low (OE = VIL ).
7. DOUT is the same phase of write data of this write cycle.
8. DOUT is the read data of next address.
9. If CE is low during this period, DQ pins are in the output state. Then the data input signals of
opposite phase to the outputs must not be applied to them.
10. Transition is measured 500mV from steady state with CL= 5pF as shown in Figure 1B.
The parameter is guaranteed but not 100% tested.
11. TCW is measured from the later of CE going low to the end of write.
±
Revision 2.4
April 2002
8
R0201-BS616LV4011
PACKAGE
E: TSOP 2
B: BGA - 48 PIN(8x10mm)
A: BGA - 48 PIN(6x8mm)
D: DICE
ORDERING INFORMATION
BSI
BS616LV4011 X X -- Y Y
GRADE
C: +0oC ~ +70oC
I: -40oC ~ +85oC
SPEED
70: 70ns
10: 100ns
BS616LV4011
PACKAGE DIMENSIONS
TSOP2-44
Revision 2.4
April 2002
9
BS616LV4011
BSI
R0201-BS616LV4011
PACKAGE DIMENSIONS (continued)
48 mini-BGA (8 x 10mm)
E0.1
3: SYMBOL "N" IS THE NUMBER OF SOLDER BALLS.
1: CONTROLLING DIMENSIONS ARE IN MILLIMETERS.
2: PIN#1 DOT MARKING BY LASER OR PAD PRINT.
N ED
NOTES:
48 10.0 8.0
E1D1 e
3.755.25 0.75
SIDE VIEW
D0.1
D1
1.4 Max.
e
E1
0.25 0.05
SOLDER BALL 0.350.05
VIEW A
D1
VIEW A
1.4 Max.
e
E1
1: CONTROLLING DIMENSIONS ARE IN MILLIMETERS.
2: PIN#1 DOT MARKING BY LASER OR PAD PRINT.
3: SYMBOL "N" IS THE NUMBER OF SOLDER BALLS.
BALL PITCH e = 0.75
D
8.0 6.0
EN
48 3.75
E1D1
5.25
NOTES:
48 mini-BGA (6 x 8mm)
Revision 2.4
April 2002
10
BSI
R0201-BS616LV4011
REVISION HISTORY
Revision Description Date Note
2.2 2001 Data Sheet release Apr. 15, 2001
2.3 Modify Standby Current (Typ. and
Max.)
Jun. 29, 2001
2.4 Modify some AC parameters.
Modify 5V ICCSB1_Max(I-grade)
from 25uA to 50uA.
April,11,2002
BS616LV4011
